3 files changed, 102 insertions, 0 deletions
diff --git a/support/regression/ports/tlcs90/spec.mk b/support/regression/ports/tlcs90/spec.mk
new file mode 100644
index 0000000..8d6dbd2
--- /dev/null
+++ b/support/regression/ports/tlcs90/spec.mk
@@ -0,0 +1,73 @@
+# Regression test specification for the tlcs90 target running with uCsim
+
+# simulation timeout in seconds
+SIM_TIMEOUT = 40
+
+# path to uCsim
+ifdef SDCC_BIN_PATH
+  UCTLCS90C = $(SDCC_BIN_PATH)/stlcs$(EXEEXT)
+
+  AS_TLCS90C = $(SDCC_BIN_PATH)/sdastlcs90$(EXEEXT)
+else
+  ifdef UCSIM_DIR
+    UCTLCS90A = $(UCSIM_DIR)/tlcs.src/stlcs$(EXEEXT)
+  else
+    UCTLCS90A = $(top_builddir)/sim/ucsim/tlcs.src/stlcs$(EXEEXT)
+    UCTLCS90B = $(top_builddir)/bin/stlcs$(EXEEXT)
+  endif
+
+  EMU = $(WINE) $(shell if [ -f $(UCTLCS90A) ]; then echo $(UCTLCS90A); else echo $(UCTLCS90B); fi)
+
+  AS = $(WINE) $(top_builddir)/bin/sdastlcs90$(EXEEXT)
+
+ifndef CROSSCOMPILING
+  SDCCFLAGS += --nostdinc -I$(top_srcdir)
+  LINKFLAGS += --nostdlib -L$(top_builddir)/device/lib/build/tlcs90
+endif
+endif
+
+ifdef CROSSCOMPILING
+  SDCCFLAGS += -I$(top_srcdir)
+endif
+
+SDCCFLAGS += --debug -mtlcs90 --less-pedantic --out-fmt-ihx
+LINKFLAGS += tlcs90.lib
+
+OBJEXT = .rel
+BINEXT = .ihx
+
+# otherwise `make` deletes testfwk.rel and `make -j` will fail
+.PRECIOUS: $(PORT_CASES_DIR)/%$(OBJEXT)
+
+# Required extras
+EXTRAS = $(PORT_CASES_DIR)/testfwk$(OBJEXT) $(PORT_CASES_DIR)/support$(OBJEXT)
+include $(srcdir)/fwk/lib/spec.mk
+
+# Rule to link into .ihx
+%$(BINEXT): %$(OBJEXT) $(EXTRAS) $(FWKLIB) $(PORT_CASES_DIR)/fwk.lib
+	$(SDCC) $(SDCCFLAGS) $(LINKFLAGS) $(EXTRAS) $(PORT_CASES_DIR)/fwk.lib $< -o $@
+
+%$(OBJEXT): %.asm
+	$(AS) -plosgff $<
+
+%$(OBJEXT): %.c
+	$(SDCC) $(SDCCFLAGS) -c $< -o $@
+
+$(PORT_CASES_DIR)/%$(OBJEXT): $(PORTS_DIR)/$(PORT)/%.c
+	$(SDCC) $(SDCCFLAGS) -c $< -o $@
+
+$(PORT_CASES_DIR)/%$(OBJEXT): $(srcdir)/fwk/lib/%.c
+	$(SDCC) $(SDCCFLAGS) -c $< -o $@
+
+$(PORT_CASES_DIR)/fwk.lib: $(srcdir)/fwk/lib/fwk.lib
+	cat < $(srcdir)/fwk/lib/fwk.lib > $@
+
+# run simulator with SIM_TIMEOUT seconds timeout
+%.out: %$(BINEXT) $(CASES_DIR)/timeout
+	mkdir -p $(dir $@)
+	-$(CASES_DIR)/timeout $(SIM_TIMEOUT) $(EMU) $< < $(PORTS_DIR)/$(PORT)/uCsim.cmd > $@ \
+	  || echo -e --- FAIL: \"timeout, simulation killed\" in $(<:$(BINEXT)=.c)"\n"--- Summary: 1/1/1: timeout >> $@
+	$(PYTHON) $(srcdir)/get_ticks.py < $@ >> $@
+	-grep -n FAIL $@ /dev/null || true
+
+_clean:
diff --git a/support/regression/ports/tlcs90/support.c b/support/regression/ports/tlcs90/support.c
new file mode 100644
index 0000000..6444f15
--- /dev/null
+++ b/support/regression/ports/tlcs90/support.c
@@ -0,0 +1,19 @@
+static unsigned char * volatile sif= (unsigned char *)0xffff;
+
+void
+_putchar(unsigned char c)
+{
+  *sif= 'p';
+  *sif= c;
+}
+
+void
+_initEmu(void)
+{
+}
+
+void
+_exitEmu(void)
+{
+  *sif= 's';
+}
diff --git a/support/regression/ports/tlcs90/uCsim.cmd b/support/regression/ports/tlcs90/uCsim.cmd
new file mode 100644
index 0000000..35dc5be
--- /dev/null
+++ b/support/regression/ports/tlcs90/uCsim.cmd
@@ -0,0 +1,10 @@
+set error non-classified off
+set error unknown_code off
+set error memory off
+set error stack off
+
+set hw simif nas 0xffff
+
+run
+state
+quit