sdcc-3.9.0 fork implementing GNU assembler syntax

This fork aims to provide better support for stm8-binutils

38 files changed, 2260 insertions, 0 deletions

diff --git a/sim/ucsim/stm8.src/test/Makefile b/sim/ucsim/stm8.src/test/Makefile
new file mode 100644
index 0000000..1d0296b
--- /dev/null
+++ b/sim/ucsim/stm8.src/test/Makefile
@@ -0,0 +1,18 @@
+PROJECTS	= s0 s1 s2 s3 t1 t2 t3 t4 xtest \
+		  sl ss lled sled ltim stim sertest \
+		  getbl \
+		  monitor
+
+.PHONY: projects $(PROJECTS)
+
+projects: $(PROJECTS)
+
+$(PROJECTS):
+	$(MAKE) MAIN=$@ -f sdcc.mk
+
+clean:
+	for p in $(PROJECTS); do \
+		$(MAKE) MAIN=$$p -f sdcc.mk clean ;\
+		rm -rf $$p*.hex ;\
+		rm -rf $$p*.cdb ;\
+	done
diff --git a/sim/ucsim/stm8.src/test/conf.cmd b/sim/ucsim/stm8.src/test/conf.cmd
new file mode 100644
index 0000000..f921d23
--- /dev/null
+++ b/sim/ucsim/stm8.src/test/conf.cmd
@@ -0,0 +1,2 @@
+set hw simif rom 0x7fff
+set opt debug 1
diff --git a/sim/ucsim/stm8.src/test/dl_ldisc.sh b/sim/ucsim/stm8.src/test/dl_ldisc.sh
new file mode 100755
index 0000000..c858a5a
--- /dev/null
+++ b/sim/ucsim/stm8.src/test/dl_ldisc.sh
@@ -0,0 +1,3 @@
+#!/bin/bash
+
+stm8flash -c stlink -p stm8l152c6 -w ${1}
diff --git a/sim/ucsim/stm8.src/test/dl_sdic.sh b/sim/ucsim/stm8.src/test/dl_sdic.sh
new file mode 100755
index 0000000..8848a73
--- /dev/null
+++ b/sim/ucsim/stm8.src/test/dl_sdic.sh
@@ -0,0 +1,3 @@
+#!/bin/bash
+
+stm8flash -c stlink -p stm8s105c6 -w ${1}
diff --git a/sim/ucsim/stm8.src/test/flash.c b/sim/ucsim/stm8.src/test/flash.c
new file mode 100644
index 0000000..07a2394
--- /dev/null
+++ b/sim/ucsim/stm8.src/test/flash.c
@@ -0,0 +1,141 @@
+/* */
+
+#include <string.h>
+
+#include "stm8.h"
+
+#include "flash.h"
+
+
+// Lock, unklock
+
+void
+flash_punlock(void)
+{
+  FLASH->pukr= 0x56;
+  FLASH->pukr= 0xae;
+}
+
+void
+flash_dunlock(void)
+{
+  FLASH->pukr= 0xae;
+  FLASH->pukr= 0x56;
+}
+
+void
+flash_plock(void)
+{
+  FLASH->iapsr&= ~0x02;
+}
+
+void
+flash_dlock(void)
+{
+  FLASH->iapsr&= ~0x08;
+}
+
+void
+flash_lock(void)
+{
+  FLASH->iapsr&= ~0x0a;
+}
+
+
+// Set programing mode
+
+void
+flash_byte_mode(void)
+{
+  FLASH->cr2= 0;
+#if (DEVICE & DEV_STM8SAF)
+  FLASH->ncr2= 0xff;
+#endif
+}
+
+void
+flash_word_mode(void)
+{
+  FLASH->cr2= 0x40;
+#if (DEVICE & DEV_STM8SAF)
+  FLASH->ncr2= 0xbf;
+#endif
+}
+
+void
+flash_erase_mode(void)
+{
+  FLASH->cr2= 0x20;
+#if (DEVICE & DEV_STM8SAF)
+  FLASH->ncr2= 0xdf;
+#endif
+}
+
+
+// Check the result
+
+uint8_t
+flash_wait_finish(void)
+{
+  unsigned long int timeout= 0xfffff;
+  //volatile
+  uint8_t r;
+
+  r= FLASH->iapsr;
+  while (((r & 0x05) == 0) &&
+	 (timeout != 0))
+    {
+      timeout--;
+      r= FLASH->iapsr;
+    }
+  if (r & 0x04)
+    return 0;
+  if (r & 0x01)
+    return 1;
+  if (timeout == 0)
+    return 2;
+  return 3;
+}
+
+uint8_t
+flash_erase_fn(volatile uint8_t *addr, volatile uint8_t *iapsr)
+{
+  volatile uint8_t r;
+  unsigned long timeout= 0xfffff;
+  flash_erase_mode();
+  *(addr++)= 0;
+  *(addr++)= 0;
+  *(addr++)= 0;
+  *(addr)= 0;
+  r= *iapsr;
+  while (((r & 0x05) == 0) &&
+	 (timeout != 0))
+    {
+      timeout--;
+      r= *iapsr;
+      GPIOD->odr^= 1;
+    }
+  if (r & 0x04)
+    return 0;
+  if (r & 0x01)
+    return 1;
+  if (timeout == 0)
+    return 2;
+  return 3;
+}
+
+uint8_t flash_op_in_ram[120];
+
+uint8_t
+flash_erase(volatile uint8_t *addr, volatile uint8_t *iapsr)
+{
+  uint8_t r;
+  typedef uint8_t (*ft)(volatile uint8_t *addr, volatile uint8_t *iapsr);
+  ft f= (ft)flash_op_in_ram;
+  memcpy(flash_op_in_ram, &flash_erase_fn, 119);
+  r= (*f)(addr, iapsr);
+  return r;
+}
+
+
+/* End of stm8.src/test/flash.c */
diff --git a/sim/ucsim/stm8.src/test/flash.h b/sim/ucsim/stm8.src/test/flash.h
new file mode 100644
index 0000000..52a7ac6
--- /dev/null
+++ b/sim/ucsim/stm8.src/test/flash.h
@@ -0,0 +1,23 @@
+/* */
+
+#ifndef FLASH_HEADER
+#define FLASH_HEADER
+
+#include <stdbool.h>
+
+extern void flash_punlock(void);
+extern void flash_dunlock(void);
+extern void flash_plock(void);
+extern void flash_dlock(void);
+extern void flash_lock(void);
+
+extern void flash_byte_mode(void);
+extern void flash_word_mode(void);
+extern void flash_erase_mode(void);
+
+extern uint8_t flash_wait_finish(void);
+extern uint8_t flash_erase(volatile uint8_t *addr, volatile uint8_t *iapsr);
+
+#endif
+
+/* End of stm8.src/test/flash.h */
diff --git a/sim/ucsim/stm8.src/test/getbl.c b/sim/ucsim/stm8.src/test/getbl.c
new file mode 100644
index 0000000..4a04423
--- /dev/null
+++ b/sim/ucsim/stm8.src/test/getbl.c
@@ -0,0 +1,63 @@
+// Source code under CC0 1.0
+#include <stdint.h>
+#include <stdio.h>
+
+#include "stm8.h"
+
+#include "serial.h"
+
+volatile unsigned char *sif= (unsigned char *)0x7fff;
+
+void
+print_bl()
+{
+  int a, l;
+  uint8_t *p= (uint8_t *)0x6000;
+  printf("%c\n", 2);
+  printf("$A%04x,\n", 0x6000);
+  for (a= 0, l= 0; a < 0x800; a++)
+    {
+      printf("%02x ", p[a]);
+      l++;
+      if ((l % 16) == 0)
+	{
+	  l= 0;
+	  printf("\n");
+	}
+    }
+  printf("%c\n", 3);
+}
+	 
+void main(void)
+{
+  unsigned long i = 0;
+  
+  CLK->ckdivr = 0x00; // Set the frequency to 16 MHz
+  CLK->pckenr1 = 0xFF; // Enable peripherals
+
+  USART->cr2 = USART_CR2_TEN | USART_CR2_REN; // Allow TX and RX
+  USART->cr3 &= ~(USART_CR3_STOP1 | USART_CR3_STOP2); // 1 stop bit
+  USART->brr2 = 0x03;
+  USART->brr1 = 0x68; // 9600 baud
+
+  USART->cr2|= USART_CR2_RIEN;
+  EI;
+
+  for(;;)
+    {
+      if (serial_received())
+	{
+	  char c= getchar();
+	  if (c == '=')
+	    {
+	      print_bl();
+	    }
+	  else if (c == '*')
+	    {
+	      printf("0x%04x\n", 0x6000);
+	    }
+	  else
+	    printf("%c", c);
+	}
+    }
+}
diff --git a/sim/ucsim/stm8.src/test/getbl.mk b/sim/ucsim/stm8.src/test/getbl.mk
new file mode 100644
index 0000000..8dda245
--- /dev/null
+++ b/sim/ucsim/stm8.src/test/getbl.mk
@@ -0,0 +1,3 @@
+DEVICES		= SDISC LDISC
+
+OTHERS		= serial
diff --git a/sim/ucsim/stm8.src/test/lled.c b/sim/ucsim/stm8.src/test/lled.c
new file mode 100644
index 0000000..dd1cd08
--- /dev/null
+++ b/sim/ucsim/stm8.src/test/lled.c
@@ -0,0 +1,47 @@
+// Source code under CC0 1.0
+#include <stdint.h>
+
+#include "stm8.h"
+
+#define PC GPIOC
+#define PE GPIOE
+
+unsigned int clock(void)
+{
+  unsigned char h, l;
+  h = TIM1->cntrh;
+  l = TIM1->cntrl;
+  return((unsigned int)(h) << 8 | l);
+}
+
+void main(void)
+{
+  CLK->ckdivr = 0x00; // Set the frequency to 16 MHz
+  CLK->pckenr2 |= 0x02; // Enable clock to timer
+
+  // Configure timer
+  // 1000 ticks per second
+  TIM1->pscrh = 0x3e;
+  TIM1->pscrl = 0x80;
+  // Enable timer
+  TIM1->cr1 = TIM_CR1_CEN;
+
+  // Configure pins
+  PE->ddr = 0x80;
+  PE->cr1 = 0x80;
+
+  PC->ddr = 0x80;
+  PC->cr1 = 0x80;
+
+  for(;;)
+    {
+      if (clock() % 1000 <= 500)
+	PE->odr |= 0x80;
+      else
+	PE->odr &= 0x7f;
+      if (clock() % 2000 <= 1000)
+	PC->odr |= 0x80;
+      else
+	PC->odr &= 0x7f;
+    }
+}
diff --git a/sim/ucsim/stm8.src/test/lled.mk b/sim/ucsim/stm8.src/test/lled.mk
new file mode 100644
index 0000000..5d8d31b
--- /dev/null
+++ b/sim/ucsim/stm8.src/test/lled.mk
@@ -0,0 +1 @@
+DEVICES		= LDISC
diff --git a/sim/ucsim/stm8.src/test/ltim.c b/sim/ucsim/stm8.src/test/ltim.c
new file mode 100644
index 0000000..55740d6
--- /dev/null
+++ b/sim/ucsim/stm8.src/test/ltim.c
@@ -0,0 +1,84 @@
+// Source code under CC0 1.0
+#include <stdint.h>
+
+#include "stm8.h"
+
+#define PC GPIOC
+#define PE GPIOE
+
+volatile unsigned long clk= 0;
+
+void tim1_up_isr(void) __interrupt(TIM1_UP_IRQ)
+{
+  TIM1->sr1&= ~TIM_SR1_UIF;
+  clk++;
+  //PE->odr^= 0x80;
+}
+
+unsigned long clock(void)
+{
+  unsigned long c;
+  TIM1->ier&= ~TIM_IER_UIE;
+  c= clk;
+  TIM1->ier|= TIM_IER_UIE;
+  return c;
+}
+
+unsigned long last_tick1= 0;
+
+void tick1(unsigned long c)
+{
+  //unsigned long c= clock();
+  if (c - last_tick1 > 500)
+    {
+      last_tick1= c;
+      PE->odr^= 0x80;
+    }
+}
+
+unsigned long last_tick2= 0;
+
+void tick2(unsigned long c)
+{
+  //unsigned long c= clock();
+  if (c - last_tick2 > 1000)
+    {
+      last_tick2= c;
+      PC->odr^= 0x80;
+    }
+}
+
+void main(void)
+{
+  CLK->ckdivr = 0x00; // Set the frequency to 16 MHz
+  CLK->pckenr2 |= 0x02; // Enable clock to timer
+
+  // Configure timer
+  // 16 MHz clock for timer
+  TIM1->pscrh = 0;//0x3e;
+  TIM1->pscrl = 0;//0x80;
+  // Update event at every 1 ms (16000 count)
+  #define AR 16000
+  TIM1->arrh = AR >> 8;
+  TIM1->arrl = AR & 0xff;
+  // Enable timer
+  TIM1->cr1 = TIM_CR1_CEN;
+
+  // Enable interrupt for timer1 update
+  TIM1->ier|= TIM_IER_UIE;
+  EI;
+  
+  // Configure pins
+  PE->ddr = 0x80;
+  PE->cr1 = 0x80;
+
+  PC->ddr = 0x80;
+  PC->cr1 = 0x80;
+
+  for(;;)
+    {
+      unsigned long c= clock();
+      tick1(c);
+      tick2(c);
+    }
+}
diff --git a/sim/ucsim/stm8.src/test/ltim.mk b/sim/ucsim/stm8.src/test/ltim.mk
new file mode 100644
index 0000000..5d8d31b
--- /dev/null
+++ b/sim/ucsim/stm8.src/test/ltim.mk
@@ -0,0 +1 @@
+DEVICES		= LDISC
diff --git a/sim/ucsim/stm8.src/test/monitor.c b/sim/ucsim/stm8.src/test/monitor.c
new file mode 100644
index 0000000..0e209e2
--- /dev/null
+++ b/sim/ucsim/stm8.src/test/monitor.c
@@ -0,0 +1,282 @@
+// Source code under CC0 1.0
+#include <stdint.h>
+#include <stdio.h>
+#include <string.h>
+#include <stdlib.h>
+#include <ctype.h>
+
+#include "stm8.h"
+
+#include "serial.h"
+#include "flash.h"
+
+#if (DEVICE & DEV_SDISC)
+#define LED_PORT GPIOD
+#define LED_MASK 0x01
+#else
+#define LED_PORT GPIOC
+#define LED_MASK 0x80
+#endif
+
+volatile unsigned char *sif= (unsigned char *)0x7fff;
+
+void
+print_bl()
+{
+  int a, l;
+  uint8_t *p= (uint8_t *)0x6000;
+  printf("%c\n", 2);
+  printf("$A%04x,\n", 0x6000);
+  for (a= 0, l= 0; a < 0x800; a++)
+    {
+      printf("%02x ", p[a]);
+      l++;
+      if ((l % 16) == 0)
+	{
+	  l= 0;
+	  printf("\n");
+	}
+    }
+  printf("%c\n", 3);
+}
+
+void
+dump(unsigned long int start, unsigned long int len)
+{
+  uint8_t *p= (uint8_t *)0;
+  int i= 0;
+  
+  printf("%06lx ", start);
+  while (i<len)
+    {
+      printf("%02x ", p[start+i]);
+      i++;
+      if ((i<len) && ((start+i)%8 == 0))
+	{
+	  printf("\n%06lx ", start+i);
+	}
+    }
+  printf("\n");
+}
+
+#define DELIM " ,"
+
+int
+xtoi(char *s)
+{
+  int r= 0;
+  while (*s)
+    {
+      if (isdigit(*s))
+	r= r*16 + *s-'0';
+      else if ((*s >= 'a') && (*s <= 'f'))
+	r= r*16 + *s-'a'+10;
+      else if ((*s >= 'A') && (*s <= 'F'))
+	r= r*16 + *s-'A'+10;
+      s++;
+    }
+  return r;
+}
+
+unsigned long int
+xtol(char *s)
+{
+  unsigned long int r= 0;
+  while (*s)
+    {
+      if (isdigit(*s))
+	r= r*16 + *s-'0';
+      else if ((*s >= 'a') && (*s <= 'f'))
+	r= r*16 + *s-'a'+10;
+      else if ((*s >= 'A') && (*s <= 'F'))
+	r= r*16 + *s-'A'+10;
+      s++;
+    }
+  return r;
+}
+
+void f1() {}
+void f2() {}
+
+void
+proc_cmd(char *cmd)
+{
+  char *w= strtok(cmd, DELIM);
+  char *s;
+  uint8_t res;
+  uint8_t *rom= (uint8_t *)0;
+  unsigned long addr;
+  
+  if (w)
+    {
+      if (strcmp(w, "bl") == 0)
+	print_bl();
+      else if (strcmp(w, "uid") == 0)
+	{
+#if defined UID
+	  int i;
+	  uint8_t *p= UID;
+	  printf("0x%04x ", p);
+	  for (i= 0; i < 12; i++)
+	    printf("%02x ", p[i]);
+	  printf("\n");
+#else
+	  printf("no uid\n");
+#endif
+	}
+      else if (strstr(w, "dump") == w)
+	{
+	  s= strtok(NULL, DELIM);
+	  if (s)
+	    {
+	      unsigned long int start= xtol(s);
+	      unsigned long int len= 32;
+	      s= strtok(NULL, DELIM);
+	      if (s)
+		len= xtol(s);
+	      dump(start, len);
+	    }
+	}
+      else if (strcmp(w, "fb") == 0)
+	{
+	  addr= 0xa000;
+	  printf("Before:\n");
+	  dump(addr, 1);
+	  f1();
+	  flash_byte_mode();
+	  flash_punlock();
+	  rom[addr]= 0xa5;
+	  res= flash_wait_finish();
+	  f2();
+	  flash_plock();
+	  printf("After (%s,%d):\n", (res==0)?"succ":"fail", res);
+	  dump(addr, 1);
+	}
+      else if (strcmp(w, "fw") == 0)
+	{
+	  LED_PORT->odr|= LED_MASK;
+	  addr= 0xa0a0;
+	  printf("Before:\n");
+	  dump(addr, 4);
+	  f1();
+	  flash_word_mode();
+	  flash_punlock();
+	  rom[addr+0]= 0x12;
+	  rom[addr+1]= 0x34;
+	  rom[addr+2]= 0x56;
+	  rom[addr+3]= 0x78;
+	  res= flash_wait_finish();
+	  f2();
+	  flash_plock();
+	  printf("After (%s,%d):\n", (res==0)?"succ":"fail", res);
+	  dump(addr, 4);
+	  LED_PORT->odr&= ~LED_MASK;
+	}
+      else if (strcmp(w, "fe") == 0)
+	{
+	  LED_PORT->odr|= LED_MASK;
+	  addr= 0xa000;
+	  printf("Before:\n");
+	  dump(addr, 64);
+	  f1();
+	  flash_punlock();
+	  /*
+	  rom[addr+0]= 0;
+	  rom[addr+1]= 0;
+	  rom[addr+2]= 0;
+	  rom[addr+3]= 0;
+	  res= flash_wait_finish();
+	  */
+	  res= flash_erase((uint8_t*)0xa000, &(FLASH->iapsr));	  
+	  f2();
+	  flash_plock();
+	  printf("After (%s,%d):\n", (res==0)?"succ":"fail", res);
+	  dump(addr, 64);
+	  LED_PORT->odr&= ~LED_MASK;
+	}
+      else if (strstr(w, "test") == w)
+	{
+	  printf("%d\n", sizeof(flash_erase));
+	}
+      else
+	printf("Unknown command: \"%s\"\n", w);
+    }
+  else
+    printf("What?\n");
+}
+
+char cmd[100];
+
+void
+proc_input(char c)
+{
+  int l= strlen(cmd);
+
+  printf("%c", c);
+  if ((c == '\n') ||
+      (c == '\r'))
+    {
+      proc_cmd(cmd);
+      cmd[0]= 0;
+    }
+  else
+    {
+      if (l < 99)
+	{
+	  cmd[l++]= c;
+	  cmd[l]= 0;
+	}
+    }
+}
+  
+void main(void)
+{
+  unsigned long i = 0;
+  unsigned int a= 0;
+
+  CLK->ckdivr = 0x00; // Set the frequency to 16 MHz
+  CLK->pckenr1 = 0xFF; // Enable peripherals
+
+  LED_PORT->ddr= LED_MASK;
+  LED_PORT->cr1= LED_MASK;
+  
+  // USART2
+  // TX: PD5, CN4.10
+  // RX: PD6, CN4.11
+  USART->cr2 = USART_CR2_TEN | USART_CR2_REN; // Allow TX and RX
+  USART->cr3 &= ~(USART_CR3_STOP1 | USART_CR3_STOP2); // 1 stop bit
+  // 0 68 3 0x0683=1667 16MHz-> 9600 baud
+  //USART->brr2 = 0x03;
+  //USART->brr1 = 0x68;
+  // 0 08 b 0x008b=139  16MHz-> 115200 baud
+  USART->brr2 = 0x0b;
+  USART->brr1 = 0x08;
+
+  USART->cr2|= USART_CR2_RIEN;
+  EI;
+
+  printf("%d discovery monitor\n", DEVICE);
+  /*{
+      uint8_t *p= (uint8_t *)0x123456;
+      printf("sizeof p=%d\n", sizeof(p));
+      *p= 0;
+      }*/
+  cmd[0]= 0;
+  {/*
+    struct st {
+      volatile uint8_t v;
+    };
+    struct st s;*/
+    uint8_t r= FLASH->iapsr;
+    while (FLASH->iapsr == 0)
+      ;//r= FLASH->iapsr;
+  }
+  for(;;)
+    {
+      if (serial_received())
+	{
+	  char c= getchar();
+	  proc_input(c);
+	}
+    }
+}
diff --git a/sim/ucsim/stm8.src/test/monitor.mk b/sim/ucsim/stm8.src/test/monitor.mk
new file mode 100644
index 0000000..97542a8
--- /dev/null
+++ b/sim/ucsim/stm8.src/test/monitor.mk
@@ -0,0 +1,3 @@
+OTHERS		= serial flash
+
+DEVICES		= SDISC LDISC
diff --git a/sim/ucsim/stm8.src/test/s0.c b/sim/ucsim/stm8.src/test/s0.c
new file mode 100644
index 0000000..d0ee5f0
--- /dev/null
+++ b/sim/ucsim/stm8.src/test/s0.c
@@ -0,0 +1,33 @@
+#include <stdint.h>
+#include <stdio.h>
+
+#define DEVICE DEV_STM8S208
+
+#include "stm8.h"
+
+int putchar(int c)
+{
+  while(!(USART->sr & USART_SR_TXE));
+
+  USART->dr = c;
+  return c;
+}
+
+void main(void)
+{
+  unsigned long i = 0;
+
+  CLK->ckdivr = 0x00; // Set the frequency to 16 MHz
+  CLK->pckenr1 = 0xFF; // Enable peripherals
+
+  USART->cr2 = USART_CR2_TEN; // Allow TX and RX
+  USART->cr3 &= ~(USART_CR3_STOP1 | USART_CR3_STOP2); // 1 stop bit
+  USART->brr2 = 0x03;
+  USART->brr1 = 0x68; // 9600 baud
+  
+  for(;;)
+    {
+      printf("Hello World!\n");
+      for(i = 0; i < 147456; i++); // Sleep
+    }
+}
diff --git a/sim/ucsim/stm8.src/test/s1.c b/sim/ucsim/stm8.src/test/s1.c
new file mode 100644
index 0000000..b48a0fd
--- /dev/null
+++ b/sim/ucsim/stm8.src/test/s1.c
@@ -0,0 +1,29 @@
+#include <stdint.h>
+#include <stdio.h>
+
+#define DEVICE DEV_STM8S208
+
+#include "stm8.h"
+
+int putchar(int c)
+{
+  while(!(USART->sr & USART_SR_TXE));
+  USART->dr = c;
+  return c;
+}
+
+void main(void)
+{
+  unsigned long i = 0;
+
+  CLK->ckdivr = 0x00; // Set the frequency to 16 MHz
+  CLK->pckenr1 = 0xFF; // Enable peripherals
+
+  USART->cr2 = USART_CR2_TEN; // Allow TX and RX
+  USART->cr3 &= ~(USART_CR3_STOP1 | USART_CR3_STOP2); // 1 stop bit
+  USART->brr2 = 0x03;
+  USART->brr1 = 0x68; // 9600 baud
+
+  printf("Hello World!\n");
+  for (;;) ;
+}
diff --git a/sim/ucsim/stm8.src/test/s2.c b/sim/ucsim/stm8.src/test/s2.c
new file mode 100644
index 0000000..f83a877
--- /dev/null
+++ b/sim/ucsim/stm8.src/test/s2.c
@@ -0,0 +1,78 @@
+#include <stdint.h>
+#include <stdio.h>
+#include <ctype.h>
+
+#define DEVICE DEV_STM8S208
+
+#include "stm8.h"
+
+volatile unsigned char *sif= (unsigned char *)0x7fff;
+
+int sifchar(int c)
+{
+  *sif= 'p';
+  *sif= c;
+  return c;
+}
+
+void waitsend()
+{
+  while(!(USART->sr & USART_SR_TXE));
+}
+
+int putchar(int c)
+{
+  while(!(USART->sr & USART_SR_TXE));
+  USART->dr = c;
+  return c;
+}
+
+char received()
+{
+  return USART->sr & USART_SR_RXNE;
+}
+
+char getchar()
+{
+  while (!received())
+    ;
+  return USART->dr;
+}
+
+void prints(char *s)
+{
+  char i= 0;
+  while (s[i])
+    {
+      putchar(s[i]);
+      i++;
+    }
+}
+
+void main(void)
+{
+  unsigned long i = 0;
+
+  CLK->ckdivr = 0x00; // Set the frequency to 16 MHz
+  CLK->pckenr1 = 0xFF; // Enable peripherals
+
+  USART->cr2 = USART_CR2_TEN; // Allow TX only yet
+  USART->cr3 &= ~(USART_CR3_STOP1 | USART_CR3_STOP2); // 1 stop bit
+  USART->brr2 = 0x03;
+  USART->brr1 = 0x68; // 9600 baud
+  
+  printf("Hello World!\n");
+  waitsend();
+  USART->cr2 = USART_CR2_TEN | USART_CR2_REN; // Allow TX and RX
+  for (;;)
+    {
+      if (received())
+	{
+	  char c= getchar();
+	  *sif= 'x';*sif= c;
+	  putchar(toupper(c));
+	  if (c == 'Z')
+	    *sif= 's';
+	}
+    }
+}
diff --git a/sim/ucsim/stm8.src/test/s3.c b/sim/ucsim/stm8.src/test/s3.c
new file mode 100644
index 0000000..9635bf6
--- /dev/null
+++ b/sim/ucsim/stm8.src/test/s3.c
@@ -0,0 +1,98 @@
+#include <stdint.h>
+#include <stdio.h>
+#include <ctype.h>
+
+#define DEVICE DEV_STM8S208
+
+#include "stm8.h"
+
+volatile unsigned char *sif= (unsigned char *)0x7fff;
+
+int sifchar(int c)
+{
+  *sif= 'p';
+  *sif= c;
+  return c;
+}
+
+int putchar(int c)
+{
+  while(!(USART->sr & USART_SR_TXE));
+  USART->dr = c;
+  return c;
+}
+
+volatile uint8_t rx_buf[8];
+volatile uint8_t first_free= 0;
+volatile uint8_t last_used= 0;
+
+void isr_rx(void) __interrupt(USART_RX_IRQ)
+{
+  volatile uint8_t d;
+  *sif='p';*sif='I';
+  if (USART->sr & USART_SR_RXNE)
+    {
+      uint8_t n;
+      d= USART->dr;
+      n= (first_free+1)%8;
+      if (n != last_used)
+	{
+	  rx_buf[first_free]= d;
+	  first_free= n;
+	}
+    }
+}
+
+char received()
+{
+  //return UART2_SR & UART_SR_RXNE;
+  return first_free != last_used;
+}
+
+char getchar()
+{
+  uint8_t o;
+  while (!received())
+    ;
+  o= last_used;
+  last_used= (last_used+1)%8;
+  return rx_buf[o];
+}
+
+void prints(char *s)
+{
+  char i= 0;
+  while (s[i])
+    {
+      putchar(s[i]);
+      i++;
+    }
+}
+
+
+void main(void)
+{
+  unsigned long i = 0;
+
+  CLK->ckdivr = 0x00; // Set the frequency to 16 MHz
+  CLK->pckenr1 = 0xFF; // Enable peripherals
+
+  USART->cr2 = USART_CR2_TEN | USART_CR2_REN; // Allow TX and RX
+  USART->cr3 &= ~(USART_CR3_STOP1 | USART_CR3_STOP2); // 1 stop bit
+  USART->brr2 = 0x03;
+  USART->brr1 = 0x68; // 9600 baud
+
+  USART->cr2|= USART_CR2_RIEN;
+  EI;
+  
+  printf("Hello World!\n");
+  for (;;)
+    {
+      if (received())
+	{
+	  char c= getchar();
+	  *sif= 'x';*sif= c;
+	  putchar(toupper(c));
+	}
+    }
+}
diff --git a/sim/ucsim/stm8.src/test/sdcc.mk b/sim/ucsim/stm8.src/test/sdcc.mk
new file mode 100644
index 0000000..2b54862
--- /dev/null
+++ b/sim/ucsim/stm8.src/test/sdcc.mk
@@ -0,0 +1,67 @@
+VPATH		= ..
+
+vpath		%.mk $(VPATH)
+
+TARGET		= stm8
+
+CC		= sdcc -m$(TARGET) --std-c99
+
+CPPFLAGS	=
+CFLAGS		= --debug
+LDFLAGS		=
+LIBS		=
+
+-include	$(MAIN).mk
+
+DEVICES		?= S208
+
+ALL		= $(MAIN) $(OTHERS)
+
+OBJECTS		= $(MAIN).rel $(OTHERS:=.rel)
+
+CPPFLAGS	= -DDEVICE=DEV_STM8$(DEVICE) -I$(VPATH)
+
+.SUFFIXES: .rel .ihx .hex
+
+.PHONY: $(DEVICES)
+
+all: $(DEVICES)
+
+$(DEVICES):
+	test -d $@ || mkdir $@
+	$(MAKE) -C $@ DEVICE=$@ REAL=yes MAIN=$(MAIN) -I$(VPATH) -f$(VPATH)/sdcc.mk compile copy_result
+
+copy_result: $(VPATH)/$(MAIN)_$(DEVICE).hex $(VPATH)/$(MAIN)_$(DEVICE).cdb
+
+$(VPATH)/$(MAIN)_$(DEVICE).hex: $(MAIN).hex
+	cp $< $@
+
+$(VPATH)/$(MAIN)_$(DEVICE).cdb: $(MAIN).cdb
+	cp $(MAIN).cdb $@
+
+compile: dep $(MAIN).hex
+
+.c.rel:
+	$(CC) $(CPPFLAGS) $(CFLAGS) -o $@ -c $<
+
+.ihx.hex:
+	packihx $< >$@
+
+$(MAIN).ihx: $(OBJECTS)
+	$(CC) $(CFLAGS) $(LDFLAAGS) $(OBJECTS) -o $@
+
+$(MAIN).cdb: $(MAIN).hex
+
+dep: $(MAIN).dep
+
+$(MAIN).dep: $(addprefix ../,$(OBJECTS:.rel=.c)) ../*.h
+	for c in $(addprefix ../,$(OBJECTS:.rel=.c)); do \
+		$(CC) -MM $(CPPFLAGS) $$c >>$@; \
+	done
+
+clean:
+	rm -rf $(DEVICES)
+
+ifeq ($(REAL),yes)
+include $(MAIN).dep
+endif
diff --git a/sim/ucsim/stm8.src/test/serial.c b/sim/ucsim/stm8.src/test/serial.c
new file mode 100644
index 0000000..8d8fddd
--- /dev/null
+++ b/sim/ucsim/stm8.src/test/serial.c
@@ -0,0 +1,114 @@
+#include <stdio.h>
+
+#include "stm8.h"
+
+#include "serial.h"
+
+extern volatile unsigned char *sif;
+
+int
+putchar(int c)
+{
+  while(!(USART->sr & USART_SR_TXE));
+  
+  USART->dr = c;
+  return c;
+}
+
+volatile uint8_t rx_buf[UART_BUF_SIZE];
+volatile uint8_t first_free= 0;
+volatile uint8_t last_used= 0;
+
+unsigned char
+serial_nuof_received()
+{
+  if (first_free == last_used)
+    return 0;
+  else if (first_free > last_used)
+    return first_free - last_used;
+  else
+    return UART_BUF_SIZE - (last_used - first_free);
+}
+
+void isr_rx(void) __interrupt(USART_RX_IRQ)
+{
+  volatile uint8_t d;
+  if (USART->sr & USART_SR_RXNE)
+    {
+      uint8_t n;
+      d= USART->dr;
+      n= (first_free+1)%UART_BUF_SIZE;
+      *sif= 'p';*sif= '|';
+      *sif= 'p';*sif= d;
+      *sif= 'p';*sif= '|';
+      if (n != last_used)
+	{
+	  rx_buf[first_free]= d;
+	  first_free= n;
+	}
+      else
+	{
+	  *sif= 'p';*sif= '*';
+	  *sif= 'p';*sif= d;
+	  *sif= 'p';*sif= '*';
+	}
+      d= serial_nuof_received();
+      *sif= 'p';*sif= '/';
+      *sif= 'p';*sif= d+'0';
+      *sif= 'p';*sif= '/';
+    }
+}
+
+char
+serial_received()
+{
+  //return UART2_SR & UART_SR_RXNE;
+  return first_free != last_used;
+}
+
+char getchar()
+{
+  uint8_t o, nr;
+  while (!serial_received())
+    ;
+  o= last_used;
+  last_used= (last_used+1)%UART_BUF_SIZE;
+  o= rx_buf[o];
+  nr= serial_nuof_received();
+  *sif= 'p';*sif= '@';
+  *sif= 'p';*sif= nr+'0';
+  *sif= 'p';*sif= '@';
+  return o;
+}
+
+void
+print_cx1(char c)
+{
+  if (c > 9)
+    printf("%c", c-10+'A');
+  else
+    printf("%c", c+'0');
+}
+
+void
+print_cx2(char c)
+{
+  int d;
+  d= (c>>4) & 0xf;
+  print_cx1(d);
+  d= c & 0xf;
+  print_cx1(d);
+}
+
+void
+print_ix4(int i)
+{
+  int d= i>>12;
+  print_cx1(d);
+  d= (i>>8) & 0xf;
+  print_cx1(d);
+  d= (i>>4) & 0xf;
+  print_cx1(d);
+  d= i & 0xf;
+  print_cx1(d);
+}
diff --git a/sim/ucsim/stm8.src/test/serial.h b/sim/ucsim/stm8.src/test/serial.h
new file mode 100644
index 0000000..8552c19
--- /dev/null
+++ b/sim/ucsim/stm8.src/test/serial.h
@@ -0,0 +1,16 @@
+#ifndef SERIAL_HEADER
+#define SERIAL_HEADER
+
+#include "stm8.h"
+
+#define UART_BUF_SIZE 8
+
+extern void isr_rx(void) __interrupt(USART_RX_IRQ);
+
+extern char serial_received();
+
+extern void print_cx1(char c);
+extern void print_cx2(char c);
+extern void print_ix4(int i);
+
+#endif
diff --git a/sim/ucsim/stm8.src/test/sertest.c b/sim/ucsim/stm8.src/test/sertest.c
new file mode 100644
index 0000000..1f77cf9
--- /dev/null
+++ b/sim/ucsim/stm8.src/test/sertest.c
@@ -0,0 +1,51 @@
+// Source code under CC0 1.0
+#include <stdint.h>
+#include <stdio.h>
+
+#include "stm8.h"
+
+#include "serial.h"
+
+volatile unsigned char *sif= (unsigned char *)0x7fff;
+
+
+void main(void)
+{
+  unsigned long i = 0;
+  unsigned int a= 0;
+
+  CLK->ckdivr = 0x00; // Set the frequency to 16 MHz
+  CLK->pckenr1 = 0xFF; // Enable peripherals
+
+  // USART2
+  // TX: PD5, CN4.10
+  // RX: PD6, CN4.11
+  USART->cr2 = USART_CR2_TEN | USART_CR2_REN; // Allow TX and RX
+  USART->cr3 &= ~(USART_CR3_STOP1 | USART_CR3_STOP2); // 1 stop bit
+  USART->brr2 = 0x03;
+  USART->brr1 = 0x68; // 9600 baud
+
+  USART->cr2|= USART_CR2_RIEN;
+  EI;
+
+  for(;;)
+    {
+      i++;
+      if (serial_received())
+	{
+	  char c= getchar();
+	  if (c == '*')
+	    {
+	      printf("0x%04x\n", a);
+	    }
+	  printf("%c", c);
+	  i= 0;
+	}
+      if (i > 147456*2)
+	{
+	  printf("tick %u 0x%04x Hello World!\n", a, a);
+	  i= 0;
+	  a++;
+	}
+    }
+}
diff --git a/sim/ucsim/stm8.src/test/sertest.mk b/sim/ucsim/stm8.src/test/sertest.mk
new file mode 100644
index 0000000..dfc8f06
--- /dev/null
+++ b/sim/ucsim/stm8.src/test/sertest.mk
@@ -0,0 +1,3 @@
+DEVICES		= LDISC SDISC
+
+OTHERS		= serial
diff --git a/sim/ucsim/stm8.src/test/sl.c b/sim/ucsim/stm8.src/test/sl.c
new file mode 100644
index 0000000..0132275
--- /dev/null
+++ b/sim/ucsim/stm8.src/test/sl.c
@@ -0,0 +1,59 @@
+// Source code under CC0 1.0
+#include <stdint.h>
+#include <stdio.h>
+
+#define PC_DDR	(*(volatile uint8_t *)0x500c)
+#define PC_CR1	(*(volatile uint8_t *)0x500d)
+
+#define CLK_DIVR	(*(volatile uint8_t *)0x50c0)
+#define CLK_PCKENR1	(*(volatile uint8_t *)0x50c3)
+
+#define USART1_SR	(*(volatile uint8_t *)0x5230)
+#define USART1_DR	(*(volatile uint8_t *)0x5231)
+#define USART1_BRR1	(*(volatile uint8_t *)0x5232)
+#define USART1_BRR2	(*(volatile uint8_t *)0x5233)
+#define USART1_CR2	(*(volatile uint8_t *)0x5235)
+#define USART1_CR3	(*(volatile uint8_t *)0x5236)
+
+#define USART_CR2_TEN (1 << 3)
+#define USART_CR3_STOP2 (1 << 5)
+#define USART_CR3_STOP1 (1 << 4)
+#define USART_SR_TXE (1 << 7)
+
+int putchar(int c)
+{
+  while(!(USART1_SR & USART_SR_TXE));
+
+  USART1_DR = c;
+  return c;
+}
+
+char dbuf[10];
+char xbuf[10];
+
+void main(void)
+{
+  unsigned long i = 0;
+  int a= 0;
+	
+  CLK_DIVR = 0x00; // Set the frequency to 16 MHz
+  CLK_PCKENR1 = 0xFF; // Enable peripherals
+
+  PC_DDR = 0x08; // Put TX line on
+  PC_CR1 = 0x08;
+
+  USART1_CR2 = USART_CR2_TEN; // Allow TX and RX
+  USART1_CR3 &= ~(USART_CR3_STOP1 | USART_CR3_STOP2); // 1 stop bit
+  USART1_BRR2 = 0x03; USART1_BRR1 = 0x68; // 9600 baud
+
+  sprintf(dbuf, "%d", 1234);
+  printf("%s\n", dbuf);
+  sprintf(xbuf, "%x", 0x1234);
+  printf("%s\n", xbuf);
+  for(;;)
+    {
+      printf("Hello World %d %x!\n", a, a);
+      for(i = 0; i < 147456; i++); // Sleep
+      a++;
+    }
+}
diff --git a/sim/ucsim/stm8.src/test/sl.mk b/sim/ucsim/stm8.src/test/sl.mk
new file mode 100644
index 0000000..5d8d31b
--- /dev/null
+++ b/sim/ucsim/stm8.src/test/sl.mk
@@ -0,0 +1 @@
+DEVICES		= LDISC
diff --git a/sim/ucsim/stm8.src/test/sled.c b/sim/ucsim/stm8.src/test/sled.c
new file mode 100644
index 0000000..f3ffe09
--- /dev/null
+++ b/sim/ucsim/stm8.src/test/sled.c
@@ -0,0 +1,44 @@
+// Source code under CC0 1.0
+#include <stdint.h>
+
+#include "stm8.h"
+
+#define PD GPIOD
+
+unsigned int clock(void)
+{
+  unsigned char h = TIM1->cntrh;
+  unsigned char l = TIM1->cntrl;
+  return((unsigned int)(h) << 8 | l);
+}
+
+unsigned int last= 0;
+
+void main(void)
+{
+  unsigned int now;
+  CLK->ckdivr = 0x00; // Set the frequency to 16 MHz
+
+  // Configure timer
+  // 1000 ticks per second
+  TIM1->pscrh = 0x3e;
+  TIM1->pscrl = 0x80;
+  // Enable timer
+  TIM1->cr1 = 0x01;
+  
+  PD->ddr = 0x01;
+  PD->cr1 = 0x01;
+
+  for(;;)
+    {
+      now= clock();
+      if (now - last > 500)
+	{
+	  if (PD->odr & 1)
+	    PD->odr&= ~1;
+	  else
+	    PD->odr|= 1;
+	  last= now;
+	}
+    }
+}
diff --git a/sim/ucsim/stm8.src/test/sled.mk b/sim/ucsim/stm8.src/test/sled.mk
new file mode 100644
index 0000000..cd27c9e
--- /dev/null
+++ b/sim/ucsim/stm8.src/test/sled.mk
@@ -0,0 +1 @@
+DEVICES		= SDISC
diff --git a/sim/ucsim/stm8.src/test/ss.c b/sim/ucsim/stm8.src/test/ss.c
new file mode 100644
index 0000000..253b55b
--- /dev/null
+++ b/sim/ucsim/stm8.src/test/ss.c
@@ -0,0 +1,46 @@
+// Source code under CC0 1.0
+#include <stdint.h>
+#include <stdio.h>
+
+#define CLK_DIVR	(*(volatile uint8_t *)0x50c6)
+#define CLK_PCKENR1	(*(volatile uint8_t *)0x50c7)
+
+#define UART2_SR	(*(volatile uint8_t *)0x5240)
+#define UART2_DR	(*(volatile uint8_t *)0x5241)
+#define UART2_BRR1	(*(volatile uint8_t *)0x5242)
+#define UART2_BRR2	(*(volatile uint8_t *)0x5243)
+#define UART2_CR2	(*(volatile uint8_t *)0x5245)
+#define UART2_CR3	(*(volatile uint8_t *)0x5246)
+
+#define UART_CR2_TEN (1 << 3)
+#define UART_CR3_STOP2 (1 << 5)
+#define UART_CR3_STOP1 (1 << 4)
+#define UART_SR_TXE (1 << 7)
+
+int putchar(int c)
+{
+  while(!(UART2_SR & UART_SR_TXE));
+  
+  UART2_DR = c;
+  return c;
+}
+
+void main(void)
+{
+  unsigned long i = 0;
+  int a= 0;
+  
+  CLK_DIVR = 0x00; // Set the frequency to 16 MHz
+  CLK_PCKENR1 = 0xFF; // Enable peripherals
+
+  UART2_CR2 = UART_CR2_TEN; // Allow TX and RX
+  UART2_CR3 &= ~(UART_CR3_STOP1 | UART_CR3_STOP2); // 1 stop bit
+  UART2_BRR2 = 0x03; UART2_BRR1 = 0x68; // 9600 baud
+
+  for(;;)
+    {
+      printf("Hello World %d %x!\n", a, a);
+      for(i = 0; i < 147456; i++); // Sleep
+      a++;
+    }
+}
diff --git a/sim/ucsim/stm8.src/test/ss.mk b/sim/ucsim/stm8.src/test/ss.mk
new file mode 100644
index 0000000..cd27c9e
--- /dev/null
+++ b/sim/ucsim/stm8.src/test/ss.mk
@@ -0,0 +1 @@
+DEVICES		= SDISC
diff --git a/sim/ucsim/stm8.src/test/stim.c b/sim/ucsim/stm8.src/test/stim.c
new file mode 100644
index 0000000..2851b9b
--- /dev/null
+++ b/sim/ucsim/stm8.src/test/stim.c
@@ -0,0 +1,66 @@
+// Source code under CC0 1.0
+#include <stdint.h>
+
+#include "stm8.h"
+
+#define PD GPIOD
+
+volatile unsigned long clk= 0;
+
+void tim1_up_isr(void) __interrupt(TIM1_UP_IRQ)
+{
+  TIM1->sr1&= ~TIM_SR1_UIF;
+  clk++;
+  //PE->odr^= 0x80;
+}
+
+unsigned int clock(void)
+{
+  unsigned long c;
+  TIM1->ier&= ~TIM_IER_UIE;
+  c= clk;
+  TIM1->ier|= TIM_IER_UIE;
+  return c;
+}
+
+unsigned long last_tick1= 0;
+
+void tick1(unsigned long c)
+{
+  //unsigned long c= clock();
+  if (c - last_tick1 > 500)
+    {
+      last_tick1= c;
+      PD->odr^= 1;
+    }
+}
+
+void main(void)
+{
+  CLK->ckdivr = 0x00; // Set the frequency to 16 MHz
+
+  // Configure timer
+  // 1000 ticks per second
+  TIM1->pscrh = 0; //0x3e;
+  TIM1->pscrl = 0; //0x80;
+  // Update event at every 1 ms (16000 count)
+  #define AR 16000
+  TIM1->arrh = AR >> 8;
+  TIM1->arrl = AR & 0xff;
+  // Enable timer
+  TIM1->cr1 = 0x01;
+  
+  // Enable interrupt for timer1 update
+  TIM1->ier|= TIM_IER_UIE;
+  EI;
+
+  // Configure pin
+  PD->ddr = 0x01;
+  PD->cr1 = 0x01;
+
+  for(;;)
+    {
+      unsigned long c= clock();
+      tick1(c);
+    }
+}
diff --git a/sim/ucsim/stm8.src/test/stim.mk b/sim/ucsim/stm8.src/test/stim.mk
new file mode 100644
index 0000000..cd27c9e
--- /dev/null
+++ b/sim/ucsim/stm8.src/test/stim.mk
@@ -0,0 +1 @@
+DEVICES		= SDISC
diff --git a/sim/ucsim/stm8.src/test/stm8.h b/sim/ucsim/stm8.src/test/stm8.h
new file mode 100644
index 0000000..c9ff61a
--- /dev/null
+++ b/sim/ucsim/stm8.src/test/stm8.h
@@ -0,0 +1,798 @@
+#ifndef STM8_HEADER
+#define STM8_HEADER
+
+#include "stdint.h"
+
+/* DEVICES 
+ */
+
+#define DEV_STM8S903	0x00000001
+#define DEV_STM8S003	0x00000002
+#define DEV_STM8S005	0x00000004
+#define DEV_STM8S007	0x00000008
+#define DEV_STM8S103	0x00000010
+#define DEV_STM8S105	0x00000020
+#define DEV_STM8S207	0x00000040
+#define DEV_STM8S208	0x00000080
+#define DEV_STM8S	(DEV_STM8S903|\
+			 DEV_STM8S003|\
+			 DEV_STM8S005|\
+			 DEV_STM8S007|\
+			 DEV_STM8S103|\
+			 DEV_STM8S105|\
+			 DEV_STM8S207|\
+			 DEV_STM8S208)
+
+#define DEV_STM8AF52	0x00000100
+#define DEV_STM8AF62_12	0x00000200
+#define DEV_STM8AF62_46	0x00000400
+#define DEV_STM8AF	(DEV_STM8AF52|\
+			 DEV_STM8AF62_12|\
+			 DEV_STM8AF62_46)
+
+#define DEV_STM8SAF	(DEV_STM8S|DEV_STM8AF)
+
+#define DEV_STM8AL3xE	0x00010000
+#define DEV_STM8AL3x8	0x00020000
+#define DEV_STM8AL3x346	0x00040000
+#define DEV_STM8AL	(DEV_STM8AL3xE|\
+			 DEV_STM8AL3x8|\
+			 DEV_STM8AL3x346)
+
+#define DEV_STM8L051	0x01000000
+#define DEV_STM8L052C	0x02000000
+#define DEV_STM8L052R	0x04000000
+#define DEV_STM8L151x23	0x08000000
+#define DEV_STM8L15x46	0x10000000
+#define DEV_STM8L15x8	0x20000000
+#define DEV_STM8L162	0x40000000
+
+#define DEV_STM8L	(DEV_STM8L051|\
+			 DEV_STM8L052C|\
+			 DEV_STM8L052R|\
+			 DEV_STM8L151x23|\
+			 DEV_STM8L15x46|\
+			 DEV_STM8L15x8|\
+			 DEV_STM8L162)
+
+#define DEV_STM8ALL	(DEV_STM8AL|DEV_STM8L)
+
+#define DEV_STM8L101	0x00001000
+
+#define DEV_STM8LDISC	DEV_STM8L15x46
+#define DEV_LDISC	DEV_STM8L15x46
+#define DEV_STM8SDISC	DEV_STM8S105
+#define DEV_SDISC	DEV_STM8S105
+
+#ifndef DEVICE
+#define DEVICE DEV_STM8S208
+#endif
+
+//#define CLK_DIVR	(*(volatile uint8_t *)0x50c6)
+//#define CLK_PCKENR1	(*(volatile uint8_t *)0x50c7)
+
+
+//#define UART2_SR	(*(volatile uint8_t *)0x5240)
+//#define UART2_DR	(*(volatile uint8_t *)0x5241)
+//#define UART2_BRR1	(*(volatile uint8_t *)0x5242)
+//#define UART2_BRR2	(*(volatile uint8_t *)0x5243)
+//#define UART2_CR2	(*(volatile uint8_t *)0x5245)
+//#define UART2_CR3	(*(volatile uint8_t *)0x5246)
+
+//#define UART_CR2_TEN (1 << 3)
+//#define UART_CR2_REN (1 << 2)
+//#define UART_CR2_RIEN (1 << 5)
+//#define UART_CR3_STOP2 (1 << 5)
+//#define UART_CR3_STOP1 (1 << 4)
+//#define UART_SR_TXE (1 << 7)
+//#define UART_SR_RXNE (1 << 5)
+
+
+/* GPIO
+ */
+
+struct GPIO_t {
+  volatile uint8_t odr;
+  volatile uint8_t idr;
+  volatile uint8_t ddr;
+  volatile uint8_t cr1;
+  volatile uint8_t cr2;
+};
+
+#define GPIOA ((struct GPIO_t *)0x5000)
+#define GPIOB ((struct GPIO_t *)0x5005)
+#define GPIOC ((struct GPIO_t *)0x500A)
+#define GPIOD ((struct GPIO_t *)0x500F)
+#if (DEVICE & DEV_STM8SAF) || \
+  (DEVICE & DEV_STM8AL) || \
+  (DEVICE & DEV_STM8L052C) || \
+  (DEVICE & DEV_STM8L052R) || \
+  (DEVICE & DEV_STM8L151x23) || \
+  (DEVICE & DEV_STM8L15x46) || \
+  (DEVICE & DEV_STM8L15x8) || \
+  (DEVICE & DEV_STM8L162)
+#define GPIOE ((struct GPIO_t *)0x5014)
+#define GPIOF ((struct GPIO_t *)0x5019)
+#endif
+#if (DEVICE & DEV_STM8S005) || \
+  (DEVICE & DEV_STM8S007) || \
+  (DEVICE & DEV_STM8S105) || \
+  (DEVICE & DEV_STM8S207) || \
+  (DEVICE & DEV_STM8S208) || \
+  (DEVICE & DEV_STM8AF52) || \
+  (DEVICE & DEV_STM8AF62_46) || \
+  (DEVICE & DEV_STM8AL3xE) || \
+  (DEVICE & DEV_STM8AL3x8) || \
+  (DEVICE & DEV_STM8L052R) || \
+  (DEVICE & DEV_STM8L15x8) || \
+  (DEVICE & DEV_STM8L162)
+#define GPIOG ((struct GPIO_t *)0x501E)
+#endif
+#if (DEVICE & DEV_STM8S005) || \
+  (DEVICE & DEV_STM8S007) || \
+  (DEVICE & DEV_STM8S105) || \
+  (DEVICE & DEV_STM8S207) || \
+  (DEVICE & DEV_STM8S208) || \
+  (DEVICE & DEV_STM8AF52) || \
+  (DEVICE & DEV_STM8AL3xE) || \
+  (DEVICE & DEV_STM8AL3x8) || \
+  (DEVICE & DEV_STM8L15x8) || \
+  (DEVICE & DEV_STM8L162)
+#define  GPIOH ((struct GPIO_t *)0x5023)
+#define  GPIOI ((struct GPIO_t *)0x5028)
+#endif
+
+
+/* Timers
+ */
+
+/* bits of control 1 register */
+#define TIM_CR1_CEN	(1 << 0)
+
+/* Bits of interrupt enable register */
+#define TIM_IER_UIE	(1 << 0)
+
+/* Bits of interrupt flag register */
+#define TIM_SR1_UIF	(1 << 0)
+
+/* Bits of event generator register */
+#define TIM_EGR_UG	(1 << 0)
+
+/* TIM1
+ */
+
+#if (DEVICE & DEV_STM8SAF)
+struct TIM1_t {
+  volatile uint8_t cr1;		//=  0;
+  volatile uint8_t cr2;		//=  1;
+  volatile uint8_t smcr;	//=  2;
+  volatile uint8_t etr;		//=  3;
+  volatile uint8_t ier;		//=  4;
+  volatile uint8_t sr1;		//=  5;
+  volatile uint8_t sr2;		//=  6;
+  volatile uint8_t egr;		//=  7;
+  volatile uint8_t ccmr1;	//=  8;
+  volatile uint8_t ccmr2;	//=  9;
+  volatile uint8_t ccmr3;	//= 10;
+  volatile uint8_t ccmr4;	//= 11;
+  volatile uint8_t ccer1;	//= 12;
+  volatile uint8_t ccer2;	//= 13;
+  volatile uint8_t cntrh;	//= 14;
+  volatile uint8_t cntrl;	//= 15;
+  volatile uint8_t pscrh;	//= 16;
+  volatile uint8_t pscrl;	//= 17;
+  volatile uint8_t arrh;	//= 18;
+  volatile uint8_t arrl;	//= 19;
+  volatile uint8_t rcr;		//= 20;
+  volatile uint8_t ccr1h;	//= 21;
+  volatile uint8_t ccr1l;	//= 22;
+  volatile uint8_t ccr2h;	//= 23;
+  volatile uint8_t ccr2l;	//= 24;
+  volatile uint8_t ccr3h;	//= 25;
+  volatile uint8_t ccr3l;	//= 26;
+  volatile uint8_t ccr4h;	//= 27;
+  volatile uint8_t ccr4l;	//= 28;
+  volatile uint8_t bkr;		//= 29;
+  volatile uint8_t dtr;		//= 30;
+  volatile uint8_t oisr;	//= 31;
+};
+#define TIM1_UP_IRQ	11
+#define TIM1_CC_IRQ	12
+#elif (DEVICE & DEV_STM8ALL)
+struct TIM1_t {
+  volatile uint8_t cr1;		//=  0;
+  volatile uint8_t cr2;		//=  1;
+  volatile uint8_t smcr;	//=  2;
+  volatile uint8_t etr;		//=  3;
+  volatile uint8_t der;         //=  4;
+  volatile uint8_t ier;		//=  5;
+  volatile uint8_t sr1;		//=  6;
+  volatile uint8_t sr2;		//=  7;
+  volatile uint8_t egr;		//=  8;
+  volatile uint8_t ccmr1;	//=  9;
+  volatile uint8_t ccmr2;	//= 10;
+  volatile uint8_t ccmr3;	//= 11;
+  volatile uint8_t ccmr4;	//= 12;
+  volatile uint8_t ccer1;	//= 13;
+  volatile uint8_t ccer2;	//= 14;
+  volatile uint8_t cntrh;	//= 15;
+  volatile uint8_t cntrl;	//= 16;
+  volatile uint8_t pscrh;	//= 17;
+  volatile uint8_t pscrl;	//= 18;
+  volatile uint8_t arrh;	//= 19;
+  volatile uint8_t arrl;	//= 20;
+  volatile uint8_t rcr;		//= 21;
+  volatile uint8_t ccr1h;	//= 22;
+  volatile uint8_t ccr1l;	//= 23;
+  volatile uint8_t ccr2h;	//= 24;
+  volatile uint8_t ccr2l;	//= 25;
+  volatile uint8_t ccr3h;	//= 26;
+  volatile uint8_t ccr3l;	//= 27;
+  volatile uint8_t ccr4h;	//= 28;
+  volatile uint8_t ccr4l;	//= 29;
+  volatile uint8_t bkr;		//= 30;
+  volatile uint8_t dtr;		//= 31;
+  volatile uint8_t oisr;	//= 32;
+};
+#define TIM1_UP_IRQ	23
+#define TIM1_CC_IRQ	24
+#endif
+
+#if (DEVICE & DEV_STM8S) || (DEVICE & DEV_STM8AF)
+#define TIM1 ((struct TIM1_t *)0x5250)
+#endif
+#if (DEVICE & DEV_STM8AL) || \
+  (DEVICE & DEV_STM8L052C) || \
+  (DEVICE & DEV_STM8L052R) || \
+  (DEVICE & DEV_STM8L15x46) || \
+  (DEVICE & DEV_STM8L15x8) || \
+  (DEVICE & DEV_STM8L162)
+#define TIM1 ((struct TIM1_t *)0x52B0)
+#endif
+
+/* TIM2
+ */
+
+#if ((DEVICE & DEV_STM8S005) || \
+     (DEVICE & DEV_STM8S007) || \
+     (DEVICE & DEV_STM8S105) || \
+     (DEVICE & DEV_STM8S207) || \
+     (DEVICE & DEV_STM8S208) || \
+     (DEVICE & DEV_STM8AF52) ||	\
+     (DEVICE & DEV_STM8AF62_46))
+struct TIM2_t {
+  volatile uint8_t cr1;		//=  0;
+  volatile uint8_t ier;		//=  1;
+  volatile uint8_t sr1;		//=  2;
+  volatile uint8_t sr2;		//=  3;
+  volatile uint8_t egr;		//=  4;
+  volatile uint8_t ccmr1;	//=  5;
+  volatile uint8_t ccmr2;	//=  6;
+  volatile uint8_t ccmr3;	//=  7;
+  volatile uint8_t ccer1;	//=  8;
+  volatile uint8_t ccer2;	//=  9;
+  volatile uint8_t cntrh;	//= 10;
+  volatile uint8_t cntrl;	//= 11;
+  volatile uint8_t pscrl;	//= 12;
+  volatile uint8_t arrh;	//= 13;
+  volatile uint8_t arrl;	//= 14;
+  volatile uint8_t ccr1h;	//= 15;
+  volatile uint8_t ccr1l;	//= 0x10;
+  volatile uint8_t ccr2h;	//= 0x11;
+  volatile uint8_t ccr2l;	//= 0x12;
+  volatile uint8_t ccr3h;	//= 0x13;
+  volatile uint8_t ccr3l;	//= 0x14;
+};
+#define TIM2_UP_IRQ 13
+#define TIM2_CC_IRQ 14
+#define TIM2 ((struct TIM2_t *)0x5300)
+#elif ((DEVICE & DEV_STM8S003) || \
+       (DEVICE & DEV_STM8S103))
+struct TIM2_t {
+  volatile uint8_t cr1;		//=  0;
+  volatile uint8_t _dummy1;	//=  1;
+  volatile uint8_t _dummy2;	//=  2;
+  volatile uint8_t ier;		//=  3;
+  volatile uint8_t sr1;		//=  4;
+  volatile uint8_t sr2;		//=  5;
+  volatile uint8_t egr;		//=  6;
+  volatile uint8_t ccmr1;	//=  7;
+  volatile uint8_t ccmr2;	//=  8;
+  volatile uint8_t ccmr3;	//=  9;
+  volatile uint8_t ccer1;	//= 10;
+  volatile uint8_t ccer2;	//= 11;
+  volatile uint8_t cntrh;	//= 12;
+  volatile uint8_t cntrl;	//= 13;
+  volatile uint8_t pscrl;	//= 14;
+  volatile uint8_t arrh;	//= 15;
+  volatile uint8_t arrl;	//= 16;
+  volatile uint8_t ccr1h;	//= 0x11;
+  volatile uint8_t ccr1l;	//= 0x12;
+  volatile uint8_t ccr2h;	//= 0x13;
+  volatile uint8_t ccr2l;	//= 0x14;
+  volatile uint8_t ccr3h;	//= 0x15;
+  volatile uint8_t ccr3l;	//= 0x16;
+};
+#define TIM2_UP_IRQ 13
+#define TIM2_CC_IRQ 14
+#define TIM2 ((struct TIM2_t *)0x5300)
+#elif (DEVICE & DEV_STM8ALL)
+struct TIM2_t {
+  volatile uint8_t cr1;		//=  0;
+  volatile uint8_t cr2;		//=  1;
+  volatile uint8_t smcr;	//=  2;
+  volatile uint8_t etr;		//=  3;
+  volatile uint8_t der;		//=  4;
+  volatile uint8_t ier;		//=  5;
+  volatile uint8_t sr1;		//=  6;
+  volatile uint8_t sr2;		//=  7;
+  volatile uint8_t egr;		//=  8;
+  volatile uint8_t ccmr1;	//=  9;
+  volatile uint8_t ccmr2;	//= 0x0a;
+  volatile uint8_t ccer1;	//= 0x0b;
+  volatile uint8_t cntrh;	//= 0x0c;
+  volatile uint8_t cntrl;	//= 0x0d;
+  volatile uint8_t pscrl;	//= 0x0e;
+  volatile uint8_t arrh;	//= 0x0f;
+  volatile uint8_t arrl;	//= 0x10;
+  volatile uint8_t ccr1h;	//= 0x11;
+  volatile uint8_t ccr1l;	//= 0x12;
+  volatile uint8_t ccr2h;	//= 0x13;
+  volatile uint8_t ccr2l;	//= 0x14;
+  volatile uint8_t bkr;		//= 0x15;
+  volatile uint8_t oisr;	//= 0x16;
+};
+#define TIM2_UP_IRQ 19
+#define TIM2_CC_IRQ 20
+#define TIM2 ((struct TIM2_t *)0x5250)
+#elif (DEVICE & DEV_STM8L101)
+struct TIM2_t {
+  volatile uint8_t cr1;		//=  0;
+  volatile uint8_t cr2;		//=  1;
+  volatile uint8_t smcr;	//=  2;
+  volatile uint8_t etr;		//=  3;
+  volatile uint8_t ier;		//=  4;
+  volatile uint8_t sr1;		//=  5;
+  volatile uint8_t sr2;		//=  6;
+  volatile uint8_t egr;		//=  7;
+  volatile uint8_t ccmr1;	//=  8;
+  volatile uint8_t ccmr2;	//= 0x09;
+  volatile uint8_t ccer1;	//= 0x0a;
+  volatile uint8_t cntrh;	//= 0x0b;
+  volatile uint8_t cntrl;	//= 0x0c;
+  volatile uint8_t pscrl;	//= 0x0d;
+  volatile uint8_t arrh;	//= 0x0e;
+  volatile uint8_t arrl;	//= 0x0f;
+  volatile uint8_t ccr1h;	//= 0x10;
+  volatile uint8_t ccr1l;	//= 0x11;
+  volatile uint8_t ccr2h;	//= 0x12;
+  volatile uint8_t ccr2l;	//= 0x13;
+  volatile uint8_t bkr;		//= 0x14;
+  volatile uint8_t oisr;	//= 0x15;
+};
+#define TIM2_UP_IRQ 19
+#define TIM2_CC_IRQ 20
+#define TIM2 ((struct TIM2_t *)0x5250)
+#endif
+
+/* USART
+ */
+
+#define USART_CR2_TEN (1 << 3)
+#define USART_CR2_REN (1 << 2)
+#define USART_CR2_RIEN (1 << 5)
+#define USART_CR3_STOP2 (1 << 5)
+#define USART_CR3_STOP1 (1 << 4)
+#define USART_SR_TXE (1 << 7)
+#define USART_SR_RXNE (1 << 5)
+
+/* USART1
+ */
+
+struct USART1_saf_t {
+  volatile uint8_t sr;
+  volatile uint8_t dr;
+  volatile uint8_t brr1;
+  volatile uint8_t brr2;
+  volatile uint8_t cr1;
+  volatile uint8_t cr2;
+  volatile uint8_t cr3;
+  volatile uint8_t cr4;
+  volatile uint8_t cr5;
+  volatile uint8_t gtr;
+  volatile uint8_t pscr;
+};
+
+struct USART1_all_t {
+  volatile uint8_t sr;
+  volatile uint8_t dr;
+  volatile uint8_t brr1;
+  volatile uint8_t brr2;
+  volatile uint8_t cr1;
+  volatile uint8_t cr2;
+  volatile uint8_t cr3;
+  volatile uint8_t cr4;
+  volatile uint8_t cr5;
+  volatile uint8_t gtr;
+  volatile uint8_t pscr;
+};
+
+struct USART1_l101_t {
+  volatile uint8_t sr;
+  volatile uint8_t dr;
+  volatile uint8_t brr1;
+  volatile uint8_t brr2;
+  volatile uint8_t cr1;
+  volatile uint8_t cr2;
+  volatile uint8_t cr3;
+  volatile uint8_t cr4;
+};
+
+#if (DEVICE & DEV_STM8S003) || \
+  (DEVICE & DEV_STM8S007) || \
+  (DEVICE & DEV_STM8S103) || \
+  (DEVICE & DEV_STM8S207) || \
+  (DEVICE & DEV_STM8S208) || \
+  (DEVICE & DEV_STM8S903) || \
+  (DEVICE & DEV_STM8AF52)
+#define USART1_t USART1_saf_t
+#define USART1 ((struct USART1_t *)0x5230)
+#endif
+
+#if (DEVICE & DEV_STM8ALL)
+#define USART1_t USART1_all_t
+#define USART1 ((struct USART1_t *)0x5230)
+#endif
+
+#if (DEVICE & DEV_STM8L101)
+#define USART1_t USART1_l101_t
+#define USART1 ((struct USART1_t *)0x5230)
+#endif
+
+/* USART2
+ */
+
+struct USART2_saf_t {
+  volatile uint8_t sr;
+  volatile uint8_t dr;
+  volatile uint8_t brr1;
+  volatile uint8_t brr2;
+  volatile uint8_t cr1;
+  volatile uint8_t cr2;
+  volatile uint8_t cr3;
+  volatile uint8_t cr4;
+  volatile uint8_t cr5;
+  volatile uint8_t cr6;
+  volatile uint8_t gtr;
+  volatile uint8_t pscr;
+};
+
+struct USART2_all_t {
+  volatile uint8_t sr;
+  volatile uint8_t dr;
+  volatile uint8_t brr1;
+  volatile uint8_t brr2;
+  volatile uint8_t cr1;
+  volatile uint8_t cr2;
+  volatile uint8_t cr3;
+  volatile uint8_t cr4;
+  volatile uint8_t cr5;
+  volatile uint8_t gtr;
+  volatile uint8_t pscr;
+};
+
+#if (DEVICE & DEV_STM8S005) || \
+  (DEVICE & DEV_STM8S105) || \
+  (DEVICE & DEV_STM8AF62_46)
+#define USART2_t USART2_saf_t
+#define USART2 ((struct USART2_t *)0x5240)
+#endif
+
+#if (DEVICE & DEV_STM8AL3xE) || \
+  (DEVICE & DEV_STM8AL3x8) || \
+  (DEVICE & DEV_STM8L052R) || \
+  (DEVICE & DEV_STM8L15x8) || \
+  (DEVICE & DEV_STM8L162)
+#define USART2_t USART2_all_t
+#define USART2 ((struct USART2_t *)0x53E0)
+#endif
+
+/* USART3
+ */
+
+struct USART3_saf_t {
+  volatile uint8_t sr;
+  volatile uint8_t dr;
+  volatile uint8_t brr1;
+  volatile uint8_t brr2;
+  volatile uint8_t cr1;
+  volatile uint8_t cr2;
+  volatile uint8_t cr3;
+  volatile uint8_t cr4;
+  volatile uint8_t _dummy;
+  volatile uint8_t cr6;
+  volatile uint8_t gtr;
+  volatile uint8_t pscr;
+};
+
+struct USART3_all_t {
+  volatile uint8_t sr;
+  volatile uint8_t dr;
+  volatile uint8_t brr1;
+  volatile uint8_t brr2;
+  volatile uint8_t cr1;
+  volatile uint8_t cr2;
+  volatile uint8_t cr3;
+  volatile uint8_t cr4;
+  volatile uint8_t cr5;
+  volatile uint8_t gtr;
+  volatile uint8_t pscr;
+};
+
+#if (DEVICE & DEV_STM8S007) || \
+  (DEVICE & DEV_STM8S207) || \
+  (DEVICE & DEV_STM8S208) || \
+  (DEVICE & DEV_STM8AF52)
+#define USART3_t USART3_saf_t
+#define USART3 ((struct USART3_t *)0x5240)
+#endif
+
+#if (DEVICE & DEV_STM8AL3xE) || \
+  (DEVICE & DEV_STM8AL3x8) || \
+  (DEVICE & DEV_STM8L052R) || \
+  (DEVICE & DEV_STM8L15x8) || \
+  (DEVICE & DEV_STM8L162)
+#define USART3_t USART3_all_t
+#define USART3 ((struct USART3_t *)0x53F0)
+#endif
+
+/* USART4
+ */
+
+struct USART4_saf_t {
+  volatile uint8_t sr;
+  volatile uint8_t dr;
+  volatile uint8_t brr1;
+  volatile uint8_t brr2;
+  volatile uint8_t cr1;
+  volatile uint8_t cr2;
+  volatile uint8_t cr3;
+  volatile uint8_t cr4;
+  volatile uint8_t cr5;
+  volatile uint8_t cr6;
+  volatile uint8_t gtr;
+  volatile uint8_t pscr;
+};
+
+#if (DEVICE & DEV_STM8AF62_12)
+#define USART4_t USART4_saf_t
+#define USART4 ((struct USART4_t *)0x5230)
+#endif
+
+/* USART interrupt numbers */
+
+#if (DEVICE & DEV_STM8SAF)
+#if defined USART1
+#define USART1_TX_IRQ 17
+#define USART1_RX_IRQ 18
+#endif
+#endif
+#if (DEVICE & DEV_STM8ALL) || \
+  (DEVICE & DEV_STM8_L101)
+#if defined USART1
+#define USART1_TX_IRQ 27
+#define USART1_RX_IRQ 28
+#endif
+#endif
+
+#if (DEVICE & DEV_STM8SAF)
+#if defined USART2
+#define USART2_TX_IRQ 20
+#define USART2_RX_IRQ 21
+#endif
+#endif
+#if (DEVICE & DEV_STM8ALL)
+#if defined USART2
+#define USART2_TX_IRQ 19
+#define USART2_RX_IRQ 20
+#endif
+#endif
+
+#if (DEVICE & DEV_STM8SAF)
+#if defined USART3
+#define USART3_TX_IRQ 20
+#define USART3_RX_IRQ 21
+#endif
+#endif
+#if (DEVICE & DEV_STM8ALL)
+#if defined USART3
+#define USART3_TX_IRQ 21
+#define USART3_RX_IRQ 22
+#endif
+#endif
+
+#if defined USART4
+#define USART3_TX_IRQ 17
+#define USART3_RX_IRQ 18
+#endif
+
+/* Select first USART as default */
+
+#ifndef USART
+#if (DEVICE & DEV_STM8S003) || \
+  (DEVICE & DEV_STM8S007) || \
+  (DEVICE & DEV_STM8S103) || \
+  (DEVICE & DEV_STM8S207) || \
+  (DEVICE & DEV_STM8S208) || \
+  (DEVICE & DEV_STM8S903) || \
+  (DEVICE & DEV_STM8AF52) || \
+  (DEVICE & DEV_STM8ALL) || \
+  (DEVICE & DEV_STM8L101)
+#define USART USART1
+#define USART_TX_IRQ USART1_TX_IRQ
+#define USART_RX_IRQ USART1_RX_IRQ
+#endif
+#if (DEVICE & DEV_STM8S005) || \
+  (DEVICE & DEV_STM8S105) || \
+  (DEVICE & DEV_STM8AF62_46)
+#define USART USART2
+#define USART_TX_IRQ USART2_TX_IRQ
+#define USART_RX_IRQ USART2_RX_IRQ
+#endif
+#if (DEVICE & DEV_STM8AF62_12)
+#define USART USART4
+#define USART_TX_IRQ USART4_TX_IRQ
+#define USART_RX_IRQ USART4_RX_IRQ
+#endif
+#endif
+#if ((DEVICE & DEV_STM8S003) || \
+     (DEVICE & DEV_STM8S005) || \
+     (DEVICE & DEV_STM8S103) || \
+     (DEVICE & DEV_STM8S105) || \
+     (DEVICE & DEV_STM8S903) || \
+     (DEVICE & DEV_STM8AF62_12) || \
+     (DEVICE & DEV_STM8AF62_46))
+#define USART_TX_GPIO GPIOD
+#define USART_RX_GPIO GPIOD
+#define USART_TX_PIN  5
+#define USART_RX_PIN  6
+#endif
+#if ((DEVICE & DEV_STM8S007) ||\
+     (DEVICE & DEV_STM8S207) ||\
+     (DEVICE & DEV_STM8S208) ||\
+     (DEVICE & DEV_STM8AF52))
+#define USART_TX_GPIO GPIOA
+#define USART_RX_GPIO GPIOA
+#define USART_TX_PIN  5
+#define USART_RX_PIN  4
+#endif
+#if (DEVICE & DEV_STM8AL) ||\
+  (DEVICE & DEV_STM8L052C) ||\
+  (DEVICE & DEV_STM8L052R) ||\
+  (DEVICE & DEV_STM8L151x23) ||\
+  (DEVICE & DEV_STM8L15x46) ||\
+  (DEVICE & DEV_STM8L15x8) ||\
+  (DEVICE & DEV_STM8L162) ||\
+  (DEVICE & DEV_STM8L101)
+#define USART_TX_GPIO GPIOC
+#define USART_RX_GPIO GPIOC
+#define USART_TX_PIN  3
+#define USART_RX_PIN  2
+#endif
+#if (DEVICE & DEV_STM8L051)
+/* non-default AF only because C2 and C3 are not available */
+#define USART_TX_GPIO
+#define USART_RX_GPIO
+#define USART_TX_PIN 
+#define USART_RX_PIN 
+#endif
+
+/* CLK
+ */
+
+#if (DEVICE & DEV_STM8SAF)
+struct CLK_t {
+  uint8_t ickr;
+  uint8_t eckr;
+  uint8_t _dummy1;
+  uint8_t cmsr;
+  uint8_t swr;
+  uint8_t swcr;
+  uint8_t ckdivr;
+  uint8_t pckenr1;
+  uint8_t cssr;
+  uint8_t ccor;
+  uint8_t pckenr2;
+  uint8_t _dummy2;
+  uint8_t hsitrimr;
+  uint8_t swimccr;
+};
+#endif
+#if (DEVICE & DEV_STM8ALL)
+struct CLK_t {
+  uint8_t ckdivr;
+  uint8_t crtcr;
+  uint8_t ickcr;
+  uint8_t pckenr1;
+  uint8_t pckenr2;
+  uint8_t ccor;
+  uint8_t eckcr;
+  uint8_t scsr;
+  uint8_t swr;
+  uint8_t swcr;
+  uint8_t cssr;
+  uint8_t cbeepr;
+  uint8_t hsicalr;
+  uint8_t hsitrimr;
+  uint8_t hsiunclkr;
+  uint8_t regcsr;
+  uint8_t pckenr3;
+};
+#endif
+#if (DEVICE & DEV_STM8L101)
+struct CLK_t {
+  uint8_t ckdivr;
+  uint8_t _dummy1;
+  uint8_t _dummy2;
+  uint8_t pckenr;
+  uint8_t _dummy3;
+  uint8_t ccor;
+};
+#endif
+
+#define CLK ((struct CLK_t *)0x50C0)
+
+/* UID
+ */
+
+#if (DEVICE & DEV_STM8S103) || \
+  (DEVICE & DEV_STM8S903) || \
+  (DEVICE & DEV_STM8AF62_12)
+#define UID ((uint8_t*)0x4865)
+#endif
+#if (DEVICE & DEV_STM8AL) || \
+  (DEVICE & DEV_STM8L151x23) || \
+  (DEVICE & DEV_STM8L15x46) ||	\
+  (DEVICE & DEV_STM8L15x8) || \
+  (DEVICE & DEV_STM8L162)
+#define UID ((uint8_t*)0x4926)
+#endif
+#if (DEVICE & DEV_STM8L101)
+#define UID ((uint8_t*)0x4925)
+#endif
+
+/* FLASH
+ */
+
+#if (DEVICE & DEV_STM8SAF)
+struct FLASH_t {
+  volatile uint8_t cr1;
+  volatile uint8_t cr2;
+  volatile uint8_t ncr2;
+  volatile uint8_t fpr;
+  volatile uint8_t nfpr;
+  volatile uint8_t iapsr;
+  volatile uint16_t dummy1;
+  volatile uint8_t pukr;
+  volatile uint8_t dummy2;
+  volatile uint8_t dukr;
+};
+#define FLASH ((volatile struct FLASH_t * volatile)0x505a)
+#define FLASH_IRQ 24
+#elif (DEVICE & DEV_STM8ALL) ||			\
+  (DEVICE & DEV_STM8L101)
+struct FLASH_t {
+  volatile uint8_t cr1;
+  volatile uint8_t cr2;
+  volatile uint8_t pukr;
+  volatile uint8_t dukr;
+  volatile uint8_t iapsr;
+};
+#define FLASH ((struct FLASH_t *)0x5050)
+#define FLASH_IRQ 1
+#endif
+
+#define EI __asm__("rim")
+#define DI __asm__("sim")
+
+#endif
diff --git a/sim/ucsim/stm8.src/test/t1.c b/sim/ucsim/stm8.src/test/t1.c
new file mode 100644
index 0000000..354f72a
--- /dev/null
+++ b/sim/ucsim/stm8.src/test/t1.c
@@ -0,0 +1,21 @@
+volatile int x= 1;
+
+void isr_trap(void) __trap
+{
+  x= 2;
+}
+
+void trap()
+{
+  __asm
+    trap;
+  __endasm;
+}
+
+void
+main(void)
+{
+  trap();
+  for (;;)
+    ;
+}
diff --git a/sim/ucsim/stm8.src/test/t2.c b/sim/ucsim/stm8.src/test/t2.c
new file mode 100644
index 0000000..a3e3df8
--- /dev/null
+++ b/sim/ucsim/stm8.src/test/t2.c
@@ -0,0 +1,17 @@
+volatile unsigned char *sif= (unsigned char *)0x7fff;
+
+volatile char c;
+
+int f(int i)
+{
+  c= i;
+  return i;
+}
+
+void main(void)
+{
+  f('H'*256 + 'L');
+  *sif= 'p';
+  *sif= c;
+  *sif= 's';
+}
diff --git a/sim/ucsim/stm8.src/test/t3.c b/sim/ucsim/stm8.src/test/t3.c
new file mode 100644
index 0000000..d182906
--- /dev/null
+++ b/sim/ucsim/stm8.src/test/t3.c
@@ -0,0 +1,15 @@
+#include <stdio.h>
+
+volatile unsigned char *sif= (unsigned char *)0x7fff;
+
+int putchar(int c)
+{
+  *sif= 'p';
+  *sif= c;
+  return c;
+}
+
+void main(void)
+{
+  printf("A");
+}
diff --git a/sim/ucsim/stm8.src/test/t4.c b/sim/ucsim/stm8.src/test/t4.c
new file mode 100644
index 0000000..d594dfe
--- /dev/null
+++ b/sim/ucsim/stm8.src/test/t4.c
@@ -0,0 +1,16 @@
+#include <stdio.h>
+
+volatile unsigned char c;
+
+int putchar(int ch)
+{
+  c= ch;
+  return ch;
+}
+
+void main(void)
+{
+  printf("A");
+  putchar('B');
+  for (;;) ;
+}
diff --git a/sim/ucsim/stm8.src/test/xtest.c b/sim/ucsim/stm8.src/test/xtest.c
new file mode 100644
index 0000000..95f7598
--- /dev/null
+++ b/sim/ucsim/stm8.src/test/xtest.c
@@ -0,0 +1,10 @@
+#include <stdio.h>
+
+char buf[10];
+
+void
+main(void)
+{
+  sprintf(buf, "%x", 0x1234);
+  for (;;);
+}
diff --git a/sim/ucsim/stm8.src/test/xtest.mk b/sim/ucsim/stm8.src/test/xtest.mk
new file mode 100644
index 0000000..5d8d31b
--- /dev/null
+++ b/sim/ucsim/stm8.src/test/xtest.mk
@@ -0,0 +1 @@
+DEVICES		= LDISC