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| author | Xavier ASUS <xavi92psx@gmail.com> | 2019-10-18 00:31:54 +0200 |
|---|---|---|
| committer | Xavier ASUS <xavi92psx@gmail.com> | 2019-10-18 00:31:54 +0200 |
| commit | 268a53de823a6750d6256ee1fb1e7707b4b45740 (patch) | |
| tree | 42c1799a9a82b2f7d9790ee9fe181d72a7274751 /sim/ucsim/stm8.src | |
| download | sdcc-gas-268a53de823a6750d6256ee1fb1e7707b4b45740.tar.gz | |
sdcc-3.9.0 fork implementing GNU assembler syntax
This fork aims to provide better support for stm8-binutils
Diffstat (limited to 'sim/ucsim/stm8.src')
97 files changed, 12854 insertions, 0 deletions
diff --git a/sim/ucsim/stm8.src/(c).1 b/sim/ucsim/stm8.src/(c).1 new file mode 100644 index 0000000..d673f9f --- /dev/null +++ b/sim/ucsim/stm8.src/(c).1 @@ -0,0 +1,25 @@ +/* + * Simulator of microcontrollers (@@F@@) + * + * Copyright (C) @@S@@,@@Y@@ Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ diff --git a/sim/ucsim/stm8.src/Makefile b/sim/ucsim/stm8.src/Makefile new file mode 100644 index 0000000..48f016a --- /dev/null +++ b/sim/ucsim/stm8.src/Makefile @@ -0,0 +1,183 @@ +# +# uCsim stm8.src/Makefile +# +# (c) Drotos Daniel, Talker Bt. 1997 +# + +STARTYEAR = 1997 + +SHELL = /bin/sh +CXX = g++ +CPP = gcc -E +CXXCPP = g++ -E +RANLIB = ranlib +INSTALL = /usr/bin/install -c +STRIP = strip +MAKEDEP = g++ -MM +SREC_CAT = + +top_builddir = .. +top_srcdir = .. + +DEFS = $(subs -DHAVE_CONFIG_H,,-DHAVE_CONFIG_H) +CPPFLAGS = -I$(srcdir) -I$(top_srcdir) -I$(top_builddir) \ + -I$(top_srcdir)/cmd.src -I$(top_srcdir)/sim.src \ + -I$(top_srcdir)/gui.src +CFLAGS = -g -O2 -Wall +CXXFLAGS = -g -O2 -g -Wall +LDFLAGS = +PICOPT = -fPIC -DPIC +SHAREDLIB = yes + +EXEEXT = + +LIBS = -L$(top_builddir) -lsim -lucsimutil -lguiucsim -lcmd -lsim -lrt -lnsl +DL = -ldl +dl_ok = yes + +prefix = /usr/local +exec_prefix = ${prefix} +bindir = ${exec_prefix}/bin +libdir = ${exec_prefix}/lib +datadir = ${datarootdir} +datarootdir = ${prefix}/share +includedir = ${prefix}/include +mandir = ${datarootdir}/man +man1dir = $(mandir)/man1 +man2dir = $(mandir)/man2 +infodir = ${datarootdir}/info +srcdir = . + + +OBJECTS_SHARED = glob.o itc.o serial.o rst.o timer.o port.o clk.o \ + uid.o bl.o flash.o \ + inst.o \ + simstm8.o stm8.o +OBJECTS_EXE = sstm8.o +OBJECTS = $(OBJECTS_SHARED) $(OBJECTS_EXE) + +STM8ASM = + +enable_dlso = no +dlso_ok = no + +#TEST_OBJ = test_bit.hex test_dis.hex test_mov.hex test_jmp.hex \ +# test_arith.hex + +# Compiling entire program or any subproject +# ------------------------------------------ +all: checkconf otherlibs stm8.src + +tests: $(TEST_OBJ) + + +# Compiling and installing everything and runing test +# --------------------------------------------------- +install: all installdirs + $(INSTALL) sstm8$(EXEEXT) $(DESTDIR)$(bindir)/`echo sstm8|sed '$(transform)'`$(EXEEXT) + $(STRIP) $(DESTDIR)$(bindir)/`echo sstm8|sed '$(transform)'`$(EXEEXT) + + +# Deleting all the installed files +# -------------------------------- +uninstall: + rm -f $(DESTDIR)$(bindir)/`echo sstm8|sed '$(transform)'`$(EXEEXT) + + +# Performing self-test +# -------------------- +check: test + +test: + + +# Performing installation test +# ---------------------------- +installcheck: + + +# Creating installation directories +# --------------------------------- +installdirs: + test -d $(DESTDIR)$(bindir) || $(INSTALL) -d $(DESTDIR)$(bindir) + + +# Creating dependencies +# --------------------- +dep: Makefile.dep + +Makefile.dep: $(srcdir)/*.cc $(srcdir)/*.h + $(MAKEDEP) $(CPPFLAGS) $(filter %.cc,$^) >Makefile.dep + +-include Makefile.dep +include $(srcdir)/clean.mk + +# My rules +# -------- +.SUFFIXES: .asm .hex + +stm8.src: sstm8$(EXEEXT) shared_lib + +sstm8$(EXEEXT): $(OBJECTS) $(top_builddir)/libcmd.a $(top_builddir)/libguiucsim.a $(top_builddir)/libsim.a $(top_builddir)/libucsimutil.a + $(CXX) $(CXXFLAGS) $(LDFLAGS) $(OBJECTS) $(LIBS) -o $@ + +ifeq ($(dlso_ok),yes) +shared_lib: $(top_builddir)/sstm8.so +else +shared_lib: + @$(top_srcdir)/mkecho $(top_builddir) "No stm8 shared lib made." + @$(top_srcdir)/mkecho $(top_builddir) "(SHAREDLIB="$(SHAREDLIB)",dl_ok="$(dl_ok)",enable_dlso="$(enable_dlso)")" +endif + +$(top_builddir)/sstm8.so: $(OBJECTS_SHARED) + $(CXX) -shared $(LDFLAGS) $(OBJECTS_SHARED) -o $(top_builddir)/sstm8.so + +otherlibs: $(top_builddir)/libcmd.a $(top_builddir)/libguiucsim.a $(top_builddir)/libsim.a $(top_builddir)/libucsimutil.a + +$(top_builddir)/libcmd.a: + $(MAKE) -C $(top_builddir)/cmd.src all + +$(top_builddir)/libguiucsim.a: + $(MAKE) -C $(top_builddir)/gui.src checkconf ucsim_lib + +$(top_builddir)/libsim.a: + $(MAKE) -C $(top_builddir)/sim.src all + +$(top_builddir)/libucsimutil.a: + $(MAKE) -C $(top_builddir) -f main.mk + +.cc.o: + $(CXX) $(CXXFLAGS) $(PICOPT) $(CPPFLAGS) $(TARGET_ARCH) -c $< -o $@ + +.asm.hex: + $(STM8ASM) -l $< -o $@ -e $<.lst + + +# Remaking configuration +# ---------------------- +checkconf: + @if [ -f $(top_builddir)/devel ]; then\ + $(MAKE) -C $(top_builddir) -f conf.mk srcdir="$(srcdir)" top_builddir="$(top_builddir)" freshconf;\ + fi + +#bl_l15x46.hex: bl_l15x46.asc +# $(SREC_CAT) $< -Ascii_Hex -Output $@ -Intel + +#bl_l15x46.cc: bl_l15x46.asc +# $(SREC_CAT) $< -Ascii_Hex -Output $@ -C-Array bl_l15x46 -INClude -No-CONST + +#bl_s105.hex: bl_s105.asc +# $(SREC_CAT) $< -Ascii_Hex -Output $@ -Intel + +#bl_s105.cc: bl_s105.asc +# $(SREC_CAT) $< -Ascii_Hex -Output $@ -C-Array bl_s105 -INClude -No-CONST + +#bl_source: bl.cc bl.h + +#bl.cc: bl_head.cc bl_l15x46.cc bl_s105.cc +# cat bl_head.cc bl_l15x46.cc bl_s105.cc|sed 's/unsigned char/t_mem/' >$@ + +#bl.h: bl_l15x46.h bl_s105.h +# cat bl_l15x46.h bl_s105.h|sed 's/unsigned char/t_mem/' >$@ + +# End of stm8.src/Makefile.in diff --git a/sim/ucsim/stm8.src/Makefile.dep b/sim/ucsim/stm8.src/Makefile.dep new file mode 100644 index 0000000..af24d61 --- /dev/null +++ b/sim/ucsim/stm8.src/Makefile.dep @@ -0,0 +1,123 @@ +uid.o: uid.cc uidcl.h ../sim.src/hwcl.h ../stypes.h ../ddconfig.h \ + ../pobjcl.h ../pobjt.h ../eventcl.h ../charscl.h ../sim.src/guiobjcl.h \ + ../ddconfig.h ../cmd.src/newcmdcl.h ../optioncl.h ../pobjcl.h \ + ../stypes.h ../cmd.src/commandcl.h ../cmd.src/newcmdcl.h \ + ../cmd.src/newcmdposixcl.h ../fiocl.h ../cmd.src/cmdutil.h \ + ../sim.src/memcl.h ../eventcl.h ../errorcl.h ../sim.src/uccl.h \ + ../pobjt.h ../sim.src/hwcl.h ../sim.src/brkcl.h ../sim.src/stackcl.h \ + ../sim.src/varcl.h ../sim.src/uccl_instructions.h +bl_s105.o: bl_s105.cc +bl.o: bl.cc ../stypes.h ../ddconfig.h bl.h +bl_l15x46.o: bl_l15x46.cc +flash.o: flash.cc ../globals.h ../ddconfig.h ../stypes.h ../appcl.h \ + ../pobjcl.h ../pobjt.h ../eventcl.h ../charscl.h ../optioncl.h \ + ../sim.src/argcl.h ../pobjcl.h ../stypes.h ../sim.src/simcl.h \ + ../cmd.src/newcmdcl.h ../ddconfig.h ../optioncl.h ../cmd.src/commandcl.h \ + ../cmd.src/newcmdcl.h ../gui.src/guicl.h ../gui.src/ifcl.h \ + ../sim.src/guiobjcl.h ../sim.src/uccl.h ../pobjt.h ../sim.src/hwcl.h \ + ../sim.src/guiobjcl.h ../cmd.src/newcmdposixcl.h ../fiocl.h \ + ../cmd.src/cmdutil.h ../sim.src/memcl.h ../eventcl.h ../errorcl.h \ + ../sim.src/brkcl.h ../sim.src/stackcl.h ../sim.src/varcl.h \ + ../sim.src/uccl_instructions.h ../sim.src/argcl.h stm8cl.h \ + ../sim.src/uccl.h ../sim.src/itsrccl.h regsstm8.h itccl.h instcl.h \ + flashcl.h ../sim.src/hwcl.h ../sim.src/memcl.h +port.o: port.cc portcl.h ../sim.src/port_hwcl.h \ + ../cmd.src/newcmdposixcl.h ../fiocl.h ../charscl.h ../pobjcl.h \ + ../ddconfig.h ../pobjt.h ../eventcl.h ../cmd.src/newcmdcl.h \ + ../ddconfig.h ../pobjcl.h ../optioncl.h ../stypes.h \ + ../cmd.src/commandcl.h ../cmd.src/cmdutil.h ../sim.src/hwcl.h \ + ../stypes.h ../sim.src/guiobjcl.h ../cmd.src/newcmdcl.h \ + ../sim.src/memcl.h ../eventcl.h ../errorcl.h ../sim.src/uccl.h \ + ../pobjt.h ../sim.src/brkcl.h ../sim.src/stackcl.h ../sim.src/varcl.h \ + ../sim.src/uccl_instructions.h +timer.o: timer.cc ../sim.src/itsrccl.h ../pobjcl.h ../ddconfig.h \ + ../pobjt.h ../eventcl.h ../charscl.h ../stypes.h ../sim.src/uccl.h \ + ../pobjt.h ../sim.src/hwcl.h ../sim.src/guiobjcl.h ../ddconfig.h \ + ../cmd.src/newcmdcl.h ../optioncl.h ../pobjcl.h ../stypes.h \ + ../cmd.src/commandcl.h ../cmd.src/newcmdcl.h ../cmd.src/newcmdposixcl.h \ + ../fiocl.h ../cmd.src/cmdutil.h ../sim.src/memcl.h ../eventcl.h \ + ../errorcl.h ../sim.src/brkcl.h ../sim.src/stackcl.h ../sim.src/varcl.h \ + ../sim.src/uccl_instructions.h clkcl.h ../sim.src/hwcl.h timercl.h +bl_head.o: bl_head.cc ../stypes.h ../ddconfig.h bl.h +sstm8.o: sstm8.cc ../globals.h ../ddconfig.h ../stypes.h ../appcl.h \ + ../pobjcl.h ../pobjt.h ../eventcl.h ../charscl.h ../optioncl.h \ + ../sim.src/argcl.h ../pobjcl.h ../stypes.h ../sim.src/simcl.h \ + ../cmd.src/newcmdcl.h ../ddconfig.h ../optioncl.h ../cmd.src/commandcl.h \ + ../cmd.src/newcmdcl.h ../gui.src/guicl.h ../gui.src/ifcl.h \ + ../sim.src/guiobjcl.h ../sim.src/uccl.h ../pobjt.h ../sim.src/hwcl.h \ + ../sim.src/guiobjcl.h ../cmd.src/newcmdposixcl.h ../fiocl.h \ + ../cmd.src/cmdutil.h ../sim.src/memcl.h ../eventcl.h ../errorcl.h \ + ../sim.src/brkcl.h ../sim.src/stackcl.h ../sim.src/varcl.h \ + ../sim.src/uccl_instructions.h ../sim.src/argcl.h ../appcl.h simstm8cl.h +serial.o: serial.cc ../ddconfig.h ../globals.h ../ddconfig.h ../stypes.h \ + ../appcl.h ../pobjcl.h ../pobjt.h ../eventcl.h ../charscl.h \ + ../optioncl.h ../sim.src/argcl.h ../pobjcl.h ../stypes.h \ + ../sim.src/simcl.h ../cmd.src/newcmdcl.h ../optioncl.h \ + ../cmd.src/commandcl.h ../cmd.src/newcmdcl.h ../gui.src/guicl.h \ + ../gui.src/ifcl.h ../sim.src/guiobjcl.h ../sim.src/uccl.h ../pobjt.h \ + ../sim.src/hwcl.h ../sim.src/guiobjcl.h ../cmd.src/newcmdposixcl.h \ + ../fiocl.h ../cmd.src/cmdutil.h ../sim.src/memcl.h ../eventcl.h \ + ../errorcl.h ../sim.src/brkcl.h ../sim.src/stackcl.h ../sim.src/varcl.h \ + ../sim.src/uccl_instructions.h ../sim.src/argcl.h ../utils.h ../fiocl.h \ + ../cmd.src/cmdutil.h ../sim.src/itsrccl.h clkcl.h ../sim.src/hwcl.h \ + serialcl.h ../sim.src/uccl.h ../sim.src/serial_hwcl.h +stm8.o: stm8.cc ../ddconfig.h ../i_string.h ../ddconfig.h ../pobjcl.h \ + ../pobjt.h ../eventcl.h ../charscl.h ../globals.h ../stypes.h ../appcl.h \ + ../pobjcl.h ../optioncl.h ../sim.src/argcl.h ../stypes.h \ + ../sim.src/simcl.h ../cmd.src/newcmdcl.h ../optioncl.h \ + ../cmd.src/commandcl.h ../cmd.src/newcmdcl.h ../gui.src/guicl.h \ + ../gui.src/ifcl.h ../sim.src/guiobjcl.h ../sim.src/uccl.h ../pobjt.h \ + ../sim.src/hwcl.h ../sim.src/guiobjcl.h ../cmd.src/newcmdposixcl.h \ + ../fiocl.h ../cmd.src/cmdutil.h ../sim.src/memcl.h ../eventcl.h \ + ../errorcl.h ../sim.src/brkcl.h ../sim.src/stackcl.h ../sim.src/varcl.h \ + ../sim.src/uccl_instructions.h ../sim.src/argcl.h stm8cl.h \ + ../sim.src/uccl.h ../sim.src/itsrccl.h regsstm8.h itccl.h instcl.h \ + glob.h stm8mac.h serialcl.h ../sim.src/serial_hwcl.h rstcl.h \ + ../sim.src/hwcl.h timercl.h portcl.h ../sim.src/port_hwcl.h clkcl.h \ + uidcl.h bl.h flashcl.h ../sim.src/memcl.h +rst.o: rst.cc rstcl.h ../sim.src/hwcl.h ../stypes.h ../ddconfig.h \ + ../pobjcl.h ../pobjt.h ../eventcl.h ../charscl.h ../sim.src/guiobjcl.h \ + ../ddconfig.h ../cmd.src/newcmdcl.h ../optioncl.h ../pobjcl.h \ + ../stypes.h ../cmd.src/commandcl.h ../cmd.src/newcmdcl.h \ + ../cmd.src/newcmdposixcl.h ../fiocl.h ../cmd.src/cmdutil.h \ + ../sim.src/memcl.h ../eventcl.h ../errorcl.h ../sim.src/uccl.h \ + ../pobjt.h ../sim.src/hwcl.h ../sim.src/brkcl.h ../sim.src/stackcl.h \ + ../sim.src/varcl.h ../sim.src/uccl_instructions.h +glob.o: glob.cc ../stypes.h ../ddconfig.h +clk.o: clk.cc stm8cl.h ../sim.src/uccl.h ../stypes.h ../ddconfig.h \ + ../pobjcl.h ../pobjt.h ../eventcl.h ../charscl.h ../pobjt.h \ + ../sim.src/hwcl.h ../sim.src/guiobjcl.h ../ddconfig.h \ + ../cmd.src/newcmdcl.h ../optioncl.h ../pobjcl.h ../stypes.h \ + ../cmd.src/commandcl.h ../cmd.src/newcmdcl.h ../cmd.src/newcmdposixcl.h \ + ../fiocl.h ../cmd.src/cmdutil.h ../sim.src/memcl.h ../eventcl.h \ + ../errorcl.h ../sim.src/uccl.h ../sim.src/brkcl.h ../sim.src/stackcl.h \ + ../sim.src/varcl.h ../sim.src/uccl_instructions.h ../sim.src/itsrccl.h \ + regsstm8.h itccl.h instcl.h clkcl.h ../sim.src/hwcl.h +itc.o: itc.cc ../utils.h ../stypes.h ../ddconfig.h ../charscl.h \ + ../fiocl.h ../pobjcl.h ../pobjt.h ../eventcl.h ../sim.src/itsrccl.h \ + ../pobjcl.h ../stypes.h ../sim.src/uccl.h ../pobjt.h ../sim.src/hwcl.h \ + ../sim.src/guiobjcl.h ../ddconfig.h ../cmd.src/newcmdcl.h ../optioncl.h \ + ../cmd.src/commandcl.h ../cmd.src/newcmdcl.h ../cmd.src/newcmdposixcl.h \ + ../fiocl.h ../cmd.src/cmdutil.h ../sim.src/memcl.h ../eventcl.h \ + ../errorcl.h ../sim.src/brkcl.h ../sim.src/stackcl.h ../sim.src/varcl.h \ + ../sim.src/uccl_instructions.h itccl.h ../sim.src/uccl.h +inst.o: inst.cc ../ddconfig.h stm8cl.h ../sim.src/uccl.h ../stypes.h \ + ../ddconfig.h ../pobjcl.h ../pobjt.h ../eventcl.h ../charscl.h \ + ../pobjt.h ../sim.src/hwcl.h ../sim.src/guiobjcl.h ../cmd.src/newcmdcl.h \ + ../optioncl.h ../pobjcl.h ../stypes.h ../cmd.src/commandcl.h \ + ../cmd.src/newcmdcl.h ../cmd.src/newcmdposixcl.h ../fiocl.h \ + ../cmd.src/cmdutil.h ../sim.src/memcl.h ../eventcl.h ../errorcl.h \ + ../sim.src/uccl.h ../sim.src/brkcl.h ../sim.src/stackcl.h \ + ../sim.src/varcl.h ../sim.src/uccl_instructions.h ../sim.src/itsrccl.h \ + regsstm8.h itccl.h instcl.h stm8mac.h +simstm8.o: simstm8.cc ../globals.h ../ddconfig.h ../stypes.h ../appcl.h \ + ../pobjcl.h ../pobjt.h ../eventcl.h ../charscl.h ../optioncl.h \ + ../sim.src/argcl.h ../pobjcl.h ../stypes.h ../sim.src/simcl.h \ + ../cmd.src/newcmdcl.h ../ddconfig.h ../optioncl.h ../cmd.src/commandcl.h \ + ../cmd.src/newcmdcl.h ../gui.src/guicl.h ../gui.src/ifcl.h \ + ../sim.src/guiobjcl.h ../sim.src/uccl.h ../pobjt.h ../sim.src/hwcl.h \ + ../sim.src/guiobjcl.h ../cmd.src/newcmdposixcl.h ../fiocl.h \ + ../cmd.src/cmdutil.h ../sim.src/memcl.h ../eventcl.h ../errorcl.h \ + ../sim.src/brkcl.h ../sim.src/stackcl.h ../sim.src/varcl.h \ + ../sim.src/uccl_instructions.h ../sim.src/argcl.h simstm8cl.h stm8cl.h \ + ../sim.src/uccl.h ../sim.src/itsrccl.h regsstm8.h itccl.h instcl.h diff --git a/sim/ucsim/stm8.src/Makefile.in b/sim/ucsim/stm8.src/Makefile.in new file mode 100644 index 0000000..60fa543 --- /dev/null +++ b/sim/ucsim/stm8.src/Makefile.in @@ -0,0 +1,183 @@ +# +# uCsim stm8.src/Makefile +# +# (c) Drotos Daniel, Talker Bt. 1997 +# + +STARTYEAR = 1997 + +SHELL = /bin/sh +CXX = @CXX@ +CPP = @CPP@ +CXXCPP = @CXXCPP@ +RANLIB = @RANLIB@ +INSTALL = @INSTALL@ +STRIP = @STRIP@ +MAKEDEP = @MAKEDEP@ +SREC_CAT = @SREC_CAT@ + +top_builddir = @top_builddir@ +top_srcdir = @top_srcdir@ + +DEFS = $(subs -DHAVE_CONFIG_H,,@DEFS@) +CPPFLAGS = @CPPFLAGS@ -I$(srcdir) -I$(top_srcdir) -I$(top_builddir) \ + -I$(top_srcdir)/cmd.src -I$(top_srcdir)/sim.src \ + -I$(top_srcdir)/gui.src +CFLAGS = @CFLAGS@ @WALL_FLAG@ +CXXFLAGS = @CXXFLAGS@ @WALL_FLAG@ +LDFLAGS = @LDFLAGS@ +PICOPT = @PICOPT@ +SHAREDLIB = @SHAREDLIB@ + +EXEEXT = @EXEEXT@ + +LIBS = -L$(top_builddir) -lsim -lucsimutil -lguiucsim -lcmd -lsim @LIBS@ +DL = @DL@ +dl_ok = @dl_ok@ + +prefix = @prefix@ +exec_prefix = @exec_prefix@ +bindir = @bindir@ +libdir = @libdir@ +datadir = @datadir@ +datarootdir = @datarootdir@ +includedir = @includedir@ +mandir = @mandir@ +man1dir = $(mandir)/man1 +man2dir = $(mandir)/man2 +infodir = @infodir@ +srcdir = @srcdir@ +VPATH = @srcdir@ + +OBJECTS_SHARED = glob.o itc.o serial.o rst.o timer.o port.o clk.o \ + uid.o bl.o flash.o \ + inst.o \ + simstm8.o stm8.o +OBJECTS_EXE = sstm8.o +OBJECTS = $(OBJECTS_SHARED) $(OBJECTS_EXE) + +STM8ASM = + +enable_dlso = @enable_dlso@ +dlso_ok = @dlso_ok@ + +#TEST_OBJ = test_bit.hex test_dis.hex test_mov.hex test_jmp.hex \ +# test_arith.hex + +# Compiling entire program or any subproject +# ------------------------------------------ +all: checkconf otherlibs stm8.src + +tests: $(TEST_OBJ) + + +# Compiling and installing everything and runing test +# --------------------------------------------------- +install: all installdirs + $(INSTALL) sstm8$(EXEEXT) $(DESTDIR)$(bindir)/`echo sstm8|sed '$(transform)'`$(EXEEXT) + $(STRIP) $(DESTDIR)$(bindir)/`echo sstm8|sed '$(transform)'`$(EXEEXT) + + +# Deleting all the installed files +# -------------------------------- +uninstall: + rm -f $(DESTDIR)$(bindir)/`echo sstm8|sed '$(transform)'`$(EXEEXT) + + +# Performing self-test +# -------------------- +check: test + +test: + + +# Performing installation test +# ---------------------------- +installcheck: + + +# Creating installation directories +# --------------------------------- +installdirs: + test -d $(DESTDIR)$(bindir) || $(INSTALL) -d $(DESTDIR)$(bindir) + + +# Creating dependencies +# --------------------- +dep: Makefile.dep + +Makefile.dep: $(srcdir)/*.cc $(srcdir)/*.h + $(MAKEDEP) $(CPPFLAGS) $(filter %.cc,$^) >Makefile.dep + +-include Makefile.dep +include $(srcdir)/clean.mk + +# My rules +# -------- +.SUFFIXES: .asm .hex + +stm8.src: sstm8$(EXEEXT) shared_lib + +sstm8$(EXEEXT): $(OBJECTS) $(top_builddir)/libcmd.a $(top_builddir)/libguiucsim.a $(top_builddir)/libsim.a $(top_builddir)/libucsimutil.a + $(CXX) $(CXXFLAGS) $(LDFLAGS) $(OBJECTS) $(LIBS) -o $@ + +ifeq ($(dlso_ok),yes) +shared_lib: $(top_builddir)/sstm8.so +else +shared_lib: + @$(top_srcdir)/mkecho $(top_builddir) "No stm8 shared lib made." + @$(top_srcdir)/mkecho $(top_builddir) "(SHAREDLIB="$(SHAREDLIB)",dl_ok="$(dl_ok)",enable_dlso="$(enable_dlso)")" +endif + +$(top_builddir)/sstm8.so: $(OBJECTS_SHARED) + $(CXX) -shared $(LDFLAGS) $(OBJECTS_SHARED) -o $(top_builddir)/sstm8.so + +otherlibs: $(top_builddir)/libcmd.a $(top_builddir)/libguiucsim.a $(top_builddir)/libsim.a $(top_builddir)/libucsimutil.a + +$(top_builddir)/libcmd.a: + $(MAKE) -C $(top_builddir)/cmd.src all + +$(top_builddir)/libguiucsim.a: + $(MAKE) -C $(top_builddir)/gui.src checkconf ucsim_lib + +$(top_builddir)/libsim.a: + $(MAKE) -C $(top_builddir)/sim.src all + +$(top_builddir)/libucsimutil.a: + $(MAKE) -C $(top_builddir) -f main.mk + +.cc.o: + $(CXX) $(CXXFLAGS) $(PICOPT) $(CPPFLAGS) $(TARGET_ARCH) -c $< -o $@ + +.asm.hex: + $(STM8ASM) -l $< -o $@ -e $<.lst + + +# Remaking configuration +# ---------------------- +checkconf: + @if [ -f $(top_builddir)/devel ]; then\ + $(MAKE) -C $(top_builddir) -f conf.mk srcdir="$(srcdir)" top_builddir="$(top_builddir)" freshconf;\ + fi + +#bl_l15x46.hex: bl_l15x46.asc +# $(SREC_CAT) $< -Ascii_Hex -Output $@ -Intel + +#bl_l15x46.cc: bl_l15x46.asc +# $(SREC_CAT) $< -Ascii_Hex -Output $@ -C-Array bl_l15x46 -INClude -No-CONST + +#bl_s105.hex: bl_s105.asc +# $(SREC_CAT) $< -Ascii_Hex -Output $@ -Intel + +#bl_s105.cc: bl_s105.asc +# $(SREC_CAT) $< -Ascii_Hex -Output $@ -C-Array bl_s105 -INClude -No-CONST + +#bl_source: bl.cc bl.h + +#bl.cc: bl_head.cc bl_l15x46.cc bl_s105.cc +# cat bl_head.cc bl_l15x46.cc bl_s105.cc|sed 's/unsigned char/t_mem/' >$@ + +#bl.h: bl_l15x46.h bl_s105.h +# cat bl_l15x46.h bl_s105.h|sed 's/unsigned char/t_mem/' >$@ + +# End of stm8.src/Makefile.in diff --git a/sim/ucsim/stm8.src/bl.cc b/sim/ucsim/stm8.src/bl.cc new file mode 100644 index 0000000..2f3365a --- /dev/null +++ b/sim/ucsim/stm8.src/bl.cc @@ -0,0 +1,370 @@ +#include "stypes.h" +#include "bl.h" +/* http://srecord.sourceforge.net/ */ +t_mem bl_l15x46[] = +{ +0x9B, 0xC6, 0x80, 0x00, 0xA1, 0x82, 0x27, 0x06, 0xA1, 0xAC, 0x27, 0x02, +0x20, 0x0C, 0xCE, 0x48, 0x0B, 0xA3, 0x55, 0xAA, 0x27, 0x04, 0xAC, 0x00, +0x80, 0x00, 0xC6, 0x48, 0x00, 0xA1, 0xAA, 0x27, 0x07, 0xCD, 0x64, 0x50, +0xAC, 0x00, 0x80, 0x00, 0x4F, 0xC7, 0x50, 0xC0, 0x72, 0x14, 0x50, 0x0D, +0x35, 0x56, 0x50, 0x52, 0x35, 0xAE, 0x50, 0x52, 0x35, 0xAE, 0x50, 0x53, +0x35, 0x56, 0x50, 0x53, 0x3F, 0x91, 0xAD, 0x71, 0x72, 0x06, 0x00, 0x91, +0x07, 0xCD, 0x64, 0x50, 0xAC, 0x00, 0x80, 0x00, 0xA6, 0x45, 0xCD, 0x64, +0x9F, 0xA6, 0x79, 0xAD, 0x45, 0x3F, 0x97, 0x9D, 0xCD, 0x61, 0x3C, 0xCD, +0x64, 0x50, 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long bl_l15x46_finish = 0x00006800; +unsigned long bl_l15x46_length = 0x00000800; + +#define BL_L15X46_TERMINATION 0x00000000 +#define BL_L15X46_START 0x00006000 +#define BL_L15X46_FINISH 0x00006800 +#define BL_L15X46_LENGTH 0x00000800 +/* http://srecord.sourceforge.net/ */ +t_mem bl_s105[] = +{ +0x9B, 0xC6, 0x80, 0x00, 0xA1, 0x82, 0x27, 0x06, 0xA1, 0xAC, 0x27, 0x02, +0x20, 0x0A, 0xCE, 0x48, 0x7E, 0xA3, 0x55, 0xAA, 0x27, 0x02, 0x20, 0x07, +0xC6, 0x48, 0x00, 0xA1, 0xAA, 0x26, 0x09, 0x5F, 0x4F, 0x4B, 0x28, 0x86, +0xAC, 0x00, 0x80, 0x00, 0xAD, 0x3B, 0x72, 0x10, 0x50, 0xC0, 0x4F, 0xC7, +0x50, 0xC6, 0xCD, 0x60, 0x76, 0x72, 0x1C, 0x50, 0x12, 0x3F, 0x8E, 0xA6, +0x01, 0xB7, 0x95, 0xCD, 0x60, 0xDD, 0x72, 0x06, 0x00, 0x8E, 0x02, 0x20, +0xD6, 0x35, 0x56, 0x50, 0x62, 0x35, 0xAE, 0x50, 0x62, 0x35, 0xAE, 0x50, +0x64, 0x35, 0x56, 0x50, 0x64, 0xA6, 0x79, 0xCD, 0x60, 0xA9, 0xCD, 0x61, +0xD1, 0x92, 0xAC, 0x00, 0x8A, 0x35, 0x55, 0x50, 0xE0, 0x35, 0x05, 0x50, +0xE1, 0x35, 0xAA, 0x50, 0xE0, 0x35, 0x7F, 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0x00000000 +#define BL_S105_START 0x00006000 +#define BL_S105_FINISH 0x00006800 +#define BL_S105_LENGTH 0x00000800 diff --git a/sim/ucsim/stm8.src/bl.h b/sim/ucsim/stm8.src/bl.h new file mode 100644 index 0000000..454265e --- /dev/null +++ b/sim/ucsim/stm8.src/bl.h @@ -0,0 +1,20 @@ +#ifndef BL_L15X46_H +#define BL_L15X46_H + +extern unsigned long bl_l15x46_termination; +extern unsigned long bl_l15x46_start; +extern unsigned long bl_l15x46_finish; +extern unsigned long bl_l15x46_length; +extern t_mem bl_l15x46[]; + +#endif /* BL_L15X46_H */ +#ifndef BL_S105_H +#define BL_S105_H + +extern unsigned long bl_s105_termination; +extern unsigned long bl_s105_start; +extern unsigned long bl_s105_finish; +extern unsigned long bl_s105_length; +extern t_mem bl_s105[]; + +#endif /* BL_S105_H */ diff --git a/sim/ucsim/stm8.src/bl.o b/sim/ucsim/stm8.src/bl.o Binary files differnew file mode 100644 index 0000000..0a00c2b --- /dev/null +++ b/sim/ucsim/stm8.src/bl.o diff --git a/sim/ucsim/stm8.src/bl_head.cc b/sim/ucsim/stm8.src/bl_head.cc new file mode 100644 index 0000000..7428e18 --- /dev/null +++ b/sim/ucsim/stm8.src/bl_head.cc @@ -0,0 +1,2 @@ +#include "stypes.h" +#include "bl.h" diff --git a/sim/ucsim/stm8.src/bl_l15x46.asc b/sim/ucsim/stm8.src/bl_l15x46.asc new file mode 100644 index 0000000..b683a50 --- /dev/null +++ b/sim/ucsim/stm8.src/bl_l15x46.asc @@ -0,0 +1,131 @@ + +$A6000, +9b c6 80 00 a1 82 27 06 a1 ac 27 02 20 0c ce 48 +0b a3 55 aa 27 04 ac 00 80 00 c6 48 00 a1 aa 27 +07 cd 64 50 ac 00 80 00 4f c7 50 c0 72 14 50 0d +35 56 50 52 35 ae 50 52 35 ae 50 53 35 56 50 53 +3f 91 ad 71 72 06 00 91 07 cd 64 50 ac 00 80 00 +a6 45 cd 64 9f a6 79 ad 45 3f 97 9d cd 61 3c cd +64 50 92 ac 00 8d 35 55 50 e0 35 05 50 e1 35 aa +50 e0 35 7f 50 d3 81 72 1a 50 c3 72 16 50 0d 72 +15 50 0d 72 16 52 35 72 14 52 35 72 18 52 34 72 +14 52 34 b6 95 c7 52 33 b6 94 c7 52 32 81 b7 90 +72 01 00 91 0f c6 52 30 b6 90 c7 52 31 72 0d 52 +30 fb 20 00 81 72 12 50 c3 a6 07 c7 52 8e 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+#define BL_L15X46_H + +extern unsigned long bl_l15x46_termination; +extern unsigned long bl_l15x46_start; +extern unsigned long bl_l15x46_finish; +extern unsigned long bl_l15x46_length; +extern unsigned char bl_l15x46[]; + +#endif /* BL_L15X46_H */ diff --git a/sim/ucsim/stm8.src/bl_l15x46.hex b/sim/ucsim/stm8.src/bl_l15x46.hex new file mode 100644 index 0000000..1d23923 --- /dev/null +++ b/sim/ucsim/stm8.src/bl_l15x46.hex @@ -0,0 +1,66 @@ +:020000040000FA +:206000009BC68000A1822706A1AC2702200CCE480BA355AA2704AC008000C64800A1AA2713 +:2060200007CD6450AC0080004FC750C07214500D3556505235AE505235AE5053355650533D +:206040003F91AD717206009107CD6450AC008000A645CD649FA679AD453F979DCD613CCD1F +:20606000645092AC008D355550E0350550E135AA50E0357F50D381721A50C37216500D721F +:2060800015500D72165235721452357218523472145234B695C75233B694C7523281B79062 +:2060A000720100910FC65230B690C75231720D5230FB200081721250C3A607C7528E7210EB +:2060C000528072015286FB4FC7528672105280202A7204500B21AE0460721050C35A2717EB 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/dev/null +++ b/sim/ucsim/stm8.src/bl_s105.cc @@ -0,0 +1,184 @@ +/* http://srecord.sourceforge.net/ */ +unsigned char bl_s105[] = +{ +0x9B, 0xC6, 0x80, 0x00, 0xA1, 0x82, 0x27, 0x06, 0xA1, 0xAC, 0x27, 0x02, +0x20, 0x0A, 0xCE, 0x48, 0x7E, 0xA3, 0x55, 0xAA, 0x27, 0x02, 0x20, 0x07, +0xC6, 0x48, 0x00, 0xA1, 0xAA, 0x26, 0x09, 0x5F, 0x4F, 0x4B, 0x28, 0x86, +0xAC, 0x00, 0x80, 0x00, 0xAD, 0x3B, 0x72, 0x10, 0x50, 0xC0, 0x4F, 0xC7, +0x50, 0xC6, 0xCD, 0x60, 0x76, 0x72, 0x1C, 0x50, 0x12, 0x3F, 0x8E, 0xA6, +0x01, 0xB7, 0x95, 0xCD, 0x60, 0xDD, 0x72, 0x06, 0x00, 0x8E, 0x02, 0x20, +0xD6, 0x35, 0x56, 0x50, 0x62, 0x35, 0xAE, 0x50, 0x62, 0x35, 0xAE, 0x50, +0x64, 0x35, 0x56, 0x50, 0x64, 0xA6, 0x79, 0xCD, 0x60, 0xA9, 0xCD, 0x61, +0xD1, 0x92, 0xAC, 0x00, 0x8A, 0x35, 0x55, 0x50, 0xE0, 0x35, 0x05, 0x50, +0xE1, 0x35, 0xAA, 0x50, 0xE0, 0x35, 0x7F, 0x50, 0xD1, 0x81, 0xA6, 0x42, +0xC7, 0x52, 0x01, 0x72, 0x1F, 0x50, 0x0D, 0x72, 0x1E, 0x50, 0x0E, 0x4F, +0xC7, 0x52, 0x02, 0xA6, 0x40, 0xC7, 0x52, 0x00, 0x81, 0x72, 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b/sim/ucsim/stm8.src/bl_s105.h new file mode 100644 index 0000000..b600f17 --- /dev/null +++ b/sim/ucsim/stm8.src/bl_s105.h @@ -0,0 +1,10 @@ +#ifndef BL_S105_H +#define BL_S105_H + +extern unsigned long bl_s105_termination; +extern unsigned long bl_s105_start; +extern unsigned long bl_s105_finish; +extern unsigned long bl_s105_length; +extern unsigned char bl_s105[]; + +#endif /* BL_S105_H */ diff --git a/sim/ucsim/stm8.src/bl_s105.hex b/sim/ucsim/stm8.src/bl_s105.hex new file mode 100644 index 0000000..a2912f4 --- /dev/null +++ b/sim/ucsim/stm8.src/bl_s105.hex @@ -0,0 +1,66 @@ +:020000040000FA +:206000009BC68000A1822706A1AC2702200ACE487EA355AA27022007C64800A1AA26095F42 +:206020004F4B2886AC008000AD3B721050C04FC750C6CD6076721C50123F8EA601B795CD26 +:2060400060DD7206008E0220D63556506235AE506235AE506435565064A679CD60A9CD613A +:20606000D192AC008A355550E0350550E135AA50E0357F50D181A642C75201721F500D729B +:206080001E500E4FC75202A640C7520081721D50127216524572145245721A52499DB69261 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----------------------------------------------------------------- +distclean: clean + rm -f config.cache config.log config.status + rm -f Makefile *.dep + + +# Like clean but some files may still exist +# ----------------------------------------- +mostlyclean: clean + + +# Deleting everything that can reconstructed by this Makefile. It deletes +# everything deleted by distclean plus files created by bison, etc. +# ----------------------------------------------------------------------- +realclean: distclean + +# End of stm8.src/clean.mk diff --git a/sim/ucsim/stm8.src/clk.cc b/sim/ucsim/stm8.src/clk.cc new file mode 100644 index 0000000..7b2804e --- /dev/null +++ b/sim/ucsim/stm8.src/clk.cc @@ -0,0 +1,316 @@ +/* + * Simulator of microcontrollers (stm8.src/clk.cc) + * + * Copyright (C) 2017,17 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#include "stm8cl.h" + +#include "clkcl.h" + + +cl_clk::cl_clk(class cl_uc *auc): + cl_hw(auc, HW_CLOCK, 0, "clk") +{ + base= 0x50C0; + ckdivr= NULL; + pckenr1= NULL; + pckenr2= NULL; + pckenr3= NULL; +} + +int +cl_clk::init(void) +{ + cl_hw::init(); + + make_partner(HW_TIMER, 1); + make_partner(HW_TIMER, 2); + make_partner(HW_TIMER, 3); + make_partner(HW_TIMER, 4); + make_partner(HW_TIMER, 5); + make_partner(HW_TIMER, 6); + + make_partner(HW_UART, 1); + make_partner(HW_UART, 2); + make_partner(HW_UART, 3); + make_partner(HW_UART, 4); + + return 0; +} + +void +cl_clk::write(class cl_memory_cell *cell, t_mem *val) +{ + cl_clk_event e; + hw_event ev; + + if ((cell == pckenr1) || + (cell == pckenr2) || + (cell == pckenr3)) + { + cell->set(*val); + + e.set(HW_TIMER, 1); + ev= tim(e.id)?EV_CLK_ON:EV_CLK_OFF; + inform_partners(ev, &e); + + e.id= 2; + ev= tim(e.id)?EV_CLK_ON:EV_CLK_OFF; + inform_partners(ev, &e); + + e.id= 3; + ev= tim(e.id)?EV_CLK_ON:EV_CLK_OFF; + inform_partners(ev, &e); + + e.id= 4; + ev= tim(e.id)?EV_CLK_ON:EV_CLK_OFF; + inform_partners(ev, &e); + + e.id= 5; + ev= tim(e.id)?EV_CLK_ON:EV_CLK_OFF; + inform_partners(ev, &e); + + e.id= 6; + ev= tim(e.id)?EV_CLK_ON:EV_CLK_OFF; + inform_partners(ev, &e); + + e.set(HW_UART, 1); + ev= usart(e.id)?EV_CLK_ON:EV_CLK_OFF; + inform_partners(ev, &e); + + e.id= 2; + ev= usart(e.id)?EV_CLK_ON:EV_CLK_OFF; + inform_partners(ev, &e); + + e.id= 3; + ev= usart(e.id)?EV_CLK_ON:EV_CLK_OFF; + inform_partners(ev, &e); + + e.id= 4; + ev= usart(e.id)?EV_CLK_ON:EV_CLK_OFF; + inform_partners(ev, &e); + } +} + + +/* SAF */ + +cl_clk_saf::cl_clk_saf(class cl_uc *auc): + cl_clk(auc) +{ +} + +int +cl_clk_saf::init(void) +{ + cl_clk::init(); + ckdivr= register_cell(uc->rom, base+6); + pckenr1= register_cell(uc->rom, base+7); + pckenr2= register_cell(uc->rom, base+10); + return 0; +} + +void +cl_clk_saf::reset(void) +{ + //ickr->write(0x01); + //eckr->write(0); + //cmsr->write(0xe1); + //swr->write(0xe1); + //swcr->write(0); + ckdivr->write(0x18); + pckenr1->write(0xff); + //cssr->write(0); + //ccor->write(0); + pckenr2->write(0xff); + //hsitrimr->write(0); + //swimccr->write(0); +} + +bool +cl_clk_saf::tim(int id) +{ + switch (id) + { + case 1: + return pckenr1 && (pckenr1->get() & 0x80); + case 2: case 5: + return pckenr1 && (pckenr1->get() & 0x20); + case 3: + return pckenr1 && (pckenr1->get() & 0x40); + case 4: case 6: + return pckenr1 && (pckenr1->get() & 0x10); + } + return false; +} + +bool +cl_clk_saf::usart(int id) +{ + cl_stm8 *u= (cl_stm8 *)uc; + if (id == 1) + switch (u->type->subtype) + { + case DEV_STM8S003: case DEV_STM8S103: case DEV_STM8S903: + return pckenr1 && (pckenr1->get() & 0x08); + case DEV_STM8S007: case DEV_STM8S207: case DEV_STM8S208: + case DEV_STM8AF52: + return pckenr1 && (pckenr1->get() & 0x04); + } + else if (id == 2) + switch (u->type->subtype) + { + case DEV_STM8S005: case DEV_STM8S105: case DEV_STM8AF62_46: + return pckenr1 && (pckenr1->get() & 0x08); + } + else if (id == 3) + switch (u->type->subtype) + { + case DEV_STM8S007: case DEV_STM8S207: case DEV_STM8S208: + case DEV_STM8AF52: + return pckenr1 && (pckenr1->get() & 0x08); + } + else if (id == 4) + switch (u->type->subtype) + { + case DEV_STM8AF62_12: + return pckenr1 && (pckenr1->get() & 0x08); + } + return false; +} + +/* ALL */ + +cl_clk_all::cl_clk_all(class cl_uc *auc): + cl_clk(auc) +{ +} + +int +cl_clk_all::init(void) +{ + cl_clk::init(); + ckdivr= register_cell(uc->rom, base+0); + pckenr1= register_cell(uc->rom, base+3); + pckenr2= register_cell(uc->rom, base+4); + pckenr3= register_cell(uc->rom, base+16); + return 0; +} + +void +cl_clk_all::reset(void) +{ + ckdivr->write(3); + pckenr1->write(0); + pckenr2->write(0x80); + pckenr3->write(0); +} + +bool +cl_clk_all::tim(int id) +{ + switch (id) + { + case 1: + return pckenr2 && (pckenr2->get() & 0x02); + case 2: + return pckenr1 && (pckenr1->get() & 0x01); + case 3: + return pckenr1 && (pckenr1->get() & 0x02); + case 4: + return pckenr1 && (pckenr1->get() & 0x04); + case 5: + return pckenr3 && (pckenr3->get() & 0x02); + } + return false; +} + +bool +cl_clk_all::usart(int id) +{ + switch (id) + { + case 1: + return pckenr1 && (pckenr1->get() & 0x20); + case 2: + return pckenr3 && (pckenr3->get() & 0x08); + case 3: + return pckenr3 && (pckenr3->get() & 0x10); + } + return false; +} + + +/* L101 */ + +cl_clk_l101::cl_clk_l101(class cl_uc *auc): + cl_clk(auc) +{ +} + +int +cl_clk_l101::init(void) +{ + cl_clk::init(); + ckdivr= register_cell(uc->rom, base+0); + pckenr1= register_cell(uc->rom, base+3); + return 0; +} + +void +cl_clk_l101::reset(void) +{ + ckdivr->write(3); + pckenr1->write(0); +} + +bool +cl_clk_l101::tim(int id) +{ + switch (id) + { + case 2: + return pckenr1 && (pckenr1->get() & 0x01); + case 3: + return pckenr1 && (pckenr1->get() & 0x02); + case 4: + return pckenr1 && (pckenr1->get() & 0x04); + } + return false; +} + +bool +cl_clk_l101::usart(int id) +{ + switch (id) + { + case 1: + return pckenr1 && (pckenr1->get() & 0x20); + } + return false; +} + + +/* End of stm8.src/clk.cc */ diff --git a/sim/ucsim/stm8.src/clk.o b/sim/ucsim/stm8.src/clk.o Binary files differnew file mode 100644 index 0000000..3bcdb13 --- /dev/null +++ b/sim/ucsim/stm8.src/clk.o diff --git a/sim/ucsim/stm8.src/clkcl.h b/sim/ucsim/stm8.src/clkcl.h new file mode 100644 index 0000000..e3a285a --- /dev/null +++ b/sim/ucsim/stm8.src/clkcl.h @@ -0,0 +1,104 @@ +/* + * Simulator of microcontrollers (stm8.src/clkcl.h) + * + * Copyright (C) 2017,17 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#ifndef CLKCL_HEADER +#define CLKCL_HEADER + +#include "hwcl.h" + +class cl_clk_event: public cl_base +{ + public: + enum hw_cath cath; + int id; + cl_clk_event(void): cl_base() {} + cl_clk_event(enum hw_cath acath, int aid): cl_base() + { cath= acath; id= aid; } + virtual void set(enum hw_cath acath, int aid) + { cath= acath; id= aid; } +}; + +class cl_clk: public cl_hw +{ + protected: + t_addr base; + class cl_memory_cell + *ckdivr, + *pckenr1, + *pckenr2, + *pckenr3; + public: + cl_clk(class cl_uc *auc); + virtual int init(void); + + virtual void write(class cl_memory_cell *cell, t_mem *val); + virtual bool tim(int id) { return false; } + virtual bool usart(int id) { return false; } + + virtual void reset(void) {} +}; + +class cl_clk_saf: public cl_clk +{ + public: + cl_clk_saf(class cl_uc *auc); + virtual int init(void); + + virtual void reset(void); + + virtual bool tim(int id); + virtual bool usart(int id); +}; + +class cl_clk_all: public cl_clk +{ + public: + cl_clk_all(class cl_uc *auc); + virtual int init(void); + + virtual void reset(void); + + virtual bool tim(int id); + virtual bool usart(int id); +}; + +class cl_clk_l101: public cl_clk +{ + public: + cl_clk_l101(class cl_uc *auc); + virtual int init(void); + + virtual void reset(void); + + virtual bool tim(int id); + virtual bool usart(int id); +}; + + +#endif + +/* End of stm8.src/clkcl.h */ diff --git a/sim/ucsim/stm8.src/conf.mk b/sim/ucsim/stm8.src/conf.mk new file mode 100644 index 0000000..6f4c0e3 --- /dev/null +++ b/sim/ucsim/stm8.src/conf.mk @@ -0,0 +1,10 @@ +# +# Makefile targets to remake configuration +# + +freshconf: Makefile + +Makefile: $(srcdir)/Makefile.in $(top_srcdir)/configure.ac + cd $(top_builddir) && $(SHELL) ./config.status + +# End of stm8.src/conf.mk diff --git a/sim/ucsim/stm8.src/flash.cc b/sim/ucsim/stm8.src/flash.cc new file mode 100644 index 0000000..74e2150 --- /dev/null +++ b/sim/ucsim/stm8.src/flash.cc @@ -0,0 +1,611 @@ +/* + * Simulator of microcontrollers (stm8.src/flash.cc) + * + * Copyright (C) 2017,17 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#include <stdlib.h> + +#include "globals.h" + +#include "stm8cl.h" + +#include "flashcl.h" + + +/* Address space/cell which can contain flash memory */ + +t_mem +cl_flash_cell::write(t_mem val) +{ + if (flags & CELL_READ_ONLY) + { + class cl_stm8 *uc= (cl_stm8 *)(application->get_uc()); + if (uc) + { + t_addr a; + if (uc->rom->is_owned(this, &a) && + uc->flash_ctrl) + { + uc->flash_ctrl->flash_write(a, val); + return d(); + } + } + } + return cl_cell8::write(val); +} + +cl_flash_as::cl_flash_as(const char *id, t_addr astart, t_addr asize): + cl_address_space(id, astart, asize, 8) +{ + class cl_flash_cell c8(8); + class cl_memory_cell *cell= &c8; + start_address= astart; + decoders= new cl_decoder_list(2, 2, false); + cella= (class cl_memory_cell *)malloc(size * sizeof(class cl_memory_cell)); + //cell->init(); + int i; + for (i= 0; i < size; i++) + { + void *p= &(cella[i]); + memcpy(p, cell, sizeof(class cl_memory_cell)); + cella[i].init(); + } + dummy= new cl_dummy_cell(8); + dummy->init(); +} + +int +cl_flash_as::init(void) +{ + return cl_address_space::init(); +} + + +/* Flash controller */ + +cl_flash::cl_flash(class cl_uc *auc, t_addr abase, const char *aname): + cl_hw(auc, HW_FLASH, 0, aname) +{ + base= abase; + set_name(aname); + wbuf_started= false; + wbuf_start= 0; + rww= true; +} + +int +cl_flash::init(void) +{ + cl_hw::init(); + registration(); + reset(); + return 0; +} + +char * +cl_flash::cfg_help(t_addr addr) +{ + switch (addr) + { + case stm8_flash_on: return (char*)"Turn simulation of flash on/off (bool, RW)"; + } + return (char*)"Not used"; +} + +int +cl_flash::tick(int cycles) +{ + if (state & fs_busy) + { + double now= uc->get_rtime(); + double elapsed= (now - start_time) * 10e6; + + if ((state == fs_pre_erase) && + (elapsed > tprog/2.0)) + { + int i; + uc->sim->app->debug("FLASH zeroing %06lx .. %d\n", wbuf_start, wbuf_size); + for (i= 0; i < wbuf_size; i++) + { + class cl_memory_cell *c= uc->rom->get_cell(wbuf_start + i); + c->download(0); + } + if (mode == fm_erase) + { + uc->sim->app->debug("FLASH end of erase, finish\n"); + finish_program(true); + } + else + { + uc->sim->app->debug("FLASH end of erase, cont program\n"); + state= fs_program; + } + } + else if (elapsed > tprog) + { + int i; + uc->sim->app->debug("FLASH dl-ing %06lx .. %d\n", wbuf_start, wbuf_size); + for (i= 0; i < wbuf_size; i++) + { + class cl_memory_cell *c= uc->rom->get_cell(wbuf_start + i); + t_mem org= c->get(); + c->download(org | wbuf[i]); + } + uc->sim->app->debug("FLASH end of program\n"); + finish_program(true); + } + } + return 0; +} + +void +cl_flash::finish_program(bool ok) +{ + if (ok) + iapsr->set_bit1(0x04); + else + iapsr->set_bit1(0x01); + state= fs_wait_mode; +} + +void +cl_flash::reset(void) +{ + uc->sim->app->debug("FLASH reset\n"); + puk1st= false; + duk1st= false; + p_unlocked= false; + d_unlocked= false; + p_failed= false; + d_failed= false; + + state= fs_wait_mode; + mode= fm_unknown; + + cr1r->write(0); + iapsr->write(0x40); + cr2r->write(0); + if (ncr2r) + ncr2r->write(0xff); +} + +t_mem +cl_flash::read(class cl_memory_cell *cell) +{ + t_mem v= cell->get(); + + if (cell == pukr) + v= 0; + else if (cell == dukr) + v= 0; + else if (cell == iapsr) + { + v&= ~0x0a; + if (p_unlocked) + v|= 0x02; + if (d_unlocked) + v|= 0x08; + // read clears EOP and WR_PG_DIS bits + cell->set(v & ~0x05); + if (v & 0x05) uc->sim->app->debug("FLASH read iapsr5 %02x\n",v); + } + return v; +} + +void +cl_flash::write(class cl_memory_cell *cell, t_mem *val) +{ + if (conf(cell, val)) + return; + + if (conf(cell, NULL)) + return; + + if (cell == pukr) + { + uc->sim->app->debug("FLASH write-pukr %02x\n",*val); + if (p_failed) + ; + else if (!puk1st) + { + if (*val == PMASS1) + puk1st= true; + else + p_failed= true; + } + else + { + if (*val == PMASS2) + puk1st= false, p_unlocked= true; + else + puk1st= false, p_failed= true; + } + *val= 0; + } + else if (cell == dukr) + { + uc->sim->app->debug("FLASH write-dukr %02x\n",*val); + if (d_failed) + ; + else if (!duk1st) + { + if (*val == DMASS1) + duk1st= true; + else + d_failed= true; + } + else + { + if (*val == DMASS2) + duk1st= false, d_unlocked= true; + else + duk1st= false, d_failed= true; + } + *val= 0; + } + else if (cell == iapsr) + { + uc->sim->app->debug("FLASH write-iapsr %02x\n",*val); + t_mem org= iapsr->get(); + // PUL, DUL + if (!(*val & 0x02)) + p_unlocked= puk1st= false; + if (!(*val & 0x08)) + d_unlocked= duk1st= false; + *val&= ~0x0a; + if (p_unlocked) + *val|= 0x02; + if (d_unlocked) + *val|= 0x08; + // HVOFF + *val&= ~0x40; + // EOP + *val&= 0x40; + if (org & 0x40) + *val|= 0x40; + } + else if (cell == cr2r) + { + uc->sim->app->debug("FLASH write-cr2r %02x\n",*val); + *val&= ~0x0e; + if (state & fs_busy) + { + *val&= ~0x30; + *val|= (cr2r->get() & 0x30); + } + if ((ncr2r == NULL) || + (ncr2r->get() == ((~(*val))&0xff))) + set_flash_mode(*val); + } + else if ((ncr2r != NULL) && + (cell == ncr2r)) + { + uc->sim->app->debug("FLASH write-ncr2r %02x\n",*val); + *val|= 0x0e; + if (state & fs_busy) + { + *val&= ~0x30; + *val|= (ncr2r->get() & 0x30); + } + if (cr2r->get() == ((~(*val))&0xff)) + set_flash_mode((~(*val))&0xff); + } +} + +t_mem +cl_flash::conf_op(cl_memory_cell *cell, t_addr addr, t_mem *val) +{ + switch ((enum stm8_flash_cfg)addr) + { + case stm8_flash_on: + if (val) + { + if (*val) + on= true; + else + on= false; + } + else + cell->set(on?1:0); + break; + case stm8_flash_nuof_cfg: + break; + } + return cell->get(); +} + +void +cl_flash::flash_write(t_addr a, t_mem val) +{ + uc->sim->app->debug("FLASH wr(%06lx,%02x)\n",a,val); + if (!uc) + { + uc->sim->app->debug(" no uc\n"); + return; + } + if (uc->rom == NULL) + { + uc->sim->app->debug(" no rom\n"); + return; + } + if ((a >= 0x8000) && + !p_unlocked) + { + uc->sim->app->debug(" plocked\n"); + return; + } + if ((a < 0x8000) && + !d_unlocked) + { + uc->sim->app->debug(" dlocked\n"); + return; + } + if (state & fs_busy) + { + uc->sim->app->debug(" busy %d\n",state); + return; + } + + uc->sim->app->debug(" wbuf_start=%06lx\n",wbuf_start); + if (wbuf_start == 0) + { + uc->sim->app->debug(" calling start_wbuf(%06lx)\n",a); + start_wbuf(a); + } + + int offset= a - wbuf_start; + uc->sim->app->debug(" offset=%d\n",offset); + if (mode == fm_byte) + { + // fixup tprog + wbuf[0]= uc->rom->get(wbuf_start + 0); + wbuf[1]= uc->rom->get(wbuf_start + 1); + wbuf[2]= uc->rom->get(wbuf_start + 2); + wbuf[3]= uc->rom->get(wbuf_start + 3); + if (tprog < 6000) + { + if (wbuf[0] || + wbuf[1] || + wbuf[2] || + wbuf[3]) + tprog= 6000; + } + wbuf[offset]= val; + if (tprog < 6000) + start_program(fs_program); + } + else if (mode == fm_erase) + { + uc->sim->app->debug(" romwrite in erase mode\n"); + wbuf[offset]= val; + wbuf_writes++; + if ((wbuf_writes == 4) && + (((a+1) % 4) == 0)) + { + u8_t v= 0; + v|= wbuf[0]; + v|= wbuf[1]; + v|= wbuf[2]; + v|= wbuf[3]; + if (v == 0) + { + uc->sim->app->debug(" starting erase\n"); + start_program(fs_pre_erase); + } + } + } + else + { + wbuf[offset]= val; + wbuf_started= true; + wbuf_writes++; + if ((wbuf_writes == wbuf_size) || + (offset == wbuf_size-1)) + { + if ((mode == fm_fast_word) || + (mode == fm_fast_block)) + start_program(fs_program); + else + start_program(fs_pre_erase); + } + } +} + +// normal program: 6 ms +// fast program: 3 ms +// erase: 3 ms + +void +cl_flash::set_flash_mode(t_mem cr2val) +{ + bool fix= cr1r->get() & 0x01; /* FIX */ + + uc->sim->app->debug("FLASH set_mode %02x\n", cr2val); + if (cr2val & 0x40 /* WPRG */ ) + { + mode= fm_word; + tprog= 6000; /* normal mode */ + wbuf_size= 4; + } + else if (cr2val & 0x20 /* ERASE */ ) + { + mode= fm_erase; + tprog= 3000; + wbuf_size= 128; + } + else if (cr2val & 0x10 /* FPRG */ ) + { + mode= fm_fast_block; + tprog= 3000; + wbuf_size= 128; + } + else if (cr2val & 0x01 /* PRG */ ) + { + mode= fm_block; + tprog= 6000; + wbuf_size= 128; + } + else + { + mode= fm_byte; + tprog= fix?6000:3000; + wbuf_size= 4; + } + state= fs_wait_data; + wbuf_started= false; + wbuf_start= 0; +} + +void +cl_flash::start_wbuf(t_addr addr) +{ + int i; + wbuf_start= addr - (addr % wbuf_size); + wbuf_writes= 0; + for (i= 0; i < 256; i++) + wbuf[i]= 0; + uc->sim->app->debug("FLASH start_wbuf %06lx (wbuf_start=%06lx,size=%d)\n", addr, wbuf_start, wbuf_size); +} + +void +cl_flash::start_program(enum stm8_flash_state start_state) +{ + uc->sim->app->debug("FLASH start prg %d\n", start_state); + state= start_state; + start_time= uc->get_rtime(); +} + +const char * +cl_flash::state_name(enum stm8_flash_state s) +{ + switch (s) + { + case fs_wait_mode: return "wait_mode"; + case fs_wait_data: return "wait_data"; + case fs_pre_erase: return "erase"; + case fs_program: return "program"; + case fs_busy: return "busy"; + } + return "unknown"; +} + +void +cl_flash::print_info(class cl_console_base *con) +{ + con->dd_printf(chars("", "Flash at %s\n", uc->rom->addr_format), base); + con->dd_printf("PUK: "); + if (p_failed) + con->dd_printf("fail"); + else if (p_unlocked) + con->dd_printf("unlocked"); + else if (puk1st) + con->dd_printf("MASS1"); + else + con->dd_printf("locked"); + con->dd_printf("\n"); + + con->dd_printf("DUK: "); + if (d_failed) + con->dd_printf("fail"); + else if (d_unlocked) + con->dd_printf("unlocked"); + else if (duk1st) + con->dd_printf("MASS1"); + else + con->dd_printf("locked"); + con->dd_printf("\n"); + + con->dd_printf("State: %s\n", state_name(state)); + print_cfg_info(con); +} + + +/* SAF */ + +cl_saf_flash::cl_saf_flash(class cl_uc *auc, t_addr abase): + cl_flash(auc, abase, "flash") +{ +} + +void +cl_saf_flash::registration(void) +{ + class cl_it_src *is; + + cr1r= register_cell(uc->rom, base+0); + cr2r= register_cell(uc->rom, base+1); + ncr2r= register_cell(uc->rom, base+2); + iapsr= register_cell(uc->rom, base+5); + pukr= register_cell(uc->rom, base+8); + dukr= register_cell(uc->rom, base+10); + + uc->it_sources->add(is= new cl_it_src(uc, 24, + cr1r,0x02, + iapsr,0x04, + 0x8008+24*4, false, false, + chars("end of flash programming"), 20*20+0)); + uc->it_sources->add(is= new cl_it_src(uc, 24, + cr1r,0x02, + iapsr,0x01, + 0x8008+24*4, false, false, + chars("write attempted to protected page"), 20*20+1)); + is->init(); +} + + +/* L,L101 */ + +cl_l_flash::cl_l_flash(class cl_uc *auc, t_addr abase): + cl_flash(auc, abase, "flash") +{ +} + +void +cl_l_flash::registration(void) +{ + class cl_it_src *is; + + cr1r= register_cell(uc->rom, base+0); + cr2r= register_cell(uc->rom, base+1); + pukr= register_cell(uc->rom, base+2); + dukr= register_cell(uc->rom, base+3); + iapsr= register_cell(uc->rom, base+4); + ncr2r= NULL; + + uc->it_sources->add(is= new cl_it_src(uc, 1, + cr1r,0x02, + iapsr,0x04, + 0x8008+1*4, false, false, + chars("end of flash programming"), 20*20+0)); + uc->it_sources->add(is= new cl_it_src(uc, 1, + cr1r,0x02, + iapsr,0x01, + 0x8008+1*4, false, false, + chars("write attempted to protected page"), 20*20+1)); + is->init(); +} + + +/* End of stm8.src/flash.cc */ diff --git a/sim/ucsim/stm8.src/flash.o b/sim/ucsim/stm8.src/flash.o Binary files differnew file mode 100644 index 0000000..0da1141 --- /dev/null +++ b/sim/ucsim/stm8.src/flash.o diff --git a/sim/ucsim/stm8.src/flashcl.h b/sim/ucsim/stm8.src/flashcl.h new file mode 100644 index 0000000..3d341ef --- /dev/null +++ b/sim/ucsim/stm8.src/flashcl.h @@ -0,0 +1,137 @@ +/* + * Simulator of microcontrollers (stm8.src/flashcl.h) + * + * Copyright (C) 2017,17 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#ifndef FLASHCL_HEADER +#define FLASHCL_HEADER + +#include "hwcl.h" +#include "memcl.h" + + +/* Special memory/address space to handle flash ops */ + +class cl_flash_cell: public cl_cell8 +{ + public: + cl_flash_cell(uchar awidth): cl_cell8(awidth) {} + virtual t_mem write(t_mem val); +}; + +class cl_flash_as: public cl_address_space +{ + public: + cl_flash_as(const char *id, t_addr astart, t_addr asize); + virtual int init(void); +}; + +enum stm8_flash_cfg { + stm8_flash_on= 0, + stm8_flash_nuof_cfg= 1 +}; + +enum stm8_mass { + PMASS1= 0x56, + PMASS2= 0xae, + DMASS1= 0xae, + DMASS2= 0x56 +}; + +enum stm8_flash_state { + fs_wait_mode= 0x00, + fs_wait_data= 0x01, + fs_pre_erase= 0x02, + fs_program= 0x04, + fs_busy= fs_pre_erase|fs_program +}; + +enum stm8_flash_mode { + fm_unknown= 0, + fm_byte= 1, + fm_word= 2, + fm_fast_word= 3, + fm_block= 4, + fm_fast_block= 5, + fm_erase= 6 +}; + +class cl_flash: public cl_hw +{ + protected: + t_addr base; + cl_memory_cell *cr1r, *cr2r, *ncr2r, *pukr, *dukr, *iapsr; + bool puk1st, duk1st; + bool p_unlocked, d_unlocked; + bool p_failed, d_failed; + u8_t wbuf[256]; /* buffer of block */ + bool wbuf_started; /* any writes happened to block */ + int wbuf_size; /* block size */ + int wbuf_writes; /* nr of writes to block */ + t_addr wbuf_start; /* start address of block */ + bool rww; + enum stm8_flash_state state; + enum stm8_flash_mode mode; + double tprog; /* programing time in usec */ + double start_time; + public: + cl_flash(class cl_uc *auc, t_addr abase, const char *aname); + virtual int init(void); + virtual void registration(void) {} + virtual int tick(int cycles); + virtual void reset(void); + + virtual t_mem read(class cl_memory_cell *cell); + virtual void write(class cl_memory_cell *cell, t_mem *val); + virtual t_mem conf_op(cl_memory_cell *cell, t_addr addr, t_mem *val); + virtual char *cfg_help(t_addr addr); + + virtual void flash_write(t_addr a, t_mem val); + virtual void set_flash_mode(t_mem cr2val); + virtual void start_wbuf(t_addr addr); + virtual void start_program(enum stm8_flash_state start_state); + virtual void finish_program(bool ok); + + virtual const char *state_name(enum stm8_flash_state s); + virtual void print_info(class cl_console_base *con); +}; + +class cl_saf_flash: public cl_flash +{ + public: + cl_saf_flash(class cl_uc *auc, t_addr abase); + virtual void registration(void); +}; + +class cl_l_flash: public cl_flash +{ + public: + cl_l_flash(class cl_uc *auc, t_addr abase); + virtual void registration(void); +}; + +#endif + +/* End of stm8.src/flashcl.h */ diff --git a/sim/ucsim/stm8.src/glob.cc b/sim/ucsim/stm8.src/glob.cc new file mode 100644 index 0000000..5ae7705 --- /dev/null +++ b/sim/ucsim/stm8.src/glob.cc @@ -0,0 +1,782 @@ +/* + * Simulator of microcontrollers (glob.cc) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#include <stdio.h> + +#include "stypes.h" + +/* STM8 instructions described in PM0044 + * + * 22.10.2011 - table is complete, can be checked for correctness + * + */ + + +/* +%d - direct addressing +%x - extended addressing +%p - pc relative addressing +%b - unsigned byte immediate addressing +%w - unsigned word immediate addressing +%e - unsigned 24bit immediate addressing (extmem) +%s - signed byte immediate +%1 - unsigned byte index offset +%2 - unsigned word index offset +%3 - unsigned 24bit index offset +*/ + +/* uint code, mask; char branch; uchar length; char *mnemonic; */ + +struct dis_entry disass_stm8[]= { + { 0x0019, 0x00ff, ' ', 2, "adc A,(%1,SP)" }, + { 0x00a9, 0x00ff, ' ', 2, "adc A,%b" }, + { 0x00b9, 0x00ff, ' ', 2, "adc A,%d" }, + { 0x00c9, 0x00ff, ' ', 3, "adc A,%x" }, + { 0x00d9, 0x00ff, ' ', 3, "adc A,(%2,X)" }, + { 0x00e9, 0x00ff, ' ', 2, "adc A,(%1,X)" }, + { 0x00f9, 0x00ff, ' ', 1, "adc A,(X)" }, + + { 0x001b, 0x00ff, ' ', 2, "add A,(%1,SP)" }, + { 0x00ab, 0x00ff, ' ', 2, "add A,%b" }, + { 0x00bb, 0x00ff, ' ', 2, "add A,%d" }, + { 0x00cb, 0x00ff, ' ', 3, "add A,%x" }, + { 0x00db, 0x00ff, ' ', 3, "add A,(%2,X)" }, + { 0x00eb, 0x00ff, ' ', 2, "add A,(%1,X)" }, + { 0x00fb, 0x00ff, ' ', 1, "add A,(X)" }, + { 0x005b, 0x00ff, ' ', 2, "add SP,%b" }, + + { 0x001c, 0x00ff, ' ', 3, "addw X,%w" }, + + { 0x0014, 0x00ff, ' ', 2, "and A,(%1,SP)" }, + { 0x00a4, 0x00ff, ' ', 2, "and A,%b" }, + { 0x00b4, 0x00ff, ' ', 2, "and A,%d" }, + { 0x00c4, 0x00ff, ' ', 3, "and A,%x" }, + { 0x00d4, 0x00ff, ' ', 3, "and A,(%2,X)" }, + { 0x00e4, 0x00ff, ' ', 2, "and A,(%1,X)" }, + { 0x00f4, 0x00ff, ' ', 1, "and A,(X)" }, + + { 0x0015, 0x00ff, ' ', 2, "bcp A,(%1,SP)" }, + { 0x00a5, 0x00ff, ' ', 2, "bcp A,%b" }, + { 0x00b5, 0x00ff, ' ', 2, "bcp A,%d" }, + { 0x00c5, 0x00ff, ' ', 3, "bcp A,%x" }, + { 0x00d5, 0x00ff, ' ', 3, "bcp A,(%2,X)" }, + { 0x00e5, 0x00ff, ' ', 2, "bcp A,(%1,X)" }, + { 0x00f5, 0x00ff, ' ', 1, "bcp A,(X)" }, + + { 0x00cd, 0x00ff, ' ', 3, "call %x", true }, + { 0x00dd, 0x00ff, ' ', 3, "call (%2,X)", true }, + { 0x00ed, 0x00ff, ' ', 2, "call (%1,X)", true }, + { 0x00fd, 0x00ff, ' ', 1, "call (X)", true }, + { 0x008d, 0x00ff, ' ', 4, "callf %e", true }, + { 0x00ad, 0x00ff, ' ', 2, "callr %p", true }, + + { 0x008c, 0x00ff, ' ', 1, "ccf" }, + + { 0x000f, 0x00ff, ' ', 2, "clr (%1,SP)" }, + { 0x003f, 0x00ff, ' ', 2, "clr %d" }, + { 0x004f, 0x00ff, ' ', 1, "clr A" }, + { 0x006f, 0x00ff, ' ', 2, "clr (%1,X)" }, + { 0x007f, 0x00ff, ' ', 1, "clr (X)" }, + { 0x005f, 0x00ff, ' ', 1, "clrw X" }, + + { 0x0011, 0x00ff, ' ', 2, "cp A,(%1,SP)" }, + { 0x00a1, 0x00ff, ' ', 2, "cp A,%b" }, + { 0x00b1, 0x00ff, ' ', 2, "cp A,%d" }, + { 0x00c1, 0x00ff, ' ', 3, "cp A,%x" }, + { 0x00d1, 0x00ff, ' ', 3, "cp A,(%2,X)" }, + { 0x00e1, 0x00ff, ' ', 2, "cp A,(%1,X)" }, + { 0x00f1, 0x00ff, ' ', 1, "cp A,(X)" }, + { 0x0013, 0x00ff, ' ', 2, "cpw X,(%1,SP)" }, + { 0x00a3, 0x00ff, ' ', 3, "cpw X,%w" }, + { 0x00b3, 0x00ff, ' ', 2, "cpw X,%d" }, + { 0x00c3, 0x00ff, ' ', 3, "cpw X,%x" }, + { 0x00d3, 0x00ff, ' ', 3, "cpw Y,(%2,X)" }, + { 0x00e3, 0x00ff, ' ', 2, "cpw Y,(%1,X)" }, + { 0x00f3, 0x00ff, ' ', 1, "cpw Y,(X)" }, + + { 0x0003, 0x00ff, ' ', 2, "cpl (%1,SP)" }, + { 0x0033, 0x00ff, ' ', 2, "cpl %d" }, + { 0x0043, 0x00ff, ' ', 1, "cpl A" }, + { 0x0063, 0x00ff, ' ', 2, "cpl (%1,X)" }, + { 0x0073, 0x00ff, ' ', 1, "cpl (X)" }, + { 0x0053, 0x00ff, ' ', 1, "cplw X" }, + + { 0x000a, 0x00ff, ' ', 2, "dec (%1,SP)" }, + { 0x003a, 0x00ff, ' ', 2, "dec %d" }, + { 0x004a, 0x00ff, ' ', 1, "dec A" }, + { 0x006a, 0x00ff, ' ', 2, "dec (%1,X)" }, + { 0x007a, 0x00ff, ' ', 1, "dec (X)" }, + { 0x005a, 0x00ff, ' ', 1, "decw X" }, + + { 0x0062, 0x00ff, ' ', 1, "div X,A" }, + { 0x0065, 0x00ff, ' ', 1, "divw X,Y" }, + { 0x0031, 0x00ff, ' ', 3, "exg A,%x" }, + { 0x0041, 0x00ff, ' ', 1, "exg A,XL" }, + { 0x0051, 0x00ff, ' ', 1, "exgw X,Y" }, + { 0x0061, 0x00ff, ' ', 1, "exg A,YL" }, + { 0x008e, 0x00ff, ' ', 1, "halt" }, + { 0x0082, 0x00ff, ' ', 4, "int %e" }, + + { 0x000c, 0x00ff, ' ', 2, "inc (%1,SP)" }, + { 0x003c, 0x00ff, ' ', 2, "inc %d" }, + { 0x004c, 0x00ff, ' ', 1, "inc A" }, + { 0x006c, 0x00ff, ' ', 2, "inc (%1,X)" }, + { 0x007c, 0x00ff, ' ', 1, "inc (X)" }, + { 0x005c, 0x00ff, ' ', 1, "incw X" }, + + { 0x0080, 0x00ff, ' ', 1, "iret" }, + + { 0x00cc, 0x00ff, ' ', 3, "jp %x" }, + { 0x00dc, 0x00ff, ' ', 3, "jp (%2,X)" }, + { 0x00ec, 0x00ff, ' ', 2, "jp (%1,X)" }, + { 0x00fc, 0x00ff, ' ', 1, "jp (X)" }, + { 0x00ac, 0x00ff, ' ', 4, "jpf %e" }, + { 0x0020, 0x00ff, ' ', 2, "jra %p" }, + + { 0x0021, 0x00ff, ' ', 2, "jrf %p" }, + { 0x0022, 0x00ff, ' ', 2, "jrugt %p" }, + { 0x0023, 0x00ff, ' ', 2, "jrule %p" }, + { 0x0024, 0x00ff, ' ', 2, "jruge %p" }, + { 0x0025, 0x00ff, ' ', 2, "jrult %p" }, + { 0x0026, 0x00ff, ' ', 2, "jrne %p" }, + { 0x0027, 0x00ff, ' ', 2, "jreq %p" }, + { 0x0028, 0x00ff, ' ', 2, "jrnv %p" }, + { 0x0029, 0x00ff, ' ', 2, "jrv %p" }, + { 0x002a, 0x00ff, ' ', 2, "jrpl %p" }, + { 0x002b, 0x00ff, ' ', 2, "jrmi %p" }, + { 0x002c, 0x00ff, ' ', 2, "jrsgt %p" }, + { 0x002d, 0x00ff, ' ', 2, "jrsle %p" }, + { 0x002e, 0x00ff, ' ', 2, "jrsge %p" }, + { 0x002f, 0x00ff, ' ', 2, "jrslt %p" }, + + { 0x007b, 0x00ff, ' ', 2, "ld A,(%1,SP)" }, + { 0x00a6, 0x00ff, ' ', 2, "ld A,%b" }, + { 0x00b6, 0x00ff, ' ', 2, "ld A,%d" }, + { 0x00c6, 0x00ff, ' ', 3, "ld A,%x" }, + { 0x00d6, 0x00ff, ' ', 3, "ld A,(%2,X)" }, + { 0x00e6, 0x00ff, ' ', 2, "ld A,(%1,X)" }, + { 0x00f6, 0x00ff, ' ', 1, "ld A,(X)" }, + { 0x006b, 0x00ff, ' ', 2, "ld (%1,SP),A" }, + { 0x00a7, 0x00ff, ' ', 2, "ld %b,A" }, + { 0x00b7, 0x00ff, ' ', 2, "ld %d,A" }, + { 0x00c7, 0x00ff, ' ', 3, "ld %x,A" }, + { 0x00d7, 0x00ff, ' ', 3, "ld (%2,X),A" }, + { 0x00e7, 0x00ff, ' ', 2, "ld (%1,X),A" }, + { 0x00f7, 0x00ff, ' ', 1, "ld (X),A" }, + { 0x0095, 0x00ff, ' ', 1, "ld XH,A" }, + { 0x0097, 0x00ff, ' ', 1, "ld XL,A" }, + { 0x009e, 0x00ff, ' ', 1, "ld A,XH" }, + { 0x009f, 0x00ff, ' ', 1, "ld A,XL" }, + + { 0x00a7, 0x00ff, ' ', /*2*/4, "ldf (%3,X),A" }, + { 0x00af, 0x00ff, ' ', /*2*/4, "ldf A,(%3,X)" }, + { 0x00bd, 0x00ff, ' ', /*2*/4, "ldf %e,A" }, + { 0x00bc, 0x00ff, ' ', /*2*/4, "ldf A,%e" }, + { 0x001e, 0x00ff, ' ', 2, "ldw X,(%1,SP)" }, + { 0x00ae, 0x00ff, ' ', 3, "ldw X,%w" }, + { 0x00be, 0x00ff, ' ', 2, "ldw X,%d" }, + { 0x00ce, 0x00ff, ' ', 3, "ldw X,%x" }, + { 0x00de, 0x00ff, ' ', 3, "ldw X,(%2,X)" }, + { 0x00ee, 0x00ff, ' ', 2, "ldw X,(%1,X)" }, + { 0x00fe, 0x00ff, ' ', 1, "ldw X,(X)" }, + { 0x001f, 0x00ff, ' ', 2, "ldw (%1,SP),X" }, + { 0x00bf, 0x00ff, ' ', 2, "ldw %d,X" }, + { 0x00cf, 0x00ff, ' ', 3, "ldw %x,X" }, + { 0x00df, 0x00ff, ' ', 3, "ldw (%2,X),Y" }, + { 0x00ef, 0x00ff, ' ', 2, "ldw (%1,X),Y" }, + { 0x00ff, 0x00ff, ' ', 1, "ldw (X),Y" }, + { 0x0016, 0x00ff, ' ', 2, "ldw Y,(%1,SP)" }, + { 0x0017, 0x00ff, ' ', 2, "ldw (%1,SP),Y" }, + { 0x0093, 0x00ff, ' ', 1, "ldw X,Y" }, + { 0x0094, 0x00ff, ' ', 1, "ldw SP,X" }, + { 0x0096, 0x00ff, ' ', 1, "ldw X,SP" }, + + { 0x0035, 0x00ff, ' ', 4, "mov %b,%x" }, + { 0x0045, 0x00ff, ' ', 3, "mov %d,%d" }, + { 0x0055, 0x00ff, ' ', 5, "mov %x,%x" }, + { 0x0042, 0x00ff, ' ', 1, "mul X,A" }, + + { 0x0000, 0x00ff, ' ', 2, "neg (%1,SP)" }, + { 0x0030, 0x00ff, ' ', 2, "neg %d" }, + { 0x0040, 0x00ff, ' ', 1, "neg A" }, + { 0x0060, 0x00ff, ' ', 2, "neg (%1,X)" }, + { 0x0070, 0x00ff, ' ', 1, "neg (X)" }, + { 0x0050, 0x00ff, ' ', 1, "negw X" }, + + { 0x009d, 0x00ff, ' ', 1, "nop" }, + + { 0x001a, 0x00ff, ' ', 2, "or A,(%1,SP)" }, + { 0x00aa, 0x00ff, ' ', 2, "or A,%b" }, + { 0x00ba, 0x00ff, ' ', 2, "or A,%d" }, + { 0x00ca, 0x00ff, ' ', 3, "or A,%x" }, + { 0x00da, 0x00ff, ' ', 3, "or A,(%2,X)" }, + { 0x00ea, 0x00ff, ' ', 2, "or A,(%1,X)" }, + { 0x00fa, 0x00ff, ' ', 1, "or A,(X)" }, + + { 0x0084, 0x00ff, ' ', 1, "pop A" }, + { 0x0085, 0x00ff, ' ', 1, "popw X" }, + { 0x0086, 0x00ff, ' ', 1, "pop CC" }, + { 0x0032, 0x00ff, ' ', 3, "pop %x" }, + { 0x0088, 0x00ff, ' ', 1, "push A" }, + { 0x0089, 0x00ff, ' ', 1, "pushw X" }, + { 0x008a, 0x00ff, ' ', 1, "push CC" }, + { 0x003b, 0x00ff, ' ', 3, "push %x" }, + { 0x004b, 0x00ff, ' ', 2, "push %b" }, + + { 0x0098, 0x00ff, ' ', 1, "rcf" }, + { 0x0081, 0x00ff, ' ', 1, "ret" }, + { 0x0087, 0x00ff, ' ', 1, "retf" }, + { 0x009a, 0x00ff, ' ', 1, "rim" }, + + { 0x0009, 0x00ff, ' ', 2, "rlc (%1,SP)" }, + { 0x0039, 0x00ff, ' ', 2, "rlc %d" }, + { 0x0049, 0x00ff, ' ', 1, "rlc A" }, + { 0x0069, 0x00ff, ' ', 2, "rlc (%1,X)" }, + { 0x0079, 0x00ff, ' ', 1, "rlc (X)" }, + { 0x0059, 0x00ff, ' ', 1, "rlcw X" }, + { 0x0002, 0x00ff, ' ', 1, "rlwa X,A" }, + { 0x0006, 0x00ff, ' ', 2, "rrc (%1,SP)" }, + { 0x0036, 0x00ff, ' ', 2, "rrc %d" }, + { 0x0046, 0x00ff, ' ', 1, "rrc A" }, + { 0x0066, 0x00ff, ' ', 2, "rrc (%1,X)" }, + { 0x0076, 0x00ff, ' ', 1, "rrc (X)" }, + { 0x0056, 0x00ff, ' ', 1, "rrcw X" }, + { 0x0001, 0x00ff, ' ', 1, "rrwa X,A" }, + + { 0x009c, 0x00ff, ' ', 1, "rvf" }, + + { 0x0012, 0x00ff, ' ', 2, "sbc A,(%1,SP)" }, + { 0x00a2, 0x00ff, ' ', 2, "sbc A,%b" }, + { 0x00b2, 0x00ff, ' ', 2, "sbc A,%d" }, + { 0x00c2, 0x00ff, ' ', 3, "sbc A,%x" }, + { 0x00d2, 0x00ff, ' ', 3, "sbc A,(%2,X)" }, + { 0x00e2, 0x00ff, ' ', 2, "sbc A,(%1,X)" }, + { 0x00f2, 0x00ff, ' ', 1, "sbc A,(X)" }, + + { 0x0099, 0x00ff, ' ', 1, "scf" }, + { 0x009b, 0x00ff, ' ', 1, "sim" }, + + { 0x0008, 0x00ff, ' ', 2, "sla (%1,SP)" }, + { 0x0038, 0x00ff, ' ', 2, "sla %d" }, + { 0x0048, 0x00ff, ' ', 1, "sla A" }, + { 0x0068, 0x00ff, ' ', 2, "sla (%1,X)" }, + { 0x0078, 0x00ff, ' ', 1, "sla (X)" }, + { 0x0058, 0x00ff, ' ', 1, "slaw X" }, + { 0x0007, 0x00ff, ' ', 2, "sra (%1,SP)" }, + { 0x0037, 0x00ff, ' ', 2, "sra %d" }, + { 0x0047, 0x00ff, ' ', 1, "sra A" }, + { 0x0067, 0x00ff, ' ', 2, "sra (%1,X)" }, + { 0x0077, 0x00ff, ' ', 1, "sra (X)" }, + { 0x0057, 0x00ff, ' ', 1, "sraw X" }, + { 0x0004, 0x00ff, ' ', 2, "srl (%1,SP)" }, + { 0x0034, 0x00ff, ' ', 2, "srl %d" }, + { 0x0044, 0x00ff, ' ', 1, "srl A" }, + { 0x0064, 0x00ff, ' ', 2, "srl (%1,X)" }, + { 0x0074, 0x00ff, ' ', 1, "srl (X)" }, + { 0x0054, 0x00ff, ' ', 1, "srlw X" }, + + { 0x0010, 0x00ff, ' ', 2, "sub A,(%1,SP)" }, + { 0x00a0, 0x00ff, ' ', 2, "sub A,%b" }, + { 0x00b0, 0x00ff, ' ', 2, "sub A,%d" }, + { 0x00c0, 0x00ff, ' ', 3, "sub A,%x" }, + { 0x00d0, 0x00ff, ' ', 3, "sub A,(%2,X)" }, + { 0x00e0, 0x00ff, ' ', 2, "sub A,(%1,X)" }, + { 0x00f0, 0x00ff, ' ', 1, "sub A,(X)" }, + { 0x0052, 0x00ff, ' ', 2, "sub SP,%b" }, + + { 0x001d, 0x00ff, ' ', 3, "subw X,%w" }, + + { 0x000e, 0x00ff, ' ', 2, "swap (%1,SP)" }, + { 0x003e, 0x00ff, ' ', 2, "swap %d" }, + { 0x004e, 0x00ff, ' ', 1, "swap A" }, + { 0x006e, 0x00ff, ' ', 2, "swap (%1,X)" }, + { 0x007e, 0x00ff, ' ', 1, "swap (X)" }, + { 0x005e, 0x00ff, ' ', 1, "swapw X" }, + + { 0x000d, 0x00ff, ' ', 2, "tnz (%1,SP)" }, + { 0x003d, 0x00ff, ' ', 2, "tnz %d" }, + { 0x004d, 0x00ff, ' ', 1, "tnz A" }, + { 0x006d, 0x00ff, ' ', 2, "tnz (%1,X)" }, + { 0x007d, 0x00ff, ' ', 1, "tnz (X)" }, + { 0x005d, 0x00ff, ' ', 1, "tnzw X" }, + + { 0x0083, 0x00ff, ' ', 1, "trap", true }, + { 0x008f, 0x00ff, ' ', 1, "wfi" }, + + { 0x0018, 0x00ff, ' ', 2, "xor A,(%1,SP)" }, + { 0x00a8, 0x00ff, ' ', 2, "xor A,%b" }, + { 0x00b8, 0x00ff, ' ', 2, "xor A,%d" }, + { 0x00c8, 0x00ff, ' ', 3, "xor A,%x" }, + { 0x00d8, 0x00ff, ' ', 3, "xor A,(%2,X)" }, + { 0x00e8, 0x00ff, ' ', 2, "xor A,(%1,X)" }, + { 0x00f8, 0x00ff, ' ', 1, "xor A,(X)" }, + + { 0x008b, 0x00ff, ' ', 1, "break" }, + + { 0, 0, 0, 0, NULL } +}; + + +struct dis_entry disass_stm8_71[]= { + { 0x00ec, 0x00ff, ' ', 1, "halt" }, + { 0x00ed, 0x00ff, ' ', 1, "putchar" }, + + { 0, 0, 0, 0, NULL } +}; + +struct dis_entry disass_stm8_72[]= { + + { 0x00c9, 0x00ff, ' ', 3, "adc A,[%2.w]" }, + { 0x00d9, 0x00ff, ' ', 3, "adc A,([%2.w],X)" }, + { 0x00cb, 0x00ff, ' ', 3, "add A,[%2.w]" }, + { 0x00db, 0x00ff, ' ', 3, "add A,([%2.w],X)" }, + { 0x00bb, 0x00ff, ' ', 3, "addw X,%x" }, + { 0x00b9, 0x00ff, ' ', 3, "addw Y,%x" }, + { 0x00a9, 0x00ff, ' ', 3, "addw Y,%w" }, + { 0x00f9, 0x00ff, ' ', 3, "addw Y,%d" }, + { 0x00fb, 0x00ff, ' ', 2, "addw X,(%1,SP)" }, + { 0x00f9, 0x00ff, ' ', 2, "addw Y,(%1,SP)" }, + { 0x00c4, 0x00ff, ' ', 3, "and A,[%2.w]" }, + { 0x00d4, 0x00ff, ' ', 3, "and A,([%2.w],X)" }, + { 0x00c5, 0x00ff, ' ', 3, "bcp A,[%2.w]" }, + { 0x00d5, 0x00ff, ' ', 3, "bcp A,([%2.w],X)" }, + + { 0x0011, 0x00ff, ' ', 3, "bres %x,#0" }, + { 0x0013, 0x00ff, ' ', 3, "bres %x,#1" }, + { 0x0015, 0x00ff, ' ', 3, "bres %x,#2" }, + { 0x0017, 0x00ff, ' ', 3, "bres %x,#3" }, + { 0x0019, 0x00ff, ' ', 3, "bres %x,#4" }, + { 0x001b, 0x00ff, ' ', 3, "bres %x,#5" }, + { 0x001d, 0x00ff, ' ', 3, "bres %x,#6" }, + { 0x001f, 0x00ff, ' ', 3, "bres %x,#7" }, + + { 0x0010, 0x00ff, ' ', 3, "bset %x,#0" }, + { 0x0012, 0x00ff, ' ', 3, "bset %x,#1" }, + { 0x0014, 0x00ff, ' ', 3, "bset %x,#2" }, + { 0x0016, 0x00ff, ' ', 3, "bset %x,#3" }, + { 0x0018, 0x00ff, ' ', 3, "bset %x,#4" }, + { 0x001a, 0x00ff, ' ', 3, "bset %x,#5" }, + { 0x001c, 0x00ff, ' ', 3, "bset %x,#6" }, + { 0x001e, 0x00ff, ' ', 3, "bset %x,#7" }, + + { 0x0001, 0x00ff, ' ', 4, "btjf %x,#0,%p" }, + { 0x0003, 0x00ff, ' ', 4, "btjf %x,#1,%p" }, + { 0x0005, 0x00ff, ' ', 4, "btjf %x,#2,%p" }, + { 0x0007, 0x00ff, ' ', 4, "btjf %x,#3,%p" }, + { 0x0009, 0x00ff, ' ', 4, "btjf %x,#4,%p" }, + { 0x000b, 0x00ff, ' ', 4, "btjf %x,#5,%p" }, + { 0x000d, 0x00ff, ' ', 4, "btjf %x,#6,%p" }, + { 0x000f, 0x00ff, ' ', 4, "btjf %x,#7,%p" }, + + { 0x0000, 0x00ff, ' ', 4, "btjt %x,#0,%p" }, + { 0x0002, 0x00ff, ' ', 4, "btjt %x,#1,%p" }, + { 0x0004, 0x00ff, ' ', 4, "btjt %x,#2,%p" }, + { 0x0006, 0x00ff, ' ', 4, "btjt %x,#3,%p" }, + { 0x0008, 0x00ff, ' ', 4, "btjt %x,#4,%p" }, + { 0x000a, 0x00ff, ' ', 4, "btjt %x,#5,%p" }, + { 0x000c, 0x00ff, ' ', 4, "btjt %x,#6,%p" }, + { 0x000e, 0x00ff, ' ', 4, "btjt %x,#7,%p" }, + + { 0x00cd, 0x00ff, ' ', 3, "call [%2.w]", true }, + { 0x00dd, 0x00ff, ' ', 3, "call ([%2.w],X)", true }, + + { 0x003f, 0x00ff, ' ', 3, "clr [%2.w]" }, + { 0x004f, 0x00ff, ' ', 3, "clr (%2,X)" }, + { 0x005f, 0x00ff, ' ', 3, "clr %x" }, + { 0x006f, 0x00ff, ' ', 3, "clr ([%2.w],X)" }, + + { 0x00c1, 0x00ff, ' ', 3, "cp A,[%2.w]" }, + { 0x00d1, 0x00ff, ' ', 3, "cp A,([%2.w],X)" }, + { 0x00c3, 0x00ff, ' ', 3, "cpw Y,[%2.w]" }, + { 0x00d3, 0x00ff, ' ', 3, "cpw Y,([%2.w],X)" }, + + { 0x0033, 0x00ff, ' ', 3, "cpl [%2.w]" }, + { 0x0043, 0x00ff, ' ', 3, "cpl (%2,X)" }, + { 0x0053, 0x00ff, ' ', 3, "cpl %x" }, + { 0x0063, 0x00ff, ' ', 3, "cpl ([%2.w],X)" }, + + { 0x003a, 0x00ff, ' ', 3, "dec [%2.w]" }, + { 0x004a, 0x00ff, ' ', 3, "dec (%2,X)" }, + { 0x005a, 0x00ff, ' ', 3, "dec %x" }, + { 0x006a, 0x00ff, ' ', 3, "dec ([%2.w],X)" }, + + { 0x003c, 0x00ff, ' ', 3, "inc [%2.w]" }, + { 0x004c, 0x00ff, ' ', 3, "inc (%2,X)" }, + { 0x005c, 0x00ff, ' ', 3, "inc %x" }, + { 0x006c, 0x00ff, ' ', 3, "inc ([%2.w],X)" }, + + { 0x00cc, 0x00ff, ' ', 3, "jp [%2.w]" }, + { 0x00dc, 0x00ff, ' ', 3, "jp ([%2.w],X)" }, + + { 0x00c6, 0x00ff, ' ', 3, "ld A,[%2.w]" }, + { 0x00d6, 0x00ff, ' ', 3, "ld A,([%2.w],X)" }, + { 0x00c7, 0x00ff, ' ', 3, "ld [%2.w],A" }, + { 0x00d7, 0x00ff, ' ', 3, "ld ([%2.w],X),A" }, + { 0x00ce, 0x00ff, ' ', 3, "ldw X,[%2.w]" }, + { 0x00de, 0x00ff, ' ', 3, "ldw X,([%2.w],X)" }, + { 0x00cf, 0x00ff, ' ', 3, "ldw [%2.w],X" }, + { 0x00df, 0x00ff, ' ', 3, "ldw ([%2.w],X),Y" }, + + { 0x0030, 0x00ff, ' ', 3, "neg [%2.w]" }, + { 0x0040, 0x00ff, ' ', 3, "neg (%2,X)" }, + { 0x0050, 0x00ff, ' ', 3, "neg %x" }, + { 0x0060, 0x00ff, ' ', 3, "neg ([%2.w],X)" }, + + { 0x00ca, 0x00ff, ' ', 3, "or A,[%2.w]" }, + { 0x00da, 0x00ff, ' ', 3, "or A,([%2.w],X)" }, + + { 0x0039, 0x00ff, ' ', 3, "rlc [%2.w]" }, + { 0x0049, 0x00ff, ' ', 3, "rlc (%2,X)" }, + { 0x0059, 0x00ff, ' ', 3, "rlc %x" }, + { 0x0069, 0x00ff, ' ', 3, "rlc ([%2.w],X)" }, + { 0x0036, 0x00ff, ' ', 3, "rrc [%2.w]" }, + { 0x0046, 0x00ff, ' ', 3, "rrc (%2,X)" }, + { 0x0056, 0x00ff, ' ', 3, "rrc %x" }, + { 0x0066, 0x00ff, ' ', 3, "rrc ([%2.w],X)" }, + + { 0x00c2, 0x00ff, ' ', 3, "sbc A,[%2.w]" }, + { 0x00d2, 0x00ff, ' ', 3, "sbc A,([%2.w],X)" }, + + { 0x0038, 0x00ff, ' ', 3, "sla [%2.w]" }, + { 0x0048, 0x00ff, ' ', 3, "sla (%2,X)" }, + { 0x0058, 0x00ff, ' ', 3, "sla %x" }, + { 0x0068, 0x00ff, ' ', 3, "sla ([%2.w],X)" }, + { 0x0037, 0x00ff, ' ', 3, "sra [%2.w]" }, + { 0x0047, 0x00ff, ' ', 3, "sra (%2,X)" }, + { 0x0057, 0x00ff, ' ', 3, "sra %x" }, + { 0x0067, 0x00ff, ' ', 3, "sra ([%2.w],X)" }, + { 0x0034, 0x00ff, ' ', 3, "srl [%2.w]" }, + { 0x0044, 0x00ff, ' ', 3, "srl (%2,X)" }, + { 0x0054, 0x00ff, ' ', 3, "srl %x" }, + { 0x0064, 0x00ff, ' ', 3, "srl ([%2.w],X)" }, + + { 0x00c0, 0x00ff, ' ', 3, "sub A,[%2.w]" }, + { 0x00d0, 0x00ff, ' ', 3, "sub A,([%2.w],X)" }, + + { 0x00b0, 0x00ff, ' ', 3, "subw X,%d" }, + { 0x00a2, 0x00ff, ' ', 3, "subw Y,%w" }, + { 0x00f2, 0x00ff, ' ', 3, "subw Y,%d" }, + { 0x00f0, 0x00ff, ' ', 2, "subw X,(%1,SP)" }, + { 0x00f2, 0x00ff, ' ', 2, "subw Y,(%1,SP)" }, + + { 0x003e, 0x00ff, ' ', 3, "swap [%2.w]" }, + { 0x004e, 0x00ff, ' ', 3, "swap (%2,X)" }, + { 0x005e, 0x00ff, ' ', 3, "swap %x" }, + { 0x006e, 0x00ff, ' ', 3, "swap ([%2.w],X)" }, + + { 0x003d, 0x00ff, ' ', 3, "tnz [%2.w]" }, + { 0x004d, 0x00ff, ' ', 3, "tnz (%2,X)" }, + { 0x005d, 0x00ff, ' ', 3, "tnz %x" }, + { 0x006d, 0x00ff, ' ', 3, "tnz ([%2.w],X)" }, + + { 0x008f, 0x00ff, ' ', 1, "wfe" }, + + { 0x00c8, 0x00ff, ' ', 3, "xor A,[%2.w]" }, + { 0x00d8, 0x00ff, ' ', 3, "xor A,([%2.w],X)" }, + + { 0, 0, 0, 0, NULL } +}; + +struct dis_entry disass_stm8_90[]= { + // 90 + { 0x00d9, 0x00ff, ' ', 3, "adc A,(%2,Y)" }, + { 0x00e9, 0x00ff, ' ', 2, "adc A,(%1,Y)" }, + { 0x00f9, 0x00ff, ' ', 1, "adc A,(Y)" }, + { 0x00db, 0x00ff, ' ', 3, "add A,(%2,Y)" }, + { 0x00eb, 0x00ff, ' ', 2, "add A,(%1,Y)" }, + { 0x00fb, 0x00ff, ' ', 1, "add A,(Y)" }, + { 0x00d4, 0x00ff, ' ', 3, "and A,(%2,Y)" }, + { 0x00e4, 0x00ff, ' ', 2, "and A,(%1,Y)" }, + { 0x00f4, 0x00ff, ' ', 1, "and A,(Y)" }, + { 0x00d5, 0x00ff, ' ', 3, "bcp A,(%2,Y)" }, + { 0x00e5, 0x00ff, ' ', 2, "bcp A,(%1,Y)" }, + { 0x00f5, 0x00ff, ' ', 1, "bcp A,(Y)" }, + //90 + { 0x0011, 0x00ff, ' ', 3, "bccm %d,#0" }, + { 0x0013, 0x00ff, ' ', 3, "bccm %d,#1" }, + { 0x0015, 0x00ff, ' ', 3, "bccm %d,#2" }, + { 0x0017, 0x00ff, ' ', 3, "bccm %d,#3" }, + { 0x0019, 0x00ff, ' ', 3, "bccm %d,#4" }, + { 0x001b, 0x00ff, ' ', 3, "bccm %d,#5" }, + { 0x001d, 0x00ff, ' ', 3, "bccm %d,#6" }, + { 0x001f, 0x00ff, ' ', 3, "bccm %d,#7" }, + // 90 + { 0x0010, 0x00ff, ' ', 3, "bcpl %d,#0" }, + { 0x0012, 0x00ff, ' ', 3, "bcpl %d,#1" }, + { 0x0014, 0x00ff, ' ', 3, "bcpl %d,#2" }, + { 0x0016, 0x00ff, ' ', 3, "bcpl %d,#3" }, + { 0x0018, 0x00ff, ' ', 3, "bcpl %d,#4" }, + { 0x001a, 0x00ff, ' ', 3, "bcpl %d,#5" }, + { 0x001c, 0x00ff, ' ', 3, "bcpl %d,#6" }, + { 0x001e, 0x00ff, ' ', 3, "bcpl %d,#7" }, + // 90 + { 0x00dd, 0x00ff, ' ', 3, "call (%2,Y)", true }, + { 0x00ed, 0x00ff, ' ', 2, "call (%1,Y)", true }, + { 0x00fd, 0x00ff, ' ', 1, "call (Y)", true }, + // 90 + { 0x004f, 0x00ff, ' ', 3, "clr (%2,Y)" }, + { 0x006f, 0x00ff, ' ', 2, "clr (%1,Y)" }, + { 0x007f, 0x00ff, ' ', 1, "clr (Y)" }, + { 0x005f, 0x00ff, ' ', 1, "clrw Y" }, + // 90 + { 0x00d1, 0x00ff, ' ', 3, "cp A,(%2,Y)" }, + { 0x00e1, 0x00ff, ' ', 2, "cp A,(%1,Y)" }, + { 0x00f1, 0x00ff, ' ', 1, "cp A,(Y)" }, + { 0x00a3, 0x00ff, ' ', 3, "cpw Y,%w" }, + { 0x00b3, 0x00ff, ' ', 2, "cpw Y,%d" }, + { 0x00c3, 0x00ff, ' ', 3, "cpw Y,%x" }, + { 0x00d3, 0x00ff, ' ', 3, "cpw X,(%2,Y)" }, + { 0x00e3, 0x00ff, ' ', 2, "cpw X,(%1,Y)" }, + { 0x00f3, 0x00ff, ' ', 1, "cpw X,(Y)" }, + // 90 + { 0x0043, 0x00ff, ' ', 3, "cpl (%2,Y)" }, + { 0x0063, 0x00ff, ' ', 2, "cpl (%1,Y)" }, + { 0x0073, 0x00ff, ' ', 1, "cpl (Y)" }, + { 0x0053, 0x00ff, ' ', 1, "cplw Y" }, + // 90 + { 0x004a, 0x00ff, ' ', 3, "dec (%2,Y)" }, + { 0x006a, 0x00ff, ' ', 2, "dec (%1,Y)" }, + { 0x007a, 0x00ff, ' ', 1, "dec (Y)" }, + { 0x005a, 0x00ff, ' ', 1, "decw Y" }, + // 90 + { 0x0062, 0x00ff, ' ', 1, "div Y,A" }, + // 90 + { 0x004c, 0x00ff, ' ', 3, "inc (%2,Y)" }, + { 0x006c, 0x00ff, ' ', 2, "inc (%1,Y)" }, + { 0x007c, 0x00ff, ' ', 1, "inc (Y)" }, + { 0x005c, 0x00ff, ' ', 1, "incw Y" }, + // 90 + { 0x00dc, 0x00ff, ' ', 3, "jp (%2,Y)" }, + { 0x00ec, 0x00ff, ' ', 2, "jp (%1,Y)" }, + { 0x00fc, 0x00ff, ' ', 1, "jp (Y)" }, + // 90 + { 0x0028, 0x00ff, ' ', 2, "jrnh %p" }, + { 0x0029, 0x00ff, ' ', 2, "jrh %p" }, + { 0x002c, 0x00ff, ' ', 2, "jrnm %p" }, + { 0x002d, 0x00ff, ' ', 2, "jrm %p" }, + { 0x002e, 0x00ff, ' ', 2, "jril %p" }, + { 0x002f, 0x00ff, ' ', 2, "jrih %p" }, + // 90 + { 0x00d6, 0x00ff, ' ', 3, "ld A,(%2,Y)" }, + { 0x00e6, 0x00ff, ' ', 2, "ld A,(%1,Y)" }, + { 0x00f6, 0x00ff, ' ', 1, "ld A,(Y)" }, + { 0x00d7, 0x00ff, ' ', 3, "ld (%2,Y),A" }, + { 0x00e7, 0x00ff, ' ', 2, "ld (%1,Y),A" }, + { 0x00f7, 0x00ff, ' ', 1, "ld (Y),A" }, + { 0x0095, 0x00ff, ' ', 1, "ld YH,A" }, + { 0x0097, 0x00ff, ' ', 1, "ld YL,A" }, + { 0x009e, 0x00ff, ' ', 1, "ld A,YH" }, + { 0x009f, 0x00ff, ' ', 1, "ld A,YL" }, + { 0x00a7, 0x00ff, ' ', /*2*/4, "ldf (%e,Y),A" }, // 90 + { 0x00af, 0x00ff, ' ', /*2*/4, "ldf A,(%e,Y)" }, + { 0x00ae, 0x00ff, ' ', 3, "ldw Y,%w" }, + { 0x00be, 0x00ff, ' ', 2, "ldw Y,%d" }, + { 0x00ce, 0x00ff, ' ', 3, "ldw Y,%x" }, + { 0x00de, 0x00ff, ' ', 3, "ldw Y,(%2,Y)" }, + { 0x00ee, 0x00ff, ' ', 2, "ldw Y,(%1,Y)" }, + { 0x00fe, 0x00ff, ' ', 1, "ldw Y,(Y)" }, + { 0x00bf, 0x00ff, ' ', 2, "ldw %d,Y" }, + { 0x00cf, 0x00ff, ' ', 3, "ldw %x,Y" }, + { 0x00df, 0x00ff, ' ', 3, "ldw (%2,Y),X" }, + { 0x00ef, 0x00ff, ' ', 2, "ldw (%1,Y),X" }, + { 0x00ff, 0x00ff, ' ', 1, "ldw (Y),X" }, + { 0x0093, 0x00ff, ' ', 1, "ldw Y,X" }, + { 0x0094, 0x00ff, ' ', 1, "ldw SP,Y" }, + { 0x0096, 0x00ff, ' ', 1, "ldw Y,SP" }, + // 90 + { 0x0042, 0x00ff, ' ', 1, "mul Y,A" }, + // 90 + { 0x0040, 0x00ff, ' ', 3, "neg (%2,Y)" }, + { 0x0060, 0x00ff, ' ', 2, "neg (%1,Y)" }, + { 0x0070, 0x00ff, ' ', 1, "neg (Y)" }, + { 0x0050, 0x00ff, ' ', 1, "negw Y" }, + // 90 + { 0x00da, 0x00ff, ' ', 3, "or A,(%2,Y)" }, + { 0x00ea, 0x00ff, ' ', 2, "or A,(%1,Y)" }, + { 0x00fa, 0x00ff, ' ', 1, "or A,(Y)" }, + // 90 + { 0x0085, 0x00ff, ' ', 1, "popw Y" }, + { 0x0089, 0x00ff, ' ', 1, "pushw Y" }, + // 90 + { 0x0049, 0x00ff, ' ', 3, "rlc (%2,Y)" }, + { 0x0069, 0x00ff, ' ', 2, "rlc (%1,Y)" }, + { 0x0079, 0x00ff, ' ', 1, "rlc (Y)" }, + { 0x0059, 0x00ff, ' ', 1, "rlcw Y" }, + { 0x0002, 0x00ff, ' ', 1, "rlwa Y,A" }, + { 0x0046, 0x00ff, ' ', 3, "rrc (%2,Y)" }, + { 0x0066, 0x00ff, ' ', 2, "rrc (%1,Y)" }, + { 0x0076, 0x00ff, ' ', 1, "rrc (Y)" }, + { 0x0056, 0x00ff, ' ', 1, "rrcw Y" }, + { 0x0001, 0x00ff, ' ', 1, "rrwa Y,A" }, + + { 0x00d2, 0x00ff, ' ', 3, "sbc A,(%2,Y)" }, + { 0x00e2, 0x00ff, ' ', 2, "sbc A,(%1,Y)" }, + { 0x00f2, 0x00ff, ' ', 1, "sbc A,(Y)" }, + + { 0x0048, 0x00ff, ' ', 3, "sla (%2,Y)" }, + { 0x0068, 0x00ff, ' ', 2, "sla (%1,Y)" }, + { 0x0078, 0x00ff, ' ', 1, "sla (Y)" }, + { 0x0058, 0x00ff, ' ', 1, "slaw Y" }, + { 0x0047, 0x00ff, ' ', 3, "sra (%2,Y)" }, + { 0x0067, 0x00ff, ' ', 2, "sra (%1,Y)" }, + { 0x0077, 0x00ff, ' ', 1, "sra (Y)" }, + { 0x0057, 0x00ff, ' ', 1, "sraw Y" }, + { 0x0044, 0x00ff, ' ', 3, "srl (%2,Y)" }, + { 0x0064, 0x00ff, ' ', 2, "srl (%1,Y)" }, + { 0x0074, 0x00ff, ' ', 1, "srl (Y)" }, + { 0x0054, 0x00ff, ' ', 1, "srlw Y" }, + + { 0x00d0, 0x00ff, ' ', 3, "sub A,(%2,Y)" }, + { 0x00e0, 0x00ff, ' ', 2, "sub A,(%1,Y)" }, + { 0x00f0, 0x00ff, ' ', 1, "sub A,(Y)" }, + + { 0x004e, 0x00ff, ' ', 3, "swap (%2,Y)" }, + { 0x006e, 0x00ff, ' ', 2, "swap (%1,Y)" }, + { 0x007e, 0x00ff, ' ', 1, "swap (Y)" }, + { 0x005e, 0x00ff, ' ', 1, "swapw Y" }, + + { 0x004d, 0x00ff, ' ', 3, "tnz (%2,Y)" }, + { 0x006d, 0x00ff, ' ', 2, "tnz (%1,Y)" }, + { 0x007d, 0x00ff, ' ', 1, "tnz (Y)" }, + { 0x005d, 0x00ff, ' ', 1, "tnzw Y" }, + + { 0x00d8, 0x00ff, ' ', 3, "xor A,(%2,Y)" }, + { 0x00e8, 0x00ff, ' ', 2, "xor A,(%1,Y)" }, + { 0x00f8, 0x00ff, ' ', 1, "xor A,(Y)" }, + + { 0, 0, 0, 0, NULL } +}; + +struct dis_entry disass_stm8_91[]= { + // 91 + { 0x00d9, 0x00ff, ' ', 2, "adc A,([%1.w],Y)" }, + { 0x00db, 0x00ff, ' ', 2, "add A,([%1.w],Y)" }, + { 0x00d4, 0x00ff, ' ', 2, "and A,([%1.w],Y)" }, + { 0x00d5, 0x00ff, ' ', 2, "bcp A,([%1.w],Y)" }, + { 0x00dd, 0x00ff, ' ', 2, "call ([%1.w],Y)", true }, + { 0x006f, 0x00ff, ' ', 2, "clr ([%1.w],Y)" }, + { 0x00d1, 0x00ff, ' ', 2, "cp A,([%1.w],Y)" }, + { 0x00c3, 0x00ff, ' ', 2, "cpw Y,[%1.w]" }, + { 0x00d3, 0x00ff, ' ', 2, "cpw X,([%1.w],Y)" }, + { 0x0063, 0x00ff, ' ', 2, "cpl ([%1.w],Y)" }, + { 0x006a, 0x00ff, ' ', 2, "dec ([%1.w],Y)" }, + { 0x006c, 0x00ff, ' ', 2, "inc ([%1.w],Y)" }, + { 0x00dc, 0x00ff, ' ', 2, "jp ([%1.w],Y)" }, + { 0x00d6, 0x00ff, ' ', 2, "ld A,([%1.w],Y)" }, + { 0x00d7, 0x00ff, ' ', 2, "ld ([%1.w],Y),A" }, + { 0x00a7, 0x00ff, ' ', /*2*/3, "ldf ([%2.e],Y),A" }, // 91 + { 0x00af, 0x00ff, ' ', /*2*/3, "ldf A,([%2.e],Y)" }, + { 0x00ce, 0x00ff, ' ', 3, "ldw Y,[%1.w]" }, + { 0x00de, 0x00ff, ' ', 3, "ldw Y,([%1.w],Y)" }, + { 0x00cf, 0x00ff, ' ', 3, "ldw [%1.w],Y" }, + { 0x00df, 0x00ff, ' ', 3, "ldw ([%1.w],Y),X" }, + { 0x0060, 0x00ff, ' ', 2, "neg ([%1.w],Y)" }, + { 0x00da, 0x00ff, ' ', 2, "or A,([%1.w],Y)" }, + { 0x0069, 0x00ff, ' ', 2, "rlc ([%1.w],Y)" }, + { 0x0066, 0x00ff, ' ', 2, "rrc ([%1.w],Y)" }, + { 0x00d2, 0x00ff, ' ', 2, "sbc A,([%1.w],Y)" }, + { 0x0068, 0x00ff, ' ', 2, "sla ([%1.w],Y)" }, + { 0x0067, 0x00ff, ' ', 2, "sra ([%1.w],Y)" }, + { 0x0064, 0x00ff, ' ', 2, "srl ([%1.w],Y)" }, + { 0x00d0, 0x00ff, ' ', 2, "sub A,([%1.w],Y)" }, + { 0x006e, 0x00ff, ' ', 2, "swap ([%1.w],Y)" }, + { 0x006d, 0x00ff, ' ', 2, "tnz ([%1.w],Y)" }, + { 0x00d8, 0x00ff, ' ', 2, "xor A,([%1.w],Y)" }, + + { 0, 0, 0, 0, NULL } +}; + +struct dis_entry disass_stm8_92[]= { + // 92 + { 0x00c9, 0x00ff, ' ', 2, "adc A,[%1.w]" }, + { 0x00d9, 0x00ff, ' ', 2, "adc A,([%1.w],X)" }, + { 0x00cb, 0x00ff, ' ', 2, "add A,[%1.w]" }, + { 0x00db, 0x00ff, ' ', 2, "add A,([%1.w],X)" }, + { 0x00c4, 0x00ff, ' ', 2, "and A,[%1.w]" }, + { 0x00d4, 0x00ff, ' ', 2, "and A,([%1.w],X)" }, + { 0x00c5, 0x00ff, ' ', 2, "bcp A,[%1.w]" }, + { 0x00d5, 0x00ff, ' ', 2, "bcp A,([%1.w],X)" }, + { 0x00cd, 0x00ff, ' ', 2, "call [%1.w]", true }, + { 0x00dd, 0x00ff, ' ', 2, "call ([%1.w],X)", true }, + { 0x008d, 0x00ff, ' ', 3, "callf [%2.e]", true }, + { 0x003f, 0x00ff, ' ', 2, "clr [%1.w]" }, + { 0x006f, 0x00ff, ' ', 2, "clr ([%1.w],X)" }, + { 0x00c1, 0x00ff, ' ', 2, "cp A,[%1.w]" }, + { 0x00d1, 0x00ff, ' ', 2, "cp A,([%1.w],X)" }, + { 0x00c3, 0x00ff, ' ', 2, "cpw X,[%1.w]" }, + { 0x00d3, 0x00ff, ' ', 2, "cpw Y,([%1.w],X)" }, + { 0x0033, 0x00ff, ' ', 2, "cpl [%1.w]" }, + { 0x0063, 0x00ff, ' ', 2, "cpl ([%1.w],X)" }, + // 92 + { 0x003a, 0x00ff, ' ', 2, "dec [%1.w]" }, + { 0x006a, 0x00ff, ' ', 2, "dec ([%1.w],X)" }, + { 0x003c, 0x00ff, ' ', 2, "inc [%1.w]" }, + { 0x006c, 0x00ff, ' ', 2, "inc ([%1.w],X)" }, + { 0x00cc, 0x00ff, ' ', 2, "jp [%1.w]" }, + { 0x00dc, 0x00ff, ' ', 2, "jp ([%1.w],X)" }, + { 0x00ac, 0x00ff, ' ', 3, "jpf [%2.e]" }, + { 0x00c6, 0x00ff, ' ', 2, "ld A,[%1.w]" }, + { 0x00d6, 0x00ff, ' ', 2, "ld A,([%1.w],X)" }, + { 0x00c7, 0x00ff, ' ', 2, "ld [%1.w],A" }, + { 0x00d7, 0x00ff, ' ', 2, "ld ([%1.w],X),A" }, + { 0x00a7, 0x00ff, ' ', /*2*/3, "ldf ([%2.e],X),A" }, + { 0x00af, 0x00ff, ' ', /*2*/3, "ldf A,([%2.e],X)" }, + { 0x00ce, 0x00ff, ' ', 2, "ldw X,[%1.w]" }, + { 0x00de, 0x00ff, ' ', 2, "ldw X,([%1.w],X)" }, + { 0x00cf, 0x00ff, ' ', 2, "ldw [%1.w],X" }, + { 0x00df, 0x00ff, ' ', 2, "ldw ([%1.w],X),Y" }, + // 92 + { 0x0030, 0x00ff, ' ', 2, "neg [%1.w]" }, + { 0x0060, 0x00ff, ' ', 2, "neg ([%1.w],X)" }, + { 0x00ca, 0x00ff, ' ', 2, "or A,[%1.w]" }, + { 0x00da, 0x00ff, ' ', 2, "or A,([%1.w],X)" }, + { 0x0039, 0x00ff, ' ', 2, "rlc [%1.w]" }, + { 0x0069, 0x00ff, ' ', 2, "rlc ([%1.w],X)" }, + { 0x0036, 0x00ff, ' ', 2, "rrc [%1.w]" }, + { 0x0066, 0x00ff, ' ', 2, "rrc ([%1.w],X)" }, + { 0x00c2, 0x00ff, ' ', 2, "sbc A,[%1.w]" }, + { 0x00d2, 0x00ff, ' ', 2, "sbc A,([%1.w],X)" }, + { 0x0038, 0x00ff, ' ', 2, "sla [%1.w]" }, + { 0x0068, 0x00ff, ' ', 2, "sla ([%1.w],X)" }, + { 0x0037, 0x00ff, ' ', 2, "sra [%1.w]" }, + { 0x0067, 0x00ff, ' ', 2, "sra ([%1.w],X)" }, + { 0x0034, 0x00ff, ' ', 2, "srl [%1.w]" }, + { 0x0064, 0x00ff, ' ', 2, "srl ([%1.w],X)" }, + // 92 + { 0x00c0, 0x00ff, ' ', 2, "sub A,[%1.w]" }, + { 0x00d0, 0x00ff, ' ', 2, "sub A,([%1.w],X)" }, + { 0x003e, 0x00ff, ' ', 2, "swap [%1.w]" }, + { 0x006e, 0x00ff, ' ', 2, "swap ([%1.w],X)" }, + { 0x003d, 0x00ff, ' ', 2, "tnz [%1.w]" }, + { 0x006d, 0x00ff, ' ', 2, "tnz ([%1.w],X)" }, + { 0x00c8, 0x00ff, ' ', 2, "xor A,[%1.w]" }, + { 0x00d8, 0x00ff, ' ', 2, "xor A,([%1.w],X)" }, + + { 0, 0, 0, 0, NULL } +}; + +/* glob.cc */ diff --git a/sim/ucsim/stm8.src/glob.h b/sim/ucsim/stm8.src/glob.h new file mode 100644 index 0000000..83e19f2 --- /dev/null +++ b/sim/ucsim/stm8.src/glob.h @@ -0,0 +1,48 @@ +/* + * Simulator of microcontrollers (glob.h) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#ifndef GLOB_HEADER +#define GLOB_HEADER + +#include "stypes.h" + + +extern struct dis_entry disass_stm8[]; + +extern struct dis_entry disass_stm8_71[]; + +extern struct dis_entry disass_stm8_72[]; + +extern struct dis_entry disass_stm8_90[]; + +extern struct dis_entry disass_stm8_91[]; + +extern struct dis_entry disass_stm8_92[]; + +#endif + +/* End of stm8.src/glob.h */ diff --git a/sim/ucsim/stm8.src/glob.o b/sim/ucsim/stm8.src/glob.o Binary files differnew file mode 100644 index 0000000..79074e9 --- /dev/null +++ b/sim/ucsim/stm8.src/glob.o diff --git a/sim/ucsim/stm8.src/inst.cc b/sim/ucsim/stm8.src/inst.cc new file mode 100644 index 0000000..275689a --- /dev/null +++ b/sim/ucsim/stm8.src/inst.cc @@ -0,0 +1,1403 @@ +/*
+ * Simulator of microcontrollers (inst.cc)
+ *
+ * stm8 code base from Vaclav Peroutka vaclavpe@users.sourceforge.net
+ * and Valentin Dudouyt valentin.dudouyt@gmail.com
+ *
+ * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
+ *
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING. If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#include "ddconfig.h"
+#include "stdio.h"
+#include <stdlib.h>
+
+// local
+#include "stm8cl.h"
+#include "regsstm8.h"
+#include "stm8mac.h"
+
+int
+cl_stm8::fetchea(t_mem code, unsigned char prefix)
+{
+ int ftc;
+
+ switch ((code >> 4) & 0x0f) {
+ case 0x1: return (unsigned char)fetch()+regs.SP; // SP indexed
+
+ case 0xb: return fetch(); // direct short
+
+
+ case 0xc:
+ if ( 0 == prefix) { // direct long
+ return fetch2();
+ } else if ( 0x72 == prefix) { // long pointer
+ ftc = fetch2();
+ return get2(ftc);
+ } else if ( 0x92 == prefix) { // short pointer
+ ftc = fetch();
+ return get2(ftc);
+ } else {
+ printf("************* bad prefix !!!!\n");
+ return (resHALT);
+ }
+
+ case 0xd:
+ if ( 0 == prefix) { // long offset with X reg
+ return fetch2()+regs.X;
+ } else if ( 0x72 == prefix) { // long pointer to offset with X reg
+ ftc = fetch2();
+ return get2(ftc)+regs.X;
+ } else if ( 0x90 == prefix) { // long offset with Y reg
+ return fetch2()+regs.Y;
+ } else if ( 0x91 == prefix) { // short pointer to offset with Y reg
+ ftc = fetch();
+ return get2(ftc)+regs.Y;
+ } else if ( 0x92 == prefix) { // short pointer to offset with X reg
+ ftc = fetch();
+ return get2(ftc)+regs.X;
+ } else {
+ return( resHALT);
+ }
+
+
+ case 0xe:
+ if ( 0 == prefix) { // short offset with X reg
+ return fetch()+regs.X;
+ } else if ( 0x90 == prefix) { // short offset with Y reg
+ return fetch()+regs.Y;
+ } else {
+ return( resHALT);
+ }
+
+ case 0xf:
+ if ( 0 == prefix) { // X index
+ return regs.X;
+ } else if ( 0x90 == prefix) { // Y index
+ return regs.Y;
+ } else {
+ return( resHALT);
+ }
+
+ default:
+ return(resHALT);
+ }
+}
+
+int
+cl_stm8::get_dest(t_mem code, unsigned char prefix)
+{
+ int resaddr, ftc;
+
+ switch ((code >> 4) & 0x0f) {
+ case 0x0:
+ if ( 0 == prefix) { // short offset with SP
+ resaddr = fetch()+regs.SP;
+ } else {
+ resaddr = ( resHALT);
+ }
+ break;
+
+ case 0x3:
+ if ( 0 == prefix) { // short direct
+ resaddr = fetch();
+ } else if ( 0x72 == prefix) { // long indirect - pointer
+ ftc = fetch2();
+ resaddr = get2(ftc);
+ } else if ( 0x92 == prefix) { // short indirect - pointer
+ ftc = fetch();
+ resaddr = get2(ftc);
+ } else {
+ resaddr = ( resHALT);
+ }
+ break;
+
+ case 0x4:
+ if ( 0x72 == prefix) { // long offset with X
+ ftc = fetch2();
+ resaddr = ftc + regs.X;
+ } else if ( 0x90 == prefix) { // long offset with Y
+ ftc = fetch2();
+ resaddr = ftc + regs.Y;
+ } else {
+ resaddr = ( resHALT);
+ }
+ break;
+
+ case 0x5:
+ if ( 0x72 == prefix) { // long direct
+ resaddr = fetch2();
+ } else {
+ resaddr = ( resHALT);
+ }
+ break;
+
+ case 0x6:
+ if ( 0 == prefix) { // short offset with X
+ resaddr = (fetch()+regs.X);
+ } else if ( 0x72 == prefix) { // long pointer to offset with X
+ ftc = fetch2();
+ resaddr = (get2(ftc)+regs.X);
+ } else if ( 0x90 == prefix) { // short offset with Y
+ resaddr = (fetch()+regs.Y);
+ } else if ( 0x91 == prefix) { // short pointer to offset with Y
+ ftc = fetch();
+ resaddr = (get2(ftc)+regs.Y);
+ } else if ( 0x92 == prefix) { // short pointer to offset with X
+ ftc = fetch();
+ resaddr = (get2(ftc)+regs.X);
+ } else {
+ resaddr =( resHALT);
+ }
+ break;
+
+ case 0x7:
+ if ( 0 == prefix) { // X index
+ resaddr = regs.X;
+ } else if ( 0x90 == prefix) { // Y index
+ resaddr = regs.Y;
+ } else {
+ resaddr =( resHALT);
+ }
+ break;
+
+ default:
+ resaddr =(resHALT);
+ break;
+ }
+
+ return resaddr;
+}
+
+void
+cl_stm8::flag_cvh(int x, int m, int r, bool byte, bool add, int mask)
+{
+ bool xt, xs, xh, mt, ms, mh, rt, rs, rh;
+
+ if (byte)
+ {
+ xt = !!(x & 0x80);
+ xs = !!(x & 0x40);
+ xh = !!(x & 0x08);
+ mt = !!(m & 0x80);
+ ms = !!(m & 0x40);
+ mh = !!(m & 0x08);
+ rt = !!(r & 0x80);
+ rs = !!(r & 0x40);
+ rh = !!(r & 0x08);
+ }
+ else
+ {
+ xt = !!(x & 0x8000);
+ xs = !!(x & 0x4000);
+ xh = !!(x & 0x0080);
+ mt = !!(m & 0x8000);
+ ms = !!(m & 0x4000);
+ mh = !!(m & 0x0080);
+ rt = !!(r & 0x8000);
+ rs = !!(r & 0x4000);
+ rh = !!(r & 0x0080);
+ }
+
+ if (add)
+ {
+ if (mask & BIT_V)
+ FLAG_ASSIGN (BIT_V, ((xt && mt) || (mt && !rt) || (!rt && xt)) ^ ((xs && ms) || (ms && !rs) || (!rs && xs)));
+ if (mask & BIT_C)
+ FLAG_ASSIGN (BIT_C, (xt && mt) || (mt && !rt) || (!rt && xt));
+ if (mask & BIT_H)
+ FLAG_ASSIGN (BIT_H, (xh && mh) || (mh && !rh) || (!rh && xh));
+ }
+ else
+ {
+ if (mask & BIT_V)
+ FLAG_ASSIGN (BIT_V, ((!xt && mt) || (!xt && rt) || (xt && mt && rt)) ^ ((!xs && ms) || (!xs && rs) || (xs && ms && rs)));
+ if (mask & BIT_H)
+ FLAG_ASSIGN (BIT_H, (!xh && mh) || (!xh && rh) || (xh && mh && rh));
+ if (mask & BIT_C)
+ FLAG_ASSIGN (BIT_C, (!xt && mt) || (!xt && rt) || (xt && mt && rt));
+ }
+}
+
+#define FLAG_CVH_BYTE_ADD(x, m, r, mask) flag_cvh(x, m, r, true, true, mask)
+#define FLAG_CVH_BYTE_SUB(x, m, r, mask) flag_cvh(x, m, r, true, false, mask)
+#define FLAG_CVH_WORD_ADD(x, m, r, mask) flag_cvh(x, m, r, false, true, mask)
+#define FLAG_CVH_WORD_SUB(x, m, r, mask) flag_cvh(x, m, r, false, false, mask)
+
+int
+cl_stm8::inst_adc(t_mem code, unsigned char prefix)
+{
+ int result, operand1, operand2;
+ int carryin = !!(regs.CC & BIT_C);
+
+ operand1 = regs.A;
+ operand2 = OPERAND(code, prefix);
+ result = operand1 + operand2 + carryin;
+
+ FLAG_NZ (result);
+ FLAG_CVH_BYTE_ADD(operand1, operand2, result, BIT_C | BIT_V | BIT_H);
+
+ regs.A = result & 0xff;
+ return(resGO);
+}
+
+int
+cl_stm8::inst_add(t_mem code, unsigned char prefix)
+{
+ FLAG_CLEAR(BIT_C);
+ return inst_adc(code, prefix);
+}
+
+int
+cl_stm8::get_1(unsigned int addr)
+{
+ vc.rd++;
+ return ram->read((t_addr) (addr));
+}
+
+int
+cl_stm8::get2(unsigned int addr)
+{
+ vc.rd+= 2;
+ return((ram->read((t_addr) (addr)) << 8) | ram->read((t_addr) (addr+1)));
+}
+
+int
+cl_stm8::get3(unsigned int addr)
+{
+ vc.rd+= 3;
+ return((ram->read((t_addr) (addr)) << 16) | (ram->read((t_addr) (addr+1)) << 8) |ram->read((t_addr) (addr+2)));
+}
+
+int
+cl_stm8::inst_addw(t_mem code, unsigned char prefix)
+{
+ long int result, operand1, operand2, nibble_high, nibble_low;
+ u16_t *dest_ptr;
+ bool sub;
+
+ nibble_high = (code >> 4) & 0x0f;
+ nibble_low = code & 0x0f;
+ dest_ptr = nibble_low == 0x09 || nibble_low == 0x02 ? ®s.Y : ®s.X;
+ operand1 = *dest_ptr;
+
+ switch(nibble_high)
+ {
+ case 0x1:
+ case 0xa: operand2 = fetch2(); break; // Immediate
+ case 0xb: operand2 = get2(fetch2()); break; // Long
+ case 0xf: operand2 = get2(regs.SP + fetch()); break; // sp-indexed
+ default: return(resHALT);
+ }
+
+ switch(nibble_low)
+ {
+ case 0x0:
+ case 0x2:
+ case 0xd: sub = true; break;
+ case 0x9:
+ case 0xb:
+ case 0xc: sub = false; break;
+ default: return(resHALT);
+ }
+
+ if (sub)
+ result = operand1 - operand2;
+ else
+ result = operand1 + operand2;
+
+ FLAG_ASSIGN (BIT_N, 0x8000 & result);
+ FLAG_ASSIGN (BIT_Z, (result & 0xffff) == 0);
+ if (sub)
+ FLAG_CVH_WORD_SUB(operand1, operand2, result, BIT_C | BIT_H | BIT_V);
+ else
+ FLAG_CVH_WORD_ADD(operand1, operand2, result, BIT_C | BIT_H | BIT_V);
+
+ *dest_ptr = result & 0xffff;
+ return(resGO);
+}
+
+int
+cl_stm8::inst_and(t_mem code, unsigned char prefix)
+{
+ int result, operand1, operand2;
+
+ operand1 = regs.A;
+ operand2 = OPERAND(code, prefix);
+ result = operand1 & operand2;
+ FLAG_NZ (result);
+
+ regs.A = result & 0xff;
+ return(resGO);
+}
+
+int
+cl_stm8::inst_bccmbcpl(t_mem code, unsigned char prefix)
+{
+ int ea = fetch2();
+ unsigned char dbyte;
+ dbyte= get1( ea);
+
+ if (code & 0x01) { // bccm
+ char pos = (code - 0x11) >> 1;
+ dbyte = dbyte & (~(1<<pos));
+ if (regs.CC & BIT_C) {
+ dbyte |= (1<<pos);
+ }
+ } else { // bcpl
+ char pos = (code - 0x10) >> 1;
+ dbyte = dbyte ^ (1<<pos);
+ }
+
+ store1(ea, dbyte);
+ return(resGO);
+}
+int
+cl_stm8::inst_bcp(t_mem code, unsigned char prefix)
+{
+ int result, operand1, operand2;
+
+ operand1 = regs.A;
+ operand2 = OPERAND(code, prefix);
+ result = operand1 & operand2 & 0xff;
+ FLAG_NZ (result);
+
+ return(resGO);
+}
+
+int
+cl_stm8::inst_bresbset(t_mem code, unsigned char prefix)
+{
+ int ea = fetch2();
+ unsigned char dbyte;
+ dbyte= get1( ea);
+
+ if (code & 0x01) { // bres
+ char pos = (code - 0x11) >> 1;
+ dbyte = dbyte & (~(1<<pos));
+ } else { // bset
+ char pos = (code - 0x10) >> 1;
+ dbyte = dbyte | (1<<pos);
+ }
+
+ store1(ea, dbyte);
+ return(resGO);
+}
+int
+cl_stm8::inst_btjfbtjt(t_mem code, unsigned char prefix)
+{
+ int ea = fetch2();
+ unsigned char dbyte;
+ dbyte= get1( ea);
+ char reljump = fetch();
+ char pos;
+
+ if (code & 0x01) { // btjf
+ pos = (code - 0x01) >> 1;
+ if(!( dbyte & (1<<pos))) {
+ PC += reljump;
+ }
+ } else { // btjt
+ pos = (code - 0x00) >> 1;
+ if ( dbyte & (1<<pos)) {
+ PC += reljump;
+ }
+ }
+
+ FLAG_ASSIGN (BIT_C, !!(dbyte & (1<<pos)));
+
+ return(resGO);
+}
+
+int
+cl_stm8::inst_call(t_mem code, unsigned char prefix)
+{
+ t_addr newPC = (PC & 0xff0000ul) + fetchea(code, prefix);
+ push2(PC);
+ PC = newPC;
+
+ return(resGO);
+}
+
+int
+cl_stm8::inst_clr(t_mem code, unsigned char prefix)
+{
+ unsigned int opaddr = 0;
+
+
+ FLAG_SET (BIT_Z);
+ FLAG_CLEAR (BIT_N);
+
+ switch(((code & 0xf0) | (prefix << 8)) >> 4) {
+ /* clr */
+ case 0x004: regs.A = 0; return(resGO);
+ case 0x003: opaddr = fetch(); break;
+ case 0x725: opaddr = fetch2(); break;
+ case 0x007: opaddr = regs.X; break;
+ case 0x006: opaddr = regs.X + fetch(); break;
+ case 0x724: opaddr = regs.X + fetch2(); break;
+ case 0x907: opaddr = regs.Y; break;
+ case 0x906: opaddr = regs.Y + fetch(); break;
+ case 0x904: opaddr = regs.Y + fetch2(); break;
+ case 0x000: opaddr = regs.SP + fetch(); break;
+ case 0x923: opaddr = get2(fetch()); break; // short indirect
+ case 0x723: opaddr = get2(fetch2()); break; // long indirect
+ case 0x926: opaddr = get2(fetch()) + regs.X; break; // short x-indexed indirect
+ case 0x726: opaddr = get2(fetch2()) + regs.X; break; // long x-indexed indirect
+ case 0x916: opaddr = get2(fetch()) + regs.Y; break; // short y-indexed indirect
+ /* clrw */
+ case 0x005: regs.X = 0; return(resGO);
+ case 0x905: regs.Y = 0; return(resGO);
+ default: return(resHALT);
+ }
+
+ store1(opaddr, 0);
+ return(resGO);
+}
+
+int
+cl_stm8::inst_cp(t_mem code, unsigned char prefix)
+{
+ int result, operand1, operand2;
+
+ operand1 = regs.A;
+ operand2 = OPERAND(code, prefix);
+ result = (operand1 - operand2) & 0xff;
+
+ FLAG_NZ (result);
+ FLAG_CVH_BYTE_SUB(operand1, operand2, result, BIT_C | BIT_V);
+
+ return(resGO);
+}
+
+int
+cl_stm8::inst_cpw(t_mem code, unsigned char prefix)
+{
+ long int operand1, operand2, result;
+ int reversed = 0;
+
+ operand1 = prefix == 0x90 ? regs.Y : regs.X;
+ operand2 = prefix == 0x90 ? regs.X : regs.Y;
+
+ switch((code & 0xf0) >> 4)
+ {
+ case 0xa: operand2 = fetch2(); break; // Immediate
+ case 0xb: operand2 = get2(fetch()); break; // Short
+ case 0xc:
+ switch (prefix)
+ {
+ case 0x00:
+ case 0x90: operand2 = get2(fetch2()); break; // Long direct
+ case 0x92: operand2 = get2(get2(fetch())); break; // short indirect
+ case 0x72: operand2 = get2(get2(fetch2())); break; // long indirect
+ case 0x91: operand2 = get2(get2(fetch())); operand1 = regs.Y; break; // short indirect
+ default: return(resHALT);
+ }
+ break;
+ case 0x1: operand2 = get2(regs.SP + fetch()); break; // SP-indexed
+ case 0xf: operand1 = get2(operand1); reversed = 1; break; // cpw X|Y, (Y|X)
+ case 0xe: operand1 = get2(operand1 + fetch()); reversed = 1; break; // short indexed direct
+ case 0xd:
+ switch (prefix)
+ {
+ case 0x00:
+ case 0x90: operand1 = get2(operand1 + fetch2()); break; // short indexed direct
+ case 0x91: operand1 = get2(regs.Y + get2(fetch())); operand2 = regs.X; break; // short y-indexed indirect
+ case 0x92: operand1 = get2(operand1 + get2(fetch())); break; // short x-indexed indirect
+ case 0x72: operand1 = get2(operand1 + get2(fetch2())); break; // long x-indexed indirect
+ default: return(resHALT);
+ }
+ reversed = 1;
+ break;
+ default: return(resHALT);
+ }
+
+ if (!reversed)
+ result = (operand1 - operand2) & 0xffff;
+ else
+ result = (operand2 - operand1) & 0xffff;
+
+ FLAG_ASSIGN (BIT_Z, (result & 0xffff) == 0);
+ FLAG_ASSIGN (BIT_N, 0x8000 & result);
+ if (!reversed)
+ FLAG_CVH_WORD_SUB(operand1, operand2, result, BIT_C | BIT_V);
+ else
+ FLAG_CVH_WORD_SUB(operand2, operand1, result, BIT_C | BIT_V);
+
+ return(resGO);
+}
+
+int
+cl_stm8::inst_cpl(t_mem code, unsigned char prefix)
+{
+ long int operand;
+ unsigned int opaddr = 0;
+
+ if (((code&0xf0)==0x40) &&(prefix == 0x00)) {
+ operand = regs.A;
+ } else if (((code&0xf0)==0x50) &&(prefix == 0x00)) {
+ operand = regs.X;
+ } else if (((code&0xf0)==0x50) &&(prefix == 0x90)) {
+ operand = regs.Y;
+ } else {
+ opaddr = get_dest(code,prefix);
+ operand = get1(opaddr);
+ }
+
+ operand ^= 0xffff;
+
+ FLAG_SET (BIT_C);
+
+ if (((code&0xf0)==0x40) &&(prefix == 0x00)) {
+ regs.A = operand&0xff;
+ FLAG_ASSIGN (BIT_Z, (operand & 0xff) == 0);
+ FLAG_ASSIGN (BIT_N, 0x80 & operand);
+ } else if (((code&0xf0)==0x50) &&(prefix == 0x00)) {
+ regs.X = operand & 0xffff;
+ FLAG_ASSIGN (BIT_Z, (operand & 0xffff) == 0);
+ FLAG_ASSIGN (BIT_N, 0x8000 & operand);
+ } else if (((code&0xf0)==0x50) &&(prefix == 0x90)) {
+ regs.Y = operand & 0xffff;
+ FLAG_ASSIGN (BIT_Z, (operand & 0xffff) == 0);
+ FLAG_ASSIGN (BIT_N, 0x8000 & operand);
+ } else {
+ store1(opaddr, operand &0xff);
+ FLAG_ASSIGN (BIT_Z, (operand & 0xff) == 0);
+ FLAG_ASSIGN (BIT_N, 0x80 & operand);
+ }
+
+ return(resGO);
+}
+
+int
+cl_stm8::inst_dec(t_mem code, unsigned char prefix)
+{
+ long int operand, resval;
+ unsigned int opaddr = 0;
+
+ if (((code&0xf0)==0x40) &&(prefix == 0x00)) {
+ operand = regs.A;
+ } else if (((code&0xf0)==0x50) &&(prefix == 0x00)) {
+ operand = regs.X;
+ } else if (((code&0xf0)==0x50) &&(prefix == 0x90)) {
+ operand = regs.Y;
+ } else {
+ opaddr = get_dest(code,prefix);
+ operand = get1(opaddr);
+ }
+
+ resval = operand - 1;
+
+ if (((code&0xf0)==0x40) &&(prefix == 0x00)) {
+ regs.A = resval&0xff;
+ FLAG_ASSIGN (BIT_Z, (resval & 0xff) == 0);
+ FLAG_ASSIGN (BIT_N, 0x80 & resval);
+ FLAG_CVH_BYTE_ADD(operand, 0xff, resval, BIT_V);
+ } else if (((code&0xf0)==0x50) &&(prefix == 0x00)) {
+ regs.X = resval & 0xffff;
+ FLAG_ASSIGN (BIT_Z, (resval & 0xffff) == 0);
+ FLAG_ASSIGN (BIT_N, 0x8000 & resval);
+ FLAG_CVH_WORD_ADD(operand, 0xffff, resval, BIT_V);
+ } else if (((code&0xf0)==0x50) &&(prefix == 0x90)) {
+ regs.Y = resval & 0xffff;
+ FLAG_ASSIGN (BIT_Z, (resval & 0xffff) == 0);
+ FLAG_ASSIGN (BIT_N, 0x8000 & resval);
+ FLAG_CVH_WORD_ADD(operand, 0xffff, resval, BIT_V);
+ } else {
+ store1(opaddr, resval &0xff);
+ FLAG_ASSIGN (BIT_Z, (resval & 0xff) == 0);
+ FLAG_ASSIGN (BIT_N, 0x80 & resval);
+ FLAG_CVH_BYTE_ADD(operand, 0xff, resval, BIT_V);
+ }
+
+ return(resGO);
+}
+
+int
+cl_stm8::inst_div(t_mem code, unsigned char prefix)
+{
+ unsigned int quot, remi;
+
+ FLAG_CLEAR(BIT_N);
+ FLAG_CLEAR(BIT_H);
+ FLAG_CLEAR(BIT_V);
+
+ if( code == 0x65) { // divw
+ if (regs.Y == 0x00) {
+ FLAG_SET(BIT_C);
+ } else {
+ FLAG_CLEAR(BIT_C);
+ quot = regs.X / regs.Y;
+ remi = regs.X % regs.Y;
+ regs.X = quot;
+ regs.Y = remi;
+ FLAG_ASSIGN (BIT_Z, (quot & 0xffff) == 0);
+ }
+ } else { //div
+ if (regs.A == 0x00) {
+ FLAG_SET(BIT_C);
+ } else {
+ FLAG_CLEAR(BIT_C);
+ if (prefix == 0x00) {
+ quot = regs.X / regs.A;
+ remi = regs.X % regs.A;
+ regs.X = quot;
+ regs.A = remi;
+ } else if (prefix == 0x90) {
+ quot = regs.Y / regs.A;
+ remi = regs.Y % regs.A;
+ regs.Y = quot;
+ regs.A = remi;
+ } else {
+ return (resHALT);
+ }
+ FLAG_ASSIGN (BIT_Z, (quot & 0xffff) == 0);
+ }
+ }
+
+ return(resGO);
+}
+
+int
+cl_stm8::inst_inc(t_mem code, unsigned char prefix)
+{
+ long int operand, resval;
+ unsigned int opaddr = 0;
+
+ if (((code&0xf0)==0x40) &&(prefix == 0x00)) {
+ operand = regs.A;
+ } else if (((code&0xf0)==0x50) &&(prefix == 0x00)) {
+ operand = regs.X;
+ } else if (((code&0xf0)==0x50) &&(prefix == 0x90)) {
+ operand = regs.Y;
+ } else {
+ opaddr = get_dest(code,prefix);
+ operand = get1(opaddr);
+ }
+
+ resval = operand + 1;
+
+ if (((code&0xf0)==0x40) &&(prefix == 0x00)) {
+ regs.A = resval&0xff;
+ FLAG_ASSIGN (BIT_Z, (resval & 0xff) == 0);
+ FLAG_ASSIGN (BIT_N, 0x80 & resval);
+ FLAG_CVH_BYTE_ADD(operand, 0x01, resval, BIT_V);
+ } else if (((code&0xf0)==0x50) &&(prefix == 0x00)) {
+ regs.X = resval & 0xffff;
+ FLAG_ASSIGN (BIT_Z, (resval & 0xffff) == 0);
+ FLAG_ASSIGN (BIT_N, 0x8000 & resval);
+ FLAG_CVH_WORD_ADD(operand, 0x0001, resval, BIT_V);
+ } else if (((code&0xf0)==0x50) &&(prefix == 0x90)) {
+ regs.Y = resval & 0xffff;
+ FLAG_ASSIGN (BIT_Z, (resval & 0xffff) == 0);
+ FLAG_ASSIGN (BIT_N, 0x8000 & resval);
+ FLAG_CVH_WORD_ADD(operand, 0x0001, resval, BIT_V);
+ } else {
+ store1(opaddr, resval &0xff);
+ FLAG_ASSIGN (BIT_Z, (resval & 0xff) == 0);
+ FLAG_ASSIGN (BIT_N, 0x80 & resval);
+ FLAG_CVH_BYTE_ADD(operand, 0x01, resval, BIT_V);
+ }
+
+ return(resGO);
+}
+
+int
+cl_stm8::inst_jp(t_mem code, unsigned char prefix)
+{
+ t_addr newPC = (PC & 0xff0000ul) + fetchea(code, prefix);
+ PC = newPC;
+ return(resGO);
+}
+
+int
+cl_stm8::inst_jr(t_mem code, unsigned char prefix)
+{
+ bool taken;
+ signed char ofs;
+ unsigned char bz, bn, bv;
+
+ if (prefix ==0x00) {
+ switch ((code>>1) & 7) {
+ case 0: // JRT - JRA (20) / JRF (21)
+ taken = 1;
+ break;
+ case 1: // JRUGT (22) / JRULE (23)
+ taken = !(regs.CC & (BIT_C | BIT_Z));
+ break;
+ case 2: // JRUGE (24) / JRULT (25)
+ taken = !(regs.CC & BIT_C);
+ break;
+ case 3: // JRNE (26) / JREQ (27)
+ taken = !(regs.CC & BIT_Z);
+ break;
+ case 4: // JRNV (28) / JRV (29)
+ taken = !(regs.CC & BIT_V);
+ break;
+ case 5: // JRPL (2A) / JRMI (2B)
+ taken = !(regs.CC & BIT_N);
+ break;
+ case 6: // JRSGT (2C) - Z or (N xor V) = 0 / JRSLE (2D) - Z or (N xor V) = 1
+ bz = !!(regs.CC & BIT_Z);
+ bn = !!(regs.CC & BIT_N);
+ bv = !!(regs.CC & BIT_V);
+ taken = !(bz | (bn ^ bv));
+ break;
+ case 7: // JRSGE (2E) - N xor V = 0 / / JRSLT(2F) N xor V = 1
+ bn = !!(regs.CC & BIT_N);
+ bv = !!(regs.CC & BIT_V);
+ taken = !(bn ^ bv);
+ break;
+ default:
+ return(resHALT);
+ }
+ }
+ else if (prefix==0x90) {
+ switch ((code>>1) & 7) {
+ case 4: // JRNH (28) / JRH (29)
+ taken = !(regs.CC & BIT_H);
+ break;
+ case 6: // JRNM (2C) / JRM (2D)
+ taken = !(regs.CC & (BIT_I1|BIT_I0));
+ break;
+ case 7: // JRIL (2E) / JRIH (2F), no means to test this ???
+ taken = 0;
+ default:
+ return(resHALT);
+ }
+ }
+ else
+ return(resHALT);
+
+ if (code & 1)
+ taken = ! taken;
+
+
+ ofs = fetch();
+ if (taken)
+ {
+ PC += ofs;
+ tick(1);
+ }
+ return(resGO);
+}
+
+int
+cl_stm8::inst_lda(t_mem code, unsigned char prefix)
+{
+ int operand;
+ operand = OPERAND(code, prefix);
+ FLAG_NZ (operand);
+ regs.A = operand;
+ return(resGO);
+}
+
+int
+cl_stm8::operandw(t_mem code, unsigned char prefix)
+{
+ if(EA_IMM(code)) {
+ return(fetch2());
+ } else {
+ int addr = fetchea(code,prefix);
+ int result = get2(addr);
+ return(result);
+ }
+}
+
+int
+cl_stm8::inst_ldxy(t_mem code, unsigned char prefix)
+{
+ unsigned int operand;
+ u16_t *dest_ptr;
+
+ tick(1);
+
+ dest_ptr = (prefix == 0x90) ? ®s.Y : ®s.X;
+ if((prefix == 0x00 && code == 0x16) || (prefix == 0x91 && code == 0xce) || (prefix == 0x91 && code == 0xde)) dest_ptr = ®s.Y;
+
+ switch((code & 0xf0) >> 4) {
+ case 0xa: operand = fetch2(); break; // Immediate
+ case 0xb: operand = get2(fetch()); break; // Short
+ case 0xc:
+ switch (prefix) {
+ case 0x90:
+ case 0x00:
+ operand = get2(fetch2()); // Long direct
+ break;
+ case 0x92:
+ case 0x91:
+ operand = get2(get2(fetch())); // short indirect
+ break;
+ case 0x72:
+ operand = get2(get2(fetch2())); // long indirect
+ break;
+ default:
+ return(resHALT);
+ }
+ break;
+ case 0xf: operand = get2(*dest_ptr); break;
+ case 0xe: operand = get2(*dest_ptr + fetch()); break;
+ case 0xd:
+ switch (prefix) {
+ case 0x90:
+ case 0x00:
+ operand = get2(*dest_ptr + fetch2()); // Long x/y-indexed direct
+ break;
+ case 0x92:
+ case 0x91:
+ operand = get2(*dest_ptr + get2(fetch())); // short x/y-indexed indirect
+ break;
+ case 0x72:
+ operand = get2(*dest_ptr + get2(fetch2())); // long x-indexed indirect
+ break;
+ default:
+ return(resHALT);
+ }
+ break;
+ case 0x1: operand = get2(regs.SP + fetch()); break;
+ default: return(resHALT);
+ }
+
+ if ((code & 0xf0) != 0x90)
+ {
+ FLAG_ASSIGN (BIT_Z, (operand & 0xffff) == 0);
+ FLAG_ASSIGN (BIT_N, 0x8000 & operand);
+ }
+
+ *dest_ptr = operand;
+
+ return(resGO);
+}
+
+int
+cl_stm8::inst_lddst(t_mem code, unsigned char prefix)
+{
+ unsigned int opaddr;
+
+ opaddr = fetchea(code,prefix);
+
+ FLAG_ASSIGN (BIT_Z, (regs.A & 0xff) == 0);
+ FLAG_ASSIGN (BIT_N, 0x80 & regs.A);
+
+ store1(opaddr, regs.A);
+
+ return(resGO);
+}
+
+int
+cl_stm8::inst_ldxydst(t_mem code, unsigned char prefix)
+{
+ /* ldw dst, REG */
+ unsigned int opaddr, operand;
+
+ tick(1);
+
+ switch ((((code & 0xf0) | (prefix << 8)) >> 4) & 0xfff)
+ {
+ case 0x00b:
+ case 0x00c:
+ case 0x92c:
+ case 0x72c:
+ case 0x90f:
+ case 0x90e:
+ case 0x90d:
+ case 0x91d:
+ operand = regs.X;
+ break;
+ case 0x00f:
+ case 0x00e:
+ case 0x00d:
+ case 0x92d:
+ case 0x72d:
+ case 0x90b:
+ case 0x90c:
+ case 0x91c:
+ operand = regs.Y;
+ break;
+ case 0x001:
+ switch (code)
+ {
+ case 0x17:
+ operand = regs.Y;
+ break;
+ case 0x1f:
+ operand = regs.X;
+ break;
+ default:
+ return resHALT;
+ }
+ break;
+ default:
+ return resHALT;
+ }
+
+ switch((code & 0xf0) >> 4) {
+ case 0x1: opaddr = regs.SP + fetch(); break;
+ case 0xb: opaddr = fetch(); break;
+ case 0xc:
+ switch (prefix) {
+ case 0x00:
+ case 0x90:
+ opaddr = fetch2(); // long direct
+ break;
+ case 0x91:
+ case 0x92:
+ opaddr = get2(fetch()); // short indirect
+ break;
+ case 0x72:
+ opaddr = get2(fetch2()); // long indirect
+ break;
+ default:
+ return (resHALT);
+ }
+ break;
+ case 0xf: opaddr = (prefix == 0x90) ? regs.Y : regs.X; break;
+ case 0xe: opaddr = ((prefix == 0x90) ? regs.Y : regs.X) + fetch(); break;
+ case 0xd:
+ switch (prefix) {
+ case 0x90:
+ opaddr = regs.Y + fetch2(); // long y-indexed direct
+ break;
+ case 0x00:
+ opaddr = regs.X + fetch2(); // long x-indexed direct
+ break;
+ case 0x92:
+ opaddr = regs.X + get2(fetch()); // short x-indexed indirect
+ break;
+ case 0x91:
+ opaddr = regs.Y + get2(fetch()); // short y-indexed indirect
+ break;
+ case 0x72:
+ opaddr = regs.X + get2(fetch2()); // long x-indexed indirect
+ break;
+ default:
+ return (resHALT);
+ }
+ break;
+ default: return(resHALT);
+ }
+
+ FLAG_ASSIGN (BIT_Z, (operand & 0xffff) == 0);
+ FLAG_ASSIGN (BIT_N, 0x8000 & operand);
+
+ store2(opaddr, operand);
+
+ return(resGO);
+}
+
+int
+cl_stm8::inst_neg(t_mem code, unsigned char prefix)
+{
+ long int operand, resval;
+ unsigned int opaddr = 0;
+
+ if (((code&0xf0)==0x40) &&(prefix == 0x00)) {
+ operand = regs.A;
+ } else if (((code&0xf0)==0x50) &&(prefix == 0x00)) {
+ operand = regs.X;
+ } else if (((code&0xf0)==0x50) &&(prefix == 0x90)) {
+ operand = regs.Y;
+ } else {
+ opaddr = get_dest(code,prefix);
+ operand = get1(opaddr);
+ }
+
+ resval = 0 - operand;
+
+ if (((code&0xf0)==0x40) &&(prefix == 0x00)) {
+ regs.A = resval&0xff;
+ FLAG_ASSIGN (BIT_Z, (resval & 0xff) == 0);
+ FLAG_ASSIGN (BIT_N, 0x80 & resval);
+ FLAG_ASSIGN (BIT_V, (0x80 == operand));
+ FLAG_ASSIGN (BIT_C, 0x100 & resval);
+ } else if (((code&0xf0)==0x50) &&(prefix == 0x00)) {
+ regs.X = resval&0xffff;
+ FLAG_ASSIGN (BIT_Z, (resval & 0xffff) == 0);
+ FLAG_ASSIGN (BIT_N, 0x8000 & resval);
+ FLAG_ASSIGN (BIT_V, (0x8000 == operand));
+ FLAG_ASSIGN (BIT_C, 0x10000 & resval);
+ } else if (((code&0xf0)==0x50) &&(prefix == 0x90)) {
+ regs.Y = resval&0xffff;
+ FLAG_ASSIGN (BIT_Z, (resval & 0xffff) == 0);
+ FLAG_ASSIGN (BIT_N, 0x8000 & resval);
+ FLAG_ASSIGN (BIT_V, (0x8000 == operand));
+ FLAG_ASSIGN (BIT_C, 0x10000 & resval);
+ } else {
+ store1(opaddr, resval &0xff);
+ FLAG_ASSIGN (BIT_Z, (resval & 0xff) == 0);
+ FLAG_ASSIGN (BIT_N, 0x80 & resval);
+ FLAG_ASSIGN (BIT_V, (0x80 == operand));
+ FLAG_ASSIGN (BIT_C, 0x100 & resval);
+ }
+
+ return(resGO);
+}
+
+int
+cl_stm8::inst_or(t_mem code, unsigned char prefix)
+{
+ int result, operand1, operand2;
+
+ operand1 = regs.A;
+ operand2 = OPERAND(code, prefix);
+ result = (operand1 | operand2) & 0xff;
+ FLAG_NZ (result);
+
+ regs.A = result & 0xff;
+ return(resGO);
+}
+
+int
+cl_stm8::inst_rlc(t_mem code, unsigned char prefix)
+{
+ long int operand, resval;
+ unsigned int opaddr = 0;
+
+ if (((code&0xf0)==0x40) && (prefix == 0x00)) {
+ operand = regs.A;
+ } else if (((code&0xf0)==0x50) && (prefix == 0x00)) {
+ operand = regs.X;
+ } else if (((code&0xf0)==0x50) && (prefix == 0x90)) {
+ operand = regs.Y;
+ } else {
+ opaddr = get_dest (code, prefix);
+ operand = get1 (opaddr);
+ }
+
+ resval = operand << 0x1;
+
+ if (regs.CC & BIT_C) {
+ resval++;
+ }
+
+ if (((code&0xf0)==0x40) &&(prefix == 0x00)) {
+ regs.A = resval&0xff;
+ FLAG_ASSIGN (BIT_Z, (resval & 0xff) == 0);
+ FLAG_ASSIGN (BIT_N, 0x80 & resval);
+ FLAG_ASSIGN (BIT_C, (resval & 0x100));
+ } else if (((code&0xf0)==0x50) &&(prefix == 0x00)) {
+ regs.X = resval & 0xffff;
+ FLAG_ASSIGN (BIT_Z, (resval & 0xffff) == 0);
+ FLAG_ASSIGN (BIT_N, 0x8000 & resval);
+ FLAG_ASSIGN (BIT_C, (resval & 0x10000));
+ } else if (((code&0xf0)==0x50) &&(prefix == 0x90)) {
+ regs.Y = resval & 0xffff;
+ FLAG_ASSIGN (BIT_Z, (resval & 0xffff) == 0);
+ FLAG_ASSIGN (BIT_N, 0x8000 & resval);
+ FLAG_ASSIGN (BIT_C, (resval & 0x10000));
+ } else {
+ store1(opaddr, resval &0xff);
+ FLAG_ASSIGN (BIT_Z, (resval & 0xff) == 0);
+ FLAG_ASSIGN (BIT_N, 0x80 & resval);
+ FLAG_ASSIGN (BIT_C, (resval & 0x100));
+ }
+
+ return (resGO);
+}
+
+int
+cl_stm8::inst_rrc(t_mem code, unsigned char prefix)
+{
+ long int operand, resval;
+ unsigned int opaddr = 0;
+
+ if (((code&0xf0)==0x40) &&(prefix == 0x00)) {
+ operand = regs.A;
+ } else if (((code&0xf0)==0x50) &&(prefix == 0x00)) {
+ operand = regs.X;
+ } else if (((code&0xf0)==0x50) &&(prefix == 0x90)) {
+ operand = regs.Y;
+ } else {
+ opaddr = get_dest(code,prefix);
+ operand = get1(opaddr);
+ }
+
+ resval = operand >> 1;
+
+ if (((code&0xf0)==0x40) &&(prefix == 0x00)) {
+ if (regs.CC & BIT_C) { resval |= 0x80; }
+ regs.A = resval&0xff;
+ FLAG_ASSIGN (BIT_Z, (resval & 0xff) == 0);
+ FLAG_ASSIGN (BIT_N, 0x80 & resval);
+ FLAG_ASSIGN (BIT_C, (operand & 0x1));
+ } else if (((code&0xf0)==0x50) &&(prefix == 0x00)) {
+ if (regs.CC & BIT_C) { resval |= 0x8000; }
+ regs.X = resval & 0xffff;
+ FLAG_ASSIGN (BIT_Z, (resval & 0xffff) == 0);
+ FLAG_ASSIGN (BIT_N, 0x8000 & resval);
+ FLAG_ASSIGN (BIT_C, (operand & 0x1));
+ } else if (((code&0xf0)==0x50) &&(prefix == 0x90)) {
+ if (regs.CC & BIT_C) { resval |= 0x8000; }
+ regs.Y = resval & 0xffff;
+ FLAG_ASSIGN (BIT_Z, (resval & 0xffff) == 0);
+ FLAG_ASSIGN (BIT_N, 0x8000 & resval);
+ FLAG_ASSIGN (BIT_C, (operand & 0x1));
+ } else {
+ if (regs.CC & BIT_C) { resval |= 0x80; }
+ store1(opaddr, resval &0xff);
+ FLAG_ASSIGN (BIT_Z, (resval & 0xff) == 0);
+ FLAG_ASSIGN (BIT_N, 0x80 & resval);
+ FLAG_ASSIGN (BIT_C, (operand & 0x1));
+ }
+
+ return(resGO);
+}
+
+int
+cl_stm8::inst_sbc(t_mem code, unsigned char prefix)
+{
+ int result, operand1, operand2;
+ int carryin = !!(regs.CC & BIT_C);
+
+ operand1 = regs.A;
+ operand2 = OPERAND(code, prefix);
+ result = (operand1 - operand2 - carryin) & 0xff;
+
+ FLAG_NZ (result);
+ FLAG_CVH_BYTE_SUB(operand1, operand2, result, BIT_C | BIT_V);
+
+ regs.A = result;
+ return(resGO);
+}
+
+int
+cl_stm8::inst_sll(t_mem code, unsigned char prefix)
+{
+ long int operand, resval;
+ unsigned int opaddr = 0;
+
+ if (((code&0xf0)==0x40) &&(prefix == 0x00)) {
+ operand = regs.A;
+ } else if (((code&0xf0)==0x50) &&(prefix == 0x00)) {
+ operand = regs.X;
+ } else if (((code&0xf0)==0x50) &&(prefix == 0x90)) {
+ operand = regs.Y;
+ } else {
+ opaddr = get_dest(code,prefix);
+ operand = get1(opaddr);
+ }
+
+ resval = operand << 0x1;
+
+ if (((code&0xf0)==0x40) &&(prefix == 0x00)) {
+ regs.A = resval&0xff;
+ FLAG_ASSIGN (BIT_Z, (resval & 0xff) == 0);
+ FLAG_ASSIGN (BIT_N, 0x80 & resval);
+ FLAG_ASSIGN (BIT_C, (resval & 0x100));
+ } else if (((code&0xf0)==0x50) &&(prefix == 0x00)) {
+ regs.X = resval & 0xffff;
+ FLAG_ASSIGN (BIT_Z, (resval & 0xffff) == 0);
+ FLAG_ASSIGN (BIT_N, 0x8000 & resval);
+ FLAG_ASSIGN (BIT_C, (resval & 0x10000));
+ } else if (((code&0xf0)==0x50) &&(prefix == 0x90)) {
+ regs.Y = resval & 0xffff;
+ FLAG_ASSIGN (BIT_Z, (resval & 0xffff) == 0);
+ FLAG_ASSIGN (BIT_N, 0x8000 & resval);
+ FLAG_ASSIGN (BIT_C, (resval & 0x10000));
+ } else {
+ store1(opaddr, resval &0xff);
+ FLAG_ASSIGN (BIT_Z, (resval & 0xff) == 0);
+ FLAG_ASSIGN (BIT_N, 0x80 & resval);
+ FLAG_ASSIGN (BIT_C, (resval & 0x100));
+ }
+
+ return(resGO);
+}
+
+int
+cl_stm8::inst_sra(t_mem code, unsigned char prefix)
+{
+ long int operand, resval;
+ unsigned int opaddr = 0;
+
+ if (((code&0xf0)==0x40) &&(prefix == 0x00)) {
+ operand = regs.A;
+ } else if (((code&0xf0)==0x50) &&(prefix == 0x00)) {
+ operand = regs.X;
+ } else if (((code&0xf0)==0x50) &&(prefix == 0x90)) {
+ operand = regs.Y;
+ } else {
+ opaddr = get_dest(code,prefix);
+ operand = get1(opaddr);
+ }
+
+ resval = operand >> 1;
+
+ if (((code&0xf0)==0x40) &&(prefix == 0x00)) {
+ if (operand & 0x80) { resval |= 0x80; }
+ regs.A = resval&0xff;
+ FLAG_ASSIGN (BIT_Z, (resval & 0xff) == 0);
+ FLAG_ASSIGN (BIT_N, 0x80 & resval);
+ FLAG_ASSIGN (BIT_C, (operand & 0x1));
+ } else if (((code&0xf0)==0x50) &&(prefix == 0x00)) {
+ if (operand & 0x8000) { resval |= 0x8000; }
+ regs.X = resval & 0xffff;
+ FLAG_ASSIGN (BIT_Z, (resval & 0xffff) == 0);
+ FLAG_ASSIGN (BIT_N, 0x8000 & resval);
+ FLAG_ASSIGN (BIT_C, (operand & 0x1));
+ } else if (((code&0xf0)==0x50) &&(prefix == 0x90)) {
+ if (operand & 0x8000) { resval |= 0x8000; }
+ regs.Y = resval & 0xffff;
+ FLAG_ASSIGN (BIT_Z, (resval & 0xffff) == 0);
+ FLAG_ASSIGN (BIT_N, 0x8000 & resval);
+ FLAG_ASSIGN (BIT_C, (operand & 0x1));
+ } else {
+ if (operand & 0x80) { resval |= 0x80; }
+ store1(opaddr, resval &0xff);
+ FLAG_ASSIGN (BIT_Z, (resval & 0xff) == 0);
+ FLAG_ASSIGN (BIT_N, 0x80 & resval);
+ FLAG_ASSIGN (BIT_C, (operand & 0x1));
+ }
+
+ return(resGO);
+}
+
+int
+cl_stm8::inst_srl(t_mem code, unsigned char prefix)
+{
+ long int operand, resval;
+ unsigned int opaddr = 0;
+
+ if (((code&0xf0)==0x40) &&(prefix == 0x00)) {
+ operand = regs.A;
+ } else if (((code&0xf0)==0x50) &&(prefix == 0x00)) {
+ operand = regs.X;
+ } else if (((code&0xf0)==0x50) &&(prefix == 0x90)) {
+ operand = regs.Y;
+ } else {
+ opaddr = get_dest(code,prefix);
+ operand = get1(opaddr);
+ }
+
+ resval = operand >> 1;
+
+ if (((code&0xf0)==0x40) &&(prefix == 0x00)) {
+ regs.A = resval&0xff;
+ FLAG_ASSIGN (BIT_Z, (resval & 0xff) == 0);
+ FLAG_ASSIGN (BIT_N, 0x80 & resval);
+ FLAG_ASSIGN (BIT_C, (operand & 0x1));
+ } else if (((code&0xf0)==0x50) &&(prefix == 0x00)) {
+ regs.X = resval & 0xffff;
+ FLAG_ASSIGN (BIT_Z, (resval & 0xffff) == 0);
+ FLAG_ASSIGN (BIT_N, 0x8000 & resval);
+ FLAG_ASSIGN (BIT_C, (operand & 0x1));
+ } else if (((code&0xf0)==0x50) &&(prefix == 0x90)) {
+ regs.Y = resval & 0xffff;
+ FLAG_ASSIGN (BIT_Z, (resval & 0xffff) == 0);
+ FLAG_ASSIGN (BIT_N, 0x8000 & resval);
+ FLAG_ASSIGN (BIT_C, (operand & 0x1));
+ } else {
+ store1(opaddr, resval &0xff);
+ FLAG_ASSIGN (BIT_Z, (resval & 0xff) == 0);
+ FLAG_ASSIGN (BIT_N, 0x80 & resval);
+ FLAG_ASSIGN (BIT_C, (operand & 0x1));
+ }
+
+ return(resGO);
+}
+
+int
+cl_stm8::inst_sub(t_mem code, unsigned char prefix)
+{
+ FLAG_CLEAR(BIT_C);
+ return inst_sbc(code, prefix);
+}
+
+int
+cl_stm8::inst_swap(t_mem code, unsigned char prefix)
+{
+ long int operand, resval;
+ unsigned int opaddr = 0;
+
+ if (((code&0xf0)==0x40) &&(prefix == 0x00)) {
+ operand = regs.A;
+ resval = (operand << 4) | (operand >> 4);
+ regs.A = resval&0xff;
+ FLAG_ASSIGN (BIT_Z, (resval & 0xff) == 0);
+ FLAG_ASSIGN (BIT_N, 0x80 & resval);
+ } else if (((code&0xf0)==0x50) &&(prefix == 0x00)) {
+ operand = regs.X;
+ resval = (operand << 8) | (operand >> 8);
+ regs.X = resval&0xffff;
+ FLAG_ASSIGN (BIT_Z, (resval & 0xffff) == 0);
+ FLAG_ASSIGN (BIT_N, 0x8000 & resval);
+ } else if (((code&0xf0)==0x50) &&(prefix == 0x90)) {
+ operand = regs.Y;
+ resval = (operand << 8) | (operand >> 8);
+ regs.Y = resval&0xffff;
+ FLAG_ASSIGN (BIT_Z, (resval & 0xffff) == 0);
+ FLAG_ASSIGN (BIT_N, 0x8000 & resval);
+ } else {
+ opaddr = get_dest(code,prefix);
+ operand = get1(opaddr);
+ resval = (operand << 4) | (operand >> 4);
+ store1(opaddr, resval &0xff);
+ FLAG_ASSIGN (BIT_Z, (resval & 0xff) == 0);
+ FLAG_ASSIGN (BIT_N, 0x80 & resval);
+ }
+
+ return(resGO);
+}
+
+int
+cl_stm8::inst_tnz(t_mem code, unsigned char prefix)
+{
+ unsigned int resval;
+ unsigned int opaddr = 0;
+
+ if (((code&0xf0)==0x40) &&(prefix == 0x00)) {
+ resval = regs.A;
+ FLAG_ASSIGN (BIT_Z, (resval & 0xff) == 0);
+ FLAG_ASSIGN (BIT_N, 0x80 & resval);
+ } else if (((code&0xf0)==0x50) &&(prefix == 0x00)) {
+ resval = regs.X;
+ FLAG_ASSIGN (BIT_Z, (resval & 0xffff) == 0);
+ FLAG_ASSIGN (BIT_N, 0x8000 & resval);
+ } else if (((code&0xf0)==0x50) &&(prefix == 0x90)) {
+ resval = regs.Y;
+ FLAG_ASSIGN (BIT_Z, (resval & 0xffff) == 0);
+ FLAG_ASSIGN (BIT_N, 0x8000 & resval);
+ } else {
+ opaddr = get_dest(code,prefix);
+ resval = get1(opaddr);
+ FLAG_ASSIGN (BIT_Z, (resval & 0xff) == 0);
+ FLAG_ASSIGN (BIT_N, 0x80 & resval);
+ }
+
+ return(resGO);
+}
+
+int
+cl_stm8::inst_xor(t_mem code, unsigned char prefix)
+{
+ int result, operand1, operand2;
+
+ operand1 = regs.A;
+ operand2 = OPERAND(code, prefix);
+ result = operand1 ^ operand2;
+ FLAG_NZ (result);
+
+ regs.A = result & 0xff;
+ return(resGO);
+}
+
+/* End of stm8.src/inst.cc */
diff --git a/sim/ucsim/stm8.src/inst.o b/sim/ucsim/stm8.src/inst.o Binary files differnew file mode 100644 index 0000000..e51c1aa --- /dev/null +++ b/sim/ucsim/stm8.src/inst.o diff --git a/sim/ucsim/stm8.src/instcl.h b/sim/ucsim/stm8.src/instcl.h new file mode 100644 index 0000000..81efd9e --- /dev/null +++ b/sim/ucsim/stm8.src/instcl.h @@ -0,0 +1,48 @@ +
+/* stm8.src/instcl.h */
+
+ //virtual void incx(void);
+ virtual int fetchea(t_mem code, unsigned char prefix);
+ virtual int get_1(unsigned int addr);
+ virtual int get2(unsigned int addr);
+ virtual int get3(unsigned int addr);
+ virtual int get_dest(t_mem code, unsigned char prefix);
+ virtual int operandw(t_mem code, unsigned char prefix);
+ virtual void flag_cvh(int x, int m, int r, bool byte, bool add, int mask);
+
+ virtual int inst_adc(t_mem code, unsigned char prefix);
+ virtual int inst_add(t_mem code, unsigned char prefix);
+ virtual int inst_addw(t_mem code, unsigned char prefix);
+ virtual int inst_and(t_mem code, unsigned char prefix);
+ virtual int inst_bccmbcpl(t_mem code, unsigned char prefix);
+ virtual int inst_bcp(t_mem code, unsigned char prefix);
+ virtual int inst_bresbset(t_mem code, unsigned char prefix);
+ virtual int inst_btjfbtjt(t_mem code, unsigned char prefix);
+ virtual int inst_call(t_mem code, unsigned char prefix);
+ virtual int inst_clr(t_mem code, unsigned char prefix);
+ virtual int inst_cp(t_mem code, unsigned char prefix);
+ virtual int inst_cpw(t_mem code, unsigned char prefix);
+ virtual int inst_cpl(t_mem code, unsigned char prefix);
+ virtual int inst_dec(t_mem code, unsigned char prefix);
+ virtual int inst_div(t_mem code, unsigned char prefix);
+ virtual int inst_inc(t_mem code, unsigned char prefix);
+ virtual int inst_jp(t_mem code, unsigned char prefix);
+ virtual int inst_jr(t_mem code, unsigned char prefix);
+ virtual int inst_lda(t_mem code, unsigned char prefix);
+ virtual int inst_ldxy(t_mem code, unsigned char prefix);
+ virtual int inst_lddst(t_mem code, unsigned char prefix);
+ virtual int inst_ldxydst(t_mem code, unsigned char prefix);
+ virtual int inst_neg(t_mem code, unsigned char prefix);
+ virtual int inst_or(t_mem code, unsigned char prefix);
+ virtual int inst_rlc(t_mem code, unsigned char prefix);
+ virtual int inst_rrc(t_mem code, unsigned char prefix);
+ virtual int inst_sbc(t_mem code, unsigned char prefix);
+ virtual int inst_sll(t_mem code, unsigned char prefix);
+ virtual int inst_sra(t_mem code, unsigned char prefix);
+ virtual int inst_srl(t_mem code, unsigned char prefix);
+ virtual int inst_sub(t_mem code, unsigned char prefix);
+ virtual int inst_swap(t_mem code, unsigned char prefix);
+ virtual int inst_tnz(t_mem code, unsigned char prefix);
+ virtual int inst_xor(t_mem code, unsigned char prefix);
+
+/* End of stm8.src/instcl.h */
diff --git a/sim/ucsim/stm8.src/itc.cc b/sim/ucsim/stm8.src/itc.cc new file mode 100644 index 0000000..7dddd51 --- /dev/null +++ b/sim/ucsim/stm8.src/itc.cc @@ -0,0 +1,166 @@ +/* + * Simulator of microcontrollers (itc.cc) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +// prj + +#include <stdarg.h> +#include "utils.h" + +// sim +#include "itsrccl.h" + +// local +#include "itccl.h" + + +cl_itc::cl_itc(class cl_uc *auc): + cl_hw(auc, HW_INTERRUPT, 0, "itc") +{ + int i; + for (i= 0; i < 8; i++) + spr[i]= 0; +} + +int +cl_itc::init(void) +{ + int i; + cl_hw::init(); + for (i= 0; i < 8; i++) + { + if (spr[i]) + unregister_cell(spr[i]); + spr[i]= register_cell(uc->rom, 0x7f70+i); + } + return(0); +} + +void +cl_itc::added_to_uc(void) +{ +} + +void +cl_itc::new_hw_added(class cl_hw *new_hw) +{ +} + +t_mem +cl_itc::read(class cl_memory_cell *cell) +{ + return cell->get(); +} + +void +cl_itc::write(class cl_memory_cell *cell, t_mem *val) +{ + t_addr a; + if (uc->rom->is_owned(cell, &a) && + (a >= 0x7f70) && + (a < 0x7f70+8)) + { + u8_t mask= 0xff; + if ((*val & 0x03) == 0x02) + mask&= ~0x03; + if ((*val & 0x0c) == 0x08) + mask&= ~0x0c; + if ((*val & 0x30) == 0x20) + mask&= ~0x30; + if ((*val & 0xc0) == 0x80) + mask&= ~0xc0; + u8_t o= cell->get(), v= *val; + o&= ~mask; + v&= mask; + o|= v; + *val= o; + } +} + +/*void +cl_itc::mem_cell_changed(class cl_m *mem, t_addr addr) +{ +}*/ + +int +cl_itc::tick(int cycles) +{ + return(resGO); +} + +void +cl_itc::reset(void) +{ + int i; + for (i= 0; i < 8; i++) + spr[i]->write(0xff); +} + +void +cl_itc::happen(class cl_hw *where, enum hw_event he, void *params) +{ +} + + +void +cl_itc::print_info(class cl_console_base *con) +{ + int i; + + con->dd_printf("Interrupts are %s. Interrupt sources:\n", + (uc->it_enabled())?"enabled":"disabled"); + con->dd_printf(" Handler En Pr Req Act Name\n"); + for (i= 0; i < uc->it_sources->count; i++) + { + class cl_it_src *is= (class cl_it_src *)(uc->it_sources->at(i)); + con->dd_printf(" 0x%06x", AU(is->addr)); + con->dd_printf(" %-3s", (is->enabled())?"en":"dis"); + con->dd_printf(" %2d", uc->priority_of(/*is->ie_mask*/is->nuof)); + con->dd_printf(" %-3s", (is->pending())?"YES":"no"); + con->dd_printf(" %-3s", (is->active)?"act":"no"); + con->dd_printf(" %s", object_name(is)); + con->dd_printf("\n"); + } + con->dd_printf("Active interrupt service(s):\n"); + con->dd_printf(" Pr Handler PC Source\n"); + for (i= 0; i < uc->it_levels->count; i++) + { + class it_level *il= (class it_level *)(uc->it_levels->at(i)); + if (il->level >= 0) + { + con->dd_printf(" %2d", il->level); + con->dd_printf(" 0x%06x", AU(il->addr)); + con->dd_printf(" 0x%06x", AU(il->PC)); + con->dd_printf(" %s", (il->source)?(object_name(il->source)): + "nothing"); + con->dd_printf("\n"); + } + } + print_cfg_info(con); +} + + +/* End of s51.src/itc.cc */ diff --git a/sim/ucsim/stm8.src/itc.o b/sim/ucsim/stm8.src/itc.o Binary files differnew file mode 100644 index 0000000..70fcf2b --- /dev/null +++ b/sim/ucsim/stm8.src/itc.o diff --git a/sim/ucsim/stm8.src/itccl.h b/sim/ucsim/stm8.src/itccl.h new file mode 100644 index 0000000..24b8510 --- /dev/null +++ b/sim/ucsim/stm8.src/itccl.h @@ -0,0 +1,62 @@ +/* + * Simulator of microcontrollers (itc.h) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#ifndef STM8_ITCCL_HEADER +#define STM8_ITCCL_HEADER + +#include "stypes.h" +#include "pobjcl.h" +#include "uccl.h" + +#include "newcmdcl.h" + + +class cl_itc: public cl_hw +{ + public: + class cl_memory_cell *spr[8]; + public: + cl_itc(class cl_uc *auc); + virtual int init(void); + + + virtual void new_hw_added(class cl_hw *new_hw); + virtual void added_to_uc(void); + virtual t_mem read(class cl_memory_cell *cell); + virtual void write(class cl_memory_cell *cell, t_mem *val); + + virtual int tick(int cycles); + virtual void reset(void); + virtual void happen(class cl_hw *where, enum hw_event he, void *params); + + virtual void print_info(class cl_console_base *con); +}; + + +#endif + +/* End of s51.src/itc.h */ diff --git a/sim/ucsim/stm8.src/port.cc b/sim/ucsim/stm8.src/port.cc new file mode 100644 index 0000000..bf0addd --- /dev/null +++ b/sim/ucsim/stm8.src/port.cc @@ -0,0 +1,130 @@ +/* + * Simulator of microcontrollers (stm8.src/port.cc) + * + * Copyright (C) 2017,17 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#include "portcl.h" + +cl_port::cl_port(class cl_uc *auc, t_addr abase/*, int aid*/, const char *aname): + cl_hw(auc, HW_PORT, /*aid*/0, aname) +{ + base = abase; + set_name(aname); +} + +int +cl_port::init(void) +{ + cl_hw::init(); + // ODR + cell_p= register_cell(uc->rom, base + 0); + // IDR + cell_in= register_cell(uc->rom, base + 1); + // DDR: 0=input, 1=output + cell_dir= register_cell(uc->rom, base + 2); + + cl_var *v; + chars pn= cchars(get_name()); + uc->vars->add(v= new cl_var(pn+chars("_ddr"), uc->rom, base+2, + "Direction register")); + v->init(); + uc->vars->add(v= new cl_var(pn+chars("_odr"), uc->rom, base+0, + "Output data register")); + v->init(); + uc->vars->add(v= new cl_var(pn+chars("_idr"), uc->rom, base+1, + "Input data register (outside value of port pins)")); + v->init(); + uc->vars->add(v= new cl_var(pn+chars("_pin"), uc->rom, base+1, + "Outside value of port pins")); + v->init(); + uc->vars->add(v= new cl_var(pn+chars("_pins"), uc->rom, base+1, + "Outside value of port pins")); + v->init(); + + return 0; +} + +void +cl_port::reset(void) +{ + cell_dir->write(0); + cell_p->write(0); + cell_in->write(0); +} + +void +cl_port::write(class cl_memory_cell *cell, t_mem *val) +{ + if ((cell == cell_p) || + (cell == cell_in) || + (cell == cell_dir)) + { + cell->set(*val); + t_mem p= cell_p->get(); + t_mem i= cell_in->get(); + t_mem d= cell_dir->get(); + i&= ~d; + i|= (p & d); + cell_in->set(i); + if (cell == cell_in) + *val= i; + } +} + +void +cl_port::print_info(class cl_console_base *con) +{ + int m; + t_mem o= cell_p->get(), + i= cell_in->get(), + d= cell_dir->get(); + con->dd_printf("%s at 0x%04x\n", get_name(), base); + con->dd_printf("dir: 0x%02x ", d); + for (m= 0x80; m; m>>= 1) + con->dd_printf("%c", (d & m)?'O':'I'); + con->dd_printf("\n"); + con->dd_printf("out: 0x%02x ", o); + for (m= 0x80; m; m>>= 1) + { + if (d & m) + con->dd_printf("%c", (o & m)?'1':'0'); + else + con->dd_printf("-"); + } + con->dd_printf("\n"); + con->dd_printf("in : 0x%02x ", i); + for (m= 0x80; m; m>>= 1) + { + //if (!(d & m)) + con->dd_printf("%c", (i & m)?'1':'0'); + //else + //con->dd_printf("-"); + } + con->dd_printf("\n"); + print_cfg_info(con); +} + + +/* End of stm8.src/port.cc */ diff --git a/sim/ucsim/stm8.src/port.o b/sim/ucsim/stm8.src/port.o Binary files differnew file mode 100644 index 0000000..e644ffc --- /dev/null +++ b/sim/ucsim/stm8.src/port.o diff --git a/sim/ucsim/stm8.src/portcl.h b/sim/ucsim/stm8.src/portcl.h new file mode 100644 index 0000000..fe5cd6d --- /dev/null +++ b/sim/ucsim/stm8.src/portcl.h @@ -0,0 +1,52 @@ +/* + * Simulator of microcontrollers (stm8.src/portcl.h) + * + * Copyright (C) 2017,17 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#ifndef PORTCL_HEADER +#define PORTCL_HEADER + +#include "port_hwcl.h" + + +class cl_port: public cl_hw +{ + public: + class cl_memory_cell *cell_p, *cell_in, *cell_dir; + t_addr base; + public: + cl_port(class cl_uc *auc, t_addr abase/*, int aid*/, const char *aname); + virtual int init(void); + virtual void reset(void); + + virtual void write(class cl_memory_cell *cell, t_mem *val); + + virtual void print_info(class cl_console_base *con); +}; + + +#endif + +/* End of stm8.src/portcl.h */ diff --git a/sim/ucsim/stm8.src/regsstm8.h b/sim/ucsim/stm8.src/regsstm8.h new file mode 100644 index 0000000..69327c5 --- /dev/null +++ b/sim/ucsim/stm8.src/regsstm8.h @@ -0,0 +1,65 @@ +/* + * Simulator of microcontrollers (regsstm8.h) + * + * some z80 code base from Karl Bongers karl@turbobit.com + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#ifndef REGSTM8_HEADER +#define REGSTM8_HEADER + +#include "ddconfig.h" + + +struct t_regs +{ + u8_t A; + u16_t X; + u16_t Y; + u16_t SP; + u8_t CC; + //u8_t VECTOR; +}; + +#define BIT_C 0x01 // carry status(out of bit 7) +#define BIT_Z 0x02 // zero status, 1=zero, 0=nonzero +#define BIT_N 0x04 // sign, 1=negative, 0=positive (or zero) +#define BIT_I0 0x08 // interrupt mask, 1=disabled, 0=enabled +#define BIT_H 0x10 // half carry status(out of bit 3) +#define BIT_I1 0x20 // interrupt mask, 1=disabled, 0=enabled +#define BIT_V 0x80 // signed overflow, 1=overflow +#define BIT_ALL (BIT_C |BIT_Z |BIT_N |BIT_I0 |BIT_H |BIT_I1 |BIT_V) // all bits + +#define BITPOS_C 0 // 1 +#define BITPOS_Z 1 // 2H +#define BITPOS_N 2 // 4H +#define BITPOS_I0 3 // 8H +#define BITPOS_H 4 // 10H +#define BITPOS_I1 5 // 20H +#define BITPOS_V 7 // 80H + +#endif + +/* End of stm8.src/regsstm8.h */ diff --git a/sim/ucsim/stm8.src/rst.cc b/sim/ucsim/stm8.src/rst.cc new file mode 100644 index 0000000..0a342cd --- /dev/null +++ b/sim/ucsim/stm8.src/rst.cc @@ -0,0 +1,63 @@ +/* + * Simulator of microcontrollers (stm8.src/rst.cc) + * + * Copyright (C) 2016,16 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#include "rstcl.h" + + +cl_rst::cl_rst(class cl_uc *auc, t_addr abase, t_mem amask): + cl_hw(auc, HW_RESET, 0, "rst") +{ + base= abase; + rst_sr= 0; + mask= amask; +} + +int +cl_rst::init(void) +{ + rst_sr= register_cell(uc->rom, base); + return 0; +} + +t_mem +cl_rst::read(class cl_memory_cell *cell) +{ + return cell->get(); +} + +void +cl_rst::write(class cl_memory_cell *cell, t_mem *val) +{ + if (cell == rst_sr) + { + u8_t v= *val & mask, o= cell->get(); + *val= o & ~v; + } +} + + +/* End of stm8.src/rst.cc */ diff --git a/sim/ucsim/stm8.src/rst.o b/sim/ucsim/stm8.src/rst.o Binary files differnew file mode 100644 index 0000000..e7a0f09 --- /dev/null +++ b/sim/ucsim/stm8.src/rst.o diff --git a/sim/ucsim/stm8.src/rstcl.h b/sim/ucsim/stm8.src/rstcl.h new file mode 100644 index 0000000..b648073 --- /dev/null +++ b/sim/ucsim/stm8.src/rstcl.h @@ -0,0 +1,57 @@ +/* + * Simulator of microcontrollers (stm8.src/rstcl.h) + * + * Copyright (C) 2016,16 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#ifndef STM8_RSTCL_HEADER +#define STM8_RSTCL_HEADER + +// sim +#include "hwcl.h" + + +class cl_rst: public cl_hw +{ + public: + t_addr base; + class cl_memory_cell *rst_sr; + t_mem mask; + public: + cl_rst(class cl_uc *auc, t_addr abase, t_mem amask); + //virtual ~cl_rst(void); + virtual int init(void); + + //virtual void new_hw_added(class cl_hw *new_hw); + //virtual void added_to_uc(void); + virtual t_mem read(class cl_memory_cell *cell); + virtual void write(class cl_memory_cell *cell, t_mem *val); + + //virtual int tick(int cycles); +}; + + +#endif + +/* End of stm8.src/rstcl.cc */ diff --git a/sim/ucsim/stm8.src/serial.cc b/sim/ucsim/stm8.src/serial.cc new file mode 100644 index 0000000..ff4a959 --- /dev/null +++ b/sim/ucsim/stm8.src/serial.cc @@ -0,0 +1,440 @@ +/* + * Simulator of microcontrollers (serial.cc) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#include "ddconfig.h" + +#include <stdio.h> +#include <stdlib.h> +#include <ctype.h> +#include <errno.h> +#include <fcntl.h> +#include <sys/time.h> +#include <strings.h> + +// prj +#include "globals.h" +#include "utils.h" + +// cmd +#include "cmdutil.h" + +// sim +#include "itsrccl.h" + +// local +#include "clkcl.h" +#include "serialcl.h" + + +enum reg_idx { + sr = 0, + dr = 1, + brr1 = 2, + brr2 = 3, + cr1 = 4, + cr2 = 5, + cr3 = 6, + cr4 = 7, + cr5 = 8, + cr6 = 9, + gtr = 10, + pscr = 11 +}; + + +cl_serial::cl_serial(class cl_uc *auc, + t_addr abase, + int ttype, int atxit, int arxit): + cl_serial_hw(auc, ttype, "uart") +{ + type= ttype; + base= abase; + txit= atxit; + rxit= arxit; +} + + +cl_serial::~cl_serial(void) +{ +} + +int +cl_serial::init(void) +{ + int i; + class cl_it_src *is; + + set_name("stm8_uart"); + cl_serial_hw::init(); + clk_enabled= false; + for (i= 0; i < 12; i++) + { + regs[i]= register_cell(uc->rom, base+i); + } + pick_div(); + pick_ctrl(); + + uc->it_sources->add(is= new cl_it_src(uc, txit, + regs[cr2], 0x80, + regs[sr], 0x80, + 0x8008+txit*4, false, false, + chars("", "usart%d transmit register empty", id), 20*10+1)); + is->init(); + uc->it_sources->add(is= new cl_it_src(uc, txit, + regs[cr2], 0x40, + regs[sr], 0x40, + 0x8008+txit*4, false, false, + chars("", "usart%d transmit complete", id), 20*10+2)); + is->init(); + uc->it_sources->add(is= new cl_it_src(uc, rxit, + regs[cr2], 0x20, + regs[sr], 0x20, + 0x8008+rxit*4, false, false, + chars("", "usart%d receive", id), 20*10+3)); + is->init(); + + sr_read= false; + + return(0); +} + + +void +cl_serial::new_hw_added(class cl_hw *new_hw) +{ +} + +void +cl_serial::added_to_uc(void) +{ +} + +t_mem +cl_serial::read(class cl_memory_cell *cell) +{ + if (cell == regs[dr]) + { + if (sr_read) + regs[sr]->set_bit0(0x1f); + regs[sr]->set_bit0(0x20); + cfg_set(serconf_able_receive, 1); + return s_in; + } + sr_read= (cell == regs[sr]); + conf(cell, NULL); + return cell->get(); +} + +void +cl_serial::write(class cl_memory_cell *cell, t_mem *val) +{ + if (conf(cell, val)) + return; + if (cell == regs[sr]) + { + u8_t v= cell->get(); + if ((*val & 0x40) == 0) + { + v&= ~0x40; + *val= v; + } + } + else + { + cell->set(*val); + if ((cell == regs[brr1]) || + (cell == regs[brr2])) + { + pick_div(); + } + else if ((cell == regs[cr1]) || + (cell == regs[cr2])) + { + pick_ctrl(); + } + + else if (cell == regs[dr]) + { + s_txd= *val; + s_tx_written= true; + show_writable(false); + if (sr_read) + show_tx_complete(false); + if (!s_sending) + { + start_send(); + } + } + } + + sr_read= false; +} + +t_mem +cl_serial::conf_op(cl_memory_cell *cell, t_addr addr, t_mem *val) +{ + if (addr < serconf_common) + return cl_serial_hw::conf_op(cell, addr, val); + switch ((enum serial_cfg)addr) + { + /* + case serial_: + if (val) + { + if (*val) + on= true; + else + on= false; + } + else + { + cell->set(on?1:0); + } + break; + */ + default: + break; + } + return cell->get(); +} + +int +cl_serial::tick(int cycles) +{ + char c; + + if (!en || + !clk_enabled) + return 0; + + if ((mcnt+= cycles) >= div) + { + mcnt-= div; + if (ten) + s_tr_bit++; + if (ren) + s_rec_bit++; + } + else + return 0; + + if (s_sending && + (s_tr_bit >= bits)) + { + s_sending= false; + //io->dd_printf("%c", s_out); + io->write((char*)&s_out, 1); + s_tr_bit-= bits; + if (s_tx_written) + restart_send(); + else + finish_send(); + } + if ((ren) && + io->get_fin() && + !s_receiving) + { + if (cfg_get(serconf_check_often)) + { + if (io->input_avail()) + io->proc_input(0); + } + if (input_avail) + { + s_receiving= true; + s_rec_bit= 0; + } + else + show_idle(true); + } + if (s_receiving && + (s_rec_bit >= bits)) + { + { + c= input; + input_avail= false; + s_in= c; + received(); + } + s_receiving= false; + s_rec_bit-= bits; + } + + return(0); +} + +void +cl_serial::start_send() +{ + if (ten) + { + s_out= s_txd; + s_tx_written= false; + s_sending= true; + s_tr_bit= 0; + show_writable(true); + } +} + +void +cl_serial::restart_send() +{ + if (ten) + { + s_out= s_txd; + s_tx_written= false; + s_sending= true; + s_tr_bit= 0; + show_writable(true); + } +} + +void +cl_serial::finish_send() +{ + show_writable(true); + show_tx_complete(true); +} + +void +cl_serial::received() +{ + set_dr(s_in); + cfg_write(serconf_received, s_in); + if (regs[sr]->get() & 0x20) + regs[sr]->set_bit1(0x08); // overrun + show_readable(true); +} + +void +cl_serial::reset(void) +{ + int i; + regs[sr]->set(0xc0); + for (i= 2; i < 12; i++) + regs[i]->set(0); +} + +void +cl_serial::happen(class cl_hw *where, enum hw_event he, + void *params) +{ + if ((he == EV_CLK_ON) || + (he == EV_CLK_OFF)) + { + cl_clk_event *e= (cl_clk_event *)params; + if ((e->cath == HW_UART) && + (e->id == id)) + clk_enabled= he == EV_CLK_ON; + } +} + +void +cl_serial::pick_div() +{ + u8_t b1= regs[brr1]->get(); + u8_t b2= regs[brr2]->get(); + div= ((((b2&0xf0)<<4) + b1)<<4) + (b2&0xf); + mcnt= 0; +} + +void +cl_serial::pick_ctrl() +{ + u8_t c1= regs[cr1]->get(); + u8_t c2= regs[cr2]->get(); + en= !(c1 & 0x20); + ten= c2 & 0x08; + ren= c2 & 0x04; + bits= 10; + s_rec_bit= s_tr_bit= 0; + s_receiving= false; + s_tx_written= false; +} + +void +cl_serial::show_writable(bool val) +{ + if (val) + // TXE=1 + regs[sr]->write_bit1(0x80); + else + // TXE=0 + regs[sr]->write_bit0(0x80); +} + +void +cl_serial::show_readable(bool val) +{ + if (val) + regs[sr]->write_bit1(0x20); + else + regs[sr]->write_bit0(0x20); +} + +void +cl_serial::show_tx_complete(bool val) +{ + if (val) + regs[sr]->write_bit1(0x40); + else + regs[sr]->write_bit0(0x40); +} + +void +cl_serial::show_idle(bool val) +{ + if (val) + regs[sr]->write_bit1(0x10); + else + regs[sr]->write_bit0(0x10); +} + +void +cl_serial::set_dr(t_mem val) +{ + regs[dr]->set(val); +} + +void +cl_serial::print_info(class cl_console_base *con) +{ + con->dd_printf("%s[%d] at 0x%06x %s\n", id_string, id, base, on?"on":"off"); + con->dd_printf("clk %s\n", clk_enabled?"enabled":"disabled"); + con->dd_printf("Input: "); + class cl_f *fin= io->get_fin(), *fout= io->get_fout(); + if (fin) + con->dd_printf("%s/%d ", fin->get_file_name(), fin->file_id); + con->dd_printf("Output: "); + if (fout) + con->dd_printf("%s/%d", fout->get_file_name(), fout->file_id); + con->dd_printf("\n"); + print_cfg_info(con); +} + + +/* End of stm8.src/serial.cc */ diff --git a/sim/ucsim/stm8.src/serial.o b/sim/ucsim/stm8.src/serial.o Binary files differnew file mode 100644 index 0000000..7c284b0 --- /dev/null +++ b/sim/ucsim/stm8.src/serial.o diff --git a/sim/ucsim/stm8.src/serialcl.h b/sim/ucsim/stm8.src/serialcl.h new file mode 100644 index 0000000..7c4dbf8 --- /dev/null +++ b/sim/ucsim/stm8.src/serialcl.h @@ -0,0 +1,102 @@ +/* + * Simulator of microcontrollers (serialcl.h) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#ifndef STM8_SERIALCL_HEADER +#define STM8_SERIALCL_HEADER + +#include "fiocl.h" +#include "stypes.h" +#include "pobjcl.h" + +#include "uccl.h" +#include "serial_hwcl.h" + +#include "newcmdposixcl.h" + + +class cl_serial_listener; + +class cl_serial: public cl_serial_hw +{ + protected: + bool clk_enabled; + t_addr base; + int type, txit, rxit; + class cl_memory_cell *regs[12]; + int div; + int mcnt; + bool sr_read; // last op was read of SR + u8_t s_in; // Serial channel input reg + u8_t s_out; // Serial channel output reg + u8_t s_txd; // TX data register + bool s_sending; // Transmitter is working (s_out is not empty) + bool s_receiving; // Receiver is working (s_in is shifting) + bool s_tx_written; // TX data reg has been written + int s_rec_bit; // Bit counter of receiver + int s_tr_bit; // Bit counter of transmitter + uchar bits; // Nr of bits to send/receive + bool ren; // Receiving is enabled + bool ten; // Transmitter is enabled + bool en; // USART is enabled + public: + cl_serial(class cl_uc *auc, + t_addr abase, + int ttype, int atxit, int arxit); + virtual ~cl_serial(void); + virtual int init(void); + virtual int cfg_size(void) { return 10; } + + virtual void new_hw_added(class cl_hw *new_hw); + virtual void added_to_uc(void); + virtual t_mem read(class cl_memory_cell *cell); + virtual void write(class cl_memory_cell *cell, t_mem *val); + virtual t_mem conf_op(cl_memory_cell *cell, t_addr addr, t_mem *val); + + virtual int tick(int cycles); + virtual void start_send(); + virtual void restart_send(); + virtual void finish_send(); + virtual void received(); + virtual void reset(void); + virtual void happen(class cl_hw *where, enum hw_event he, + void *params); + + virtual void pick_div(); + virtual void pick_ctrl(); + virtual void show_writable(bool val); + virtual void show_readable(bool val); + virtual void show_tx_complete(bool val); + virtual void show_idle(bool vol); + virtual void set_dr(t_mem val); + + virtual void print_info(class cl_console_base *con); +}; + + +#endif + +/* End of stm8.src/serialcl.h */ diff --git a/sim/ucsim/stm8.src/simstm8.cc b/sim/ucsim/stm8.src/simstm8.cc new file mode 100644 index 0000000..d8858bc --- /dev/null +++ b/sim/ucsim/stm8.src/simstm8.cc @@ -0,0 +1,75 @@ +/* + * Simulator of microcontrollers (simstm8.cc) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +// prj +#include "globals.h" + +// local +#include "simstm8cl.h" +#include "stm8cl.h" + + +cl_simstm8::cl_simstm8(class cl_app *the_app): + cl_sim(the_app) +{} + +class cl_uc * +cl_simstm8::mk_controller(void) +{ + int i; + char *typ= 0; + class cl_optref type_option(this); + + type_option.init(); + type_option.use(cchars("cpu_type")); + i= 0; + if ((typ= type_option.get_value(typ)) == 0) + typ= cchars("STM8S"); + while ((cpus_stm8[i].type_str != NULL) && + (strcasecmp(typ, cpus_stm8[i].type_str) != 0)) + i++; + if (cpus_stm8[i].type_str == NULL) + { + fprintf(stderr, "Unknown processor type. " + "Use -H option to see known types.\n"); + return(NULL); + } + switch (cpus_stm8[i].type) + { + case CPU_STM8S: + case CPU_STM8L: + case CPU_STM8L101: + return(new cl_stm8(&cpus_stm8[i], this)); + default: + fprintf(stderr, "Unknown processor type\n"); + return NULL; + } + return NULL; +} + + +/* End of stm8.src/simstm8.cc */ diff --git a/sim/ucsim/stm8.src/simstm8.o b/sim/ucsim/stm8.src/simstm8.o Binary files differnew file mode 100644 index 0000000..158db27 --- /dev/null +++ b/sim/ucsim/stm8.src/simstm8.o diff --git a/sim/ucsim/stm8.src/simstm8cl.h b/sim/ucsim/stm8.src/simstm8cl.h new file mode 100644 index 0000000..7a36e06 --- /dev/null +++ b/sim/ucsim/stm8.src/simstm8cl.h @@ -0,0 +1,45 @@ +/* + * Simulator of microcontrollers (simstm8cl.h) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#ifndef SIMSTM8CL_HEADER +#define SIMSTM8CL_HEADER + +#include "simcl.h" + + +class cl_simstm8: public cl_sim +{ +public: + cl_simstm8(class cl_app *the_app); + + virtual class cl_uc *mk_controller(void); +}; + + +#endif + +/* End of stm8.src/simstm8cl.h */ diff --git a/sim/ucsim/stm8.src/sstm8 b/sim/ucsim/stm8.src/sstm8 Binary files differnew file mode 100755 index 0000000..2c51c66 --- /dev/null +++ b/sim/ucsim/stm8.src/sstm8 diff --git a/sim/ucsim/stm8.src/sstm8.cc b/sim/ucsim/stm8.src/sstm8.cc new file mode 100644 index 0000000..046fa17 --- /dev/null +++ b/sim/ucsim/stm8.src/sstm8.cc @@ -0,0 +1,57 @@ +/* + * Simulator of microcontrollers (sstm8.cc) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +// prj +#include "globals.h" + +// sim.src +#include "appcl.h" + +// local +#include "simstm8cl.h" + + +int +main(int argc, char *argv[]) +{ + class cl_sim *sim; + + cpus= cpus_stm8; + application= new cl_app(); + application->init(argc, argv); + sim= new cl_simstm8(application); + if (sim->init()) + sim->state|= SIM_QUIT; + application->set_simulator(sim); + application->run(); + application->done(); + delete application; + return(0); +} + + +/* End of stm8.src/sstm8.cc */ diff --git a/sim/ucsim/stm8.src/sstm8.o b/sim/ucsim/stm8.src/sstm8.o Binary files differnew file mode 100644 index 0000000..07b8ba1 --- /dev/null +++ b/sim/ucsim/stm8.src/sstm8.o diff --git a/sim/ucsim/stm8.src/stm8.cc b/sim/ucsim/stm8.src/stm8.cc new file mode 100644 index 0000000..7f98e8d --- /dev/null +++ b/sim/ucsim/stm8.src/stm8.cc @@ -0,0 +1,2054 @@ +/* + * Simulator of microcontrollers (stm8.cc) + * + * some stm8 code base from Karl Bongers karl@turbobit.com + * and Valentin Dudouyt valentin.dudouyt@gmail.com + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#include "ddconfig.h" + +#include <stdarg.h> /* for va_list */ +#include <stdio.h> +#include <stdlib.h> +#include <ctype.h> +#include "i_string.h" + +// prj +#include "pobjcl.h" +#include "globals.h" + +// sim +#include "simcl.h" + +// local +#include "stm8cl.h" +#include "glob.h" +#include "regsstm8.h" +#include "stm8mac.h" +#include "itccl.h" +#include "serialcl.h" +#include "rstcl.h" +#include "timercl.h" +#include "portcl.h" +#include "clkcl.h" +#include "uidcl.h" +#include "bl.h" +#include "flashcl.h" + +/*******************************************************************/ + + +/* + * Base type of STM8 controllers + */ + +cl_stm8::cl_stm8(struct cpu_entry *IType, class cl_sim *asim): + cl_uc(asim) +{ + type= IType; + flash_ctrl= NULL; +} + +int +cl_stm8::init(void) +{ + cl_uc::init(); /* Memories now exist */ + + xtal = 8000000; + + //rom = address_space(MEM_ROM_ID); + //ram = mem(MEM_XRAM); + //ram = rom; + + //printf("******************** leave the RAM dirty now \n"); + // zero out ram(this is assumed in regression tests) + //for (int i=0x0; i<0x8000; i++) { + // ram->set((t_addr) i, 0); + //} + + trap_src= new cl_it_src(this, -1, + (cl_memory_cell*)NULL, (t_mem)0, + (cl_memory_cell*)NULL, (t_mem)0, + (t_addr)0x8004, + false, false, + "trap", 0); + trap_src->init(); + return(0); +} + + +void +cl_stm8::reset(void) +{ + cl_uc::reset(); + + regs.SP = 0x17ff; + regs.A = 0; + regs.X = 0; + regs.Y = 0; + regs.CC = 0x28; + //regs.VECTOR = 1; + PC= 0x8000; +} + + +char * +cl_stm8::id_string(void) +{ + switch (type->type) + { + case CPU_STM8S: + return((char*)"STM8 S,AF"); + case CPU_STM8L: + return((char*)"STM8 AL,L"); + case CPU_STM8L101: + return((char*)"STM8 L101"); + default: + return((char*)"STM8"); + } +} + + +/* + * Making elements of the controller + */ +/* +t_addr +cl_stm8::get_mem_size(enum mem_class type) +{ + switch(type) + { + case MEM_ROM: return(0x10000); + case MEM_XRAM: return(0x10000); + default: return(0); + } + return(cl_uc::get_mem_size(type)); +} +*/ + + /* + L15x46 uid: 0x4926 00 5b 00 16 11 47 30 31 38 35 35 36 + */ + +static class cl_port_ui *d= NULL; +static int puix= 1; +static int puiy= 4; +static int puik= 0; +static int puis= 1; +static const char *puiks= keysets[puik]; +static class cl_port_data pd; + +void +cl_stm8::mk_port(t_addr base, chars n) +{ + class cl_port *p; + add_hw(p= new cl_port(this, base, n)); + p->init(); + + pd.set_name(n); + pd.cell_p = p->cell_p; + pd.cell_in = p->cell_in; + pd.cell_dir= p->cell_dir; + pd.keyset = chars(puiks); + pd.basx = puix; + pd.basy = puiy; + d->add_port(&pd, puis++); + + if ((puix+= 20) > 80) + { + puix= 1; + if ((puiy+= 7) > 20) + ; + } + if ((puik+= 1) > 7) + puiks= NULL; + else + puiks= keysets[puik]; +} + +void +cl_stm8::mk_hw_elements(void) +{ + class cl_hw *h; + cl_uc::mk_hw_elements(); + class cl_option *o; + + if ((o= application->options->get_option("serial1_in_file")) == NULL) + { + o= new cl_string_option(this, "serial1_in_file", + "Input file for serial line uart1 (-S)"); + application->options->new_option(o); + o->init(); + o->hide(); + } + if ((o= application->options->get_option("serial1_out_file")) == NULL) + { + o= new cl_string_option(this, "serial1_out_file", + "Output file for serial line uart1 (-S)"); + application->options->new_option(o); + o->init(); + o->hide(); + } + + if ((o= application->options->get_option("serial2_in_file")) == NULL) + { + o= new cl_string_option(this, "serial2_in_file", + "Input file for serial line uart2 (-S)"); + application->options->new_option(o); + o->init(); + o->hide(); + } + if ((o= application->options->get_option("serial2_out_file")) == NULL) + { + o= new cl_string_option(this, "serial2_out_file", + "Output file for serial line uart2 (-S)"); + application->options->new_option(o); + o->init(); + o->hide(); + } + + if ((o= application->options->get_option("serial3_in_file")) == NULL) + { + o= new cl_string_option(this, "serial3_in_file", + "Input file for serial line uart3 (-S)"); + application->options->new_option(o); + o->init(); + o->hide(); + } + if ((o= application->options->get_option("serial3_out_file")) == NULL) + { + o= new cl_string_option(this, "serial3_out_file", + "Output file for serial line uart3 (-S)"); + application->options->new_option(o); + o->init(); + o->hide(); + } + + if ((o= application->options->get_option("serial4_in_file")) == NULL) + { + o= new cl_string_option(this, "serial4_in_file", + "Input file for serial line uart4 (-S)"); + application->options->new_option(o); + o->init(); + o->hide(); + } + if ((o= application->options->get_option("serial4_out_file")) == NULL) + { + o= new cl_string_option(this, "serial4_out_file", + "Output file for serial line uart4 (-S)"); + application->options->new_option(o); + o->init(); + o->hide(); + } + + add_hw(d= new cl_port_ui(this, 0, "dport")); + d->init(); + pd.init(); + + add_hw(h= new cl_stm8_cpu(this)); + h->init(); + + if (type->type == CPU_STM8S) + { + add_hw(h= new cl_clk_saf(this)); + h->init(); + if (type->subtype & (DEV_STM8S003| + DEV_STM8S007| + DEV_STM8S103| + DEV_STM8S207| + DEV_STM8S208| + DEV_STM8S903| + DEV_STM8AF52)) + { + add_hw(h= new cl_serial(this, 0x5230, 1, 17, 18)); + h->init(); + } + if (type->subtype & (DEV_STM8S005| + DEV_STM8S105| + DEV_STM8AF62_46)) + { + add_hw(h= new cl_serial(this, 0x5240, 2, 20, 21)); + h->init(); + } + if (type->subtype & (DEV_STM8S007| + DEV_STM8S207| + DEV_STM8S208| + DEV_STM8AF52)) + { + add_hw(h= new cl_serial(this, 0x5240, 3, 20, 21)); + h->init(); + } + if (type->subtype & (DEV_STM8AF62_12)) + { + add_hw(h= new cl_serial(this, 0x5230, 4, 17, 18)); + h->init(); + } + } + if (type->type == CPU_STM8L) + { + add_hw(h= new cl_clk_all(this)); + h->init(); + add_hw(h= new cl_serial(this, 0x5230, 1, 27, 28)); + h->init(); + if (type->subtype & (DEV_STM8AL3xE| + DEV_STM8AL3x8| + DEV_STM8L052R| + DEV_STM8L15x8| + DEV_STM8L162)) + { + add_hw(h= new cl_serial(this, 0x53e0, 2, 19, 20)); + h->init(); + } + if (type->subtype & (DEV_STM8AL3xE| + DEV_STM8AL3x8| + DEV_STM8L052R| + DEV_STM8L15x8| + DEV_STM8L162)) + { + add_hw(h= new cl_serial(this, 0x53f0, 3, 21, 22)); + h->init(); + } + } + if (type->type == CPU_STM8L101) + { + add_hw(h= new cl_clk_l101(this)); + h->init(); + add_hw(h= new cl_serial(this, 0x5230, 1, 27, 28)); + h->init(); + } + + add_hw(itc= new cl_itc(this)); + itc->init(); + + { + mk_port(0x5000, "pa"); + mk_port(0x5005, "pb"); + mk_port(0x500a, "pc"); + mk_port(0x500f, "pd"); + } + + if (type->type == CPU_STM8S) + { + // all S and AF + mk_port(0x5014, "pe"); + mk_port(0x5019, "pf"); + if (type->subtype & (DEV_STM8S005| + DEV_STM8S007| + DEV_STM8S105| + DEV_STM8S207| + DEV_STM8S208| + DEV_STM8AF52| + DEV_STM8AF62_46)) + { + mk_port(0x501e, "pg"); + if (type->subtype != DEV_STM8AF62_46) + { + mk_port(0x5023, "ph"); + mk_port(0x5028, "pi"); + } + } + add_hw(h= new cl_rst(this, 0x50b3, 0x1f)); + h->init(); + add_hw(h= new cl_tim1_saf(this, 1, 0x5250)); + h->init(); + // some S, some AF + if (type->subtype & (DEV_STM8S005| + DEV_STM8S007| + DEV_STM8S105| + DEV_STM8S207| + DEV_STM8S208| + DEV_STM8AF52| + DEV_STM8AF62_46)) + { + add_hw(h= new cl_tim2_saf_a(this, 2, 0x5300)); + h->init(); + add_hw(h= new cl_tim3_saf(this, 3, 0x5320)); + h->init(); + add_hw(h= new cl_tim4_saf_a(this, 4, 0x5340)); + h->init(); + } + if (type->subtype & (DEV_STM8S903| + DEV_STM8AF62_12)) + { + add_hw(h= new cl_tim5_saf(this, 5, 0x5300)); + h->init(); + add_hw(h= new cl_tim6_saf(this, 6, 0x5340)); + h->init(); + } + if (type->subtype & (DEV_STM8S003| + DEV_STM8S103)) + { + add_hw(h= new cl_tim2_saf_b(this, 2, 0x5300)); + h->init(); + // tim4 B + add_hw(h= new cl_tim4_saf_b(this, 4, 0x5340)); + h->init(); + } + } + else if (type->type == CPU_STM8L) + { + if (type->subtype != DEV_STM8L051) + { + mk_port(0x5014, "pe"); + mk_port(0x5019, "pf"); + } + if (type->subtype & (DEV_STM8AL3xE| + DEV_STM8AL3x8| + DEV_STM8L052R| + DEV_STM8L15x8| + DEV_STM8L162)) + { + mk_port(0x501e, "pg"); + if (type->subtype != DEV_STM8L052R) + { + mk_port(0x5023, "ph"); + mk_port(0x5028, "pi"); + } + } + add_hw(h= new cl_rst(this, 0x50b0+1, 0x3f)); + h->init(); + add_hw(h= new cl_tim2_all(this, 2, 0x5250)); + h->init(); + add_hw(h= new cl_tim3_all(this, 3, 0x5280)); + h->init(); + add_hw(h= new cl_tim4_all(this, 4, 0x52E0)); + h->init(); + // all AL + if (type->subtype & DEV_STM8AL) + { + add_hw(h= new cl_tim1_all(this, 1, 0x52b0)); + h->init(); + } + // some L + if (type->subtype & (DEV_STM8L052C | + DEV_STM8L052R | + DEV_STM8L15x46 | + DEV_STM8L15x8 | + DEV_STM8L162)) + { + add_hw(h= new cl_tim1_all(this, 1, 0x52b0)); + h->init(); + } + if (type->subtype & (DEV_STM8AL3xE | + DEV_STM8AL3x8 | + DEV_STM8L052R | + DEV_STM8L15x8 | + DEV_STM8L162)) + { + add_hw(h= new cl_tim5_all(this, 5, 0x5300)); + h->init(); + } + } + else if (type->type == CPU_STM8L101) + { + add_hw(h= new cl_rst(this, 0x50b0+1, 0x0f)); + h->init(); + add_hw(h= new cl_tim2_l101(this, 2, 0x5250)); + h->init(); + add_hw(h= new cl_tim3_l101(this, 2, 0x5280)); + h->init(); + add_hw(h= new cl_tim4_l101(this, 4, 0x52E0)); + h->init(); + } + + // UID + if (type->subtype & (DEV_STM8S103 | + DEV_STM8S903 | + DEV_STM8AF62_12)) + { + add_hw(h= new cl_uid(this, 0x4865)); + h->init(); + } + else if (type->subtype & (DEV_STM8AL | + DEV_STM8L151x23 | + DEV_STM8L15x46 | + DEV_STM8L15x8 | + DEV_STM8L162)) + { + add_hw(h= new cl_uid(this, 0x4926)); + h->init(); + } + else if (type->subtype & (DEV_STM8L101)) + { + add_hw(h= new cl_uid(this, 0x4925)); + h->init(); + } + + // FLASH + if (type->subtype & (DEV_STM8SAF)) + { + add_hw(flash_ctrl= new cl_saf_flash(this, 0x505a)); + flash_ctrl->init(); + } + else if (type->subtype & (DEV_STM8ALL | + DEV_STM8L101)) + { + add_hw(flash_ctrl= new cl_l_flash(this, 0x5050)); + flash_ctrl->init(); + } + //add_hw(h= new cl_tim235(this, 3, 0x5320)); + //h->init(); + //add_hw(h= new cl_tim46(this, 4, 0x5340)); + //h->init(); +} + +class cl_memory_chip *c; + +void +cl_stm8::make_memories(void) +{ + class cl_address_space *as; + + rom= ram= as= new cl_flash_as/*address_space*/("rom", 0, 0x28000/*, 8*/); + as->init(); + address_spaces->add(as); + + class cl_address_decoder *ad; + class cl_memory_chip /* *chip,*/ *rom_chip; + + c= rom_chip= NULL;/*new cl_memory_chip("rom_chip", 0x20000, 8, 0); + rom_chip->init(); + memchips->add(rom_chip);*/ + + ram_chip= new cl_memory_chip("ram_chip", 0x1800, 8); + ram_chip->init(); + memchips->add(ram_chip); + eeprom_chip= new cl_memory_chip("eeprom_chip", 0x0800, 8, 0); + eeprom_chip->init(); + memchips->add(eeprom_chip); + option_chip= new cl_memory_chip("option_chip", 0x0800, 8, 0); + option_chip->init(); + memchips->add(option_chip); + io_chip= new cl_memory_chip("io_chip", 0x0800, 8); + io_chip->init(); + memchips->add(io_chip); + if (type->subtype & DEV_STM8S105) + boot_chip= new cl_memory_chip("boot_chip_s105", bl_s105_length, 8, bl_s105); + else if (type->subtype & DEV_STM8L15x46) + boot_chip= new cl_memory_chip("boot_chip_l15x46", bl_l15x46_length, 8, bl_l15x46); + /*else if (type->subtype & DEV_STM8L101) + boot_chip= new cl_memory_chip("boot_chip_l101", bl_l15x46_length, 8, bl_l15x46);*/ + else + boot_chip= new cl_memory_chip("boot_chip", 0x0800, 8); + boot_chip->init(); + memchips->add(boot_chip); + cpu_chip= new cl_memory_chip("cpu_chip", 0x0100, 8); + cpu_chip->init(); + memchips->add(cpu_chip); + flash_chip= new cl_memory_chip("flash_chip", 0x20000, 8, 0); + flash_chip->init(); + memchips->add(flash_chip); + /* + ad= new cl_address_decoder(as= address_space("rom"), rom_chip, 0, 0x1ffff, 0); + ad->init(); + as->decoders->add(ad); + ad->activate(0); + */ + ad= new cl_address_decoder(as= rom, ram_chip, 0, 0x17ff, 0); + ad->init(); + as->decoders->add(ad); + ad->activate(0); + + ad= new cl_address_decoder(as= rom, eeprom_chip, 0x4000, 0x47ff, 0); + ad->init(); + as->decoders->add(ad); + ad->activate(0); + + ad= new cl_address_decoder(as= rom, option_chip, 0x4800, 0x4fff, 0); + ad->init(); + as->decoders->add(ad); + ad->activate(0); + + ad= new cl_address_decoder(as= rom, io_chip, 0x5000, 0x57ff, 0); + ad->init(); + as->decoders->add(ad); + ad->activate(0); + + ad= new cl_address_decoder(as= rom, boot_chip, 0x6000, 0x67ff, 0); + ad->init(); + as->decoders->add(ad); + ad->activate(0); + rom->set_cell_flag(0x6000, 0x67ff, true, CELL_READ_ONLY); + + ad= new cl_address_decoder(as= rom, cpu_chip, 0x7f00, 0x7fff, 0); + ad->init(); + as->decoders->add(ad); + ad->activate(0); + + ad= new cl_address_decoder(as= rom, flash_chip, 0x8000, 0x27fff, 0); + ad->init(); + as->decoders->add(ad); + ad->activate(0); + class cl_option *o= application->options->get_option("writable_flash"); + bool wv= false; + if (o) + o->get_value(&wv); + if (!wv) + rom->set_cell_flag(0x8000, 0x27fff, true, CELL_READ_ONLY); + + regs8= new cl_address_space("regs8", 0, 2, 8); + regs8->init(); + regs8->get_cell(0)->decode((t_mem*)®s.A); + regs8->get_cell(1)->decode((t_mem*)®s.CC); + + regs16= new cl_address_space("regs16", 0, 3, 16); + regs16->init(); + + regs16->get_cell(0)->decode((t_mem*)®s.X); + regs16->get_cell(1)->decode((t_mem*)®s.Y); + regs16->get_cell(2)->decode((t_mem*)®s.SP); + + address_spaces->add(regs8); + address_spaces->add(regs16); + + class cl_var *v; + vars->add(v= new cl_var(cchars("A"), regs8, 0, "")); + v->init(); + vars->add(v= new cl_var(cchars("CC"), regs8, 1, "")); + v->init(); + + vars->add(v= new cl_var(cchars("X"), regs16, 0, "")); + v->init(); + vars->add(v= new cl_var(cchars("Y"), regs16, 1, "")); + v->init(); + vars->add(v= new cl_var(cchars("SP"), regs16, 2, "")); + v->init(); +} + + +/* + * Help command interpreter + */ + +struct dis_entry * +cl_stm8::dis_tbl(void) +{ + return(disass_stm8); +} + +/*struct name_entry * +cl_stm8::sfr_tbl(void) +{ + return(0); +}*/ + +/*struct name_entry * +cl_stm8::bit_tbl(void) +{ + //FIXME + return(0); +}*/ + +int +cl_stm8::inst_length(t_addr addr) +{ + int len = 0; + + get_disasm_info(addr, &len, NULL, NULL, NULL); + + return len; +} +int +cl_stm8::inst_branch(t_addr addr) +{ + int b; + + get_disasm_info(addr, NULL, &b, NULL, NULL); + + return b; +} + +bool +cl_stm8::is_call(t_addr addr) +{ + struct dis_entry *e; + + get_disasm_info(addr, NULL, NULL, NULL, &e); + + return e?(e->is_call):false; +} + +int +cl_stm8::longest_inst(void) +{ + return 5; +} + + + +const char * +cl_stm8::get_disasm_info(t_addr addr, + int *ret_len, + int *ret_branch, + int *immed_offset, + struct dis_entry **dentry) +{ + const char *b = NULL; + uint code; + int len = 0; + int immed_n = 0; + int i; + int start_addr = addr; + struct dis_entry *dis_e; + + code= rom->get(addr++); + dis_e = NULL; + + switch(code) { + /* here will be all the prefixes for STM8 */ + case 0x72 : + code= rom->get(addr++); + i= 0; + while ((code & disass_stm8_72[i].mask) != disass_stm8_72[i].code && + disass_stm8_72[i].mnemonic) + i++; + dis_e = &disass_stm8_72[i]; + b= disass_stm8_72[i].mnemonic; + if (b != NULL) + len += (disass_stm8_72[i].length + 1); + break; + + case 0x71 : + code= rom->get(addr++); + i= 0; + while ((code & disass_stm8_71[i].mask) != disass_stm8_71[i].code && + disass_stm8_71[i].mnemonic) + i++; + dis_e = &disass_stm8_71[i]; + b= disass_stm8_71[i].mnemonic; + if (b != NULL) + len += (disass_stm8_71[i].length + 1); + break; + + case 0x90 : + code= rom->get(addr++); + i= 0; + while ((code & disass_stm8_90[i].mask) != disass_stm8_90[i].code && + disass_stm8_90[i].mnemonic) + i++; + dis_e = &disass_stm8_90[i]; + b= disass_stm8_90[i].mnemonic; + if (b != NULL) + len += (disass_stm8_90[i].length + 1); + break; + + case 0x91 : + code= rom->get(addr++); + i= 0; + while ((code & disass_stm8_91[i].mask) != disass_stm8_91[i].code && + disass_stm8_91[i].mnemonic) + i++; + dis_e = &disass_stm8_91[i]; + b= disass_stm8_91[i].mnemonic; + if (b != NULL) + len += (disass_stm8_91[i].length + 1); + break; + + case 0x92 : + code= rom->get(addr++); + i= 0; + while ((code & disass_stm8_92[i].mask) != disass_stm8_92[i].code && + disass_stm8_92[i].mnemonic) + i++; + dis_e = &disass_stm8_92[i]; + b= disass_stm8_92[i].mnemonic; + if (b != NULL) + len += (disass_stm8_92[i].length + 1); + break; + + + default: + i= 0; + while ((code & disass_stm8[i].mask) != disass_stm8[i].code && + disass_stm8[i].mnemonic) + i++; + dis_e = &disass_stm8[i]; + b= disass_stm8[i].mnemonic; + if (b != NULL) + len += (disass_stm8[i].length); + break; + } + + if (ret_branch) { + *ret_branch = dis_e->branch; + } + + if (immed_offset) { + if (immed_n > 0) + *immed_offset = immed_n; + else *immed_offset = (addr - start_addr); + } + + if (len == 0) + len = 1; + + if (ret_len) + *ret_len = len; + + if (dentry) + *dentry= dis_e; + + return b; +} + +char * +cl_stm8::disass(t_addr addr, const char *sep) +{ + char work[256], temp[20]; + const char *b; + char *buf, *p, *t; + int len = 0; + int immed_offset = 0; + + + p= work; + + b = get_disasm_info(addr, &len, NULL, &immed_offset, NULL); + + if (b == NULL) { + buf= (char*)malloc(30); + strcpy(buf, "UNKNOWN/INVALID"); + return(buf); + } + + while (*b) + { + if (*b == '%') + { + b++; + switch (*(b++)) + { + case 's': // s signed byte immediate + sprintf(temp, "#%d", (char)rom->get(addr+immed_offset)); + ++immed_offset; + break; + case 'e': // e extended 24bit immediate operand + sprintf(temp, "#0x%06lx", + (ulong)((rom->get(addr+immed_offset)<<16) | + (rom->get(addr+immed_offset+1)<<8) | + (rom->get(addr+immed_offset+2))) ); + ++immed_offset; + ++immed_offset; + ++immed_offset; + break; + case 'w': // w word immediate operand + sprintf(temp, "#0x%04x", + (uint)((rom->get(addr+immed_offset)<<8) | + (rom->get(addr+immed_offset+1))) ); + ++immed_offset; + ++immed_offset; + break; + case 'b': // b byte immediate operand + sprintf(temp, "#0x%02x", (uint)rom->get(addr+immed_offset)); + ++immed_offset; + break; + case 'x': // x extended addressing + sprintf(temp, "0x%04x", + (uint)((rom->get(addr+immed_offset)<<8) | + (rom->get(addr+immed_offset+1))) ); + ++immed_offset; + ++immed_offset; + break; + case 'd': // d direct addressing + sprintf(temp, "0x%02x", (uint)rom->get(addr+immed_offset)); + ++immed_offset; + break; + case '3': // 3 24bit index offset + sprintf(temp, "0x%06lx", + (ulong)((rom->get(addr+immed_offset)<<16) | + (rom->get(addr+immed_offset+1)<<8) | + (rom->get(addr+immed_offset+2))) ); + ++immed_offset; + ++immed_offset; + ++immed_offset; + break; + case '2': // 2 word index offset + sprintf(temp, "0x%04x", + (uint)((rom->get(addr+immed_offset)<<8) | + (rom->get(addr+immed_offset+1))) ); + ++immed_offset; + ++immed_offset; + break; + case '1': // b byte index offset + sprintf(temp, "0x%02x", (uint)rom->get(addr+immed_offset)); + ++immed_offset; + break; + case 'p': // b byte index offset + { + long int base; + i8_t offs; + base= addr+immed_offset+1; + offs= rom->get(addr+immed_offset); + long int res= base+offs; + sprintf(temp, "0x%04lx", + /*(long int)(addr+immed_offset+1 + +(int)rom->get(addr+immed_offset))*/ + res + ); + ++immed_offset; + } + break; + default: + strcpy(temp, "?"); + break; + } + t= temp; + while (*t) + *(p++)= *(t++); + } + else + *(p++)= *(b++); + } + *p= '\0'; + + p= strchr(work, ' '); + if (!p) + { + buf= strdup(work); + return(buf); + } + if (sep == NULL) + buf= (char *)malloc(6+strlen(p)+1); + else + buf= (char *)malloc((p-work)+strlen(sep)+strlen(p)+1); + for (p= work, t= buf; *p != ' '; p++, t++) + *t= *p; + p++; + *t= '\0'; + if (sep == NULL) + { + while (strlen(buf) < 6) + strcat(buf, " "); + } + else + strcat(buf, sep); + strcat(buf, p); + return(buf); +} + + +void +cl_stm8::print_regs(class cl_console_base *con) +{ + con->dd_printf("V-IHINZC Flags= 0x%02x %3d %c ", + regs.CC, regs.CC, isprint(regs.CC)?regs.CC:'.'); + con->dd_printf("A= 0x%02x %3d %c\n", + regs.A, regs.A, isprint(regs.A)?regs.A:'.'); + con->dd_printf("%c-%c%c%c%c%c%c ", + (regs.CC&BIT_V)?'1':'0', + (regs.CC&BIT_I1)?'1':'0', + (regs.CC&BIT_H)?'1':'0', + (regs.CC&BIT_I0)?'1':'0', + (regs.CC&BIT_N)?'1':'0', + (regs.CC&BIT_Z)?'1':'0', + (regs.CC&BIT_C)?'1':'0'); + con->dd_printf("X= 0x%04x %3d %c ", + regs.X, regs.X, isprint(regs.X)?regs.X:'.'); + con->dd_printf("Y= 0x%04x %3d %c\n", + regs.Y, regs.Y, isprint(regs.Y)?regs.Y:'.'); + con->dd_printf("SP= 0x%04x [SP+1]= %02x %3d %c\n", + regs.SP, ram->get(regs.SP+1), ram->get(regs.SP+1), + isprint(ram->get(regs.SP+1))?ram->get(regs.SP+1):'.'); + + print_disass(PC, con); +} + +/* + * Execution + */ + +int +cl_stm8::exec_inst(void) +{ + t_mem code; + unsigned char cprefix; // prefix used for processing in functions + /* + if (regs.VECTOR) { + PC = get1(0x8000); + if (PC == 0x82) { // this is reserved opcode for vector table + regs.VECTOR = 0; + PC = get1(0x8001)*(1<<16); + PC += get2(0x8002); + return(resGO); + } else { + return( resERROR); + } + } + */ + + instPC= PC; + + if (fetch(&code)) { + //printf("******************** break \n"); + return(resBREAKPOINT); + } + tick(1); + + switch (code) + { // get prefix + case 0x72: + case 0x90: + case 0x91: + case 0x92: + cprefix = code; + fetch(&code); + break; + case 0x82: + { + int ce= fetch(); + int ch= fetch(); + int cl= fetch(); + PC= ce*0x10000 + ch*0x100 + cl; + return resGO; + } + case 0x8b: return resSTOP; // BREAK instruction + default: + cprefix = 0x00; + break; + } + + // exceptions + if((cprefix==0x90)&&((code&0xf0)==0x10)) { + return ( inst_bccmbcpl( code, cprefix)); + } + if((cprefix==0x72)&&((code&0xf0)==0x10)) { + return ( inst_bresbset( code, cprefix)); + } + if((cprefix==0x72)&&((code&0xf0)==0x00)) { + return ( inst_btjfbtjt( code, cprefix)); + } + if ((code &0xf0) == 0x20) { + return ( inst_jr( code, cprefix)); + } + if (cprefix == 0x72) { + switch (code) { + // addw + case 0xa9: + case 0xb9: + case 0xbb: + case 0xf9: + case 0xfb: + return( inst_addw( code, cprefix)); + // subw + case 0xa2: + case 0xb2: + case 0xb0: + case 0xf2: + case 0xf0: + return( inst_addw( code, cprefix)); + //default is processing in the next switch statement + default: + break; + } + } + + // main switch + switch (code & 0xf) { + unsigned int tempi; + int opaddr; + case 0x0: + switch ( code & 0xf0) { + case 0x00: + case 0x30: + case 0x40: + case 0x50: + case 0x60: + case 0x70: // neg + return( inst_neg( code, cprefix)); + break; + case 0x80: // IRET + pop1( regs.CC); + pop1( regs.A); + pop2( regs.X); + pop2( regs.Y); + pop1( tempi); + pop2( PC); + PC += (tempi <<16); //Add PCE to PC + { + class it_level *il= (class it_level *)(it_levels->top()); + if (il && + il->level >= 0) + { + il= (class it_level *)(it_levels->pop()); + delete il; + } + } + return(resGO); + case 0x10: + case 0xA0: + case 0xB0: + case 0xC0: + case 0xD0: + case 0xE0: + case 0xF0: // SUB + return( inst_sub( code, cprefix)); + default: + //printf("************* bad code !!!!\n"); + return(resINV_INST); + } + break; + case 0x1: + switch ( code & 0xf0) { + case 0x00: // RRWA + if (cprefix == 0x00) { // rrwa X,A + tempi = regs.X; + regs.X >>= 8; + regs.X |= (regs.A << 8); + regs.A = tempi & 0xff; + FLAG_ASSIGN (BIT_N, 0x8000 & regs.X); + FLAG_ASSIGN (BIT_Z, regs.X == 0x0000); + } else if (cprefix == 0x90) { // rrwa Y,A + tempi = regs.Y; + regs.Y >>= 8; + regs.Y |= (regs.A << 8); + regs.A = tempi & 0xff; + FLAG_ASSIGN (BIT_N, 0x8000 & regs.Y); + FLAG_ASSIGN (BIT_Z, regs.Y == 0x0000); + } else { + return(resHALT); + } + return(resGO); + break; + case 0x30: // exg A,longmem + opaddr = fetch2(); + tempi = get1(opaddr); + store1( opaddr, regs.A); + regs.A = tempi; + return(resGO); + case 0x40: // exg A,XL + tempi = regs.X; + regs.X = (regs.X &0xff00) | regs.A; + regs.A = tempi & 0xff; + return(resGO); + case 0x50: // exgw X,Y + tempi = regs.Y; + regs.Y = regs.X; + regs.X = tempi; + return(resGO); + case 0x60: // exg A,YL + tempi = regs.Y; + regs.Y = (regs.Y &0xff00) | regs.A; + regs.A = tempi & 0xff; + return(resGO); + case 0x70: // special opcodes + code = fetch(); + switch(code) { + case 0xEC: return(resHALT); + case 0xED: putchar(regs.A); fflush(stdout); return(resGO); + default: + //printf("************* bad code !!!!\n"); + return(resINV_INST); + } + case 0x80: // ret + pop2( PC); + return(resGO); + case 0x10: + case 0xA0: + case 0xB0: + case 0xC0: + case 0xD0: + case 0xE0: + case 0xF0: // CP + return( inst_cp( code, cprefix)); + break; + default: + //printf("************* bad code !!!!\n"); + return(resINV_INST); + } + break; + case 0x2: + switch ( code & 0xf0) { + case 0x00: // RLWA + if (cprefix == 0x00) { // rlwa X,A + tempi = regs.X; + regs.X <<= 8; + regs.X |= regs.A ; + regs.A = tempi >> 8; + FLAG_ASSIGN (BIT_N, 0x8000 & regs.X); + FLAG_ASSIGN (BIT_Z, regs.X == 0x0000); + } else if (cprefix == 0x90) { // rlwa Y,A + tempi = regs.Y; + regs.Y <<= 8; + regs.Y |= regs.A ; + regs.A = tempi >> 8; + FLAG_ASSIGN (BIT_N, 0x8000 & regs.Y); + FLAG_ASSIGN (BIT_Z, regs.Y == 0x0000); + } else { + return(resHALT); + } + return(resGO); + break; + case 0x30: // POP longmem + opaddr = fetch2(); + pop1(tempi); + store1(opaddr, tempi); + return(resGO); + case 0x40: // mul + tick(3); + if(cprefix==0x90) { + regs.Y = (regs.Y&0xff) * regs.A; + } else if(cprefix==0x00) { + regs.X = (regs.X&0xff) * regs.A; + } else { + return(resHALT); + } + FLAG_CLEAR(BIT_H); + FLAG_CLEAR(BIT_C); + return(resGO); + break; + case 0x50: // sub sp,#val + regs.SP -= fetch(); + return(resGO); + break; + case 0x60: //div + return(inst_div(code, cprefix)); + break; + case 0x10: + case 0xA0: + case 0xB0: + case 0xC0: + case 0xD0: + case 0xE0: + case 0xF0: // SBC + return( inst_sbc( code, cprefix)); + break; + default: + //printf("************* bad code !!!!\n"); + return(resINV_INST); + } + break; + case 0x3: + switch ( code & 0xf0) { + case 0x00: + case 0x30: + case 0x40: + case 0x50: + case 0x60: + case 0x70: // CPL, CPLW + return( inst_cpl( code, cprefix)); + break; + case 0x80: // TRAP + { + class it_level *il= new it_level(3, 0x8004, PC, trap_src); + accept_it(il); + } + return(/*resHALT*/resGO); + case 0x90: + if(cprefix==0x90) { + regs.Y = regs.X; + } else if(cprefix==0x00) { + regs.X = regs.Y; + } else { + return(resHALT); + } + return(resGO); + break; + case 0x10: + case 0xA0: + case 0xB0: + case 0xC0: + case 0xD0: + case 0xE0: + case 0xF0: // CPW + return( inst_cpw( code, cprefix)); + break; + default: + //printf("************* bad code !!!!\n"); + return(resINV_INST); + } + break; + case 0x4: + switch ( code & 0xf0) { + case 0x00: + case 0x30: + case 0x40: + case 0x50: + case 0x60: + case 0x70: // SRL + return( inst_srl( code, cprefix)); + break; + case 0x80: + pop1( regs.A); + return(resGO); + case 0x90: + if(cprefix==0x90) { + regs.SP = regs.Y; + } else if(cprefix==0x00) { + regs.SP = regs.X; + } else { + return(resHALT); + } + return(resGO); + break; + case 0x10: + case 0xA0: + case 0xB0: + case 0xC0: + case 0xD0: + case 0xE0: + case 0xF0: // AND + return( inst_and( code, cprefix)); + break; + default: + //printf("************* bad code !!!!\n"); + return(resINV_INST); + } + break; + case 0x5: + switch ( code & 0xf0) { + case 0x30: // MOV + tempi = fetch1(); + opaddr = fetch2(); + store1(opaddr, tempi); + return( resGO); + break; + case 0x40: + tempi = get1(fetch1()); + opaddr = fetch1(); + store1(opaddr, tempi); + return( resGO); + break; + case 0x50: + tempi = get1(fetch2()); + opaddr = fetch2(); + store1(opaddr, tempi); + return( resGO); + break; + case 0x60: // DIVW + return( inst_div( code, cprefix)); + break; + case 0x80: + if(cprefix==0x90) { + pop2(regs.Y); + } else if(cprefix==0x00) { + pop2(regs.X); + } else { + return(resHALT); + } + return(resGO); + break; + case 0x90: + if(cprefix==0x90) { + regs.Y = (regs.Y & 0xff) | (regs.A<<8); + } else if(cprefix==0x00) { + regs.X = (regs.X & 0xff) | (regs.A<<8); + } else { + return(resHALT); + } + return(resGO); + break; + case 0x10: + case 0xA0: + case 0xB0: + case 0xC0: + case 0xD0: + case 0xE0: + case 0xF0: // BCP + return( inst_bcp( code, cprefix)); + break; + default: + //printf("************* bad code !!!!\n"); + return(resINV_INST); + } + break; + case 0x6: + switch ( code & 0xf0) { + case 0x00: + case 0x30: + case 0x40: + case 0x50: + case 0x60: + case 0x70: // RRC + return( inst_rrc( code, cprefix)); + break; + case 0x10: + return(inst_ldxy( code, cprefix)); + break; + case 0x80: + pop1( regs.CC); + return(resGO); + case 0x90: + if(cprefix==0x90) { + regs.Y = regs.SP; + } else if(cprefix==0x00) { + regs.X = regs.SP; + } else { + return(resHALT); + } + return(resGO); + break; + case 0xA0: + case 0xB0: + case 0xC0: + case 0xD0: + case 0xE0: + case 0xF0: // LD A,... + return( inst_lda( code, cprefix)); + break; + default: + //printf("************* bad code !!!!\n"); + return(resINV_INST); + } + break; + case 0x7: + switch ( code & 0xf0) { + case 0x00: + case 0x30: + case 0x40: + case 0x50: + case 0x60: + case 0x70: // SRA + return( inst_sra( code, cprefix)); + break; + case 0x10: + opaddr = fetch1()+regs.SP; + store2(opaddr, regs.Y); + FLAG_ASSIGN (BIT_Z, (regs.Y & 0xffff) == 0x0000); + FLAG_ASSIGN (BIT_N, regs.Y & 0x8000); + return(resGO); + break; + case 0x80: // RETF + pop1( tempi); + pop2( PC); + PC += (tempi <<16); //Add PCE to PC + return(resGO); + case 0x90: + if(cprefix==0x90) { + regs.Y = (regs.Y & 0xff00) | regs.A; + } else if(cprefix==0x00) { + regs.X = (regs.X & 0xff00) | regs.A; + } else { + return(resHALT); + } + return(resGO); + break; + case 0xA0: + opaddr = fetch2(); + if (cprefix == 0x92) { + store1(get3(opaddr)+regs.X,regs.A); + } else if(cprefix==0x91) { + store1(get3(opaddr)+regs.Y,regs.A); + } else if(cprefix==0x90) { + store1((opaddr << 8) + fetch() + regs.Y, regs.A); + } else if(cprefix==0x00) { + store1((opaddr << 8) + fetch() + regs.X, regs.A); + } else { + return(resHALT); + } + FLAG_NZ (regs.A); + return(resGO); + case 0xB0: + case 0xC0: + case 0xD0: + case 0xE0: + case 0xF0: // LD dst,A + return( inst_lddst( code, cprefix)); + break; + default: + //printf("************* bad code !!!!\n"); + return(resINV_INST); + } + break; + case 0x8: + switch ( code & 0xf0) { + case 0x00: + case 0x30: + case 0x40: + case 0x50: + case 0x60: + case 0x70: // SLL + return( inst_sll( code, cprefix)); + break; + case 0x80: + push1( regs.A); + return(resGO); + case 0x90: // RCF + FLAG_CLEAR(BIT_C); + return(resGO); + case 0x10: + case 0xA0: + case 0xB0: + case 0xC0: + case 0xD0: + case 0xE0: + case 0xF0: // XOR + return( inst_xor( code, cprefix)); + break; + default: + //printf("************* bad code !!!!\n"); + return(resINV_INST); + } + break; + case 0x9: + switch ( code & 0xf0) { + case 0x00: + case 0x30: + case 0x40: + case 0x50: + case 0x60: + case 0x70: // RLC + return( inst_rlc( code, cprefix)); + break; + case 0x80: // PUSHW + if(cprefix==0x90) { + push2(regs.Y); + } else if(cprefix==0x00) { + push2(regs.X); + } else { + return(resHALT); + } + return(resGO); + break; + case 0x90: // SCF + FLAG_SET(BIT_C); + return(resGO); + case 0x10: + case 0xA0: + case 0xB0: + case 0xC0: + case 0xD0: + case 0xE0: + case 0xF0: // ADC + return( inst_adc( code, cprefix)); + break; + default: + //printf("************* bad code !!!!\n"); + return(resINV_INST); + } + break; + case 0xa: + switch ( code & 0xf0) { + case 0x00: + case 0x30: + case 0x40: + case 0x50: + case 0x60: + case 0x70: // DEC + return( inst_dec( code, cprefix)); + break; + case 0x80: + push1( regs.CC); + return(resGO); + case 0x90: // RIM + FLAG_CLEAR(BIT_I0); + FLAG_SET(BIT_I1); + return(resGO); + case 0x10: + case 0xA0: + case 0xB0: + case 0xC0: + case 0xD0: + case 0xE0: + case 0xF0: // OR + return( inst_or( code, cprefix)); + break; + default: + //printf("************* bad code !!!!\n"); + return(resINV_INST); + } + break; + case 0xb: + switch ( code & 0xf0) { + case 0x30: // push longmem + push1( get1(fetch2())); + return(resGO); + case 0x40: // push #byte + push1( fetch1()); + return(resGO); + case 0x50: // addw sp,#val + regs.SP += fetch1(); + return(resGO); + break; + case 0x60: // ld (shortoff,SP),A + store1(fetch1()+regs.SP, regs.A); + FLAG_NZ(regs.A); + return(resGO); + break; + case 0x70: // ld A,(shortoff,SP) + regs.A = get1(fetch1()+regs.SP); + FLAG_NZ(regs.A); + return(resGO); + break; + case 0x80: // BREAK + return(resSTOP); + case 0x90: // SIM - disable INT + FLAG_SET(BIT_I0); + FLAG_SET(BIT_I1); + return(resGO); + case 0x10: + case 0xA0: + case 0xB0: + case 0xC0: + case 0xD0: + case 0xE0: + case 0xF0: // ADD + return( inst_add( code, cprefix)); + break; + default: + //printf("************* bad code !!!!\n"); + return(resINV_INST); + } + break; + case 0xc: + switch ( code & 0xf0) { + case 0x00: + case 0x30: + case 0x40: + case 0x50: + case 0x60: + case 0x70: // INC + return( inst_inc( code, cprefix)); + break; + case 0x10: // ADDW X,#word + return( inst_addw( code, cprefix)); + break; + case 0x80: // CCF + regs.CC ^= BIT_C; + return(resGO); + break; + case 0x90: // RVF + FLAG_CLEAR(BIT_V); + return(resGO); + case 0xA0: // JPF + opaddr = fetch2(); + if (cprefix == 0x92) { + PC = get3(opaddr); + } else { + PC = (opaddr << 8) + fetch(); + } + return(resGO); + break; + case 0xb0: // LDF + opaddr = fetch2(); + if (cprefix == 0x92) { + regs.A = get1(get3(opaddr)); + } else { + regs.A = get1((opaddr << 8) + fetch()); + } + FLAG_NZ (regs.A); + return(resGO); + break; + case 0xC0: + case 0xD0: + case 0xE0: + case 0xF0: // JP + return( inst_jp( code, cprefix)); + break; + default: + //printf("************* bad code !!!!\n"); + return(resINV_INST); + } + break; + case 0xd: + switch ( code & 0xf0) { + case 0x00: + case 0x30: + case 0x40: + case 0x50: + case 0x60: + case 0x70: // tnz + return( inst_tnz( code, cprefix)); + break; + case 0x10: // SUBW X,#word + return( inst_addw( code, cprefix)); + break; + case 0x80: // CALLF + opaddr = fetch2(); + if (cprefix == 0x92) { + push2(PC & 0xffff); + push1(PC >> 16); + PC = get3(opaddr); + } else { + unsigned char c = fetch(); + push2(PC & 0xffff); + push1(PC >> 16); + PC = (opaddr << 8) + c; + } + return(resGO); + break; + case 0x90: // NOP + return(resGO); + break; + case 0xA0: // CALLR + { + signed char c = (signed char) fetch1(); + push2(PC); + PC += c; + return(resGO); + } + break; + case 0xb0: // LDF + opaddr = fetch2(); + if (cprefix == 0x92) { + store1(get3(opaddr),regs.A); + } else { + store1((opaddr << 8) + fetch(), regs.A); + } + FLAG_NZ (regs.A); + return(resGO); + break; + case 0xC0: + case 0xD0: + case 0xE0: + case 0xF0: // CALL + return( inst_call( code, cprefix)); + break; + default: + //printf("************* bad code !!!!\n"); + return(resINV_INST); + } + break; + case 0xe: + switch ( code & 0xf0) { + case 0x00: + case 0x30: + case 0x40: + case 0x50: + case 0x60: + case 0x70: // swap + return( inst_swap( code, cprefix)); + break; + case 0x80: + //printf("************* HALT instruction reached !!!!\n"); + return(resHALT); + case 0x90: // LD A, YH / XH + if(cprefix==0x90) { + regs.A = (regs.Y >> 8) & 0xff; + } else if(cprefix==0x00) { + regs.A = (regs.X >> 8) & 0xff; + } else { + return(resHALT); + } + return(resGO); + break; + case 0x10: + case 0xA0: + case 0xB0: + case 0xC0: + case 0xD0: + case 0xE0: + case 0xF0: // LDXY + return( inst_ldxy( code, cprefix)); + break; + default: + //printf("************* bad code !!!!\n"); + return(resINV_INST); + } + break; + case 0xf: + switch ( code & 0xf0) { + case 0x10: + // ldw (offset,SP),X + return( inst_ldxydst( code, cprefix ) ); + break; + case 0x00: + case 0x30: + case 0x40: + case 0x50: + case 0x60: + case 0x70: // CLR + return( inst_clr( code, cprefix)); + break; + case 0x80: + //printf("************* WFI/WFE instruction not implemented !!!!\n"); + return(resINV_INST); + case 0x90: + if(cprefix==0x90) { + regs.A = (regs.Y & 0xff); + } else if(cprefix==0x00) { + regs.A = (regs.X & 0xff); + } else { + return(resHALT); + } + return(resGO); + case 0xA0: // LDF + opaddr = fetch2(); + if (cprefix == 0x92) { + regs.A = get1(get3(opaddr)+regs.X); + } else if(cprefix==0x91) { + regs.A = get1(get3(opaddr)+regs.Y); + } else if(cprefix==0x90) { + regs.A = get1((opaddr << 8) + fetch() + regs.Y); + } else if(cprefix==0x00) { + regs.A = get1((opaddr << 8) + fetch() + regs.X); + } else { + return(resHALT); + } + FLAG_NZ (regs.A); + return(resGO); + case 0xB0: + case 0xC0: + case 0xD0: + case 0xE0: + case 0xF0: // LDXYDST + return( inst_ldxydst( code, cprefix)); + break; + default: + //printf("************* bad code !!!!\n"); + return(resINV_INST); + } + break; + default: + //printf("************* bad code !!!!\n"); + return(resINV_INST); + + } + + //printf("************* bad code !!!!\n"); + /*if (PC) + PC--; + else + PC= get_mem_size(MEM_ROM_ID)-1;*/ + //PC= rom->inc_address(PC, -1); + + //sim->stop(resINV_INST); + return(resINV_INST); +} + + +/* + * Checking for interrupt requests and accept one if needed + */ + +int +cl_stm8::do_interrupt(void) +{ + return cl_uc::do_interrupt(); +} + +int +cl_stm8::priority_of(uchar nuof_it) +{ + t_addr ra= 0x7f70; + int idx= nuof_it / 4; + u8_t i1_mask, i0_mask, i0, i1; + cl_memory_cell *c; + t_mem cv; + int levels[4]= { 2, 1, 0, 3 }; + + if (nuof_it > 31) + return 0; + i1_mask= 2 << ((nuof_it % 4) * 2); + i0_mask= 1 << ((nuof_it % 4) * 2); + c= ram->get_cell(ra + idx); + cv= c->read(); + i0= (cv & i0_mask)?1:0; + i1= (cv & i1_mask)?2:0; + return levels[i1+i0]; +} + +int +cl_stm8::priority_main(void) +{ + t_mem cv= regs.CC; + u8_t i1, i0; + int levels[4]= { 2, 1, 0, 3 }; + i0= (cv & BIT_I0)?1:0; + i1= (cv & BIT_I1)?2:0; + return levels[i1+i0]; +} + + +/* + * Accept an interrupt + */ + +int +cl_stm8::accept_it(class it_level *il) +{ + //class cl_it_src *is= il->source; + push2( PC & 0xffff); + push1( PC >> 16); //extended PC + push2( regs.Y); + push2( regs.X); + push1( regs.A); + push1( regs.CC); + // set I1 and I0 status bits + if (il->level == 0) + { FLAG_SET(BIT_I1) FLAG_CLEAR(BIT_I0) } + else if (il->level == 1) + { FLAG_CLEAR(BIT_I1) FLAG_SET(BIT_I0) } + else if (il->level == 2) + { FLAG_CLEAR(BIT_I1) FLAG_CLEAR(BIT_I0) } + else // 3 + { FLAG_SET(BIT_I1) FLAG_SET(BIT_I0) } + PC = il->addr; + + it_levels->push(il); + return resGO;//resINTERRUPT; +} + + +/* check if interrupts are enabled (globally) + */ + +bool +cl_stm8::it_enabled(void) +{ + return !(regs.CC & BIT_I0) || !(regs.CC & BIT_I1); +} + + +cl_stm8_cpu::cl_stm8_cpu(class cl_uc *auc): + cl_hw(auc, HW_DUMMY, 0, "cpu") +{ +} + +int +cl_stm8_cpu::init(void) +{ + int i; + cl_hw::init(); + for (i= 0; i < 11; i++) + { + regs[i]= register_cell(uc->rom, 0x7f00+i); + } + return 0; +} + +void +cl_stm8_cpu::write(class cl_memory_cell *cell, t_mem *val) +{ + t_addr a; + cl_stm8 *u= (cl_stm8*)uc; + + if (conf(cell, val)) + return; + + if (conf(cell, NULL)) + return; + + *val&= 0xff; + if (!uc->rom->is_owned(cell, &a)) + return; + if ((a < 0x7f00) || + (a > 0x7f0a)) + return; + + a-= 0x7f00; + switch (a) + { + case 0: + u->regs.A= *val; + break; + case 1: + u->PC= (u->PC & 0xffff) + (*val << 16); + break; + case 2: + u->PC= (u->PC & 0xff00ff) | (*val << 8); + break; + case 3: + u->PC= (u->PC & 0xffff00) | (*val); + break; + case 4: + u->regs.X= (u->regs.X & 0xff) | (*val << 8); + break; + case 5: + u->regs.X= (u->regs.X & 0xff00) | (*val); + break; + case 6: + u->regs.Y= (u->regs.Y & 0xff) | (*val << 8); + break; + case 7: + u->regs.Y= (u->regs.Y & 0xff00) | (*val); + break; + case 8: + u->regs.SP= (u->regs.SP & 0xff) | (*val << 8); + break; + case 9: + u->regs.SP= (u->regs.SP & 0xff00) | (*val); + break; + case 0xa: + u->regs.CC= (u->regs.CC & 0xff00) | (*val); + break; + } +} + +t_mem +cl_stm8_cpu::read(class cl_memory_cell *cell) +{ + t_mem v= cell->get(); + t_addr a; + cl_stm8 *u= (cl_stm8*)uc; + + if (conf(cell, NULL)) + return v; + if (!uc->rom->is_owned(cell, &a)) + return v; + if ((a < 0x7f00) || + (a > 0x7f0a)) + return v; + + a-= 0x7f00; + switch (a) + { + case 0: + v= u->regs.A; + break; + case 1: + v= (u->PC >> 16) & 0xff; + break; + case 2: + v= (u->PC >> 8) & 0xff; + break; + case 3: + v= u->PC & 0xff; + break; + case 4: + v= (u->regs.X >> 8) & 0xff; + break; + case 5: + v= u->regs.X & 0xff; + break; + case 6: + v= (u->regs.Y >> 8) & 0xff; + break; + case 7: + v= u->regs.Y & 0xff; + break; + case 8: + v= (u->regs.SP >> 8) & 0xff; + break; + case 9: + v= u->regs.SP & 0xff; + break; + case 0xa: + v= u->regs.CC; + break; + } + return v; +} + +t_mem +cl_stm8_cpu::conf_op(cl_memory_cell *cell, t_addr addr, t_mem *val) +{ + if (val) + cell->set(*val); + return cell->get(); +} + + +/* End of stm8.src/stm8.cc */ diff --git a/sim/ucsim/stm8.src/stm8.o b/sim/ucsim/stm8.src/stm8.o Binary files differnew file mode 100644 index 0000000..1de0e22 --- /dev/null +++ b/sim/ucsim/stm8.src/stm8.o diff --git a/sim/ucsim/stm8.src/stm8cl.h b/sim/ucsim/stm8.src/stm8cl.h new file mode 100644 index 0000000..5bc685d --- /dev/null +++ b/sim/ucsim/stm8.src/stm8cl.h @@ -0,0 +1,117 @@ +/* + * Simulator of microcontrollers (stm8cl.h) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#ifndef STM8CL_HEADER +#define STM8CL_HEADER + +#include "uccl.h" +#include "itsrccl.h" + +#include "regsstm8.h" +#include "itccl.h" + + +/* + * Base type of STM8 microcontrollers + */ + +class cl_stm8: public cl_uc +{ +public: + class cl_address_space *ram; + class cl_address_space *regs8; + class cl_address_space *regs16; + class cl_memory_chip + *ram_chip, // max 6k + *eeprom_chip, // max 2k + *option_chip, // 128 bytes + *io_chip, // 2k + *boot_chip, // 2k + *cpu_chip, // 256 bytes + *flash_chip; // max 128k + //class cl_memory *rom; + struct t_regs regs; + class cl_itc *itc; + class cl_it_src *trap_src; + class cl_flash *flash_ctrl; +public: + cl_stm8(struct cpu_entry *IType, class cl_sim *asim); + virtual int init(void); + virtual char *id_string(void); + + //virtual t_addr get_mem_size(enum mem_class type); + virtual void mk_port(t_addr base, chars n); + virtual void mk_hw_elements(void); + virtual void make_memories(void); + + virtual struct dis_entry *dis_tbl(void); + virtual int inst_length(t_addr addr); + virtual int inst_branch(t_addr addr); + virtual int longest_inst(void); + virtual char *disass(t_addr addr, const char *sep); + virtual void print_regs(class cl_console_base *con); + + virtual int exec_inst(void); + + virtual const char *get_disasm_info(t_addr addr, + int *ret_len, + int *ret_branch, + int *immed_offset, + struct dis_entry **dentry); + virtual bool is_call(t_addr addr); + + virtual void reset(void); + + virtual int do_interrupt(void); + virtual int priority_of(uchar nuof_it); + virtual int priority_main(void); + virtual int accept_it(class it_level *il); + virtual bool it_enabled(void); + +#include "instcl.h" +}; + + +class cl_stm8_cpu: public cl_hw +{ + protected: + class cl_memory_cell *regs[11]; + public: + cl_stm8_cpu(class cl_uc *auc); + virtual int init(void); + virtual int cfg_size(void) { return 2; } + //virtual char *cfg_help(t_addr addr); + + virtual void write(class cl_memory_cell *cell, t_mem *val); + virtual t_mem read(class cl_memory_cell *cell); + virtual t_mem conf_op(cl_memory_cell *cell, t_addr addr, t_mem *val); +}; + + +#endif + +/* End of stm8.src/stm8cl.h */ diff --git a/sim/ucsim/stm8.src/stm8mac.h b/sim/ucsim/stm8.src/stm8mac.h new file mode 100644 index 0000000..b734105 --- /dev/null +++ b/sim/ucsim/stm8.src/stm8mac.h @@ -0,0 +1,48 @@ +/* + * Simulator of microcontrollers (stm8mac.h) + * + * some z80 code base from Karl Bongers karl@turbobit.com + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +// shift positions +#define BITPOS_C 0 // 1 +#define BITPOS_Z 1 // 2H +#define BITPOS_N 2 // 4H +#define BITPOS_I0 3 // 8H +#define BITPOS_H 4 // 10H +#define BITPOS_I1 5 // 20H +#define BITPOS_V 7 // 80H + +#define store2(addr, val) { ram->write((t_addr) (addr), (val >> 8) & 0xff); \ + ram->write((t_addr) (addr+1), val & 0xff); \ + vc.wr+= 2; } +#define store1(addr, val) { ram->write((t_addr) (addr), val); vc.wr++; } +//#define get1(addr) ram->read((t_addr) (addr)) +#define get1(addr) get_1(addr) +#define fetch2() ((fetch() << 8) | fetch() ) +#define fetch1() fetch() +#define push2(val) {store2(regs.SP-1,(val)); regs.SP-=2; } +#define push1(val) {store1(regs.SP,(val)); regs.SP-=1; } +#define pop2(var) {var=get2(regs.SP+1); regs.SP+=2;} +#define pop1(var) {var=get1(regs.SP+1); regs.SP+=1;} + + +#define FLAG_SET(f) {regs.CC |= f;} +#define FLAG_CLEAR(f) {regs.CC &= ~(f);} +#define FLAG_ASSIGN(f,c) {regs.CC = (c) ? regs.CC | (f) : regs.CC & ~(f);} +#define FLAG_NZ(f) { \ + regs.CC = (regs.CC & ~(BIT_N|BIT_Z)) \ + | (((f) & 0xff) ? 0 : BIT_Z) \ + | (((f) & 0x80) ? BIT_N : 0) \ + ; } +#define EA_IMM(c) ((((c) >> 4) & 0xf)==0xa) +#define OPERAND(code,prefix) (EA_IMM(code) ? fetch() : get1(fetchea(code,prefix))) +#define OPERANDW(code,prefix) (EA_IMM(code) ? fetch2() : get2(fetchea(code,prefix))) + + + diff --git a/sim/ucsim/stm8.src/test/Makefile b/sim/ucsim/stm8.src/test/Makefile new file mode 100644 index 0000000..1d0296b --- /dev/null +++ b/sim/ucsim/stm8.src/test/Makefile @@ -0,0 +1,18 @@ +PROJECTS = s0 s1 s2 s3 t1 t2 t3 t4 xtest \ + sl ss lled sled ltim stim sertest \ + getbl \ + monitor + +.PHONY: projects $(PROJECTS) + +projects: $(PROJECTS) + +$(PROJECTS): + $(MAKE) MAIN=$@ -f sdcc.mk + +clean: + for p in $(PROJECTS); do \ + $(MAKE) MAIN=$$p -f sdcc.mk clean ;\ + rm -rf $$p*.hex ;\ + rm -rf $$p*.cdb ;\ + done diff --git a/sim/ucsim/stm8.src/test/conf.cmd b/sim/ucsim/stm8.src/test/conf.cmd new file mode 100644 index 0000000..f921d23 --- /dev/null +++ b/sim/ucsim/stm8.src/test/conf.cmd @@ -0,0 +1,2 @@ +set hw simif rom 0x7fff +set opt debug 1 diff --git a/sim/ucsim/stm8.src/test/dl_ldisc.sh b/sim/ucsim/stm8.src/test/dl_ldisc.sh new file mode 100755 index 0000000..c858a5a --- /dev/null +++ b/sim/ucsim/stm8.src/test/dl_ldisc.sh @@ -0,0 +1,3 @@ +#!/bin/bash + +stm8flash -c stlink -p stm8l152c6 -w ${1} diff --git a/sim/ucsim/stm8.src/test/dl_sdic.sh b/sim/ucsim/stm8.src/test/dl_sdic.sh new file mode 100755 index 0000000..8848a73 --- /dev/null +++ b/sim/ucsim/stm8.src/test/dl_sdic.sh @@ -0,0 +1,3 @@ +#!/bin/bash + +stm8flash -c stlink -p stm8s105c6 -w ${1} diff --git a/sim/ucsim/stm8.src/test/flash.c b/sim/ucsim/stm8.src/test/flash.c new file mode 100644 index 0000000..07a2394 --- /dev/null +++ b/sim/ucsim/stm8.src/test/flash.c @@ -0,0 +1,141 @@ +/* */ + +#include <string.h> + +#include "stm8.h" + +#include "flash.h" + + +// Lock, unklock + +void +flash_punlock(void) +{ + FLASH->pukr= 0x56; + FLASH->pukr= 0xae; +} + +void +flash_dunlock(void) +{ + FLASH->pukr= 0xae; + FLASH->pukr= 0x56; +} + +void +flash_plock(void) +{ + FLASH->iapsr&= ~0x02; +} + +void +flash_dlock(void) +{ + FLASH->iapsr&= ~0x08; +} + +void +flash_lock(void) +{ + FLASH->iapsr&= ~0x0a; +} + + +// Set programing mode + +void +flash_byte_mode(void) +{ + FLASH->cr2= 0; +#if (DEVICE & DEV_STM8SAF) + FLASH->ncr2= 0xff; +#endif +} + +void +flash_word_mode(void) +{ + FLASH->cr2= 0x40; +#if (DEVICE & DEV_STM8SAF) + FLASH->ncr2= 0xbf; +#endif +} + +void +flash_erase_mode(void) +{ + FLASH->cr2= 0x20; +#if (DEVICE & DEV_STM8SAF) + FLASH->ncr2= 0xdf; +#endif +} + + +// Check the result + +uint8_t +flash_wait_finish(void) +{ + unsigned long int timeout= 0xfffff; + //volatile + uint8_t r; + + r= FLASH->iapsr; + while (((r & 0x05) == 0) && + (timeout != 0)) + { + timeout--; + r= FLASH->iapsr; + } + if (r & 0x04) + return 0; + if (r & 0x01) + return 1; + if (timeout == 0) + return 2; + return 3; +} + +uint8_t +flash_erase_fn(volatile uint8_t *addr, volatile uint8_t *iapsr) +{ + volatile uint8_t r; + unsigned long timeout= 0xfffff; + flash_erase_mode(); + *(addr++)= 0; + *(addr++)= 0; + *(addr++)= 0; + *(addr)= 0; + r= *iapsr; + while (((r & 0x05) == 0) && + (timeout != 0)) + { + timeout--; + r= *iapsr; + GPIOD->odr^= 1; + } + if (r & 0x04) + return 0; + if (r & 0x01) + return 1; + if (timeout == 0) + return 2; + return 3; +} + +uint8_t flash_op_in_ram[120]; + +uint8_t +flash_erase(volatile uint8_t *addr, volatile uint8_t *iapsr) +{ + uint8_t r; + typedef uint8_t (*ft)(volatile uint8_t *addr, volatile uint8_t *iapsr); + ft f= (ft)flash_op_in_ram; + memcpy(flash_op_in_ram, &flash_erase_fn, 119); + r= (*f)(addr, iapsr); + return r; +} + + +/* End of stm8.src/test/flash.c */ diff --git a/sim/ucsim/stm8.src/test/flash.h b/sim/ucsim/stm8.src/test/flash.h new file mode 100644 index 0000000..52a7ac6 --- /dev/null +++ b/sim/ucsim/stm8.src/test/flash.h @@ -0,0 +1,23 @@ +/* */ + +#ifndef FLASH_HEADER +#define FLASH_HEADER + +#include <stdbool.h> + +extern void flash_punlock(void); +extern void flash_dunlock(void); +extern void flash_plock(void); +extern void flash_dlock(void); +extern void flash_lock(void); + +extern void flash_byte_mode(void); +extern void flash_word_mode(void); +extern void flash_erase_mode(void); + +extern uint8_t flash_wait_finish(void); +extern uint8_t flash_erase(volatile uint8_t *addr, volatile uint8_t *iapsr); + +#endif + +/* End of stm8.src/test/flash.h */ diff --git a/sim/ucsim/stm8.src/test/getbl.c b/sim/ucsim/stm8.src/test/getbl.c new file mode 100644 index 0000000..4a04423 --- /dev/null +++ b/sim/ucsim/stm8.src/test/getbl.c @@ -0,0 +1,63 @@ +// Source code under CC0 1.0 +#include <stdint.h> +#include <stdio.h> + +#include "stm8.h" + +#include "serial.h" + +volatile unsigned char *sif= (unsigned char *)0x7fff; + +void +print_bl() +{ + int a, l; + uint8_t *p= (uint8_t *)0x6000; + printf("%c\n", 2); + printf("$A%04x,\n", 0x6000); + for (a= 0, l= 0; a < 0x800; a++) + { + printf("%02x ", p[a]); + l++; + if ((l % 16) == 0) + { + l= 0; + printf("\n"); + } + } + printf("%c\n", 3); +} + +void main(void) +{ + unsigned long i = 0; + + CLK->ckdivr = 0x00; // Set the frequency to 16 MHz + CLK->pckenr1 = 0xFF; // Enable peripherals + + USART->cr2 = USART_CR2_TEN | USART_CR2_REN; // Allow TX and RX + USART->cr3 &= ~(USART_CR3_STOP1 | USART_CR3_STOP2); // 1 stop bit + USART->brr2 = 0x03; + USART->brr1 = 0x68; // 9600 baud + + USART->cr2|= USART_CR2_RIEN; + EI; + + for(;;) + { + if (serial_received()) + { + char c= getchar(); + if (c == '=') + { + print_bl(); + } + else if (c == '*') + { + printf("0x%04x\n", 0x6000); + } + else + printf("%c", c); + } + } +} diff --git a/sim/ucsim/stm8.src/test/getbl.mk b/sim/ucsim/stm8.src/test/getbl.mk new file mode 100644 index 0000000..8dda245 --- /dev/null +++ b/sim/ucsim/stm8.src/test/getbl.mk @@ -0,0 +1,3 @@ +DEVICES = SDISC LDISC + +OTHERS = serial diff --git a/sim/ucsim/stm8.src/test/lled.c b/sim/ucsim/stm8.src/test/lled.c new file mode 100644 index 0000000..dd1cd08 --- /dev/null +++ b/sim/ucsim/stm8.src/test/lled.c @@ -0,0 +1,47 @@ +// Source code under CC0 1.0 +#include <stdint.h> + +#include "stm8.h" + +#define PC GPIOC +#define PE GPIOE + +unsigned int clock(void) +{ + unsigned char h, l; + h = TIM1->cntrh; + l = TIM1->cntrl; + return((unsigned int)(h) << 8 | l); +} + +void main(void) +{ + CLK->ckdivr = 0x00; // Set the frequency to 16 MHz + CLK->pckenr2 |= 0x02; // Enable clock to timer + + // Configure timer + // 1000 ticks per second + TIM1->pscrh = 0x3e; + TIM1->pscrl = 0x80; + // Enable timer + TIM1->cr1 = TIM_CR1_CEN; + + // Configure pins + PE->ddr = 0x80; + PE->cr1 = 0x80; + + PC->ddr = 0x80; + PC->cr1 = 0x80; + + for(;;) + { + if (clock() % 1000 <= 500) + PE->odr |= 0x80; + else + PE->odr &= 0x7f; + if (clock() % 2000 <= 1000) + PC->odr |= 0x80; + else + PC->odr &= 0x7f; + } +} diff --git a/sim/ucsim/stm8.src/test/lled.mk b/sim/ucsim/stm8.src/test/lled.mk new file mode 100644 index 0000000..5d8d31b --- /dev/null +++ b/sim/ucsim/stm8.src/test/lled.mk @@ -0,0 +1 @@ +DEVICES = LDISC diff --git a/sim/ucsim/stm8.src/test/ltim.c b/sim/ucsim/stm8.src/test/ltim.c new file mode 100644 index 0000000..55740d6 --- /dev/null +++ b/sim/ucsim/stm8.src/test/ltim.c @@ -0,0 +1,84 @@ +// Source code under CC0 1.0 +#include <stdint.h> + +#include "stm8.h" + +#define PC GPIOC +#define PE GPIOE + +volatile unsigned long clk= 0; + +void tim1_up_isr(void) __interrupt(TIM1_UP_IRQ) +{ + TIM1->sr1&= ~TIM_SR1_UIF; + clk++; + //PE->odr^= 0x80; +} + +unsigned long clock(void) +{ + unsigned long c; + TIM1->ier&= ~TIM_IER_UIE; + c= clk; + TIM1->ier|= TIM_IER_UIE; + return c; +} + +unsigned long last_tick1= 0; + +void tick1(unsigned long c) +{ + //unsigned long c= clock(); + if (c - last_tick1 > 500) + { + last_tick1= c; + PE->odr^= 0x80; + } +} + +unsigned long last_tick2= 0; + +void tick2(unsigned long c) +{ + //unsigned long c= clock(); + if (c - last_tick2 > 1000) + { + last_tick2= c; + PC->odr^= 0x80; + } +} + +void main(void) +{ + CLK->ckdivr = 0x00; // Set the frequency to 16 MHz + CLK->pckenr2 |= 0x02; // Enable clock to timer + + // Configure timer + // 16 MHz clock for timer + TIM1->pscrh = 0;//0x3e; + TIM1->pscrl = 0;//0x80; + // Update event at every 1 ms (16000 count) + #define AR 16000 + TIM1->arrh = AR >> 8; + TIM1->arrl = AR & 0xff; + // Enable timer + TIM1->cr1 = TIM_CR1_CEN; + + // Enable interrupt for timer1 update + TIM1->ier|= TIM_IER_UIE; + EI; + + // Configure pins + PE->ddr = 0x80; + PE->cr1 = 0x80; + + PC->ddr = 0x80; + PC->cr1 = 0x80; + + for(;;) + { + unsigned long c= clock(); + tick1(c); + tick2(c); + } +} diff --git a/sim/ucsim/stm8.src/test/ltim.mk b/sim/ucsim/stm8.src/test/ltim.mk new file mode 100644 index 0000000..5d8d31b --- /dev/null +++ b/sim/ucsim/stm8.src/test/ltim.mk @@ -0,0 +1 @@ +DEVICES = LDISC diff --git a/sim/ucsim/stm8.src/test/monitor.c b/sim/ucsim/stm8.src/test/monitor.c new file mode 100644 index 0000000..0e209e2 --- /dev/null +++ b/sim/ucsim/stm8.src/test/monitor.c @@ -0,0 +1,282 @@ +// Source code under CC0 1.0 +#include <stdint.h> +#include <stdio.h> +#include <string.h> +#include <stdlib.h> +#include <ctype.h> + +#include "stm8.h" + +#include "serial.h" +#include "flash.h" + +#if (DEVICE & DEV_SDISC) +#define LED_PORT GPIOD +#define LED_MASK 0x01 +#else +#define LED_PORT GPIOC +#define LED_MASK 0x80 +#endif + +volatile unsigned char *sif= (unsigned char *)0x7fff; + +void +print_bl() +{ + int a, l; + uint8_t *p= (uint8_t *)0x6000; + printf("%c\n", 2); + printf("$A%04x,\n", 0x6000); + for (a= 0, l= 0; a < 0x800; a++) + { + printf("%02x ", p[a]); + l++; + if ((l % 16) == 0) + { + l= 0; + printf("\n"); + } + } + printf("%c\n", 3); +} + +void +dump(unsigned long int start, unsigned long int len) +{ + uint8_t *p= (uint8_t *)0; + int i= 0; + + printf("%06lx ", start); + while (i<len) + { + printf("%02x ", p[start+i]); + i++; + if ((i<len) && ((start+i)%8 == 0)) + { + printf("\n%06lx ", start+i); + } + } + printf("\n"); +} + +#define DELIM " ," + +int +xtoi(char *s) +{ + int r= 0; + while (*s) + { + if (isdigit(*s)) + r= r*16 + *s-'0'; + else if ((*s >= 'a') && (*s <= 'f')) + r= r*16 + *s-'a'+10; + else if ((*s >= 'A') && (*s <= 'F')) + r= r*16 + *s-'A'+10; + s++; + } + return r; +} + +unsigned long int +xtol(char *s) +{ + unsigned long int r= 0; + while (*s) + { + if (isdigit(*s)) + r= r*16 + *s-'0'; + else if ((*s >= 'a') && (*s <= 'f')) + r= r*16 + *s-'a'+10; + else if ((*s >= 'A') && (*s <= 'F')) + r= r*16 + *s-'A'+10; + s++; + } + return r; +} + +void f1() {} +void f2() {} + +void +proc_cmd(char *cmd) +{ + char *w= strtok(cmd, DELIM); + char *s; + uint8_t res; + uint8_t *rom= (uint8_t *)0; + unsigned long addr; + + if (w) + { + if (strcmp(w, "bl") == 0) + print_bl(); + else if (strcmp(w, "uid") == 0) + { +#if defined UID + int i; + uint8_t *p= UID; + printf("0x%04x ", p); + for (i= 0; i < 12; i++) + printf("%02x ", p[i]); + printf("\n"); +#else + printf("no uid\n"); +#endif + } + else if (strstr(w, "dump") == w) + { + s= strtok(NULL, DELIM); + if (s) + { + unsigned long int start= xtol(s); + unsigned long int len= 32; + s= strtok(NULL, DELIM); + if (s) + len= xtol(s); + dump(start, len); + } + } + else if (strcmp(w, "fb") == 0) + { + addr= 0xa000; + printf("Before:\n"); + dump(addr, 1); + f1(); + flash_byte_mode(); + flash_punlock(); + rom[addr]= 0xa5; + res= flash_wait_finish(); + f2(); + flash_plock(); + printf("After (%s,%d):\n", (res==0)?"succ":"fail", res); + dump(addr, 1); + } + else if (strcmp(w, "fw") == 0) + { + LED_PORT->odr|= LED_MASK; + addr= 0xa0a0; + printf("Before:\n"); + dump(addr, 4); + f1(); + flash_word_mode(); + flash_punlock(); + rom[addr+0]= 0x12; + rom[addr+1]= 0x34; + rom[addr+2]= 0x56; + rom[addr+3]= 0x78; + res= flash_wait_finish(); + f2(); + flash_plock(); + printf("After (%s,%d):\n", (res==0)?"succ":"fail", res); + dump(addr, 4); + LED_PORT->odr&= ~LED_MASK; + } + else if (strcmp(w, "fe") == 0) + { + LED_PORT->odr|= LED_MASK; + addr= 0xa000; + printf("Before:\n"); + dump(addr, 64); + f1(); + flash_punlock(); + /* + rom[addr+0]= 0; + rom[addr+1]= 0; + rom[addr+2]= 0; + rom[addr+3]= 0; + res= flash_wait_finish(); + */ + res= flash_erase((uint8_t*)0xa000, &(FLASH->iapsr)); + f2(); + flash_plock(); + printf("After (%s,%d):\n", (res==0)?"succ":"fail", res); + dump(addr, 64); + LED_PORT->odr&= ~LED_MASK; + } + else if (strstr(w, "test") == w) + { + printf("%d\n", sizeof(flash_erase)); + } + else + printf("Unknown command: \"%s\"\n", w); + } + else + printf("What?\n"); +} + +char cmd[100]; + +void +proc_input(char c) +{ + int l= strlen(cmd); + + printf("%c", c); + if ((c == '\n') || + (c == '\r')) + { + proc_cmd(cmd); + cmd[0]= 0; + } + else + { + if (l < 99) + { + cmd[l++]= c; + cmd[l]= 0; + } + } +} + +void main(void) +{ + unsigned long i = 0; + unsigned int a= 0; + + CLK->ckdivr = 0x00; // Set the frequency to 16 MHz + CLK->pckenr1 = 0xFF; // Enable peripherals + + LED_PORT->ddr= LED_MASK; + LED_PORT->cr1= LED_MASK; + + // USART2 + // TX: PD5, CN4.10 + // RX: PD6, CN4.11 + USART->cr2 = USART_CR2_TEN | USART_CR2_REN; // Allow TX and RX + USART->cr3 &= ~(USART_CR3_STOP1 | USART_CR3_STOP2); // 1 stop bit + // 0 68 3 0x0683=1667 16MHz-> 9600 baud + //USART->brr2 = 0x03; + //USART->brr1 = 0x68; + // 0 08 b 0x008b=139 16MHz-> 115200 baud + USART->brr2 = 0x0b; + USART->brr1 = 0x08; + + USART->cr2|= USART_CR2_RIEN; + EI; + + printf("%d discovery monitor\n", DEVICE); + /*{ + uint8_t *p= (uint8_t *)0x123456; + printf("sizeof p=%d\n", sizeof(p)); + *p= 0; + }*/ + cmd[0]= 0; + {/* + struct st { + volatile uint8_t v; + }; + struct st s;*/ + uint8_t r= FLASH->iapsr; + while (FLASH->iapsr == 0) + ;//r= FLASH->iapsr; + } + for(;;) + { + if (serial_received()) + { + char c= getchar(); + proc_input(c); + } + } +} diff --git a/sim/ucsim/stm8.src/test/monitor.mk b/sim/ucsim/stm8.src/test/monitor.mk new file mode 100644 index 0000000..97542a8 --- /dev/null +++ b/sim/ucsim/stm8.src/test/monitor.mk @@ -0,0 +1,3 @@ +OTHERS = serial flash + +DEVICES = SDISC LDISC diff --git a/sim/ucsim/stm8.src/test/s0.c b/sim/ucsim/stm8.src/test/s0.c new file mode 100644 index 0000000..d0ee5f0 --- /dev/null +++ b/sim/ucsim/stm8.src/test/s0.c @@ -0,0 +1,33 @@ +#include <stdint.h> +#include <stdio.h> + +#define DEVICE DEV_STM8S208 + +#include "stm8.h" + +int putchar(int c) +{ + while(!(USART->sr & USART_SR_TXE)); + + USART->dr = c; + return c; +} + +void main(void) +{ + unsigned long i = 0; + + CLK->ckdivr = 0x00; // Set the frequency to 16 MHz + CLK->pckenr1 = 0xFF; // Enable peripherals + + USART->cr2 = USART_CR2_TEN; // Allow TX and RX + USART->cr3 &= ~(USART_CR3_STOP1 | USART_CR3_STOP2); // 1 stop bit + USART->brr2 = 0x03; + USART->brr1 = 0x68; // 9600 baud + + for(;;) + { + printf("Hello World!\n"); + for(i = 0; i < 147456; i++); // Sleep + } +} diff --git a/sim/ucsim/stm8.src/test/s1.c b/sim/ucsim/stm8.src/test/s1.c new file mode 100644 index 0000000..b48a0fd --- /dev/null +++ b/sim/ucsim/stm8.src/test/s1.c @@ -0,0 +1,29 @@ +#include <stdint.h> +#include <stdio.h> + +#define DEVICE DEV_STM8S208 + +#include "stm8.h" + +int putchar(int c) +{ + while(!(USART->sr & USART_SR_TXE)); + USART->dr = c; + return c; +} + +void main(void) +{ + unsigned long i = 0; + + CLK->ckdivr = 0x00; // Set the frequency to 16 MHz + CLK->pckenr1 = 0xFF; // Enable peripherals + + USART->cr2 = USART_CR2_TEN; // Allow TX and RX + USART->cr3 &= ~(USART_CR3_STOP1 | USART_CR3_STOP2); // 1 stop bit + USART->brr2 = 0x03; + USART->brr1 = 0x68; // 9600 baud + + printf("Hello World!\n"); + for (;;) ; +} diff --git a/sim/ucsim/stm8.src/test/s2.c b/sim/ucsim/stm8.src/test/s2.c new file mode 100644 index 0000000..f83a877 --- /dev/null +++ b/sim/ucsim/stm8.src/test/s2.c @@ -0,0 +1,78 @@ +#include <stdint.h> +#include <stdio.h> +#include <ctype.h> + +#define DEVICE DEV_STM8S208 + +#include "stm8.h" + +volatile unsigned char *sif= (unsigned char *)0x7fff; + +int sifchar(int c) +{ + *sif= 'p'; + *sif= c; + return c; +} + +void waitsend() +{ + while(!(USART->sr & USART_SR_TXE)); +} + +int putchar(int c) +{ + while(!(USART->sr & USART_SR_TXE)); + USART->dr = c; + return c; +} + +char received() +{ + return USART->sr & USART_SR_RXNE; +} + +char getchar() +{ + while (!received()) + ; + return USART->dr; +} + +void prints(char *s) +{ + char i= 0; + while (s[i]) + { + putchar(s[i]); + i++; + } +} + +void main(void) +{ + unsigned long i = 0; + + CLK->ckdivr = 0x00; // Set the frequency to 16 MHz + CLK->pckenr1 = 0xFF; // Enable peripherals + + USART->cr2 = USART_CR2_TEN; // Allow TX only yet + USART->cr3 &= ~(USART_CR3_STOP1 | USART_CR3_STOP2); // 1 stop bit + USART->brr2 = 0x03; + USART->brr1 = 0x68; // 9600 baud + + printf("Hello World!\n"); + waitsend(); + USART->cr2 = USART_CR2_TEN | USART_CR2_REN; // Allow TX and RX + for (;;) + { + if (received()) + { + char c= getchar(); + *sif= 'x';*sif= c; + putchar(toupper(c)); + if (c == 'Z') + *sif= 's'; + } + } +} diff --git a/sim/ucsim/stm8.src/test/s3.c b/sim/ucsim/stm8.src/test/s3.c new file mode 100644 index 0000000..9635bf6 --- /dev/null +++ b/sim/ucsim/stm8.src/test/s3.c @@ -0,0 +1,98 @@ +#include <stdint.h> +#include <stdio.h> +#include <ctype.h> + +#define DEVICE DEV_STM8S208 + +#include "stm8.h" + +volatile unsigned char *sif= (unsigned char *)0x7fff; + +int sifchar(int c) +{ + *sif= 'p'; + *sif= c; + return c; +} + +int putchar(int c) +{ + while(!(USART->sr & USART_SR_TXE)); + USART->dr = c; + return c; +} + +volatile uint8_t rx_buf[8]; +volatile uint8_t first_free= 0; +volatile uint8_t last_used= 0; + +void isr_rx(void) __interrupt(USART_RX_IRQ) +{ + volatile uint8_t d; + *sif='p';*sif='I'; + if (USART->sr & USART_SR_RXNE) + { + uint8_t n; + d= USART->dr; + n= (first_free+1)%8; + if (n != last_used) + { + rx_buf[first_free]= d; + first_free= n; + } + } +} + +char received() +{ + //return UART2_SR & UART_SR_RXNE; + return first_free != last_used; +} + +char getchar() +{ + uint8_t o; + while (!received()) + ; + o= last_used; + last_used= (last_used+1)%8; + return rx_buf[o]; +} + +void prints(char *s) +{ + char i= 0; + while (s[i]) + { + putchar(s[i]); + i++; + } +} + + +void main(void) +{ + unsigned long i = 0; + + CLK->ckdivr = 0x00; // Set the frequency to 16 MHz + CLK->pckenr1 = 0xFF; // Enable peripherals + + USART->cr2 = USART_CR2_TEN | USART_CR2_REN; // Allow TX and RX + USART->cr3 &= ~(USART_CR3_STOP1 | USART_CR3_STOP2); // 1 stop bit + USART->brr2 = 0x03; + USART->brr1 = 0x68; // 9600 baud + + USART->cr2|= USART_CR2_RIEN; + EI; + + printf("Hello World!\n"); + for (;;) + { + if (received()) + { + char c= getchar(); + *sif= 'x';*sif= c; + putchar(toupper(c)); + } + } +} diff --git a/sim/ucsim/stm8.src/test/sdcc.mk b/sim/ucsim/stm8.src/test/sdcc.mk new file mode 100644 index 0000000..2b54862 --- /dev/null +++ b/sim/ucsim/stm8.src/test/sdcc.mk @@ -0,0 +1,67 @@ +VPATH = .. + +vpath %.mk $(VPATH) + +TARGET = stm8 + +CC = sdcc -m$(TARGET) --std-c99 + +CPPFLAGS = +CFLAGS = --debug +LDFLAGS = +LIBS = + +-include $(MAIN).mk + +DEVICES ?= S208 + +ALL = $(MAIN) $(OTHERS) + +OBJECTS = $(MAIN).rel $(OTHERS:=.rel) + +CPPFLAGS = -DDEVICE=DEV_STM8$(DEVICE) -I$(VPATH) + +.SUFFIXES: .rel .ihx .hex + +.PHONY: $(DEVICES) + +all: $(DEVICES) + +$(DEVICES): + test -d $@ || mkdir $@ + $(MAKE) -C $@ DEVICE=$@ REAL=yes MAIN=$(MAIN) -I$(VPATH) -f$(VPATH)/sdcc.mk compile copy_result + +copy_result: $(VPATH)/$(MAIN)_$(DEVICE).hex $(VPATH)/$(MAIN)_$(DEVICE).cdb + +$(VPATH)/$(MAIN)_$(DEVICE).hex: $(MAIN).hex + cp $< $@ + +$(VPATH)/$(MAIN)_$(DEVICE).cdb: $(MAIN).cdb + cp $(MAIN).cdb $@ + +compile: dep $(MAIN).hex + +.c.rel: + $(CC) $(CPPFLAGS) $(CFLAGS) -o $@ -c $< + +.ihx.hex: + packihx $< >$@ + +$(MAIN).ihx: $(OBJECTS) + $(CC) $(CFLAGS) $(LDFLAAGS) $(OBJECTS) -o $@ + +$(MAIN).cdb: $(MAIN).hex + +dep: $(MAIN).dep + +$(MAIN).dep: $(addprefix ../,$(OBJECTS:.rel=.c)) ../*.h + for c in $(addprefix ../,$(OBJECTS:.rel=.c)); do \ + $(CC) -MM $(CPPFLAGS) $$c >>$@; \ + done + +clean: + rm -rf $(DEVICES) + +ifeq ($(REAL),yes) +include $(MAIN).dep +endif diff --git a/sim/ucsim/stm8.src/test/serial.c b/sim/ucsim/stm8.src/test/serial.c new file mode 100644 index 0000000..8d8fddd --- /dev/null +++ b/sim/ucsim/stm8.src/test/serial.c @@ -0,0 +1,114 @@ +#include <stdio.h> + +#include "stm8.h" + +#include "serial.h" + +extern volatile unsigned char *sif; + +int +putchar(int c) +{ + while(!(USART->sr & USART_SR_TXE)); + + USART->dr = c; + return c; +} + +volatile uint8_t rx_buf[UART_BUF_SIZE]; +volatile uint8_t first_free= 0; +volatile uint8_t last_used= 0; + +unsigned char +serial_nuof_received() +{ + if (first_free == last_used) + return 0; + else if (first_free > last_used) + return first_free - last_used; + else + return UART_BUF_SIZE - (last_used - first_free); +} + +void isr_rx(void) __interrupt(USART_RX_IRQ) +{ + volatile uint8_t d; + if (USART->sr & USART_SR_RXNE) + { + uint8_t n; + d= USART->dr; + n= (first_free+1)%UART_BUF_SIZE; + *sif= 'p';*sif= '|'; + *sif= 'p';*sif= d; + *sif= 'p';*sif= '|'; + if (n != last_used) + { + rx_buf[first_free]= d; + first_free= n; + } + else + { + *sif= 'p';*sif= '*'; + *sif= 'p';*sif= d; + *sif= 'p';*sif= '*'; + } + d= serial_nuof_received(); + *sif= 'p';*sif= '/'; + *sif= 'p';*sif= d+'0'; + *sif= 'p';*sif= '/'; + } +} + +char +serial_received() +{ + //return UART2_SR & UART_SR_RXNE; + return first_free != last_used; +} + +char getchar() +{ + uint8_t o, nr; + while (!serial_received()) + ; + o= last_used; + last_used= (last_used+1)%UART_BUF_SIZE; + o= rx_buf[o]; + nr= serial_nuof_received(); + *sif= 'p';*sif= '@'; + *sif= 'p';*sif= nr+'0'; + *sif= 'p';*sif= '@'; + return o; +} + +void +print_cx1(char c) +{ + if (c > 9) + printf("%c", c-10+'A'); + else + printf("%c", c+'0'); +} + +void +print_cx2(char c) +{ + int d; + d= (c>>4) & 0xf; + print_cx1(d); + d= c & 0xf; + print_cx1(d); +} + +void +print_ix4(int i) +{ + int d= i>>12; + print_cx1(d); + d= (i>>8) & 0xf; + print_cx1(d); + d= (i>>4) & 0xf; + print_cx1(d); + d= i & 0xf; + print_cx1(d); +} diff --git a/sim/ucsim/stm8.src/test/serial.h b/sim/ucsim/stm8.src/test/serial.h new file mode 100644 index 0000000..8552c19 --- /dev/null +++ b/sim/ucsim/stm8.src/test/serial.h @@ -0,0 +1,16 @@ +#ifndef SERIAL_HEADER +#define SERIAL_HEADER + +#include "stm8.h" + +#define UART_BUF_SIZE 8 + +extern void isr_rx(void) __interrupt(USART_RX_IRQ); + +extern char serial_received(); + +extern void print_cx1(char c); +extern void print_cx2(char c); +extern void print_ix4(int i); + +#endif diff --git a/sim/ucsim/stm8.src/test/sertest.c b/sim/ucsim/stm8.src/test/sertest.c new file mode 100644 index 0000000..1f77cf9 --- /dev/null +++ b/sim/ucsim/stm8.src/test/sertest.c @@ -0,0 +1,51 @@ +// Source code under CC0 1.0 +#include <stdint.h> +#include <stdio.h> + +#include "stm8.h" + +#include "serial.h" + +volatile unsigned char *sif= (unsigned char *)0x7fff; + + +void main(void) +{ + unsigned long i = 0; + unsigned int a= 0; + + CLK->ckdivr = 0x00; // Set the frequency to 16 MHz + CLK->pckenr1 = 0xFF; // Enable peripherals + + // USART2 + // TX: PD5, CN4.10 + // RX: PD6, CN4.11 + USART->cr2 = USART_CR2_TEN | USART_CR2_REN; // Allow TX and RX + USART->cr3 &= ~(USART_CR3_STOP1 | USART_CR3_STOP2); // 1 stop bit + USART->brr2 = 0x03; + USART->brr1 = 0x68; // 9600 baud + + USART->cr2|= USART_CR2_RIEN; + EI; + + for(;;) + { + i++; + if (serial_received()) + { + char c= getchar(); + if (c == '*') + { + printf("0x%04x\n", a); + } + printf("%c", c); + i= 0; + } + if (i > 147456*2) + { + printf("tick %u 0x%04x Hello World!\n", a, a); + i= 0; + a++; + } + } +} diff --git a/sim/ucsim/stm8.src/test/sertest.mk b/sim/ucsim/stm8.src/test/sertest.mk new file mode 100644 index 0000000..dfc8f06 --- /dev/null +++ b/sim/ucsim/stm8.src/test/sertest.mk @@ -0,0 +1,3 @@ +DEVICES = LDISC SDISC + +OTHERS = serial diff --git a/sim/ucsim/stm8.src/test/sl.c b/sim/ucsim/stm8.src/test/sl.c new file mode 100644 index 0000000..0132275 --- /dev/null +++ b/sim/ucsim/stm8.src/test/sl.c @@ -0,0 +1,59 @@ +// Source code under CC0 1.0 +#include <stdint.h> +#include <stdio.h> + +#define PC_DDR (*(volatile uint8_t *)0x500c) +#define PC_CR1 (*(volatile uint8_t *)0x500d) + +#define CLK_DIVR (*(volatile uint8_t *)0x50c0) +#define CLK_PCKENR1 (*(volatile uint8_t *)0x50c3) + +#define USART1_SR (*(volatile uint8_t *)0x5230) +#define USART1_DR (*(volatile uint8_t *)0x5231) +#define USART1_BRR1 (*(volatile uint8_t *)0x5232) +#define USART1_BRR2 (*(volatile uint8_t *)0x5233) +#define USART1_CR2 (*(volatile uint8_t *)0x5235) +#define USART1_CR3 (*(volatile uint8_t *)0x5236) + +#define USART_CR2_TEN (1 << 3) +#define USART_CR3_STOP2 (1 << 5) +#define USART_CR3_STOP1 (1 << 4) +#define USART_SR_TXE (1 << 7) + +int putchar(int c) +{ + while(!(USART1_SR & USART_SR_TXE)); + + USART1_DR = c; + return c; +} + +char dbuf[10]; +char xbuf[10]; + +void main(void) +{ + unsigned long i = 0; + int a= 0; + + CLK_DIVR = 0x00; // Set the frequency to 16 MHz + CLK_PCKENR1 = 0xFF; // Enable peripherals + + PC_DDR = 0x08; // Put TX line on + PC_CR1 = 0x08; + + USART1_CR2 = USART_CR2_TEN; // Allow TX and RX + USART1_CR3 &= ~(USART_CR3_STOP1 | USART_CR3_STOP2); // 1 stop bit + USART1_BRR2 = 0x03; USART1_BRR1 = 0x68; // 9600 baud + + sprintf(dbuf, "%d", 1234); + printf("%s\n", dbuf); + sprintf(xbuf, "%x", 0x1234); + printf("%s\n", xbuf); + for(;;) + { + printf("Hello World %d %x!\n", a, a); + for(i = 0; i < 147456; i++); // Sleep + a++; + } +} diff --git a/sim/ucsim/stm8.src/test/sl.mk b/sim/ucsim/stm8.src/test/sl.mk new file mode 100644 index 0000000..5d8d31b --- /dev/null +++ b/sim/ucsim/stm8.src/test/sl.mk @@ -0,0 +1 @@ +DEVICES = LDISC diff --git a/sim/ucsim/stm8.src/test/sled.c b/sim/ucsim/stm8.src/test/sled.c new file mode 100644 index 0000000..f3ffe09 --- /dev/null +++ b/sim/ucsim/stm8.src/test/sled.c @@ -0,0 +1,44 @@ +// Source code under CC0 1.0 +#include <stdint.h> + +#include "stm8.h" + +#define PD GPIOD + +unsigned int clock(void) +{ + unsigned char h = TIM1->cntrh; + unsigned char l = TIM1->cntrl; + return((unsigned int)(h) << 8 | l); +} + +unsigned int last= 0; + +void main(void) +{ + unsigned int now; + CLK->ckdivr = 0x00; // Set the frequency to 16 MHz + + // Configure timer + // 1000 ticks per second + TIM1->pscrh = 0x3e; + TIM1->pscrl = 0x80; + // Enable timer + TIM1->cr1 = 0x01; + + PD->ddr = 0x01; + PD->cr1 = 0x01; + + for(;;) + { + now= clock(); + if (now - last > 500) + { + if (PD->odr & 1) + PD->odr&= ~1; + else + PD->odr|= 1; + last= now; + } + } +} diff --git a/sim/ucsim/stm8.src/test/sled.mk b/sim/ucsim/stm8.src/test/sled.mk new file mode 100644 index 0000000..cd27c9e --- /dev/null +++ b/sim/ucsim/stm8.src/test/sled.mk @@ -0,0 +1 @@ +DEVICES = SDISC diff --git a/sim/ucsim/stm8.src/test/ss.c b/sim/ucsim/stm8.src/test/ss.c new file mode 100644 index 0000000..253b55b --- /dev/null +++ b/sim/ucsim/stm8.src/test/ss.c @@ -0,0 +1,46 @@ +// Source code under CC0 1.0 +#include <stdint.h> +#include <stdio.h> + +#define CLK_DIVR (*(volatile uint8_t *)0x50c6) +#define CLK_PCKENR1 (*(volatile uint8_t *)0x50c7) + +#define UART2_SR (*(volatile uint8_t *)0x5240) +#define UART2_DR (*(volatile uint8_t *)0x5241) +#define UART2_BRR1 (*(volatile uint8_t *)0x5242) +#define UART2_BRR2 (*(volatile uint8_t *)0x5243) +#define UART2_CR2 (*(volatile uint8_t *)0x5245) +#define UART2_CR3 (*(volatile uint8_t *)0x5246) + +#define UART_CR2_TEN (1 << 3) +#define UART_CR3_STOP2 (1 << 5) +#define UART_CR3_STOP1 (1 << 4) +#define UART_SR_TXE (1 << 7) + +int putchar(int c) +{ + while(!(UART2_SR & UART_SR_TXE)); + + UART2_DR = c; + return c; +} + +void main(void) +{ + unsigned long i = 0; + int a= 0; + + CLK_DIVR = 0x00; // Set the frequency to 16 MHz + CLK_PCKENR1 = 0xFF; // Enable peripherals + + UART2_CR2 = UART_CR2_TEN; // Allow TX and RX + UART2_CR3 &= ~(UART_CR3_STOP1 | UART_CR3_STOP2); // 1 stop bit + UART2_BRR2 = 0x03; UART2_BRR1 = 0x68; // 9600 baud + + for(;;) + { + printf("Hello World %d %x!\n", a, a); + for(i = 0; i < 147456; i++); // Sleep + a++; + } +} diff --git a/sim/ucsim/stm8.src/test/ss.mk b/sim/ucsim/stm8.src/test/ss.mk new file mode 100644 index 0000000..cd27c9e --- /dev/null +++ b/sim/ucsim/stm8.src/test/ss.mk @@ -0,0 +1 @@ +DEVICES = SDISC diff --git a/sim/ucsim/stm8.src/test/stim.c b/sim/ucsim/stm8.src/test/stim.c new file mode 100644 index 0000000..2851b9b --- /dev/null +++ b/sim/ucsim/stm8.src/test/stim.c @@ -0,0 +1,66 @@ +// Source code under CC0 1.0 +#include <stdint.h> + +#include "stm8.h" + +#define PD GPIOD + +volatile unsigned long clk= 0; + +void tim1_up_isr(void) __interrupt(TIM1_UP_IRQ) +{ + TIM1->sr1&= ~TIM_SR1_UIF; + clk++; + //PE->odr^= 0x80; +} + +unsigned int clock(void) +{ + unsigned long c; + TIM1->ier&= ~TIM_IER_UIE; + c= clk; + TIM1->ier|= TIM_IER_UIE; + return c; +} + +unsigned long last_tick1= 0; + +void tick1(unsigned long c) +{ + //unsigned long c= clock(); + if (c - last_tick1 > 500) + { + last_tick1= c; + PD->odr^= 1; + } +} + +void main(void) +{ + CLK->ckdivr = 0x00; // Set the frequency to 16 MHz + + // Configure timer + // 1000 ticks per second + TIM1->pscrh = 0; //0x3e; + TIM1->pscrl = 0; //0x80; + // Update event at every 1 ms (16000 count) + #define AR 16000 + TIM1->arrh = AR >> 8; + TIM1->arrl = AR & 0xff; + // Enable timer + TIM1->cr1 = 0x01; + + // Enable interrupt for timer1 update + TIM1->ier|= TIM_IER_UIE; + EI; + + // Configure pin + PD->ddr = 0x01; + PD->cr1 = 0x01; + + for(;;) + { + unsigned long c= clock(); + tick1(c); + } +} diff --git a/sim/ucsim/stm8.src/test/stim.mk b/sim/ucsim/stm8.src/test/stim.mk new file mode 100644 index 0000000..cd27c9e --- /dev/null +++ b/sim/ucsim/stm8.src/test/stim.mk @@ -0,0 +1 @@ +DEVICES = SDISC diff --git a/sim/ucsim/stm8.src/test/stm8.h b/sim/ucsim/stm8.src/test/stm8.h new file mode 100644 index 0000000..c9ff61a --- /dev/null +++ b/sim/ucsim/stm8.src/test/stm8.h @@ -0,0 +1,798 @@ +#ifndef STM8_HEADER +#define STM8_HEADER + +#include "stdint.h" + +/* DEVICES + */ + +#define DEV_STM8S903 0x00000001 +#define DEV_STM8S003 0x00000002 +#define DEV_STM8S005 0x00000004 +#define DEV_STM8S007 0x00000008 +#define DEV_STM8S103 0x00000010 +#define DEV_STM8S105 0x00000020 +#define DEV_STM8S207 0x00000040 +#define DEV_STM8S208 0x00000080 +#define DEV_STM8S (DEV_STM8S903|\ + DEV_STM8S003|\ + DEV_STM8S005|\ + DEV_STM8S007|\ + DEV_STM8S103|\ + DEV_STM8S105|\ + DEV_STM8S207|\ + DEV_STM8S208) + +#define DEV_STM8AF52 0x00000100 +#define DEV_STM8AF62_12 0x00000200 +#define DEV_STM8AF62_46 0x00000400 +#define DEV_STM8AF (DEV_STM8AF52|\ + DEV_STM8AF62_12|\ + DEV_STM8AF62_46) + +#define DEV_STM8SAF (DEV_STM8S|DEV_STM8AF) + +#define DEV_STM8AL3xE 0x00010000 +#define DEV_STM8AL3x8 0x00020000 +#define DEV_STM8AL3x346 0x00040000 +#define DEV_STM8AL (DEV_STM8AL3xE|\ + DEV_STM8AL3x8|\ + DEV_STM8AL3x346) + +#define DEV_STM8L051 0x01000000 +#define DEV_STM8L052C 0x02000000 +#define DEV_STM8L052R 0x04000000 +#define DEV_STM8L151x23 0x08000000 +#define DEV_STM8L15x46 0x10000000 +#define DEV_STM8L15x8 0x20000000 +#define DEV_STM8L162 0x40000000 + +#define DEV_STM8L (DEV_STM8L051|\ + DEV_STM8L052C|\ + DEV_STM8L052R|\ + DEV_STM8L151x23|\ + DEV_STM8L15x46|\ + DEV_STM8L15x8|\ + DEV_STM8L162) + +#define DEV_STM8ALL (DEV_STM8AL|DEV_STM8L) + +#define DEV_STM8L101 0x00001000 + +#define DEV_STM8LDISC DEV_STM8L15x46 +#define DEV_LDISC DEV_STM8L15x46 +#define DEV_STM8SDISC DEV_STM8S105 +#define DEV_SDISC DEV_STM8S105 + +#ifndef DEVICE +#define DEVICE DEV_STM8S208 +#endif + +//#define CLK_DIVR (*(volatile uint8_t *)0x50c6) +//#define CLK_PCKENR1 (*(volatile uint8_t *)0x50c7) + + +//#define UART2_SR (*(volatile uint8_t *)0x5240) +//#define UART2_DR (*(volatile uint8_t *)0x5241) +//#define UART2_BRR1 (*(volatile uint8_t *)0x5242) +//#define UART2_BRR2 (*(volatile uint8_t *)0x5243) +//#define UART2_CR2 (*(volatile uint8_t *)0x5245) +//#define UART2_CR3 (*(volatile uint8_t *)0x5246) + +//#define UART_CR2_TEN (1 << 3) +//#define UART_CR2_REN (1 << 2) +//#define UART_CR2_RIEN (1 << 5) +//#define UART_CR3_STOP2 (1 << 5) +//#define UART_CR3_STOP1 (1 << 4) +//#define UART_SR_TXE (1 << 7) +//#define UART_SR_RXNE (1 << 5) + + +/* GPIO + */ + +struct GPIO_t { + volatile uint8_t odr; + volatile uint8_t idr; + volatile uint8_t ddr; + volatile uint8_t cr1; + volatile uint8_t cr2; +}; + +#define GPIOA ((struct GPIO_t *)0x5000) +#define GPIOB ((struct GPIO_t *)0x5005) +#define GPIOC ((struct GPIO_t *)0x500A) +#define GPIOD ((struct GPIO_t *)0x500F) +#if (DEVICE & DEV_STM8SAF) || \ + (DEVICE & DEV_STM8AL) || \ + (DEVICE & DEV_STM8L052C) || \ + (DEVICE & DEV_STM8L052R) || \ + (DEVICE & DEV_STM8L151x23) || \ + (DEVICE & DEV_STM8L15x46) || \ + (DEVICE & DEV_STM8L15x8) || \ + (DEVICE & DEV_STM8L162) +#define GPIOE ((struct GPIO_t *)0x5014) +#define GPIOF ((struct GPIO_t *)0x5019) +#endif +#if (DEVICE & DEV_STM8S005) || \ + (DEVICE & DEV_STM8S007) || \ + (DEVICE & DEV_STM8S105) || \ + (DEVICE & DEV_STM8S207) || \ + (DEVICE & DEV_STM8S208) || \ + (DEVICE & DEV_STM8AF52) || \ + (DEVICE & DEV_STM8AF62_46) || \ + (DEVICE & DEV_STM8AL3xE) || \ + (DEVICE & DEV_STM8AL3x8) || \ + (DEVICE & DEV_STM8L052R) || \ + (DEVICE & DEV_STM8L15x8) || \ + (DEVICE & DEV_STM8L162) +#define GPIOG ((struct GPIO_t *)0x501E) +#endif +#if (DEVICE & DEV_STM8S005) || \ + (DEVICE & DEV_STM8S007) || \ + (DEVICE & DEV_STM8S105) || \ + (DEVICE & DEV_STM8S207) || \ + (DEVICE & DEV_STM8S208) || \ + (DEVICE & DEV_STM8AF52) || \ + (DEVICE & DEV_STM8AL3xE) || \ + (DEVICE & DEV_STM8AL3x8) || \ + (DEVICE & DEV_STM8L15x8) || \ + (DEVICE & DEV_STM8L162) +#define GPIOH ((struct GPIO_t *)0x5023) +#define GPIOI ((struct GPIO_t *)0x5028) +#endif + + +/* Timers + */ + +/* bits of control 1 register */ +#define TIM_CR1_CEN (1 << 0) + +/* Bits of interrupt enable register */ +#define TIM_IER_UIE (1 << 0) + +/* Bits of interrupt flag register */ +#define TIM_SR1_UIF (1 << 0) + +/* Bits of event generator register */ +#define TIM_EGR_UG (1 << 0) + +/* TIM1 + */ + +#if (DEVICE & DEV_STM8SAF) +struct TIM1_t { + volatile uint8_t cr1; //= 0; + volatile uint8_t cr2; //= 1; + volatile uint8_t smcr; //= 2; + volatile uint8_t etr; //= 3; + volatile uint8_t ier; //= 4; + volatile uint8_t sr1; //= 5; + volatile uint8_t sr2; //= 6; + volatile uint8_t egr; //= 7; + volatile uint8_t ccmr1; //= 8; + volatile uint8_t ccmr2; //= 9; + volatile uint8_t ccmr3; //= 10; + volatile uint8_t ccmr4; //= 11; + volatile uint8_t ccer1; //= 12; + volatile uint8_t ccer2; //= 13; + volatile uint8_t cntrh; //= 14; + volatile uint8_t cntrl; //= 15; + volatile uint8_t pscrh; //= 16; + volatile uint8_t pscrl; //= 17; + volatile uint8_t arrh; //= 18; + volatile uint8_t arrl; //= 19; + volatile uint8_t rcr; //= 20; + volatile uint8_t ccr1h; //= 21; + volatile uint8_t ccr1l; //= 22; + volatile uint8_t ccr2h; //= 23; + volatile uint8_t ccr2l; //= 24; + volatile uint8_t ccr3h; //= 25; + volatile uint8_t ccr3l; //= 26; + volatile uint8_t ccr4h; //= 27; + volatile uint8_t ccr4l; //= 28; + volatile uint8_t bkr; //= 29; + volatile uint8_t dtr; //= 30; + volatile uint8_t oisr; //= 31; +}; +#define TIM1_UP_IRQ 11 +#define TIM1_CC_IRQ 12 +#elif (DEVICE & DEV_STM8ALL) +struct TIM1_t { + volatile uint8_t cr1; //= 0; + volatile uint8_t cr2; //= 1; + volatile uint8_t smcr; //= 2; + volatile uint8_t etr; //= 3; + volatile uint8_t der; //= 4; + volatile uint8_t ier; //= 5; + volatile uint8_t sr1; //= 6; + volatile uint8_t sr2; //= 7; + volatile uint8_t egr; //= 8; + volatile uint8_t ccmr1; //= 9; + volatile uint8_t ccmr2; //= 10; + volatile uint8_t ccmr3; //= 11; + volatile uint8_t ccmr4; //= 12; + volatile uint8_t ccer1; //= 13; + volatile uint8_t ccer2; //= 14; + volatile uint8_t cntrh; //= 15; + volatile uint8_t cntrl; //= 16; + volatile uint8_t pscrh; //= 17; + volatile uint8_t pscrl; //= 18; + volatile uint8_t arrh; //= 19; + volatile uint8_t arrl; //= 20; + volatile uint8_t rcr; //= 21; + volatile uint8_t ccr1h; //= 22; + volatile uint8_t ccr1l; //= 23; + volatile uint8_t ccr2h; //= 24; + volatile uint8_t ccr2l; //= 25; + volatile uint8_t ccr3h; //= 26; + volatile uint8_t ccr3l; //= 27; + volatile uint8_t ccr4h; //= 28; + volatile uint8_t ccr4l; //= 29; + volatile uint8_t bkr; //= 30; + volatile uint8_t dtr; //= 31; + volatile uint8_t oisr; //= 32; +}; +#define TIM1_UP_IRQ 23 +#define TIM1_CC_IRQ 24 +#endif + +#if (DEVICE & DEV_STM8S) || (DEVICE & DEV_STM8AF) +#define TIM1 ((struct TIM1_t *)0x5250) +#endif +#if (DEVICE & DEV_STM8AL) || \ + (DEVICE & DEV_STM8L052C) || \ + (DEVICE & DEV_STM8L052R) || \ + (DEVICE & DEV_STM8L15x46) || \ + (DEVICE & DEV_STM8L15x8) || \ + (DEVICE & DEV_STM8L162) +#define TIM1 ((struct TIM1_t *)0x52B0) +#endif + +/* TIM2 + */ + +#if ((DEVICE & DEV_STM8S005) || \ + (DEVICE & DEV_STM8S007) || \ + (DEVICE & DEV_STM8S105) || \ + (DEVICE & DEV_STM8S207) || \ + (DEVICE & DEV_STM8S208) || \ + (DEVICE & DEV_STM8AF52) || \ + (DEVICE & DEV_STM8AF62_46)) +struct TIM2_t { + volatile uint8_t cr1; //= 0; + volatile uint8_t ier; //= 1; + volatile uint8_t sr1; //= 2; + volatile uint8_t sr2; //= 3; + volatile uint8_t egr; //= 4; + volatile uint8_t ccmr1; //= 5; + volatile uint8_t ccmr2; //= 6; + volatile uint8_t ccmr3; //= 7; + volatile uint8_t ccer1; //= 8; + volatile uint8_t ccer2; //= 9; + volatile uint8_t cntrh; //= 10; + volatile uint8_t cntrl; //= 11; + volatile uint8_t pscrl; //= 12; + volatile uint8_t arrh; //= 13; + volatile uint8_t arrl; //= 14; + volatile uint8_t ccr1h; //= 15; + volatile uint8_t ccr1l; //= 0x10; + volatile uint8_t ccr2h; //= 0x11; + volatile uint8_t ccr2l; //= 0x12; + volatile uint8_t ccr3h; //= 0x13; + volatile uint8_t ccr3l; //= 0x14; +}; +#define TIM2_UP_IRQ 13 +#define TIM2_CC_IRQ 14 +#define TIM2 ((struct TIM2_t *)0x5300) +#elif ((DEVICE & DEV_STM8S003) || \ + (DEVICE & DEV_STM8S103)) +struct TIM2_t { + volatile uint8_t cr1; //= 0; + volatile uint8_t _dummy1; //= 1; + volatile uint8_t _dummy2; //= 2; + volatile uint8_t ier; //= 3; + volatile uint8_t sr1; //= 4; + volatile uint8_t sr2; //= 5; + volatile uint8_t egr; //= 6; + volatile uint8_t ccmr1; //= 7; + volatile uint8_t ccmr2; //= 8; + volatile uint8_t ccmr3; //= 9; + volatile uint8_t ccer1; //= 10; + volatile uint8_t ccer2; //= 11; + volatile uint8_t cntrh; //= 12; + volatile uint8_t cntrl; //= 13; + volatile uint8_t pscrl; //= 14; + volatile uint8_t arrh; //= 15; + volatile uint8_t arrl; //= 16; + volatile uint8_t ccr1h; //= 0x11; + volatile uint8_t ccr1l; //= 0x12; + volatile uint8_t ccr2h; //= 0x13; + volatile uint8_t ccr2l; //= 0x14; + volatile uint8_t ccr3h; //= 0x15; + volatile uint8_t ccr3l; //= 0x16; +}; +#define TIM2_UP_IRQ 13 +#define TIM2_CC_IRQ 14 +#define TIM2 ((struct TIM2_t *)0x5300) +#elif (DEVICE & DEV_STM8ALL) +struct TIM2_t { + volatile uint8_t cr1; //= 0; + volatile uint8_t cr2; //= 1; + volatile uint8_t smcr; //= 2; + volatile uint8_t etr; //= 3; + volatile uint8_t der; //= 4; + volatile uint8_t ier; //= 5; + volatile uint8_t sr1; //= 6; + volatile uint8_t sr2; //= 7; + volatile uint8_t egr; //= 8; + volatile uint8_t ccmr1; //= 9; + volatile uint8_t ccmr2; //= 0x0a; + volatile uint8_t ccer1; //= 0x0b; + volatile uint8_t cntrh; //= 0x0c; + volatile uint8_t cntrl; //= 0x0d; + volatile uint8_t pscrl; //= 0x0e; + volatile uint8_t arrh; //= 0x0f; + volatile uint8_t arrl; //= 0x10; + volatile uint8_t ccr1h; //= 0x11; + volatile uint8_t ccr1l; //= 0x12; + volatile uint8_t ccr2h; //= 0x13; + volatile uint8_t ccr2l; //= 0x14; + volatile uint8_t bkr; //= 0x15; + volatile uint8_t oisr; //= 0x16; +}; +#define TIM2_UP_IRQ 19 +#define TIM2_CC_IRQ 20 +#define TIM2 ((struct TIM2_t *)0x5250) +#elif (DEVICE & DEV_STM8L101) +struct TIM2_t { + volatile uint8_t cr1; //= 0; + volatile uint8_t cr2; //= 1; + volatile uint8_t smcr; //= 2; + volatile uint8_t etr; //= 3; + volatile uint8_t ier; //= 4; + volatile uint8_t sr1; //= 5; + volatile uint8_t sr2; //= 6; + volatile uint8_t egr; //= 7; + volatile uint8_t ccmr1; //= 8; + volatile uint8_t ccmr2; //= 0x09; + volatile uint8_t ccer1; //= 0x0a; + volatile uint8_t cntrh; //= 0x0b; + volatile uint8_t cntrl; //= 0x0c; + volatile uint8_t pscrl; //= 0x0d; + volatile uint8_t arrh; //= 0x0e; + volatile uint8_t arrl; //= 0x0f; + volatile uint8_t ccr1h; //= 0x10; + volatile uint8_t ccr1l; //= 0x11; + volatile uint8_t ccr2h; //= 0x12; + volatile uint8_t ccr2l; //= 0x13; + volatile uint8_t bkr; //= 0x14; + volatile uint8_t oisr; //= 0x15; +}; +#define TIM2_UP_IRQ 19 +#define TIM2_CC_IRQ 20 +#define TIM2 ((struct TIM2_t *)0x5250) +#endif + +/* USART + */ + +#define USART_CR2_TEN (1 << 3) +#define USART_CR2_REN (1 << 2) +#define USART_CR2_RIEN (1 << 5) +#define USART_CR3_STOP2 (1 << 5) +#define USART_CR3_STOP1 (1 << 4) +#define USART_SR_TXE (1 << 7) +#define USART_SR_RXNE (1 << 5) + +/* USART1 + */ + +struct USART1_saf_t { + volatile uint8_t sr; + volatile uint8_t dr; + volatile uint8_t brr1; + volatile uint8_t brr2; + volatile uint8_t cr1; + volatile uint8_t cr2; + volatile uint8_t cr3; + volatile uint8_t cr4; + volatile uint8_t cr5; + volatile uint8_t gtr; + volatile uint8_t pscr; +}; + +struct USART1_all_t { + volatile uint8_t sr; + volatile uint8_t dr; + volatile uint8_t brr1; + volatile uint8_t brr2; + volatile uint8_t cr1; + volatile uint8_t cr2; + volatile uint8_t cr3; + volatile uint8_t cr4; + volatile uint8_t cr5; + volatile uint8_t gtr; + volatile uint8_t pscr; +}; + +struct USART1_l101_t { + volatile uint8_t sr; + volatile uint8_t dr; + volatile uint8_t brr1; + volatile uint8_t brr2; + volatile uint8_t cr1; + volatile uint8_t cr2; + volatile uint8_t cr3; + volatile uint8_t cr4; +}; + +#if (DEVICE & DEV_STM8S003) || \ + (DEVICE & DEV_STM8S007) || \ + (DEVICE & DEV_STM8S103) || \ + (DEVICE & DEV_STM8S207) || \ + (DEVICE & DEV_STM8S208) || \ + (DEVICE & DEV_STM8S903) || \ + (DEVICE & DEV_STM8AF52) +#define USART1_t USART1_saf_t +#define USART1 ((struct USART1_t *)0x5230) +#endif + +#if (DEVICE & DEV_STM8ALL) +#define USART1_t USART1_all_t +#define USART1 ((struct USART1_t *)0x5230) +#endif + +#if (DEVICE & DEV_STM8L101) +#define USART1_t USART1_l101_t +#define USART1 ((struct USART1_t *)0x5230) +#endif + +/* USART2 + */ + +struct USART2_saf_t { + volatile uint8_t sr; + volatile uint8_t dr; + volatile uint8_t brr1; + volatile uint8_t brr2; + volatile uint8_t cr1; + volatile uint8_t cr2; + volatile uint8_t cr3; + volatile uint8_t cr4; + volatile uint8_t cr5; + volatile uint8_t cr6; + volatile uint8_t gtr; + volatile uint8_t pscr; +}; + +struct USART2_all_t { + volatile uint8_t sr; + volatile uint8_t dr; + volatile uint8_t brr1; + volatile uint8_t brr2; + volatile uint8_t cr1; + volatile uint8_t cr2; + volatile uint8_t cr3; + volatile uint8_t cr4; + volatile uint8_t cr5; + volatile uint8_t gtr; + volatile uint8_t pscr; +}; + +#if (DEVICE & DEV_STM8S005) || \ + (DEVICE & DEV_STM8S105) || \ + (DEVICE & DEV_STM8AF62_46) +#define USART2_t USART2_saf_t +#define USART2 ((struct USART2_t *)0x5240) +#endif + +#if (DEVICE & DEV_STM8AL3xE) || \ + (DEVICE & DEV_STM8AL3x8) || \ + (DEVICE & DEV_STM8L052R) || \ + (DEVICE & DEV_STM8L15x8) || \ + (DEVICE & DEV_STM8L162) +#define USART2_t USART2_all_t +#define USART2 ((struct USART2_t *)0x53E0) +#endif + +/* USART3 + */ + +struct USART3_saf_t { + volatile uint8_t sr; + volatile uint8_t dr; + volatile uint8_t brr1; + volatile uint8_t brr2; + volatile uint8_t cr1; + volatile uint8_t cr2; + volatile uint8_t cr3; + volatile uint8_t cr4; + volatile uint8_t _dummy; + volatile uint8_t cr6; + volatile uint8_t gtr; + volatile uint8_t pscr; +}; + +struct USART3_all_t { + volatile uint8_t sr; + volatile uint8_t dr; + volatile uint8_t brr1; + volatile uint8_t brr2; + volatile uint8_t cr1; + volatile uint8_t cr2; + volatile uint8_t cr3; + volatile uint8_t cr4; + volatile uint8_t cr5; + volatile uint8_t gtr; + volatile uint8_t pscr; +}; + +#if (DEVICE & DEV_STM8S007) || \ + (DEVICE & DEV_STM8S207) || \ + (DEVICE & DEV_STM8S208) || \ + (DEVICE & DEV_STM8AF52) +#define USART3_t USART3_saf_t +#define USART3 ((struct USART3_t *)0x5240) +#endif + +#if (DEVICE & DEV_STM8AL3xE) || \ + (DEVICE & DEV_STM8AL3x8) || \ + (DEVICE & DEV_STM8L052R) || \ + (DEVICE & DEV_STM8L15x8) || \ + (DEVICE & DEV_STM8L162) +#define USART3_t USART3_all_t +#define USART3 ((struct USART3_t *)0x53F0) +#endif + +/* USART4 + */ + +struct USART4_saf_t { + volatile uint8_t sr; + volatile uint8_t dr; + volatile uint8_t brr1; + volatile uint8_t brr2; + volatile uint8_t cr1; + volatile uint8_t cr2; + volatile uint8_t cr3; + volatile uint8_t cr4; + volatile uint8_t cr5; + volatile uint8_t cr6; + volatile uint8_t gtr; + volatile uint8_t pscr; +}; + +#if (DEVICE & DEV_STM8AF62_12) +#define USART4_t USART4_saf_t +#define USART4 ((struct USART4_t *)0x5230) +#endif + +/* USART interrupt numbers */ + +#if (DEVICE & DEV_STM8SAF) +#if defined USART1 +#define USART1_TX_IRQ 17 +#define USART1_RX_IRQ 18 +#endif +#endif +#if (DEVICE & DEV_STM8ALL) || \ + (DEVICE & DEV_STM8_L101) +#if defined USART1 +#define USART1_TX_IRQ 27 +#define USART1_RX_IRQ 28 +#endif +#endif + +#if (DEVICE & DEV_STM8SAF) +#if defined USART2 +#define USART2_TX_IRQ 20 +#define USART2_RX_IRQ 21 +#endif +#endif +#if (DEVICE & DEV_STM8ALL) +#if defined USART2 +#define USART2_TX_IRQ 19 +#define USART2_RX_IRQ 20 +#endif +#endif + +#if (DEVICE & DEV_STM8SAF) +#if defined USART3 +#define USART3_TX_IRQ 20 +#define USART3_RX_IRQ 21 +#endif +#endif +#if (DEVICE & DEV_STM8ALL) +#if defined USART3 +#define USART3_TX_IRQ 21 +#define USART3_RX_IRQ 22 +#endif +#endif + +#if defined USART4 +#define USART3_TX_IRQ 17 +#define USART3_RX_IRQ 18 +#endif + +/* Select first USART as default */ + +#ifndef USART +#if (DEVICE & DEV_STM8S003) || \ + (DEVICE & DEV_STM8S007) || \ + (DEVICE & DEV_STM8S103) || \ + (DEVICE & DEV_STM8S207) || \ + (DEVICE & DEV_STM8S208) || \ + (DEVICE & DEV_STM8S903) || \ + (DEVICE & DEV_STM8AF52) || \ + (DEVICE & DEV_STM8ALL) || \ + (DEVICE & DEV_STM8L101) +#define USART USART1 +#define USART_TX_IRQ USART1_TX_IRQ +#define USART_RX_IRQ USART1_RX_IRQ +#endif +#if (DEVICE & DEV_STM8S005) || \ + (DEVICE & DEV_STM8S105) || \ + (DEVICE & DEV_STM8AF62_46) +#define USART USART2 +#define USART_TX_IRQ USART2_TX_IRQ +#define USART_RX_IRQ USART2_RX_IRQ +#endif +#if (DEVICE & DEV_STM8AF62_12) +#define USART USART4 +#define USART_TX_IRQ USART4_TX_IRQ +#define USART_RX_IRQ USART4_RX_IRQ +#endif +#endif +#if ((DEVICE & DEV_STM8S003) || \ + (DEVICE & DEV_STM8S005) || \ + (DEVICE & DEV_STM8S103) || \ + (DEVICE & DEV_STM8S105) || \ + (DEVICE & DEV_STM8S903) || \ + (DEVICE & DEV_STM8AF62_12) || \ + (DEVICE & DEV_STM8AF62_46)) +#define USART_TX_GPIO GPIOD +#define USART_RX_GPIO GPIOD +#define USART_TX_PIN 5 +#define USART_RX_PIN 6 +#endif +#if ((DEVICE & DEV_STM8S007) ||\ + (DEVICE & DEV_STM8S207) ||\ + (DEVICE & DEV_STM8S208) ||\ + (DEVICE & DEV_STM8AF52)) +#define USART_TX_GPIO GPIOA +#define USART_RX_GPIO GPIOA +#define USART_TX_PIN 5 +#define USART_RX_PIN 4 +#endif +#if (DEVICE & DEV_STM8AL) ||\ + (DEVICE & DEV_STM8L052C) ||\ + (DEVICE & DEV_STM8L052R) ||\ + (DEVICE & DEV_STM8L151x23) ||\ + (DEVICE & DEV_STM8L15x46) ||\ + (DEVICE & DEV_STM8L15x8) ||\ + (DEVICE & DEV_STM8L162) ||\ + (DEVICE & DEV_STM8L101) +#define USART_TX_GPIO GPIOC +#define USART_RX_GPIO GPIOC +#define USART_TX_PIN 3 +#define USART_RX_PIN 2 +#endif +#if (DEVICE & DEV_STM8L051) +/* non-default AF only because C2 and C3 are not available */ +#define USART_TX_GPIO +#define USART_RX_GPIO +#define USART_TX_PIN +#define USART_RX_PIN +#endif + +/* CLK + */ + +#if (DEVICE & DEV_STM8SAF) +struct CLK_t { + uint8_t ickr; + uint8_t eckr; + uint8_t _dummy1; + uint8_t cmsr; + uint8_t swr; + uint8_t swcr; + uint8_t ckdivr; + uint8_t pckenr1; + uint8_t cssr; + uint8_t ccor; + uint8_t pckenr2; + uint8_t _dummy2; + uint8_t hsitrimr; + uint8_t swimccr; +}; +#endif +#if (DEVICE & DEV_STM8ALL) +struct CLK_t { + uint8_t ckdivr; + uint8_t crtcr; + uint8_t ickcr; + uint8_t pckenr1; + uint8_t pckenr2; + uint8_t ccor; + uint8_t eckcr; + uint8_t scsr; + uint8_t swr; + uint8_t swcr; + uint8_t cssr; + uint8_t cbeepr; + uint8_t hsicalr; + uint8_t hsitrimr; + uint8_t hsiunclkr; + uint8_t regcsr; + uint8_t pckenr3; +}; +#endif +#if (DEVICE & DEV_STM8L101) +struct CLK_t { + uint8_t ckdivr; + uint8_t _dummy1; + uint8_t _dummy2; + uint8_t pckenr; + uint8_t _dummy3; + uint8_t ccor; +}; +#endif + +#define CLK ((struct CLK_t *)0x50C0) + +/* UID + */ + +#if (DEVICE & DEV_STM8S103) || \ + (DEVICE & DEV_STM8S903) || \ + (DEVICE & DEV_STM8AF62_12) +#define UID ((uint8_t*)0x4865) +#endif +#if (DEVICE & DEV_STM8AL) || \ + (DEVICE & DEV_STM8L151x23) || \ + (DEVICE & DEV_STM8L15x46) || \ + (DEVICE & DEV_STM8L15x8) || \ + (DEVICE & DEV_STM8L162) +#define UID ((uint8_t*)0x4926) +#endif +#if (DEVICE & DEV_STM8L101) +#define UID ((uint8_t*)0x4925) +#endif + +/* FLASH + */ + +#if (DEVICE & DEV_STM8SAF) +struct FLASH_t { + volatile uint8_t cr1; + volatile uint8_t cr2; + volatile uint8_t ncr2; + volatile uint8_t fpr; + volatile uint8_t nfpr; + volatile uint8_t iapsr; + volatile uint16_t dummy1; + volatile uint8_t pukr; + volatile uint8_t dummy2; + volatile uint8_t dukr; +}; +#define FLASH ((volatile struct FLASH_t * volatile)0x505a) +#define FLASH_IRQ 24 +#elif (DEVICE & DEV_STM8ALL) || \ + (DEVICE & DEV_STM8L101) +struct FLASH_t { + volatile uint8_t cr1; + volatile uint8_t cr2; + volatile uint8_t pukr; + volatile uint8_t dukr; + volatile uint8_t iapsr; +}; +#define FLASH ((struct FLASH_t *)0x5050) +#define FLASH_IRQ 1 +#endif + +#define EI __asm__("rim") +#define DI __asm__("sim") + +#endif diff --git a/sim/ucsim/stm8.src/test/t1.c b/sim/ucsim/stm8.src/test/t1.c new file mode 100644 index 0000000..354f72a --- /dev/null +++ b/sim/ucsim/stm8.src/test/t1.c @@ -0,0 +1,21 @@ +volatile int x= 1; + +void isr_trap(void) __trap +{ + x= 2; +} + +void trap() +{ + __asm + trap; + __endasm; +} + +void +main(void) +{ + trap(); + for (;;) + ; +} diff --git a/sim/ucsim/stm8.src/test/t2.c b/sim/ucsim/stm8.src/test/t2.c new file mode 100644 index 0000000..a3e3df8 --- /dev/null +++ b/sim/ucsim/stm8.src/test/t2.c @@ -0,0 +1,17 @@ +volatile unsigned char *sif= (unsigned char *)0x7fff; + +volatile char c; + +int f(int i) +{ + c= i; + return i; +} + +void main(void) +{ + f('H'*256 + 'L'); + *sif= 'p'; + *sif= c; + *sif= 's'; +} diff --git a/sim/ucsim/stm8.src/test/t3.c b/sim/ucsim/stm8.src/test/t3.c new file mode 100644 index 0000000..d182906 --- /dev/null +++ b/sim/ucsim/stm8.src/test/t3.c @@ -0,0 +1,15 @@ +#include <stdio.h> + +volatile unsigned char *sif= (unsigned char *)0x7fff; + +int putchar(int c) +{ + *sif= 'p'; + *sif= c; + return c; +} + +void main(void) +{ + printf("A"); +} diff --git a/sim/ucsim/stm8.src/test/t4.c b/sim/ucsim/stm8.src/test/t4.c new file mode 100644 index 0000000..d594dfe --- /dev/null +++ b/sim/ucsim/stm8.src/test/t4.c @@ -0,0 +1,16 @@ +#include <stdio.h> + +volatile unsigned char c; + +int putchar(int ch) +{ + c= ch; + return ch; +} + +void main(void) +{ + printf("A"); + putchar('B'); + for (;;) ; +} diff --git a/sim/ucsim/stm8.src/test/xtest.c b/sim/ucsim/stm8.src/test/xtest.c new file mode 100644 index 0000000..95f7598 --- /dev/null +++ b/sim/ucsim/stm8.src/test/xtest.c @@ -0,0 +1,10 @@ +#include <stdio.h> + +char buf[10]; + +void +main(void) +{ + sprintf(buf, "%x", 0x1234); + for (;;); +} diff --git a/sim/ucsim/stm8.src/test/xtest.mk b/sim/ucsim/stm8.src/test/xtest.mk new file mode 100644 index 0000000..5d8d31b --- /dev/null +++ b/sim/ucsim/stm8.src/test/xtest.mk @@ -0,0 +1 @@ +DEVICES = LDISC diff --git a/sim/ucsim/stm8.src/timer.cc b/sim/ucsim/stm8.src/timer.cc new file mode 100644 index 0000000..ad511c2 --- /dev/null +++ b/sim/ucsim/stm8.src/timer.cc @@ -0,0 +1,1435 @@ +/* + * Simulator of microcontrollers (stm8.src/timer.cc) + * + * Copyright (C) 2016,16 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#include "itsrccl.h" + +#include "clkcl.h" +#include "timercl.h" + + +enum tim_cr1_bits { + cen = 0x01, + udis = 0x02, + urs = 0x04, + opm = 0x08, + dir = 0x10, + cms = 0x60, + cms0 = 0x00, // edge aligned mode + cms1 = 0x20, // center aligned 1 (irq during downcount) + cms2 = 0x40, // center aligned 2 (irq during upcount) + cms3 = 0x60, // center aligned 3 (irq in both counting dir) + arpe = 0x80 +}; + +enum tim_sr1_bits { + uif = 0x01 +}; + +enum tim_ier_bits { + uie = 0x01 +}; + +enum tim_egr_bits { + ug = 0x01 +}; + +cl_tim::cl_tim(class cl_uc *auc, int aid, t_addr abase): + cl_hw(auc, HW_TIMER, aid, "tim") +{ + base= abase; + int i; + for (i= 0; i<32+6; i++) + regs[i]= 0; + memset(&idx, 0xff, sizeof(idx)); +} + +int +cl_tim::init(void) +{ + int i; + chars s("tim"); + s.append("%d", id); + set_name(s); + id_string= strdup(s); + cl_hw::init(); + for (i= 0; i < 32+6; i++) + { + regs[i]= register_cell(uc->rom, base+i); + } + + switch (id) + { + case 2: + bits= 16; mask= 0xffff; + break; + case 3: + bits= 16; mask= 0xffff; + break; + case 5: + bits= 16; mask= 0xffff; + break; + case 4: + bits= 8; mask= 0xff; + break; + case 6: + bits= 8; mask= 0xff; + break; + default: // 1 + bits= 16; mask= 0xffff; + break; + } + pbits= 16; + bidir= true; + clk_enabled= false; + + return 0; +} + +char * +cl_tim::cfg_help(t_addr addr) +{ + switch (addr) + { + case stm8_tim_on: return (char*)"Turn simulation of timer on/off (bool, RW)"; + } + return (char*)"Not used"; +} + +int +cl_tim::tick(int cycles) +{ + if (!on || + !clk_enabled) + return resGO; + + while (cycles--) + { + // count prescaler + if (prescaler_cnt) + prescaler_cnt--; + if (prescaler_cnt == 0) + { + prescaler_cnt= calc_prescaler() - 1; + // count + if (regs[idx.cr1]->get() & cen) + { + count(); + } + } + } + + return resGO; +} + +void +cl_tim::reset(void) +{ + int i; + + cnt= 0; + prescaler_cnt= 0; + prescaler_preload= 0; + + for (i= 0; i<32+6; i++) + regs[i]->set(0); + if (bits > 8) + regs[idx.arrh]->set(0xff); + regs[idx.arrl]->set(0xff); + + update_event(); + regs[idx.sr1]->set_bit0(uif); +} + +void +cl_tim::happen(class cl_hw *where, enum hw_event he, + void *params) +{ + if ((he == EV_CLK_ON) || + (he == EV_CLK_OFF)) + { + cl_clk_event *e= (cl_clk_event *)params; + if ((e->cath == HW_TIMER) && + (e->id == id)) + clk_enabled= he == EV_CLK_ON; + } +} + +t_mem +cl_tim::read(class cl_memory_cell *cell) +{ + t_mem v= cell->get(); + t_addr a; + + if (conf(cell, NULL)) + return v; + if (!uc->rom->is_owned(cell, &a)) + return v; + if ((a < base) || + (a >= base+32+6)) + return v; + + a-= base; + + if (a == idx.pscrl) + v= prescaler_preload && 0xff; + else if (a == idx.pscrh) + v= (prescaler_preload >> 8) & 0xff; + + else if (a == idx.cntrh) + timer_ls_buffer= regs[idx.cntrl]->get(); + else if (a == idx.cntrl) + { + if (bits > 8) + v= timer_ls_buffer; + } + + return v; +} + +void +cl_tim::write(class cl_memory_cell *cell, t_mem *val) +{ + t_addr a; + + if (conf(cell, val)) + return; + + if (conf(cell, NULL)) + return; + + *val&= 0xff; + if (!uc->rom->is_owned(cell, &a)) + return; + if ((a < base) || + (a >= base+32+6)) + return; + + a-= base; + if (a == idx.cr1) + { + u8_t v= cell->get(); + if (!bidir) + *val&= 0x1f; + else + { + if ((v & cms)) + { + *val&= ~dir; + if (v & dir) + *val|= dir; + } + } + } + else if (a == idx.egr) + { + if (*val & ug) + { + update_event(); + prescaler_cnt= calc_prescaler() - 1; + //*val&= ~0x01; + } + *val= 0; + } + else if (a == idx.pscrh) + { + prescaler_ms_buffer= *val; + //*val= cell->get(); + } + else if (a == idx.pscrl) + { + prescaler_preload= *val; + if (idx.pscrh > 0) + prescaler_preload+= prescaler_ms_buffer * 256; + } + + else if (a == idx.arrh) + { + if ((regs[idx.cr1]->get() & arpe) != 0) + { + arr_ms_buffer= *val; + //*val= cell->get(); + } + } + else if (a == idx.arrl) + { + u8_t l, h= 0; + if ((regs[idx.cr1]->get() & arpe) != 0) + { + regs[idx.arrl]->set(l= *val); + if (idx.arrh > 0) + regs[idx.arrh]->set(h= arr_ms_buffer); + if ((regs[idx.cr1]->get() & arpe) == 0) + set_counter(h*256 + l); + } + } +} + +t_mem +cl_tim::conf_op(cl_memory_cell *cell, t_addr addr, t_mem *val) +{ + switch ((enum stm8_tim_cfg)addr) + { + case stm8_tim_on: + if (val) + { + if (*val) + on= true; + else + on= false; + } + else + cell->set(on?1:0); + break; + case stm8_tim_nuof_cfg: + break; + } + return cell->get(); +} + + +void +cl_tim::count(void) +{ + u8_t c1= regs[idx.cr1]->get(); + if (get_dir()) + { + // up + u16_t arr= get_arr(); + set_counter(cnt+1); + if (cnt == arr) + { + if ((c1 & cms) == cms0) + // edge aligned + set_counter(0); + else + // center aligned + regs[idx.cr1]->set(c1|= dir); + if ((c1 & udis) == 0) + update_event(); + } + } + else + { + // down + set_counter(cnt-1); + if (cnt == 0) + { + if ((c1 & cms) == cms0) + // edge aligned + set_counter(get_arr()); + else + // center aligned + regs[idx.cr1]->set(c1&= ~dir); + if ((c1 & udis) == 0) + update_event(); + } + } +} + +u16_t +cl_tim::get_counter() +{ + if (bits > 8) + return regs[idx.cntrh]->get()*256 + regs[idx.cntrl]->get(); + return regs[idx.cntrl]->get(); +} + +u16_t +cl_tim::set_counter(u16_t val) +{ + cnt= val & mask; + regs[idx.cntrl]->set(val&0xff); + if (bits > 8) + regs[idx.cntrh]->set(val>>8); + return val; +} + +void +cl_tim::update_event(void) +{ + u8_t c1= regs[idx.cr1]->get(); + + if (c1 & opm) + regs[idx.cr1]->set_bit0(cen); + else + { + if (get_dir()) + { + // up + set_counter(0); + } + else + { + // down + u16_t ar= get_arr(); + set_counter(ar); + } + } + regs[idx.sr1]->write_bit1(uif); +} + +// true: UP, false: down +bool +cl_tim::get_dir() +{ + return !(regs[idx.cr1]->get() & dir); +} + +u16_t +cl_tim::get_arr() +{ + u16_t arr= regs[idx.arrl]->get(); + if (bits > 8) + arr+= regs[idx.arrh]->get() * 256; + return arr; +} + +u16_t +cl_tim::calc_prescaler() +{ + u16_t v; + switch (pbits) + { + case 3: + v= (1 << (prescaler_preload & 0x07)); + break; + case 4: + v= (1 << (prescaler_preload & 0x0f)); + break; + default: // 16 + v= prescaler_preload + 1; + break; + } + return v; +} + +void +cl_tim::print_info(class cl_console_base *con) +{ + u8_t c1= regs[idx.cr1]->get(); + // features + con->dd_printf("Simulation of %s is %s\n", get_name(), on?"ON":"OFF"); + con->dd_printf("%s %d bit %s counter at 0x%06x\n", get_name(), bits, + bidir?"Up/Down":"Up", base); + // actual values + con->dd_printf("clk= %s\n", clk_enabled?"enabled":"disabled"); + con->dd_printf("cnt= 0x%04x %d %s\n", cnt, cnt, (c1&cen)?"on":"off"); + con->dd_printf("dir= %s\n", (c1&dir)?"down":"up"); + con->dd_printf("prs= 0x%04x %d of 0x%04x %d\n", + prescaler_cnt, prescaler_cnt, + calc_prescaler(), calc_prescaler()); + con->dd_printf("arr= 0x%04x %d\n", get_arr(), get_arr()); + print_cfg_info(con); +} + + +/************************************************************************ 1 */ + +cl_tim1::cl_tim1(class cl_uc *auc, int aid, t_addr abase): + cl_tim(auc, aid, abase) +{ +} + +int +cl_tim1::init(void) +{ + cl_tim::init(); + return 0; +} + +cl_tim1_saf::cl_tim1_saf(class cl_uc *auc, int aid, t_addr abase): + cl_tim1(auc, aid, abase) +{ + idx.cr1 = 0; + idx.cr2 = 1; + idx.smcr = 2; + idx.etr = 3; + idx.ier = 4; + idx.sr1 = 5; + idx.sr2 = 6; + idx.egr = 7; + idx.ccmr1 = 8; + idx.ccmr2 = 9; + idx.ccmr3 = 10; + idx.ccmr4 = 11; + idx.ccer1 = 12; + idx.ccer2 = 13; + idx.cntrh = 14; + idx.cntrl = 15; + idx.pscrh = 16; + idx.pscrl = 17; + idx.arrh = 18; + idx.arrl = 19; + idx.rcr = 20; + idx.ccr1h = 21; + idx.ccr1l = 22; + idx.ccr2h = 23; + idx.ccr2l = 24; + idx.ccr3h = 25; + idx.ccr3l = 26; + idx.ccr4h = 27; + idx.ccr4l = 28; + idx.bkr = 29; + idx.dtr = 30; + idx.oisr = 31; +} + +int +cl_tim1_saf::init(void) +{ + class cl_it_src *is; + cl_tim1::init(); + uc->it_sources->add(is= new cl_it_src(uc, 11, + regs[idx.ier], uie, + regs[idx.sr1], uif, + 0x8008+11*4, false, false, + "timer1 update", + 30*10+1)); + is->init(); + return 0; +} + +cl_tim1_all::cl_tim1_all(class cl_uc *auc, int aid, t_addr abase): + cl_tim1(auc, aid, abase) +{ + idx.cr1 = 0; + idx.cr2 = 1; + idx.smcr = 2; + idx.etr = 3; + idx.der = 4; + idx.ier = 5; + idx.sr1 = 6; + idx.sr2 = 7; + idx.egr = 8; + idx.ccmr1 = 9; + idx.ccmr2 = 10; + idx.ccmr3 = 11; + idx.ccmr4 = 12; + idx.ccer1 = 13; + idx.ccer2 = 14; + idx.cntrh = 15; + idx.cntrl = 16; + idx.pscrh = 17; + idx.pscrl = 18; + idx.arrh = 19; + idx.arrl = 20; + idx.rcr = 21; + idx.ccr1h = 22; + idx.ccr1l = 23; + idx.ccr2h = 24; + idx.ccr2l = 25; + idx.ccr3h = 26; + idx.ccr3l = 27; + idx.ccr4h = 28; + idx.ccr4l = 29; + idx.bkr = 30; + idx.dtr = 31; + idx.oisr = 32; + //dcr1=33 + //dcr2=34 + //dmar=35 +} + +int +cl_tim1_all::init(void) +{ + class cl_it_src *is; + cl_tim1::init(); + uc->it_sources->add(is= new cl_it_src(uc, 23, + regs[idx.ier], uie, + regs[idx.sr1], uif, + 0x8008+23*4, false, false, + "timer1 update", + 30*10+1)); + is->init(); + return 0; +} + + +/********************************************************************** 235 */ + +cl_tim235::cl_tim235(class cl_uc *auc, int aid, t_addr abase): + cl_tim(auc, aid, abase) +{ +} + +int +cl_tim235::init(void) +{ + cl_tim::init(); + return 0; +} + + +/****** TIM 2 */ + +cl_tim2_saf_a::cl_tim2_saf_a(class cl_uc *auc, int aid, t_addr abase): + cl_tim235(auc, aid, abase) +{ + idx.cr1 = 0; + //idx.cr2 = 1; + //idx.smcr = 2; + //idx.etr = 3; + //der=4 + idx.ier = 1; + idx.sr1 = 2; + idx.sr2 = 3; + idx.egr = 4; + idx.ccmr1 = 5; + idx.ccmr2 = 6; + idx.ccmr3 = 7; + //idx.ccmr4 = 10; + idx.ccer1 = 8; + idx.ccer2 = 9; + idx.cntrh = 10; + idx.cntrl = 11; + //idx.pscrh = 14; + idx.pscrl = 12; + idx.arrh = 13; + idx.arrl = 14; + //idx.rcr = 21; + idx.ccr1h = 15; + idx.ccr1l = 0x10; + idx.ccr2h = 0x11; + idx.ccr2l = 0x12; + idx.ccr3h = 0x13; + idx.ccr3l = 0x14; + //idx.ccr4h = 28; + //idx.ccr4l = 29; + //idx.bkr = 30; + //idx.dtr = 31; + //idx.oisr = 32; + //dcr1=33 + //dcr2=34 + //dmar=35 +} + +int +cl_tim2_saf_a::init(void) +{ + class cl_it_src *is; + cl_tim235::init(); + pbits= 4; + bidir= false; + uc->it_sources->add(is= new cl_it_src(uc, 13, + regs[idx.ier], uie, + regs[idx.sr1], uif, + 0x8008+13*4, false, false, + "timer2 update", + 30*10+2)); + is->init(); + return 0; +} + + +cl_tim2_saf_b::cl_tim2_saf_b(class cl_uc *auc, int aid, t_addr abase): + cl_tim235(auc, aid, abase) +{ + idx.cr1 = 0; + //idx.cr2 = 1; + //idx.smcr = 2; + //idx.etr = 3; + //der=4 + idx.ier = 3; + idx.sr1 = 4; + idx.sr2 = 5; + idx.egr = 6; + idx.ccmr1 = 7; + idx.ccmr2 = 8; + idx.ccmr3 = 9; + //idx.ccmr4 = 10; + idx.ccer1 = 10; + idx.ccer2 = 11; + idx.cntrh = 12; + idx.cntrl = 13; + //idx.pscrh = 14; + idx.pscrl = 14; + idx.arrh = 15; + idx.arrl = 16; + //idx.rcr = 21; + idx.ccr1h = 0x11; + idx.ccr1l = 0x12; + idx.ccr2h = 0x13; + idx.ccr2l = 0x14; + idx.ccr3h = 0x15; + idx.ccr3l = 0x16; + //idx.ccr4h = 28; + //idx.ccr4l = 29; + //idx.bkr = 30; + //idx.dtr = 31; + //idx.oisr = 32; + //dcr1=33 + //dcr2=34 + //dmar=35 +} + +int +cl_tim2_saf_b::init(void) +{ + class cl_it_src *is; + cl_tim235::init(); + pbits= 4; + bidir= false; + uc->it_sources->add(is= new cl_it_src(uc, 13, + regs[idx.ier], uie, + regs[idx.sr1], uif, + 0x8008+13*4, false, false, + "timer2 update", + 30*10+2)); + is->init(); + return 0; +} + + +cl_tim2_all::cl_tim2_all(class cl_uc *auc, int aid, t_addr abase): + cl_tim235(auc, aid, abase) +{ + idx.cr1 = 0; + idx.cr2 = 1; + idx.smcr = 2; + idx.etr = 3; + idx.der = 4; + idx.ier = 5; + idx.sr1 = 6; + idx.sr2 = 7; + idx.egr = 8; + idx.ccmr1 = 9; + idx.ccmr2 = 0x0a; + //idx.ccmr3 = 9; + //idx.ccmr4 = 10; + idx.ccer1 = 0x0b; + //idx.ccer2 = 11; + idx.cntrh = 0x0c; + idx.cntrl = 0x0d; + //idx.pscrh = 14; + idx.pscrl = 0x0e; + idx.arrh = 0x0f; + idx.arrl = 0x10; + //idx.rcr = 21; + idx.ccr1h = 0x11; + idx.ccr1l = 0x12; + idx.ccr2h = 0x13; + idx.ccr2l = 0x14; + //idx.ccr3h = 0x15; + //idx.ccr3l = 0x16; + //idx.ccr4h = 28; + //idx.ccr4l = 29; + idx.bkr = 0x15; + //idx.dtr = 31; + idx.oisr = 0x16; + //dcr1=33 + //dcr2=34 + //dmar=35 +} + +int +cl_tim2_all::init(void) +{ + class cl_it_src *is; + cl_tim235::init(); + pbits= 3; + uc->it_sources->add(is= new cl_it_src(uc, 19, + regs[idx.ier], uie, + regs[idx.sr1], uif, + 0x8008+19*4, false, false, + "timer2 update", + 30*10+2)); + is->init(); + return 0; +} + + +cl_tim2_l101::cl_tim2_l101(class cl_uc *auc, int aid, t_addr abase): + cl_tim235(auc, aid, abase) +{ + idx.cr1 = 0; + idx.cr2 = 1; + idx.smcr = 2; + idx.etr = 3; + //idx.der = 4; + idx.ier = 4; + idx.sr1 = 5; + idx.sr2 = 6; + idx.egr = 7; + idx.ccmr1 = 8; + idx.ccmr2 = 0x09; + //idx.ccmr3 = 9; + //idx.ccmr4 = 10; + idx.ccer1 = 0x0a; + //idx.ccer2 = 11; + idx.cntrh = 0x0b; + idx.cntrl = 0x0c; + //idx.pscrh = 14; + idx.pscrl = 0x0d; + idx.arrh = 0x0e; + idx.arrl = 0x0f; + //idx.rcr = 21; + idx.ccr1h = 0x10; + idx.ccr1l = 0x11; + idx.ccr2h = 0x12; + idx.ccr2l = 0x13; + //idx.ccr3h = 0x15; + //idx.ccr3l = 0x16; + //idx.ccr4h = 28; + //idx.ccr4l = 29; + idx.bkr = 0x14; + //idx.dtr = 31; + idx.oisr = 0x15; + //dcr1=33 + //dcr2=34 + //dmar=35 +} + +int +cl_tim2_l101::init(void) +{ + class cl_it_src *is; + cl_tim235::init(); + pbits= 3; + uc->it_sources->add(is= new cl_it_src(uc, 19, + regs[idx.ier], uie, + regs[idx.sr1], uif, + 0x8008+19*4, false, false, + "timer2 update", + 30*10+2)); + is->init(); + return 0; +} + + +/****** TIM 3 */ + +cl_tim3_saf::cl_tim3_saf(class cl_uc *auc, int aid, t_addr abase): + cl_tim235(auc, aid, abase) +{ + idx.cr1 = 0; + //idx.cr2 = 1; + //idx.smcr = 2; + //idx.etr = 3; + //der=4 + idx.ier = 1; + idx.sr1 = 2; + idx.sr2 = 3; + idx.egr = 4; + idx.ccmr1 = 5; + idx.ccmr2 = 6; + //idx.ccmr3 = 9; + //idx.ccmr4 = 10; + idx.ccer1 = 7; + //idx.ccer2 = 8; + idx.cntrh = 8; + idx.cntrl = 9; + //idx.pscrh = 14; + idx.pscrl = 0xa; + idx.arrh = 0xb; + idx.arrl = 0xc; + //idx.rcr = 21; + idx.ccr1h = 0x0d; + idx.ccr1l = 0x0c; + idx.ccr2h = 0x0f; + idx.ccr2l = 0x10; + //idx.ccr3h = 0x15; + //idx.ccr3l = 0x16; + //idx.ccr4h = 28; + //idx.ccr4l = 29; + //idx.bkr = 30; + //idx.dtr = 31; + //idx.oisr = 32; + //dcr1=33 + //dcr2=34 + //dmar=35 +} + +int +cl_tim3_saf::init(void) +{ + class cl_it_src *is; + cl_tim235::init(); + pbits= 4; + bidir= false; + uc->it_sources->add(is= new cl_it_src(uc, 15, + regs[idx.ier], uie, + regs[idx.sr1], uif, + 0x8008+15*4, false, false, + "timer3 update", + 30*10+3)); + is->init(); + return 0; +} + + +cl_tim3_all::cl_tim3_all(class cl_uc *auc, int aid, t_addr abase): + cl_tim235(auc, aid, abase) +{ + idx.cr1 = 0; + idx.cr2 = 1; + idx.smcr = 2; + idx.etr = 3; + idx.der = 4; + idx.ier = 5; + idx.sr1 = 6; + idx.sr2 = 7; + idx.egr = 8; + idx.ccmr1 = 9; + idx.ccmr2 = 0x0a; + //idx.ccmr3 = 9; + //idx.ccmr4 = 10; + idx.ccer1 = 0x0b; + //idx.ccer2 = 11; + idx.cntrh = 0x0c; + idx.cntrl = 0x0d; + //idx.pscrh = 14; + idx.pscrl = 0x0e; + idx.arrh = 0x0f; + idx.arrl = 0x10; + //idx.rcr = 21; + idx.ccr1h = 0x11; + idx.ccr1l = 0x12; + idx.ccr2h = 0x13; + idx.ccr2l = 0x14; + //idx.ccr3h = 0x15; + //idx.ccr3l = 0x16; + //idx.ccr4h = 28; + //idx.ccr4l = 29; + idx.bkr = 0x15; + //idx.dtr = 31; + idx.oisr = 0x16; + //dcr1=33 + //dcr2=34 + //dmar=35 +} + +int +cl_tim3_all::init(void) +{ + class cl_it_src *is; + cl_tim235::init(); + pbits= 3; + uc->it_sources->add(is= new cl_it_src(uc, 21, + regs[idx.ier], uie, + regs[idx.sr1], uif, + 0x8008+21*4, false, false, + "timer3 update", + 30*10+3)); + is->init(); + return 0; +} + + +cl_tim3_l101::cl_tim3_l101(class cl_uc *auc, int aid, t_addr abase): + cl_tim235(auc, aid, abase) +{ + idx.cr1 = 0; + idx.cr2 = 1; + idx.smcr = 2; + idx.etr = 3; + //idx.der = 4; + idx.ier = 4; + idx.sr1 = 5; + idx.sr2 = 6; + idx.egr = 7; + idx.ccmr1 = 8; + idx.ccmr2 = 0x09; + //idx.ccmr3 = 9; + //idx.ccmr4 = 10; + idx.ccer1 = 0x0a; + //idx.ccer2 = 11; + idx.cntrh = 0x0b; + idx.cntrl = 0x0c; + //idx.pscrh = 14; + idx.pscrl = 0x0d; + idx.arrh = 0x0e; + idx.arrl = 0x0f; + //idx.rcr = 21; + idx.ccr1h = 0x10; + idx.ccr1l = 0x11; + idx.ccr2h = 0x12; + idx.ccr2l = 0x13; + //idx.ccr3h = 0x15; + //idx.ccr3l = 0x16; + //idx.ccr4h = 28; + //idx.ccr4l = 29; + idx.bkr = 0x14; + //idx.dtr = 31; + idx.oisr = 0x15; + //dcr1=33 + //dcr2=34 + //dmar=35 +} + +int +cl_tim3_l101::init(void) +{ + class cl_it_src *is; + cl_tim235::init(); + pbits= 3; + uc->it_sources->add(is= new cl_it_src(uc, 21, + regs[idx.ier], uie, + regs[idx.sr1], uif, + 0x8008+21*4, false, false, + "timer3 update", + 30*10+3)); + is->init(); + return 0; +} + + +/****** TIM 5 */ + +cl_tim5_saf::cl_tim5_saf(class cl_uc *auc, int aid, t_addr abase): + cl_tim235(auc, aid, abase) +{ + idx.cr1 = 0; + idx.cr2 = 1; + idx.smcr = 2; + //idx.etr = 3; + //der=4 + idx.ier = 3; + idx.sr1 = 4; + idx.sr2 = 5; + idx.egr = 6; + idx.ccmr1 = 7; + idx.ccmr2 = 8; + idx.ccmr3 = 9; + //idx.ccmr4 = 10; + idx.ccer1 = 0xa; + idx.ccer2 = 0xb; + idx.cntrh = 0xc; + idx.cntrl = 0xd; + //idx.pscrh = 14; + idx.pscrl = 0xe; + idx.arrh = 0xf; + idx.arrl = 0x10; + //idx.rcr = 21; + idx.ccr1h = 0x11; + idx.ccr1l = 0x12; + idx.ccr2h = 0x13; + idx.ccr2l = 0x14; + idx.ccr3h = 0x15; + idx.ccr3l = 0x16; + //idx.ccr4h = 28; + //idx.ccr4l = 29; + //idx.bkr = 30; + //idx.dtr = 31; + //idx.oisr = 32; + //dcr1=33 + //dcr2=34 + //dmar=35 +} + +int +cl_tim5_saf::init(void) +{ + class cl_it_src *is; + cl_tim235::init(); + pbits= 4; + bidir= false; + uc->it_sources->add(is= new cl_it_src(uc, 13, + regs[idx.ier], uie, + regs[idx.sr1], uif, + 0x8008+13*4, false, false, + "timer5 update", + 30*10+5)); + is->init(); + return 0; +} + + +cl_tim5_all::cl_tim5_all(class cl_uc *auc, int aid, t_addr abase): + cl_tim235(auc, aid, abase) +{ + idx.cr1 = 0; + idx.cr2 = 1; + idx.smcr = 2; + idx.etr = 3; + idx.der = 4; + idx.ier = 5; + idx.sr1 = 6; + idx.sr2 = 7; + idx.egr = 8; + idx.ccmr1 = 9; + idx.ccmr2 = 0x0a; + //idx.ccmr3 = 9; + //idx.ccmr4 = 10; + idx.ccer1 = 0x0b; + //idx.ccer2 = 11; + idx.cntrh = 0x0c; + idx.cntrl = 0x0d; + //idx.pscrh = 14; + idx.pscrl = 0x0e; + idx.arrh = 0x0f; + idx.arrl = 0x10; + //idx.rcr = 21; + idx.ccr1h = 0x11; + idx.ccr1l = 0x12; + idx.ccr2h = 0x13; + idx.ccr2l = 0x14; + //idx.ccr3h = 0x15; + //idx.ccr3l = 0x16; + //idx.ccr4h = 28; + //idx.ccr4l = 29; + idx.bkr = 0x15; + //idx.dtr = 31; + idx.oisr = 0x16; + //dcr1=33 + //dcr2=34 + //dmar=35 +} + +int +cl_tim5_all::init(void) +{ + class cl_it_src *is; + cl_tim235::init(); + pbits= 3; + uc->it_sources->add(is= new cl_it_src(uc, 27, + regs[idx.ier], uie, + regs[idx.sr1], uif, + 0x8008+27*4, false, false, + "timer5 update", + 30*10+5)); + is->init(); + return 0; +} + + +/*********************************************************************** 46 */ + +cl_tim46::cl_tim46(class cl_uc *auc, int aid, t_addr abase): + cl_tim(auc, aid, abase) +{ +} + +int +cl_tim46::init(void) +{ + cl_tim::init(); + pbits= 4; + return 0; +} + + +/********* TIM 4 */ + +cl_tim4_saf_a::cl_tim4_saf_a(class cl_uc *auc, int aid, t_addr abase): + cl_tim46(auc, aid, abase) +{ + idx.cr1 = 0; + //idx.cr2 = 1; + //idx.smcr = 2; + //idx.etr = 3; + //idx.der = 4; + idx.ier = 1; + idx.sr1 = 2; + //idx.sr2 = 7; + idx.egr = 3; + //idx.ccmr1 = 9; + //idx.ccmr2 = 0x0a; + //idx.ccmr3 = 9; + //idx.ccmr4 = 10; + //idx.ccer1 = 0x0b; + //idx.ccer2 = 11; + //idx.cntrh = 0x0c; + idx.cntrl = 0x04; + //idx.pscrh = 14; + idx.pscrl = 0x05; + //idx.arrh = 0x0f; + idx.arrl = 0x06; + //idx.rcr = 21; + //idx.ccr1h = 0x11; + //idx.ccr1l = 0x12; + //idx.ccr2h = 0x13; + //idx.ccr2l = 0x14; + //idx.ccr3h = 0x15; + //idx.ccr3l = 0x16; + //idx.ccr4h = 28; + //idx.ccr4l = 29; + //idx.bkr = 0x15; + //idx.dtr = 31; + //idx.oisr = 0x16; + //dcr1=33 + //dcr2=34 + //dmar=35 +} + +int +cl_tim4_saf_a::init(void) +{ + class cl_it_src *is; + cl_tim46::init(); + pbits= 3; + bidir= false; + uc->it_sources->add(is= new cl_it_src(uc, 23, + regs[idx.ier], uie, + regs[idx.sr1], uif, + 0x8008+23*4, false, false, + "timer4 update", + 30*10+4)); + is->init(); + return 0; +} + + +cl_tim4_saf_b::cl_tim4_saf_b(class cl_uc *auc, int aid, t_addr abase): + cl_tim46(auc, aid, abase) +{ + idx.cr1 = 0; + //idx.cr2 = 1; + //idx.smcr = 2; + //idx.etr = 3; + //idx.der = 4; + idx.ier = 3; + idx.sr1 = 4; + //idx.sr2 = 7; + idx.egr = 5; + //idx.ccmr1 = 9; + //idx.ccmr2 = 0x0a; + //idx.ccmr3 = 9; + //idx.ccmr4 = 10; + //idx.ccer1 = 0x0b; + //idx.ccer2 = 11; + //idx.cntrh = 0x0c; + idx.cntrl = 0x06; + //idx.pscrh = 14; + idx.pscrl = 0x07; + //idx.arrh = 0x0f; + idx.arrl = 0x08; + //idx.rcr = 21; + //idx.ccr1h = 0x11; + //idx.ccr1l = 0x12; + //idx.ccr2h = 0x13; + //idx.ccr2l = 0x14; + //idx.ccr3h = 0x15; + //idx.ccr3l = 0x16; + //idx.ccr4h = 28; + //idx.ccr4l = 29; + //idx.bkr = 0x15; + //idx.dtr = 31; + //idx.oisr = 0x16; + //dcr1=33 + //dcr2=34 + //dmar=35 +} + +int +cl_tim4_saf_b::init(void) +{ + class cl_it_src *is; + cl_tim46::init(); + pbits= 3; + bidir= false; + uc->it_sources->add(is= new cl_it_src(uc, 23, + regs[idx.ier], uie, + regs[idx.sr1], uif, + 0x8008+23*4, false, false, + "timer4 update", + 30*10+4)); + is->init(); + return 0; +} + + +cl_tim4_all::cl_tim4_all(class cl_uc *auc, int aid, t_addr abase): + cl_tim46(auc, aid, abase) +{ + idx.cr1 = 0; + idx.cr2 = 1; + idx.smcr = 2; + //idx.etr = 3; + idx.der = 3; + idx.ier = 4; + idx.sr1 = 5; + //idx.sr2 = 7; + idx.egr = 6; + //idx.ccmr1 = 9; + //idx.ccmr2 = 0x0a; + //idx.ccmr3 = 9; + //idx.ccmr4 = 10; + //idx.ccer1 = 0x0b; + //idx.ccer2 = 11; + //idx.cntrh = 0x0c; + idx.cntrl = 0x07; + //idx.pscrh = 14; + idx.pscrl = 0x08; + //idx.arrh = 0x0f; + idx.arrl = 0x09; + //idx.rcr = 21; + //idx.ccr1h = 0x11; + //idx.ccr1l = 0x12; + //idx.ccr2h = 0x13; + //idx.ccr2l = 0x14; + //idx.ccr3h = 0x15; + //idx.ccr3l = 0x16; + //idx.ccr4h = 28; + //idx.ccr4l = 29; + //idx.bkr = 0x15; + //idx.dtr = 31; + //idx.oisr = 0x16; + //dcr1=33 + //dcr2=34 + //dmar=35 +} + +int +cl_tim4_all::init(void) +{ + class cl_it_src *is; + cl_tim46::init(); + pbits= 4; + bidir= false; + uc->it_sources->add(is= new cl_it_src(uc, 25, + regs[idx.ier], uie, + regs[idx.sr1], uif, + 0x8008+25*4, false, false, + "timer4 update", + 30*10+4)); + is->init(); + return 0; +} + + +cl_tim4_l101::cl_tim4_l101(class cl_uc *auc, int aid, t_addr abase): + cl_tim46(auc, aid, abase) +{ + idx.cr1 = 0; + idx.cr2 = 1; + idx.smcr = 2; + //idx.etr = 3; + //idx.der = 3; + idx.ier = 3; + idx.sr1 = 4; + //idx.sr2 = 7; + idx.egr = 5; + //idx.ccmr1 = 9; + //idx.ccmr2 = 0x0a; + //idx.ccmr3 = 9; + //idx.ccmr4 = 10; + //idx.ccer1 = 0x0b; + //idx.ccer2 = 11; + //idx.cntrh = 0x0c; + idx.cntrl = 0x06; + //idx.pscrh = 14; + idx.pscrl = 0x07; + //idx.arrh = 0x0f; + idx.arrl = 0x08; + //idx.rcr = 21; + //idx.ccr1h = 0x11; + //idx.ccr1l = 0x12; + //idx.ccr2h = 0x13; + //idx.ccr2l = 0x14; + //idx.ccr3h = 0x15; + //idx.ccr3l = 0x16; + //idx.ccr4h = 28; + //idx.ccr4l = 29; + //idx.bkr = 0x15; + //idx.dtr = 31; + //idx.oisr = 0x16; + //dcr1=33 + //dcr2=34 + //dmar=35 +} + +int +cl_tim4_l101::init(void) +{ + class cl_it_src *is; + cl_tim46::init(); + pbits= 4; + bidir= false; + uc->it_sources->add(is= new cl_it_src(uc, 25, + regs[idx.ier], uie, + regs[idx.sr1], uif, + 0x8008+25*4, false, false, + "timer4 update", + 30*10+4)); + is->init(); + return 0; +} + + +/*********** TIM6 */ + +cl_tim6_saf::cl_tim6_saf(class cl_uc *auc, int aid, t_addr abase): + cl_tim46(auc, aid, abase) +{ + idx.cr1 = 0; + idx.cr2 = 1; + idx.smcr = 2; + //idx.etr = 3; + //idx.der = 4; + idx.ier = 3; + idx.sr1 = 4; + //idx.sr2 = 7; + idx.egr = 5; + //idx.ccmr1 = 9; + //idx.ccmr2 = 0x0a; + //idx.ccmr3 = 9; + //idx.ccmr4 = 10; + //idx.ccer1 = 0x0b; + //idx.ccer2 = 11; + //idx.cntrh = 0x0c; + idx.cntrl = 0x06; + //idx.pscrh = 14; + idx.pscrl = 0x07; + //idx.arrh = 0x0f; + idx.arrl = 0x08; + //idx.rcr = 21; + //idx.ccr1h = 0x11; + //idx.ccr1l = 0x12; + //idx.ccr2h = 0x13; + //idx.ccr2l = 0x14; + //idx.ccr3h = 0x15; + //idx.ccr3l = 0x16; + //idx.ccr4h = 28; + //idx.ccr4l = 29; + //idx.bkr = 0x15; + //idx.dtr = 31; + //idx.oisr = 0x16; + //dcr1=33 + //dcr2=34 + //dmar=35 +} + +int +cl_tim6_saf::init(void) +{ + class cl_it_src *is; + cl_tim46::init(); + pbits= 3; + bidir= false; + uc->it_sources->add(is= new cl_it_src(uc, 23, + regs[idx.ier], uie, + regs[idx.sr1], uif, + 0x8008+23*4, false, false, + "timer6 update", + 30*10+6)); + is->init(); + return 0; +} + + +/* End of stm8.src/timer.cc */ diff --git a/sim/ucsim/stm8.src/timer.o b/sim/ucsim/stm8.src/timer.o Binary files differnew file mode 100644 index 0000000..55bc3d9 --- /dev/null +++ b/sim/ucsim/stm8.src/timer.o diff --git a/sim/ucsim/stm8.src/timercl.h b/sim/ucsim/stm8.src/timercl.h new file mode 100644 index 0000000..b71fd34 --- /dev/null +++ b/sim/ucsim/stm8.src/timercl.h @@ -0,0 +1,282 @@ +/* + * Simulator of microcontrollers (stm8.src/timercl.h) + * + * Copyright (C) 2016,16 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#ifndef STM8_TIMERCL_HEADER +#define STM8_TIMERCL_HEADER + +#include "hwcl.h" + + +enum stm8_tim_cfg { + stm8_tim_on= 0, + stm8_tim_nuof_cfg= 1 +}; + + +class cl_tim: public cl_hw +{ + protected: + struct + { + int + // register indexes + cr1, // control 1 + cr2, // control 2 (used in Master/Slave timers only, all except SAF 235) + smcr, // slave mode control + etr, // external trigger + der, // + ier, // interrupt enable + sr1, // status 1 + sr2, // status 2 + egr, // event generation + ccmr1, // capture/compare mode 1 + ccmr2, // capture/compare mode 2 + ccmr3, // capture/compare mode 3 + ccmr4, // capture/compare mode 4 + ccer1, // capture/compare enable 1 + ccer2, // capture/compare enable 2 + cntrh, // counter high + cntrl, // counter low + pscrh, // prescaler high (used only n TIM1) + pscrl, // prescaler low + arrh, // auto-reload high (used in 16 bit counters) + arrl, // auto-reload low + rcr, // repetition counter + ccr1h, // capture/compare 1 high + ccr1l, // capture/compare 1 low + ccr2h, // capture/compare 2 high + ccr2l, // capture/compare 2 low + ccr3h, // capture/compare 3 high + ccr3l, // capture/compare 3 low + ccr4h, // capture/compare 4 high + ccr4l, // capture/compare 4 low + bkr, // break + dtr, // deadtime + oisr; // output idle state + } + idx; + protected: + t_addr base; + cl_memory_cell *regs[32+6]; + bool clk_enabled; + + int cnt; // copy of counter value + + // Features + int bits; // size of counter: 8 or 16 + int mask; // binary mask according to counter size + int pbits; // nuof bits used in prescaler value + bool bidir; + + // Internal "regs" + u16_t prescaler_cnt; // actual downcounter + u16_t prescaler_preload; // start value of prescaler downcount + u8_t prescaler_ms_buffer; // written MS buffered until LS write + u8_t arr_ms_buffer; // written MS buffered until LS write + u8_t timer_ls_buffer; // LS buffered at MS read + + public: + cl_tim(class cl_uc *auc, int aid, t_addr abase); + virtual int init(void); + virtual int cfg_size(void) { return stm8_tim_nuof_cfg; } + virtual char *cfg_help(t_addr addr); + + virtual int tick(int cycles); + virtual void reset(void); + virtual void happen(class cl_hw *where, enum hw_event he, + void *params); + + virtual t_mem read(class cl_memory_cell *cell); + virtual void write(class cl_memory_cell *cell, t_mem *val); + virtual t_mem conf_op(cl_memory_cell *cell, t_addr addr, t_mem *val); + + virtual void count(void); + virtual u16_t get_counter(); + virtual u16_t set_counter(u16_t val); + virtual void update_event(void); + virtual bool get_dir(); // true: UP, false: down + virtual u16_t get_arr(); + virtual u16_t calc_prescaler(); + + virtual void print_info(class cl_console_base *con); +}; + + +// Advanced +class cl_tim1: public cl_tim +{ + public: + cl_tim1(class cl_uc *auc, int aid, t_addr abase); + virtual int init(void); +}; + +class cl_tim1_saf: public cl_tim1 +{ + public: + cl_tim1_saf(class cl_uc *auc, int aid, t_addr abase); + virtual int init(void); +}; + +class cl_tim1_all: public cl_tim1 +{ + public: + cl_tim1_all(class cl_uc *auc, int aid, t_addr abase); + virtual int init(void); +}; + + +// General purpose 2, 3, and 5 +class cl_tim235: public cl_tim +{ + public: + cl_tim235(class cl_uc *auc, int aid, t_addr abase); + virtual int init(void); +}; + +class cl_tim2_saf_a: public cl_tim235 +{ + public: + cl_tim2_saf_a(class cl_uc *auc, int aid, t_addr abase); + virtual int init(void); + virtual bool get_dir() { return true; } +}; + +class cl_tim2_saf_b: public cl_tim235 +{ + public: + cl_tim2_saf_b(class cl_uc *auc, int aid, t_addr abase); + virtual int init(void); + virtual bool get_dir() { return true; } +}; + +class cl_tim2_all: public cl_tim235 +{ + public: + cl_tim2_all(class cl_uc *auc, int aid, t_addr abase); + virtual int init(void); +}; + +class cl_tim2_l101: public cl_tim235 +{ + public: + cl_tim2_l101(class cl_uc *auc, int aid, t_addr abase); + virtual int init(void); +}; + + +class cl_tim3_saf: public cl_tim235 +{ + public: + cl_tim3_saf(class cl_uc *auc, int aid, t_addr abase); + virtual int init(void); + virtual bool get_dir() { return true; } +}; + +class cl_tim3_all: public cl_tim235 +{ + public: + cl_tim3_all(class cl_uc *auc, int aid, t_addr abase); + virtual int init(void); +}; + +class cl_tim3_l101: public cl_tim235 +{ + public: + cl_tim3_l101(class cl_uc *auc, int aid, t_addr abase); + virtual int init(void); +}; + + +class cl_tim5_saf: public cl_tim235 +{ + public: + cl_tim5_saf(class cl_uc *auc, int aid, t_addr abase); + virtual int init(void); + virtual bool get_dir() { return true; } +}; + +class cl_tim5_all: public cl_tim235 +{ + public: + cl_tim5_all(class cl_uc *auc, int aid, t_addr abase); + virtual int init(void); +}; + + +// Basic 4 and 6 +class cl_tim46: public cl_tim +{ + public: + cl_tim46(class cl_uc *auc, int aid, t_addr abase); + virtual int init(void); + virtual bool get_dir() { return true; } +}; + +class cl_tim4_saf_a: public cl_tim46 +{ + public: + cl_tim4_saf_a(class cl_uc *auc, int aid, t_addr abase); + virtual int init(void); + virtual bool get_dir() { return true; } +}; + +class cl_tim4_saf_b: public cl_tim46 +{ + public: + cl_tim4_saf_b(class cl_uc *auc, int aid, t_addr abase); + virtual int init(void); + virtual bool get_dir() { return true; } +}; + +class cl_tim4_all: public cl_tim46 +{ + public: + cl_tim4_all(class cl_uc *auc, int aid, t_addr abase); + virtual int init(void); + virtual bool get_dir() { return true; } +}; + +class cl_tim4_l101: public cl_tim46 +{ + public: + cl_tim4_l101(class cl_uc *auc, int aid, t_addr abase); + virtual int init(void); + virtual bool get_dir() { return true; } +}; + +class cl_tim6_saf: public cl_tim46 +{ + public: + cl_tim6_saf(class cl_uc *auc, int aid, t_addr abase); + virtual int init(void); + virtual bool get_dir() { return true; } +}; + + +#endif + +/* End of stm8.src/timercl.h */ diff --git a/sim/ucsim/stm8.src/uid.cc b/sim/ucsim/stm8.src/uid.cc new file mode 100644 index 0000000..25ab555 --- /dev/null +++ b/sim/ucsim/stm8.src/uid.cc @@ -0,0 +1,122 @@ +/* + * Simulator of microcontrollers (stm8.src/uid.cc) + * + * Copyright (C) 2017,17 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#include "uidcl.h" + + +cl_uid::cl_uid(class cl_uc *auc, t_addr abase): + cl_hw(auc, HW_DUMMY, 0, "uid") +{ + base= abase; +} + +static u8_t uid[12]= { + 0x00, + 0x5b, + 0x00, + 0x16, + 0x11, + 0x47, + 0x30, + 0x31, + 0x38, + 0x35, + 0x35, + 0x36 +}; + +int +cl_uid::init(void) +{ + int i; + cl_hw::init(); + for (i= 0; i < 12; i++) + { + //regs[i]= register_cell(uc->rom, base+i); + uc->rom->download(base+i, uid[i]); + uc->rom->set_cell_flag(base+i, true, CELL_READ_ONLY); + } + return 0; +} + +t_mem +cl_uid::read(class cl_memory_cell *cell) +{ + t_mem v= cell->get(); + //t_addr a; + + if (conf(cell, NULL)) + return v; + /* + if (!uc->rom->is_owned(cell, &a)) + return v; + if ((a < base) || + (a >= base+12)) + return v; + a-= base; + + cell->set(v= uid[a]); + */ + return v; +} + +void +cl_uid::write(class cl_memory_cell *cell, t_mem *val) +{ + //t_addr a; + + if (conf(cell, val)) + return; + /* + if (!uc->rom->is_owned(cell, &a)) + return; + if ((a < base) || + (a >= base+12)) + return; + a-= base; + *val= uid[a]; + */ +} + +void +cl_uid::print_info(class cl_console_base *con) +{ + /* + con->dd_printf("base= 0x%04x\n", base); + con->dd_printf("end = 0x%04x\n", base+12); + con->dd_printf("uid ="); + int i; + for (i= 0; i < 12; i++) + con->dd_printf(" %02x", uc->rom->get(base+i)); + con->dd_printf("\n"); + */ + uc->rom->dump(base, base+12, 16, con/*->get_fout()*/); + print_cfg_info(con); +} + + +/* End of stm8.src/uid.cc */ diff --git a/sim/ucsim/stm8.src/uid.o b/sim/ucsim/stm8.src/uid.o Binary files differnew file mode 100644 index 0000000..722e8b8 --- /dev/null +++ b/sim/ucsim/stm8.src/uid.o diff --git a/sim/ucsim/stm8.src/uidcl.h b/sim/ucsim/stm8.src/uidcl.h new file mode 100644 index 0000000..8ebbdf4 --- /dev/null +++ b/sim/ucsim/stm8.src/uidcl.h @@ -0,0 +1,49 @@ +/* + * Simulator of microcontrollers (stm8.src/uidcl.h) + * + * Copyright (C) 2017,17 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#ifndef UIDCL_HEADER +#define UIDCL_HEADER + +#include "hwcl.h" + +class cl_uid: public cl_hw +{ + protected: + t_addr base; + //class cl_memory_cell *regs[12]; + public: + cl_uid(class cl_uc *auc, t_addr abase); + virtual int init(void); + + virtual t_mem read(class cl_memory_cell *cell); + virtual void write(class cl_memory_cell *cell, t_mem *val); + virtual void print_info(class cl_console_base *con); +}; + +#endif + +/* End of stm8.src/uidcl.h */ |