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| author | iCatButler <i.am.catbutler@gmail.com> | 2016-07-02 16:52:21 +0100 |
|---|---|---|
| committer | iCatButler <i.am.catbutler@gmail.com> | 2016-07-02 16:52:21 +0100 |
| commit | 03cfe9e6c22044c5b6e333b90c2b0021842fffad (patch) | |
| tree | 281c0ad4632c169313b2f7fc89bd9d9b9059e28f /libpcsxcore/pgxp_cpu.c | |
| parent | e634f6058957234c46667f74143b57fae9020745 (diff) | |
| download | pcsxr-03cfe9e6c22044c5b6e333b90c2b0021842fffad.tar.gz | |
Additional checks
- Change processor transfer functions to use take both source and destination values
- Add enum values to all debug functions to double check instructions are correct
- Temporarily store instruction codes in interpreter wrappers as these are sometimes changed by branching
- Change recompiler wrapper functions to store register values in global variables in case they're changed by the original function
Diffstat (limited to 'libpcsxcore/pgxp_cpu.c')
| -rw-r--r-- | libpcsxcore/pgxp_cpu.c | 12 |
1 files changed, 8 insertions, 4 deletions
diff --git a/libpcsxcore/pgxp_cpu.c b/libpcsxcore/pgxp_cpu.c index f2fff96e..c9022046 100644 --- a/libpcsxcore/pgxp_cpu.c +++ b/libpcsxcore/pgxp_cpu.c @@ -773,32 +773,36 @@ void PGXP_CPU_SB(u32 instr, u8 rtVal, u32 addr) //////////////////////////////////// // Data transfer tracking //////////////////////////////////// -void PGXP_CP0_MFC0(u32 instr, u32 rdVal) +void PGXP_CP0_MFC0(u32 instr, u32 rtVal, u32 rdVal) { // CPU[Rt] = CP0[Rd] Validate(&CP0_reg[rd(instr)], rdVal); CPU_reg[rt(instr)] = CP0_reg[rd(instr)]; + CPU_reg[rt(instr)].value = rtVal; } -void PGXP_CP0_MTC0(u32 instr, u32 rtVal) +void PGXP_CP0_MTC0(u32 instr, u32 rdVal, u32 rtVal) { // CP0[Rd] = CPU[Rt] Validate(&CPU_reg[rt(instr)], rtVal); CP0_reg[rd(instr)] = CPU_reg[rt(instr)]; + CP0_reg[rd(instr)].value = rdVal; } -void PGXP_CP0_CFC0(u32 instr, u32 rdVal) +void PGXP_CP0_CFC0(u32 instr, u32 rtVal, u32 rdVal) { // CPU[Rt] = CP0[Rd] Validate(&CP0_reg[rd(instr)], rdVal); CPU_reg[rt(instr)] = CP0_reg[rd(instr)]; + CPU_reg[rt(instr)].value = rtVal; } -void PGXP_CP0_CTC0(u32 instr, u32 rtVal) +void PGXP_CP0_CTC0(u32 instr, u32 rdVal, u32 rtVal) { // CP0[Rd] = CPU[Rt] Validate(&CPU_reg[rt(instr)], rtVal); CP0_reg[rd(instr)] = CPU_reg[rt(instr)]; + CP0_reg[rd(instr)].value = rdVal; } void PGXP_CP0_RFE(u32 instr) |
