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* defconfig: remove useless usb storage stuffMoyster2019-08-011-11/+11
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* defconfig: remove unused comp algosMoyster2019-08-011-4/+2
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* Enlarge ram console size from 12KB to 15KB.Piazza Lo2019-05-032-2/+2
| | | | | | | | BUG:67857304 Change-Id: I7bb176458bd6b8d62218dea3e5e9a9d815afc5ee Signed-off-by: Piazza Lo <piazza.lo@mediatek.com> Signed-off-by: Moyster <oysterized@gmail.com>
* ARM: 7933/1: rename ioremap_cached to ioremap_cacheRob Herring2019-05-031-1/+1
| | | | | | | | | | | | | | | | | | | | | ioremap_cache is more aligned with other architectures. There are only 2 users of this in the kernel: pxa2xx-flash and Xen. This fixes Xen build failures on arm64: drivers/tty/hvc/hvc_xen.c:233:2: error: implicit declaration of function 'ioremap_cached' [-Werror=implicit-function-declaration] drivers/xen/grant-table.c:1174:3: error: implicit declaration of function 'ioremap_cached' [-Werror=implicit-function-declaration] drivers/xen/xenbus/xenbus_probe.c:778:4: error: implicit declaration of function 'ioremap_cached' [-Werror=implicit-function-declaration] Signed-off-by: Rob Herring <rob.herring@calxeda.com> Signed-off-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git Git-commit: 0a5ccc86507f45b80831dac1049197c4d45be955 [joonwoop@codeaurora.org: fixed trivial merge conflict.] Signed-off-by: Joonwoo Park <joonwoop@codeaurora.org> Change-Id: I867b893aa63bc8647ed0d7cbf66b7fbb464ef8f0
* arm64/xen: implement ioremap_cached on arm64Stefano Stabellini2019-05-031-0/+2
| | | | | | | | Change-Id: I567349ba54959b45e817e8ebacbb8babca1ca453 Signed-off-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com> Git-Repo: git://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/ Git-commit: 22d4102f778df9cab47e871b8de3400f6e685378 Signed-off-by: Abhimanyu Kapur <abhimany@codeaurora.org>
* defconfig: fixMoyster2019-05-021-4/+8
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* defconfig: regenMoyster2019-01-131-6/+2
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* defconfig: cleanup quota configMoyster2019-01-131-4/+4
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* defconfig: enable AES-GCMMoyster2019-01-131-1/+1
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* defconfig: regen for sdfat and new ram_consoleMoyster2018-12-021-19/+23
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* defconfig: build with CONFIG_MAGIC_SYSRQMoyster2018-12-021-1/+1
| | | | fixes : [ 206.299213]<1> (1)[1:init]android_reboot: Failed to open sysrq-trigger.
* arm64: build vdso without libgcovArnd Bergmann2018-11-301-0/+3
| | | | | | | | | | | | | | | | | | commit 543097843ca7c9ac3758d0b5879ea2a6f44089de upstream. On a cross-toolchain without glibc support, libgcov may not be available, and attempting to build an arm64 kernel with GCOV enabled then results in a build error: /home/arnd/cross-gcc/lib/gcc/aarch64-linux/5.2.1/../../../../aarch64-linux/bin/ld: cannot find -lgcov We don't really want to link libgcov into the vdso anyway, so this patch just disables GCOV in the vdso directory, just as we do for most other architectures. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* Revert "GCC: Fix up for gcc 5+"Moyster2018-11-301-1/+0
| | | | This reverts commit ff505baaf412985af758d5820cd620ed9f1a7e05.
* arm64: support __int128 on gcc 5+Jason A. Donenfeld2018-11-303-1/+82
| | | | | | | | | | | | | | | | | | | | | | | [Upstream: fb8722735f50cd51204bfbeefa2e5e7e9ff5b2be] [Upstream: 9bfe7553fadb269e45a6e10f68b727957dff5676] Versions of gcc prior to gcc 5 emitted a __multi3 function call when dealing with TI types, resulting in failures when trying to link to libgcc, and more generally, bad performance. However, since gcc 5, the compiler supports actually emitting fast instructions, which means we can at long last enable this option and receive the speedups. The gcc commit that added proper Aarch64 support is: https://gcc.gnu.org/git/?p=gcc.git;a=commitdiff;h=d1ae7bb994f49316f6f63e6173f2931e837a351d This commit appears to be part of the gcc 5 release. There are still a few instructions, __lshrti3, __ashlti3, and __ashrti3, which require libgcc, which is fine. Rather than linking to libgcc, we simply provide them ourselves, since they're not that complicated. Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Nathan Chancellor <natechancellor@gmail.com>
* Replace <asm/uaccess.h> with <linux/uaccess.h> globallyLinus Torvalds2018-11-292-2/+2
| | | | | | | | | | | | | | This was entirely automated, using the script by Al: PATT='^[[:blank:]]*#[[:blank:]]*include[[:blank:]]*<asm/uaccess.h>' sed -i -e "s!$PATT!#include <linux/uaccess.h>!" \ $(git grep -l "$PATT"|grep -v ^include/linux/uaccess.h) to do the replacement at the end of the merge window. Requested-by: Al Viro <viro@zeniv.linux.org.uk> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org> Signed-off-by: Moyster <oysterized@gmail.com>
* defconfig: regen m2note_defconfigMoyster2018-11-291-0/+3
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* arm64: kuser32-bit helpers: dont include unistd32.hAmit Pundir2018-11-291-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | While building lsk-3.10-android branch, we run into a series of build warnings for arm64 arch: ---------- In file included from arch/arm64/kernel/kuser32.S:32:0: arch/arm64/include/asm/unistd32.h:24:0: warning: "__NR_restart_syscall" redefined #define __NR_restart_syscall 0 ^ In file included from include/asm-generic/unistd.h:1:0, from arch/arm64/include/uapi/asm/unistd.h:16, from arch/arm64/include/asm/unistd.h:50, from arch/arm64/kernel/kuser32.S:31: include/uapi/asm-generic/unistd.h:390:0: note: this is the location of the previous definition #define __NR_restart_syscall 128 ^ In file included from arch/arm64/kernel/kuser32.S:32:0: arch/arm64/include/asm/unistd32.h:26:0: warning: "__NR_exit" redefined #define __NR_exit 1 ^ In file included from include/asm-generic/unistd.h:1:0, from arch/arm64/include/uapi/asm/unistd.h:16, from arch/arm64/include/asm/unistd.h:50, from arch/arm64/kernel/kuser32.S:31: include/uapi/asm-generic/unistd.h:292:0: note: this is the location of the previous definition #define __NR_exit 93 ^ ---------- This fix removes asm/unitstd32.h include to avoid duplication of "__NR_" syscall definitions. It is based on mainline commit: f3e5c847ec3d "arm64: Add __NR_* definitions for compat syscalls". The corresponding change in AOSP (commit: cfc7e99e9e39, "arm64: Add..") seem to be the early version or backport of the above mainline commit to aosp/android-3.10. The only difference between mainline and aosp commit is that the latter didn't have to deal with that problematic include because it is not present in aosp/android-3.10 unlike mainline or lsk-v3.10-android tree. Signed-off-by: Amit Pundir <amit.pundir@linaro.org> Signed-off-by: Kevin Hilman <khilman@linaro.org>
* GCC: Fix up for gcc 5+mydongistiny2018-11-291-0/+1
| | | | | Signed-off-by: mydongistiny <jaysonedson@gmail.com> Signed-off-by: Mister Oyster <oysterized@gmail.com>
* arm64: move ET_DYN base lower in the address spaceDaniel Micay2018-05-161-2/+2
| | | | Signed-off-by: Daniel Micay <danielmicay@gmail.com>
* arm64: determine stack entropy based on mmap entropyDaniel Micay2018-05-161-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | Stack mapping entropy is currently hard-wired to 11 bits of entropy on 32-bit and 18 bits of entropy on 64-bit. The stack itself gains an extra 8 bits of entropy from lower bit randomization within 16 byte alignment constraints. The argument block could have all lower bits randomized but it currently only gets the mapping randomization. Rather than hard-wiring values this switches to using the mmap entropy configuration like the mmap base and executable base, resulting in a range of 8 to 16 bits on 32-bit and 18 to 24 bits on 64-bit (with 4k pages) depending on kernel configuration and overridable via the sysctl entries. It's worth noting that since these kernel configuration options default to the minimum supported entropy value, the entropy on 32-bit will drop from 11 to 8 bits for builds using the defaults. However, following the configuration seems like the right thing to do regardless. At the very least, changing the defaults for COMPAT (32-bit processes on 64-bit) should be considered due to the larger address space compared to real 32-bit. Signed-off-by: Daniel Micay <danielmicay@gmail.com>
* arm64: properly account for stack rnd in mmap baseDaniel Micay2018-05-161-1/+4
| | | | | | | | | | The stack ASLR base was not included in the gap size for rlimit values larger than MIN_GAP, resulting in insufficient space being reserved. PaX uses an alternate approach where the mmap base is instead offset from the actual random stack base, but this works for the time being. Signed-off-by: Daniel Micay <danielmicay@gmail.com>
* arm64: issue isb when trapping CNTVCT_EL0 accessGreg Hackmann2018-01-151-0/+2
| | | | | Bug: 68266545 Change-Id: I6005a6e944494257bfc2243fde2f7a09c3fd76c6
* BACKPORT: arm64: Add CNTFRQ_EL0 trap handlerMarc Zyngier2018-01-152-0/+15
| | | | | | | | | | | | | | | | | | | | | We now trap accesses to CNTVCT_EL0 when the counter is broken enough to require the kernel to mediate the access. But it turns out that some existing userspace (such as OpenMPI) do probe for the counter frequency, leading to an UNDEF exception as CNTVCT_EL0 and CNTFRQ_EL0 share the same control bit. The fix is to handle the exception the same way we do for CNTVCT_EL0. Bug: 68266545 Fixes: a86bd139f2ae ("arm64: arch_timer: Enable CNTVCT_EL0 trap if workaround is enabled") Reported-by: Hanjun Guo <guohanjun@huawei.com> Tested-by: Hanjun Guo <guohanjun@huawei.com> Reviewed-by: Hanjun Guo <guohanjun@huawei.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> (cherry picked from commit 9842119a238bfb92cbab63258dabb54f0e7b111b) Change-Id: Ie5a9a93fcca238d6097ecacd6df0e540be90220b
* BACKPORT: arm64: Add CNTVCT_EL0 trap handlerMarc Zyngier2018-01-153-1/+68
| | | | | | | | | | | | | | Since people seem to make a point in breaking the userspace visible counter, we have no choice but to trap the access. Add the required handler. Bug: 68266545 Acked-by: Thomas Gleixner <tglx@linutronix.de> Acked-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> (cherry picked from commit 6126ce0588eb5a0752d5c8b5796a7fca324fd887) Change-Id: I0705f47c85a78040df38df18f51a4a22500b904d
* mtk: turn unneeded MTK_WFD_SUPPORTMister Oyster2018-01-132-2/+0
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* defconfig: renable ext4_fs_encryptionMister Oyster2018-01-051-2/+2
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* defconfig: don't build ecryptfs & turn off ext4 FBE based encryptionMister Oyster2018-01-011-3/+2
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* crypto: remove duplicate impl.Mister Oyster2017-12-279-4232/+0
| | | | | | | | | | Revert "crypto: arm64/sha2 - add generated .S files to .gitignore" This reverts commit 9345ccbf273209e3946c3981122d068221a135d2. Revert "crypto: arm64/sha2 - integrate OpenSSL implementations of SHA256/SHA512" This reverts commit 02ea19edc643061fab3b6ea8bd54b96110a9f43b.
* defconfig: enable CRC32_ARM64 algoMister Oyster2017-12-271-1/+1
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* arm64: dts: add DT entry to mount /system early during bootfire8552017-12-273-0/+51
| | | | | | BaCkPoRtEd To 3.10 By ThE BigGeSt MidGeT iN tHe GaMe Signed-off-by: Mister Oyster <oysterized@gmail.com>
* defconfig: regen and disable MTK_PASSPOINT_R1_SUPPORTMister Oyster2017-12-271-2/+1
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* UPSTREAM: arm64: jump labels: NOP out NOP -> NOP replacementMark Rutland2017-12-251-14/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the arm64 arch_static_branch implementation we place an A64 NOP into the instruction stream and log relevant details to a jump_entry in a __jump_table section. Later this may be replaced with an immediate branch without link to the code for the unlikely case. At init time, the core calls arch_jump_label_transform_static to initialise the NOPs. On x86 this involves inserting the optimal NOP for a given microarchitecture, but on arm64 we only use the architectural NOP, and hence replace each NOP with the exact same NOP. This is somewhat pointless. Additionally, at module load time we don't call jump_label_apply_nops to patch the optimal NOPs in, unlike other architectures, but get away with this because we only use the architectural NOP anyway. A later notifier will patch NOPs with branches as required. Similarly to x86 commit 11570da1c5b1dee1 (x86/jump-label: Do not bother updating NOPs if they are correct), we can avoid patching NOPs with identical NOPs. Given that we only use a single NOP encoding, this means we can NOP-out the body of arch_jump_label_transform_static entirely. As the default __weak arch_jump_label_transform_static implementation performs a patch, we must use an empty function to achieve this. Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Jiang Liu <liuj97@gmail.com> Cc: Laura Abbott <lauraa@codeaurora.org> Acked-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> (cherry picked from commit 6ddae4186886a81e22ad78ad7c6936ed36bc8225) Signed-off-by: Tomasz Figa <tfiga@chromium.org> Bug: 24475017 Change-Id: I9ef07c3a5a7f91418b30006850fcc0c421e147e2 Signed-off-by: Kees Cook <keescook@google.com> Signed-off-by: franciscofranco <franciscofranco.1990@gmail.com> Signed-off-by: Joe Maples <joe@frap129.org>
* arm64: use the new *_relaxed macros for lower power usagefranciscofranco2017-12-255-9/+9
| | | | | | Signed-off-by: franciscofranco <franciscofranco.1990@gmail.com> Signed-off-by: Joe Maples <joe@frap129.org> Signed-off-by: Mister Oyster <oysterized@gmail.com>
* defconfig: remove VMEMMister Oyster2017-12-242-2/+0
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* defconfig: remove android_pmem config (and delete recovery_defconfig, never ↵Mister Oyster2017-12-243-3316/+0
| | | | used)
* ARM64: Wire up getrandom.Josh Gao2017-12-232-1/+3
| | | | | Bug: http://b/29621447 Change-Id: I2e7623ae13318b91589d17d779391c4baa292421
* cflags: cleanup Makefile & arm64 Makefile (-ftree-vectorize is enabled when ↵Moyster2017-12-221-1/+1
| | | | building with O3, let's keep it clean)
* defconfig: raise frame_warm to 2048Moyster2017-12-221-1/+1
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* Revert "arch/arm64: skip randomization within stack"Mister Oyster2017-12-221-0/+2
| | | | This reverts commit 76848d1b0190a973e54cde8b7dab8af87b34f6f5.
* defconfig: support NFSMister Oyster2017-12-221-1/+25
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* defconfig: disable selinux bootparamMister Oyster2017-12-221-2/+1
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* defconfig: don't build old deprecated OSS sound stuffMister Oyster2017-12-221-8/+5
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* defconfig: update mmap_rnd_* to max valueMister Oyster2017-12-211-2/+2
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* defconfig: turnoff deprecated configMister Oyster2017-12-211-1/+1
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* defconfig: support LZMA/XZ/LZ4 compressed ramdiskMister Oyster2017-12-211-5/+15
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* defconfig: enable chacha20_neonMister Oyster2017-12-211-0/+1
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* backport: crypto: arm64/chacha20 - implement NEON version based on SSE3 codeArd Biesheuvel2017-12-214-0/+596
| | | | | | | | | | | | | | This is a straight port to arm64/NEON of the x86 SSE3 implementation of the ChaCha20 stream cipher. It uses the new skcipher walksize attribute to process the input in strides of 4x the block size. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au> backported to 3.10 the same way arm chacha20 SNEON3 imp. for 3.18 was done : https://android-review.googlesource.com/c/kernel/common/+/551349 Signed-off-by: Mister Oyster <oysterized@gmail.com>
* arm64/crypto: issue aese/aesmc instructions in pairsArd Biesheuvel2017-12-212-13/+9
| | | | | | | | | | | | | | | | | | | This changes the AES core transform implementations to issue aese/aesmc (and aesd/aesimc) in pairs. This enables a micro-architectural optimization in recent Cortex-A5x cores that improves performance by 50-90%. Measured performance in cycles per byte (Cortex-A57): CBC enc CBC dec CTR before 3.64 1.34 1.32 after 1.95 0.85 0.93 Note that this results in a ~5% performance decrease for older cores. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Will Deacon <will.deacon@arm.com> (cherry picked from commit 4a97abd44329bf7b9c57f020224da5f823c9c9ea) Change-Id: I9d6b28b9bd9263bb273607590704111529323ca9
* arm64: crypto: increase AES interleave to 4xArd Biesheuvel2017-12-211-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch increases the interleave factor for parallel AES modes to 4x. This improves performance on Cortex-A57 by ~35%. This is due to the 3-cycle latency of AES instructions on the A57's relatively deep pipeline (compared to Cortex-A53 where the AES instruction latency is only 2 cycles). At the same time, disable inline expansion of the core AES functions, as the performance benefit of this feature is negligible. Measured on AMD Seattle (using tcrypt.ko mode=500 sec=1): Baseline (2x interleave, inline expansion) ------------------------------------------ testing speed of async cbc(aes) (cbc-aes-ce) decryption test 4 (128 bit key, 8192 byte blocks): 95545 operations in 1 seconds test 14 (256 bit key, 8192 byte blocks): 68496 operations in 1 seconds This patch (4x interleave, no inline expansion) ----------------------------------------------- testing speed of async cbc(aes) (cbc-aes-ce) decryption test 4 (128 bit key, 8192 byte blocks): 124735 operations in 1 seconds test 14 (256 bit key, 8192 byte blocks): 92328 operations in 1 seconds Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> (cherry picked from commit 0eee0fbd41c7b57d01136df2519c92ec1506e333) Change-Id: I0fb82b0cc7f685a13c3d15c919be435917e17429
* arm64/crypto: use crypto instructions to generate AES key scheduleArd Biesheuvel2017-12-215-11/+133
| | | | | | | | | | | | | | This patch implements the AES key schedule generation using ARMv8 Crypto Instructions. It replaces the table based C implementation in aes_generic.ko, which means we can drop the dependency on that module. Tested-by: Steve Capper <steve.capper@linaro.org> Acked-by: Steve Capper <steve.capper@linaro.org> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Will Deacon <will.deacon@arm.com> (cherry picked from commit 12ac3efe74f888a13cb4df88b38bb01e8034dea8) Change-Id: I48488f43e280c4de8256365eb0be40d7be26d418
generated by cgit v1.2.3 (git 2.39.1) at 2026-03-14 08:31:23 +0000