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* Fix "BACKPORT: ARM: wire up getrandom syscall"Michael Bestas2019-07-071-1/+1
| | | | | | | * Syscalls need to be greater than __NR_last_syscall+1 in order to account for the padding in the syscall table Change-Id: Ide15e25e8a2287fff29c75d898c935318b660ea2
* BACKPORT: ARM: wire up getrandom syscall Clean cherry pick of ↵Russell King2019-07-072-6/+12
| | | | | | | | | | | | eb6452537b280652eee66801ec97cc369e27e5d8. Add the new getrandom syscall for ARM. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Bug: http://b/29621447 Change-Id: I6d50b57f3a61fbf9102c69103b9a5b7ebf239860 (cherry picked from commit eb6452537b280652eee66801ec97cc369e27e5d8)
* ARM: 7933/1: rename ioremap_cached to ioremap_cacheRob Herring2019-05-032-2/+2
| | | | | | | | | | | | | | | | | | | | | ioremap_cache is more aligned with other architectures. There are only 2 users of this in the kernel: pxa2xx-flash and Xen. This fixes Xen build failures on arm64: drivers/tty/hvc/hvc_xen.c:233:2: error: implicit declaration of function 'ioremap_cached' [-Werror=implicit-function-declaration] drivers/xen/grant-table.c:1174:3: error: implicit declaration of function 'ioremap_cached' [-Werror=implicit-function-declaration] drivers/xen/xenbus/xenbus_probe.c:778:4: error: implicit declaration of function 'ioremap_cached' [-Werror=implicit-function-declaration] Signed-off-by: Rob Herring <rob.herring@calxeda.com> Signed-off-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git Git-commit: 0a5ccc86507f45b80831dac1049197c4d45be955 [joonwoop@codeaurora.org: fixed trivial merge conflict.] Signed-off-by: Joonwoo Park <joonwoop@codeaurora.org> Change-Id: I867b893aa63bc8647ed0d7cbf66b7fbb464ef8f0
* ARM: spectre-v1: add array_index_mask_nospec() implementationRussell King2019-05-031-0/+19
| | | | | | | | | | | Add an implementation of the array_index_mask_nospec() function for mitigating Spectre variant 1 throughout the kernel. Change-Id: I66d16e24b4725df0bf70f53c91a34be9f26fba98 Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Acked-by: Mark Rutland <mark.rutland@arm.com> Boot-tested-by: Tony Lindgren <tony@atomide.com> Reviewed-by: Tony Lindgren <tony@atomide.com>
* ARM: spectre-v1: add speculation barrier (csdb) macrosRussell King2019-05-032-0/+21
| | | | | | | | | | Add assembly and C macros for the new CSDB instruction. Change-Id: Iff3490a0ebc290edf22128eba9e367dc5134fb3e Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Acked-by: Mark Rutland <mark.rutland@arm.com> Boot-tested-by: Tony Lindgren <tony@atomide.com> Reviewed-by: Tony Lindgren <tony@atomide.com>
* ARM: 8584/1: floppy: avoid gcc-6 warningArnd Bergmann2018-11-301-1/+1
| | | | | | | | | | | | | | | | | | | | | | | commit dd665be0e243873343a28e18f9f345927b658daf upstream. gcc-6.0 warns about comparisons between two identical expressions, which is what we get in the floppy driver when writing to the FD_DOR register: drivers/block/floppy.c: In function 'set_dor': drivers/block/floppy.c:810:44: error: self-comparison always evaluates to true [-Werror=tautological-compare] fd_outb(newdor, FD_DOR); It would be nice to use a static inline function instead of the macro, to avoid the warning, but we cannot do that because the FD_DOR definition is incomplete at this point. Adding a cast to (u32) is a harmless way to shut up the warning, just not very nice. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* ARM: 8158/1: LLVMLinux: use static inline in ARM ftrace.hBehan Webster2018-11-291-1/+1
| | | | | | | | | | | | | With compilers which follow the C99 standard (like modern versions of gcc and clang), "extern inline" does the wrong thing (emits code for an externally linkable version of the inline function). In this case using static inline and removing the NULL version of return_address in return_address.c does the right thing. Signed-off-by: Behan Webster <behanw@converseincode.com> Reviewed-by: Mark Charlebois <charlebm@gmail.com> Acked-by: Steven Rostedt <rostedt@goodmis.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: fix put_user() for gcc-8Arnd Bergmann2018-11-291-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | Building kernels before linux-4.7 with gcc-8 results in many build failures when gcc triggers a check that was meant to catch broken compilers: /tmp/ccCGMQmS.s:648: Error: .err encountered According to the discussion in the gcc bugzilla, a local "register asm()" variable is still supposed to be the correct way to force an inline assembly to use a particular register, but marking it 'const' lets the compiler do optimizations that break that, i.e the compiler is free to treat the variable as either 'const' or 'register' in that case. Upstream commit 9f73bd8bb445 ("ARM: uaccess: remove put_user() code duplication") fixed this problem in linux-4.8 as part of a larger change, but seems a little too big to be backported to 4.4. Let's take the simplest fix and change only the one broken line in the same way as newer kernels. Suggested-by: Bernd Edlinger <bernd.edlinger@hotmail.de> Link: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=85745 Link: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=86673 Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* ARM: 8634/1: hw_breakpoint: blacklist Scorpion CPUsMark Rutland2017-07-041-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | commit ddc37832a1349f474c4532de381498020ed71d31 upstream. On APQ8060, the kernel crashes in arch_hw_breakpoint_init, taking an undefined instruction trap within write_wb_reg. This is because Scorpion CPUs erroneously appear to set DBGPRSR.SPD when WFI is issued, even if the core is not powered down. When DBGPRSR.SPD is set, breakpoint and watchpoint registers are treated as undefined. It's possible to trigger similar crashes later on from userspace, by requesting the kernel to install a breakpoint or watchpoint, as we can go idle at any point between the reset of the debug registers and their later use. This has always been the case. Given that this has always been broken, no-one has complained until now, and there is no clear workaround, disable hardware breakpoints and watchpoints on Scorpion to avoid these issues. Signed-off-by: Mark Rutland <mark.rutland@arm.com> Reported-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Acked-by: Will Deacon <will.deacon@arm.com> Cc: Russell King <linux@armlinux.org.uk> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Willy Tarreau <w@1wt.eu>
* UPSTREAM: arm: perf: Fix callchain parse error with kernel tracepoint eventsHou Pengyang2017-05-241-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For ARM, when tracing with tracepoint events, the IP and cpsr are set to 0, preventing the perf code parsing the callchain and resolving the symbols correctly. ./perf record -e sched:sched_switch -g --call-graph dwarf ls [ perf record: Captured and wrote 0.006 MB perf.data ] ./perf report -f Samples: 5 of event 'sched:sched_switch', Event count (approx.): 5 Children Self Command Shared Object Symbol 100.00% 100.00% ls [unknown] [.] 00000000 The fix is to implement perf_arch_fetch_caller_regs for ARM, which fills several necessary registers used for callchain unwinding, including pc,sp, fp and cpsr. With this patch, callchain can be parsed correctly as : ..... - 100.00% 100.00% ls [kernel.kallsyms] [k] __sched_text_start + __sched_text_start + 20.00% 0.00% ls libc-2.18.so [.] _dl_addr + 20.00% 0.00% ls libc-2.18.so [.] write ..... Jean Pihet found this in ARM and come up with a patch: http://thread.gmane.org/gmane.linux.kernel/1734283/focus=1734280 This patch rewrite Jean's patch in C. Signed-off-by: Hou Pengyang <houpengyang@huawei.com> Signed-off-by: Will Deacon <will.deacon@arm.com> (cherry picked from commit b3eac0265bf6258f08dcd4ac7fa7f87cc050defc) Bug: 29520177 Signed-off-by: Mohan Srinivasan <srmohan@google.com> Change-Id: I0a5f24d6a16ff828674a1bb72e7d96e63d211492
* UPSTREAM: ARM: 8170/1: Add global named register current_stack_pointer for ARMBehan Webster2017-05-241-0/+5
| | | | | | | | | | | | | | | | Define a global named register for current_stack_pointer. The use of this new variable guarantees that both gcc and clang can access this register in C code. Signed-off-by: Behan Webster <behanw@converseincode.com> Reviewed-by: Jan-Simon Möller <dl9pf@gmx.de> Reviewed-by: Mark Charlebois <charlebm@gmail.com> Acked-by: Will Deacon <will.deacon@arm.com> Acked-by: Nicolas Pitre <nico@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> (cherry picked from commit 0abc08baf2ddf61a37d375a9fb832be612f9c5a5) Bug: 29520177 Signed-off-by: Mohan Srinivasan <srmohan@google.com> Change-Id: I8c7b3e2f92845ad20b6c5341ac9eb4ff86242604
* locking/mcs: Allow architecture specific asm files to be used for contended caseTim Chen2017-05-031-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch allows each architecture to add its specific assembly optimized arch_mcs_spin_lock_contended and arch_mcs_spinlock_uncontended for MCS lock and unlock functions. Signed-off-by: Tim Chen <tim.c.chen@linux.intel.com> Cc: Scott J Norton <scott.norton@hp.com> Cc: Raghavendra K T <raghavendra.kt@linux.vnet.ibm.com> Cc: AswinChandramouleeswaran <aswin@hp.com> Cc: George Spelvin <linux@horizon.com> Cc: Rik vanRiel <riel@redhat.com> Cc: Andrea Arcangeli <aarcange@redhat.com> Cc: MichelLespinasse <walken@google.com> Cc: Peter Hurley <peter@hurleysoftware.com> Cc: Andi Kleen <andi@firstfloor.org> Cc: Alex Shi <alex.shi@linaro.org> Cc: Dave Hansen <dave.hansen@intel.com> Cc: Tim Chen <tim.c.chen@linux.intel.com> Cc: Arnd Bergmann <arnd@arndb.de> Cc: "Figo.zhang" <figo1802@gmail.com> Cc: "Paul E.McKenney" <paulmck@linux.vnet.ibm.com> Cc: "H. Peter Anvin" <hpa@zytor.com> Cc: Davidlohr Bueso <davidlohr.bueso@hp.com> Cc: Waiman Long <waiman.long@hp.com> Cc: Ingo Molnar <mingo@elte.hu> Cc: Will Deacon <will.deacon@arm.com> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Matthew R Wilcox <matthew.r.wilcox@intel.com> Signed-off-by: Peter Zijlstra <peterz@infradead.org> Link: http://lkml.kernel.org/r/1390347382.3138.67.camel@schen9-DESK Signed-off-by: Ingo Molnar <mingo@kernel.org> Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git Git-commit: ddf1d169c0a489d498c1799a7043904a43b0c159 [joonwoop@codeaurora.org: Resolve merge conflicts; we don't have changes for arch other than ARM/ARM64] Signed-off-by: Joonwoo Park <joonwoop@codeaurora.org>
* Get rid of __cpuinitMoyster2017-04-111-1/+1
| | | | | | | | | | | | | | | | | | | | | This commit is the result of find . -name '*.c' | xargs sed -i 's/ __cpuinit / /g' find . -name '*.c' | xargs sed -i 's/ __cpuexit / /g' find . -name '*.c' | xargs sed -i 's/ __cpuinitdata / /g' find . -name '*.c' | xargs sed -i 's/ __cpuinit$//g' find ./arch/ -name '*.h' | xargs sed -i 's/ __cpuinit//g' find . -name '*.c' | xargs sed -i 's/^__cpuinit //g' find . -name '*.c' | xargs sed -i 's/^__cpuinitdata //g' find . -name '*.c' | xargs sed -i 's/\*__cpuinit /\*/g' find . -name '*.c' | xargs sed -i 's/ __cpuinitconst / /g' find . -name '*.h' | xargs sed -i 's/ __cpuinit / /g' find . -name '*.h' | xargs sed -i 's/ __cpuinitdata / /g' git add . git reset include/linux/init.h git checkout -- include/linux/init.h based off : https://github.com/jollaman999/jolla-kernel_bullhead/commit/bc15db84a622eed7d61d3ece579b577154d0ec29
* Optimize ARM memset and memzero functionsHarm Hanemaaijer2017-04-111-0/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ARM memset and memzero functions are optimized with lower overhead for small requests, generation of more 16-bit Thumb2 instructions when compiled in Thumb2 mode, and configurable destination alignment before the main block-copying loop. The new compile-time constant MEMSET_WRITE_ALIGN_BYTES is introduced in assembler.h, to augment the CALGN macro that previously regulated 32-byte write alignment but was only used on the Feroceon platform. MEMSET_WRITE_ALIGN_BYTES can have values of 0 (no write alignment), 8, or 32. Apart from Feroceon, memset write alignment of 32 bytes appears to benefit the armv6 platform, while the armv7 platform seems benefit from alignment to 8 bytes for memset/memzero. The CALGN macro is renamed to MEMSET_CALGN for memset and memzero; the original CALGN macro is reserved for the memcpy family of functions (memcpy, copy_from_user, copy_to_user) currently implemented in copy_template.S, and the associated compile time constant WRITE_ALIGN_BYTES defines the write alignment for memcpy-related functions that will be utilized in subsequent contributions. Because the current CALGN implementation in copy_template.S only implements 32-byte write alignment and is broken on Thumb2, it is only enabled when WRITE_ALIGN_BYTES is equal to 32 and Thumb2 mode is not enabled. Finally, memset and memzero now include a directive to enable unified ARM assembler syntax. Signed-off-by: Harm Hanemaaijer <fgenfb@yahoo.com>
* Optimize copy_page for modern ARM platformsHarm Hanemaaijer2017-04-112-0/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | The existing implementation of copy_page for ARM appears to be optimized for older platforms. Benchmark testing in a sandbox environment shows suboptimal performance on modern platforms like armv6 and armv7, with speed-ups ranging from 10% (Cortex A8) to 80% (armv6 used in Raspberry Pi) being achievable. This commit optimizes copy_page and introduces the new compile-time constant PREFETCH_DISTANCE, defined in cache.h, which when multiplied by L1_CACHE_BYTES is equal to the offset used for prefetches performed with the PLD instruction. For platforms where L1_CACHE_BYTES is 32 (armv5 and armv6), copy_page processes 32 bytes at a time while doing one prefetch per iteration, while for armv7 (with L1_CACHE_BYTES equal to 64), 64 bytes are processed at at time with one prefetch per iteration. When no preload instruction is available (platforms earlier than armv5), no preload instructions are generated and 32 bytes are processed at at time. To facilitate specifying instructions for architectures with no preload instruction, the NO_PLD macro is added to assembler.h, augmenting the PLD macro. Signed-off-by: Harm Hanemaaijer <fgenfb@yahoo.com> Signed-off-by: RyTek <rytek1128@outlook.com>
* Rename ARM assembler push/pull macrosHarm Hanemaaijer2017-04-111-4/+4
| | | | | | | | | | | | | | | | | | The ARM assembler library functions use a macro called "push" that along with a macro called "pull" is used to shift bytes around in a word in an endian-independent way. However, the modern unified ARM assembler syntax also defines the instruction "push" to push data onto the stack, which has specific encodings in the Thumb2 instruction set. For prevent possible conflicts going forward, and to allow the use of the more transparent "push" instruction along with the modern unified assembler syntax, this patch renames all occurrences of the "push" macro to "pushbits", as well as renaming the macro argument, when also called "push", to "pushshift". For consistency, the macro called "pull" with its argument name "pull" are also renamed to "pullbits" and "pullshift", respectively. Signed-off-by: Harm Hanemaaijer <fgenfb@yahoo.com>
* ARM: rwsem: use asm-generic rwsem implementationWill Deacon2016-09-131-0/+1
| | | | | | | | | | asm-generic offers an atomic-add based rwsem implementation, which can avoid the need for heavier, spinlock-based synchronisation on the fast path. This patch makes use of the optimised implementation for ARM CPUs. Signed-off-by: Will Deacon <will.deacon@arm.com>
* ARM: optimize memset_io()/memcpy_fromio()/memcpy_toio()Russell King2016-09-131-0/+25
| | | | | | | | | If we are building for a LE platform, and we haven't overriden the MMIO ops, then we can optimize the mem*io operations using the standard string functions. Acked-by: Nicolas Pitre <nico@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* arm: asm: relaxed.h: defined relaxed.hSumit Singh2016-09-101-0/+20
| | | | | | | | | | | | | | | | | | | Defined a new header file relaxed.h, which uses generic definitions of some macros used by arm64 for improving power efficiency. bug 1440421 Change-Id: I654dcef609812e3bb54e6c892c1554f9cbb4bd3d Signed-off-by: Sumit Singh <sumsingh@nvidia.com> Reviewed-on: http://git-master/r/398766 (cherry picked from commit a96e59b1959f3ee216503b4f9df3cb75f7093ed6) Reviewed-on: http://git-master/r/422211 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Signed-off-by: franciscofranco <franciscofranco.1990@gmail.com>
* arm: atomic.h: defined relaxed atomic_readSumit Singh2016-09-101-0/+1
| | | | | | | | | | | | | | | Defining relaxed version of atomic read as cpu_relaxed_read_atomic. bug 1440421 Change-Id: I39303d72350985890c7eb5a1afc768c3f8064b47 Signed-off-by: Sumit Singh <sumsingh@nvidia.com> (cherry picked from commit 6c20e8c2aed05ad1a9d1b41cfdd875dc377db44c) Reviewed-on: http://git-master/r/415637 GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Signed-off-by: franciscofranco <franciscofranco.1990@gmail.com>
* 3.10.76 -> 3.10.77Jan Engelmohr2016-08-261-1/+1
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* 3.10.67 -> 3.10.68Jan Engelmohr2016-08-267-56/+82
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* first commitMeizu OpenSource2016-08-15245-0/+22951
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