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* ARM: dts: da850-evm: fix read access to SPI flashFabien Parent2017-07-041-0/+1
| | | | | | | | | | | | | | | | | | | | | | commit 43849785e1079f6606a31cb7fda92d1200849728 upstream. Read access to the SPI flash are broken on da850-evm, i.e. the data read is not what is actually programmed on the flash. According to the datasheet for the M25P64 part present on the da850-evm, if the SPI frequency is higher than 20MHz then the READ command is not usable anymore and only the FAST_READ command can be used to read data. This commit specifies in the DTS that we should use FAST_READ command instead of the READ command. Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Fabien Parent <fparent@baylibre.com> [nsekhar@ti.com: subject line adjustment] Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Jiri Slaby <jslaby@suse.cz> Signed-off-by: Olof Johansson <olof@lixom.net> Signed-off-by: Willy Tarreau <w@1wt.eu>
* ARM: dts: imx31: fix AVIC base addressVladimir Zapolskiy2017-06-171-2/+2
| | | | | | | | | | | | | | | commit af92305e567b7f4c9cf48b9e46c1f48ec9ffb1fb upstream. On i.MX31 AVIC interrupt controller base address is at 0x68000000. The problem was shadowed by the AVIC driver, which takes the correct base address from a SoC specific header file. Fixes: d2a37b3d91f4 ("ARM i.MX31: Add devicetree support") Signed-off-by: Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Willy Tarreau <w@1wt.eu>
* ARM: dts: imx31: move CCM device node to AIPS2 bus devicesVladimir Zapolskiy2017-06-171-7/+7
| | | | | | | | | | | | | commit 1f87aee6a2e55eda466a43ba6248a8b75eede153 upstream. i.MX31 Clock Control Module controller is found on AIPS2 bus, move it there from SPBA bus to avoid a conflict of device IO space mismatch. Fixes: ef0e4a606fb6 ("ARM: mx31: Replace clk_register_clkdev with clock DT lookup") Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Willy Tarreau <w@1wt.eu>
* ARM: dts: imx31: fix clock control module interrupts descriptionVladimir Zapolskiy2017-06-171-1/+1
| | | | | | | | | | | | | | commit 2e575cbc930901718cc18e084566ecbb9a4b5ebb upstream. The type of AVIC interrupt controller found on i.MX31 is one-cell, namely 31 for CCM DVFS and 53 for CCM, however for clock control module its interrupts are specified as 3-cells, fix it. Fixes: ef0e4a606fb6 ("ARM: mx31: Replace clk_register_clkdev with clock DT lookup") Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Willy Tarreau <w@1wt.eu>
* 3.10.79 -> 3.10.80Jan Engelmohr2016-08-261-1/+1
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* 3.10.78 -> 3.10.79Jan Engelmohr2016-08-264-1/+7
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* 3.10.77 -> 3.10.78Jan Engelmohr2016-08-261-2/+2
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* 3.10.66 -> 3.10.67Jan Engelmohr2016-08-261-4/+4
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* 3.10.65 -> 3.10.66Jan Engelmohr2016-08-261-1/+1
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* first commitMeizu OpenSource2016-08-15360-0/+74902