Setup project skeleton

1 files changed, 97 insertions, 0 deletions

diff --git a/src/drv/ps1/dma/include/drv/ps1/dma.h b/src/drv/ps1/dma/include/drv/ps1/dma.h
new file mode 100644
index 0000000..9538c3b
--- /dev/null
+++ b/src/drv/ps1/dma/include/drv/ps1/dma.h
@@ -0,0 +1,97 @@
+/*
+ * wnix, a Unix-like operating system for WebAssembly applications.
+ * Copyright (C) 2025  Xavier Del Campo Romero
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Affero General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Affero General Public License for more details.
+ *
+ * You should have received a copy of the GNU Affero General Public License
+ * along with this program.  If not, see <https://www.gnu.org/licenses/>.
+ */
+
+#ifndef DRV_PS1_DMA_H
+#define DRV_PS1_DMA_H
+
+#include <stdint.h>
+
+union dpcr
+{
+    struct
+    {
+        uint32_t mdecin_prio :3, mdecin_en :1, mdecout_prio :3, mdecout_en :1,
+            gpu_prio :3, gpu_en :1, cdrom_prio :3, cdrom_en :1, spu_prio :3,
+            spu_en :1, pio_prio :3, pio_en :1, otc_prio :3, otc_en :1, :4;
+    } bits;
+
+    uint32_t mask;
+};
+
+union madr
+{
+    struct
+    {
+        uint32_t addr :24, :8;
+    } bits;
+
+    uint32_t mask;
+};
+
+union bcr
+{
+    struct
+    {
+        uint16_t nwords, reserved;
+    } syncmode_0;
+
+    struct
+    {
+        uint16_t blocksz, nblocks;
+    } syncmode_1;
+
+    struct
+    {
+        uint32_t reserved;
+    } syncmode_2;
+
+    uint32_t mask;
+};
+
+enum
+{
+    CHCR_DIR_TO_RAM,
+    CHCR_DIR_FROM_RAM
+};
+
+enum
+{
+    CHCR_SYNC_MODE_ALL,
+    CHCR_SYNC_MODE_BLOCKS,
+    CHCR_SYNC_MODE_LINKED_LIST
+};
+
+union chcr
+{
+    struct
+    {
+        uint32_t dir :1, memstep :1, :6, chopping :1, sync_mode :2, :5,
+            chopping_dma_window_sz :3, :1, chopping_cpu_window_sz :3, :1,
+            start_busy :1, :3, start_trigger :1, :3;
+    } bits;
+
+    uint32_t mask;
+};
+
+#define DMA_BASE(dma, off) ((dma) * 0x10 + 0x1f801080 + (off))
+#define D2_MADR ((volatile union madr *)DMA_BASE(2, 0))
+#define D2_BCR ((volatile union bcr *)DMA_BASE(2, 4))
+#define D2_CHCR ((volatile union chcr *)DMA_BASE(2, 8))
+#define DPCR ((volatile union dpcr *)0x1f8010f0)
+
+#endif