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/*
* This definitions of the PIC12F752 MCU.
*
* This file is part of the GNU PIC library for SDCC, originally
* created by Molnar Karoly <molnarkaroly@users.sf.net> 2016.
*
* This file is generated automatically by the cinc2h.pl, 2016-04-13 17:23:04 UTC.
*
* SDCC is licensed under the GNU Public license (GPL) v2. Note that
* this license covers the code to the compiler and other executables,
* but explicitly does not cover any code or objects generated by sdcc.
*
* For pic device libraries and header files which are derived from
* Microchip header (.inc) and linker script (.lkr) files Microchip
* requires that "The header files should state that they are only to be
* used with authentic Microchip devices" which makes them incompatible
* with the GPL. Pic device libraries and header files are located at
* non-free/lib and non-free/include directories respectively.
* Sdcc should be run with the --use-non-free command line option in
* order to include non-free header files and libraries.
*
* See http://sdcc.sourceforge.net/ for the latest information on sdcc.
*/
#include <pic12f752.h>
//==============================================================================
__at(0x0000) __sfr INDF;
__at(0x0001) __sfr TMR0;
__at(0x0002) __sfr PCL;
__at(0x0003) __sfr STATUS;
__at(0x0003) volatile __STATUSbits_t STATUSbits;
__at(0x0004) __sfr FSR;
__at(0x0005) __sfr PORTA;
__at(0x0005) volatile __PORTAbits_t PORTAbits;
__at(0x0008) __sfr IOCAF;
__at(0x0008) volatile __IOCAFbits_t IOCAFbits;
__at(0x000A) __sfr PCLATH;
__at(0x000B) __sfr INTCON;
__at(0x000B) volatile __INTCONbits_t INTCONbits;
__at(0x000C) __sfr PIR1;
__at(0x000C) volatile __PIR1bits_t PIR1bits;
__at(0x000D) __sfr PIR2;
__at(0x000D) volatile __PIR2bits_t PIR2bits;
__at(0x000F) __sfr TMR1;
__at(0x000F) __sfr TMR1L;
__at(0x0010) __sfr TMR1H;
__at(0x0011) __sfr T1CON;
__at(0x0011) volatile __T1CONbits_t T1CONbits;
__at(0x0012) __sfr T1GCON;
__at(0x0012) volatile __T1GCONbits_t T1GCONbits;
__at(0x0013) __sfr CCPR1;
__at(0x0013) __sfr CCPR1L;
__at(0x0014) __sfr CCPR1H;
__at(0x0015) __sfr CCP1CON;
__at(0x0015) volatile __CCP1CONbits_t CCP1CONbits;
__at(0x001C) __sfr ADRES;
__at(0x001C) __sfr ADRESL;
__at(0x001D) __sfr ADRESH;
__at(0x001E) __sfr ADCON0;
__at(0x001E) volatile __ADCON0bits_t ADCON0bits;
__at(0x001F) __sfr ADCON1;
__at(0x001F) volatile __ADCON1bits_t ADCON1bits;
__at(0x0081) __sfr OPTION_REG;
__at(0x0081) volatile __OPTION_REGbits_t OPTION_REGbits;
__at(0x0085) __sfr TRISA;
__at(0x0085) volatile __TRISAbits_t TRISAbits;
__at(0x0088) __sfr IOCAP;
__at(0x0088) volatile __IOCAPbits_t IOCAPbits;
__at(0x008C) __sfr PIE1;
__at(0x008C) volatile __PIE1bits_t PIE1bits;
__at(0x008D) __sfr PIE2;
__at(0x008D) volatile __PIE2bits_t PIE2bits;
__at(0x008F) __sfr OSCCON;
__at(0x008F) volatile __OSCCONbits_t OSCCONbits;
__at(0x0090) __sfr FVRCON;
__at(0x0090) volatile __FVRCONbits_t FVRCONbits;
__at(0x0091) __sfr DACCON0;
__at(0x0091) volatile __DACCON0bits_t DACCON0bits;
__at(0x0092) __sfr DACCON1;
__at(0x0092) volatile __DACCON1bits_t DACCON1bits;
__at(0x009B) __sfr C2CON0;
__at(0x009B) volatile __C2CON0bits_t C2CON0bits;
__at(0x009B) __sfr CM2CON0;
__at(0x009B) volatile __CM2CON0bits_t CM2CON0bits;
__at(0x009C) __sfr C2CON1;
__at(0x009C) volatile __C2CON1bits_t C2CON1bits;
__at(0x009C) __sfr CM2CON1;
__at(0x009C) volatile __CM2CON1bits_t CM2CON1bits;
__at(0x009D) __sfr C1CON0;
__at(0x009D) volatile __C1CON0bits_t C1CON0bits;
__at(0x009D) __sfr CM1CON0;
__at(0x009D) volatile __CM1CON0bits_t CM1CON0bits;
__at(0x009E) __sfr C1CON1;
__at(0x009E) volatile __C1CON1bits_t C1CON1bits;
__at(0x009E) __sfr CM1CON1;
__at(0x009E) volatile __CM1CON1bits_t CM1CON1bits;
__at(0x009F) __sfr CMOUT;
__at(0x009F) volatile __CMOUTbits_t CMOUTbits;
__at(0x009F) __sfr MCOUT;
__at(0x009F) volatile __MCOUTbits_t MCOUTbits;
__at(0x0105) __sfr LATA;
__at(0x0105) volatile __LATAbits_t LATAbits;
__at(0x0108) __sfr IOCAN;
__at(0x0108) volatile __IOCANbits_t IOCANbits;
__at(0x010C) __sfr WPUA;
__at(0x010C) volatile __WPUAbits_t WPUAbits;
__at(0x010D) __sfr SLRCONA;
__at(0x010D) volatile __SLRCONAbits_t SLRCONAbits;
__at(0x010F) __sfr PCON;
__at(0x010F) volatile __PCONbits_t PCONbits;
__at(0x0110) __sfr TMR2;
__at(0x0111) __sfr PR2;
__at(0x0112) __sfr T2CON;
__at(0x0112) volatile __T2CONbits_t T2CONbits;
__at(0x0113) __sfr HLTMR1;
__at(0x0114) __sfr HLTPR1;
__at(0x0115) __sfr HLT1CON0;
__at(0x0115) volatile __HLT1CON0bits_t HLT1CON0bits;
__at(0x0116) __sfr HLT1CON1;
__at(0x0116) volatile __HLT1CON1bits_t HLT1CON1bits;
__at(0x0185) __sfr ANSELA;
__at(0x0185) volatile __ANSELAbits_t ANSELAbits;
__at(0x0188) __sfr APFCON;
__at(0x0188) volatile __APFCONbits_t APFCONbits;
__at(0x0189) __sfr OSCTUNE;
__at(0x0189) volatile __OSCTUNEbits_t OSCTUNEbits;
__at(0x018C) __sfr PMCON1;
__at(0x018C) volatile __PMCON1bits_t PMCON1bits;
__at(0x018D) __sfr PMCON2;
__at(0x018E) __sfr PMADR;
__at(0x018E) __sfr PMADRL;
__at(0x018F) __sfr PMADRH;
__at(0x0190) __sfr PMDAT;
__at(0x0190) __sfr PMDATL;
__at(0x0191) __sfr PMDATH;
__at(0x0192) __sfr COG1PH;
__at(0x0192) volatile __COG1PHbits_t COG1PHbits;
__at(0x0193) __sfr COG1BLK;
__at(0x0193) volatile __COG1BLKbits_t COG1BLKbits;
__at(0x0194) __sfr COG1DB;
__at(0x0194) volatile __COG1DBbits_t COG1DBbits;
__at(0x0195) __sfr COG1CON0;
__at(0x0195) volatile __COG1CON0bits_t COG1CON0bits;
__at(0x0196) __sfr COG1CON1;
__at(0x0196) volatile __COG1CON1bits_t COG1CON1bits;
__at(0x0197) __sfr COG1ASD;
__at(0x0197) volatile __COG1ASDbits_t COG1ASDbits;
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