diff options
Diffstat (limited to 'device/non-free/include/pic14/pic12f635.h')
| -rw-r--r-- | device/non-free/include/pic14/pic12f635.h | 1304 |
1 files changed, 1304 insertions, 0 deletions
diff --git a/device/non-free/include/pic14/pic12f635.h b/device/non-free/include/pic14/pic12f635.h new file mode 100644 index 0000000..41d6a96 --- /dev/null +++ b/device/non-free/include/pic14/pic12f635.h @@ -0,0 +1,1304 @@ +/* + * This declarations of the PIC12F635 MCU. + * + * This file is part of the GNU PIC library for SDCC, originally + * created by Molnar Karoly <molnarkaroly@users.sf.net> 2016. + * + * This file is generated automatically by the cinc2h.pl, 2016-04-13 17:23:04 UTC. + * + * SDCC is licensed under the GNU Public license (GPL) v2. Note that + * this license covers the code to the compiler and other executables, + * but explicitly does not cover any code or objects generated by sdcc. + * + * For pic device libraries and header files which are derived from + * Microchip header (.inc) and linker script (.lkr) files Microchip + * requires that "The header files should state that they are only to be + * used with authentic Microchip devices" which makes them incompatible + * with the GPL. Pic device libraries and header files are located at + * non-free/lib and non-free/include directories respectively. + * Sdcc should be run with the --use-non-free command line option in + * order to include non-free header files and libraries. + * + * See http://sdcc.sourceforge.net/ for the latest information on sdcc. + */ + +#ifndef __PIC12F635_H__ +#define __PIC12F635_H__ + +//============================================================================== +// +// Register Addresses +// +//============================================================================== + +#ifndef NO_ADDR_DEFINES + +#define INDF_ADDR 0x0000 +#define TMR0_ADDR 0x0001 +#define PCL_ADDR 0x0002 +#define STATUS_ADDR 0x0003 +#define FSR_ADDR 0x0004 +#define GPIO_ADDR 0x0005 +#define PORTA_ADDR 0x0005 +#define PCLATH_ADDR 0x000A +#define INTCON_ADDR 0x000B +#define PIR1_ADDR 0x000C +#define TMR1_ADDR 0x000E +#define TMR1L_ADDR 0x000E +#define TMR1H_ADDR 0x000F +#define T1CON_ADDR 0x0010 +#define WDTCON_ADDR 0x0018 +#define CMCON0_ADDR 0x0019 +#define CMCON1_ADDR 0x001A +#define OPTION_REG_ADDR 0x0081 +#define TRISA_ADDR 0x0085 +#define TRISIO_ADDR 0x0085 +#define PIE1_ADDR 0x008C +#define PCON_ADDR 0x008E +#define OSCCON_ADDR 0x008F +#define OSCTUNE_ADDR 0x0090 +#define LVDCON_ADDR 0x0094 +#define WPUDA_ADDR 0x0095 +#define IOCA_ADDR 0x0096 +#define WDA_ADDR 0x0097 +#define VRCON_ADDR 0x0099 +#define EEDAT_ADDR 0x009A +#define EEDATA_ADDR 0x009A +#define EEADR_ADDR 0x009B +#define EECON1_ADDR 0x009C +#define EECON2_ADDR 0x009D +#define CRCON_ADDR 0x0110 +#define CRDAT0_ADDR 0x0111 +#define CRDAT1_ADDR 0x0112 +#define CRDAT2_ADDR 0x0113 +#define CRDAT3_ADDR 0x0114 + +#endif // #ifndef NO_ADDR_DEFINES + +//============================================================================== +// +// Register Definitions +// +//============================================================================== + +extern __at(0x0000) __sfr INDF; +extern __at(0x0001) __sfr TMR0; +extern __at(0x0002) __sfr PCL; + +//============================================================================== +// STATUS Bits + +extern __at(0x0003) __sfr STATUS; + +typedef union + { + struct + { + unsigned C : 1; + unsigned DC : 1; + unsigned Z : 1; + unsigned NOT_PD : 1; + unsigned NOT_TO : 1; + unsigned RP0 : 1; + unsigned RP1 : 1; + unsigned IRP : 1; + }; + + struct + { + unsigned : 5; + unsigned RP : 2; + unsigned : 1; + }; + } __STATUSbits_t; + +extern __at(0x0003) volatile __STATUSbits_t STATUSbits; + +#define _C 0x01 +#define _DC 0x02 +#define _Z 0x04 +#define _NOT_PD 0x08 +#define _NOT_TO 0x10 +#define _RP0 0x20 +#define _RP1 0x40 +#define _IRP 0x80 + +//============================================================================== + +extern __at(0x0004) __sfr FSR; + +//============================================================================== +// GPIO Bits + +extern __at(0x0005) __sfr GPIO; + +typedef union + { + struct + { + unsigned GP0 : 1; + unsigned GP1 : 1; + unsigned GP2 : 1; + unsigned GP3 : 1; + unsigned GP4 : 1; + unsigned GP5 : 1; + unsigned : 1; + unsigned : 1; + }; + + struct + { + unsigned RA0 : 1; + unsigned RA1 : 1; + unsigned RA2 : 1; + unsigned RA3 : 1; + unsigned RA4 : 1; + unsigned RA5 : 1; + unsigned : 1; + unsigned : 1; + }; + + struct + { + unsigned RA : 6; + unsigned : 2; + }; + + struct + { + unsigned GP : 6; + unsigned : 2; + }; + } __GPIObits_t; + +extern __at(0x0005) volatile __GPIObits_t GPIObits; + +#define _GP0 0x01 +#define _RA0 0x01 +#define _GP1 0x02 +#define _RA1 0x02 +#define _GP2 0x04 +#define _RA2 0x04 +#define _GP3 0x08 +#define _RA3 0x08 +#define _GP4 0x10 +#define _RA4 0x10 +#define _GP5 0x20 +#define _RA5 0x20 + +//============================================================================== + + +//============================================================================== +// PORTA Bits + +extern __at(0x0005) __sfr PORTA; + +typedef union + { + struct + { + unsigned GP0 : 1; + unsigned GP1 : 1; + unsigned GP2 : 1; + unsigned GP3 : 1; + unsigned GP4 : 1; + unsigned GP5 : 1; + unsigned : 1; + unsigned : 1; + }; + + struct + { + unsigned RA0 : 1; + unsigned RA1 : 1; + unsigned RA2 : 1; + unsigned RA3 : 1; + unsigned RA4 : 1; + unsigned RA5 : 1; + unsigned : 1; + unsigned : 1; + }; + + struct + { + unsigned RA : 6; + unsigned : 2; + }; + + struct + { + unsigned GP : 6; + unsigned : 2; + }; + } __PORTAbits_t; + +extern __at(0x0005) volatile __PORTAbits_t PORTAbits; + +#define _PORTA_GP0 0x01 +#define _PORTA_RA0 0x01 +#define _PORTA_GP1 0x02 +#define _PORTA_RA1 0x02 +#define _PORTA_GP2 0x04 +#define _PORTA_RA2 0x04 +#define _PORTA_GP3 0x08 +#define _PORTA_RA3 0x08 +#define _PORTA_GP4 0x10 +#define _PORTA_RA4 0x10 +#define _PORTA_GP5 0x20 +#define _PORTA_RA5 0x20 + +//============================================================================== + +extern __at(0x000A) __sfr PCLATH; + +//============================================================================== +// INTCON Bits + +extern __at(0x000B) __sfr INTCON; + +typedef struct + { + unsigned RAIF : 1; + unsigned INTF : 1; + unsigned T0IF : 1; + unsigned RAIE : 1; + unsigned INTE : 1; + unsigned T0IE : 1; + unsigned PEIE : 1; + unsigned GIE : 1; + } __INTCONbits_t; + +extern __at(0x000B) volatile __INTCONbits_t INTCONbits; + +#define _RAIF 0x01 +#define _INTF 0x02 +#define _T0IF 0x04 +#define _RAIE 0x08 +#define _INTE 0x10 +#define _T0IE 0x20 +#define _PEIE 0x40 +#define _GIE 0x80 + +//============================================================================== + + +//============================================================================== +// PIR1 Bits + +extern __at(0x000C) __sfr PIR1; + +typedef struct + { + unsigned TMR1IF : 1; + unsigned : 1; + unsigned OSFIF : 1; + unsigned C1IF : 1; + unsigned : 1; + unsigned CRIF : 1; + unsigned LVDIF : 1; + unsigned EEIF : 1; + } __PIR1bits_t; + +extern __at(0x000C) volatile __PIR1bits_t PIR1bits; + +#define _TMR1IF 0x01 +#define _OSFIF 0x04 +#define _C1IF 0x08 +#define _CRIF 0x20 +#define _LVDIF 0x40 +#define _EEIF 0x80 + +//============================================================================== + +extern __at(0x000E) __sfr TMR1; +extern __at(0x000E) __sfr TMR1L; +extern __at(0x000F) __sfr TMR1H; + +//============================================================================== +// T1CON Bits + +extern __at(0x0010) __sfr T1CON; + +typedef union + { + struct + { + unsigned TMR1ON : 1; + unsigned TMR1CS : 1; + unsigned NOT_T1SYNC : 1; + unsigned T1OSCEN : 1; + unsigned T1CKPS0 : 1; + unsigned T1CKPS1 : 1; + unsigned TMR1GE : 1; + unsigned T1GINV : 1; + }; + + struct + { + unsigned : 4; + unsigned T1CKPS : 2; + unsigned : 2; + }; + } __T1CONbits_t; + +extern __at(0x0010) volatile __T1CONbits_t T1CONbits; + +#define _TMR1ON 0x01 +#define _TMR1CS 0x02 +#define _NOT_T1SYNC 0x04 +#define _T1OSCEN 0x08 +#define _T1CKPS0 0x10 +#define _T1CKPS1 0x20 +#define _TMR1GE 0x40 +#define _T1GINV 0x80 + +//============================================================================== + + +//============================================================================== +// WDTCON Bits + +extern __at(0x0018) __sfr WDTCON; + +typedef union + { + struct + { + unsigned SWDTEN : 1; + unsigned WDTPS0 : 1; + unsigned WDTPS1 : 1; + unsigned WDTPS2 : 1; + unsigned WDTPS3 : 1; + unsigned : 1; + unsigned : 1; + unsigned : 1; + }; + + struct + { + unsigned : 1; + unsigned WDTPS : 4; + unsigned : 3; + }; + } __WDTCONbits_t; + +extern __at(0x0018) volatile __WDTCONbits_t WDTCONbits; + +#define _SWDTEN 0x01 +#define _WDTPS0 0x02 +#define _WDTPS1 0x04 +#define _WDTPS2 0x08 +#define _WDTPS3 0x10 + +//============================================================================== + + +//============================================================================== +// CMCON0 Bits + +extern __at(0x0019) __sfr CMCON0; + +typedef union + { + struct + { + unsigned CM0 : 1; + unsigned CM1 : 1; + unsigned CM2 : 1; + unsigned CIS : 1; + unsigned CINV : 1; + unsigned : 1; + unsigned COUT : 1; + unsigned : 1; + }; + + struct + { + unsigned : 1; + unsigned : 1; + unsigned : 1; + unsigned : 1; + unsigned C1INV : 1; + unsigned : 1; + unsigned C1OUT : 1; + unsigned : 1; + }; + + struct + { + unsigned CM : 3; + unsigned : 5; + }; + } __CMCON0bits_t; + +extern __at(0x0019) volatile __CMCON0bits_t CMCON0bits; + +#define _CM0 0x01 +#define _CM1 0x02 +#define _CM2 0x04 +#define _CIS 0x08 +#define _CINV 0x10 +#define _C1INV 0x10 +#define _COUT 0x40 +#define _C1OUT 0x40 + +//============================================================================== + + +//============================================================================== +// CMCON1 Bits + +extern __at(0x001A) __sfr CMCON1; + +typedef union + { + struct + { + unsigned CMSYNC : 1; + unsigned T1GSS : 1; + unsigned : 1; + unsigned : 1; + unsigned : 1; + unsigned : 1; + unsigned : 1; + unsigned : 1; + }; + + struct + { + unsigned C1SYNC : 1; + unsigned : 1; + unsigned : 1; + unsigned : 1; + unsigned : 1; + unsigned : 1; + unsigned : 1; + unsigned : 1; + }; + } __CMCON1bits_t; + +extern __at(0x001A) volatile __CMCON1bits_t CMCON1bits; + +#define _CMSYNC 0x01 +#define _C1SYNC 0x01 +#define _T1GSS 0x02 + +//============================================================================== + + +//============================================================================== +// OPTION_REG Bits + +extern __at(0x0081) __sfr OPTION_REG; + +typedef union + { + struct + { + unsigned PS0 : 1; + unsigned PS1 : 1; + unsigned PS2 : 1; + unsigned PSA : 1; + unsigned T0SE : 1; + unsigned T0CS : 1; + unsigned INTEDG : 1; + unsigned NOT_RAPU : 1; + }; + + struct + { + unsigned PS : 3; + unsigned : 5; + }; + } __OPTION_REGbits_t; + +extern __at(0x0081) volatile __OPTION_REGbits_t OPTION_REGbits; + +#define _PS0 0x01 +#define _PS1 0x02 +#define _PS2 0x04 +#define _PSA 0x08 +#define _T0SE 0x10 +#define _T0CS 0x20 +#define _INTEDG 0x40 +#define _NOT_RAPU 0x80 + +//============================================================================== + + +//============================================================================== +// TRISA Bits + +extern __at(0x0085) __sfr TRISA; + +typedef union + { + struct + { + unsigned TRISIO0 : 1; + unsigned TRISIO1 : 1; + unsigned TRISIO2 : 1; + unsigned TRISIO3 : 1; + unsigned TRISIO4 : 1; + unsigned TRISIO5 : 1; + unsigned : 1; + unsigned : 1; + }; + + struct + { + unsigned TRISA0 : 1; + unsigned TRISA1 : 1; + unsigned TRISA2 : 1; + unsigned TRISA3 : 1; + unsigned TRISA4 : 1; + unsigned TRISA5 : 1; + unsigned : 1; + unsigned : 1; + }; + + struct + { + unsigned TRISA : 6; + unsigned : 2; + }; + + struct + { + unsigned TRISIO : 6; + unsigned : 2; + }; + } __TRISAbits_t; + +extern __at(0x0085) volatile __TRISAbits_t TRISAbits; + +#define _TRISIO0 0x01 +#define _TRISA0 0x01 +#define _TRISIO1 0x02 +#define _TRISA1 0x02 +#define _TRISIO2 0x04 +#define _TRISA2 0x04 +#define _TRISIO3 0x08 +#define _TRISA3 0x08 +#define _TRISIO4 0x10 +#define _TRISA4 0x10 +#define _TRISIO5 0x20 +#define _TRISA5 0x20 + +//============================================================================== + + +//============================================================================== +// TRISIO Bits + +extern __at(0x0085) __sfr TRISIO; + +typedef union + { + struct + { + unsigned TRISIO0 : 1; + unsigned TRISIO1 : 1; + unsigned TRISIO2 : 1; + unsigned TRISIO3 : 1; + unsigned TRISIO4 : 1; + unsigned TRISIO5 : 1; + unsigned : 1; + unsigned : 1; + }; + + struct + { + unsigned TRISA0 : 1; + unsigned TRISA1 : 1; + unsigned TRISA2 : 1; + unsigned TRISA3 : 1; + unsigned TRISA4 : 1; + unsigned TRISA5 : 1; + unsigned : 1; + unsigned : 1; + }; + + struct + { + unsigned TRISIO : 6; + unsigned : 2; + }; + + struct + { + unsigned TRISA : 6; + unsigned : 2; + }; + } __TRISIObits_t; + +extern __at(0x0085) volatile __TRISIObits_t TRISIObits; + +#define _TRISIO_TRISIO0 0x01 +#define _TRISIO_TRISA0 0x01 +#define _TRISIO_TRISIO1 0x02 +#define _TRISIO_TRISA1 0x02 +#define _TRISIO_TRISIO2 0x04 +#define _TRISIO_TRISA2 0x04 +#define _TRISIO_TRISIO3 0x08 +#define _TRISIO_TRISA3 0x08 +#define _TRISIO_TRISIO4 0x10 +#define _TRISIO_TRISA4 0x10 +#define _TRISIO_TRISIO5 0x20 +#define _TRISIO_TRISA5 0x20 + +//============================================================================== + + +//============================================================================== +// PIE1 Bits + +extern __at(0x008C) __sfr PIE1; + +typedef struct + { + unsigned TMR1IE : 1; + unsigned : 1; + unsigned OSFIE : 1; + unsigned C1IE : 1; + unsigned : 1; + unsigned CRIE : 1; + unsigned LVDIE : 1; + unsigned EEIE : 1; + } __PIE1bits_t; + +extern __at(0x008C) volatile __PIE1bits_t PIE1bits; + +#define _TMR1IE 0x01 +#define _OSFIE 0x04 +#define _C1IE 0x08 +#define _CRIE 0x20 +#define _LVDIE 0x40 +#define _EEIE 0x80 + +//============================================================================== + + +//============================================================================== +// PCON Bits + +extern __at(0x008E) __sfr PCON; + +typedef union + { + struct + { + unsigned NOT_BOR : 1; + unsigned NOT_POR : 1; + unsigned : 1; + unsigned NOT_WUR : 1; + unsigned SBOREN : 1; + unsigned ULPWUE : 1; + unsigned : 1; + unsigned : 1; + }; + + struct + { + unsigned NOT_BOD : 1; + unsigned : 1; + unsigned : 1; + unsigned : 1; + unsigned SBODEN : 1; + unsigned : 1; + unsigned : 1; + unsigned : 1; + }; + } __PCONbits_t; + +extern __at(0x008E) volatile __PCONbits_t PCONbits; + +#define _NOT_BOR 0x01 +#define _NOT_BOD 0x01 +#define _NOT_POR 0x02 +#define _NOT_WUR 0x08 +#define _SBOREN 0x10 +#define _SBODEN 0x10 +#define _ULPWUE 0x20 + +//============================================================================== + + +//============================================================================== +// OSCCON Bits + +extern __at(0x008F) __sfr OSCCON; + +typedef union + { + struct + { + unsigned SCS : 1; + unsigned LTS : 1; + unsigned HTS : 1; + unsigned OSTS : 1; + unsigned IRCF0 : 1; + unsigned IRCF1 : 1; + unsigned IRCF2 : 1; + unsigned : 1; + }; + + struct + { + unsigned : 4; + unsigned IRCF : 3; + unsigned : 1; + }; + } __OSCCONbits_t; + +extern __at(0x008F) volatile __OSCCONbits_t OSCCONbits; + +#define _SCS 0x01 +#define _LTS 0x02 +#define _HTS 0x04 +#define _OSTS 0x08 +#define _IRCF0 0x10 +#define _IRCF1 0x20 +#define _IRCF2 0x40 + +//============================================================================== + + +//============================================================================== +// OSCTUNE Bits + +extern __at(0x0090) __sfr OSCTUNE; + +typedef union + { + struct + { + unsigned TUN0 : 1; + unsigned TUN1 : 1; + unsigned TUN2 : 1; + unsigned TUN3 : 1; + unsigned TUN4 : 1; + unsigned : 1; + unsigned : 1; + unsigned : 1; + }; + + struct + { + unsigned TUN : 5; + unsigned : 3; + }; + } __OSCTUNEbits_t; + +extern __at(0x0090) volatile __OSCTUNEbits_t OSCTUNEbits; + +#define _TUN0 0x01 +#define _TUN1 0x02 +#define _TUN2 0x04 +#define _TUN3 0x08 +#define _TUN4 0x10 + +//============================================================================== + + +//============================================================================== +// LVDCON Bits + +extern __at(0x0094) __sfr LVDCON; + +typedef union + { + struct + { + unsigned LVDL0 : 1; + unsigned LVDL1 : 1; + unsigned LVDL2 : 1; + unsigned : 1; + unsigned LVDEN : 1; + unsigned IRVST : 1; + unsigned : 1; + unsigned : 1; + }; + + struct + { + unsigned : 1; + unsigned : 1; + unsigned : 1; + unsigned : 1; + unsigned PLVDEN : 1; + unsigned : 1; + unsigned : 1; + unsigned : 1; + }; + + struct + { + unsigned LVDL : 3; + unsigned : 5; + }; + } __LVDCONbits_t; + +extern __at(0x0094) volatile __LVDCONbits_t LVDCONbits; + +#define _LVDL0 0x01 +#define _LVDL1 0x02 +#define _LVDL2 0x04 +#define _LVDEN 0x10 +#define _PLVDEN 0x10 +#define _IRVST 0x20 + +//============================================================================== + + +//============================================================================== +// WPUDA Bits + +extern __at(0x0095) __sfr WPUDA; + +typedef struct + { + unsigned WPUDA0 : 1; + unsigned WPUDA1 : 1; + unsigned WPUDA2 : 1; + unsigned : 1; + unsigned WPUDA4 : 1; + unsigned WPUDA5 : 1; + unsigned : 1; + unsigned : 1; + } __WPUDAbits_t; + +extern __at(0x0095) volatile __WPUDAbits_t WPUDAbits; + +#define _WPUDA0 0x01 +#define _WPUDA1 0x02 +#define _WPUDA2 0x04 +#define _WPUDA4 0x10 +#define _WPUDA5 0x20 + +//============================================================================== + + +//============================================================================== +// IOCA Bits + +extern __at(0x0096) __sfr IOCA; + +typedef union + { + struct + { + unsigned IOCA0 : 1; + unsigned IOCA1 : 1; + unsigned IOCA2 : 1; + unsigned IOCA3 : 1; + unsigned IOCA4 : 1; + unsigned IOCA5 : 1; + unsigned : 1; + unsigned : 1; + }; + + struct + { + unsigned IOCA : 6; + unsigned : 2; + }; + } __IOCAbits_t; + +extern __at(0x0096) volatile __IOCAbits_t IOCAbits; + +#define _IOCA0 0x01 +#define _IOCA1 0x02 +#define _IOCA2 0x04 +#define _IOCA3 0x08 +#define _IOCA4 0x10 +#define _IOCA5 0x20 + +//============================================================================== + + +//============================================================================== +// WDA Bits + +extern __at(0x0097) __sfr WDA; + +typedef struct + { + unsigned WDA0 : 1; + unsigned WDA1 : 1; + unsigned WDA2 : 1; + unsigned : 1; + unsigned WDA4 : 1; + unsigned WDA5 : 1; + unsigned : 1; + unsigned : 1; + } __WDAbits_t; + +extern __at(0x0097) volatile __WDAbits_t WDAbits; + +#define _WDA0 0x01 +#define _WDA1 0x02 +#define _WDA2 0x04 +#define _WDA4 0x10 +#define _WDA5 0x20 + +//============================================================================== + + +//============================================================================== +// VRCON Bits + +extern __at(0x0099) __sfr VRCON; + +typedef union + { + struct + { + unsigned VR0 : 1; + unsigned VR1 : 1; + unsigned VR2 : 1; + unsigned VR3 : 1; + unsigned : 1; + unsigned VRR : 1; + unsigned : 1; + unsigned VREN : 1; + }; + + struct + { + unsigned VR : 4; + unsigned : 4; + }; + } __VRCONbits_t; + +extern __at(0x0099) volatile __VRCONbits_t VRCONbits; + +#define _VR0 0x01 +#define _VR1 0x02 +#define _VR2 0x04 +#define _VR3 0x08 +#define _VRR 0x20 +#define _VREN 0x80 + +//============================================================================== + +extern __at(0x009A) __sfr EEDAT; +extern __at(0x009A) __sfr EEDATA; +extern __at(0x009B) __sfr EEADR; + +//============================================================================== +// EECON1 Bits + +extern __at(0x009C) __sfr EECON1; + +typedef struct + { + unsigned RD : 1; + unsigned WR : 1; + unsigned WREN : 1; + unsigned WRERR : 1; + unsigned : 1; + unsigned : 1; + unsigned : 1; + unsigned : 1; + } __EECON1bits_t; + +extern __at(0x009C) volatile __EECON1bits_t EECON1bits; + +#define _RD 0x01 +#define _WR 0x02 +#define _WREN 0x04 +#define _WRERR 0x08 + +//============================================================================== + +extern __at(0x009D) __sfr EECON2; + +//============================================================================== +// CRCON Bits + +extern __at(0x0110) __sfr CRCON; + +typedef union + { + struct + { + unsigned CRREG0 : 1; + unsigned CRREG1 : 1; + unsigned : 1; + unsigned : 1; + unsigned : 1; + unsigned : 1; + unsigned ENC_NOT_DEC : 1; + unsigned GO_NOT_DONE : 1; + }; + + struct + { + unsigned : 1; + unsigned : 1; + unsigned : 1; + unsigned : 1; + unsigned : 1; + unsigned : 1; + unsigned ENC_DEC : 1; + unsigned GO : 1; + }; + + struct + { + unsigned CRREG : 2; + unsigned : 6; + }; + } __CRCONbits_t; + +extern __at(0x0110) volatile __CRCONbits_t CRCONbits; + +#define _CRREG0 0x01 +#define _CRREG1 0x02 +#define _ENC_NOT_DEC 0x40 +#define _ENC_DEC 0x40 +#define _GO_NOT_DONE 0x80 +#define _GO 0x80 + +//============================================================================== + +extern __at(0x0111) __sfr CRDAT0; +extern __at(0x0112) __sfr CRDAT1; +extern __at(0x0113) __sfr CRDAT2; +extern __at(0x0114) __sfr CRDAT3; + +//============================================================================== +// +// Configuration Bits +// +//============================================================================== + +#define _CONFIG 0x2007 + +//----------------------------- CONFIG Options ------------------------------- + +#define _FOSC_LP 0x3FF8 // LP oscillator: Low-power crystal on RA5/T1CKI/OSC1/CLKIN and RA4/T1G/OSC2/CLKOUT. +#define _LP_OSC 0x3FF8 // LP oscillator: Low-power crystal on RA5/T1CKI/OSC1/CLKIN and RA4/T1G/OSC2/CLKOUT. +#define _FOSC_XT 0x3FF9 // XT oscillator: Crystal/resonator on RA5/T1CKI/OSC1/CLKIN and RA4/T1G/OSC2/CLKOUT. +#define _XT_OSC 0x3FF9 // XT oscillator: Crystal/resonator on RA5/T1CKI/OSC1/CLKIN and RA4/T1G/OSC2/CLKOUT. +#define _FOSC_HS 0x3FFA // HS oscillator: High-speed crystal/resonator on RA5/T1CKI/OSC1/CLKIN and RA4/T1G/OSC2/CLKOUT. +#define _HS_OSC 0x3FFA // HS oscillator: High-speed crystal/resonator on RA5/T1CKI/OSC1/CLKIN and RA4/T1G/OSC2/CLKOUT. +#define _FOSC_EC 0x3FFB // EC: I/O function on RA4/T1G/OSC2/CLKOUT, CLKIN on RA5/T1CKI/OSC1/CLKIN. +#define _EC_OSC 0x3FFB // EC: I/O function on RA4/T1G/OSC2/CLKOUT, CLKIN on RA5/T1CKI/OSC1/CLKIN. +#define _FOSC_INTOSCIO 0x3FFC // INTOSCIO oscillator: I/O function on RA4/T1G/OSC2/CLKOUT pin, I/O function on RA5/T1CKI/OSC1/CLKIN. +#define _INTRC_OSC_NOCLKOUT 0x3FFC // INTOSCIO oscillator: I/O function on RA4/T1G/OSC2/CLKOUT pin, I/O function on RA5/T1CKI/OSC1/CLKIN. +#define _FOSC_INTOSCCLK 0x3FFD // INTOSC oscillator: CLKOUT function on RA4/T1G/OSC2/CLKOUT pin, I/O function on RA5/T1CKI/OSC1/CLKIN. +#define _INTRC_OSC_CLKOUT 0x3FFD // INTOSC oscillator: CLKOUT function on RA4/T1G/OSC2/CLKOUT pin, I/O function on RA5/T1CKI/OSC1/CLKIN. +#define _FOSC_EXTRCIO 0x3FFE // RCIO oscillator: I/O function on RA4/T1G/OSC2/CLKOUT pin, RC on RA5/T1CKI/OSC1/CLKIN. +#define _EXTRC_OSC_NOCLKOUT 0x3FFE // RCIO oscillator: I/O function on RA4/T1G/OSC2/CLKOUT pin, RC on RA5/T1CKI/OSC1/CLKIN. +#define _FOSC_EXTRCCLK 0x3FFF // RC oscillator: CLKOUT function on RA4/T1G/OSC2/CLKOUT pin, RC on RA5/T1CKI/OSC1/CLKIN. +#define _EXTRC_OSC_CLKOUT 0x3FFF // RC oscillator: CLKOUT function on RA4/T1G/OSC2/CLKOUT pin, RC on RA5/T1CKI/OSC1/CLKIN. +#define _WDTE_OFF 0x3FF7 // WDT disabled and can be enabled by SWDTEN bit of the WDTCON register. +#define _WDT_OFF 0x3FF7 // WDT disabled and can be enabled by SWDTEN bit of the WDTCON register. +#define _WDTE_ON 0x3FFF // WDT enabled. +#define _WDT_ON 0x3FFF // WDT enabled. +#define _PWRTE_ON 0x3FEF // PWRT enabled. +#define _PWRTE_OFF 0x3FFF // PWRT disabled. +#define _MCLRE_OFF 0x3FDF // MCLR pin function is alternate function, MCLR function is internally disabled. +#define _MCLRE_ON 0x3FFF // MCLR pin is MCLR function and weak internal pull-up is enabled. +#define _CP_ON 0x3FBF // Program memory is external read and write-protected. +#define _CP_OFF 0x3FFF // Program memory is not code protected. +#define _CPD_ON 0x3F7F // Data memory is external read protected. +#define _CPD_OFF 0x3FFF // Data memory is not code protected. +#define _BOREN_OFF 0x3CFF // BOD and SBODEN disabled. +#define _BOD_OFF 0x3CFF // BOD and SBODEN disabled. +#define _BOREN_SBODEN 0x3DFF // SBODEN controls BOD function. +#define _BOD_SBODEN 0x3DFF // SBODEN controls BOD function. +#define _BOREN_NSLEEP 0x3EFF // BOD enabled while running and disabled in Sleep. SBODEN bit disabled. +#define _BOD_NSLEEP 0x3EFF // BOD enabled while running and disabled in Sleep. SBODEN bit disabled. +#define _BOREN_ON 0x3FFF // BOD enabled and SBOdEN bit disabled. +#define _BOD_ON 0x3FFF // BOD enabled and SBOdEN bit disabled. +#define _IESO_OFF 0x3BFF // Internal External Switchover mode disabled. +#define _IESO_ON 0x3FFF // Internal External Switchover mode enabled. +#define _FCMEN_OFF 0x37FF // Fail-Safe Clock Monitor disabled. +#define _FCMEN_ON 0x3FFF // Fail-Safe Clock Monitor enabled. +#define _WURE_ON 0x2FFF // Wake-up and Reset enabled. +#define _WUREN_ON 0x2FFF // Wake-up and Reset enabled. +#define _WURE_OFF 0x3FFF // Standard wake-up and continue enabled. +#define _WUREN_OFF 0x3FFF // Standard wake-up and continue enabled. + +//============================================================================== + +#define _DEVID1 0x2006 + +#define _IDLOC0 0x2000 +#define _IDLOC1 0x2001 +#define _IDLOC2 0x2002 +#define _IDLOC3 0x2003 + +//============================================================================== + +#ifndef NO_BIT_DEFINES + +#define CM0 CMCON0bits.CM0 // bit 0 +#define CM1 CMCON0bits.CM1 // bit 1 +#define CM2 CMCON0bits.CM2 // bit 2 +#define CIS CMCON0bits.CIS // bit 3 +#define CINV CMCON0bits.CINV // bit 4, shadows bit in CMCON0bits +#define C1INV CMCON0bits.C1INV // bit 4, shadows bit in CMCON0bits +#define COUT CMCON0bits.COUT // bit 6, shadows bit in CMCON0bits +#define C1OUT CMCON0bits.C1OUT // bit 6, shadows bit in CMCON0bits + +#define CMSYNC CMCON1bits.CMSYNC // bit 0, shadows bit in CMCON1bits +#define C1SYNC CMCON1bits.C1SYNC // bit 0, shadows bit in CMCON1bits +#define T1GSS CMCON1bits.T1GSS // bit 1 + +#define CRREG0 CRCONbits.CRREG0 // bit 0 +#define CRREG1 CRCONbits.CRREG1 // bit 1 +#define ENC_NOT_DEC CRCONbits.ENC_NOT_DEC // bit 6, shadows bit in CRCONbits +#define ENC_DEC CRCONbits.ENC_DEC // bit 6, shadows bit in CRCONbits +#define GO_NOT_DONE CRCONbits.GO_NOT_DONE // bit 7, shadows bit in CRCONbits +#define GO CRCONbits.GO // bit 7, shadows bit in CRCONbits + +#define RD EECON1bits.RD // bit 0 +#define WR EECON1bits.WR // bit 1 +#define WREN EECON1bits.WREN // bit 2 +#define WRERR EECON1bits.WRERR // bit 3 + +#define GP0 GPIObits.GP0 // bit 0, shadows bit in GPIObits +#define RA0 GPIObits.RA0 // bit 0, shadows bit in GPIObits +#define GP1 GPIObits.GP1 // bit 1, shadows bit in GPIObits +#define RA1 GPIObits.RA1 // bit 1, shadows bit in GPIObits +#define GP2 GPIObits.GP2 // bit 2, shadows bit in GPIObits +#define RA2 GPIObits.RA2 // bit 2, shadows bit in GPIObits +#define GP3 GPIObits.GP3 // bit 3, shadows bit in GPIObits +#define RA3 GPIObits.RA3 // bit 3, shadows bit in GPIObits +#define GP4 GPIObits.GP4 // bit 4, shadows bit in GPIObits +#define RA4 GPIObits.RA4 // bit 4, shadows bit in GPIObits +#define GP5 GPIObits.GP5 // bit 5, shadows bit in GPIObits +#define RA5 GPIObits.RA5 // bit 5, shadows bit in GPIObits + +#define RAIF INTCONbits.RAIF // bit 0 +#define INTF INTCONbits.INTF // bit 1 +#define T0IF INTCONbits.T0IF // bit 2 +#define RAIE INTCONbits.RAIE // bit 3 +#define INTE INTCONbits.INTE // bit 4 +#define T0IE INTCONbits.T0IE // bit 5 +#define PEIE INTCONbits.PEIE // bit 6 +#define GIE INTCONbits.GIE // bit 7 + +#define IOCA0 IOCAbits.IOCA0 // bit 0 +#define IOCA1 IOCAbits.IOCA1 // bit 1 +#define IOCA2 IOCAbits.IOCA2 // bit 2 +#define IOCA3 IOCAbits.IOCA3 // bit 3 +#define IOCA4 IOCAbits.IOCA4 // bit 4 +#define IOCA5 IOCAbits.IOCA5 // bit 5 + +#define LVDL0 LVDCONbits.LVDL0 // bit 0 +#define LVDL1 LVDCONbits.LVDL1 // bit 1 +#define LVDL2 LVDCONbits.LVDL2 // bit 2 +#define LVDEN LVDCONbits.LVDEN // bit 4, shadows bit in LVDCONbits +#define PLVDEN LVDCONbits.PLVDEN // bit 4, shadows bit in LVDCONbits +#define IRVST LVDCONbits.IRVST // bit 5 + +#define PS0 OPTION_REGbits.PS0 // bit 0 +#define PS1 OPTION_REGbits.PS1 // bit 1 +#define PS2 OPTION_REGbits.PS2 // bit 2 +#define PSA OPTION_REGbits.PSA // bit 3 +#define T0SE OPTION_REGbits.T0SE // bit 4 +#define T0CS OPTION_REGbits.T0CS // bit 5 +#define INTEDG OPTION_REGbits.INTEDG // bit 6 +#define NOT_RAPU OPTION_REGbits.NOT_RAPU // bit 7 + +#define SCS OSCCONbits.SCS // bit 0 +#define LTS OSCCONbits.LTS // bit 1 +#define HTS OSCCONbits.HTS // bit 2 +#define OSTS OSCCONbits.OSTS // bit 3 +#define IRCF0 OSCCONbits.IRCF0 // bit 4 +#define IRCF1 OSCCONbits.IRCF1 // bit 5 +#define IRCF2 OSCCONbits.IRCF2 // bit 6 + +#define TUN0 OSCTUNEbits.TUN0 // bit 0 +#define TUN1 OSCTUNEbits.TUN1 // bit 1 +#define TUN2 OSCTUNEbits.TUN2 // bit 2 +#define TUN3 OSCTUNEbits.TUN3 // bit 3 +#define TUN4 OSCTUNEbits.TUN4 // bit 4 + +#define NOT_BOR PCONbits.NOT_BOR // bit 0, shadows bit in PCONbits +#define NOT_BOD PCONbits.NOT_BOD // bit 0, shadows bit in PCONbits +#define NOT_POR PCONbits.NOT_POR // bit 1 +#define NOT_WUR PCONbits.NOT_WUR // bit 3 +#define SBOREN PCONbits.SBOREN // bit 4, shadows bit in PCONbits +#define SBODEN PCONbits.SBODEN // bit 4, shadows bit in PCONbits +#define ULPWUE PCONbits.ULPWUE // bit 5 + +#define TMR1IE PIE1bits.TMR1IE // bit 0 +#define OSFIE PIE1bits.OSFIE // bit 2 +#define C1IE PIE1bits.C1IE // bit 3 +#define CRIE PIE1bits.CRIE // bit 5 +#define LVDIE PIE1bits.LVDIE // bit 6 +#define EEIE PIE1bits.EEIE // bit 7 + +#define TMR1IF PIR1bits.TMR1IF // bit 0 +#define OSFIF PIR1bits.OSFIF // bit 2 +#define C1IF PIR1bits.C1IF // bit 3 +#define CRIF PIR1bits.CRIF // bit 5 +#define LVDIF PIR1bits.LVDIF // bit 6 +#define EEIF PIR1bits.EEIF // bit 7 + +#define C STATUSbits.C // bit 0 +#define DC STATUSbits.DC // bit 1 +#define Z STATUSbits.Z // bit 2 +#define NOT_PD STATUSbits.NOT_PD // bit 3 +#define NOT_TO STATUSbits.NOT_TO // bit 4 +#define RP0 STATUSbits.RP0 // bit 5 +#define RP1 STATUSbits.RP1 // bit 6 +#define IRP STATUSbits.IRP // bit 7 + +#define TMR1ON T1CONbits.TMR1ON // bit 0 +#define TMR1CS T1CONbits.TMR1CS // bit 1 +#define NOT_T1SYNC T1CONbits.NOT_T1SYNC // bit 2 +#define T1OSCEN T1CONbits.T1OSCEN // bit 3 +#define T1CKPS0 T1CONbits.T1CKPS0 // bit 4 +#define T1CKPS1 T1CONbits.T1CKPS1 // bit 5 +#define TMR1GE T1CONbits.TMR1GE // bit 6 +#define T1GINV T1CONbits.T1GINV // bit 7 + +#define TRISIO0 TRISAbits.TRISIO0 // bit 0, shadows bit in TRISAbits +#define TRISA0 TRISAbits.TRISA0 // bit 0, shadows bit in TRISAbits +#define TRISIO1 TRISAbits.TRISIO1 // bit 1, shadows bit in TRISAbits +#define TRISA1 TRISAbits.TRISA1 // bit 1, shadows bit in TRISAbits +#define TRISIO2 TRISAbits.TRISIO2 // bit 2, shadows bit in TRISAbits +#define TRISA2 TRISAbits.TRISA2 // bit 2, shadows bit in TRISAbits +#define TRISIO3 TRISAbits.TRISIO3 // bit 3, shadows bit in TRISAbits +#define TRISA3 TRISAbits.TRISA3 // bit 3, shadows bit in TRISAbits +#define TRISIO4 TRISAbits.TRISIO4 // bit 4, shadows bit in TRISAbits +#define TRISA4 TRISAbits.TRISA4 // bit 4, shadows bit in TRISAbits +#define TRISIO5 TRISAbits.TRISIO5 // bit 5, shadows bit in TRISAbits +#define TRISA5 TRISAbits.TRISA5 // bit 5, shadows bit in TRISAbits + +#define VR0 VRCONbits.VR0 // bit 0 +#define VR1 VRCONbits.VR1 // bit 1 +#define VR2 VRCONbits.VR2 // bit 2 +#define VR3 VRCONbits.VR3 // bit 3 +#define VRR VRCONbits.VRR // bit 5 +#define VREN VRCONbits.VREN // bit 7 + +#define WDA0 WDAbits.WDA0 // bit 0 +#define WDA1 WDAbits.WDA1 // bit 1 +#define WDA2 WDAbits.WDA2 // bit 2 +#define WDA4 WDAbits.WDA4 // bit 4 +#define WDA5 WDAbits.WDA5 // bit 5 + +#define SWDTEN WDTCONbits.SWDTEN // bit 0 +#define WDTPS0 WDTCONbits.WDTPS0 // bit 1 +#define WDTPS1 WDTCONbits.WDTPS1 // bit 2 +#define WDTPS2 WDTCONbits.WDTPS2 // bit 3 +#define WDTPS3 WDTCONbits.WDTPS3 // bit 4 + +#define WPUDA0 WPUDAbits.WPUDA0 // bit 0 +#define WPUDA1 WPUDAbits.WPUDA1 // bit 1 +#define WPUDA2 WPUDAbits.WPUDA2 // bit 2 +#define WPUDA4 WPUDAbits.WPUDA4 // bit 4 +#define WPUDA5 WPUDAbits.WPUDA5 // bit 5 + +#endif // #ifndef NO_BIT_DEFINES + +#endif // #ifndef __PIC12F635_H__ |