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| author | Xavier ASUS <xavi92psx@gmail.com> | 2019-10-18 00:31:54 +0200 |
|---|---|---|
| committer | Xavier ASUS <xavi92psx@gmail.com> | 2019-10-18 00:31:54 +0200 |
| commit | 268a53de823a6750d6256ee1fb1e7707b4b45740 (patch) | |
| tree | 42c1799a9a82b2f7d9790ee9fe181d72a7274751 /sim/ucsim/z80.src | |
| download | sdcc-gas-268a53de823a6750d6256ee1fb1e7707b4b45740.tar.gz | |
sdcc-3.9.0 fork implementing GNU assembler syntax
This fork aims to provide better support for stm8-binutils
Diffstat (limited to 'sim/ucsim/z80.src')
49 files changed, 14001 insertions, 0 deletions
diff --git a/sim/ucsim/z80.src/(c).1 b/sim/ucsim/z80.src/(c).1 new file mode 100644 index 0000000..d673f9f --- /dev/null +++ b/sim/ucsim/z80.src/(c).1 @@ -0,0 +1,25 @@ +/* + * Simulator of microcontrollers (@@F@@) + * + * Copyright (C) @@S@@,@@Y@@ Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ diff --git a/sim/ucsim/z80.src/Makefile b/sim/ucsim/z80.src/Makefile new file mode 100644 index 0000000..50fe691 --- /dev/null +++ b/sim/ucsim/z80.src/Makefile @@ -0,0 +1,170 @@ +# +# uCsim z80.src/Makefile +# +# (c) Drotos Daniel, Talker Bt. 1997 +# + +STARTYEAR = 1997 + +SHELL = /bin/sh +CXX = g++ +CPP = gcc -E +CXXCPP = g++ -E +RANLIB = ranlib +INSTALL = /usr/bin/install -c +STRIP = strip +MAKEDEP = g++ -MM + +top_builddir = .. +top_srcdir = .. + +transform = s,x,x, + +DEFS = $(subs -DHAVE_CONFIG_H,,-DHAVE_CONFIG_H) +CPPFLAGS = -I$(srcdir) -I$(top_srcdir) -I$(top_builddir) \ + -I$(top_srcdir)/cmd.src -I$(top_srcdir)/sim.src \ + -I$(top_srcdir)/gui.src +CFLAGS = -g -O2 -Wall +CXXFLAGS = -g -O2 -g -Wall +LDFLAGS = +PICOPT = -fPIC -DPIC +SHAREDLIB = yes +EXEEXT = + +LIBS = -L$(top_builddir) -lsim -lucsimutil -lguiucsim -lcmd -lsim -lrt -lnsl +DL = -ldl +dl_ok = yes + +prefix = /usr/local +exec_prefix = ${prefix} +bindir = ${exec_prefix}/bin +libdir = ${exec_prefix}/lib +datadir = ${datarootdir} +datarootdir = ${prefix}/share +includedir = ${prefix}/include +mandir = ${datarootdir}/man +man1dir = $(mandir)/man1 +man2dir = $(mandir)/man2 +infodir = ${datarootdir}/info +srcdir = . + + +OBJECTS_SHARED = glob.o \ + inst.o \ + inst_cb.o \ + inst_dd.o \ + inst_ed.o \ + inst_fd.o \ + inst_ddcb.o \ + inst_fdcb.o \ + glob_r2k.o inst_r2k.o inst_ed_r2k.o r2k.o \ + glob_lr35902.o inst_lr35902.o lr35902.o \ + simz80.o z80.o ez80.o +OBJECTS_EXE = sz80.o +OBJECTS = $(OBJECTS_SHARED) $(OBJECTS_EXE) + +Z80ASM = + +enable_dlso = no +dlso_ok = no + +#TEST_OBJ = test_bit.hex test_dis.hex test_mov.hex test_jmp.hex \ +# test_arith.hex + +# Compiling entire program or any subproject +# ------------------------------------------ +all: checkconf otherlibs z80.src tests + +tests: $(TEST_OBJ) + + +# Compiling and installing everything and runing test +# --------------------------------------------------- +install: all installdirs + $(INSTALL) sz80$(EXEEXT) $(DESTDIR)$(bindir)/`echo sz80|sed '$(transform)'`$(EXEEXT) + $(STRIP) $(DESTDIR)$(bindir)/`echo sz80|sed '$(transform)'`$(EXEEXT) + + +# Deleting all the installed files +# -------------------------------- +uninstall: + rm -f $(DESTDIR)$(bindir)/`echo sz80|sed '$(transform)'`$(EXEEXT) + + +# Performing self-test +# -------------------- +check: test + +test: + + +# Performing installation test +# ---------------------------- +installcheck: + + +# Creating installation directories +# --------------------------------- +installdirs: + test -d $(DESTDIR)$(bindir) || $(INSTALL) -d $(DESTDIR)$(bindir) + + +# Creating dependencies +# --------------------- +dep: Makefile.dep + +Makefile.dep: $(srcdir)/*.cc $(srcdir)/*.h + $(MAKEDEP) $(CPPFLAGS) $(filter %.cc,$^) >Makefile.dep + +-include Makefile.dep +include $(srcdir)/clean.mk + +# My rules +# -------- +.SUFFIXES: .asm .hex + +z80.src: sz80$(EXEEXT) shared_lib + +sz80$(EXEEXT): $(OBJECTS) $(top_builddir)/libcmd.a $(top_builddir)/libguiucsim.a $(top_builddir)/libsim.a $(top_builddir)/libucsimutil.a + $(CXX) $(CXXFLAGS) $(LDFLAGS) $(OBJECTS) $(LIBS) -o $@ + +ifeq ($(dlso_ok),yes) +shared_lib: $(top_builddir)/sz80.so +else +shared_lib: + @$(top_srcdir)/mkecho $(top_builddir) "No z80 shared lib made." + @$(top_srcdir)/mkecho $(top_builddir) "(SHAREDLIB="$(SHAREDLIB)",dl_ok="$(dl_ok)",enable_dlso="$(enable_dlso)")" +endif + +$(top_builddir)/sz80.so: $(OBJECTS_SHARED) + $(CXX) -shared $(LDFLAGS) $(OBJECTS_SHARED) -o $(top_builddir)/sz80.so + +otherlibs: $(top_builddir)/libcmd.a $(top_builddir)/libguiucsim.a $(top_builddir)/libsim.a $(top_builddir)/libucsimutil.a + +$(top_builddir)/libcmd.a: + $(MAKE) -C $(top_builddir)/cmd.src all + +$(top_builddir)/libguiucsim.a: + $(MAKE) -C $(top_builddir)/gui.src checkconf ucsim_lib + +$(top_builddir)/libsim.a: + $(MAKE) -C $(top_builddir)/sim.src all + +$(top_builddir)/libucsimutil.a: + $(MAKE) -C $(top_builddir) -f main.mk + +.cc.o: + $(CXX) $(CXXFLAGS) $(PICOPT) $(CPPFLAGS) $(TARGET_ARCH) -c $< -o $@ + +.asm.hex: + $(Z80ASM) -l $< -o $@ -e $<.lst + + +# Remaking configuration +# ---------------------- +checkconf: + @if [ -f $(top_builddir)/devel ]; then\ + $(MAKE) -f conf.mk srcdir="$(srcdir)" top_builddir="$(top_builddir)" freshconf;\ + fi + +# End of z80.src/Makefile.in diff --git a/sim/ucsim/z80.src/Makefile.dep b/sim/ucsim/z80.src/Makefile.dep new file mode 100644 index 0000000..fa0547c --- /dev/null +++ b/sim/ucsim/z80.src/Makefile.dep @@ -0,0 +1,151 @@ +inst_ed_r2k.o: inst_ed_r2k.cc ../ddconfig.h r2kcl.h z80cl.h \ + ../sim.src/uccl.h ../stypes.h ../ddconfig.h ../pobjcl.h ../pobjt.h \ + ../eventcl.h ../charscl.h ../pobjt.h ../sim.src/hwcl.h \ + ../sim.src/guiobjcl.h ../cmd.src/newcmdcl.h ../optioncl.h ../pobjcl.h \ + ../stypes.h ../cmd.src/commandcl.h ../cmd.src/newcmdcl.h \ + ../cmd.src/newcmdposixcl.h ../fiocl.h ../cmd.src/cmdutil.h \ + ../sim.src/memcl.h ../eventcl.h ../errorcl.h ../sim.src/uccl.h \ + ../sim.src/brkcl.h ../sim.src/stackcl.h ../sim.src/varcl.h \ + ../sim.src/uccl_instructions.h regsz80.h z80mac.h +simz80.o: simz80.cc ../globals.h ../ddconfig.h ../stypes.h ../appcl.h \ + ../pobjcl.h ../pobjt.h ../eventcl.h ../charscl.h ../optioncl.h \ + ../sim.src/argcl.h ../pobjcl.h ../stypes.h ../sim.src/simcl.h \ + ../cmd.src/newcmdcl.h ../ddconfig.h ../optioncl.h ../cmd.src/commandcl.h \ + ../cmd.src/newcmdcl.h ../gui.src/guicl.h ../gui.src/ifcl.h \ + ../sim.src/guiobjcl.h ../sim.src/uccl.h ../pobjt.h ../sim.src/hwcl.h \ + ../sim.src/guiobjcl.h ../cmd.src/newcmdposixcl.h ../fiocl.h \ + ../cmd.src/cmdutil.h ../sim.src/memcl.h ../eventcl.h ../errorcl.h \ + ../sim.src/brkcl.h ../sim.src/stackcl.h ../sim.src/varcl.h \ + ../sim.src/uccl_instructions.h ../sim.src/argcl.h simz80cl.h z80cl.h \ + ../sim.src/uccl.h regsz80.h r2kcl.h lr35902cl.h ez80cl.h +inst_fdcb.o: inst_fdcb.cc ../ddconfig.h z80cl.h ../sim.src/uccl.h \ + ../stypes.h ../ddconfig.h ../pobjcl.h ../pobjt.h ../eventcl.h \ + ../charscl.h ../pobjt.h ../sim.src/hwcl.h ../sim.src/guiobjcl.h \ + ../cmd.src/newcmdcl.h ../optioncl.h ../pobjcl.h ../stypes.h \ + ../cmd.src/commandcl.h ../cmd.src/newcmdcl.h ../cmd.src/newcmdposixcl.h \ + ../fiocl.h ../cmd.src/cmdutil.h ../sim.src/memcl.h ../eventcl.h \ + ../errorcl.h ../sim.src/uccl.h ../sim.src/brkcl.h ../sim.src/stackcl.h \ + ../sim.src/varcl.h ../sim.src/uccl_instructions.h regsz80.h z80mac.h \ + inst_xxcb.cc +glob_r2k.o: glob_r2k.cc glob.cc ../stypes.h ../ddconfig.h +inst_ddcb.o: inst_ddcb.cc ../ddconfig.h z80cl.h ../sim.src/uccl.h \ + ../stypes.h ../ddconfig.h ../pobjcl.h ../pobjt.h ../eventcl.h \ + ../charscl.h ../pobjt.h ../sim.src/hwcl.h ../sim.src/guiobjcl.h \ + ../cmd.src/newcmdcl.h ../optioncl.h ../pobjcl.h ../stypes.h \ + ../cmd.src/commandcl.h ../cmd.src/newcmdcl.h ../cmd.src/newcmdposixcl.h \ + ../fiocl.h ../cmd.src/cmdutil.h ../sim.src/memcl.h ../eventcl.h \ + ../errorcl.h ../sim.src/uccl.h ../sim.src/brkcl.h ../sim.src/stackcl.h \ + ../sim.src/varcl.h ../sim.src/uccl_instructions.h regsz80.h z80mac.h \ + inst_xxcb.cc +inst_lr35902.o: inst_lr35902.cc ../ddconfig.h lr35902cl.h z80cl.h \ + ../sim.src/uccl.h ../stypes.h ../ddconfig.h ../pobjcl.h ../pobjt.h \ + ../eventcl.h ../charscl.h ../pobjt.h ../sim.src/hwcl.h \ + ../sim.src/guiobjcl.h ../cmd.src/newcmdcl.h ../optioncl.h ../pobjcl.h \ + ../stypes.h ../cmd.src/commandcl.h ../cmd.src/newcmdcl.h \ + ../cmd.src/newcmdposixcl.h ../fiocl.h ../cmd.src/cmdutil.h \ + ../sim.src/memcl.h ../eventcl.h ../errorcl.h ../sim.src/uccl.h \ + ../sim.src/brkcl.h ../sim.src/stackcl.h ../sim.src/varcl.h \ + ../sim.src/uccl_instructions.h regsz80.h +inst_xxcb.o: inst_xxcb.cc +inst.o: inst.cc ../ddconfig.h z80cl.h ../sim.src/uccl.h ../stypes.h \ + ../ddconfig.h ../pobjcl.h ../pobjt.h ../eventcl.h ../charscl.h \ + ../pobjt.h ../sim.src/hwcl.h ../sim.src/guiobjcl.h ../cmd.src/newcmdcl.h \ + ../optioncl.h ../pobjcl.h ../stypes.h ../cmd.src/commandcl.h \ + ../cmd.src/newcmdcl.h ../cmd.src/newcmdposixcl.h ../fiocl.h \ + ../cmd.src/cmdutil.h ../sim.src/memcl.h ../eventcl.h ../errorcl.h \ + ../sim.src/uccl.h ../sim.src/brkcl.h ../sim.src/stackcl.h \ + ../sim.src/varcl.h ../sim.src/uccl_instructions.h regsz80.h z80mac.h +ez80.o: ez80.cc z80mac.h ez80cl.h z80cl.h ../sim.src/uccl.h ../stypes.h \ + ../ddconfig.h ../pobjcl.h ../pobjt.h ../eventcl.h ../charscl.h \ + ../pobjt.h ../sim.src/hwcl.h ../sim.src/guiobjcl.h ../ddconfig.h \ + ../cmd.src/newcmdcl.h ../optioncl.h ../pobjcl.h ../stypes.h \ + ../cmd.src/commandcl.h ../cmd.src/newcmdcl.h ../cmd.src/newcmdposixcl.h \ + ../fiocl.h ../cmd.src/cmdutil.h ../sim.src/memcl.h ../eventcl.h \ + ../errorcl.h ../sim.src/uccl.h ../sim.src/brkcl.h ../sim.src/stackcl.h \ + ../sim.src/varcl.h ../sim.src/uccl_instructions.h regsz80.h +inst_r2k.o: inst_r2k.cc ../ddconfig.h r2kcl.h z80cl.h ../sim.src/uccl.h \ + ../stypes.h ../ddconfig.h ../pobjcl.h ../pobjt.h ../eventcl.h \ + ../charscl.h ../pobjt.h ../sim.src/hwcl.h ../sim.src/guiobjcl.h \ + ../cmd.src/newcmdcl.h ../optioncl.h ../pobjcl.h ../stypes.h \ + ../cmd.src/commandcl.h ../cmd.src/newcmdcl.h ../cmd.src/newcmdposixcl.h \ + ../fiocl.h ../cmd.src/cmdutil.h ../sim.src/memcl.h ../eventcl.h \ + ../errorcl.h ../sim.src/uccl.h ../sim.src/brkcl.h ../sim.src/stackcl.h \ + ../sim.src/varcl.h ../sim.src/uccl_instructions.h regsz80.h z80mac.h +glob_lr35902.o: glob_lr35902.cc ../stypes.h ../ddconfig.h +inst_dd.o: inst_dd.cc ../ddconfig.h z80cl.h ../sim.src/uccl.h ../stypes.h \ + ../ddconfig.h ../pobjcl.h ../pobjt.h ../eventcl.h ../charscl.h \ + ../pobjt.h ../sim.src/hwcl.h ../sim.src/guiobjcl.h ../cmd.src/newcmdcl.h \ + ../optioncl.h ../pobjcl.h ../stypes.h ../cmd.src/commandcl.h \ + ../cmd.src/newcmdcl.h ../cmd.src/newcmdposixcl.h ../fiocl.h \ + ../cmd.src/cmdutil.h ../sim.src/memcl.h ../eventcl.h ../errorcl.h \ + ../sim.src/uccl.h ../sim.src/brkcl.h ../sim.src/stackcl.h \ + ../sim.src/varcl.h ../sim.src/uccl_instructions.h regsz80.h z80mac.h \ + inst_xd.cc +inst_ed.o: inst_ed.cc ../ddconfig.h z80cl.h ../sim.src/uccl.h ../stypes.h \ + ../ddconfig.h ../pobjcl.h ../pobjt.h ../eventcl.h ../charscl.h \ + ../pobjt.h ../sim.src/hwcl.h ../sim.src/guiobjcl.h ../cmd.src/newcmdcl.h \ + ../optioncl.h ../pobjcl.h ../stypes.h ../cmd.src/commandcl.h \ + ../cmd.src/newcmdcl.h ../cmd.src/newcmdposixcl.h ../fiocl.h \ + ../cmd.src/cmdutil.h ../sim.src/memcl.h ../eventcl.h ../errorcl.h \ + ../sim.src/uccl.h ../sim.src/brkcl.h ../sim.src/stackcl.h \ + ../sim.src/varcl.h ../sim.src/uccl_instructions.h regsz80.h z80mac.h +r2k.o: r2k.cc ../ddconfig.h ../i_string.h ../ddconfig.h ../pobjcl.h \ + ../pobjt.h ../eventcl.h ../charscl.h ../sim.src/simcl.h \ + ../cmd.src/newcmdcl.h ../optioncl.h ../pobjcl.h ../stypes.h \ + ../cmd.src/commandcl.h ../cmd.src/newcmdcl.h ../gui.src/guicl.h \ + ../gui.src/ifcl.h ../sim.src/guiobjcl.h ../sim.src/uccl.h ../stypes.h \ + ../pobjt.h ../sim.src/hwcl.h ../sim.src/guiobjcl.h \ + ../cmd.src/newcmdposixcl.h ../fiocl.h ../cmd.src/cmdutil.h \ + ../sim.src/memcl.h ../eventcl.h ../errorcl.h ../sim.src/brkcl.h \ + ../sim.src/stackcl.h ../sim.src/varcl.h ../sim.src/uccl_instructions.h \ + ../sim.src/argcl.h z80cl.h ../sim.src/uccl.h regsz80.h r2kcl.h glob.h +inst_fd.o: inst_fd.cc ../ddconfig.h z80cl.h ../sim.src/uccl.h ../stypes.h \ + ../ddconfig.h ../pobjcl.h ../pobjt.h ../eventcl.h ../charscl.h \ + ../pobjt.h ../sim.src/hwcl.h ../sim.src/guiobjcl.h ../cmd.src/newcmdcl.h \ + ../optioncl.h ../pobjcl.h ../stypes.h ../cmd.src/commandcl.h \ + ../cmd.src/newcmdcl.h ../cmd.src/newcmdposixcl.h ../fiocl.h \ + ../cmd.src/cmdutil.h ../sim.src/memcl.h ../eventcl.h ../errorcl.h \ + ../sim.src/uccl.h ../sim.src/brkcl.h ../sim.src/stackcl.h \ + ../sim.src/varcl.h ../sim.src/uccl_instructions.h regsz80.h z80mac.h \ + inst_xd.cc +glob.o: glob.cc ../stypes.h ../ddconfig.h +sz80.o: sz80.cc ../globals.h ../ddconfig.h ../stypes.h ../appcl.h \ + ../pobjcl.h ../pobjt.h ../eventcl.h ../charscl.h ../optioncl.h \ + ../sim.src/argcl.h ../pobjcl.h ../stypes.h ../sim.src/simcl.h \ + ../cmd.src/newcmdcl.h ../ddconfig.h ../optioncl.h ../cmd.src/commandcl.h \ + ../cmd.src/newcmdcl.h ../gui.src/guicl.h ../gui.src/ifcl.h \ + ../sim.src/guiobjcl.h ../sim.src/uccl.h ../pobjt.h ../sim.src/hwcl.h \ + ../sim.src/guiobjcl.h ../cmd.src/newcmdposixcl.h ../fiocl.h \ + ../cmd.src/cmdutil.h ../sim.src/memcl.h ../eventcl.h ../errorcl.h \ + ../sim.src/brkcl.h ../sim.src/stackcl.h ../sim.src/varcl.h \ + ../sim.src/uccl_instructions.h ../sim.src/argcl.h ../appcl.h simz80cl.h +z80.o: z80.cc ../ddconfig.h ../i_string.h ../ddconfig.h ../pobjcl.h \ + ../pobjt.h ../eventcl.h ../charscl.h ../sim.src/simcl.h \ + ../cmd.src/newcmdcl.h ../optioncl.h ../pobjcl.h ../stypes.h \ + ../cmd.src/commandcl.h ../cmd.src/newcmdcl.h ../gui.src/guicl.h \ + ../gui.src/ifcl.h ../sim.src/guiobjcl.h ../sim.src/uccl.h ../stypes.h \ + ../pobjt.h ../sim.src/hwcl.h ../sim.src/guiobjcl.h \ + ../cmd.src/newcmdposixcl.h ../fiocl.h ../cmd.src/cmdutil.h \ + ../sim.src/memcl.h ../eventcl.h ../errorcl.h ../sim.src/brkcl.h \ + ../sim.src/stackcl.h ../sim.src/varcl.h ../sim.src/uccl_instructions.h \ + ../sim.src/argcl.h z80cl.h ../sim.src/uccl.h regsz80.h glob.h +inst_cb.o: inst_cb.cc ../ddconfig.h z80cl.h ../sim.src/uccl.h ../stypes.h \ + ../ddconfig.h ../pobjcl.h ../pobjt.h ../eventcl.h ../charscl.h \ + ../pobjt.h ../sim.src/hwcl.h ../sim.src/guiobjcl.h ../cmd.src/newcmdcl.h \ + ../optioncl.h ../pobjcl.h ../stypes.h ../cmd.src/commandcl.h \ + ../cmd.src/newcmdcl.h ../cmd.src/newcmdposixcl.h ../fiocl.h \ + ../cmd.src/cmdutil.h ../sim.src/memcl.h ../eventcl.h ../errorcl.h \ + ../sim.src/uccl.h ../sim.src/brkcl.h ../sim.src/stackcl.h \ + ../sim.src/varcl.h ../sim.src/uccl_instructions.h regsz80.h z80mac.h +inst_xd.o: inst_xd.cc +lr35902.o: lr35902.cc ../ddconfig.h ../i_string.h ../ddconfig.h \ + ../pobjcl.h ../pobjt.h ../eventcl.h ../charscl.h ../sim.src/simcl.h \ + ../cmd.src/newcmdcl.h ../optioncl.h ../pobjcl.h ../stypes.h \ + ../cmd.src/commandcl.h ../cmd.src/newcmdcl.h ../gui.src/guicl.h \ + ../gui.src/ifcl.h ../sim.src/guiobjcl.h ../sim.src/uccl.h ../stypes.h \ + ../pobjt.h ../sim.src/hwcl.h ../sim.src/guiobjcl.h \ + ../cmd.src/newcmdposixcl.h ../fiocl.h ../cmd.src/cmdutil.h \ + ../sim.src/memcl.h ../eventcl.h ../errorcl.h ../sim.src/brkcl.h \ + ../sim.src/stackcl.h ../sim.src/varcl.h ../sim.src/uccl_instructions.h \ + ../sim.src/argcl.h z80cl.h ../sim.src/uccl.h regsz80.h lr35902cl.h \ + glob.h diff --git a/sim/ucsim/z80.src/Makefile.in b/sim/ucsim/z80.src/Makefile.in new file mode 100644 index 0000000..8c3cdc4 --- /dev/null +++ b/sim/ucsim/z80.src/Makefile.in @@ -0,0 +1,170 @@ +# +# uCsim z80.src/Makefile +# +# (c) Drotos Daniel, Talker Bt. 1997 +# + +STARTYEAR = 1997 + +SHELL = /bin/sh +CXX = @CXX@ +CPP = @CPP@ +CXXCPP = @CXXCPP@ +RANLIB = @RANLIB@ +INSTALL = @INSTALL@ +STRIP = @STRIP@ +MAKEDEP = @MAKEDEP@ + +top_builddir = @top_builddir@ +top_srcdir = @top_srcdir@ + +transform = @program_transform_name@ + +DEFS = $(subs -DHAVE_CONFIG_H,,@DEFS@) +CPPFLAGS = @CPPFLAGS@ -I$(srcdir) -I$(top_srcdir) -I$(top_builddir) \ + -I$(top_srcdir)/cmd.src -I$(top_srcdir)/sim.src \ + -I$(top_srcdir)/gui.src +CFLAGS = @CFLAGS@ @WALL_FLAG@ +CXXFLAGS = @CXXFLAGS@ @WALL_FLAG@ +LDFLAGS = @LDFLAGS@ +PICOPT = @PICOPT@ +SHAREDLIB = @SHAREDLIB@ +EXEEXT = @EXEEXT@ + +LIBS = -L$(top_builddir) -lsim -lucsimutil -lguiucsim -lcmd -lsim @LIBS@ +DL = @DL@ +dl_ok = @dl_ok@ + +prefix = @prefix@ +exec_prefix = @exec_prefix@ +bindir = @bindir@ +libdir = @libdir@ +datadir = @datadir@ +datarootdir = @datarootdir@ +includedir = @includedir@ +mandir = @mandir@ +man1dir = $(mandir)/man1 +man2dir = $(mandir)/man2 +infodir = @infodir@ +srcdir = @srcdir@ +VPATH = @srcdir@ + +OBJECTS_SHARED = glob.o \ + inst.o \ + inst_cb.o \ + inst_dd.o \ + inst_ed.o \ + inst_fd.o \ + inst_ddcb.o \ + inst_fdcb.o \ + glob_r2k.o inst_r2k.o inst_ed_r2k.o r2k.o \ + glob_lr35902.o inst_lr35902.o lr35902.o \ + simz80.o z80.o ez80.o +OBJECTS_EXE = sz80.o +OBJECTS = $(OBJECTS_SHARED) $(OBJECTS_EXE) + +Z80ASM = + +enable_dlso = @enable_dlso@ +dlso_ok = @dlso_ok@ + +#TEST_OBJ = test_bit.hex test_dis.hex test_mov.hex test_jmp.hex \ +# test_arith.hex + +# Compiling entire program or any subproject +# ------------------------------------------ +all: checkconf otherlibs z80.src tests + +tests: $(TEST_OBJ) + + +# Compiling and installing everything and runing test +# --------------------------------------------------- +install: all installdirs + $(INSTALL) sz80$(EXEEXT) $(DESTDIR)$(bindir)/`echo sz80|sed '$(transform)'`$(EXEEXT) + $(STRIP) $(DESTDIR)$(bindir)/`echo sz80|sed '$(transform)'`$(EXEEXT) + + +# Deleting all the installed files +# -------------------------------- +uninstall: + rm -f $(DESTDIR)$(bindir)/`echo sz80|sed '$(transform)'`$(EXEEXT) + + +# Performing self-test +# -------------------- +check: test + +test: + + +# Performing installation test +# ---------------------------- +installcheck: + + +# Creating installation directories +# --------------------------------- +installdirs: + test -d $(DESTDIR)$(bindir) || $(INSTALL) -d $(DESTDIR)$(bindir) + + +# Creating dependencies +# --------------------- +dep: Makefile.dep + +Makefile.dep: $(srcdir)/*.cc $(srcdir)/*.h + $(MAKEDEP) $(CPPFLAGS) $(filter %.cc,$^) >Makefile.dep + +-include Makefile.dep +include $(srcdir)/clean.mk + +# My rules +# -------- +.SUFFIXES: .asm .hex + +z80.src: sz80$(EXEEXT) shared_lib + +sz80$(EXEEXT): $(OBJECTS) $(top_builddir)/libcmd.a $(top_builddir)/libguiucsim.a $(top_builddir)/libsim.a $(top_builddir)/libucsimutil.a + $(CXX) $(CXXFLAGS) $(LDFLAGS) $(OBJECTS) $(LIBS) -o $@ + +ifeq ($(dlso_ok),yes) +shared_lib: $(top_builddir)/sz80.so +else +shared_lib: + @$(top_srcdir)/mkecho $(top_builddir) "No z80 shared lib made." + @$(top_srcdir)/mkecho $(top_builddir) "(SHAREDLIB="$(SHAREDLIB)",dl_ok="$(dl_ok)",enable_dlso="$(enable_dlso)")" +endif + +$(top_builddir)/sz80.so: $(OBJECTS_SHARED) + $(CXX) -shared $(LDFLAGS) $(OBJECTS_SHARED) -o $(top_builddir)/sz80.so + +otherlibs: $(top_builddir)/libcmd.a $(top_builddir)/libguiucsim.a $(top_builddir)/libsim.a $(top_builddir)/libucsimutil.a + +$(top_builddir)/libcmd.a: + $(MAKE) -C $(top_builddir)/cmd.src all + +$(top_builddir)/libguiucsim.a: + $(MAKE) -C $(top_builddir)/gui.src checkconf ucsim_lib + +$(top_builddir)/libsim.a: + $(MAKE) -C $(top_builddir)/sim.src all + +$(top_builddir)/libucsimutil.a: + $(MAKE) -C $(top_builddir) -f main.mk + +.cc.o: + $(CXX) $(CXXFLAGS) $(PICOPT) $(CPPFLAGS) $(TARGET_ARCH) -c $< -o $@ + +.asm.hex: + $(Z80ASM) -l $< -o $@ -e $<.lst + + +# Remaking configuration +# ---------------------- +checkconf: + @if [ -f $(top_builddir)/devel ]; then\ + $(MAKE) -f conf.mk srcdir="$(srcdir)" top_builddir="$(top_builddir)" freshconf;\ + fi + +# End of z80.src/Makefile.in diff --git a/sim/ucsim/z80.src/clean.mk b/sim/ucsim/z80.src/clean.mk new file mode 100644 index 0000000..5781b8c --- /dev/null +++ b/sim/ucsim/z80.src/clean.mk @@ -0,0 +1,26 @@ +# Deleting all files created by building the program +# -------------------------------------------------- +clean: + rm -f *core *[%~] *.[oa] + rm -f .[a-z]*~ + rm -f sz80$(EXEEXT) + + +# Deleting all files created by configuring or building the program +# ----------------------------------------------------------------- +distclean: clean + rm -f config.cache config.log config.status + rm -f Makefile *.dep + + +# Like clean but some files may still exist +# ----------------------------------------- +mostlyclean: clean + + +# Deleting everything that can reconstructed by this Makefile. It deletes +# everything deleted by distclean plus files created by bison, etc. +# ----------------------------------------------------------------------- +realclean: distclean + +# End of z80.src/clean.mk diff --git a/sim/ucsim/z80.src/conf.mk b/sim/ucsim/z80.src/conf.mk new file mode 100644 index 0000000..3048376 --- /dev/null +++ b/sim/ucsim/z80.src/conf.mk @@ -0,0 +1,10 @@ +# +# Makefile targets to remake configuration +# + +freshconf: Makefile + +Makefile: $(srcdir)/Makefile.in $(top_srcdir)/configure.ac + cd $(top_builddir) && $(SHELL) ./config.status + +# End of z80.src/conf.mk diff --git a/sim/ucsim/z80.src/ez80.cc b/sim/ucsim/z80.src/ez80.cc new file mode 100644 index 0000000..e604155 --- /dev/null +++ b/sim/ucsim/z80.src/ez80.cc @@ -0,0 +1,863 @@ +/* + * Simulator of microcontrollers (ez80.cc) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#include <stdint.h> + +#include "z80mac.h" + +#include "ez80cl.h" + +struct dis_entry disass_ez80_ed[]= + { + // ED + { 0x000f, 0x00ff, ' ', 1, "LD (HL),BC" }, + { 0x001f, 0x00ff, ' ', 1, "LD (HL),DE" }, + { 0x002f, 0x00ff, ' ', 1, "LD (HL),HL" }, + { 0x0037, 0x00ff, ' ', 1, "LD IX,(HL)" }, + { 0x0031, 0x00ff, ' ', 1, "LD IY,(HL)" }, + { 0x0007, 0x00ff, ' ', 1, "LD BC,(HL)" }, + { 0x0017, 0x00ff, ' ', 1, "LD DE,(HL)" }, + { 0x0027, 0x00ff, ' ', 1, "LD HL,(HL)" }, + // ED + { 0x0032, 0x00ff, ' ', 2, "LEA IX,IX+%d" }, + { 0x0055, 0x00ff, ' ', 2, "LEA IY,IX+%d" }, + { 0x0054, 0x00ff, ' ', 2, "LEA IX,IY+%d" }, + { 0x0033, 0x00ff, ' ', 2, "LEA IY,IY+%d" }, + { 0x0002, 0x00ff, ' ', 2, "LEA BC,IX+%d" }, + { 0x0012, 0x00ff, ' ', 2, "LEA DE,IX+%d" }, + { 0x0022, 0x00ff, ' ', 2, "LEA HL,IX+%d" }, + { 0x0003, 0x00ff, ' ', 2, "LEA BC,IY+%d" }, + { 0x0013, 0x00ff, ' ', 2, "LEA DE,IY+%d" }, + { 0x0023, 0x00ff, ' ', 2, "LEA HL,IY+%d" }, + // ED + { 0x0065, 0x00ff, ' ', 2, "PEA IX+%d" }, + { 0x0066, 0x00ff, ' ', 2, "PEA IY+%d" }, + { 0, 0, 0, 0, NULL } + }; + +struct dis_entry disass_ez80_dd[]= + { + // DD + { 0x003f, 0x00ff, ' ', 2, "LD (IX+%d),IX" }, + { 0x003E, 0x00ff, ' ', 2, "LD (IX+%d),IY" }, + { 0x0037, 0x00ff, ' ', 2, "LD IX,(IX+%d)" }, + { 0x0031, 0x00ff, ' ', 2, "LD IY,(IX+%d)" }, + { 0x000f, 0x00ff, ' ', 2, "LD (IX+%d),BC" }, + { 0x001f, 0x00ff, ' ', 2, "LD (IX+%d),DE" }, + { 0x002f, 0x00ff, ' ', 2, "LD (IX+%d),HL" }, + { 0x0007, 0x00ff, ' ', 2, "LD BC,(IX+%d)" }, + { 0x0017, 0x00ff, ' ', 2, "LD DE,(IX+%d)" }, + { 0x0027, 0x00ff, ' ', 2, "LD HL,(IX+%d)" }, + // DD + { 0x0064, 0x00ff, ' ', 1, "LD IXH,IXH" }, + { 0x0065, 0x00ff, ' ', 1, "LD IXH,IXL" }, + { 0x006c, 0x00ff, ' ', 1, "LD IXL,IXH" }, + { 0x006d, 0x00ff, ' ', 1, "LD IXL,IXL" }, + { 0x0026, 0x00ff, ' ', 2, "LD IXH,%d" }, + { 0x002e, 0x00ff, ' ', 2, "LD IXL,%d" }, + // DD + { 0x0067, 0x00ff, ' ', 1, "LD IXH,A" }, + { 0x0060, 0x00ff, ' ', 1, "LD IXH,B" }, + { 0x0061, 0x00ff, ' ', 1, "LD IXH,C" }, + { 0x0062, 0x00ff, ' ', 1, "LD IXH,D" }, + { 0x0063, 0x00ff, ' ', 1, "LD IXH,E" }, + { 0x006f, 0x00ff, ' ', 1, "LD IXL,A" }, + { 0x0068, 0x00ff, ' ', 1, "LD IXL,B" }, + { 0x0069, 0x00ff, ' ', 1, "LD IXL,C" }, + { 0x006a, 0x00ff, ' ', 1, "LD IXL,D" }, + { 0x006b, 0x00ff, ' ', 1, "LD IXL,E" }, + { 0x007c, 0x00ff, ' ', 1, "LD A,IXH" }, + { 0x007d, 0x00ff, ' ', 1, "LD A,IXL" }, + { 0x0044, 0x00ff, ' ', 1, "LD B,IXH" }, + { 0x0045, 0x00ff, ' ', 1, "LD B,IXL" }, + { 0x004c, 0x00ff, ' ', 1, "LD C,IXH" }, + { 0x004d, 0x00ff, ' ', 1, "LD C,IXL" }, + { 0x0054, 0x00ff, ' ', 1, "LD D,IXH" }, + { 0x0055, 0x00ff, ' ', 1, "LD D,IXL" }, + { 0x005c, 0x00ff, ' ', 1, "LD E,IXH" }, + { 0x005d, 0x00ff, ' ', 1, "LD E,IXL" }, + // DD + { 0x0084, 0x00ff, ' ', 1, "ADD A,IXH" }, + { 0x0085, 0x00ff, ' ', 1, "ADD A,IXL" }, + { 0x008c, 0x00ff, ' ', 1, "ADC A,IXH" }, + { 0x008d, 0x00ff, ' ', 1, "ADC A,IXL" }, + // DD + { 0x0094, 0x00ff, ' ', 1, "SUB A,IXH" }, + { 0x0095, 0x00ff, ' ', 1, "SUB A,IXL" }, + { 0x009c, 0x00ff, ' ', 1, "SBC A,IXH" }, + { 0x009d, 0x00ff, ' ', 1, "SBC A,IXL" }, + { 0x00bc, 0x00ff, ' ', 1, "CP A,IXH" }, + { 0x00bd, 0x00ff, ' ', 1, "CP A,IXL" }, + // DD + { 0x0025, 0x00ff, ' ', 1, "DEC IXH" }, + { 0x002d, 0x00ff, ' ', 1, "DEC IXL" }, + { 0x0024, 0x00ff, ' ', 1, "INC IXH" }, + { 0x002c, 0x00ff, ' ', 1, "INC IXL" }, + // DD + { 0x00a4, 0x00ff, ' ', 1, "AND A,IXH" }, + { 0x00a5, 0x00ff, ' ', 1, "AND A,IXL" }, + { 0x00b4, 0x00ff, ' ', 1, "OR A,IXH" }, + { 0x00b5, 0x00ff, ' ', 1, "OR A,IXL" }, + { 0x00ac, 0x00ff, ' ', 1, "XOR A,IXH" }, + { 0x00ad, 0x00ff, ' ', 1, "XOR A,IXL" }, + { 0, 0, 0, 0, NULL } + }; + +struct dis_entry disass_ez80_fd[]= + { + // FD + { 0x003e, 0x00ff, ' ', 2, "LD (IY+%d),IX" }, + { 0x003f, 0x00ff, ' ', 2, "LD (IY+%d),IY" }, + { 0x0031, 0x00ff, ' ', 2, "LD IX,(IY+%d)" }, + { 0x003f, 0x00ff, ' ', 2, "LD IY,(IY+%d)" }, + { 0x000f, 0x00ff, ' ', 2, "LD (IY+%d),BC" }, + { 0x001f, 0x00ff, ' ', 2, "LD (IY+%d),DE" }, + { 0x002f, 0x00ff, ' ', 2, "LD (IY+%d),HL" }, + { 0x0007, 0x00ff, ' ', 2, "LD BC,(IY+%d)" }, + { 0x0017, 0x00ff, ' ', 2, "LD DE,(IY+%d)" }, + { 0x0027, 0x00ff, ' ', 2, "LD HL,(IY+%d)" }, + // FD + { 0x0064, 0x00ff, ' ', 1, "LD IYH,IYH" }, + { 0x0065, 0x00ff, ' ', 1, "LD IYH,IYL" }, + { 0x006c, 0x00ff, ' ', 1, "LD IYL,IYH" }, + { 0x006d, 0x00ff, ' ', 1, "LD IYL,IYL" }, + { 0x0026, 0x00ff, ' ', 2, "LD IYH,%d" }, + { 0x002e, 0x00ff, ' ', 2, "LD IYL,%d" }, + // FD + { 0x0067, 0x00ff, ' ', 1, "LD IYH,A" }, + { 0x0060, 0x00ff, ' ', 1, "LD IYH,B" }, + { 0x0061, 0x00ff, ' ', 1, "LD IYH,C" }, + { 0x0062, 0x00ff, ' ', 1, "LD IYH,D" }, + { 0x0063, 0x00ff, ' ', 1, "LD IYH,E" }, + { 0x006f, 0x00ff, ' ', 1, "LD IYL,A" }, + { 0x0068, 0x00ff, ' ', 1, "LD IYL,B" }, + { 0x0069, 0x00ff, ' ', 1, "LD IYL,C" }, + { 0x006a, 0x00ff, ' ', 1, "LD IYL,D" }, + { 0x006b, 0x00ff, ' ', 1, "LD IYL,E" }, + { 0x007c, 0x00ff, ' ', 1, "LD A,IYH" }, + { 0x007d, 0x00ff, ' ', 1, "LD A,IYL" }, + { 0x0044, 0x00ff, ' ', 1, "LD B,IYH" }, + { 0x0045, 0x00ff, ' ', 1, "LD B,IYL" }, + { 0x004c, 0x00ff, ' ', 1, "LD C,IYH" }, + { 0x004d, 0x00ff, ' ', 1, "LD C,IYL" }, + { 0x0054, 0x00ff, ' ', 1, "LD D,IYH" }, + { 0x0055, 0x00ff, ' ', 1, "LD D,IYL" }, + { 0x005c, 0x00ff, ' ', 1, "LD E,IYH" }, + { 0x005d, 0x00ff, ' ', 1, "LD E,IYL" }, + // FD + { 0x0094, 0x00ff, ' ', 1, "SUB A,IYH" }, + { 0x0095, 0x00ff, ' ', 1, "SUB A,IYL" }, + { 0x009c, 0x00ff, ' ', 1, "SBC A,IYH" }, + { 0x009d, 0x00ff, ' ', 1, "SBC A,IYL" }, + { 0x00bc, 0x00ff, ' ', 1, "CP A,IYH" }, + { 0x00bd, 0x00ff, ' ', 1, "CP A,IYL" }, + // FD + { 0x0025, 0x00ff, ' ', 1, "DEC IYH" }, + { 0x002d, 0x00ff, ' ', 1, "DEC IYL" }, + { 0x0024, 0x00ff, ' ', 1, "INC IYH" }, + { 0x002c, 0x00ff, ' ', 1, "INC IYL" }, + // FD + { 0x00a4, 0x00ff, ' ', 1, "AND A,IYH" }, + { 0x00a5, 0x00ff, ' ', 1, "AND A,IYL" }, + { 0x00b4, 0x00ff, ' ', 1, "OR A,IYH" }, + { 0x00b5, 0x00ff, ' ', 1, "OR A,IYL" }, + { 0x00ac, 0x00ff, ' ', 1, "XOR A,IYH" }, + { 0x00ad, 0x00ff, ' ', 1, "XOR A,IYL" }, + { 0, 0, 0, 0, NULL } + }; + +cl_ez80::cl_ez80(struct cpu_entry *Itype, class cl_sim *asim): + cl_z80(Itype, asim) +{ +} + +int +cl_ez80::init(void) +{ + return cl_z80::init(); +} + +char * +cl_ez80::id_string(void) +{ + return ((char*)"EZ80"); +} + + +const char * +cl_ez80::get_disasm_info(t_addr addr, + int *ret_len, + int *ret_branch, + int *immed_offset, + struct dis_entry **dentry) +{ + const char *b = NULL; + uint code; + t_addr addr_org= addr; + int start_addr = addr; + int i; + int len= 0; + int immed_n = 0; + struct dis_entry *dis_e= NULL; + + code= rom->get(addr++); + switch (code) + { + case 0xed: + code= rom->get(addr++); + i= 0; + while ((code & disass_ez80_ed[i].mask) != disass_ez80_ed[i].code && + disass_ez80_ed[i].mnemonic) + i++; + dis_e= &disass_ez80_ed[i]; + b= dis_e->mnemonic; + if (b == NULL) + return cl_z80::get_disasm_info(addr_org, ret_len, ret_branch, immed_offset, dentry); + len+= dis_e->length+1; + switch (code) + { + case 0x32: case 0x55: + case 0x54: case 0x33: + case 0x02: case 0x12: case 0x22: + case 0x03: case 0x13: case 0x23: + immed_n= 2; + break; + } + break; + + case 0xdd: + code= rom->get(addr++); + i= 0; + while ((code & disass_ez80_dd[i].mask) != disass_ez80_dd[i].code && + disass_ez80_dd[i].mnemonic) + i++; + dis_e= &disass_ez80_dd[i]; + b= dis_e->mnemonic; + if (b == NULL) + return cl_z80::get_disasm_info(addr_org, ret_len, ret_branch, immed_offset, dentry); + len+= dis_e->length+1; + switch (code) + { + case 0x3f: case 0x3e: + case 0x37: case 0x31: + case 0x0f: case 0x1f: case 0x2f: + case 0x07: case 0x17: case 0x27: + case 0x26: case 0x2e: + immed_n= 2; + break; + } + break; + + case 0xfd: + code= rom->get(addr++); + i= 0; + while ((code & disass_ez80_fd[i].mask) != disass_ez80_fd[i].code && + disass_ez80_fd[i].mnemonic) + i++; + dis_e= &disass_ez80_fd[i]; + b= dis_e->mnemonic; + if (b == NULL) + return cl_z80::get_disasm_info(addr_org, ret_len, ret_branch, immed_offset, dentry); + len+= dis_e->length+1; + switch (code) + { + case 0x3e: case 0x3f: + case 0x31: case 0x37: + case 0x0f: case 0x1f: case 0x2f: + case 0x07: case 0x17: case 0x27: + case 0x26: case 0x2e: + immed_n= 2; + break; + } + break; + + default: + return cl_z80::get_disasm_info(addr_org, ret_len, ret_branch, immed_offset, dentry); + } + + if (ret_branch) + *ret_branch = dis_e->branch; + + if (immed_offset) { + if (immed_n > 0) + *immed_offset = immed_n; + else *immed_offset = (addr - start_addr); + } + + if (len == 0) + len = 1; + + if (ret_len) + *ret_len = len; + + if (dentry) + *dentry= dis_e; + + return b; +} + +int +cl_ez80::inst_ed_ez80(t_mem code) +{ + int8_t d; + + switch (code) + { + // ED + case 0x0f: // LD (HL),BC + store2(regs.HL, regs.BC); + return resGO; + case 0x1f: // LD (HL),DE + store2(regs.HL, regs.DE); + return resGO; + case 0x2f: // LD (HL),HL + store2(regs.HL, regs.HL); + return resGO; + case 0x37: // LD IX,(HL) + regs.IX= get2(regs.HL); + return resGO; + case 0x31: // LD IY,(HL) + regs.IY= get2(regs.HL); + return resGO; + case 0x07: // LD BC,(HL) + regs.BC= get2(regs.HL); + return resGO; + case 0x17: // LD DE,(HL) + regs.DE= get2(regs.HL); + return resGO; + case 0x27: // LD HL,(HL) + regs.HL= get2(regs.HL); + return resGO; + + // ED + case 0x32: // LEA IX,IX+d + d= fetch1(); + regs.IX= regs.IX + d; + return resGO; + case 0x55: // LEA IY,IX+d + d= fetch1(); + regs.IY= regs.IX + d; + return resGO; + case 0x54: // LEA IX,IY+d + d= fetch1(); + regs.IX= regs.IY + d; + return resGO; + case 0x33: // LEA IY,IY+d + d= fetch1(); + regs.IY= regs.IY + d; + return resGO; + + // ED + case 0x02: // LEA BC,IX+d + d= fetch1(); + regs.BC= regs.IX + d; + return resGO; + case 0x12: // LEA DE,IX+d + d= fetch1(); + regs.DE= regs.IX + d; + return resGO; + case 0x22: // LEA HL,IX+d + d= fetch1(); + regs.HL= regs.IX + d; + return resGO; + + // ED + case 0x03: // LEA BC,IY+d + d= fetch1(); + regs.BC= regs.IY + d; + return resGO; + case 0x13: // LEA DE,IY+d + d= fetch1(); + regs.DE= regs.IY + d; + return resGO; + case 0x23: // LEA HL,IY+d + d= fetch1(); + regs.HL= regs.IY + d; + return resGO; + + // ED + case 0x65: // PEA IX+d + d= fetch1(); + push2(regs.IX + d); + vc.wr+= 2; + return resGO; + case 0x66: // PEA IY+d + d= fetch1(); + push2(regs.IY + d); + vc.wr+= 2; + return resGO; + + default: // fall back to original Z80 + return inst_ed_(code); + } +} + +int +cl_ez80::inst_ed(t_mem prefix) +{ + t_mem code; + + if (fetch(&code)) + return (resBREAKPOINT); + + return inst_ed_ez80(code); +} + +int +cl_ez80::inst_dd_spec(t_mem code) +{ + int8_t d; + + switch (code) + { + // DD + case 0x3f: // LD (IX+d),IX + d= fetch1(); + store2(regs.IX+d, regs.IX); + return resGO; + case 0x3e: // LD (IX+d),IY + d= fetch1(); + store2(regs.IX+d, regs.IY); + return resGO; + + // DD + case 0x37: // LD IX,(IX+d) + d= fetch1(); + regs.IX= get2(regs.IX+d); + return resGO; + case 0x31: // LD IY,(IX+d) + d= fetch1(); + regs.IY= get2(regs.IX+d); + return resGO; + + // DD + case 0x0f: // LD (IX+d),BC + d= fetch1(); + store2(regs.IX+d, regs.BC); + return resGO; + case 0x1f: // LD (IX+d),DE + d= fetch1(); + store2(regs.IX+d, regs.DE); + return resGO; + case 0x2f: // LD (IX+d),HL + d= fetch1(); + store2(regs.IX+d, regs.HL); + return resGO; + + // DD + case 0x07: // LD BC,(IX+d) + d= fetch1(); + regs.BC= get2(regs.IX+d); + return resGO; + case 0x17: // LD DE,(IX+d) + d= fetch1(); + regs.DE= get2(regs.IX+d); + return resGO; + case 0x27: // LD HL,(IX+d) + d= fetch1(); + regs.HL= get2(regs.IX+d); + return resGO; + + // DD + case 0x64: // LD IXH,IXH + return resGO; + case 0x65: // LD IXH,IXL + regs.ix.h= regs.ix.l; + return resGO; + case 0x6c: // LD IXL,IXH + regs.ix.l= regs.ix.h; + return resGO; + case 0x6d: // LD IXL,IXL + return resGO; + + // DD + case 0x26: // LD IXH,n + d= fetch1(); + regs.ix.h= d; + return resGO; + case 0x2e: // LD IXL,n + d= fetch1(); + regs.ix.l= d; + return resGO; + + // DD + case 0x67: // LD,IXH,A + regs.ix.h= regs.raf.A; + return resGO; + case 0x60: // LD,IXH,B + regs.ix.h= regs.bc.h; + return resGO; + case 0x61: // LD,IXH,C + regs.ix.h= regs.bc.l; + return resGO; + case 0x62: // LD,IXH,D + regs.ix.h= regs.de.h; + return resGO; + case 0x63: // LD,IXH,E + regs.ix.h= regs.de.l; + return resGO; + + // DD + case 0x6f: // LD,IXL,A + regs.ix.l= regs.raf.A; + return resGO; + case 0x68: // LD,IXL,B + regs.ix.l= regs.bc.h; + return resGO; + case 0x69: // LD,IXL,C + regs.ix.l= regs.bc.l; + return resGO; + case 0x6a: // LD,IXL,D + regs.ix.l= regs.de.h; + return resGO; + case 0x6b: // LD,IXL,E + regs.ix.l= regs.de.l; + return resGO; + + // DD + case 0x7c: // LD A,IXH + regs.raf.A= regs.ix.h; + return resGO; + case 0x7d: // LD A,IXL + regs.raf.A= regs.ix.l; + return resGO; + case 0x44: // LD B,IXH + regs.bc.h= regs.ix.h; + return resGO; + case 0x45: // LD B,IXL + regs.bc.h= regs.ix.l; + return resGO; + case 0x4c: // LD C,IXH + regs.bc.l= regs.ix.h; + return resGO; + case 0x4d: // LD C,IXL + regs.bc.l= regs.ix.l; + return resGO; + case 0x54: // LD D,IXH + regs.de.h= regs.ix.h; + return resGO; + case 0x55: // LD D,IXL + regs.de.h= regs.ix.l; + return resGO; + case 0x5c: // LD E,IXH + regs.de.l= regs.ix.h; + return resGO; + case 0x5d: // LD E,IXL + regs.de.l= regs.ix.l; + return resGO; + + // DD + case 0x84: // ADD A,IXH + add_A_bytereg(regs.ix.h); + return resGO; + case 0x85: // ADD A,IXL + add_A_bytereg(regs.ix.l); + return resGO; + case 0x8c: // ADC A,IXH + adc_A_bytereg(regs.ix.h); + return resGO; + case 0x8d: // ADC A,IXL + adc_A_bytereg(regs.ix.l); + return resGO; + + // DD + case 0x94: // SUB A,IXH + sub_A_bytereg(regs.ix.h); + return resGO; + case 0x95: // SUB A,IXL + sub_A_bytereg(regs.ix.l); + return resGO; + case 0x9c: // SBC A,IXH + sbc_A_bytereg(regs.ix.h); + return resGO; + case 0x9d: // SBC A,IXL + sbc_A_bytereg(regs.ix.l); + return resGO; + case 0xbc: // SUB A,IXH + cp_bytereg(regs.ix.h); + return resGO; + case 0xbd: // SUB A,IXL + cp_bytereg(regs.ix.l); + return resGO; + + // DD + case 0x25: // DEC IXH + dec(regs.ix.h); + return resGO; + case 0x2d: // DEC IXL + dec(regs.ix.l); + return resGO; + case 0x24: // INC IXH + inc(regs.ix.h); + return resGO; + case 0x2c: // INC IXL + inc(regs.ix.l); + return resGO; + + // DD + case 0xa4: // AND A,IXH + and_A_bytereg(regs.ix.h); + return resGO; + case 0xa5: // AND A,IXL + and_A_bytereg(regs.ix.l); + return resGO; + case 0xb4: // OR A,IXH + or_A_bytereg(regs.ix.h); + return resGO; + case 0xb5: // OR A,IXL + or_A_bytereg(regs.ix.l); + return resGO; + case 0xac: // XOR A,IXH + xor_A_bytereg(regs.ix.h); + return resGO; + case 0xad: // XOR A,IXL + xor_A_bytereg(regs.ix.l); + return resGO; + + } + + return -1; +} + +int +cl_ez80::inst_fd_spec(t_mem code) +{ + int8_t d; + + switch (code) + { + // FD + case 0x3e: // LD (IY+d),IX + d= fetch1(); + store2(regs.IY+d, regs.IX); + return resGO; + case 0x3f: // LD (IY+d),IY + d= fetch1(); + store2(regs.IY+d, regs.IY); + return resGO; + + // FD + case 0x31: // LD IX,(IY+d) + d= fetch1(); + regs.IX= get2(regs.IY+d); + return resGO; + case 0x37: // LD IY,(IY+d) + d= fetch1(); + regs.IY= get2(regs.IY+d); + return resGO; + + // FD + case 0x0f: // LD (IY+d),BC + d= fetch1(); + store2(regs.IY+d, regs.BC); + return resGO; + case 0x1f: // LD (IY+d),DE + d= fetch1(); + store2(regs.IY+d, regs.DE); + return resGO; + case 0x2f: // LD (IY+d),HL + d= fetch1(); + store2(regs.IY+d, regs.HL); + return resGO; + + // FD + case 0x07: // LD BC,(IY+d) + d= fetch1(); + regs.BC= get2(regs.IY+d); + return resGO; + case 0x17: // LD DE,(IY+d) + d= fetch1(); + regs.DE= get2(regs.IY+d); + return resGO; + case 0x27: // LD HL,(IY+d) + d= fetch1(); + regs.HL= get2(regs.IY+d); + return resGO; + + // FD + case 0x64: // LD IYH,IYH + return resGO; + case 0x65: // LD IYH,IYL + regs.iy.h= regs.iy.l; + return resGO; + case 0x6c: // LD IYL,IYH + regs.iy.l= regs.iy.h; + return resGO; + case 0x6d: // LD IYL,IYL + return resGO; + + // FD + case 0x26: // LD IYH,n + d= fetch1(); + regs.iy.h= d; + return resGO; + case 0x2e: // LD IYL,n + d= fetch1(); + regs.iy.l= d; + return resGO; + + // FD + case 0x67: // LD,IYH,A + regs.iy.h= regs.raf.A; + return resGO; + case 0x60: // LD,IYH,B + regs.iy.h= regs.bc.h; + return resGO; + case 0x61: // LD,IYH,C + regs.iy.h= regs.bc.l; + return resGO; + case 0x62: // LD,IYH,D + regs.iy.h= regs.de.h; + return resGO; + case 0x63: // LD,IYH,E + regs.iy.h= regs.de.l; + return resGO; + + // FD + case 0x6f: // LD,IYL,A + regs.iy.l= regs.raf.A; + return resGO; + case 0x68: // LD,IYL,B + regs.iy.l= regs.bc.h; + return resGO; + case 0x69: // LD,IYL,C + regs.iy.l= regs.bc.l; + return resGO; + case 0x6a: // LD,IYL,D + regs.iy.l= regs.de.h; + return resGO; + case 0x6b: // LD,IYL,E + regs.iy.l= regs.de.l; + return resGO; + + // FD + case 0x7c: // LD A,IYH + regs.raf.A= regs.iy.h; + return resGO; + case 0x7d: // LD A,IYL + regs.raf.A= regs.iy.l; + return resGO; + case 0x44: // LD B,IYH + regs.bc.h= regs.iy.h; + return resGO; + case 0x45: // LD B,IYL + regs.bc.h= regs.iy.l; + return resGO; + case 0x4c: // LD C,IYH + regs.bc.l= regs.iy.h; + return resGO; + case 0x4d: // LD C,IYL + regs.bc.l= regs.iy.l; + return resGO; + case 0x54: // LD D,IYH + regs.de.h= regs.iy.h; + return resGO; + case 0x55: // LD D,IYL + regs.de.h= regs.iy.l; + return resGO; + case 0x5c: // LD E,IYH + regs.de.l= regs.iy.h; + return resGO; + case 0x5d: // LD E,IYL + regs.de.l= regs.iy.l; + return resGO; + + // FD + case 0x84: // ADD A,IYH + add_A_bytereg(regs.iy.h); + return resGO; + case 0x85: // ADD A,IYL + add_A_bytereg(regs.iy.l); + return resGO; + case 0x8c: // ADC A,IYH + adc_A_bytereg(regs.iy.h); + return resGO; + case 0x8d: // ADC A,IYL + adc_A_bytereg(regs.iy.l); + return resGO; + + // FD + case 0x94: // SUB A,IYH + sub_A_bytereg(regs.iy.h); + return resGO; + case 0x95: // SUB A,IYL + sub_A_bytereg(regs.iy.l); + return resGO; + case 0x9c: // SBC A,IYH + sbc_A_bytereg(regs.iy.h); + return resGO; + case 0x9d: // SBC A,IYL + sbc_A_bytereg(regs.iy.l); + return resGO; + case 0xbc: // SUB A,IYH + cp_bytereg(regs.iy.h); + return resGO; + case 0xbd: // SUB A,IYL + cp_bytereg(regs.iy.l); + return resGO; + + // FD + case 0x25: // DEC IYH + dec(regs.iy.h); + return resGO; + case 0x2d: // DEC IYL + dec(regs.iy.l); + return resGO; + case 0x24: // INC IYH + inc(regs.iy.h); + return resGO; + case 0x2c: // INC IYL + inc(regs.iy.l); + return resGO; + + // DD + case 0xa4: // AND A,IYH + and_A_bytereg(regs.iy.h); + return resGO; + case 0xa5: // AND A,IYL + and_A_bytereg(regs.iy.l); + return resGO; + case 0xb4: // OR A,IYH + or_A_bytereg(regs.iy.h); + return resGO; + case 0xb5: // OR A,IYL + or_A_bytereg(regs.iy.l); + return resGO; + case 0xac: // XOR A,IYH + xor_A_bytereg(regs.iy.h); + return resGO; + case 0xad: // XOR A,IYL + xor_A_bytereg(regs.iy.l); + return resGO; + + } + + return -1; +} + + +/* End of z80.src/ez80.cc */ diff --git a/sim/ucsim/z80.src/ez80cl.h b/sim/ucsim/z80.src/ez80cl.h new file mode 100644 index 0000000..da3a4c8 --- /dev/null +++ b/sim/ucsim/z80.src/ez80cl.h @@ -0,0 +1,54 @@ +/* + * Simulator of microcontrollers (ez80cl.h) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#ifndef EZ80CL_HEADER +#define EZ80CL_HEADER + +#include "z80cl.h" + +class cl_ez80: public cl_z80 +{ + public: + public: + cl_ez80(struct cpu_entry *Itype, class cl_sim *asim); + virtual int init(void); + virtual char *id_string(void); + virtual const char *get_disasm_info(t_addr addr, + int *ret_len, + int *ret_branch, + int *immed_offset, + struct dis_entry **dentry); + + virtual int inst_ed_ez80(t_mem code); + virtual int inst_ed(t_mem prefix); + virtual int inst_dd_spec(t_mem code); + virtual int inst_fd_spec(t_mem code); +}; + +#endif + +/* End of z80.src/ez80cl.h */ diff --git a/sim/ucsim/z80.src/glob.cc b/sim/ucsim/z80.src/glob.cc new file mode 100644 index 0000000..0080f03 --- /dev/null +++ b/sim/ucsim/z80.src/glob.cc @@ -0,0 +1,1429 @@ +/* + * Simulator of microcontrollers (glob.cc) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ +/* Modified for rabbit 2000 support by Leland Morrison 2011 */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#include <stdio.h> + +#include "stypes.h" + +#ifndef R2K +#define DISASS_NAME(X) disass_z80##X +#else +#define DISASS_NAME(X) disass_r2k##X +#endif + +/* +%d - signed compl.,byte jump +%w - 2-byte jump or imm. value +%b - byte imm. value + */ +/* uint code, mask; char branch; uchar length; char *mnemonic; */ + +struct dis_entry +#ifndef R2K +disass_z80 +#else +disass_r2k +#endif + []= { + { 0x0000, 0x00ff, ' ', 1, "NOP" }, + { 0x0001, 0x00ff, ' ', 3, "LD BC,%w" }, + { 0x0002, 0x00ff, ' ', 1, "LD (BC),A" }, + { 0x0003, 0x00ff, ' ', 1, "INC BC" }, + { 0x0004, 0x00ff, ' ', 1, "INC B" }, + { 0x0005, 0x00ff, ' ', 1, "DEC B" }, + { 0x0006, 0x00ff, ' ', 2, "LD b,%b" }, + { 0x0007, 0x00ff, ' ', 1, "RLCA" }, + + { 0x0008, 0x00ff, ' ', 1, "EX AF,AF'" }, + { 0x0009, 0x00ff, ' ', 1, "ADD HL,BC" }, + { 0x000a, 0x00ff, ' ', 1, "LD A,(BC)" }, + { 0x000b, 0x00ff, ' ', 1, "DEC BC" }, + { 0x000c, 0x00ff, ' ', 1, "INC C" }, + { 0x000d, 0x00ff, ' ', 1, "DEC C" }, + { 0x000e, 0x00ff, ' ', 2, "LD C,%b" }, + { 0x000f, 0x00ff, ' ', 1, "RRCA" }, + + { 0x0010, 0x00ff, 'R', 2, "DJNZ %d" }, + { 0x0011, 0x00ff, ' ', 3, "LD DE,%w" }, + { 0x0012, 0x00ff, ' ', 1, "LD (DE),A" }, + { 0x0013, 0x00ff, ' ', 1, "INC DE" }, + { 0x0014, 0x00ff, ' ', 1, "INC D" }, + { 0x0015, 0x00ff, ' ', 1, "DEC D" }, + { 0x0016, 0x00ff, ' ', 2, "LD D,%b" }, + { 0x0017, 0x00ff, ' ', 1, "RLA" }, + + { 0x0018, 0x00ff, 'R', 2, "JR %d" }, + { 0x0019, 0x00ff, ' ', 3, "ADD HL,DE" }, + { 0x001a, 0x00ff, ' ', 1, "LD A,(DE)" }, + { 0x001b, 0x00ff, ' ', 1, "DEC DE" }, + { 0x001c, 0x00ff, ' ', 1, "INC E" }, + { 0x001d, 0x00ff, ' ', 1, "DEC E" }, + { 0x001e, 0x00ff, ' ', 2, "LD E,%b" }, + { 0x001f, 0x00ff, ' ', 1, "RRA" }, + + { 0x0020, 0x00ff, 'R', 2, "JR NZ,%d" }, + { 0x0021, 0x00ff, ' ', 3, "LD HL,%w" }, + { 0x0022, 0x00ff, ' ', 3, "LD (%w),HL" }, + { 0x0023, 0x00ff, ' ', 1, "INC HL" }, + { 0x0024, 0x00ff, ' ', 1, "INC H" }, + { 0x0025, 0x00ff, ' ', 1, "DEC H" }, + { 0x0026, 0x00ff, ' ', 2, "LD H,%b" }, +#ifndef R2K + { 0x0027, 0x00ff, ' ', 1, "DAA" }, +#else + { 0x0027, 0x00ff, ' ', 2, "ADD SP,%d" }, +#endif + + { 0x0028, 0x00ff, 'R', 2, "JR Z,%d" }, + { 0x0029, 0x00ff, ' ', 1, "ADD HL,HL" }, + { 0x002a, 0x00ff, ' ', 3, "LD HL,(%w)" }, + { 0x002b, 0x00ff, ' ', 1, "DEC HL" }, + { 0x002c, 0x00ff, ' ', 1, "INC L" }, + { 0x002d, 0x00ff, ' ', 1, "DEC L" }, + { 0x002e, 0x00ff, ' ', 2, "LD L, %b" }, + { 0x002f, 0x00ff, ' ', 1, "CPL" }, + + { 0x0030, 0x00ff, 'R', 2, "JR NC,%d" }, + { 0x0031, 0x00ff, ' ', 3, "LD SP,%w" }, + { 0x0032, 0x00ff, ' ', 3, "LD (%w),A" }, + { 0x0033, 0x00ff, ' ', 1, "INC SP" }, + { 0x0034, 0x00ff, ' ', 1, "INC (HL)" }, + { 0x0035, 0x00ff, ' ', 1, "DEC (HL)" }, + { 0x0036, 0x00ff, ' ', 2, "LD (HL),%b" }, + { 0x0037, 0x00ff, ' ', 1, "SCF" }, + + { 0x0038, 0x00ff, 'R', 2, "JR C,%d" }, + { 0x0039, 0x00ff, ' ', 1, "ADD HL,SP" }, + { 0x003a, 0x00ff, ' ', 3, "LD A,(%w)" }, + { 0x003b, 0x00ff, ' ', 1, "DEC SP" }, + { 0x003c, 0x00ff, ' ', 1, "INC A" }, + { 0x003d, 0x00ff, ' ', 1, "DEC A" }, + { 0x003e, 0x00ff, ' ', 2, "LD A,%b" }, + { 0x003f, 0x00ff, ' ', 1, "CCF" }, + + { 0x0040, 0x00ff, ' ', 1, "LD B,B" }, + { 0x0041, 0x00ff, ' ', 1, "LD B,C" }, + { 0x0042, 0x00ff, ' ', 1, "LD B,D" }, + { 0x0043, 0x00ff, ' ', 1, "LD B,E" }, + { 0x0044, 0x00ff, ' ', 1, "LD B,H" }, + { 0x0045, 0x00ff, ' ', 1, "LD B,L" }, + { 0x0046, 0x00ff, ' ', 1, "LD B,(HL)" }, + { 0x0047, 0x00ff, ' ', 1, "LD B,a" }, + + { 0x0048, 0x00ff, ' ', 1, "LD C,B" }, + { 0x0049, 0x00ff, ' ', 1, "LD C,C" }, + { 0x004a, 0x00ff, ' ', 1, "LD C,D" }, + { 0x004b, 0x00ff, ' ', 1, "LD C,E" }, + { 0x004c, 0x00ff, ' ', 1, "LD C,H" }, + { 0x004d, 0x00ff, ' ', 1, "LD C,L" }, + { 0x004e, 0x00ff, ' ', 1, "LD C,(HL)" }, + { 0x004f, 0x00ff, ' ', 1, "LD C,A" }, + + { 0x0050, 0x00ff, ' ', 1, "LD D,B" }, + { 0x0051, 0x00ff, ' ', 1, "LD D,C" }, + { 0x0052, 0x00ff, ' ', 1, "LD D,D" }, + { 0x0053, 0x00ff, ' ', 1, "LD D,E" }, + { 0x0054, 0x00ff, ' ', 1, "LD D,H" }, + { 0x0055, 0x00ff, ' ', 1, "LD D,L" }, + { 0x0056, 0x00ff, ' ', 1, "LD D,(HL)" }, + { 0x0057, 0x00ff, ' ', 1, "LD D,A" }, + + { 0x0058, 0x00ff, ' ', 1, "LD E,B" }, + { 0x0059, 0x00ff, ' ', 1, "LD E,C" }, + { 0x005a, 0x00ff, ' ', 1, "LD E,D" }, + { 0x005b, 0x00ff, ' ', 1, "LD E,E" }, + { 0x005c, 0x00ff, ' ', 1, "LD E,H" }, + { 0x005d, 0x00ff, ' ', 1, "LD E,L" }, + { 0x005e, 0x00ff, ' ', 1, "LD E,(HL)" }, + { 0x005f, 0x00ff, ' ', 1, "LD E,A" }, + + { 0x0060, 0x00ff, ' ', 1, "LD H,B" }, + { 0x0061, 0x00ff, ' ', 1, "LD H,C" }, + { 0x0062, 0x00ff, ' ', 1, "LD H,D" }, + { 0x0063, 0x00ff, ' ', 1, "LD H,E" }, + { 0x0064, 0x00ff, ' ', 1, "LD H,H" }, + { 0x0065, 0x00ff, ' ', 1, "LD H,L" }, + { 0x0066, 0x00ff, ' ', 1, "LD H,(HL)" }, + { 0x0067, 0x00ff, ' ', 1, "LD H,A" }, + + { 0x0068, 0x00ff, ' ', 1, "LD L,B" }, + { 0x0069, 0x00ff, ' ', 1, "LD L,C" }, + { 0x006a, 0x00ff, ' ', 1, "LD L,D" }, + { 0x006b, 0x00ff, ' ', 1, "LD L,E" }, + { 0x006c, 0x00ff, ' ', 1, "LD L,H" }, + { 0x006d, 0x00ff, ' ', 1, "LD L,L" }, + { 0x006e, 0x00ff, ' ', 1, "LD L,(HL)" }, + { 0x006f, 0x00ff, ' ', 1, "LD L,A" }, + + { 0x0070, 0x00ff, ' ', 1, "LD (HL),B" }, + { 0x0071, 0x00ff, ' ', 1, "LD (HL),C" }, + { 0x0072, 0x00ff, ' ', 1, "LD (HL),D" }, + { 0x0073, 0x00ff, ' ', 1, "LD (HL),E" }, + { 0x0074, 0x00ff, ' ', 1, "LD (HL),H" }, + { 0x0075, 0x00ff, ' ', 1, "LD (HL),L" }, +#ifndef R2K + { 0x0076, 0x00ff, ' ', 1, "HALT" }, +#else + { 0x0076, 0x00ff, ' ', 1, "ALTD" }, +#endif + { 0x0077, 0x00ff, ' ', 1, "LD (HL),A" }, + + { 0x0078, 0x00ff, ' ', 1, "LD A,B" }, + { 0x0079, 0x00ff, ' ', 1, "LD A,C" }, + { 0x007a, 0x00ff, ' ', 1, "LD A,D" }, + { 0x007b, 0x00ff, ' ', 1, "LD A,E" }, + { 0x007c, 0x00ff, ' ', 1, "LD A,H" }, + { 0x007d, 0x00ff, ' ', 1, "LD A,L" }, + { 0x007e, 0x00ff, ' ', 1, "LD A,(HL)" }, + { 0x007f, 0x00ff, ' ', 1, "LD A,A" }, + + { 0x0080, 0x00ff, ' ', 1, "ADD A,B" }, + { 0x0081, 0x00ff, ' ', 1, "ADD A,C" }, + { 0x0082, 0x00ff, ' ', 1, "ADD A,D" }, + { 0x0083, 0x00ff, ' ', 1, "ADD A,E" }, + { 0x0084, 0x00ff, ' ', 1, "ADD A,H" }, + { 0x0085, 0x00ff, ' ', 1, "ADD A,L" }, + { 0x0086, 0x00ff, ' ', 1, "ADD A,(HL)" }, + { 0x0087, 0x00ff, ' ', 1, "ADD A,A" }, + + { 0x0088, 0x00ff, ' ', 1, "ADC A,B" }, + { 0x0089, 0x00ff, ' ', 1, "ADC A,C" }, + { 0x008a, 0x00ff, ' ', 1, "ADC A,D" }, + { 0x008b, 0x00ff, ' ', 1, "ADC A,E" }, + { 0x008c, 0x00ff, ' ', 1, "ADC A,H" }, + { 0x008d, 0x00ff, ' ', 1, "ADC A,L" }, + { 0x008e, 0x00ff, ' ', 1, "ADC A,(HL)" }, + { 0x008f, 0x00ff, ' ', 1, "ADC A,A" }, + + { 0x0090, 0x00ff, ' ', 1, "SUB A,B"}, + { 0x0091, 0x00ff, ' ', 1, "SUB A,C"}, + { 0x0092, 0x00ff, ' ', 1, "SUB A,D"}, + { 0x0093, 0x00ff, ' ', 1, "SUB A,E"}, + { 0x0094, 0x00ff, ' ', 1, "SUB A,H"}, + { 0x0095, 0x00ff, ' ', 1, "SUB A,L"}, + { 0x0096, 0x00ff, ' ', 1, "SUB A,(HL)"}, + { 0x0097, 0x00ff, ' ', 1, "SUB A,A"}, + + { 0x0098, 0x00ff, ' ', 1, "SBC A,B" }, + { 0x0099, 0x00ff, ' ', 1, "SBC A,C" }, + { 0x009a, 0x00ff, ' ', 1, "SBC A,D" }, + { 0x009b, 0x00ff, ' ', 1, "SBC A,E" }, + { 0x009c, 0x00ff, ' ', 1, "SBC A,H" }, + { 0x009d, 0x00ff, ' ', 1, "SBC A,L" }, + { 0x009e, 0x00ff, ' ', 1, "SBC A,(HL)" }, + { 0x009f, 0x00ff, ' ', 1, "SBC A,A" }, + + { 0x00a0, 0x00ff, ' ', 1, "AND B" }, + { 0x00a1, 0x00ff, ' ', 1, "AND C" }, + { 0x00a2, 0x00ff, ' ', 1, "AND D" }, + { 0x00a3, 0x00ff, ' ', 1, "AND E" }, + { 0x00a4, 0x00ff, ' ', 1, "AND H" }, + { 0x00a5, 0x00ff, ' ', 1, "AND L" }, + { 0x00a6, 0x00ff, ' ', 1, "AND (HL)" }, + { 0x00a7, 0x00ff, ' ', 1, "AND A" }, + + { 0x00a8, 0x00ff, ' ', 1, "XOR B" }, + { 0x00a9, 0x00ff, ' ', 1, "XOR C" }, + { 0x00aa, 0x00ff, ' ', 1, "XOR D" }, + { 0x00ab, 0x00ff, ' ', 1, "XOR E" }, + { 0x00ac, 0x00ff, ' ', 1, "XOR H" }, + { 0x00ad, 0x00ff, ' ', 1, "XOR L" }, + { 0x00ae, 0x00ff, ' ', 1, "XOR (HL)" }, + { 0x00af, 0x00ff, ' ', 1, "XOR A" }, + + { 0x00b0, 0x00ff, ' ', 1, "OR B" }, + { 0x00b1, 0x00ff, ' ', 1, "OR C" }, + { 0x00b2, 0x00ff, ' ', 1, "OR D" }, + { 0x00b3, 0x00ff, ' ', 1, "OR E" }, + { 0x00b4, 0x00ff, ' ', 1, "OR H" }, + { 0x00b5, 0x00ff, ' ', 1, "OR L" }, + { 0x00b6, 0x00ff, ' ', 1, "OR (HL)" }, + { 0x00b7, 0x00ff, ' ', 1, "OR A" }, + + { 0x00b8, 0x00ff, ' ', 1, "CP B" }, + { 0x00b9, 0x00ff, ' ', 1, "CP C" }, + { 0x00ba, 0x00ff, ' ', 1, "CP D" }, + { 0x00bb, 0x00ff, ' ', 1, "CP E" }, + { 0x00bc, 0x00ff, ' ', 1, "CP H" }, + { 0x00bd, 0x00ff, ' ', 1, "CP L" }, + { 0x00be, 0x00ff, ' ', 1, "CP (HL)" }, + { 0x00bf, 0x00ff, ' ', 1, "CP A" }, + + { 0x00c0, 0x00ff, ' ', 1, "RET NZ" }, + { 0x00c1, 0x00ff, ' ', 1, "POP BC" }, + { 0x00c2, 0x00ff, 'A', 3, "JP NZ, %w" }, + { 0x00c3, 0x00ff, 'A', 3, "JP %w" }, +#ifndef R2K + { 0x00c4, 0x00ff, 'l', 3, "CALL NZ,%w", true }, +#else + { 0x00c4, 0x00ff, ' ', 2, "LD HL,(SP+%d)" }, +#endif + { 0x00c5, 0x00ff, ' ', 1, "PUSH BC" }, + { 0x00c6, 0x00ff, ' ', 2, "ADD A,%b" }, +#ifndef R2K + { 0x00c7, 0x00ff, ' ', 1, "RST 0", true }, +#else + { 0x00c7, 0x00ff, ' ', 4, "LJP %w,%b" }, +#endif + + { 0x00c8, 0x00ff, ' ', 1, "RET Z" }, + { 0x00c9, 0x00ff, ' ', 1, "RET" }, + { 0x00ca, 0x00ff, 'A', 3, "JP Z,%w" }, + { 0x00cb, 0x00ff, ' ', 2, "?cb?" }, /* ESC code to lots of op-codes, all 2-byte */ + +#ifndef R2K + { 0x00cc, 0x00ff, 'l', 3, "CALL Z,%w", true }, +#else + { 0x00cc, 0x00ff, 'l', 1, "BOOL HL" }, +#endif + { 0x00cd, 0x00ff, 'l', 3, "CALL %w", true }, + { 0x00ce, 0x00ff, ' ', 2, "ADC A,%b" }, +#ifndef R2K + { 0x00cf, 0x00ff, ' ', 1, "RST 8", true }, +#else + { 0x00cf, 0x00ff, ' ', 4, "LCALL %w,%b", true }, +#endif + + { 0x00d0, 0x00ff, ' ', 1, "RET NC" }, + { 0x00d1, 0x00ff, ' ', 1, "POP DE" }, + { 0x00d2, 0x00ff, 'A', 3, "JP NC,%w" }, +#ifndef R2K + { 0x00d3, 0x00ff, ' ', 2, "OUT (%b),A" }, + { 0x00d4, 0x00ff, 'l', 3, "CALL NC,%w", true }, +#else + { 0x00d3, 0x00ff, ' ', 1, "IOI" }, + { 0x00d4, 0x00ff, 'l', 2, "LD (SP+%d),HL" }, +#endif + { 0x00d5, 0x00ff, ' ', 1, "PUSH DE" }, + { 0x00d6, 0x00ff, ' ', 2, "sub %b" }, + { 0x00d7, 0x00ff, ' ', 1, "RST 10H", true }, + + { 0x00d8, 0x00ff, ' ', 1, "RET C" }, + { 0x00d9, 0x00ff, ' ', 1, "EXX" }, + { 0x00da, 0x00ff, 'A', 3, "JP C,%w" }, +#ifndef R2K + { 0x00db, 0x00ff, ' ', 2, "IN A,(%b)" }, + { 0x00dc, 0x00ff, 'l', 3, "CALL C,%w", true }, +#else + { 0x00db, 0x00ff, ' ', 1, "IOE" }, + { 0x00dc, 0x00ff, 'l', 1, "AND HL,DE" }, +#endif + { 0x00dd, 0x00ff, ' ', 2, "?dd?" }, /* 0xdd - ESC codes,about 284, vary lengths, IX centric */ + { 0x00de, 0x00ff, ' ', 2, "SBC A,%b" }, + { 0x00df, 0x00ff, ' ', 1, "RST 18H", true }, + + { 0x00e0, 0x00ff, ' ', 1, "RET PO" }, + { 0x00e1, 0x00ff, ' ', 1, "POP HL" }, + { 0x00e2, 0x00ff, 'A', 3, "JP PO,%w" }, +#ifndef R2K + { 0x00e3, 0x00ff, ' ', 1, "EX (SP),HL" }, + { 0x00e4, 0x00ff, 'l', 3, "CALL PO,%w", true }, +#else + { 0x00e3, 0x00ff, ' ', 1, "EX DE',HL" }, + { 0x00e4, 0x00ff, 'l', 2, "LD HL,(IX+%d)" }, +#endif + { 0x00e5, 0x00ff, ' ', 1, "PUSH HL" }, + { 0x00e6, 0x00ff, ' ', 2, "AND %b" }, + { 0x00e7, 0x00ff, ' ', 1, "RST 20H", true }, + + { 0x00e8, 0x00ff, ' ', 1, "RET PE" }, + { 0x00e9, 0x00ff, 'A', 1, "JP (HL)" }, + { 0x00ea, 0x00ff, 'A', 3, "JP PE,%w" }, + { 0x00eb, 0x00ff, ' ', 1, "EX DE,HL" }, +#ifndef R2K + { 0x00ec, 0x00ff, 'l', 3, "CALL PE, %w", true }, + { 0x00ed, 0x00ff, ' ', 2, "?ed?" }, /* ESC code to about 80 opcodes of various lengths */ +#else + { 0x00ec, 0x00ff, 'l', 1, "OR HL,DE" }, + { 0x00ed, 0x00ff, ' ', 1, "?ed?" }, /* ESC code to about 80 opcodes of various lengths */ +#endif + + { 0x00ee, 0x00ff, ' ', 2, "XOR %b" }, + { 0x00ef, 0x00ff, ' ', 1, "RST 28H", true }, + + { 0x00f0, 0x00ff, ' ', 1, "RET P" }, + { 0x00f1, 0x00ff, ' ', 1, "POP AF" }, + { 0x00f2, 0x00ff, 'A', 3, "JP P,%w" }, +#ifndef R2K + { 0x00f3, 0x00ff, ' ', 1, "DI" }, + { 0x00f4, 0x00ff, 'l', 3, "CALL P,%w", true }, +#else + { 0x00f3, 0x00ff, ' ', 1, "RL DE" }, + { 0x00f4, 0x00ff, 'l', 2, "LD (IX+%d),HL" }, +#endif + { 0x00f5, 0x00ff, ' ', 1, "PUSH AF" }, + { 0x00f6, 0x00ff, ' ', 2, "OR %b" }, +#ifndef R2K + { 0x00f7, 0x00ff, ' ', 1, "RST 30H", true }, +#else + { 0x00f7, 0x00ff, ' ', 1, "MUL" }, +#endif + { 0x00f8, 0x00ff, ' ', 1, "RET M" }, + { 0x00f9, 0x00ff, ' ', 1, "LD SP,HL" }, + { 0x00fa, 0x00ff, ' ', 3, "JP M,%w" }, +#ifndef R2K + { 0x00fb, 0x00ff, ' ', 1, "EI" }, + { 0x00fc, 0x00ff, 'l', 3, "CALL M,%w", true }, +#else + { 0x00fb, 0x00ff, ' ', 1, "RR DE" }, + { 0x00fc, 0x00ff, 'l', 1, "RR HL" }, +#endif + { 0x00fd, 0x00ff, ' ', 1, "?fd?" }, /* ESC codes,about 284, vary lengths, IY centric */ + { 0x00fe, 0x00ff, ' ', 2, "CP %b" }, + { 0x00ff, 0x00ff, ' ', 1, "RST 38H", true }, + + { 0, 0, 0, 0, NULL } +}; + + +#ifndef R2K +struct dis_entry disass_z80_ed[]= { + { 0x0000, 0x00ff, ' ', 1, "RLC B" }, + { 0x0040, 0x00ff, ' ', 1, "IN B,(C)" }, + { 0x0041, 0x00ff, ' ', 1, "OUT (C),B" }, + { 0x0042, 0x00ff, ' ', 1, "SBC HL,BC" }, + { 0x0043, 0x00ff, ' ', 1, "LD (nnnn),BC" }, + { 0x0044, 0x00ff, ' ', 1, "NEG" }, + { 0x0045, 0x00ff, ' ', 1, "RETN" }, + { 0x0046, 0x00ff, ' ', 1, "IM 0" }, + { 0x0047, 0x00ff, ' ', 1, "LD IV,A" }, + { 0x0048, 0x00ff, ' ', 1, "IN C,(C)" }, + { 0x0049, 0x00ff, ' ', 1, "OUT (C),C" }, + { 0x004A, 0x00ff, ' ', 1, "ADC HL,BC" }, + { 0x004B, 0x00ff, ' ', 1, "LD BC,(nnnn)" }, + { 0x004D, 0x00ff, ' ', 1, "RETI" }, + { 0x004F, 0x00ff, ' ', 1, "LD R,A" }, + { 0x0050, 0x00ff, ' ', 1, "IN D,(C)" }, + { 0x0051, 0x00ff, ' ', 1, "OUT (C),D" }, + { 0x0052, 0x00ff, ' ', 1, "SBC HL,DE" }, + { 0x0053, 0x00ff, ' ', 1, "LD (nnnn),DE" }, + { 0x0056, 0x00ff, ' ', 1, "IM 1" }, + { 0x0057, 0x00ff, ' ', 1, "LD A,IV" }, + { 0x0058, 0x00ff, ' ', 1, "IN E,(C)" }, + { 0x0059, 0x00ff, ' ', 1, "OUT (C),E" }, + { 0x005A, 0x00ff, ' ', 1, "ADC HL,DE" }, + { 0x005B, 0x00ff, ' ', 1, "LD DE,(nnnn)" }, + { 0x005E, 0x00ff, ' ', 1, "IM 2" }, + { 0x005F, 0x00ff, ' ', 1, "LD A,R" }, + { 0x0060, 0x00ff, ' ', 1, "IN H,(C)" }, + { 0x0061, 0x00ff, ' ', 1, "OUT (C),H" }, + { 0x0062, 0x00ff, ' ', 1, "SBC HL,HL" }, + { 0x0063, 0x00ff, ' ', 1, "LD (nnnn),HL" }, + { 0x0067, 0x00ff, ' ', 1, "RRD" }, + { 0x0068, 0x00ff, ' ', 1, "IN L,(C)" }, + { 0x0069, 0x00ff, ' ', 1, "OUT (C),L" }, + { 0x006A, 0x00ff, ' ', 1, "ADC HL,HL" }, + { 0x006B, 0x00ff, ' ', 1, "LD HL,(nnnn)" }, + { 0x006F, 0x00ff, ' ', 1, "RLD" }, + { 0x0070, 0x00ff, ' ', 1, "IN (C)" }, + { 0x0071, 0x00ff, ' ', 1, " OUT (C),0" }, + { 0x0072, 0x00ff, ' ', 1, "SBC HL,SP" }, + { 0x0073, 0x00ff, ' ', 1, "LD (nnnn),SP" }, + { 0x0078, 0x00ff, ' ', 1, "IN A,(C)" }, + { 0x0079, 0x00ff, ' ', 1, "OUT (C),A" }, + { 0x007A, 0x00ff, ' ', 1, "ADC HL,SP" }, + { 0x007B, 0x00ff, ' ', 1, "LD SP,(nnnn)" }, + { 0x00A0, 0x00ff, ' ', 1, "LDI" }, + { 0x00A1, 0x00ff, ' ', 1, "CPI" }, + { 0x00A2, 0x00ff, ' ', 1, "INI" }, + { 0x00A3, 0x00ff, ' ', 1, "OUTI" }, + { 0x00A8, 0x00ff, ' ', 1, "LDD" }, + { 0x00A9, 0x00ff, ' ', 1, "CPD" }, + { 0x00AA, 0x00ff, ' ', 1, "IND" }, + { 0x00AB, 0x00ff, ' ', 1, "OUTD" }, + { 0x00B0, 0x00ff, ' ', 1, "LDIR" }, + { 0x00B1, 0x00ff, ' ', 1, "CPIR" }, + { 0x00B2, 0x00ff, ' ', 1, "INIR" }, + { 0x00B3, 0x00ff, ' ', 1, "OTIR" }, + { 0x00B8, 0x00ff, ' ', 1, "LDDR" }, + { 0x00B9, 0x00ff, ' ', 1, "CPDR" }, + { 0x00BA, 0x00ff, ' ', 1, "INDR" }, + { 0x00BB, 0x00ff, ' ', 1, "OTDR" }, + { 0, 0, 0, 0, NULL } +}; +#endif + +#ifdef R2K +struct dis_entry disass_r2k_ed[]= { +#if 0 /* oops, rabbit 4000 only */ + { 0x0000, 0x00ff, ' ', 2, "CBM %d" }, + { 0x0002, 0x00ff, ' ', 1, "SBOX A" }, + { 0x0010, 0x00ff, 'R', 2, "DWJNZ %d" }, + + { 0x0040, 0x00ff, ' ', 1, "LD HTR,A" }, +#endif + { 0x0041, 0x00ff, ' ', 1, "LD BC',DE" }, + { 0x0042, 0x00ff, ' ', 1, "SBC HL,BC" }, + { 0x0043, 0x00ff, ' ', 3, "LD (%w),BC" }, + { 0x0044, 0x00ff, ' ', 1, "NEG" }, + { 0x0045, 0x00ff, ' ', 1, "LRET" }, + { 0x0046, 0x00ff, ' ', 1, "IPSET 0" }, + { 0x0047, 0x00ff, ' ', 1, "LD EIR,A" }, + + { 0x0048, 0x00ff, ' ', 1, "CP HL,DE" }, + { 0x0049, 0x00ff, ' ', 1, "LD BC',BC" }, + { 0x004A, 0x00ff, ' ', 1, "ADC HL,BC" }, + { 0x004B, 0x00ff, ' ', 3, "LD BC,(%w)" }, + { 0x004C, 0x00ff, ' ', 1, "TEST BC" }, + { 0x004D, 0x00ff, ' ', 1, "RETI" }, + { 0x004E, 0x00ff, ' ', 1, "IPSET 2" }, + { 0x004F, 0x00ff, ' ', 1, "LD IIR,A" }, + + /* { 0x0050, 0x00ff, ' ', 1, "LD A,HTR" }, * rabbit 4000 only */ + { 0x0051, 0x00ff, ' ', 1, "LD DE',DE" }, + { 0x0052, 0x00ff, ' ', 1, "SBC HL,DE" }, + { 0x0053, 0x00ff, ' ', 3, "LD (%w),DE" }, + { 0x0056, 0x00ff, ' ', 1, "IPSET 1" }, + { 0x0057, 0x00ff, ' ', 1, "LD A,EIR" }, + + { 0x0059, 0x00ff, ' ', 1, "LD DE',BC" }, + { 0x005A, 0x00ff, ' ', 1, "ADC HL,DE" }, + { 0x005B, 0x00ff, ' ', 3, "LD DE,(%w)" }, + { 0x005D, 0x00ff, ' ', 1, "IPRES" }, + { 0x005E, 0x00ff, ' ', 1, "IPSET 3" }, + { 0x005F, 0x00ff, ' ', 1, "LD A,IIR" }, + + { 0x0061, 0x00ff, ' ', 1, "LD HL',DE" }, + { 0x0062, 0x00ff, ' ', 1, "SBC HL,HL" }, + { 0x0063, 0x00ff, ' ', 3, "LD (nnnn),HL" }, + { 0x0067, 0x00ff, ' ', 1, "LD XPC,A" }, + + { 0x006A, 0x00ff, ' ', 1, "ADC HL,HL" }, + { 0x006B, 0x00ff, ' ', 3, "LD HL,(nnnn)" }, + + { 0x0072, 0x00ff, ' ', 1, "SBC HL,SP" }, + { 0x0073, 0x00ff, ' ', 3, "LD (nnnn),SP" }, + { 0x0076, 0x00ff, ' ', 1, "PUSH IP" }, + { 0x0077, 0x00ff, ' ', 1, "LD A,XPC" }, + + { 0x007A, 0x00ff, ' ', 1, "ADC HL,SP" }, + { 0x007B, 0x00ff, ' ', 3, "LD SP,(nnnn)" }, + { 0x007E, 0x00ff, ' ', 1, "POP IP" }, + +#if 0 + { 0x0080, 0x00ff, ' ', 1, "COPY" }, /* Rabbit 4000 and up */ + { 0x0083, 0x00ff, ' ', 1, "SRET" }, /* Rabbit 4000 and up */ + { 0x0088, 0x00ff, ' ', 1, "COPYR" }, /* Rabbit 4000 and up */ + { 0x008B, 0x00ff, ' ', 1, "LLRET" }, /* Rabbit 4000 and up */ + + { 0x0090, 0x00ff, ' ', 1, "LDISR" }, /* Rabbit 3000 and up */ + { 0x0098, 0x00ff, ' ', 1, "LDDSR" }, /* Rabbit 3000 and up */ +#endif + + { 0x00A0, 0x00ff, ' ', 1, "LDI" }, + { 0x00A8, 0x00ff, ' ', 1, "LDD" }, + + { 0x00B0, 0x00ff, ' ', 1, "LDIR" }, + { 0x00B8, 0x00ff, ' ', 1, "LDDR" }, + + { 0x00EA, 0x00ff, ' ', 1, "CALL (HL)", true }, + + { 0, 0, 0, 0, NULL } +}; +#endif + +struct dis_entry DISASS_NAME(_cb)[]= { + { 0x0000, 0x00ff, ' ', 1, "RLC B" }, + { 0x0001, 0x00ff, ' ', 1, "RLC C" }, + { 0x0002, 0x00ff, ' ', 1, "RLC D" }, + { 0x0003, 0x00ff, ' ', 1, "RLC E" }, + { 0x0004, 0x00ff, ' ', 1, "RLC H" }, + { 0x0005, 0x00ff, ' ', 1, "RLC L" }, + { 0x0006, 0x00ff, ' ', 1, "RLC (HL)" }, + { 0x0007, 0x00ff, ' ', 1, "RLC A" }, + { 0x0008, 0x00ff, ' ', 1, "RRC B" }, + { 0x0009, 0x00ff, ' ', 1, "RRC C" }, + { 0x000A, 0x00ff, ' ', 1, "RRC D" }, + { 0x000B, 0x00ff, ' ', 1, "RRC E" }, + { 0x000C, 0x00ff, ' ', 1, "RRC H" }, + { 0x000D, 0x00ff, ' ', 1, "RRC L" }, + { 0x000E, 0x00ff, ' ', 1, "RRC (HL)" }, + { 0x000F, 0x00ff, ' ', 1, "RRC A" }, + { 0x0010, 0x00ff, ' ', 1, "RL B" }, + { 0x0011, 0x00ff, ' ', 1, "RL C" }, + { 0x0012, 0x00ff, ' ', 1, "RL D" }, + { 0x0013, 0x00ff, ' ', 1, "RL E" }, + { 0x0014, 0x00ff, ' ', 1, "RL H" }, + { 0x0015, 0x00ff, ' ', 1, "RL L" }, + { 0x0016, 0x00ff, ' ', 1, "RL (HL)" }, + { 0x0017, 0x00ff, ' ', 1, "RL A" }, + { 0x0018, 0x00ff, ' ', 1, "RR B" }, + { 0x0019, 0x00ff, ' ', 1, "RR C" }, + { 0x001A, 0x00ff, ' ', 1, "RR D" }, + { 0x001B, 0x00ff, ' ', 1, "RR E" }, + { 0x001C, 0x00ff, ' ', 1, "RR H" }, + { 0x001D, 0x00ff, ' ', 1, "RR L" }, + { 0x001E, 0x00ff, ' ', 1, "RR (HL)" }, + { 0x001F, 0x00ff, ' ', 1, "RR A" }, + { 0x0020, 0x00ff, ' ', 1, "SLA B" }, + { 0x0021, 0x00ff, ' ', 1, "SLA C" }, + { 0x0022, 0x00ff, ' ', 1, "SLA D" }, + { 0x0023, 0x00ff, ' ', 1, "SLA E" }, + { 0x0024, 0x00ff, ' ', 1, "SLA H" }, + { 0x0025, 0x00ff, ' ', 1, "SLA L" }, + { 0x0026, 0x00ff, ' ', 1, "SLA (HL)" }, + { 0x0027, 0x00ff, ' ', 1, "SLA A" }, + { 0x0028, 0x00ff, ' ', 1, "SRA B" }, + { 0x0029, 0x00ff, ' ', 1, "SRA C" }, + { 0x002A, 0x00ff, ' ', 1, "SRA D" }, + { 0x002B, 0x00ff, ' ', 1, "SRA E" }, + { 0x002C, 0x00ff, ' ', 1, "SRA H" }, + { 0x002D, 0x00ff, ' ', 1, "SRA L" }, + { 0x002E, 0x00ff, ' ', 1, "SRA (HL)" }, + { 0x002F, 0x00ff, ' ', 1, "SRA A" }, + { 0x0030, 0x00ff, ' ', 1, "SLIA B" }, + { 0x0031, 0x00ff, ' ', 1, "SLIA C" }, + { 0x0032, 0x00ff, ' ', 1, "SLIA D" }, + { 0x0033, 0x00ff, ' ', 1, "SLIA E" }, + { 0x0034, 0x00ff, ' ', 1, "SLIA H" }, + { 0x0035, 0x00ff, ' ', 1, "SLIA L" }, + { 0x0036, 0x00ff, ' ', 1, "SLIA (HL)" }, + { 0x0037, 0x00ff, ' ', 1, "SLIA A" }, + { 0x0038, 0x00ff, ' ', 1, "SRL B" }, + { 0x0039, 0x00ff, ' ', 1, "SRL C" }, + { 0x003A, 0x00ff, ' ', 1, "SRL D" }, + { 0x003B, 0x00ff, ' ', 1, "SRL E" }, + { 0x003C, 0x00ff, ' ', 1, "SRL H" }, + { 0x003D, 0x00ff, ' ', 1, "SRL L" }, + { 0x003E, 0x00ff, ' ', 1, "SRL (HL)" }, + { 0x003F, 0x00ff, ' ', 1, "SRL A" }, + { 0x0040, 0x00ff, ' ', 1, "BIT 0,B" }, + { 0x0041, 0x00ff, ' ', 1, "BIT 0,C" }, + { 0x0042, 0x00ff, ' ', 1, "BIT 0,D" }, + { 0x0043, 0x00ff, ' ', 1, "BIT 0,E" }, + { 0x0044, 0x00ff, ' ', 1, "BIT 0,H" }, + { 0x0045, 0x00ff, ' ', 1, "BIT 0,L" }, + { 0x0046, 0x00ff, ' ', 1, "BIT 0,(HL)" }, + { 0x0047, 0x00ff, ' ', 1, "BIT 0,A" }, + { 0x0048, 0x00ff, ' ', 1, "BIT 1,B" }, + { 0x0049, 0x00ff, ' ', 1, "BIT 1,C" }, + { 0x004A, 0x00ff, ' ', 1, "BIT 1,D" }, + { 0x004B, 0x00ff, ' ', 1, "BIT 1,E" }, + { 0x004C, 0x00ff, ' ', 1, "BIT 1,H" }, + { 0x004D, 0x00ff, ' ', 1, "BIT 1,L" }, + { 0x004E, 0x00ff, ' ', 1, "BIT 1,(HL)" }, + { 0x004F, 0x00ff, ' ', 1, "BIT 1,A" }, + { 0x0050, 0x00ff, ' ', 1, "BIT 2,B" }, + { 0x0051, 0x00ff, ' ', 1, "BIT 2,C" }, + { 0x0052, 0x00ff, ' ', 1, "BIT 2,D" }, + { 0x0053, 0x00ff, ' ', 1, "BIT 2,E" }, + { 0x0054, 0x00ff, ' ', 1, "BIT 2,H" }, + { 0x0055, 0x00ff, ' ', 1, "BIT 2,L" }, + { 0x0056, 0x00ff, ' ', 1, "BIT 2,(HL)" }, + { 0x0057, 0x00ff, ' ', 1, "BIT 2,A" }, + { 0x0058, 0x00ff, ' ', 1, "BIT 3,B" }, + { 0x0059, 0x00ff, ' ', 1, "BIT 3,C" }, + { 0x005A, 0x00ff, ' ', 1, "BIT 3,D" }, + { 0x005B, 0x00ff, ' ', 1, "BIT 3,E" }, + { 0x005C, 0x00ff, ' ', 1, "BIT 3,H" }, + { 0x005D, 0x00ff, ' ', 1, "BIT 3,L" }, + { 0x005E, 0x00ff, ' ', 1, "BIT 3,(HL)" }, + { 0x005F, 0x00ff, ' ', 1, "BIT 3,A" }, + { 0x0060, 0x00ff, ' ', 1, "BIT 4,B" }, + { 0x0061, 0x00ff, ' ', 1, "BIT 4,C" }, + { 0x0062, 0x00ff, ' ', 1, "BIT 4,D" }, + { 0x0063, 0x00ff, ' ', 1, "BIT 4,E" }, + { 0x0064, 0x00ff, ' ', 1, "BIT 4,H" }, + { 0x0065, 0x00ff, ' ', 1, "BIT 4,L" }, + { 0x0066, 0x00ff, ' ', 1, "BIT 4,(HL)" }, + { 0x0067, 0x00ff, ' ', 1, "BIT 4,A" }, + { 0x0068, 0x00ff, ' ', 1, "BIT 5,B" }, + { 0x0069, 0x00ff, ' ', 1, "BIT 5,C" }, + { 0x006A, 0x00ff, ' ', 1, "BIT 5,D" }, + { 0x006B, 0x00ff, ' ', 1, "BIT 5,E" }, + { 0x006C, 0x00ff, ' ', 1, "BIT 5,H" }, + { 0x006D, 0x00ff, ' ', 1, "BIT 5,L" }, + { 0x006E, 0x00ff, ' ', 1, "BIT 5,(HL)" }, + { 0x006F, 0x00ff, ' ', 1, "BIT 5,A" }, + { 0x0070, 0x00ff, ' ', 1, "BIT 6,B" }, + { 0x0071, 0x00ff, ' ', 1, "BIT 6,C" }, + { 0x0072, 0x00ff, ' ', 1, "BIT 6,D" }, + { 0x0073, 0x00ff, ' ', 1, "BIT 6,E" }, + { 0x0074, 0x00ff, ' ', 1, "BIT 6,H" }, + { 0x0075, 0x00ff, ' ', 1, "BIT 6,L" }, + { 0x0076, 0x00ff, ' ', 1, "BIT 6,(HL)" }, + { 0x0077, 0x00ff, ' ', 1, "BIT 6,A" }, + { 0x0078, 0x00ff, ' ', 1, "BIT 7,B" }, + { 0x0079, 0x00ff, ' ', 1, "BIT 7,C" }, + { 0x007A, 0x00ff, ' ', 1, "BIT 7,D" }, + { 0x007B, 0x00ff, ' ', 1, "BIT 7,E" }, + { 0x007C, 0x00ff, ' ', 1, "BIT 7,H" }, + { 0x007D, 0x00ff, ' ', 1, "BIT 7,L" }, + { 0x007E, 0x00ff, ' ', 1, "BIT 7,(HL)" }, + { 0x007F, 0x00ff, ' ', 1, "BIT 7,A" }, + { 0x0080, 0x00ff, ' ', 1, "RES 0,B" }, + { 0x0081, 0x00ff, ' ', 1, "RES 0,C" }, + { 0x0082, 0x00ff, ' ', 1, "RES 0,D" }, + { 0x0083, 0x00ff, ' ', 1, "RES 0,E" }, + { 0x0084, 0x00ff, ' ', 1, "RES 0,H" }, + { 0x0085, 0x00ff, ' ', 1, "RES 0,L" }, + { 0x0086, 0x00ff, ' ', 1, "RES 0,(HL)" }, + { 0x0087, 0x00ff, ' ', 1, "RES 0,A" }, + { 0x0088, 0x00ff, ' ', 1, "RES 1,B" }, + { 0x0089, 0x00ff, ' ', 1, "RES 1,C" }, + { 0x008A, 0x00ff, ' ', 1, "RES 1,D" }, + { 0x008B, 0x00ff, ' ', 1, "RES 1,E" }, + { 0x008C, 0x00ff, ' ', 1, "RES 1,H" }, + { 0x008D, 0x00ff, ' ', 1, "RES 1,L" }, + { 0x008E, 0x00ff, ' ', 1, "RES 1,(HL)" }, + { 0x008F, 0x00ff, ' ', 1, "RES 1,A" }, + { 0x0090, 0x00ff, ' ', 1, "RES 2,B" }, + { 0x0091, 0x00ff, ' ', 1, "RES 2,C" }, + { 0x0092, 0x00ff, ' ', 1, "RES 2,D" }, + { 0x0093, 0x00ff, ' ', 1, "RES 2,E" }, + { 0x0094, 0x00ff, ' ', 1, "RES 2,H" }, + { 0x0095, 0x00ff, ' ', 1, "RES 2,L" }, + { 0x0096, 0x00ff, ' ', 1, "RES 2,(HL)" }, + { 0x0097, 0x00ff, ' ', 1, "RES 2,A" }, + { 0x0098, 0x00ff, ' ', 1, "RES 3,B" }, + { 0x0099, 0x00ff, ' ', 1, "RES 3,C" }, + { 0x009A, 0x00ff, ' ', 1, "RES 3,D" }, + { 0x009B, 0x00ff, ' ', 1, "RES 3,E" }, + { 0x009C, 0x00ff, ' ', 1, "RES 3,H" }, + { 0x009D, 0x00ff, ' ', 1, "RES 3,L" }, + { 0x009E, 0x00ff, ' ', 1, "RES 3,(HL)" }, + { 0x009F, 0x00ff, ' ', 1, "RES 3,A" }, + { 0x00A0, 0x00ff, ' ', 1, "RES 4,B" }, + { 0x00A1, 0x00ff, ' ', 1, "RES 4,C" }, + { 0x00A2, 0x00ff, ' ', 1, "RES 4,D" }, + { 0x00A3, 0x00ff, ' ', 1, "RES 4,E" }, + { 0x00A4, 0x00ff, ' ', 1, "RES 4,H" }, + { 0x00A5, 0x00ff, ' ', 1, "RES 4,L" }, + { 0x00A6, 0x00ff, ' ', 1, "RES 4,(HL)" }, + { 0x00A7, 0x00ff, ' ', 1, "RES 4,A" }, + { 0x00A8, 0x00ff, ' ', 1, "RES 5,B" }, + { 0x00A9, 0x00ff, ' ', 1, "RES 5,C" }, + { 0x00AA, 0x00ff, ' ', 1, "RES 5,D" }, + { 0x00AB, 0x00ff, ' ', 1, "RES 5,E" }, + { 0x00AC, 0x00ff, ' ', 1, "RES 5,H" }, + { 0x00AD, 0x00ff, ' ', 1, "RES 5,L" }, + { 0x00AE, 0x00ff, ' ', 1, "RES 5,(HL)" }, + { 0x00AF, 0x00ff, ' ', 1, "RES 5,A" }, + { 0x00B0, 0x00ff, ' ', 1, "RES 6,B" }, + { 0x00B1, 0x00ff, ' ', 1, "RES 6,C" }, + { 0x00B2, 0x00ff, ' ', 1, "RES 6,D" }, + { 0x00B3, 0x00ff, ' ', 1, "RES 6,E" }, + { 0x00B4, 0x00ff, ' ', 1, "RES 6,H" }, + { 0x00B5, 0x00ff, ' ', 1, "RES 6,L" }, + { 0x00B6, 0x00ff, ' ', 1, "RES 6,(HL)" }, + { 0x00B7, 0x00ff, ' ', 1, "RES 6,A" }, + { 0x00B8, 0x00ff, ' ', 1, "RES 7,B" }, + { 0x00B9, 0x00ff, ' ', 1, "RES 7,C" }, + { 0x00BA, 0x00ff, ' ', 1, "RES 7,D" }, + { 0x00BB, 0x00ff, ' ', 1, "RES 7,E" }, + { 0x00BC, 0x00ff, ' ', 1, "RES 7,H" }, + { 0x00BD, 0x00ff, ' ', 1, "RES 7,L" }, + { 0x00BE, 0x00ff, ' ', 1, "RES 7,(HL)" }, + { 0x00BF, 0x00ff, ' ', 1, "RES 7,A" }, + { 0x00C0, 0x00ff, ' ', 1, "SET 0,B" }, + { 0x00C1, 0x00ff, ' ', 1, "SET 0,C" }, + { 0x00C2, 0x00ff, ' ', 1, "SET 0,D" }, + { 0x00C3, 0x00ff, ' ', 1, "SET 0,E" }, + { 0x00C4, 0x00ff, ' ', 1, "SET 0,H" }, + { 0x00C5, 0x00ff, ' ', 1, "SET 0,L" }, + { 0x00C6, 0x00ff, ' ', 1, "SET 0,(HL)" }, + { 0x00C7, 0x00ff, ' ', 1, "SET 0,A" }, + { 0x00C8, 0x00ff, ' ', 1, "SET 1,B" }, + { 0x00C9, 0x00ff, ' ', 1, "SET 1,C" }, + { 0x00CA, 0x00ff, ' ', 1, "SET 1,D" }, + { 0x00CB, 0x00ff, ' ', 1, "SET 1,E" }, + { 0x00CC, 0x00ff, ' ', 1, "SET 1,H" }, + { 0x00CD, 0x00ff, ' ', 1, "SET 1,L" }, + { 0x00CE, 0x00ff, ' ', 1, "SET 1,(HL)" }, + { 0x00CF, 0x00ff, ' ', 1, "SET 1,A" }, + { 0x00D0, 0x00ff, ' ', 1, "SET 2,B" }, + { 0x00D1, 0x00ff, ' ', 1, "SET 2,C" }, + { 0x00D2, 0x00ff, ' ', 1, "SET 2,D" }, + { 0x00D3, 0x00ff, ' ', 1, "SET 2,E" }, + { 0x00D4, 0x00ff, ' ', 1, "SET 2,H" }, + { 0x00D5, 0x00ff, ' ', 1, "SET 2,L" }, + { 0x00D6, 0x00ff, ' ', 1, "SET 2,(HL)" }, + { 0x00D7, 0x00ff, ' ', 1, "SET 2,A" }, + { 0x00D8, 0x00ff, ' ', 1, "SET 3,B" }, + { 0x00D9, 0x00ff, ' ', 1, "SET 3,C" }, + { 0x00DA, 0x00ff, ' ', 1, "SET 3,D" }, + { 0x00DB, 0x00ff, ' ', 1, "SET 3,E" }, + { 0x00DC, 0x00ff, ' ', 1, "SET 3,H" }, + { 0x00DD, 0x00ff, ' ', 1, "SET 3,L" }, + { 0x00DE, 0x00ff, ' ', 1, "SET 3,(HL)" }, + { 0x00DF, 0x00ff, ' ', 1, "SET 3,A" }, + { 0x00E0, 0x00ff, ' ', 1, "SET 4,B" }, + { 0x00E1, 0x00ff, ' ', 1, "SET 4,C" }, + { 0x00E2, 0x00ff, ' ', 1, "SET 4,D" }, + { 0x00E3, 0x00ff, ' ', 1, "SET 4,E" }, + { 0x00E4, 0x00ff, ' ', 1, "SET 4,H" }, + { 0x00E5, 0x00ff, ' ', 1, "SET 4,L" }, + { 0x00E6, 0x00ff, ' ', 1, "SET 4,(HL)" }, + { 0x00E7, 0x00ff, ' ', 1, "SET 4,A" }, + { 0x00E8, 0x00ff, ' ', 1, "SET 5,B" }, + { 0x00E9, 0x00ff, ' ', 1, "SET 5,C" }, + { 0x00EA, 0x00ff, ' ', 1, "SET 5,D" }, + { 0x00EB, 0x00ff, ' ', 1, "SET 5,E" }, + { 0x00EC, 0x00ff, ' ', 1, "SET 5,H" }, + { 0x00ED, 0x00ff, ' ', 1, "SET 5,L" }, + { 0x00EE, 0x00ff, ' ', 1, "SET 5,(HL)" }, + { 0x00EF, 0x00ff, ' ', 1, "SET 5,A" }, + { 0x00F0, 0x00ff, ' ', 1, "SET 6,B" }, + { 0x00F1, 0x00ff, ' ', 1, "SET 6,C" }, + { 0x00F2, 0x00ff, ' ', 1, "SET 6,D" }, + { 0x00F3, 0x00ff, ' ', 1, "SET 6,E" }, + { 0x00F4, 0x00ff, ' ', 1, "SET 6,H" }, + { 0x00F5, 0x00ff, ' ', 1, "SET 6,L" }, + { 0x00F6, 0x00ff, ' ', 1, "SET 6,(HL)" }, + { 0x00F7, 0x00ff, ' ', 1, "SET 6,A" }, + { 0x00F8, 0x00ff, ' ', 1, "SET 7,B" }, + { 0x00F9, 0x00ff, ' ', 1, "SET 7,C" }, + { 0x00FA, 0x00ff, ' ', 1, "SET 7,D" }, + { 0x00FB, 0x00ff, ' ', 1, "SET 7,E" }, + { 0x00FC, 0x00ff, ' ', 1, "SET 7,H" }, + { 0x00FD, 0x00ff, ' ', 1, "SET 7,L" }, + { 0x00FE, 0x00ff, ' ', 1, "SET 7,(HL)" }, + { 0x00FF, 0x00ff, ' ', 1, "SET 7,A" }, + { 0, 0, 0, 0, NULL } +}; + +struct dis_entry DISASS_NAME(_dd)[]= { + { 0x0021, 0x00ff, ' ', 3, "LD IX,%w" }, + { 0x0022, 0x00ff, ' ', 3, "LD (%w),IX" }, + { 0x0026, 0x00ff, ' ', 2, "LD HX,%b" }, + { 0x002A, 0x00ff, ' ', 3, "LD IX,(%w)" }, + { 0x002E, 0x00ff, ' ', 2, "LD LX,%b" }, + { 0x0036, 0x00ff, ' ', 3, "LD (IX+%d),%b" }, + { 0x0044, 0x00ff, ' ', 1, "LD B,HX" }, + { 0x0045, 0x00ff, ' ', 1, "LD B,LX" }, + { 0x0046, 0x00ff, ' ', 2, "LD B,(IX+%d)" }, + { 0x004C, 0x00ff, ' ', 1, "LD C,HX" }, + { 0x004D, 0x00ff, ' ', 1, "LD C,LX" }, + { 0x004E, 0x00ff, ' ', 2, "LD C,(IX+%d)" }, + { 0x0054, 0x00ff, ' ', 1, "LD D,HX" }, + { 0x0055, 0x00ff, ' ', 1, "LD D,LX" }, + { 0x0056, 0x00ff, ' ', 2, "LD D,(IX+%d)" }, + { 0x005C, 0x00ff, ' ', 1, "LD E,H" }, + { 0x005D, 0x00ff, ' ', 1, "LD E,L" }, + { 0x005E, 0x00ff, ' ', 2, "LD E,(IX+%d)" }, + { 0x0060, 0x00ff, ' ', 1, "LD HX,B" }, + { 0x0061, 0x00ff, ' ', 1, "LD HX,C" }, + { 0x0062, 0x00ff, ' ', 1, "LD HX,D" }, + { 0x0063, 0x00ff, ' ', 1, "LD HX,E" }, + { 0x0064, 0x00ff, ' ', 1, "LD HX,HX" }, + { 0x0066, 0x00ff, ' ', 2, "LD H,(IX+%d)" }, + { 0x0067, 0x00ff, ' ', 1, "LD HX,A" }, + { 0x0068, 0x00ff, ' ', 1, "LD LX,B" }, + { 0x0069, 0x00ff, ' ', 1, "LD LX,C" }, + { 0x006A, 0x00ff, ' ', 1, "LD LX,D" }, + { 0x006B, 0x00ff, ' ', 1, "LD LX,E" }, + { 0x006C, 0x00ff, ' ', 1, "LD LX,HX" }, + { 0x006D, 0x00ff, ' ', 1, "LD LX,LX" }, + { 0x006E, 0x00ff, ' ', 2, "LD L,(IX+%d)" }, + { 0x006F, 0x00ff, ' ', 1, "LD LX,A" }, + { 0x0070, 0x00ff, ' ', 2, "LD (IX+%d),B" }, + { 0x0071, 0x00ff, ' ', 2, "LD (IX+%d),C" }, + { 0x0072, 0x00ff, ' ', 2, "LD (IX+%d),D" }, + { 0x0073, 0x00ff, ' ', 2, "LD (IX+%d),E" }, + { 0x0074, 0x00ff, ' ', 2, "LD (IX+%d),H" }, + { 0x0075, 0x00ff, ' ', 2, "LD (IX+%d),L" }, + { 0x0077, 0x00ff, ' ', 2, "LD (IX+%d),A" }, +#ifndef R2K + { 0x007C, 0x00ff, ' ', 1, "LD A,HX" }, + { 0x007D, 0x00ff, ' ', 1, "LD A,LX" }, +#else + { 0x007C, 0x00ff, ' ', 1, "LD HL,IX" }, + { 0x007D, 0x00ff, ' ', 1, "LD IX,HL" }, +#endif + { 0x007E, 0x00ff, ' ', 2, "LD A,(IX+%d)" }, + { 0x00F9, 0x00ff, ' ', 1, "LD SP,IX" }, + + { 0x0023, 0x00ff, ' ', 1, "INC IX" }, + { 0x0024, 0x00ff, ' ', 1, "INC HX" }, + { 0x002C, 0x00ff, ' ', 1, "INC LX" }, + { 0x0034, 0x00ff, ' ', 2, "INC (IX+%d)" }, + + { 0x0009, 0x00ff, ' ', 1, "ADD IX,BC" }, + { 0x0019, 0x00ff, ' ', 1, "ADD IX,DE" }, + { 0x0029, 0x00ff, ' ', 1, "ADD IX,IX" }, + { 0x0039, 0x00ff, ' ', 1, "ADD IX,SP" }, + { 0x0084, 0x00ff, ' ', 1, "ADD A,HX" }, + { 0x0085, 0x00ff, ' ', 1, "ADD A,LX" }, + { 0x0086, 0x00ff, ' ', 2, "ADD A,(IX+%d)" }, + + { 0x0025, 0x00ff, ' ', 1, "DEC HX" }, + { 0x002B, 0x00ff, ' ', 1, "DEC IX" }, + { 0x002D, 0x00ff, ' ', 1, "DEC LX" }, + { 0x0035, 0x00ff, ' ', 2, "DEC (IX+%d)" }, + + { 0x008C, 0x00ff, ' ', 1, "ADC A,HX" }, + { 0x008D, 0x00ff, ' ', 1, "ADC A,LX" }, + { 0x008E, 0x00ff, ' ', 2, "ADC A,(IX+%d)" }, + { 0x0094, 0x00ff, ' ', 1, "SUB HX" }, + { 0x0095, 0x00ff, ' ', 1, "SUB LX" }, + { 0x0096, 0x00ff, ' ', 2, "SUB (IX+%d)" }, + { 0x009C, 0x00ff, ' ', 1, "SBC A,HX" }, + { 0x009D, 0x00ff, ' ', 1, "SBC A,LX" }, + { 0x009E, 0x00ff, ' ', 2, "SBC A,(IX+%d)" }, + { 0x00A4, 0x00ff, ' ', 1, "AND HX" }, + { 0x00A5, 0x00ff, ' ', 1, "AND LX" }, + { 0x00A6, 0x00ff, ' ', 2, "AND (IX+%d)" }, + { 0x00AC, 0x00ff, ' ', 1, "XOR HX" }, + { 0x00AD, 0x00ff, ' ', 1, "XOR LX" }, + { 0x00AE, 0x00ff, ' ', 2, "XOR (IX+%d)" }, + { 0x00B4, 0x00ff, ' ', 1, "OR HX" }, + { 0x00B5, 0x00ff, ' ', 1, "OR LX" }, + { 0x00B6, 0x00ff, ' ', 2, "OR (IX+%d)" }, + { 0x00BC, 0x00ff, ' ', 1, "CP HX" }, + { 0x00BD, 0x00ff, ' ', 1, "CP LX" }, + { 0x00BE, 0x00ff, ' ', 2, "CP (IX+%d)" }, + { 0x00CB, 0x00ff, ' ', 1, "?cb?" }, + { 0x00E1, 0x00ff, ' ', 1, "POP IX" }, + { 0x00E3, 0x00ff, ' ', 1, "EX (SP),IX" }, + { 0x00E5, 0x00ff, ' ', 1, "PUSH IX" }, + { 0x00E9, 0x00ff, ' ', 1, "JP (IX)" }, + + { 0, 0, 0, 0, NULL } +}; + +struct dis_entry DISASS_NAME(_fd)[]= { + { 0x0021, 0x00ff, ' ', 3, "LD IY,%w" }, + { 0x0022, 0x00ff, ' ', 3, "LD (%w),IY" }, + { 0x0026, 0x00ff, ' ', 2, "LD HX,%b" }, + { 0x002A, 0x00ff, ' ', 3, "LD IY,(%w)" }, + { 0x002E, 0x00ff, ' ', 2, "LD LX,%b" }, + { 0x0036, 0x00ff, ' ', 3, "LD (IY+%d),%b" }, + { 0x0044, 0x00ff, ' ', 1, "LD B,HX" }, + { 0x0045, 0x00ff, ' ', 1, "LD B,LX" }, + { 0x0046, 0x00ff, ' ', 2, "LD B,(IY+%d)" }, + { 0x004C, 0x00ff, ' ', 1, "LD C,HX" }, + { 0x004D, 0x00ff, ' ', 1, "LD C,LX" }, + { 0x004E, 0x00ff, ' ', 2, "LD C,(IY+%d)" }, + { 0x0054, 0x00ff, ' ', 1, "LD D,HX" }, + { 0x0055, 0x00ff, ' ', 1, "LD D,LX" }, + { 0x0056, 0x00ff, ' ', 2, "LD D,(IY+%d)" }, + { 0x005C, 0x00ff, ' ', 1, "LD E,H" }, + { 0x005D, 0x00ff, ' ', 1, "LD E,L" }, + { 0x005E, 0x00ff, ' ', 2, "LD E,(IY+%d)" }, + { 0x0060, 0x00ff, ' ', 1, "LD HX,B" }, + { 0x0061, 0x00ff, ' ', 1, "LD HX,C" }, + { 0x0062, 0x00ff, ' ', 1, "LD HX,D" }, + { 0x0063, 0x00ff, ' ', 1, "LD HX,E" }, + { 0x0064, 0x00ff, ' ', 1, "LD HX,HX" }, + { 0x0066, 0x00ff, ' ', 2, "LD H,(IY+%d)" }, + { 0x0067, 0x00ff, ' ', 1, "LD HX,A" }, + { 0x0068, 0x00ff, ' ', 1, "LD LX,B" }, + { 0x0069, 0x00ff, ' ', 1, "LD LX,C" }, + { 0x006A, 0x00ff, ' ', 1, "LD LX,D" }, + { 0x006B, 0x00ff, ' ', 1, "LD LX,E" }, + { 0x006C, 0x00ff, ' ', 1, "LD LX,HX" }, + { 0x006D, 0x00ff, ' ', 1, "LD LX,LX" }, + { 0x006E, 0x00ff, ' ', 2, "LD L,(IY+%d)" }, + { 0x006F, 0x00ff, ' ', 1, "LD LX,A" }, + { 0x0070, 0x00ff, ' ', 2, "LD (IY+%d),B" }, + { 0x0071, 0x00ff, ' ', 2, "LD (IY+%d),C" }, + { 0x0072, 0x00ff, ' ', 2, "LD (IY+%d),D" }, + { 0x0073, 0x00ff, ' ', 2, "LD (IY+%d),E" }, + { 0x0074, 0x00ff, ' ', 2, "LD (IY+%d),H" }, + { 0x0075, 0x00ff, ' ', 2, "LD (IY+%d),L" }, + { 0x0077, 0x00ff, ' ', 2, "LD (IY+%d),A" }, +#ifndef R2K + { 0x007C, 0x00ff, ' ', 1, "LD A,HX" }, + { 0x007D, 0x00ff, ' ', 1, "LD A,LX" }, +#else + { 0x007C, 0x00ff, ' ', 1, "LD HL,IX" }, + { 0x007D, 0x00ff, ' ', 1, "LD IX,HL" }, +#endif + { 0x007E, 0x00ff, ' ', 2, "LD A,(IY+%d)" }, + { 0x00F9, 0x00ff, ' ', 1, "LD SP,IY" }, + + { 0x0023, 0x00ff, ' ', 1, "INC IY" }, + { 0x0024, 0x00ff, ' ', 1, "INC HX" }, + { 0x002C, 0x00ff, ' ', 1, "INC LX" }, + { 0x0034, 0x00ff, ' ', 2, "INC (IY+%d)" }, + + { 0x0009, 0x00ff, ' ', 1, "ADD IY,BC" }, + { 0x0019, 0x00ff, ' ', 1, "ADD IY,DE" }, + { 0x0029, 0x00ff, ' ', 1, "ADD IY,IY" }, + { 0x0039, 0x00ff, ' ', 1, "ADD IY,SP" }, + { 0x0084, 0x00ff, ' ', 1, "ADD A,HX" }, + { 0x0085, 0x00ff, ' ', 1, "ADD A,LX" }, + { 0x0086, 0x00ff, ' ', 2, "ADD A,(IY+%d)" }, + + { 0x0025, 0x00ff, ' ', 1, "DEC HX" }, + { 0x002B, 0x00ff, ' ', 1, "DEC IY" }, + { 0x002D, 0x00ff, ' ', 1, "DEC LX" }, + { 0x0035, 0x00ff, ' ', 2, "DEC (IY+%d)" }, + + { 0x008C, 0x00ff, ' ', 1, "ADC A,HX" }, + { 0x008D, 0x00ff, ' ', 1, "ADC A,LX" }, + { 0x008E, 0x00ff, ' ', 2, "ADC A,(IY+%d)" }, + { 0x0094, 0x00ff, ' ', 1, "SUB HX" }, + { 0x0095, 0x00ff, ' ', 1, "SUB LX" }, + { 0x0096, 0x00ff, ' ', 2, "SUB (IY+%d)" }, + { 0x009C, 0x00ff, ' ', 1, "SBC A,HX" }, + { 0x009D, 0x00ff, ' ', 1, "SBC A,LX" }, + { 0x009E, 0x00ff, ' ', 2, "SBC A,(IY+%d)" }, + { 0x00A4, 0x00ff, ' ', 1, "AND HX" }, + { 0x00A5, 0x00ff, ' ', 1, "AND LX" }, + { 0x00A6, 0x00ff, ' ', 2, "AND (IY+%d)" }, + { 0x00AC, 0x00ff, ' ', 1, "XOR HX" }, + { 0x00AD, 0x00ff, ' ', 1, "XOR LX" }, + { 0x00AE, 0x00ff, ' ', 2, "XOR (IY+%d)" }, + { 0x00B4, 0x00ff, ' ', 1, "OR HX" }, + { 0x00B5, 0x00ff, ' ', 1, "OR LX" }, + { 0x00B6, 0x00ff, ' ', 2, "OR (IY+%d)" }, + { 0x00BC, 0x00ff, ' ', 1, "CP HX" }, + { 0x00BD, 0x00ff, ' ', 1, "CP LX" }, + { 0x00BE, 0x00ff, ' ', 2, "CP (IY+%d)" }, + { 0x00CB, 0x00ff, ' ', 1, "escape" }, + { 0x00E1, 0x00ff, ' ', 1, "POP IY" }, + { 0x00E3, 0x00ff, ' ', 1, "EX (SP),IY" }, + { 0x00E5, 0x00ff, ' ', 1, "PUSH IY" }, + { 0x00E9, 0x00ff, ' ', 1, "JP (IY)" }, + + { 0, 0, 0, 0, NULL } +}; + + +struct dis_entry DISASS_NAME(_ddcb)[]= { + { 0x0000, 0x00ff, ' ', 2, "RLC (IX+%d)->B" }, + { 0x0001, 0x00ff, ' ', 2, "RLC (IX+%d)->C" }, + { 0x0002, 0x00ff, ' ', 2, "RLC (IX+%d)->D" }, + { 0x0003, 0x00ff, ' ', 2, "RLC (IX+%d)->E" }, + { 0x0004, 0x00ff, ' ', 2, "RLC (IX+%d)->H" }, + { 0x0005, 0x00ff, ' ', 2, "RLC (IX+%d)->L" }, + { 0x0006, 0x00ff, ' ', 2, "RLC (IX+%d)" }, + { 0x0007, 0x00ff, ' ', 2, "RLC (IX+%d)->A" }, + { 0x0008, 0x00ff, ' ', 2, "RRC (IX+%d)->B" }, + { 0x0009, 0x00ff, ' ', 2, "RRC (IX+%d)->C" }, + { 0x000A, 0x00ff, ' ', 2, "RRC (IX+%d)->D" }, + { 0x000B, 0x00ff, ' ', 2, "RRC (IX+%d)->E" }, + { 0x000C, 0x00ff, ' ', 2, "RRC (IX+%d)->H" }, + { 0x000D, 0x00ff, ' ', 2, "RRC (IX+%d)->L" }, + { 0x000E, 0x00ff, ' ', 2, "RRC (IX+%d)" }, + { 0x000F, 0x00ff, ' ', 2, "RRC (IX+%d)->A" }, + { 0x0010, 0x00ff, ' ', 2, "RL (IX+%d)->B" }, + { 0x0011, 0x00ff, ' ', 2, "RL (IX+%d)->C" }, + { 0x0012, 0x00ff, ' ', 2, "RL (IX+%d)->D" }, + { 0x0013, 0x00ff, ' ', 2, "RL (IX+%d)->E" }, + { 0x0014, 0x00ff, ' ', 2, "RL (IX+%d)->H" }, + { 0x0015, 0x00ff, ' ', 2, "RL (IX+%d)->L" }, + { 0x0016, 0x00ff, ' ', 2, "RL (IX+%d)" }, + { 0x0017, 0x00ff, ' ', 2, "RL (IX+%d)->A" }, + { 0x0018, 0x00ff, ' ', 2, "RR (IX+%d)->B" }, + { 0x0019, 0x00ff, ' ', 2, "RR (IX+%d)->C" }, + { 0x001A, 0x00ff, ' ', 2, "RR (IX+%d)->D" }, + { 0x001B, 0x00ff, ' ', 2, "RR (IX+%d)->E" }, + { 0x001C, 0x00ff, ' ', 2, "RR (IX+%d)->H" }, + { 0x001D, 0x00ff, ' ', 2, "RR (IX+%d)->L" }, + { 0x001E, 0x00ff, ' ', 2, "RR (IX+%d)" }, + { 0x001F, 0x00ff, ' ', 2, "RR (IX+%d)->A" }, + { 0x0020, 0x00ff, ' ', 2, "SLA (IX+%d)->B" }, + { 0x0021, 0x00ff, ' ', 2, "SLA (IX+%d)->C" }, + { 0x0022, 0x00ff, ' ', 2, "SLA (IX+%d)->D" }, + { 0x0023, 0x00ff, ' ', 2, "SLA (IX+%d)->E" }, + { 0x0024, 0x00ff, ' ', 2, "SLA (IX+%d)->H" }, + { 0x0025, 0x00ff, ' ', 2, "SLA (IX+%d)->L" }, + { 0x0026, 0x00ff, ' ', 2, "SLA (IX+%d)" }, + { 0x0027, 0x00ff, ' ', 2, "SLA (IX+%d)->A" }, + { 0x0028, 0x00ff, ' ', 2, "SRA (IX+%d)->B" }, + { 0x0029, 0x00ff, ' ', 2, "SRA (IX+%d)->C" }, + { 0x002A, 0x00ff, ' ', 2, "SRA (IX+%d)->D" }, + { 0x002B, 0x00ff, ' ', 2, "SRA (IX+%d)->E" }, + { 0x002C, 0x00ff, ' ', 2, "SRA (IX+%d)->H" }, + { 0x002D, 0x00ff, ' ', 2, "SRA (IX+%d)->L" }, + { 0x002E, 0x00ff, ' ', 2, "SRA (IX+%d)" }, + { 0x002F, 0x00ff, ' ', 2, "SRA (IX+%d)->A" }, + { 0x0030, 0x00ff, ' ', 2, "SLIA (IX+%d)->B" }, + { 0x0031, 0x00ff, ' ', 2, "SLIA (IX+%d)->C" }, + { 0x0032, 0x00ff, ' ', 2, "SLIA (IX+%d)->D" }, + { 0x0033, 0x00ff, ' ', 2, "SLIA (IX+%d)->E" }, + { 0x0034, 0x00ff, ' ', 2, "SLIA (IX+%d)->H" }, + { 0x0035, 0x00ff, ' ', 2, "SLIA (IX+%d)->L" }, + { 0x0036, 0x00ff, ' ', 2, "SLIA (IX+%d)" }, + { 0x0037, 0x00ff, ' ', 2, "SLIA (IX+%d)->A" }, + { 0x0038, 0x00ff, ' ', 2, "SRL (IX+%d)->B" }, + { 0x0039, 0x00ff, ' ', 2, "SRL (IX+%d)->C" }, + { 0x003A, 0x00ff, ' ', 2, "SRL (IX+%d)->D" }, + { 0x003B, 0x00ff, ' ', 2, "SRL (IX+%d)->E" }, + { 0x003C, 0x00ff, ' ', 2, "SRL (IX+%d)->H" }, + { 0x003D, 0x00ff, ' ', 2, "SRL (IX+%d)->L" }, + { 0x003E, 0x00ff, ' ', 2, "SRL (IX+%d)" }, + { 0x003F, 0x00ff, ' ', 2, "SRL A" }, + { 0x0040, 0x00ff, ' ', 2, "BIT (IX+%d)->0,B" }, + { 0x0041, 0x00ff, ' ', 2, "BIT (IX+%d)->0,C" }, + { 0x0042, 0x00ff, ' ', 2, "BIT (IX+%d)->0,D" }, + { 0x0043, 0x00ff, ' ', 2, "BIT (IX+%d)->0,E" }, + { 0x0044, 0x00ff, ' ', 2, "BIT (IX+%d)->0,H" }, + { 0x0045, 0x00ff, ' ', 2, "BIT (IX+%d)->0,L" }, + { 0x0046, 0x00ff, ' ', 2, "BIT 0,(IX+%d)" }, + { 0x004E, 0x00ff, ' ', 2, "BIT 1,(IX+%d)" }, + { 0x0056, 0x00ff, ' ', 2, "BIT 2,(IX+%d)" }, + { 0x005E, 0x00ff, ' ', 2, "BIT 3,(IX+%d)" }, + { 0x0066, 0x00ff, ' ', 2, "BIT 4,(IX+%d)" }, + { 0x006E, 0x00ff, ' ', 2, "BIT 5,(IX+%d)" }, + { 0x0076, 0x00ff, ' ', 2, "BIT 6,(IX+%d)" }, + { 0x007E, 0x00ff, ' ', 2, "BIT 7,(IX+%d)" }, + { 0x0080, 0x00ff, ' ', 2, "RES 0,(IX+%d)->B" }, + { 0x0081, 0x00ff, ' ', 2, "RES 0,(IX+%d)->C" }, + { 0x0082, 0x00ff, ' ', 2, "RES 0,(IX+%d)->D" }, + { 0x0083, 0x00ff, ' ', 2, "RES 0,(IX+%d)->E" }, + { 0x0084, 0x00ff, ' ', 2, "RES 0,(IX+%d)->H" }, + { 0x0085, 0x00ff, ' ', 2, "RES 0,(IX+%d)->L" }, + { 0x0086, 0x00ff, ' ', 2, "RES 0,(IX+%d)" }, + { 0x0087, 0x00ff, ' ', 2, "RES 0,(IX+%d)->A" }, + { 0x0088, 0x00ff, ' ', 2, "RES 1,(IX+%d)->B" }, + { 0x0089, 0x00ff, ' ', 2, "RES 1,(IX+%d)->C" }, + { 0x008A, 0x00ff, ' ', 2, "RES 1,(IX+%d)->D" }, + { 0x008B, 0x00ff, ' ', 2, "RES 1,(IX+%d)->E" }, + { 0x008C, 0x00ff, ' ', 2, "RES 1,(IX+%d)->H" }, + { 0x008D, 0x00ff, ' ', 2, "RES 1,(IX+%d)->L" }, + { 0x008E, 0x00ff, ' ', 2, "RES 1,(IX+%d)" }, + { 0x008F, 0x00ff, ' ', 2, "RES 1,(IX+%d)->A" }, + { 0x0090, 0x00ff, ' ', 2, "RES 2,(IX+%d)->B" }, + { 0x0091, 0x00ff, ' ', 2, "RES 2,(IX+%d)->C" }, + { 0x0092, 0x00ff, ' ', 2, "RES 2,(IX+%d)->D" }, + { 0x0093, 0x00ff, ' ', 2, "RES 2,(IX+%d)->E" }, + { 0x0094, 0x00ff, ' ', 2, "RES 2,(IX+%d)->H" }, + { 0x0095, 0x00ff, ' ', 2, "RES 2,(IX+%d)->L" }, + { 0x0096, 0x00ff, ' ', 2, "RES 2,(IX+%d)" }, + { 0x0097, 0x00ff, ' ', 2, "RES 2,(IX+%d)->A" }, + { 0x0098, 0x00ff, ' ', 2, "RES 3,(IX+%d)->B" }, + { 0x0099, 0x00ff, ' ', 2, "RES 3,(IX+%d)->C" }, + { 0x009A, 0x00ff, ' ', 2, "RES 3,(IX+%d)->D" }, + { 0x009B, 0x00ff, ' ', 2, "RES 3,(IX+%d)->E" }, + { 0x009C, 0x00ff, ' ', 2, "RES 3,(IX+%d)->H" }, + { 0x009D, 0x00ff, ' ', 2, "RES 3,(IX+%d)->L" }, + { 0x009E, 0x00ff, ' ', 2, "RES 3,(IX+%d)" }, + { 0x009F, 0x00ff, ' ', 2, "RES 3,(IX+%d)->A" }, + { 0x00A0, 0x00ff, ' ', 2, "RES 4,(IX+%d)->B" }, + { 0x00A1, 0x00ff, ' ', 2, "RES 4,(IX+%d)->C" }, + { 0x00A2, 0x00ff, ' ', 2, "RES 4,(IX+%d)->D" }, + { 0x00A3, 0x00ff, ' ', 2, "RES 4,(IX+%d)->E" }, + { 0x00A4, 0x00ff, ' ', 2, "RES 4,(IX+%d)->H" }, + { 0x00A5, 0x00ff, ' ', 2, "RES 4,(IX+%d)->L" }, + { 0x00A6, 0x00ff, ' ', 2, "RES 4,(IX+%d)" }, + { 0x00A7, 0x00ff, ' ', 2, "RES 4,(IX+%d)->A" }, + { 0x00A8, 0x00ff, ' ', 2, "RES 5,(IX+%d)->B" }, + { 0x00A9, 0x00ff, ' ', 2, "RES 5,(IX+%d)->C" }, + { 0x00AA, 0x00ff, ' ', 2, "RES 5,(IX+%d)->D" }, + { 0x00AB, 0x00ff, ' ', 2, "RES 5,(IX+%d)->E" }, + { 0x00AC, 0x00ff, ' ', 2, "RES 5,(IX+%d)->H" }, + { 0x00AD, 0x00ff, ' ', 2, "RES 5,(IX+%d)->L" }, + { 0x00AE, 0x00ff, ' ', 2, "RES 5,(IX+%d)" }, + { 0x00AF, 0x00ff, ' ', 2, "RES 5,(IX+%d)->A" }, + { 0x00B0, 0x00ff, ' ', 2, "RES 6,(IX+%d)->B" }, + { 0x00B1, 0x00ff, ' ', 2, "RES 6,(IX+%d)->C" }, + { 0x00B2, 0x00ff, ' ', 2, "RES 6,(IX+%d)->D" }, + { 0x00B3, 0x00ff, ' ', 2, "RES 6,(IX+%d)->E" }, + { 0x00B4, 0x00ff, ' ', 2, "RES 6,(IX+%d)->H" }, + { 0x00B5, 0x00ff, ' ', 2, "RES 6,(IX+%d)->L" }, + { 0x00B6, 0x00ff, ' ', 2, "RES 6,(IX+%d)" }, + { 0x00B7, 0x00ff, ' ', 2, "RES 6,(IX+%d)->A" }, + { 0x00B8, 0x00ff, ' ', 2, "RES 7,(IX+%d)->B" }, + { 0x00B9, 0x00ff, ' ', 2, "RES 7,(IX+%d)->C" }, + { 0x00BA, 0x00ff, ' ', 2, "RES 7,(IX+%d)->D" }, + { 0x00BB, 0x00ff, ' ', 2, "RES 7,(IX+%d)->E" }, + { 0x00BC, 0x00ff, ' ', 2, "RES 7,(IX+%d)->H" }, + { 0x00BD, 0x00ff, ' ', 2, "RES 7,(IX+%d)->L" }, + { 0x00BE, 0x00ff, ' ', 2, "RES 7,(IX+%d)" }, + { 0x00BF, 0x00ff, ' ', 2, "RES 7,(IX+%d)->A" }, + { 0x00C0, 0x00ff, ' ', 2, "SET 0,(IX+%d)->B" }, + { 0x00C1, 0x00ff, ' ', 2, "SET 0,(IX+%d)->C" }, + { 0x00C2, 0x00ff, ' ', 2, "SET 0,(IX+%d)->D" }, + { 0x00C3, 0x00ff, ' ', 2, "SET 0,(IX+%d)->E" }, + { 0x00C4, 0x00ff, ' ', 2, "SET 0,(IX+%d)->H" }, + { 0x00C5, 0x00ff, ' ', 2, "SET 0,(IX+%d)->L" }, + { 0x00C6, 0x00ff, ' ', 2, "SET 0,(IX+%d)" }, + { 0x00C7, 0x00ff, ' ', 2, "SET 0,(IX+%d)->A" }, + { 0x00C8, 0x00ff, ' ', 2, "SET 1,(IX+%d)->B" }, + { 0x00C9, 0x00ff, ' ', 2, "SET 1,(IX+%d)->C" }, + { 0x00CA, 0x00ff, ' ', 2, "SET 1,(IX+%d)->D" }, + { 0x00CB, 0x00ff, ' ', 2, "SET 1,(IX+%d)->E" }, + { 0x00CC, 0x00ff, ' ', 2, "SET 1,(IX+%d)->H" }, + { 0x00CD, 0x00ff, ' ', 2, "SET 1,(IX+%d)->L" }, + { 0x00CE, 0x00ff, ' ', 2, "SET 1,(IX+%d)" }, + { 0x00CF, 0x00ff, ' ', 2, "SET 1,(IX+%d)->A" }, + { 0x00D0, 0x00ff, ' ', 2, "SET 2,(IX+%d)->B" }, + { 0x00D1, 0x00ff, ' ', 2, "SET 2,(IX+%d)->C" }, + { 0x00D2, 0x00ff, ' ', 2, "SET 2,(IX+%d)->D" }, + { 0x00D3, 0x00ff, ' ', 2, "SET 2,(IX+%d)->E" }, + { 0x00D4, 0x00ff, ' ', 2, "SET 2,(IX+%d)->H" }, + { 0x00D5, 0x00ff, ' ', 2, "SET 2,(IX+%d)->L" }, + { 0x00D6, 0x00ff, ' ', 2, "SET 2,(IX+%d)" }, + { 0x00D7, 0x00ff, ' ', 2, "SET 2,(IX+%d)->A" }, + { 0x00D8, 0x00ff, ' ', 2, "SET 3,(IX+%d)->B" }, + { 0x00D9, 0x00ff, ' ', 2, "SET 3,(IX+%d)->C" }, + { 0x00DA, 0x00ff, ' ', 2, "SET 3,(IX+%d)->D" }, + { 0x00DB, 0x00ff, ' ', 2, "SET 3,(IX+%d)->E" }, + { 0x00DC, 0x00ff, ' ', 2, "SET 3,(IX+%d)->H" }, + { 0x00DD, 0x00ff, ' ', 2, "SET 3,(IX+%d)->L" }, + { 0x00DE, 0x00ff, ' ', 2, "SET 3,(IX+%d)" }, + { 0x00DF, 0x00ff, ' ', 2, "SET 3,(IX+%d)->A" }, + { 0x00E0, 0x00ff, ' ', 2, "SET 4,(IX+%d)->B" }, + { 0x00E1, 0x00ff, ' ', 2, "SET 4,(IX+%d)->C" }, + { 0x00E2, 0x00ff, ' ', 2, "SET 4,(IX+%d)->D" }, + { 0x00E3, 0x00ff, ' ', 2, "SET 4,(IX+%d)->E" }, + { 0x00E4, 0x00ff, ' ', 2, "SET 4,(IX+%d)->H" }, + { 0x00E5, 0x00ff, ' ', 2, "SET 4,(IX+%d)->L" }, + { 0x00E6, 0x00ff, ' ', 2, "SET 4,(IX+%d)" }, + { 0x00E7, 0x00ff, ' ', 2, "SET 4,(IX+%d)->A" }, + { 0x00E8, 0x00ff, ' ', 2, "SET 5,(IX+%d)->B" }, + { 0x00E9, 0x00ff, ' ', 2, "SET 5,(IX+%d)->C" }, + { 0x00EA, 0x00ff, ' ', 2, "SET 5,(IX+%d)->D" }, + { 0x00EB, 0x00ff, ' ', 2, "SET 5,(IX+%d)->E" }, + { 0x00EC, 0x00ff, ' ', 2, "SET 5,(IX+%d)->H" }, + { 0x00ED, 0x00ff, ' ', 2, "SET 5,(IX+%d)->L" }, + { 0x00EE, 0x00ff, ' ', 2, "SET 5,(IX+%d)" }, + { 0x00EF, 0x00ff, ' ', 2, "SET 5,(IX+%d)->A" }, + { 0x00F0, 0x00ff, ' ', 2, "SET 6,(IX+%d)->B" }, + { 0x00F1, 0x00ff, ' ', 2, "SET 6,(IX+%d)->C" }, + { 0x00F2, 0x00ff, ' ', 2, "SET 6,(IX+%d)->D" }, + { 0x00F3, 0x00ff, ' ', 2, "SET 6,(IX+%d)->E" }, + { 0x00F4, 0x00ff, ' ', 2, "SET 6,(IX+%d)->H" }, + { 0x00F5, 0x00ff, ' ', 2, "SET 6,(IX+%d)->L" }, + { 0x00F6, 0x00ff, ' ', 2, "SET 6,(IX+%d)" }, + { 0x00F7, 0x00ff, ' ', 2, "SET 6,(IX+%d)->A" }, + { 0x00F8, 0x00ff, ' ', 2, "SET 7,(IX+%d)->B" }, + { 0x00F9, 0x00ff, ' ', 2, "SET 7,(IX+%d)->C" }, + { 0x00FA, 0x00ff, ' ', 2, "SET 7,(IX+%d)->D" }, + { 0x00FB, 0x00ff, ' ', 2, "SET 7,(IX+%d)->E" }, + { 0x00FC, 0x00ff, ' ', 2, "SET 7,(IX+%d)->H" }, + { 0x00FD, 0x00ff, ' ', 2, "SET 7,(IX+%d)->L" }, + { 0x00FE, 0x00ff, ' ', 2, "SET 7,(IX+%d)" }, + { 0x00FF, 0x00ff, ' ', 2, "SET 7,(IX+%d)->A" }, + { 0, 0, 0, 0, NULL } +}; + +struct dis_entry DISASS_NAME(_fdcb)[]= { + { 0x0000, 0x00ff, ' ', 2, "RLC (IY+%d)->B" }, + { 0x0001, 0x00ff, ' ', 2, "RLC (IY+%d)->C" }, + { 0x0002, 0x00ff, ' ', 2, "RLC (IY+%d)->D" }, + { 0x0003, 0x00ff, ' ', 2, "RLC (IY+%d)->E" }, + { 0x0004, 0x00ff, ' ', 2, "RLC (IY+%d)->H" }, + { 0x0005, 0x00ff, ' ', 2, "RLC (IY+%d)->L" }, + { 0x0006, 0x00ff, ' ', 2, "RLC (IY+%d)" }, + { 0x0007, 0x00ff, ' ', 2, "RLC (IY+%d)->A" }, + { 0x0008, 0x00ff, ' ', 2, "RRC (IY+%d)->B" }, + { 0x0009, 0x00ff, ' ', 2, "RRC (IY+%d)->C" }, + { 0x000A, 0x00ff, ' ', 2, "RRC (IY+%d)->D" }, + { 0x000B, 0x00ff, ' ', 2, "RRC (IY+%d)->E" }, + { 0x000C, 0x00ff, ' ', 2, "RRC (IY+%d)->H" }, + { 0x000D, 0x00ff, ' ', 2, "RRC (IY+%d)->L" }, + { 0x000E, 0x00ff, ' ', 2, "RRC (IY+%d)" }, + { 0x000F, 0x00ff, ' ', 2, "RRC (IY+%d)->A" }, + { 0x0010, 0x00ff, ' ', 2, "RL (IY+%d)->B" }, + { 0x0011, 0x00ff, ' ', 2, "RL (IY+%d)->C" }, + { 0x0012, 0x00ff, ' ', 2, "RL (IY+%d)->D" }, + { 0x0013, 0x00ff, ' ', 2, "RL (IY+%d)->E" }, + { 0x0014, 0x00ff, ' ', 2, "RL (IY+%d)->H" }, + { 0x0015, 0x00ff, ' ', 2, "RL (IY+%d)->L" }, + { 0x0016, 0x00ff, ' ', 2, "RL (IY+%d)" }, + { 0x0017, 0x00ff, ' ', 2, "RL (IY+%d)->A" }, + { 0x0018, 0x00ff, ' ', 2, "RR (IY+%d)->B" }, + { 0x0019, 0x00ff, ' ', 2, "RR (IY+%d)->C" }, + { 0x001A, 0x00ff, ' ', 2, "RR (IY+%d)->D" }, + { 0x001B, 0x00ff, ' ', 2, "RR (IY+%d)->E" }, + { 0x001C, 0x00ff, ' ', 2, "RR (IY+%d)->H" }, + { 0x001D, 0x00ff, ' ', 2, "RR (IY+%d)->L" }, + { 0x001E, 0x00ff, ' ', 2, "RR (IY+%d)" }, + { 0x001F, 0x00ff, ' ', 2, "RR (IY+%d)->A" }, + { 0x0020, 0x00ff, ' ', 2, "SLA (IY+%d)->B" }, + { 0x0021, 0x00ff, ' ', 2, "SLA (IY+%d)->C" }, + { 0x0022, 0x00ff, ' ', 2, "SLA (IY+%d)->D" }, + { 0x0023, 0x00ff, ' ', 2, "SLA (IY+%d)->E" }, + { 0x0024, 0x00ff, ' ', 2, "SLA (IY+%d)->H" }, + { 0x0025, 0x00ff, ' ', 2, "SLA (IY+%d)->L" }, + { 0x0026, 0x00ff, ' ', 2, "SLA (IY+%d)" }, + { 0x0027, 0x00ff, ' ', 2, "SLA (IY+%d)->A" }, + { 0x0028, 0x00ff, ' ', 2, "SRA (IY+%d)->B" }, + { 0x0029, 0x00ff, ' ', 2, "SRA (IY+%d)->C" }, + { 0x002A, 0x00ff, ' ', 2, "SRA (IY+%d)->D" }, + { 0x002B, 0x00ff, ' ', 2, "SRA (IY+%d)->E" }, + { 0x002C, 0x00ff, ' ', 2, "SRA (IY+%d)->H" }, + { 0x002D, 0x00ff, ' ', 2, "SRA (IY+%d)->L" }, + { 0x002E, 0x00ff, ' ', 2, "SRA (IY+%d)" }, + { 0x002F, 0x00ff, ' ', 2, "SRA (IY+%d)->A" }, + { 0x0030, 0x00ff, ' ', 2, "SLIA (IY+%d)->B" }, + { 0x0031, 0x00ff, ' ', 2, "SLIA (IY+%d)->C" }, + { 0x0032, 0x00ff, ' ', 2, "SLIA (IY+%d)->D" }, + { 0x0033, 0x00ff, ' ', 2, "SLIA (IY+%d)->E" }, + { 0x0034, 0x00ff, ' ', 2, "SLIA (IY+%d)->H" }, + { 0x0035, 0x00ff, ' ', 2, "SLIA (IY+%d)->L" }, + { 0x0036, 0x00ff, ' ', 2, "SLIA (IY+%d)" }, + { 0x0037, 0x00ff, ' ', 2, "SLIA (IY+%d)->A" }, + { 0x0038, 0x00ff, ' ', 2, "SRL (IY+%d)->B" }, + { 0x0039, 0x00ff, ' ', 2, "SRL (IY+%d)->C" }, + { 0x003A, 0x00ff, ' ', 2, "SRL (IY+%d)->D" }, + { 0x003B, 0x00ff, ' ', 2, "SRL (IY+%d)->E" }, + { 0x003C, 0x00ff, ' ', 2, "SRL (IY+%d)->H" }, + { 0x003D, 0x00ff, ' ', 2, "SRL (IY+%d)->L" }, + { 0x003E, 0x00ff, ' ', 2, "SRL (IY+%d)" }, + { 0x003F, 0x00ff, ' ', 2, "SRL A" }, + { 0x0040, 0x00ff, ' ', 2, "BIT (IY+%d)->0,B" }, + { 0x0041, 0x00ff, ' ', 2, "BIT (IY+%d)->0,C" }, + { 0x0042, 0x00ff, ' ', 2, "BIT (IY+%d)->0,D" }, + { 0x0043, 0x00ff, ' ', 2, "BIT (IY+%d)->0,E" }, + { 0x0044, 0x00ff, ' ', 2, "BIT (IY+%d)->0,H" }, + { 0x0045, 0x00ff, ' ', 2, "BIT (IY+%d)->0,L" }, + { 0x0046, 0x00ff, ' ', 2, "BIT 0,(IY+%d)" }, + { 0x004E, 0x00ff, ' ', 2, "BIT 1,(IY+%d)" }, + { 0x0056, 0x00ff, ' ', 2, "BIT 2,(IY+%d)" }, + { 0x005E, 0x00ff, ' ', 2, "BIT 3,(IY+%d)" }, + { 0x0066, 0x00ff, ' ', 2, "BIT 4,(IY+%d)" }, + { 0x006E, 0x00ff, ' ', 2, "BIT 5,(IY+%d)" }, + { 0x0076, 0x00ff, ' ', 2, "BIT 6,(IY+%d)" }, + { 0x007E, 0x00ff, ' ', 2, "BIT 7,(IY+%d)" }, + { 0x0080, 0x00ff, ' ', 2, "RES 0,(IY+%d)->B" }, + { 0x0081, 0x00ff, ' ', 2, "RES 0,(IY+%d)->C" }, + { 0x0082, 0x00ff, ' ', 2, "RES 0,(IY+%d)->D" }, + { 0x0083, 0x00ff, ' ', 2, "RES 0,(IY+%d)->E" }, + { 0x0084, 0x00ff, ' ', 2, "RES 0,(IY+%d)->H" }, + { 0x0085, 0x00ff, ' ', 2, "RES 0,(IY+%d)->L" }, + { 0x0086, 0x00ff, ' ', 2, "RES 0,(IY+%d)" }, + { 0x0087, 0x00ff, ' ', 2, "RES 0,(IY+%d)->A" }, + { 0x0088, 0x00ff, ' ', 2, "RES 1,(IY+%d)->B" }, + { 0x0089, 0x00ff, ' ', 2, "RES 1,(IY+%d)->C" }, + { 0x008A, 0x00ff, ' ', 2, "RES 1,(IY+%d)->D" }, + { 0x008B, 0x00ff, ' ', 2, "RES 1,(IY+%d)->E" }, + { 0x008C, 0x00ff, ' ', 2, "RES 1,(IY+%d)->H" }, + { 0x008D, 0x00ff, ' ', 2, "RES 1,(IY+%d)->L" }, + { 0x008E, 0x00ff, ' ', 2, "RES 1,(IY+%d)" }, + { 0x008F, 0x00ff, ' ', 2, "RES 1,(IY+%d)->A" }, + { 0x0090, 0x00ff, ' ', 2, "RES 2,(IY+%d)->B" }, + { 0x0091, 0x00ff, ' ', 2, "RES 2,(IY+%d)->C" }, + { 0x0092, 0x00ff, ' ', 2, "RES 2,(IY+%d)->D" }, + { 0x0093, 0x00ff, ' ', 2, "RES 2,(IY+%d)->E" }, + { 0x0094, 0x00ff, ' ', 2, "RES 2,(IY+%d)->H" }, + { 0x0095, 0x00ff, ' ', 2, "RES 2,(IY+%d)->L" }, + { 0x0096, 0x00ff, ' ', 2, "RES 2,(IY+%d)" }, + { 0x0097, 0x00ff, ' ', 2, "RES 2,(IY+%d)->A" }, + { 0x0098, 0x00ff, ' ', 2, "RES 3,(IY+%d)->B" }, + { 0x0099, 0x00ff, ' ', 2, "RES 3,(IY+%d)->C" }, + { 0x009A, 0x00ff, ' ', 2, "RES 3,(IY+%d)->D" }, + { 0x009B, 0x00ff, ' ', 2, "RES 3,(IY+%d)->E" }, + { 0x009C, 0x00ff, ' ', 2, "RES 3,(IY+%d)->H" }, + { 0x009D, 0x00ff, ' ', 2, "RES 3,(IY+%d)->L" }, + { 0x009E, 0x00ff, ' ', 2, "RES 3,(IY+%d)" }, + { 0x009F, 0x00ff, ' ', 2, "RES 3,(IY+%d)->A" }, + { 0x00A0, 0x00ff, ' ', 2, "RES 4,(IY+%d)->B" }, + { 0x00A1, 0x00ff, ' ', 2, "RES 4,(IY+%d)->C" }, + { 0x00A2, 0x00ff, ' ', 2, "RES 4,(IY+%d)->D" }, + { 0x00A3, 0x00ff, ' ', 2, "RES 4,(IY+%d)->E" }, + { 0x00A4, 0x00ff, ' ', 2, "RES 4,(IY+%d)->H" }, + { 0x00A5, 0x00ff, ' ', 2, "RES 4,(IY+%d)->L" }, + { 0x00A6, 0x00ff, ' ', 2, "RES 4,(IY+%d)" }, + { 0x00A7, 0x00ff, ' ', 2, "RES 4,(IY+%d)->A" }, + { 0x00A8, 0x00ff, ' ', 2, "RES 5,(IY+%d)->B" }, + { 0x00A9, 0x00ff, ' ', 2, "RES 5,(IY+%d)->C" }, + { 0x00AA, 0x00ff, ' ', 2, "RES 5,(IY+%d)->D" }, + { 0x00AB, 0x00ff, ' ', 2, "RES 5,(IY+%d)->E" }, + { 0x00AC, 0x00ff, ' ', 2, "RES 5,(IY+%d)->H" }, + { 0x00AD, 0x00ff, ' ', 2, "RES 5,(IY+%d)->L" }, + { 0x00AE, 0x00ff, ' ', 2, "RES 5,(IY+%d)" }, + { 0x00AF, 0x00ff, ' ', 2, "RES 5,(IY+%d)->A" }, + { 0x00B0, 0x00ff, ' ', 2, "RES 6,(IY+%d)->B" }, + { 0x00B1, 0x00ff, ' ', 2, "RES 6,(IY+%d)->C" }, + { 0x00B2, 0x00ff, ' ', 2, "RES 6,(IY+%d)->D" }, + { 0x00B3, 0x00ff, ' ', 2, "RES 6,(IY+%d)->E" }, + { 0x00B4, 0x00ff, ' ', 2, "RES 6,(IY+%d)->H" }, + { 0x00B5, 0x00ff, ' ', 2, "RES 6,(IY+%d)->L" }, + { 0x00B6, 0x00ff, ' ', 2, "RES 6,(IY+%d)" }, + { 0x00B7, 0x00ff, ' ', 2, "RES 6,(IY+%d)->A" }, + { 0x00B8, 0x00ff, ' ', 2, "RES 7,(IY+%d)->B" }, + { 0x00B9, 0x00ff, ' ', 2, "RES 7,(IY+%d)->C" }, + { 0x00BA, 0x00ff, ' ', 2, "RES 7,(IY+%d)->D" }, + { 0x00BB, 0x00ff, ' ', 2, "RES 7,(IY+%d)->E" }, + { 0x00BC, 0x00ff, ' ', 2, "RES 7,(IY+%d)->H" }, + { 0x00BD, 0x00ff, ' ', 2, "RES 7,(IY+%d)->L" }, + { 0x00BE, 0x00ff, ' ', 2, "RES 7,(IY+%d)" }, + { 0x00BF, 0x00ff, ' ', 2, "RES 7,(IY+%d)->A" }, + { 0x00C0, 0x00ff, ' ', 2, "SET 0,(IY+%d)->B" }, + { 0x00C1, 0x00ff, ' ', 2, "SET 0,(IY+%d)->C" }, + { 0x00C2, 0x00ff, ' ', 2, "SET 0,(IY+%d)->D" }, + { 0x00C3, 0x00ff, ' ', 2, "SET 0,(IY+%d)->E" }, + { 0x00C4, 0x00ff, ' ', 2, "SET 0,(IY+%d)->H" }, + { 0x00C5, 0x00ff, ' ', 2, "SET 0,(IY+%d)->L" }, + { 0x00C6, 0x00ff, ' ', 2, "SET 0,(IY+%d)" }, + { 0x00C7, 0x00ff, ' ', 2, "SET 0,(IY+%d)->A" }, + { 0x00C8, 0x00ff, ' ', 2, "SET 1,(IY+%d)->B" }, + { 0x00C9, 0x00ff, ' ', 2, "SET 1,(IY+%d)->C" }, + { 0x00CA, 0x00ff, ' ', 2, "SET 1,(IY+%d)->D" }, + { 0x00CB, 0x00ff, ' ', 2, "SET 1,(IY+%d)->E" }, + { 0x00CC, 0x00ff, ' ', 2, "SET 1,(IY+%d)->H" }, + { 0x00CD, 0x00ff, ' ', 2, "SET 1,(IY+%d)->L" }, + { 0x00CE, 0x00ff, ' ', 2, "SET 1,(IY+%d)" }, + { 0x00CF, 0x00ff, ' ', 2, "SET 1,(IY+%d)->A" }, + { 0x00D0, 0x00ff, ' ', 2, "SET 2,(IY+%d)->B" }, + { 0x00D1, 0x00ff, ' ', 2, "SET 2,(IY+%d)->C" }, + { 0x00D2, 0x00ff, ' ', 2, "SET 2,(IY+%d)->D" }, + { 0x00D3, 0x00ff, ' ', 2, "SET 2,(IY+%d)->E" }, + { 0x00D4, 0x00ff, ' ', 2, "SET 2,(IY+%d)->H" }, + { 0x00D5, 0x00ff, ' ', 2, "SET 2,(IY+%d)->L" }, + { 0x00D6, 0x00ff, ' ', 2, "SET 2,(IY+%d)" }, + { 0x00D7, 0x00ff, ' ', 2, "SET 2,(IY+%d)->A" }, + { 0x00D8, 0x00ff, ' ', 2, "SET 3,(IY+%d)->B" }, + { 0x00D9, 0x00ff, ' ', 2, "SET 3,(IY+%d)->C" }, + { 0x00DA, 0x00ff, ' ', 2, "SET 3,(IY+%d)->D" }, + { 0x00DB, 0x00ff, ' ', 2, "SET 3,(IY+%d)->E" }, + { 0x00DC, 0x00ff, ' ', 2, "SET 3,(IY+%d)->H" }, + { 0x00DD, 0x00ff, ' ', 2, "SET 3,(IY+%d)->L" }, + { 0x00DE, 0x00ff, ' ', 2, "SET 3,(IY+%d)" }, + { 0x00DF, 0x00ff, ' ', 2, "SET 3,(IY+%d)->A" }, + { 0x00E0, 0x00ff, ' ', 2, "SET 4,(IY+%d)->B" }, + { 0x00E1, 0x00ff, ' ', 2, "SET 4,(IY+%d)->C" }, + { 0x00E2, 0x00ff, ' ', 2, "SET 4,(IY+%d)->D" }, + { 0x00E3, 0x00ff, ' ', 2, "SET 4,(IY+%d)->E" }, + { 0x00E4, 0x00ff, ' ', 2, "SET 4,(IY+%d)->H" }, + { 0x00E5, 0x00ff, ' ', 2, "SET 4,(IY+%d)->L" }, + { 0x00E6, 0x00ff, ' ', 2, "SET 4,(IY+%d)" }, + { 0x00E7, 0x00ff, ' ', 2, "SET 4,(IY+%d)->A" }, + { 0x00E8, 0x00ff, ' ', 2, "SET 5,(IY+%d)->B" }, + { 0x00E9, 0x00ff, ' ', 2, "SET 5,(IY+%d)->C" }, + { 0x00EA, 0x00ff, ' ', 2, "SET 5,(IY+%d)->D" }, + { 0x00EB, 0x00ff, ' ', 2, "SET 5,(IY+%d)->E" }, + { 0x00EC, 0x00ff, ' ', 2, "SET 5,(IY+%d)->H" }, + { 0x00ED, 0x00ff, ' ', 2, "SET 5,(IY+%d)->L" }, + { 0x00EE, 0x00ff, ' ', 2, "SET 5,(IY+%d)" }, + { 0x00EF, 0x00ff, ' ', 2, "SET 5,(IY+%d)->A" }, + { 0x00F0, 0x00ff, ' ', 2, "SET 6,(IY+%d)->B" }, + { 0x00F1, 0x00ff, ' ', 2, "SET 6,(IY+%d)->C" }, + { 0x00F2, 0x00ff, ' ', 2, "SET 6,(IY+%d)->D" }, + { 0x00F3, 0x00ff, ' ', 2, "SET 6,(IY+%d)->E" }, + { 0x00F4, 0x00ff, ' ', 2, "SET 6,(IY+%d)->H" }, + { 0x00F5, 0x00ff, ' ', 2, "SET 6,(IY+%d)->L" }, + { 0x00F6, 0x00ff, ' ', 2, "SET 6,(IY+%d)" }, + { 0x00F7, 0x00ff, ' ', 2, "SET 6,(IY+%d)->A" }, + { 0x00F8, 0x00ff, ' ', 2, "SET 7,(IY+%d)->B" }, + { 0x00F9, 0x00ff, ' ', 2, "SET 7,(IY+%d)->C" }, + { 0x00FA, 0x00ff, ' ', 2, "SET 7,(IY+%d)->D" }, + { 0x00FB, 0x00ff, ' ', 2, "SET 7,(IY+%d)->E" }, + { 0x00FC, 0x00ff, ' ', 2, "SET 7,(IY+%d)->H" }, + { 0x00FD, 0x00ff, ' ', 2, "SET 7,(IY+%d)->L" }, + { 0x00FE, 0x00ff, ' ', 2, "SET 7,(IY+%d)" }, + { 0x00FF, 0x00ff, ' ', 2, "SET 7,(IY+%d)->A" }, + { 0, 0, 0, 0, NULL } +}; + +/* glob.cc */ diff --git a/sim/ucsim/z80.src/glob.h b/sim/ucsim/z80.src/glob.h new file mode 100644 index 0000000..b27011f --- /dev/null +++ b/sim/ucsim/z80.src/glob.h @@ -0,0 +1,57 @@ +/* + * Simulator of microcontrollers (glob.h) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#ifndef GLOB_HEADER +#define GLOB_HEADER + +#include "stypes.h" + +extern struct dis_entry disass_z80[]; + +extern struct dis_entry disass_z80_ed[]; +extern struct dis_entry disass_z80_cb[]; +extern struct dis_entry disass_z80_dd[]; +extern struct dis_entry disass_z80_fd[]; +extern struct dis_entry disass_z80_ddcb[]; +extern struct dis_entry disass_z80_fdcb[]; + + +extern struct dis_entry disass_r2k[]; + +extern struct dis_entry disass_r2k_ed[]; +extern struct dis_entry disass_r2k_cb[]; +extern struct dis_entry disass_r2k_dd[]; +extern struct dis_entry disass_r2k_fd[]; +extern struct dis_entry disass_r2k_ddcb[]; +extern struct dis_entry disass_r2k_fdcb[]; + +extern struct dis_entry disass_lr35902[]; +extern struct dis_entry disass_lr35902_cb[]; + +#endif + +/* End of z80.src/glob.h */ diff --git a/sim/ucsim/z80.src/glob_lr35902.cc b/sim/ucsim/z80.src/glob_lr35902.cc new file mode 100755 index 0000000..0f2fc91 --- /dev/null +++ b/sim/ucsim/z80.src/glob_lr35902.cc @@ -0,0 +1,596 @@ +/*
+ * Disassembly table for LR35902, a Z-80 derivative used
+ * by the Gameboy (glob_lr35902.cc)
+ *
+ */
+/* Derived from z80 glob.cc by Leland Morrison 2011 */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+ UCSIM is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
+
+ UCSIM is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with UCSIM; see the file COPYING. If not, write to the Free
+ Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+ 02111-1307, USA.
+*/
+/*@1@*/
+#include <stdio.h>
+
+#include "stypes.h"
+
+#define DISASS_NAME(X) disass_lr35902##X
+
+
+/*
+%d - signed compl.,byte jump
+%w - 2-byte jump or imm. value
+%b - byte imm. value
+ */
+/* uint code, mask; char branch; uchar length; char *mnemonic; */
+
+struct dis_entry /*DISASS_NAME()*/disass_lr35902 []= {
+ { 0x0000, 0x00ff, ' ', 1, "NOP" },
+ { 0x0001, 0x00ff, ' ', 3, "LD BC,%w" },
+ { 0x0002, 0x00ff, ' ', 1, "LD (BC),A" },
+ { 0x0003, 0x00ff, ' ', 1, "INC BC" },
+ { 0x0004, 0x00ff, ' ', 1, "INC B" },
+ { 0x0005, 0x00ff, ' ', 1, "DEC B" },
+ { 0x0006, 0x00ff, ' ', 2, "LD b,%b" },
+ { 0x0007, 0x00ff, ' ', 1, "RLCA" },
+
+ { 0x0008, 0x00ff, ' ', 3, "LD (%w),SP" }, // unique to LR35902
+ { 0x0009, 0x00ff, ' ', 1, "ADD HL,BC" },
+ { 0x000a, 0x00ff, ' ', 1, "LD A,(BC)" },
+ { 0x000b, 0x00ff, ' ', 1, "DEC BC" },
+ { 0x000c, 0x00ff, ' ', 1, "INC C" },
+ { 0x000d, 0x00ff, ' ', 1, "DEC C" },
+ { 0x000e, 0x00ff, ' ', 2, "LD C,%b" },
+ { 0x000f, 0x00ff, ' ', 1, "RRCA" },
+
+#if 1
+ { 0x0010, 0x00ff, ' ', 2, "STOP 0" }, // unique to LR35902
+#else
+ { 0x0010, 0x00ff, 'R', 2, "DJNZ %d" },
+#endif
+ { 0x0011, 0x00ff, ' ', 3, "LD DE,%w" },
+ { 0x0012, 0x00ff, ' ', 1, "LD (DE),A" },
+ { 0x0013, 0x00ff, ' ', 1, "INC DE" },
+ { 0x0014, 0x00ff, ' ', 1, "INC D" },
+ { 0x0015, 0x00ff, ' ', 1, "DEC D" },
+ { 0x0016, 0x00ff, ' ', 2, "LD D,%b" },
+ { 0x0017, 0x00ff, ' ', 1, "RLA" },
+
+ { 0x0018, 0x00ff, 'R', 2, "JR %d" },
+ { 0x0019, 0x00ff, ' ', 3, "ADD HL,DE" },
+ { 0x001a, 0x00ff, ' ', 1, "LD A,(DE)" },
+ { 0x001b, 0x00ff, ' ', 1, "DEC DE" },
+ { 0x001c, 0x00ff, ' ', 1, "INC E" },
+ { 0x001d, 0x00ff, ' ', 1, "DEC E" },
+ { 0x001e, 0x00ff, ' ', 2, "LD E,%b" },
+ { 0x001f, 0x00ff, ' ', 1, "RRA" },
+
+ { 0x0020, 0x00ff, 'R', 2, "JR NZ,%d" },
+ { 0x0021, 0x00ff, ' ', 3, "LD HL,%w" },
+ { 0x0022, 0x00ff, ' ', 1, "LDI (HL),A" },// unique to LR35902
+ { 0x0023, 0x00ff, ' ', 1, "INC HL" },
+ { 0x0024, 0x00ff, ' ', 1, "INC H" },
+ { 0x0025, 0x00ff, ' ', 1, "DEC H" },
+ { 0x0026, 0x00ff, ' ', 2, "LD H,%b" },
+ { 0x0027, 0x00ff, ' ', 1, "DAA" },
+
+ { 0x0028, 0x00ff, 'R', 2, "JR Z,%d" },
+ { 0x0029, 0x00ff, ' ', 1, "ADD HL,HL" },
+ { 0x002a, 0x00ff, ' ', 1, "LDI A,(HL)" },// unique to LR35902
+ { 0x002b, 0x00ff, ' ', 1, "DEC HL" },
+ { 0x002c, 0x00ff, ' ', 1, "INC L" },
+ { 0x002d, 0x00ff, ' ', 1, "DEC L" },
+ { 0x002e, 0x00ff, ' ', 2, "LD L, %b" },
+ { 0x002f, 0x00ff, ' ', 1, "CPL" },
+
+ { 0x0030, 0x00ff, 'R', 2, "JR NC,%d" },
+ { 0x0031, 0x00ff, ' ', 3, "LD SP,%w" },
+ { 0x0032, 0x00ff, ' ', 1, "LDD (HL),A" }, // unique to LR35902
+ { 0x0033, 0x00ff, ' ', 1, "INC SP" },
+ { 0x0034, 0x00ff, ' ', 1, "INC (HL)" },
+ { 0x0035, 0x00ff, ' ', 1, "DEC (HL)" },
+ { 0x0036, 0x00ff, ' ', 2, "LD (HL),%b" },
+ { 0x0037, 0x00ff, ' ', 1, "SCF" },
+
+ { 0x0038, 0x00ff, 'R', 2, "JR C,%d" },
+ { 0x0039, 0x00ff, ' ', 1, "ADD HL,SP" },
+ { 0x003a, 0x00ff, ' ', 1, "LDD A,(HL)" }, // unique to LR35902
+ { 0x003b, 0x00ff, ' ', 1, "DEC SP" },
+ { 0x003c, 0x00ff, ' ', 1, "INC A" },
+ { 0x003d, 0x00ff, ' ', 1, "DEC A" },
+ { 0x003e, 0x00ff, ' ', 2, "LD A,%b" },
+ { 0x003f, 0x00ff, ' ', 1, "CCF" },
+
+ { 0x0040, 0x00ff, ' ', 1, "LD B,B" },
+ { 0x0041, 0x00ff, ' ', 1, "LD B,C" },
+ { 0x0042, 0x00ff, ' ', 1, "LD B,D" },
+ { 0x0043, 0x00ff, ' ', 1, "LD B,E" },
+ { 0x0044, 0x00ff, ' ', 1, "LD B,H" },
+ { 0x0045, 0x00ff, ' ', 1, "LD B,L" },
+ { 0x0046, 0x00ff, ' ', 1, "LD B,(HL)" },
+ { 0x0047, 0x00ff, ' ', 1, "LD B,a" },
+
+ { 0x0048, 0x00ff, ' ', 1, "LD C,B" },
+ { 0x0049, 0x00ff, ' ', 1, "LD C,C" },
+ { 0x004a, 0x00ff, ' ', 1, "LD C,D" },
+ { 0x004b, 0x00ff, ' ', 1, "LD C,E" },
+ { 0x004c, 0x00ff, ' ', 1, "LD C,H" },
+ { 0x004d, 0x00ff, ' ', 1, "LD C,L" },
+ { 0x004e, 0x00ff, ' ', 1, "LD C,(HL)" },
+ { 0x004f, 0x00ff, ' ', 1, "LD C,A" },
+
+ { 0x0050, 0x00ff, ' ', 1, "LD D,B" },
+ { 0x0051, 0x00ff, ' ', 1, "LD D,C" },
+ { 0x0052, 0x00ff, ' ', 1, "LD D,D" },
+ { 0x0053, 0x00ff, ' ', 1, "LD D,E" },
+ { 0x0054, 0x00ff, ' ', 1, "LD D,H" },
+ { 0x0055, 0x00ff, ' ', 1, "LD D,L" },
+ { 0x0056, 0x00ff, ' ', 1, "LD D,(HL)" },
+ { 0x0057, 0x00ff, ' ', 1, "LD D,A" },
+
+ { 0x0058, 0x00ff, ' ', 1, "LD E,B" },
+ { 0x0059, 0x00ff, ' ', 1, "LD E,C" },
+ { 0x005a, 0x00ff, ' ', 1, "LD E,D" },
+ { 0x005b, 0x00ff, ' ', 1, "LD E,E" },
+ { 0x005c, 0x00ff, ' ', 1, "LD E,H" },
+ { 0x005d, 0x00ff, ' ', 1, "LD E,L" },
+ { 0x005e, 0x00ff, ' ', 1, "LD E,(HL)" },
+ { 0x005f, 0x00ff, ' ', 1, "LD E,A" },
+
+ { 0x0060, 0x00ff, ' ', 1, "LD H,B" },
+ { 0x0061, 0x00ff, ' ', 1, "LD H,C" },
+ { 0x0062, 0x00ff, ' ', 1, "LD H,D" },
+ { 0x0063, 0x00ff, ' ', 1, "LD H,E" },
+ { 0x0064, 0x00ff, ' ', 1, "LD H,H" },
+ { 0x0065, 0x00ff, ' ', 1, "LD H,L" },
+ { 0x0066, 0x00ff, ' ', 1, "LD H,(HL)" },
+ { 0x0067, 0x00ff, ' ', 1, "LD H,A" },
+
+ { 0x0068, 0x00ff, ' ', 1, "LD L,B" },
+ { 0x0069, 0x00ff, ' ', 1, "LD L,C" },
+ { 0x006a, 0x00ff, ' ', 1, "LD L,D" },
+ { 0x006b, 0x00ff, ' ', 1, "LD L,E" },
+ { 0x006c, 0x00ff, ' ', 1, "LD L,H" },
+ { 0x006d, 0x00ff, ' ', 1, "LD L,L" },
+ { 0x006e, 0x00ff, ' ', 1, "LD L,(HL)" },
+ { 0x006f, 0x00ff, ' ', 1, "LD L,A" },
+
+ { 0x0070, 0x00ff, ' ', 1, "LD (HL),B" },
+ { 0x0071, 0x00ff, ' ', 1, "LD (HL),C" },
+ { 0x0072, 0x00ff, ' ', 1, "LD (HL),D" },
+ { 0x0073, 0x00ff, ' ', 1, "LD (HL),E" },
+ { 0x0074, 0x00ff, ' ', 1, "LD (HL),H" },
+ { 0x0075, 0x00ff, ' ', 1, "LD (HL),L" },
+ { 0x0076, 0x00ff, ' ', 1, "HALT" },
+ { 0x0077, 0x00ff, ' ', 1, "LD (HL),A" },
+
+ { 0x0078, 0x00ff, ' ', 1, "LD A,B" },
+ { 0x0079, 0x00ff, ' ', 1, "LD A,C" },
+ { 0x007a, 0x00ff, ' ', 1, "LD A,D" },
+ { 0x007b, 0x00ff, ' ', 1, "LD A,E" },
+ { 0x007c, 0x00ff, ' ', 1, "LD A,H" },
+ { 0x007d, 0x00ff, ' ', 1, "LD A,L" },
+ { 0x007e, 0x00ff, ' ', 1, "LD A,(HL)" },
+ { 0x007f, 0x00ff, ' ', 1, "LD A,A" },
+
+ { 0x0080, 0x00ff, ' ', 1, "ADD A,B" },
+ { 0x0081, 0x00ff, ' ', 1, "ADD A,C" },
+ { 0x0082, 0x00ff, ' ', 1, "ADD A,D" },
+ { 0x0083, 0x00ff, ' ', 1, "ADD A,E" },
+ { 0x0084, 0x00ff, ' ', 1, "ADD A,H" },
+ { 0x0085, 0x00ff, ' ', 1, "ADD A,L" },
+ { 0x0086, 0x00ff, ' ', 1, "ADD A,(HL)" },
+ { 0x0087, 0x00ff, ' ', 1, "ADD A,A" },
+
+ { 0x0088, 0x00ff, ' ', 1, "ADC A,B" },
+ { 0x0089, 0x00ff, ' ', 1, "ADC A,C" },
+ { 0x008a, 0x00ff, ' ', 1, "ADC A,D" },
+ { 0x008b, 0x00ff, ' ', 1, "ADC A,E" },
+ { 0x008c, 0x00ff, ' ', 1, "ADC A,H" },
+ { 0x008d, 0x00ff, ' ', 1, "ADC A,L" },
+ { 0x008e, 0x00ff, ' ', 1, "ADC A,(HL)" },
+ { 0x008f, 0x00ff, ' ', 1, "ADC A,A" },
+
+ { 0x0090, 0x00ff, ' ', 1, "SUB A,B"},
+ { 0x0091, 0x00ff, ' ', 1, "SUB A,C"},
+ { 0x0092, 0x00ff, ' ', 1, "SUB A,D"},
+ { 0x0093, 0x00ff, ' ', 1, "SUB A,E"},
+ { 0x0094, 0x00ff, ' ', 1, "SUB A,H"},
+ { 0x0095, 0x00ff, ' ', 1, "SUB A,L"},
+ { 0x0096, 0x00ff, ' ', 1, "SUB A,(HL)"},
+ { 0x0097, 0x00ff, ' ', 1, "SUB A,A"},
+
+ { 0x0098, 0x00ff, ' ', 1, "SBC A,B" },
+ { 0x0099, 0x00ff, ' ', 1, "SBC A,C" },
+ { 0x009a, 0x00ff, ' ', 1, "SBC A,D" },
+ { 0x009b, 0x00ff, ' ', 1, "SBC A,E" },
+ { 0x009c, 0x00ff, ' ', 1, "SBC A,H" },
+ { 0x009d, 0x00ff, ' ', 1, "SBC A,L" },
+ { 0x009e, 0x00ff, ' ', 1, "SBC A,(HL)" },
+ { 0x009f, 0x00ff, ' ', 1, "SBC A,A" },
+
+ { 0x00a0, 0x00ff, ' ', 1, "AND B" },
+ { 0x00a1, 0x00ff, ' ', 1, "AND C" },
+ { 0x00a2, 0x00ff, ' ', 1, "AND D" },
+ { 0x00a3, 0x00ff, ' ', 1, "AND E" },
+ { 0x00a4, 0x00ff, ' ', 1, "AND H" },
+ { 0x00a5, 0x00ff, ' ', 1, "AND L" },
+ { 0x00a6, 0x00ff, ' ', 1, "AND (HL)" },
+ { 0x00a7, 0x00ff, ' ', 1, "AND A" },
+
+ { 0x00a8, 0x00ff, ' ', 1, "XOR B" },
+ { 0x00a9, 0x00ff, ' ', 1, "XOR C" },
+ { 0x00aa, 0x00ff, ' ', 1, "XOR D" },
+ { 0x00ab, 0x00ff, ' ', 1, "XOR E" },
+ { 0x00ac, 0x00ff, ' ', 1, "XOR H" },
+ { 0x00ad, 0x00ff, ' ', 1, "XOR L" },
+ { 0x00ae, 0x00ff, ' ', 1, "XOR (HL)" },
+ { 0x00af, 0x00ff, ' ', 1, "XOR A" },
+
+ { 0x00b0, 0x00ff, ' ', 1, "OR B" },
+ { 0x00b1, 0x00ff, ' ', 1, "OR C" },
+ { 0x00b2, 0x00ff, ' ', 1, "OR D" },
+ { 0x00b3, 0x00ff, ' ', 1, "OR E" },
+ { 0x00b4, 0x00ff, ' ', 1, "OR H" },
+ { 0x00b5, 0x00ff, ' ', 1, "OR L" },
+ { 0x00b6, 0x00ff, ' ', 1, "OR (HL)" },
+ { 0x00b7, 0x00ff, ' ', 1, "OR A" },
+
+ { 0x00b8, 0x00ff, ' ', 1, "CP B" },
+ { 0x00b9, 0x00ff, ' ', 1, "CP C" },
+ { 0x00ba, 0x00ff, ' ', 1, "CP D" },
+ { 0x00bb, 0x00ff, ' ', 1, "CP E" },
+ { 0x00bc, 0x00ff, ' ', 1, "CP H" },
+ { 0x00bd, 0x00ff, ' ', 1, "CP L" },
+ { 0x00be, 0x00ff, ' ', 1, "CP (HL)" },
+ { 0x00bf, 0x00ff, ' ', 1, "CP A" },
+
+ { 0x00c0, 0x00ff, ' ', 1, "RET NZ" },
+ { 0x00c1, 0x00ff, ' ', 1, "POP BC" },
+ { 0x00c2, 0x00ff, 'A', 3, "JP NZ, %w" },
+ { 0x00c3, 0x00ff, 'A', 3, "JP %w" },
+ { 0x00c4, 0x00ff, 'l', 3, "CALL NZ,%w" },
+ { 0x00c5, 0x00ff, ' ', 1, "PUSH BC" },
+ { 0x00c6, 0x00ff, ' ', 2, "ADD A,%b" },
+ { 0x00c7, 0x00ff, ' ', 1, "RST 0" },
+
+ { 0x00c8, 0x00ff, ' ', 1, "RET Z" },
+ { 0x00c9, 0x00ff, ' ', 1, "RET" },
+ { 0x00ca, 0x00ff, 'A', 3, "JP Z,%w" },
+ { 0x00cb, 0x00ff, ' ', 2, "?cb?" }, /* ESC code to lots of op-codes, all 2-byte */
+
+ { 0x00cc, 0x00ff, 'l', 3, "CALL Z,%w" },
+ { 0x00cd, 0x00ff, 'l', 3, "CALL %w" },
+ { 0x00ce, 0x00ff, ' ', 2, "ADC A,%b" },
+ { 0x00cf, 0x00ff, ' ', 1, "RST 8" },
+
+ { 0x00d0, 0x00ff, ' ', 1, "RET NC" },
+ { 0x00d1, 0x00ff, ' ', 1, "POP DE" },
+ { 0x00d2, 0x00ff, 'A', 3, "JP NC,%w" },
+ { 0x00d3, 0x00ff, ' ', 2, "Illegal Op" }, // in/out do not exist on LR35902
+ { 0x00d4, 0x00ff, 'l', 3, "CALL NC,%w" },
+ { 0x00d5, 0x00ff, ' ', 1, "PUSH DE" },
+ { 0x00d6, 0x00ff, ' ', 2, "sub %b" },
+ { 0x00d7, 0x00ff, ' ', 1, "RST 10H" },
+
+ { 0x00d8, 0x00ff, ' ', 1, "RET C" },
+ { 0x00d9, 0x00ff, ' ', 1, "RETI" }, // unique to LR35902
+ { 0x00da, 0x00ff, 'A', 3, "JP C,%w" },
+ { 0x00db, 0x00ff, ' ', 2, "Illegal Op" }, // in/out do not exist on LR35902
+ { 0x00dc, 0x00ff, 'l', 3, "CALL C,%w" },
+ { 0x00dd, 0x00ff, ' ', 2, "Illegal Op" }, /* 0xdd - ESC codes,about 284, vary lengths, IX centric */
+ { 0x00de, 0x00ff, ' ', 2, "SBC A,%b" },
+ { 0x00df, 0x00ff, ' ', 1, "RST 18H" },
+
+ { 0x00e0, 0x00ff, ' ', 2, "LDH (0xFF00+%b),A" }, // unique to LR35902
+ { 0x00e1, 0x00ff, ' ', 1, "POP HL" },
+ { 0x00e2, 0x00ff, 'A', 2, "LD (0xFF00+C),A" }, // unique to LR35902
+ { 0x00e3, 0x00ff, ' ', 1, "Illegal Op" },
+ { 0x00e4, 0x00ff, 'l', 1, "Illegal Op" },
+ { 0x00e5, 0x00ff, ' ', 1, "PUSH HL" },
+ { 0x00e6, 0x00ff, ' ', 2, "AND %b" },
+ { 0x00e7, 0x00ff, ' ', 1, "RST 20H" },
+
+ { 0x00e8, 0x00ff, ' ', 2, "ADD SP,%d" }, // unique to LR35902
+ { 0x00e9, 0x00ff, 'A', 1, "JP (HL)" },
+ { 0x00ea, 0x00ff, ' ', 3, "LD (%w),A" }, // unique to LR35902
+ { 0x00eb, 0x00ff, ' ', 1, "Illegal Op" },
+ { 0x00ec, 0x00ff, 'l', 1, "Illegal Op" },
+ { 0x00ed, 0x00ff, ' ', 1, "Illegal Op" },
+ { 0x00ee, 0x00ff, ' ', 2, "XOR %b" },
+ { 0x00ef, 0x00ff, ' ', 1, "RST 28H" },
+
+ { 0x00f0, 0x00ff, ' ', 2, "LDH A,(0xFF00+%b)" }, // unique to LR35902
+ { 0x00f1, 0x00ff, ' ', 1, "POP AF" },
+ { 0x00f2, 0x00ff, ' ', 2, "LD A,(0xFF00+C)" }, // unique to LR35902
+ { 0x00f3, 0x00ff, ' ', 1, "DI" },
+ { 0x00f4, 0x00ff, 'l', 3, "Illegal Op" },
+ { 0x00f5, 0x00ff, ' ', 1, "PUSH AF" },
+ { 0x00f6, 0x00ff, ' ', 2, "OR %b" },
+ { 0x00f7, 0x00ff, ' ', 1, "RST 30H" },
+
+ { 0x00f8, 0x00ff, ' ', 2, "LD HL,SP+%d" }, // unique to LR35902
+ { 0x00f9, 0x00ff, ' ', 1, "LD SP,HL" },
+ { 0x00fa, 0x00ff, ' ', 3, "LD A,(%w)" }, // unique to LR35902
+ { 0x00fb, 0x00ff, ' ', 1, "EI" },
+ { 0x00fc, 0x00ff, 'l', 1, "Illegal Op" },
+ { 0x00fd, 0x00ff, ' ', 1, "Illegal Op" },
+ { 0x00fe, 0x00ff, ' ', 2, "CP %b" },
+ { 0x00ff, 0x00ff, ' ', 1, "RST 38H" },
+
+ { 0, 0, 0, 0, NULL }
+};
+
+
+struct dis_entry DISASS_NAME(_cb)[]= {
+ { 0x0000, 0x00ff, ' ', 1, "RLC B" },
+ { 0x0001, 0x00ff, ' ', 1, "RLC C" },
+ { 0x0002, 0x00ff, ' ', 1, "RLC D" },
+ { 0x0003, 0x00ff, ' ', 1, "RLC E" },
+ { 0x0004, 0x00ff, ' ', 1, "RLC H" },
+ { 0x0005, 0x00ff, ' ', 1, "RLC L" },
+ { 0x0006, 0x00ff, ' ', 1, "RLC (HL)" },
+ { 0x0007, 0x00ff, ' ', 1, "RLC A" },
+ { 0x0008, 0x00ff, ' ', 1, "RRC B" },
+ { 0x0009, 0x00ff, ' ', 1, "RRC C" },
+ { 0x000A, 0x00ff, ' ', 1, "RRC D" },
+ { 0x000B, 0x00ff, ' ', 1, "RRC E" },
+ { 0x000C, 0x00ff, ' ', 1, "RRC H" },
+ { 0x000D, 0x00ff, ' ', 1, "RRC L" },
+ { 0x000E, 0x00ff, ' ', 1, "RRC (HL)" },
+ { 0x000F, 0x00ff, ' ', 1, "RRC A" },
+ { 0x0010, 0x00ff, ' ', 1, "RL B" },
+ { 0x0011, 0x00ff, ' ', 1, "RL C" },
+ { 0x0012, 0x00ff, ' ', 1, "RL D" },
+ { 0x0013, 0x00ff, ' ', 1, "RL E" },
+ { 0x0014, 0x00ff, ' ', 1, "RL H" },
+ { 0x0015, 0x00ff, ' ', 1, "RL L" },
+ { 0x0016, 0x00ff, ' ', 1, "RL (HL)" },
+ { 0x0017, 0x00ff, ' ', 1, "RL A" },
+ { 0x0018, 0x00ff, ' ', 1, "RR B" },
+ { 0x0019, 0x00ff, ' ', 1, "RR C" },
+ { 0x001A, 0x00ff, ' ', 1, "RR D" },
+ { 0x001B, 0x00ff, ' ', 1, "RR E" },
+ { 0x001C, 0x00ff, ' ', 1, "RR H" },
+ { 0x001D, 0x00ff, ' ', 1, "RR L" },
+ { 0x001E, 0x00ff, ' ', 1, "RR (HL)" },
+ { 0x001F, 0x00ff, ' ', 1, "RR A" },
+ { 0x0020, 0x00ff, ' ', 1, "SLA B" },
+ { 0x0021, 0x00ff, ' ', 1, "SLA C" },
+ { 0x0022, 0x00ff, ' ', 1, "SLA D" },
+ { 0x0023, 0x00ff, ' ', 1, "SLA E" },
+ { 0x0024, 0x00ff, ' ', 1, "SLA H" },
+ { 0x0025, 0x00ff, ' ', 1, "SLA L" },
+ { 0x0026, 0x00ff, ' ', 1, "SLA (HL)" },
+ { 0x0027, 0x00ff, ' ', 1, "SLA A" },
+ { 0x0028, 0x00ff, ' ', 1, "SRA B" },
+ { 0x0029, 0x00ff, ' ', 1, "SRA C" },
+ { 0x002A, 0x00ff, ' ', 1, "SRA D" },
+ { 0x002B, 0x00ff, ' ', 1, "SRA E" },
+ { 0x002C, 0x00ff, ' ', 1, "SRA H" },
+ { 0x002D, 0x00ff, ' ', 1, "SRA L" },
+ { 0x002E, 0x00ff, ' ', 1, "SRA (HL)" },
+ { 0x002F, 0x00ff, ' ', 1, "SRA A" },
+ { 0x0030, 0x00ff, ' ', 1, "SWAP B" },
+ { 0x0031, 0x00ff, ' ', 1, "SWAP C" },
+ { 0x0032, 0x00ff, ' ', 1, "SWAP D" },
+ { 0x0033, 0x00ff, ' ', 1, "SWAP E" },
+ { 0x0034, 0x00ff, ' ', 1, "SWAP H" },
+ { 0x0035, 0x00ff, ' ', 1, "SWAP L" },
+ { 0x0036, 0x00ff, ' ', 1, "SWAP (HL)" },
+ { 0x0037, 0x00ff, ' ', 1, "SWAP A" },
+ { 0x0038, 0x00ff, ' ', 1, "SRL B" },
+ { 0x0039, 0x00ff, ' ', 1, "SRL C" },
+ { 0x003A, 0x00ff, ' ', 1, "SRL D" },
+ { 0x003B, 0x00ff, ' ', 1, "SRL E" },
+ { 0x003C, 0x00ff, ' ', 1, "SRL H" },
+ { 0x003D, 0x00ff, ' ', 1, "SRL L" },
+ { 0x003E, 0x00ff, ' ', 1, "SRL (HL)" },
+ { 0x003F, 0x00ff, ' ', 1, "SRL A" },
+ { 0x0040, 0x00ff, ' ', 1, "BIT 0,B" },
+ { 0x0041, 0x00ff, ' ', 1, "BIT 0,C" },
+ { 0x0042, 0x00ff, ' ', 1, "BIT 0,D" },
+ { 0x0043, 0x00ff, ' ', 1, "BIT 0,E" },
+ { 0x0044, 0x00ff, ' ', 1, "BIT 0,H" },
+ { 0x0045, 0x00ff, ' ', 1, "BIT 0,L" },
+ { 0x0046, 0x00ff, ' ', 1, "BIT 0,(HL)" },
+ { 0x0047, 0x00ff, ' ', 1, "BIT 0,A" },
+ { 0x0048, 0x00ff, ' ', 1, "BIT 1,B" },
+ { 0x0049, 0x00ff, ' ', 1, "BIT 1,C" },
+ { 0x004A, 0x00ff, ' ', 1, "BIT 1,D" },
+ { 0x004B, 0x00ff, ' ', 1, "BIT 1,E" },
+ { 0x004C, 0x00ff, ' ', 1, "BIT 1,H" },
+ { 0x004D, 0x00ff, ' ', 1, "BIT 1,L" },
+ { 0x004E, 0x00ff, ' ', 1, "BIT 1,(HL)" },
+ { 0x004F, 0x00ff, ' ', 1, "BIT 1,A" },
+ { 0x0050, 0x00ff, ' ', 1, "BIT 2,B" },
+ { 0x0051, 0x00ff, ' ', 1, "BIT 2,C" },
+ { 0x0052, 0x00ff, ' ', 1, "BIT 2,D" },
+ { 0x0053, 0x00ff, ' ', 1, "BIT 2,E" },
+ { 0x0054, 0x00ff, ' ', 1, "BIT 2,H" },
+ { 0x0055, 0x00ff, ' ', 1, "BIT 2,L" },
+ { 0x0056, 0x00ff, ' ', 1, "BIT 2,(HL)" },
+ { 0x0057, 0x00ff, ' ', 1, "BIT 2,A" },
+ { 0x0058, 0x00ff, ' ', 1, "BIT 3,B" },
+ { 0x0059, 0x00ff, ' ', 1, "BIT 3,C" },
+ { 0x005A, 0x00ff, ' ', 1, "BIT 3,D" },
+ { 0x005B, 0x00ff, ' ', 1, "BIT 3,E" },
+ { 0x005C, 0x00ff, ' ', 1, "BIT 3,H" },
+ { 0x005D, 0x00ff, ' ', 1, "BIT 3,L" },
+ { 0x005E, 0x00ff, ' ', 1, "BIT 3,(HL)" },
+ { 0x005F, 0x00ff, ' ', 1, "BIT 3,A" },
+ { 0x0060, 0x00ff, ' ', 1, "BIT 4,B" },
+ { 0x0061, 0x00ff, ' ', 1, "BIT 4,C" },
+ { 0x0062, 0x00ff, ' ', 1, "BIT 4,D" },
+ { 0x0063, 0x00ff, ' ', 1, "BIT 4,E" },
+ { 0x0064, 0x00ff, ' ', 1, "BIT 4,H" },
+ { 0x0065, 0x00ff, ' ', 1, "BIT 4,L" },
+ { 0x0066, 0x00ff, ' ', 1, "BIT 4,(HL)" },
+ { 0x0067, 0x00ff, ' ', 1, "BIT 4,A" },
+ { 0x0068, 0x00ff, ' ', 1, "BIT 5,B" },
+ { 0x0069, 0x00ff, ' ', 1, "BIT 5,C" },
+ { 0x006A, 0x00ff, ' ', 1, "BIT 5,D" },
+ { 0x006B, 0x00ff, ' ', 1, "BIT 5,E" },
+ { 0x006C, 0x00ff, ' ', 1, "BIT 5,H" },
+ { 0x006D, 0x00ff, ' ', 1, "BIT 5,L" },
+ { 0x006E, 0x00ff, ' ', 1, "BIT 5,(HL)" },
+ { 0x006F, 0x00ff, ' ', 1, "BIT 5,A" },
+ { 0x0070, 0x00ff, ' ', 1, "BIT 6,B" },
+ { 0x0071, 0x00ff, ' ', 1, "BIT 6,C" },
+ { 0x0072, 0x00ff, ' ', 1, "BIT 6,D" },
+ { 0x0073, 0x00ff, ' ', 1, "BIT 6,E" },
+ { 0x0074, 0x00ff, ' ', 1, "BIT 6,H" },
+ { 0x0075, 0x00ff, ' ', 1, "BIT 6,L" },
+ { 0x0076, 0x00ff, ' ', 1, "BIT 6,(HL)" },
+ { 0x0077, 0x00ff, ' ', 1, "BIT 6,A" },
+ { 0x0078, 0x00ff, ' ', 1, "BIT 7,B" },
+ { 0x0079, 0x00ff, ' ', 1, "BIT 7,C" },
+ { 0x007A, 0x00ff, ' ', 1, "BIT 7,D" },
+ { 0x007B, 0x00ff, ' ', 1, "BIT 7,E" },
+ { 0x007C, 0x00ff, ' ', 1, "BIT 7,H" },
+ { 0x007D, 0x00ff, ' ', 1, "BIT 7,L" },
+ { 0x007E, 0x00ff, ' ', 1, "BIT 7,(HL)" },
+ { 0x007F, 0x00ff, ' ', 1, "BIT 7,A" },
+ { 0x0080, 0x00ff, ' ', 1, "RES 0,B" },
+ { 0x0081, 0x00ff, ' ', 1, "RES 0,C" },
+ { 0x0082, 0x00ff, ' ', 1, "RES 0,D" },
+ { 0x0083, 0x00ff, ' ', 1, "RES 0,E" },
+ { 0x0084, 0x00ff, ' ', 1, "RES 0,H" },
+ { 0x0085, 0x00ff, ' ', 1, "RES 0,L" },
+ { 0x0086, 0x00ff, ' ', 1, "RES 0,(HL)" },
+ { 0x0087, 0x00ff, ' ', 1, "RES 0,A" },
+ { 0x0088, 0x00ff, ' ', 1, "RES 1,B" },
+ { 0x0089, 0x00ff, ' ', 1, "RES 1,C" },
+ { 0x008A, 0x00ff, ' ', 1, "RES 1,D" },
+ { 0x008B, 0x00ff, ' ', 1, "RES 1,E" },
+ { 0x008C, 0x00ff, ' ', 1, "RES 1,H" },
+ { 0x008D, 0x00ff, ' ', 1, "RES 1,L" },
+ { 0x008E, 0x00ff, ' ', 1, "RES 1,(HL)" },
+ { 0x008F, 0x00ff, ' ', 1, "RES 1,A" },
+ { 0x0090, 0x00ff, ' ', 1, "RES 2,B" },
+ { 0x0091, 0x00ff, ' ', 1, "RES 2,C" },
+ { 0x0092, 0x00ff, ' ', 1, "RES 2,D" },
+ { 0x0093, 0x00ff, ' ', 1, "RES 2,E" },
+ { 0x0094, 0x00ff, ' ', 1, "RES 2,H" },
+ { 0x0095, 0x00ff, ' ', 1, "RES 2,L" },
+ { 0x0096, 0x00ff, ' ', 1, "RES 2,(HL)" },
+ { 0x0097, 0x00ff, ' ', 1, "RES 2,A" },
+ { 0x0098, 0x00ff, ' ', 1, "RES 3,B" },
+ { 0x0099, 0x00ff, ' ', 1, "RES 3,C" },
+ { 0x009A, 0x00ff, ' ', 1, "RES 3,D" },
+ { 0x009B, 0x00ff, ' ', 1, "RES 3,E" },
+ { 0x009C, 0x00ff, ' ', 1, "RES 3,H" },
+ { 0x009D, 0x00ff, ' ', 1, "RES 3,L" },
+ { 0x009E, 0x00ff, ' ', 1, "RES 3,(HL)" },
+ { 0x009F, 0x00ff, ' ', 1, "RES 3,A" },
+ { 0x00A0, 0x00ff, ' ', 1, "RES 4,B" },
+ { 0x00A1, 0x00ff, ' ', 1, "RES 4,C" },
+ { 0x00A2, 0x00ff, ' ', 1, "RES 4,D" },
+ { 0x00A3, 0x00ff, ' ', 1, "RES 4,E" },
+ { 0x00A4, 0x00ff, ' ', 1, "RES 4,H" },
+ { 0x00A5, 0x00ff, ' ', 1, "RES 4,L" },
+ { 0x00A6, 0x00ff, ' ', 1, "RES 4,(HL)" },
+ { 0x00A7, 0x00ff, ' ', 1, "RES 4,A" },
+ { 0x00A8, 0x00ff, ' ', 1, "RES 5,B" },
+ { 0x00A9, 0x00ff, ' ', 1, "RES 5,C" },
+ { 0x00AA, 0x00ff, ' ', 1, "RES 5,D" },
+ { 0x00AB, 0x00ff, ' ', 1, "RES 5,E" },
+ { 0x00AC, 0x00ff, ' ', 1, "RES 5,H" },
+ { 0x00AD, 0x00ff, ' ', 1, "RES 5,L" },
+ { 0x00AE, 0x00ff, ' ', 1, "RES 5,(HL)" },
+ { 0x00AF, 0x00ff, ' ', 1, "RES 5,A" },
+ { 0x00B0, 0x00ff, ' ', 1, "RES 6,B" },
+ { 0x00B1, 0x00ff, ' ', 1, "RES 6,C" },
+ { 0x00B2, 0x00ff, ' ', 1, "RES 6,D" },
+ { 0x00B3, 0x00ff, ' ', 1, "RES 6,E" },
+ { 0x00B4, 0x00ff, ' ', 1, "RES 6,H" },
+ { 0x00B5, 0x00ff, ' ', 1, "RES 6,L" },
+ { 0x00B6, 0x00ff, ' ', 1, "RES 6,(HL)" },
+ { 0x00B7, 0x00ff, ' ', 1, "RES 6,A" },
+ { 0x00B8, 0x00ff, ' ', 1, "RES 7,B" },
+ { 0x00B9, 0x00ff, ' ', 1, "RES 7,C" },
+ { 0x00BA, 0x00ff, ' ', 1, "RES 7,D" },
+ { 0x00BB, 0x00ff, ' ', 1, "RES 7,E" },
+ { 0x00BC, 0x00ff, ' ', 1, "RES 7,H" },
+ { 0x00BD, 0x00ff, ' ', 1, "RES 7,L" },
+ { 0x00BE, 0x00ff, ' ', 1, "RES 7,(HL)" },
+ { 0x00BF, 0x00ff, ' ', 1, "RES 7,A" },
+ { 0x00C0, 0x00ff, ' ', 1, "SET 0,B" },
+ { 0x00C1, 0x00ff, ' ', 1, "SET 0,C" },
+ { 0x00C2, 0x00ff, ' ', 1, "SET 0,D" },
+ { 0x00C3, 0x00ff, ' ', 1, "SET 0,E" },
+ { 0x00C4, 0x00ff, ' ', 1, "SET 0,H" },
+ { 0x00C5, 0x00ff, ' ', 1, "SET 0,L" },
+ { 0x00C6, 0x00ff, ' ', 1, "SET 0,(HL)" },
+ { 0x00C7, 0x00ff, ' ', 1, "SET 0,A" },
+ { 0x00C8, 0x00ff, ' ', 1, "SET 1,B" },
+ { 0x00C9, 0x00ff, ' ', 1, "SET 1,C" },
+ { 0x00CA, 0x00ff, ' ', 1, "SET 1,D" },
+ { 0x00CB, 0x00ff, ' ', 1, "SET 1,E" },
+ { 0x00CC, 0x00ff, ' ', 1, "SET 1,H" },
+ { 0x00CD, 0x00ff, ' ', 1, "SET 1,L" },
+ { 0x00CE, 0x00ff, ' ', 1, "SET 1,(HL)" },
+ { 0x00CF, 0x00ff, ' ', 1, "SET 1,A" },
+ { 0x00D0, 0x00ff, ' ', 1, "SET 2,B" },
+ { 0x00D1, 0x00ff, ' ', 1, "SET 2,C" },
+ { 0x00D2, 0x00ff, ' ', 1, "SET 2,D" },
+ { 0x00D3, 0x00ff, ' ', 1, "SET 2,E" },
+ { 0x00D4, 0x00ff, ' ', 1, "SET 2,H" },
+ { 0x00D5, 0x00ff, ' ', 1, "SET 2,L" },
+ { 0x00D6, 0x00ff, ' ', 1, "SET 2,(HL)" },
+ { 0x00D7, 0x00ff, ' ', 1, "SET 2,A" },
+ { 0x00D8, 0x00ff, ' ', 1, "SET 3,B" },
+ { 0x00D9, 0x00ff, ' ', 1, "SET 3,C" },
+ { 0x00DA, 0x00ff, ' ', 1, "SET 3,D" },
+ { 0x00DB, 0x00ff, ' ', 1, "SET 3,E" },
+ { 0x00DC, 0x00ff, ' ', 1, "SET 3,H" },
+ { 0x00DD, 0x00ff, ' ', 1, "SET 3,L" },
+ { 0x00DE, 0x00ff, ' ', 1, "SET 3,(HL)" },
+ { 0x00DF, 0x00ff, ' ', 1, "SET 3,A" },
+ { 0x00E0, 0x00ff, ' ', 1, "SET 4,B" },
+ { 0x00E1, 0x00ff, ' ', 1, "SET 4,C" },
+ { 0x00E2, 0x00ff, ' ', 1, "SET 4,D" },
+ { 0x00E3, 0x00ff, ' ', 1, "SET 4,E" },
+ { 0x00E4, 0x00ff, ' ', 1, "SET 4,H" },
+ { 0x00E5, 0x00ff, ' ', 1, "SET 4,L" },
+ { 0x00E6, 0x00ff, ' ', 1, "SET 4,(HL)" },
+ { 0x00E7, 0x00ff, ' ', 1, "SET 4,A" },
+ { 0x00E8, 0x00ff, ' ', 1, "SET 5,B" },
+ { 0x00E9, 0x00ff, ' ', 1, "SET 5,C" },
+ { 0x00EA, 0x00ff, ' ', 1, "SET 5,D" },
+ { 0x00EB, 0x00ff, ' ', 1, "SET 5,E" },
+ { 0x00EC, 0x00ff, ' ', 1, "SET 5,H" },
+ { 0x00ED, 0x00ff, ' ', 1, "SET 5,L" },
+ { 0x00EE, 0x00ff, ' ', 1, "SET 5,(HL)" },
+ { 0x00EF, 0x00ff, ' ', 1, "SET 5,A" },
+ { 0x00F0, 0x00ff, ' ', 1, "SET 6,B" },
+ { 0x00F1, 0x00ff, ' ', 1, "SET 6,C" },
+ { 0x00F2, 0x00ff, ' ', 1, "SET 6,D" },
+ { 0x00F3, 0x00ff, ' ', 1, "SET 6,E" },
+ { 0x00F4, 0x00ff, ' ', 1, "SET 6,H" },
+ { 0x00F5, 0x00ff, ' ', 1, "SET 6,L" },
+ { 0x00F6, 0x00ff, ' ', 1, "SET 6,(HL)" },
+ { 0x00F7, 0x00ff, ' ', 1, "SET 6,A" },
+ { 0x00F8, 0x00ff, ' ', 1, "SET 7,B" },
+ { 0x00F9, 0x00ff, ' ', 1, "SET 7,C" },
+ { 0x00FA, 0x00ff, ' ', 1, "SET 7,D" },
+ { 0x00FB, 0x00ff, ' ', 1, "SET 7,E" },
+ { 0x00FC, 0x00ff, ' ', 1, "SET 7,H" },
+ { 0x00FD, 0x00ff, ' ', 1, "SET 7,L" },
+ { 0x00FE, 0x00ff, ' ', 1, "SET 7,(HL)" },
+ { 0x00FF, 0x00ff, ' ', 1, "SET 7,A" },
+ { 0, 0, 0, 0, NULL }
+};
diff --git a/sim/ucsim/z80.src/glob_r2k.cc b/sim/ucsim/z80.src/glob_r2k.cc new file mode 100644 index 0000000..e590ab4 --- /dev/null +++ b/sim/ucsim/z80.src/glob_r2k.cc @@ -0,0 +1,3 @@ +#define R2K 1
+
+#include "glob.cc"
diff --git a/sim/ucsim/z80.src/inst.cc b/sim/ucsim/z80.src/inst.cc new file mode 100644 index 0000000..7069443 --- /dev/null +++ b/sim/ucsim/z80.src/inst.cc @@ -0,0 +1,1478 @@ +/* + * Simulator of microcontrollers (inst.cc) + * + * some z80 code base from Karl Bongers karl@turbobit.com + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#include "ddconfig.h" + +#include <stdlib.h> + +// local +#include "z80cl.h" +#include "regsz80.h" +#include "z80mac.h" + + +/* + * No Instruction + * NOP + * 0000 0000 0000 0000 + *---------------------------------------------------------------------------- + */ + +int +cl_z80::inst_nop(t_mem code) +{ + return(resGO); +} + +/* + * Load Instruction + * LD + * + *---------------------------------------------------------------------------- + */ + +int +cl_z80::inst_ld(t_mem code) +{ + switch(code) + { + case 1: // LD BC,nnnn + regs.BC = fetch2(); + break; + case 2: // LD (BC),A + store1(regs.BC, regs.raf.A); + vc.wr++; + break; + case 6: // LD B,nn + regs.bc.h = fetch(); + break; + case 0xa: // LD A,(BC) + regs.raf.A = get1(regs.BC); + vc.rd++; + break; + case 0x0e: // LD C,nn + regs.bc.l = fetch(); + break; + case 0x11: // LD DE,nnnn + regs.DE = fetch2(); + break; + case 0x12: // LD (DE),A + store1(regs.DE, regs.raf.A); + vc.wr++; + break; + case 0x16: // LD D,nn + regs.de.h = fetch(); + break; + case 0x1A: // LD A,(DE) + regs.raf.A = get1(regs.DE); + vc.rd++; + break; + case 0x1E: // LD E,nn + regs.de.l = fetch(); + break; + case 0x21: // LD HL,nnnn + regs.HL = fetch2(); + break; + case 0x22: // LD (nnnn),HL + { + unsigned short tw; + tw = fetch2(); + store2(tw, regs.HL); + vc.wr+= 2; + break; + } + case 0x26: // LD H,nn + regs.hl.h = fetch(); + break; + case 0x2A: // LD HL,(nnnn) + { + unsigned short tw; + tw = fetch2(); + regs.HL = get2(tw); + vc.rd+= 2; + break; + } + case 0x2E: // LD L,nn + regs.hl.l = fetch(); + break; + case 0x31: // LD SP,nnnn + regs.SP = fetch2(); + break; + case 0x32: // LD (nnnn),A + { + unsigned short tw; + tw = fetch2(); + store1(tw, regs.raf.A); + vc.wr++; + break; + } + case 0x36: // LD (HL),nn + store1(regs.HL, fetch()); + vc.wr++; + break; + case 0x3A: // LD A,(nnnn) + regs.raf.A = get1(fetch2()); + vc.rd++; + break; + case 0x3E: // LD A,nn + regs.raf.A = fetch(); + break; + case 0x40: // LD B,B + break; + case 0x41: // LD B,C + regs.bc.h = regs.bc.l; + break; + case 0x42: // LD B,D + regs.bc.h = regs.de.h; + break; + case 0x43: // LD B,E + regs.bc.h = regs.de.l; + break; + case 0x44: // LD B,H + regs.bc.h = regs.hl.h; + break; + case 0x45: // LD B,L + regs.bc.h = regs.hl.l; + break; + case 0x46: // LD B,(HL) + regs.bc.h = get1(regs.HL); + vc.rd++; + break; + case 0x47: // LD B,A + regs.bc.h = regs.raf.A; + break; + case 0x48: // LD C,B + regs.bc.l = regs.bc.h; + break; + case 0x49: // LD C,C + break; + case 0x4A: // LD C,D + regs.bc.l = regs.de.h; + break; + case 0x4B: // LD C,E + regs.bc.l = regs.de.l; + break; + case 0x4C: // LD C,H + regs.bc.l = regs.hl.h; + break; + case 0x4D: // LD C,L + regs.bc.l = regs.hl.l; + break; + case 0x4E: // LD C,(HL) + regs.bc.l = get1(regs.HL); + vc.rd++; + break; + case 0x4F: // LD C,A + regs.bc.l = regs.raf.A; + break; + case 0x50: // LD D,B + regs.de.h = regs.bc.h; + break; + case 0x51: // LD D,C + regs.de.h = regs.bc.l; + break; + case 0x52: // LD D,D + break; + case 0x53: // LD D,E + regs.de.h = regs.de.l; + break; + case 0x54: // LD D,H + regs.de.h = regs.hl.h; + break; + case 0x55: // LD D,L + regs.de.h = regs.hl.l; + break; + case 0x56: // LD D,(HL) + regs.de.h = get1(regs.HL); + vc.rd++; + break; + case 0x57: // LD D,A + regs.de.h = regs.raf.A; + break; + case 0x58: // LD E,B + regs.de.l = regs.bc.h; + break; + case 0x59: // LD E,C + regs.de.l = regs.bc.l; + break; + case 0x5A: // LD E,D + regs.de.l = regs.de.h; + break; + case 0x5B: // LD E,E + break; + case 0x5C: // LD E,H + regs.de.l = regs.hl.h; + break; + case 0x5D: // LD E,L + regs.de.l = regs.hl.l; + break; + case 0x5E: // LD E,(HL) + regs.de.l = get1(regs.HL); + vc.rd++; + break; + case 0x5F: // LD E,A + regs.de.l = regs.raf.A; + break; + case 0x60: // LD H,B + regs.hl.h = regs.bc.h; + break; + case 0x61: // LD H,C + regs.hl.h = regs.bc.l; + break; + case 0x62: // LD H,D + regs.hl.h = regs.de.h; + break; + case 0x63: // LD H,E + regs.hl.h = regs.de.l; + break; + case 0x64: // LD H,H + regs.hl.h = regs.hl.h; + break; + case 0x65: // LD H,L + regs.hl.h = regs.hl.l; + break; + case 0x66: // LD H,(HL) + regs.hl.h = get1(regs.HL); + vc.rd++; + break; + case 0x67: // LD H,A + regs.hl.h = regs.raf.A; + break; + case 0x68: // LD L,B + regs.hl.l = regs.bc.h; + break; + case 0x69: // LD L,C + regs.hl.l = regs.bc.l; + break; + case 0x6A: // LD L,D + regs.hl.l = regs.de.h; + break; + case 0x6B: // LD L,E + regs.hl.l = regs.de.l; + break; + case 0x6C: // LD L,H + regs.hl.l = regs.hl.h; + break; + case 0x6D: // LD L,L + break; + case 0x6E: // LD L,(HL) + regs.hl.l = get1(regs.HL); + vc.rd++; + break; + case 0x6F: // LD L,A + regs.hl.l = regs.raf.A; + break; + case 0x70: // LD (HL),B + store1(regs.HL, regs.bc.h); + vc.wr++; + break; + case 0x71: // LD (HL),C + store1(regs.HL, regs.bc.l); + vc.wr++; + break; + case 0x72: // LD (HL),D + store1(regs.HL, regs.de.h); + vc.wr++; + break; + case 0x73: // LD (HL),E + store1(regs.HL, regs.de.l); + vc.wr++; + break; + case 0x74: // LD (HL),H + store1(regs.HL, regs.hl.h); + vc.wr++; + break; + case 0x75: // LD (HL),L + store1(regs.HL, regs.hl.l); + vc.wr++; + break; + case 0x76: // HALT + return(resHALT); + + case 0x77: // LD (HL),A + store1(regs.HL, regs.raf.A); + vc.wr++; + break; + case 0x78: // LD A,B + regs.raf.A = regs.bc.h; + break; + case 0x79: // LD A,C + regs.raf.A = regs.bc.l; + break; + case 0x7A: // LD A,D + regs.raf.A = regs.de.h; + break; + case 0x7B: // LD A,E + regs.raf.A = regs.de.l; + break; + case 0x7C: // LD A,H + regs.raf.A = regs.hl.h; + break; + case 0x7D: // LD A,L + regs.raf.A = regs.hl.l; + break; + case 0x7E: // LD A,(HL) + regs.raf.A = get1(regs.HL); + vc.rd++; + break; + case 0x7F: // LD A,A + break; + case 0xF9: // LD SP,HL + regs.SP = regs.HL; + break; + default: + return(resINV_INST); + break; + } + return(resGO); +} + +int +cl_z80::inst_inc(t_mem code) +{ + switch(code) + { + case 0x03: // INC BC + ++regs.BC; + break; + case 0x04: // INC B + inc(regs.bc.h); + break; + case 0x0C: // INC C + inc(regs.bc.l); + break; + case 0x13: // INC DE + ++regs.DE; + break; + case 0x14: // INC D + inc(regs.de.h); + break; + case 0x1C: // INC E + inc(regs.de.l); + break; + case 0x23: // INC HL + ++regs.HL; + break; + case 0x24: // INC H + inc(regs.hl.h); + break; + case 0x2C: // INC L + inc(regs.hl.l); + break; + case 0x33: // INC SP + ++regs.SP; + break; + case 0x34: // INC (HL) + { + unsigned char t=get1(regs.HL); + inc(t); + store1(regs.HL, t); + vc.rd++; + vc.wr++; + break; + } + case 0x3C: // INC A + inc(regs.raf.A); + break; + default: + return(resINV_INST); + break; + } + return(resGO); +} + +int +cl_z80::inst_dec(t_mem code) +{ + switch(code) + { + case 0x05: // DEC B + dec(regs.bc.h); + break; + case 0x0B: // DEC BC + --regs.BC; + break; + case 0x0D: // DEC C + dec(regs.bc.l); + break; + case 0x15: // DEC D + dec(regs.de.h); + break; + case 0x1B: // DEC DE + --regs.DE; + break; + case 0x1D: // DEC E + dec(regs.de.l); + break; + case 0x25: // DEC H + dec(regs.hl.h); + break; + case 0x2B: // DEC HL + --regs.HL; + break; + case 0x2D: // DEC L + dec(regs.hl.l); + break; + case 0x35: // DEC (HL) + { + unsigned char t=get1(regs.HL); + dec(t); + store1(regs.HL, t); + vc.rd++; + vc.wr++; + break; + } + case 0x3B: // DEC SP + --regs.SP; + break; + case 0x3D: // DEC A + dec(regs.raf.A); + break; + default: + return(resINV_INST); + break; + } + return(resGO); +} + +int +cl_z80::inst_rlca(t_mem code) +{ + regs.raf.F &= ~(BIT_A | BIT_N | BIT_C); + if (regs.raf.A & 0x80) { + regs.raf.F |= BIT_C; + regs.raf.A = (regs.raf.A << 1) | 0x01; + } else + regs.raf.A = (regs.raf.A << 1); + + return(resGO); +} + +int +cl_z80::inst_rrca(t_mem code) +{ + regs.raf.F &= ~(BIT_A | BIT_N | BIT_C); + if (regs.raf.A & 0x01) { + regs.raf.F |= BIT_C; + regs.raf.A = (regs.raf.A >> 1) | 0x80; + } + else + regs.raf.A = (regs.raf.A >> 1); + return(resGO); +} + +int +cl_z80::inst_ex(t_mem code) +{ + /* 0x08 // EX AF,AF' */ + unsigned char tmp; + u16_t tempw; + + switch (code) { + case 0x08: // EX AF,AF' + tmp = regs.ralt_af.aA; + regs.ralt_af.aA = regs.raf.A; + regs.raf.A = tmp; + + tmp = regs.ralt_af.aF; + regs.ralt_af.aF = regs.raf.F; + regs.raf.F = tmp; + break; + + case 0xE3: // EX (SP),HL + tempw = regs.HL; + regs.HL = get2(regs.SP); + store2(regs.SP, tempw); + vc.rd+= 2; + vc.wr+= 2; + break; + + case 0xEB: // EX DE,HL + tempw = regs.DE; + regs.DE = regs.HL; + regs.HL = tempw; + break; + + default: + return(resINV_INST); + break; + } + + return(resGO); +} + +int +cl_z80::inst_add(t_mem code) +{ + switch(code) + { + case 0x09: // ADD HL,BC + add_HL_Word(regs.BC); + break; + case 0x19: // ADD HL,DE + add_HL_Word(regs.DE); + break; + case 0x29: // ADD HL,HL + add_HL_Word(regs.HL); + break; + case 0x39: // ADD HL,SP + add_HL_Word(regs.SP); + break; + + case 0x80: // ADD A,B + add_A_bytereg(regs.bc.h); + break; + case 0x81: // ADD A,C + add_A_bytereg(regs.bc.l); + break; + case 0x82: // ADD A,D + add_A_bytereg(regs.de.h); + break; + case 0x83: // ADD A,E + add_A_bytereg(regs.de.l); + break; + case 0x84: // ADD A,H + add_A_bytereg(regs.hl.h); + break; + case 0x85: // ADD A,L + add_A_bytereg(regs.hl.l); + break; + + case 0x86: // ADD A,(HL) + { + unsigned char utmp; + utmp = get1(regs.HL); + add_A_bytereg(utmp); + vc.rd++; + break; + } + + case 0x87: // ADD A,A + add_A_bytereg(regs.raf.A); + break; + + case 0xC6: // ADD A,nn + { + unsigned char utmp1; + utmp1 = fetch(); + add_A_bytereg(utmp1); + break; + } + + default: + return(resINV_INST); + break; + } + + return(resGO); +} + +int +cl_z80::inst_djnz(t_mem code) +{ + signed char j; + + // 0x10: DJNZ dd + + j = fetch1(); + if ((--regs.bc.h != 0)) { + PC += j; + } else { + } + return(resGO); +} + +int +cl_z80::inst_rra(t_mem code) +{ + rr_byte(regs.raf.A); + return(resGO); +} + +int +cl_z80::inst_rla(t_mem code) +{ + rl_byte(regs.raf.A); + return(resGO); +} + +int +cl_z80::inst_jr(t_mem code) +{ + signed char j; + + j = fetch1(); + switch(code) { + case 0x18: // JR dd + PC += j; + break; + case 0x20: // JR NZ,dd + if (!(regs.raf.F & BIT_Z)) { + PC += j; + } + break; + case 0x28: // JR Z,dd + if ((regs.raf.F & BIT_Z)) { + PC += j; + } + break; + case 0x30: // JR NC,dd + if (!(regs.raf.F & BIT_C)) { + PC += j; + } + break; + case 0x38: // JR C,dd + if ((regs.raf.F & BIT_C)) { + PC += j; + } + break; + default: + return(resINV_INST); + break; + } + return(resGO); +} + +int +cl_z80::inst_daa(t_mem code) +{ + /************* from MH's z80ops.c: + unsigned char incr=0, carry=cy; + if((f&0x10) || (a&0x0f)>9) incr=6; + if((f&1) || (a>>4)>9) incr|=0x60; + if(f&2)suba(incr,0); + else { + if(a>0x90 && (a&15)>9)incr|=0x60; + adda(incr,0); + } + f=((f|carry)&0xfb); + ********/ + /* I have not tried to understand this archaic bit of BCD logic(kpb), + taking the lazy way out for now and just transcribing MH's code. + */ + unsigned char incr; + unsigned char N = regs.raf.F & BIT_N; /* save N */ + unsigned char C = regs.raf.F & BIT_C; /* save C */ + if ((regs.raf.F & BIT_A) || ((regs.raf.A & 0x0f) > 9)) + incr = 6; + else incr = 0; + + if ((regs.raf.F & BIT_C) || ((regs.raf.A & 0xf0) > 0x90) || (regs.raf.A > 0x99)) + incr |= 0x60; + + if (regs.raf.F & BIT_N) { /* not addition */ + sub_A_bytereg(incr); + } else { + add_A_bytereg(incr); + } + regs.raf.F &= ~(BIT_P | BIT_N); + if (parity(regs.raf.A)) + regs.raf.F |= BIT_P; + regs.raf.F |= N; /* restore N */ + regs.raf.F |= C; /* or with original C */ + + return(resGO); +} + +int +cl_z80::inst_cpl(t_mem code) +{ + regs.raf.F |= (BIT_A | BIT_N); + regs.raf.A = ~regs.raf.A; + return(resGO); +} + +int +cl_z80::inst_scf(t_mem code) +{ + /* Set Carry Flag */ + regs.raf.F &= ~(BIT_A | BIT_N); + regs.raf.F |= BIT_C; + return(resGO); +} + +int +cl_z80::inst_ccf(t_mem code) +{ + /* Complement Carry Flag */ + regs.raf.F &= ~(BIT_A | BIT_N); + if (regs.raf.F & BIT_C) + regs.raf.F |= BIT_A; + regs.raf.F ^= BIT_C; + return(resGO); +} + +int +cl_z80::inst_halt(t_mem code) +{ + return(resHALT); +} + +int +cl_z80::inst_adc(t_mem code) +{ + switch(code) + { + case 0x88: // ADC A,B + adc_A_bytereg(regs.bc.h); + break; + case 0x89: // ADC A,C + adc_A_bytereg(regs.bc.l); + break; + case 0x8A: // ADC A,D + adc_A_bytereg(regs.de.h); + break; + case 0x8B: // ADC A,E + adc_A_bytereg(regs.de.l); + break; + case 0x8C: // ADC A,H + adc_A_bytereg(regs.hl.h); + break; + case 0x8D: // ADC A,L + adc_A_bytereg(regs.hl.l); + break; + case 0x8E: // ADC A,(HL) + { + unsigned char utmp; + utmp = get1(regs.HL); + adc_A_bytereg(utmp); + vc.rd++; + break; + } + case 0x8F: // ADC A,A + adc_A_bytereg(regs.raf.A); + break; + + case 0xCE: // ADC A,nn + { + unsigned char utmp; + utmp = fetch(); + adc_A_bytereg(utmp); + } + break; + + default: + return(resINV_INST); + break; + } + return(resGO); +} + +int +cl_z80::inst_sbc(t_mem code) +{ + switch(code) + { + case 0x98: // SBC A,B + sbc_A_bytereg(regs.bc.h); + break; + case 0x99: // SBC A,C + sbc_A_bytereg(regs.bc.l); + break; + case 0x9A: // SBC A,D + sbc_A_bytereg(regs.de.h); + break; + case 0x9B: // SBC A,E + sbc_A_bytereg(regs.de.l); + break; + case 0x9C: // SBC A,H + sbc_A_bytereg(regs.hl.h); + break; + case 0x9D: // SBC A,L + sbc_A_bytereg(regs.hl.l); + break; + case 0x9E: // SBC A,(HL) + { + unsigned char utmp; + utmp = get1(regs.HL); + sbc_A_bytereg(utmp); + vc.rd++; + break; + } + case 0x9F: // SBC A,A + sbc_A_bytereg(regs.raf.A); + break; + case 0xDE: // SBC A,nn + { + unsigned char utmp; + utmp = fetch(); + sbc_A_bytereg(utmp); + break; + } + default: + return(resINV_INST); + break; + } + return(resGO); +} + +int +cl_z80::inst_and(t_mem code) +{ + switch(code) + { + case 0xA0: // AND B + and_A_bytereg(regs.bc.h); + break; + case 0xA1: // AND C + and_A_bytereg(regs.bc.l); + break; + case 0xA2: // AND D + and_A_bytereg(regs.de.h); + break; + case 0xA3: // AND E + and_A_bytereg(regs.de.l); + break; + case 0xA4: // AND H + and_A_bytereg(regs.hl.h); + break; + case 0xA5: // AND L + and_A_bytereg(regs.hl.l); + break; + case 0xA6: // AND (HL) + { + unsigned char utmp; + utmp = get1(regs.HL); + and_A_bytereg(utmp); + vc.rd++; + break; + } + case 0xA7: // AND A + and_A_bytereg(regs.raf.A); + break; + case 0xE6: // AND nn + and_A_bytereg(fetch()); + break; + + default: + return(resINV_INST); + break; + } + return(resGO); +} + +int +cl_z80::inst_xor(t_mem code) +{ + switch(code) + { + case 0xA8: // XOR B + xor_A_bytereg(regs.bc.h); + break; + case 0xA9: // XOR C + xor_A_bytereg(regs.bc.l); + break; + case 0xAA: // XOR D + xor_A_bytereg(regs.de.h); + break; + case 0xAB: // XOR E + xor_A_bytereg(regs.de.l); + break; + case 0xAC: // XOR H + xor_A_bytereg(regs.hl.h); + break; + case 0xAD: // XOR L + xor_A_bytereg(regs.hl.l); + break; + case 0xAE: // XOR (HL) + { + unsigned char utmp; + utmp = get1(regs.HL); + xor_A_bytereg(utmp); + vc.rd++; + break; + } + case 0xAF: // XOR A + xor_A_bytereg(regs.raf.A); + break; + case 0xEE: // XOR nn + xor_A_bytereg(fetch()); + break; + + default: + return(resINV_INST); + break; + } + return(resGO); +} + +int +cl_z80::inst_or(t_mem code) +{ + switch(code) + { + case 0xB0: // OR B + or_A_bytereg(regs.bc.h); + break; + case 0xB1: // OR C + or_A_bytereg(regs.bc.l); + break; + case 0xB2: // OR D + or_A_bytereg(regs.de.h); + break; + case 0xB3: // OR E + or_A_bytereg(regs.de.l); + break; + case 0xB4: // OR H + or_A_bytereg(regs.hl.h); + break; + case 0xB5: // OR L + or_A_bytereg(regs.hl.l); + break; + case 0xB6: // OR (HL) + { + unsigned char utmp; + utmp = get1(regs.HL); + or_A_bytereg(utmp); + vc.rd++; + break; + } + case 0xB7: // OR A + or_A_bytereg(regs.raf.A); + break; + case 0xF6: // OR nn + or_A_bytereg(fetch()); + break; + default: + return(resINV_INST); + break; + } + return(resGO); +} + +int +cl_z80::inst_cp(t_mem code) +{ + /* Compare with Accumulator - subtract and test, leave A unchanged */ + switch(code) + { + case 0xB8: // CP B + cp_bytereg(regs.bc.h); + break; + case 0xB9: // CP C + cp_bytereg(regs.bc.l); + break; + case 0xBA: // CP D + cp_bytereg(regs.de.h); + break; + case 0xBB: // CP E + cp_bytereg(regs.de.l); + break; + case 0xBC: // CP H + cp_bytereg(regs.hl.h); + break; + case 0xBD: // CP L + cp_bytereg(regs.hl.l); + break; + case 0xBE: // CP (HL) + { + unsigned char utmp; + utmp = get1(regs.HL); + cp_bytereg(utmp); + vc.rd++; + break; + } + case 0xBF: // CP A + cp_bytereg(regs.raf.A); + break; + case 0xFE: // CP nn + { + unsigned char utmp; + utmp = fetch(); + cp_bytereg(utmp); + break; + } + default: + return(resINV_INST); + break; + } + return(resGO); +} + +int +cl_z80::inst_rst(t_mem code) +{ + switch(code) + { + case 0xC7: // RST 0 + push2(PC+2); + PC = 0x0; + vc.wr+= 2; + break; + case 0xCF: // RST 8 + //PC = 0x08; + switch (regs.raf.A) + { + case 0: + return(resBREAKPOINT); + // ::exit(0); + break; + + case 1: + //printf("PUTCHAR-----> %xH\n", regs.hl.l); + putchar(regs.hl.l); + fflush(stdout); + break; + } + break; + case 0xD7: // RST 10H + push2(PC+2); + PC = 0x10; + vc.wr+= 2; + break; + case 0xDF: // RST 18H + push2(PC+2); + PC = 0x18; + vc.wr+= 2; + break; + case 0xE7: // RST 20H + push2(PC+2); + PC = 0x20; + vc.wr+= 2; + break; + case 0xEF: // RST 28H + push2(PC+2); + PC = 0x28; + vc.wr+= 2; + break; + case 0xF7: // RST 30H + push2(PC+2); + PC = 0x30; + vc.wr+= 2; + break; + case 0xFF: // RST 38H + push2(PC+2); + PC = 0x38; + vc.wr+= 2; + break; + default: + return(resINV_INST); + break; + } + return(resGO); +} + +int +cl_z80::inst_ret(t_mem code) +{ + switch(code) + { + case 0xC0: // RET NZ + if (!(regs.raf.F & BIT_Z)) { + pop2(PC); + vc.rd+= 2; + } + break; + case 0xC8: // RET Z + if ((regs.raf.F & BIT_Z)) { + pop2(PC); + vc.rd+= 2; + } + break; + case 0xC9: // RET + pop2(PC); + vc.rd+= 2; + break; + case 0xD0: // RET NC + if (!(regs.raf.F & BIT_C)) { + pop2(PC); + vc.rd+= 2; + } + break; + case 0xD8: // RET C + if ((regs.raf.F & BIT_C)) { + pop2(PC); + vc.rd+= 2; + } + break; + case 0xE0: // RET PO + if (!(regs.raf.F & BIT_P)) { + pop2(PC); + vc.rd+= 2; + } + break; + case 0xE8: // RET PE + if ((regs.raf.F & BIT_P)) { + pop2(PC); + vc.rd+= 2; + } + break; + case 0xF0: // RET P + if (!(regs.raf.F & BIT_S)) { + pop2(PC); + vc.rd+= 2; + } + break; + case 0xF8: // RET M + if ((regs.raf.F & BIT_S)) { + pop2(PC); + vc.rd+= 2; + } + break; + default: + return(resINV_INST); + break; + } + return(resGO); +} + +int +cl_z80::inst_call(t_mem code) +{ + switch(code) + { + case 0xC4: // CALL NZ,nnnn + if (!(regs.raf.F & BIT_Z)) { + push2(PC+2); + PC = fetch2(); + vc.wr+= 2; + } else { + fetch2(); + } + break; + case 0xCC: // CALL Z,nnnn + if (regs.raf.F & BIT_Z) { + push2(PC+2); + PC = fetch2(); + vc.wr+= 2; + } else { + fetch2(); + } + break; + case 0xCD: // CALL nnnn + push2(PC+2); + PC = fetch2(); + vc.wr+= 2; + break; + case 0xD4: // CALL NC,nnnn + if (!(regs.raf.F & BIT_C)) { + push2(PC+2); + PC = fetch2(); + vc.wr+= 2; + } else { + fetch2(); + } + break; + case 0xDC: // CALL C,nnnn + if (regs.raf.F & BIT_C) { + push2(PC+2); + PC = fetch2(); + vc.wr+= 2; + } else { + fetch2(); + } + break; + case 0xE4: // CALL PO,nnnn + if (!(regs.raf.F & BIT_P)) { + push2(PC+2); + PC = fetch2(); + vc.wr+= 2; + } else { + fetch2(); + } + break; + case 0xEC: // CALL PE,nnnn + if (regs.raf.F & BIT_P) { + push2(PC+2); + PC = fetch2(); + vc.wr+= 2; + } else { + fetch2(); + } + break; + case 0xF4: // CALL P,nnnn + if (!(regs.raf.F & BIT_S)) { + push2(PC+2); + PC = fetch2(); + vc.wr+= 2; + } else { + fetch2(); + } + break; + case 0xFC: // CALL M,nnnn + if (regs.raf.F & BIT_S) { + push2(PC+2); + PC = fetch2(); + vc.wr+= 2; + } else { + fetch2(); + } + break; + default: + return(resINV_INST); + break; + } + + return(resGO); +} + +int +cl_z80::inst_out(t_mem code) +{ + t_addr a= fetch(); + outputs->write(a, regs.raf.A); + return(resGO); +} + +int +cl_z80::inst_push(t_mem code) +{ + switch(code) + { + case 0xC5: // PUSH BC + push2(regs.BC); + vc.wr+= 2; + break; + case 0xD5: // PUSH DE + push2(regs.DE); + vc.wr+= 2; + break; + case 0xE5: // PUSH HL + push2(regs.HL); + vc.wr+= 2; + break; + case 0xF5: // PUSH AF + push1(regs.raf.A); + push1(regs.raf.F); + vc.wr+= 2; + break; + default: + return(resINV_INST); + break; + } + return(resGO); +} + +int +cl_z80::inst_exx(t_mem code) +{ + /* case 0xD9: // EXX - swap BC,DE,HL with alternates */ + u16_t tempw; + + tempw = regs.aHL; + regs.aHL = regs.HL; + regs.HL = tempw; + + tempw = regs.aDE; + regs.aDE = regs.DE; + regs.DE = tempw; + + tempw = regs.aBC; + regs.aBC = regs.BC; + regs.BC = tempw; + + return(resGO); +} + +int +cl_z80::inst_in(t_mem code) +{ + t_addr a= fetch(); + regs.raf.A= inputs->read(a); + return(resGO); +} + +int +cl_z80::inst_sub(t_mem code) +{ + switch(code) + { + case 0x90: // SUB B + sub_A_bytereg(regs.bc.h); + break; + case 0x91: // SUB C + sub_A_bytereg(regs.bc.l); + break; + case 0x92: // SUB D + sub_A_bytereg(regs.de.h); + break; + case 0x93: // SUB E + sub_A_bytereg(regs.de.l); + break; + case 0x94: // SUB H + sub_A_bytereg(regs.hl.h); + break; + case 0x95: // SUB L + sub_A_bytereg(regs.hl.l); + break; + case 0x96: // SUB (HL) + { + unsigned char tmp1; + tmp1 = get1(regs.HL); + sub_A_bytereg(tmp1); + vc.rd++; + } + break; + case 0x97: // SUB A + sub_A_bytereg(regs.raf.A); + break; + case 0xD6: // SUB nn + { + unsigned char tmp1; + tmp1 = fetch(); + sub_A_bytereg(tmp1); + } + break; + default: + return(resINV_INST); + break; + } + return(resGO); +} + +int +cl_z80::inst_pop(t_mem code) +{ + switch (code) + { + case 0xC1: // POP BC + regs.BC = get2(regs.SP); + regs.SP+=2; + vc.rd+= 2; + break; + case 0xD1: // POP DE + regs.DE = get2(regs.SP); + regs.SP+=2; + vc.rd+= 2; + break; + case 0xE1: // POP HL + regs.HL = get2(regs.SP); + regs.SP+=2; + vc.rd+= 2; + break; + case 0xF1: // POP AF + regs.raf.F = get1(regs.SP++); + regs.raf.A = get1(regs.SP++); + vc.rd+= 2; + break; + default: + return(resINV_INST); + break; + } + return(resGO); +} + +int +cl_z80::inst_jp(t_mem code) +{ + switch (code) + { + case 0xC2: // JP NZ,nnnn + if (!(regs.raf.F & BIT_Z)) { + PC = fetch2(); + } else { + fetch2(); + } + break; + + case 0xC3: // JP nnnn + PC = fetch2(); + break; + + case 0xCA: // JP Z,nnnn + if (regs.raf.F & BIT_Z) { + PC = fetch2(); + } else { + fetch2(); + } + break; + + case 0xD2: // JP NC,nnnn + if (!(regs.raf.F & BIT_C)) { + PC = fetch2(); + } else { + fetch2(); + } + break; + + case 0xDA: // JP C,nnnn + if (regs.raf.F & BIT_C) { + PC = fetch2(); + } else { + fetch2(); + } + break; + + case 0xE2: // JP PO,nnnn + if (!(regs.raf.F & BIT_P)) { + PC = fetch2(); + } else { + fetch2(); + } + break; + + case 0xE9: // JP (HL) + PC = regs.HL; + break; + + case 0xEA: // JP PE,nnnn + if (regs.raf.F & BIT_P) { + PC = fetch2(); + } else { + fetch2(); + } + break; + + case 0xF2: // JP P,nnnn (positive) + if (!(regs.raf.F & BIT_S)) { + PC = fetch2(); + } else { + fetch2(); + } + break; + + case 0xFA: // JP M,nnnn (sign negative) + if (regs.raf.F & BIT_S) { + PC = fetch2(); + } else { + fetch2(); + } + break; + default: + return(resINV_INST); + break; + } + return(resGO); +} + +int +cl_z80::inst_di(t_mem code) +{ + /* disable interrupts */ + return(resGO); +} + +int +cl_z80::inst_ei(t_mem code) +{ + /* enable interrupts */ + return(resGO); +} + +/* End of z80.src/inst.cc */ diff --git a/sim/ucsim/z80.src/inst_cb.cc b/sim/ucsim/z80.src/inst_cb.cc new file mode 100644 index 0000000..5bc4e86 --- /dev/null +++ b/sim/ucsim/z80.src/inst_cb.cc @@ -0,0 +1,727 @@ +/* + * Simulator of microcontrollers (inst.cc) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#include "ddconfig.h" + +// local +#include "z80cl.h" +#include "regsz80.h" +#include "z80mac.h" + +int +cl_z80::inst_cb_rlc(t_mem code) +{ + switch(code) { + case 0x00: // RLC B + rlc_byte(regs.bc.h); + break; + case 0x01: // RLC C + rlc_byte(regs.bc.l); + break; + case 0x02: // RLC D + rlc_byte(regs.de.h); + break; + case 0x03: // RLC E + rlc_byte(regs.de.l); + break; + case 0x04: // RLC H + rlc_byte(regs.hl.h); + break; + case 0x05: // RLC L + rlc_byte(regs.hl.l); + break; + case 0x06: // RLC (HL) + { unsigned char tmp; + tmp = get1(regs.HL); + rlc_byte(tmp); + store1(regs.HL, tmp); + vc.rd++; + vc.wr++; + } + break; + case 0x07: // RLC A + rlc_byte(regs.raf.A); + break; + } + return(resGO); +} + +int +cl_z80::inst_cb_rrc(t_mem code) +{ + switch(code) { + case 0x08: // RRC B + rrc_byte(regs.bc.h); + break; + case 0x09: // RRC C + rrc_byte(regs.bc.l); + break; + case 0x0A: // RRC D + rrc_byte(regs.de.h); + break; + case 0x0B: // RRC E + rrc_byte(regs.de.l); + break; + case 0x0C: // RRC H + rrc_byte(regs.hl.h); + break; + case 0x0D: // RRC L + rrc_byte(regs.hl.l); + break; + case 0x0E: // RRC (HL) + { unsigned char tmp; + tmp = get1(regs.HL); + rrc_byte(tmp); + store1(regs.HL, tmp); + vc.rd++; + vc.wr++; + } + break; + case 0x0F: // RRC A + rrc_byte(regs.raf.A); + break; + } + return(resGO); +} + +int +cl_z80::inst_cb_rl(t_mem code) +{ + switch(code) { + case 0x10: // RL B + rl_byte(regs.bc.h); + break; + case 0x11: // RL C + rl_byte(regs.bc.l); + break; + case 0x12: // RL D + rl_byte(regs.de.h); + break; + case 0x13: // RL E + rl_byte(regs.de.l); + break; + case 0x14: // RL H + rl_byte(regs.hl.h); + break; + case 0x15: // RL L + rl_byte(regs.hl.l); + break; + case 0x16: // RL (HL) + { unsigned char tmp; + tmp = get1(regs.HL); + rl_byte(tmp); + store1(regs.HL, tmp); + vc.rd++; + vc.wr++; + } + break; + case 0x17: // RL A + rl_byte(regs.raf.A); + break; + } + return(resGO); +} + +int +cl_z80::inst_cb_rr(t_mem code) +{ + switch(code) { + case 0x18: // RR B + rr_byte(regs.bc.h); + break; + case 0x19: // RR C + rr_byte(regs.bc.l); + break; + case 0x1A: // RR D + rr_byte(regs.de.h); + break; + case 0x1B: // RR E + rr_byte(regs.de.l); + break; + case 0x1C: // RR H + rr_byte(regs.hl.h); + break; + case 0x1D: // RR L + rr_byte(regs.hl.l); + break; + case 0x1E: // RR (HL) + { unsigned char tmp; + tmp = get1(regs.HL); + rr_byte(tmp); + store1(regs.HL, tmp); + vc.rd++; + vc.wr++; + } + break; + case 0x1F: // RR A + rr_byte(regs.raf.A); + break; + } + return(resGO); +} + +int +cl_z80::inst_cb_sla(t_mem code) +{ + switch(code) { + case 0x20: // SLA B + sla_byte(regs.bc.h); + break; + case 0x21: // SLA C + sla_byte(regs.bc.l); + break; + case 0x22: // SLA D + sla_byte(regs.de.h); + break; + case 0x23: // SLA E + sla_byte(regs.de.l); + break; + case 0x24: // SLA H + sla_byte(regs.hl.h); + break; + case 0x25: // SLA L + sla_byte(regs.hl.l); + break; + case 0x26: // SLA (HL) + { unsigned char tmp; + tmp = get1(regs.HL); + sla_byte(tmp); + store1(regs.HL, tmp); + vc.rd++; + vc.wr++; + } + break; + case 0x27: // SLA A + sla_byte(regs.raf.A); + break; + } + return(resGO); +} + +int +cl_z80::inst_cb_sra(t_mem code) +{ + switch(code) { + case 0x28: // SRA B + sra_byte(regs.bc.h); + break; + case 0x29: // SRA C + sra_byte(regs.bc.l); + break; + case 0x2A: // SRA D + sra_byte(regs.de.h); + break; + case 0x2B: // SRA E + sra_byte(regs.de.l); + break; + case 0x2C: // SRA H + sra_byte(regs.hl.h); + break; + case 0x2D: // SRA L + sra_byte(regs.hl.l); + break; + case 0x2E: // SRA (HL) + { unsigned char tmp; + tmp = get1(regs.HL); + sra_byte(tmp); + store1(regs.HL, tmp); + vc.rd++; + vc.wr++; + } + break; + case 0x2F: // SRA A + sra_byte(regs.raf.A); + break; + } + return(resGO); +} + +int +cl_z80::inst_cb_slia(t_mem code) +{ + switch(code) { + case 0x30: // SLIA B (Shift Left Inverted Arithmetic) + slia_byte(regs.bc.h); + break; + case 0x31: // SLIA C like SLA, but shifts in a 1 bit + slia_byte(regs.bc.l); + break; + case 0x32: // SLIA D + slia_byte(regs.de.h); + break; + case 0x33: // SLIA E + slia_byte(regs.de.l); + break; + case 0x34: // SLIA H + slia_byte(regs.hl.h); + break; + case 0x35: // SLIA L + slia_byte(regs.hl.l); + break; + case 0x36: // SLIA (HL) + { unsigned char tmp; + tmp = get1(regs.HL); + slia_byte(tmp); + store1(regs.HL, tmp); + vc.rd++; + vc.wr++; + } + break; + case 0x37: // SLIA A + slia_byte(regs.raf.A); + break; + } + return(resGO); +} + +int +cl_z80::inst_cb_srl(t_mem code) +{ + switch(code) { + case 0x38: // SRL B + srl_byte(regs.bc.h); + break; + case 0x39: // SRL C + srl_byte(regs.bc.l); + break; + case 0x3A: // SRL D + srl_byte(regs.de.h); + break; + case 0x3B: // SRL E + srl_byte(regs.de.l); + break; + case 0x3C: // SRL H + srl_byte(regs.hl.h); + break; + case 0x3D: // SRL L + srl_byte(regs.hl.l); + break; + case 0x3E: // SRL (HL) + { unsigned char tmp; + tmp = get1(regs.HL); + srl_byte(tmp); + store1(regs.HL, tmp); + vc.rd++; + vc.wr++; + } + break; + case 0x3F: // SRL A + srl_byte(regs.raf.A); + break; + } + return(resGO); +} + + +int +cl_z80::inst_cb_bit(t_mem code) +{ +#define bit_bitnum ((code >> 3) & 7) + + switch(code & 7) { + case 0x0: // BIT x,B + bit_byte(regs.bc.h, bit_bitnum); break; + case 0x1: // BIT x,C + bit_byte(regs.bc.l, bit_bitnum); break; + case 0x2: // BIT x,D + bit_byte(regs.de.h, bit_bitnum); break; + case 0x3: // BIT x,E + bit_byte(regs.de.l, bit_bitnum); break; + case 0x4: // BIT x,H + bit_byte(regs.hl.h, bit_bitnum); break; + case 0x5: // BIT x,L + bit_byte(regs.hl.l, bit_bitnum); break; + case 0x6: // BIT x,(HL) + { unsigned char tmp; + tmp = get1(regs.HL); + bit_byte(tmp, bit_bitnum); + store1(regs.HL, tmp); + vc.rd++; + vc.wr++; + } + break; + case 0x7: // BIT x,A + bit_byte(regs.raf.A, bit_bitnum); break; + break; + } + return(resGO); +} + +int +cl_z80::inst_cb_res(t_mem code) +{ +#define bit_bitnum ((code >> 3) & 7) + + switch(code & 0x7) { + case 0x0: // RES x,B + regs.bc.h &= ~(1 << bit_bitnum); break; + case 0x1: // RES x,C + regs.bc.l &= ~(1 << bit_bitnum); break; + case 0x2: // RES x,D + regs.de.h &= ~(1 << bit_bitnum); break; + case 0x3: // RES x,E + regs.de.l &= ~(1 << bit_bitnum); break; + case 0x4: // RES x,H + regs.hl.h &= ~(1 << bit_bitnum); break; + case 0x5: // RES x,L + regs.hl.l &= ~(1 << bit_bitnum); break; + case 0x6: // RES x,(HL) + { unsigned char tmp; + tmp = get1(regs.HL); + tmp &= ~(1 << bit_bitnum); + store1(regs.HL, tmp); + vc.rd++; + vc.rd++; + } + break; + case 0x7: // RES x,A + regs.raf.A &= ~(1 << bit_bitnum); break; + } + return(resGO); +} + +int +cl_z80::inst_cb_set(t_mem code) +{ +#define bit_bitnum ((code >> 3) & 7) + + switch(code & 0x7) { + case 0x0: // SET x,B + regs.bc.h |= (1 << bit_bitnum); break; + case 0x1: // SET x,C + regs.bc.l |= (1 << bit_bitnum); break; + case 0x2: // SET x,D + regs.de.h |= (1 << bit_bitnum); break; + case 0x3: // SET x,E + regs.de.l |= (1 << bit_bitnum); break; + case 0x4: // SET x,H + regs.hl.h |= (1 << bit_bitnum); break; + case 0x5: // SET x,L + regs.hl.l |= (1 << bit_bitnum); break; + case 0x6: // SET x,(HL) + { unsigned char tmp; + tmp = get1(regs.HL); + tmp |= (1 << bit_bitnum); + store1(regs.HL, tmp); + vc.rd++; + vc.wr++; + } + break; + case 0x7: // SET x,A + regs.raf.A |= (1 << bit_bitnum); break; + } + return(resGO); +} + +/******** start CB codes *****************/ +int +cl_z80::inst_cb(void) +{ + t_mem code; + + if (fetch(&code)) + return(resBREAKPOINT); + tick(1); + switch (code) + { + case 0x00: // RLC B + case 0x01: // RLC C + case 0x02: // RLC D + case 0x03: // RLC E + case 0x04: // RLC H + case 0x05: // RLC L + case 0x06: // RLC (HL) + case 0x07: // RLC A + return (inst_cb_rlc(code)); + case 0x08: // RRC B + case 0x09: // RRC C + case 0x0A: // RRC D + case 0x0B: // RRC E + case 0x0C: // RRC H + case 0x0D: // RRC L + case 0x0E: // RRC (HL) + case 0x0F: // RRC A + return (inst_cb_rrc(code)); + case 0x10: // RL B + case 0x11: // RL C + case 0x12: // RL D + case 0x13: // RL E + case 0x14: // RL H + case 0x15: // RL L + case 0x16: // RL (HL) + case 0x17: // RL A + return (inst_cb_rl(code)); + case 0x18: // RR B + case 0x19: // RR C + case 0x1A: // RR D + case 0x1B: // RR E + case 0x1C: // RR H + case 0x1D: // RR L + case 0x1E: // RR (HL) + case 0x1F: // RR A + return (inst_cb_rr(code)); + case 0x20: // SLA B + case 0x21: // SLA C + case 0x22: // SLA D + case 0x23: // SLA E + case 0x24: // SLA H + case 0x25: // SLA L + case 0x26: // SLA (HL) + case 0x27: // SLA A + return (inst_cb_sla(code)); + case 0x28: // SRA B + case 0x29: // SRA C + case 0x2A: // SRA D + case 0x2B: // SRA E + case 0x2C: // SRA H + case 0x2D: // SRA L + case 0x2E: // SRA (HL) + case 0x2F: // SRA A + return (inst_cb_sra(code)); + case 0x30: // SLIA B (Shift Left Inverted Arithmetic) + case 0x31: // SLIA C like SLA, but shifts in a 1 bit + case 0x32: // SLIA D + case 0x33: // SLIA E + case 0x34: // SLIA H + case 0x35: // SLIA L + case 0x36: // SLIA (HL) + case 0x37: // SLIA A + return (inst_cb_slia(code)); + case 0x38: // SRL B + case 0x39: // SRL C + case 0x3A: // SRL D + case 0x3B: // SRL E + case 0x3C: // SRL H + case 0x3D: // SRL L + case 0x3E: // SRL (HL) + case 0x3F: // SRL A + return (inst_cb_srl(code)); + case 0x40: // BIT 0,B + case 0x41: // BIT 0,C + case 0x42: // BIT 0,D + case 0x43: // BIT 0,E + case 0x44: // BIT 0,H + case 0x45: // BIT 0,L + case 0x46: // BIT 0,(HL) + case 0x47: // BIT 0,A + case 0x48: // BIT 1,B + case 0x49: // BIT 1,C + case 0x4A: // BIT 1,D + case 0x4B: // BIT 1,E + case 0x4C: // BIT 1,H + case 0x4D: // BIT 1,L + case 0x4E: // BIT 1,(HL) + case 0x4F: // BIT 1,A + case 0x50: // BIT 2,B + case 0x51: // BIT 2,C + case 0x52: // BIT 2,D + case 0x53: // BIT 2,E + case 0x54: // BIT 2,H + case 0x55: // BIT 2,L + case 0x56: // BIT 2,(HL) + case 0x57: // BIT 2,A + case 0x58: // BIT 3,B + case 0x59: // BIT 3,C + case 0x5A: // BIT 3,D + case 0x5B: // BIT 3,E + case 0x5C: // BIT 3,H + case 0x5D: // BIT 3,L + case 0x5E: // BIT 3,(HL) + case 0x5F: // BIT 3,A + case 0x60: // BIT 4,B + case 0x61: // BIT 4,C + case 0x62: // BIT 4,D + case 0x63: // BIT 4,E + case 0x64: // BIT 4,H + case 0x65: // BIT 4,L + case 0x66: // BIT 4,(HL) + case 0x67: // BIT 4,A + case 0x68: // BIT 5,B + case 0x69: // BIT 5,C + case 0x6A: // BIT 5,D + case 0x6B: // BIT 5,E + case 0x6C: // BIT 5,H + case 0x6D: // BIT 5,L + case 0x6E: // BIT 5,(HL) + case 0x6F: // BIT 5,A + case 0x70: // BIT 6,B + case 0x71: // BIT 6,C + case 0x72: // BIT 6,D + case 0x73: // BIT 6,E + case 0x74: // BIT 6,H + case 0x75: // BIT 6,L + case 0x76: // BIT 6,(HL) + case 0x77: // BIT 6,A + case 0x78: // BIT 7,B + case 0x79: // BIT 7,C + case 0x7A: // BIT 7,D + case 0x7B: // BIT 7,E + case 0x7C: // BIT 7,H + case 0x7D: // BIT 7,L + case 0x7E: // BIT 7,(HL) + case 0x7F: // BIT 7,A + return (inst_cb_bit(code)); + case 0x80: // RES 0,B + case 0x81: // RES 0,C + case 0x82: // RES 0,D + case 0x83: // RES 0,E + case 0x84: // RES 0,H + case 0x85: // RES 0,L + case 0x86: // RES 0,(HL) + case 0x87: // RES 0,A + case 0x88: // RES 1,B + case 0x89: // RES 1,C + case 0x8A: // RES 1,D + case 0x8B: // RES 1,E + case 0x8C: // RES 1,H + case 0x8D: // RES 1,L + case 0x8E: // RES 1,(HL) + case 0x8F: // RES 1,A + case 0x90: // RES 2,B + case 0x91: // RES 2,C + case 0x92: // RES 2,D + case 0x93: // RES 2,E + case 0x94: // RES 2,H + case 0x95: // RES 2,L + case 0x96: // RES 2,(HL) + case 0x97: // RES 2,A + case 0x98: // RES 3,B + case 0x99: // RES 3,C + case 0x9A: // RES 3,D + case 0x9B: // RES 3,E + case 0x9C: // RES 3,H + case 0x9D: // RES 3,L + case 0x9E: // RES 3,(HL) + case 0x9F: // RES 3,A + case 0xA0: // RES 4,B + case 0xA1: // RES 4,C + case 0xA2: // RES 4,D + case 0xA3: // RES 4,E + case 0xA4: // RES 4,H + case 0xA5: // RES 4,L + case 0xA6: // RES 4,(HL) + case 0xA7: // RES 4,A + case 0xA8: // RES 5,B + case 0xA9: // RES 5,C + case 0xAA: // RES 5,D + case 0xAB: // RES 5,E + case 0xAC: // RES 5,H + case 0xAD: // RES 5,L + case 0xAE: // RES 5,(HL) + case 0xAF: // RES 5,A + case 0xB0: // RES 6,B + case 0xB1: // RES 6,C + case 0xB2: // RES 6,D + case 0xB3: // RES 6,E + case 0xB4: // RES 6,H + case 0xB5: // RES 6,L + case 0xB6: // RES 6,(HL) + case 0xB7: // RES 6,A + case 0xB8: // RES 7,B + case 0xB9: // RES 7,C + case 0xBA: // RES 7,D + case 0xBB: // RES 7,E + case 0xBC: // RES 7,H + case 0xBD: // RES 7,L + case 0xBE: // RES 7,(HL) + case 0xBF: // RES 7,A + return (inst_cb_res(code)); + case 0xC0: // SET 0,B + case 0xC1: // SET 0,C + case 0xC2: // SET 0,D + case 0xC3: // SET 0,E + case 0xC4: // SET 0,H + case 0xC5: // SET 0,L + case 0xC6: // SET 0,(HL) + case 0xC7: // SET 0,A + case 0xC8: // SET 1,B + case 0xC9: // SET 1,C + case 0xCA: // SET 1,D + case 0xCB: // SET 1,E + case 0xCC: // SET 1,H + case 0xCD: // SET 1,L + case 0xCE: // SET 1,(HL) + case 0xCF: // SET 1,A + case 0xD0: // SET 2,B + case 0xD1: // SET 2,C + case 0xD2: // SET 2,D + case 0xD3: // SET 2,E + case 0xD4: // SET 2,H + case 0xD5: // SET 2,L + case 0xD6: // SET 2,(HL) + case 0xD7: // SET 2,A + case 0xD8: // SET 3,B + case 0xD9: // SET 3,C + case 0xDA: // SET 3,D + case 0xDB: // SET 3,E + case 0xDC: // SET 3,H + case 0xDD: // SET 3,L + case 0xDE: // SET 3,(HL) + case 0xDF: // SET 3,A + case 0xE0: // SET 4,B + case 0xE1: // SET 4,C + case 0xE2: // SET 4,D + case 0xE3: // SET 4,E + case 0xE4: // SET 4,H + case 0xE5: // SET 4,L + case 0xE6: // SET 4,(HL) + case 0xE7: // SET 4,A + case 0xE8: // SET 5,B + case 0xE9: // SET 5,C + case 0xEA: // SET 5,D + case 0xEB: // SET 5,E + case 0xEC: // SET 5,H + case 0xED: // SET 5,L + case 0xEE: // SET 5,(HL) + case 0xEF: // SET 5,A + case 0xF0: // SET 6,B + case 0xF1: // SET 6,C + case 0xF2: // SET 6,D + case 0xF3: // SET 6,E + case 0xF4: // SET 6,H + case 0xF5: // SET 6,L + case 0xF6: // SET 6,(HL) + case 0xF7: // SET 6,A + case 0xF8: // SET 7,B + case 0xF9: // SET 7,C + case 0xFA: // SET 7,D + case 0xFB: // SET 7,E + case 0xFC: // SET 7,H + case 0xFD: // SET 7,L + case 0xFE: // SET 7,(HL) + case 0xFF: // SET 7,A + return (inst_cb_set(code)); + } + /*if (PC) + PC--; + else + PC= get_mem_size(MEM_ROM_ID)-1;*/ + PC= rom->inc_address(PC, -1); + return(resINV_INST); +} + +/* End of z80.src/inst_cb.cc */ diff --git a/sim/ucsim/z80.src/inst_dd.cc b/sim/ucsim/z80.src/inst_dd.cc new file mode 100644 index 0000000..a1db99b --- /dev/null +++ b/sim/ucsim/z80.src/inst_dd.cc @@ -0,0 +1,54 @@ +/* + * Simulator of microcontrollers (inst_dd.cc) + * dd escaped multi-byte opcodes. + * + * some z80 code base from Karl Bongers karl@turbobit.com + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#include "ddconfig.h" + +// local +#include "z80cl.h" +#include "regsz80.h" +#include "z80mac.h" + +#define regs_iX_h regs.ix.h +#define regs_iX_l regs.ix.l +#define regs_IX_OR_IY regs.IX +#define inst_Xd_ld inst_dd_ld +#define inst_Xd_add inst_dd_add +#define inst_Xd_push inst_dd_push +#define inst_Xd_inc inst_dd_inc +#define inst_Xd_dec inst_dd_dec +#define inst_Xd_misc inst_dd_misc +#define inst_Xd inst_dd +#define inst_Xdcb inst_ddcb + +#define inst_Xfix 0xDD + +#include "inst_xd.cc" + +/* End of z80.src/inst_dd.cc */ diff --git a/sim/ucsim/z80.src/inst_ddcb.cc b/sim/ucsim/z80.src/inst_ddcb.cc new file mode 100644 index 0000000..4d04fb2 --- /dev/null +++ b/sim/ucsim/z80.src/inst_ddcb.cc @@ -0,0 +1,53 @@ +/* + * Simulator of microcontrollers (inst_ddcb.cc) + * DD CB escaped multi-byte opcodes for Z80. + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#include "ddconfig.h" + +// local +#include "z80cl.h" +#include "regsz80.h" +#include "z80mac.h" + + +#define regs_IX_OR_IY regs.IX +#define inst_XXcb_rlc inst_ddcb_rlc +#define inst_XXcb_rrc inst_ddcb_rrc +#define inst_XXcb_rl inst_ddcb_rl +#define inst_XXcb_rr inst_ddcb_rr +#define inst_XXcb_sla inst_ddcb_sla +#define inst_XXcb_sra inst_ddcb_sra +#define inst_XXcb_slia inst_ddcb_slia +#define inst_XXcb_srl inst_ddcb_srl +#define inst_XXcb_bit inst_ddcb_bit +#define inst_XXcb_res inst_ddcb_res +#define inst_XXcb_set inst_ddcb_set +#define inst_XXcb inst_ddcb + +#include "inst_xxcb.cc" + +/* End of z80.src/inst_ddcb.cc */ diff --git a/sim/ucsim/z80.src/inst_ed.cc b/sim/ucsim/z80.src/inst_ed.cc new file mode 100644 index 0000000..1ff2c34 --- /dev/null +++ b/sim/ucsim/z80.src/inst_ed.cc @@ -0,0 +1,433 @@ +/* + * Simulator of microcontrollers (inst_ed.cc) + * ED escaped multi-byte opcodes for Z80. + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#include "ddconfig.h" + +// local +#include "z80cl.h" +#include "regsz80.h" +#include "z80mac.h" + + +#define tst_A_bytereg(br) { \ + ubtmp = regs.raf.A & (br); \ + regs.raf.F &= ~(BIT_ALL); /* clear these */ \ + regs.raf.F |= BIT_A; \ + if (ubtmp == 0) regs.raf.F |= BIT_Z; \ + if (ubtmp & 0x80) regs.raf.F |= BIT_S; \ + if (parity(ubtmp)) regs.raf.F |= BIT_P; \ +} + + +int cl_z80::inst_ed_(t_mem code) +{ + unsigned short tw; + u8_t ubtmp; + + if (code < 0x40) + { + if (!(type->type & (CPU_Z180 | CPU_EZ80))) + return resINV_INST; + + switch ( code & 0x07 ) + { + case 0: // IN0 + ubtmp = fetch1( ); + reg_g_store( (code >> 3) & 0x07, in_byte( ubtmp ) ); + return resGO; + + case 1: // OUT0 + ubtmp = fetch1( ); + out_byte( ubtmp, reg_g_read( (code >> 3) & 0x07 ) ); + return resGO; + + case 4: // TST + tst_A_bytereg(reg_g_read( (code >> 3) & 0x07 )); + return resGO; + + default: + return resINV_INST; + } + } + + switch(code) + { + +#if 0 + case 0x40: // IN B,(C) + return(resGO); + case 0x41: // OUT (C),B + return(resGO); +#endif + case 0x42: // SBC HL,BC + sbc_HL_wordreg(regs.BC); + return(resGO); + case 0x43: // LD (nnnn),BC + tw = fetch2(); + store2(tw, regs.BC); + vc.wr+= 2; + return(resGO); + case 0x44: // NEG + regs.raf.F &= ~(BIT_ALL); /* clear these */ + if (regs.raf.A != 0) regs.raf.F |= BIT_C; + if (regs.raf.A == 0x80) regs.raf.F |= BIT_P; + if ((regs.raf.A & 0x0F) != 0) regs.raf.F |= BIT_A; + regs.raf.A = 0 - regs.raf.A; + regs.raf.F |= BIT_N; /* not addition */ + if (regs.raf.A == 0) regs.raf.F |= BIT_Z; + if (regs.raf.A & 0x80) regs.raf.F |= BIT_S; + return(resGO); + case 0x45: // RETN (return from non-maskable interrupt) + pop2(PC); + vc.rd+= 2; + return(resGO); +#if 0 + case 0x46: // IM 0 + /* interrupt device puts opcode on data bus */ + return(resGO); +#endif + case 0x47: // LD IV,A + regs.iv = regs.raf.A; + return(resGO); + + case 0x48: // IN C,(C) + vc.rd++; + return(resGO); + case 0x49: // OUT (C),C + vc.wr++; + return(resGO); + + case 0x4A: // ADC HL,BC + adc_HL_wordreg(regs.BC); + return(resGO); + case 0x4B: // LD BC,(nnnn) + tw = fetch2(); + regs.BC = get2(tw); + vc.rd+= 2; + return(resGO); + case 0x4C: // MLT BC + if (!(type->type & (CPU_Z180 | CPU_EZ80))) + return(resINV_INST); + regs.BC = (unsigned long)(regs.bc.h) * (unsigned long)(regs.bc.l); + return(resGO); + case 0x4D: // RETI (return from interrupt) + pop2(PC); + vc.rd+= 2; + return(resGO); + case 0x4F: // LD R,A + /* Load "refresh" register(whats that?) */ + return(resGO); + + case 0x50: // IN D,(C) + vc.rd++; + return(resGO); + case 0x51: // OUT (C),D + vc.wr++; + return(resGO); + + case 0x52: // SBC HL,DE + sbc_HL_wordreg(regs.DE); + return(resGO); + case 0x53: // LD (nnnn),DE + tw = fetch2(); + store2(tw, regs.DE); + vc.wr+= 2; + return(resGO); +#if 0 + case 0x56: // IM 1 + return(resGO); +#endif + case 0x57: // LD A,IV + regs.raf.A = regs.iv; + return(resGO); + + case 0x58: // IN E,(C) + vc.rd++; + return(resGO); + case 0x59: // OUT (C),E + vc.wr++; + return(resGO); + + case 0x5A: // ADC HL,DE + adc_HL_wordreg(regs.DE); + return(resGO); + case 0x5B: // LD DE,(nnnn) + tw = fetch2(); + regs.DE = get2(tw); + vc.rd+= 2; + return(resGO); + case 0x5C: // MLT DE + if (!(type->type & (CPU_Z180 | CPU_EZ80))) + return(resINV_INST); + regs.DE = (unsigned long)(regs.de.h) * (unsigned long)(regs.de.l); + return(resGO); +#if 0 + case 0x5E: // IM 2 + return(resGO); + case 0x5F: // LD A,R + return(resGO); + case 0x60: // IN H,(C) + vc.rd++; + return(resGO); + case 0x61: // OUT (C),H + vc.wr++; + return(resGO); +#endif + case 0x62: // SBC HL,HL + sbc_HL_wordreg(regs.HL); + return(resGO); + case 0x63: // LD (nnnn),HL opcode 22 does the same faster + tw = fetch2(); + store2(tw, regs.HL); + vc.wr+= 2; + return(resGO); + case 0x64: + if (!(type->type & (CPU_Z180 | CPU_EZ80))) + return(resINV_INST); + ubtmp = fetch(); // TST A,n + tst_A_bytereg(ubtmp); + return(resGO); + + case 0x67: // RRD + ubtmp = get1(regs.HL); + store1(regs.HL, (ubtmp >> 4) | (regs.raf.A << 4)); + regs.raf.A = (regs.raf.A & 0xf0) | (ubtmp & 0x0f); + return(resGO); + + case 0x68: // IN L,(C) + vc.rd++; + return(resGO); + case 0x69: // OUT (C),L + vc.wr++; + return(resGO); + + case 0x6A: // ADC HL,HL + adc_HL_wordreg(regs.HL); + return(resGO); + case 0x6B: // LD HL,(nnnn) opcode 2A does the same faster + tw = fetch2(); + regs.HL = get2(tw); + vc.rd+= 2; + return(resGO); + case 0x6C: // MLT HL + if (!(type->type & (CPU_Z180 | CPU_EZ80))) + return(resINV_INST); + regs.HL = (unsigned long)(regs.hl.h) * (unsigned long)(regs.hl.l); + return(resGO); + + case 0x6F: // RLD + ubtmp = get1(regs.HL); + store1(regs.HL, (ubtmp << 4) | (regs.raf.A & 0x0f)); + regs.raf.A = (regs.raf.A & 0xf0) | (ubtmp >> 4); + return(resGO); + + case 0x70: // IN (C) set flags only (TSTI) + vc.rd++; + return(resGO); + case 0x71: // OUT (C),0 + vc.wr++; + return(resGO); + + case 0x72: // SBC HL,SP + sbc_HL_wordreg(regs.SP); + return(resGO); + case 0x73: // LD (nnnn),SP + tw = fetch2(); + store2(tw, regs.SP); + vc.wr+= 2; + return(resGO); + + case 0x78: // IN A,(C) + vc.rd++; + return(resGO); + case 0x79: // OUT (C),A + vc.wr++; + return(resGO); + + case 0x7A: // ADC HL,SP + adc_HL_wordreg(regs.SP); + return(resGO); + case 0x7B: // LD SP,(nnnn) + tw = fetch2(); + regs.SP = get2(tw); + vc.rd+= 2; + return(resGO); + + case 0x7C: // MLT SP + //if(type != CPU_Z180) + return(resINV_INST); + //regs.SP = (unsigned long)(regs.sp.h) * (unsigned long)(regs.sp.l); + return(resGO); + case 0xA0: // LDI + // BC - count, sourc=HL, dest=DE. *DE++ = *HL++, --BC until zero + regs.raf.F &= ~(BIT_P | BIT_N | BIT_A); /* clear these */ + store1(regs.DE, get1(regs.HL)); + ++regs.HL; + ++regs.DE; + --regs.BC; + if (regs.BC != 0) regs.raf.F |= BIT_P; + return(resGO); + case 0xA1: // CPI + // compare acc with mem(HL), if ACC=0 set Z flag. Incr HL, decr BC. + { + unsigned char tmp; + tmp = get1(regs.HL); + cp_bytereg(tmp); + ++regs.HL; + --regs.BC; + if (regs.BC != 0) regs.raf.F |= BIT_P; + } + return(resGO); + + case 0xA2: // INI + return(resGO); + case 0xA3: // OUTI + return(resGO); + + case 0xA8: // LDD + // BC - count, source=HL, dest=DE. *DE-- = *HL--, --BC until zero + regs.raf.F &= ~(BIT_P | BIT_N | BIT_A); /* clear these */ + store1(regs.DE, get1(regs.HL)); + --regs.HL; + --regs.DE; + --regs.BC; + if (regs.BC != 0) regs.raf.F |= BIT_P; + vc.rd++; + vc.wr++; + return(resGO); + case 0xA9: // CPD +/* fixme: checkme, compare to other emul. */ + + regs.raf.F &= ~(BIT_ALL); /* clear these */ + if ((regs.raf.A - get1(regs.HL)) == 0) { + regs.raf.F |= (BIT_Z | BIT_P); + } + ++regs.HL; + --regs.BC; + if (regs.BC != 0) regs.raf.F |= BIT_P; + vc.rd++; + + return(resGO); + + case 0xAA: // IND + return(resGO); + case 0xAB: // OUTD + return(resGO); + + case 0xB0: // LDIR + // BC - count, sourc=HL, dest=DE. *DE++ = *HL++, --BC until zero + regs.raf.F &= ~(BIT_P | BIT_N | BIT_A); /* clear these */ + do { + store1(regs.DE, get1(regs.HL)); + ++regs.HL; + ++regs.DE; + --regs.BC; + vc.rd++; + vc.wr++; + } while (regs.BC != 0); + return(resGO); + + case 0xB1: // CPIR + // compare acc with mem(HL), if ACC=0 set Z flag. Incr HL, decr BC. + regs.raf.F &= ~(BIT_P | BIT_A | BIT_Z | BIT_S); /* clear these */ + regs.raf.F |= BIT_N; + do { + if((regs.raf.A - get1(regs.HL)) == 0) + regs.raf.F |= BIT_Z; + else + regs.raf.F &= ~BIT_Z; + if((regs.raf.A - get1(regs.HL)) & 0x80) + regs.raf.F |= BIT_S; + else + regs.raf.F &= ~BIT_S; +/* fixme: set BIT_A correctly. */ + ++regs.HL; + --regs.BC; + vc.rd++; + } while (regs.BC != 0 && (regs.raf.F & BIT_Z) == 0); + if(regs.BC != 0) + regs.raf.F |= BIT_P; + + return(resGO); +#if 0 + case 0xB2: // INIR + return(resGO); + case 0xB3: // OTIR + return(resGO); +#endif + case 0xB8: // LDDR + // BC - count, source=HL, dest=DE. *DE-- = *HL--, --BC until zero + regs.raf.F &= ~(BIT_P | BIT_N | BIT_A); /* clear these */ + do { + store1(regs.DE, get1(regs.HL)); + --regs.HL; + --regs.DE; + --regs.BC; + vc.rd++; + vc.wr++; + } while (regs.BC != 0); + return(resGO); + case 0xB9: // CPDR + // compare acc with mem(HL), if ACC=0 set Z flag. Incr HL, decr BC. + regs.raf.F &= ~(BIT_ALL); /* clear these */ + do { + if ((regs.raf.A - get1(regs.HL)) == 0) { + regs.raf.F |= (BIT_Z | BIT_P); + break; + } + --regs.HL; + --regs.BC; + vc.rd++; + } while (regs.BC != 0); + return(resGO); +#if 0 + case 0xBA: // INDR + return(resGO); + case 0xBB: // OTDR + return(resGO); +#endif + + default: + return(resINV_INST); + } + + return(resGO); +} + +/******** start ED codes *****************/ +int cl_z80::inst_ed(t_mem prefix) +{ + t_mem code; + + if (fetch(&code)) + return(resBREAKPOINT); + + return inst_ed_(code); +} + +/* End of z80.src/inst_ed.cc */ diff --git a/sim/ucsim/z80.src/inst_ed_r2k.cc b/sim/ucsim/z80.src/inst_ed_r2k.cc new file mode 100644 index 0000000..fd3c8b0 --- /dev/null +++ b/sim/ucsim/z80.src/inst_ed_r2k.cc @@ -0,0 +1,474 @@ +/*
+ * Simulator of microcontrollers (inst_ed.cc)
+ * ED escaped multi-byte opcodes for Z80.
+ *
+ * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
+ *
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING. If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#include "ddconfig.h"
+
+// local
+#include "r2kcl.h"
+#include "z80mac.h"
+
+
+int cl_r2k::inst_ed_(t_mem code)
+{
+ unsigned short tw;
+
+ switch(code)
+ {
+ case 0x41:
+ regs.aBC = regs.DE;
+ break;
+
+ case 0x42: // SBC HL,BC
+ sbc_HL_wordreg(regs.BC);
+ break;
+
+ case 0x43: // LD (nnnn),BC
+ tw = fetch2();
+ store2(tw, regs.BC);
+ vc.wr+= 2;
+ break;
+
+ case 0x44: // NEG
+ regs.raf.F &= ~(BIT_ALL); /* clear these */
+ if (regs.raf.A != 0) regs.raf.F |= BIT_C;
+ if (regs.raf.A == 0x80) regs.raf.F |= BIT_P;
+ if ((regs.raf.A & 0x0F) != 0) regs.raf.F |= BIT_A;
+ regs.raf.A = 0 - regs.raf.A;
+ regs.raf.F |= BIT_N; /* not addition */
+ if (regs.raf.A == 0) regs.raf.F |= BIT_Z;
+ if (regs.raf.A & 0x80) regs.raf.F |= BIT_S;
+ break;
+
+ case 0x46: // ipset0
+ case 0x56: // ipset1
+ case 0x4E: // ipset2
+ case 0x5E: // ipset3
+ ip = ((ip << 2) & 0xFC);
+ ip |= (code >> 3) & 0x03;
+ break;
+
+ case 0x47: // LD EIR,A
+ eir = regs.raf.A;
+ break;
+ case 0x49:
+ regs.aBC = regs.BC;
+ break;
+
+ case 0x4A: // ADC HL,BC
+ adc_HL_wordreg(regs.BC);
+ break;
+
+ case 0x4B: // LD BC,(nnnn)
+ tw = fetch2();
+ regs.BC = get2(tw);
+ vc.rd+= 2;
+ break;
+
+ case 0x4D: // RETI
+ ip=get1(regs.SP); regs.SP+=1;
+ pop2(PC);
+ vc.rd+= 2;
+ // TODO: chained-atomic, so set some marker
+ break;
+
+ // 0x4E: see 0x46
+ case 0x4F:
+ iir = regs.raf.A;
+ break;
+
+ case 0x51:
+ regs.aDE = regs.DE;
+ break;
+
+ case 0x52: // SBC HL,DE
+ sbc_HL_wordreg(regs.DE);
+ break;
+ case 0x53: // LD (nnnn),DE
+ tw = fetch2();
+ store2(tw, regs.DE);
+ vc.rd+= 2;
+ break;
+
+ case 0x54: // EX (SP),HL
+ tw = get2(regs.SP);
+ store2( regs.SP, regs.HL );
+ regs.HL = tw;
+ vc.rd+= 2;
+ vc.wr+= 2;
+ break;
+
+ // 0x56: see 0x46
+ case 0x57:
+ regs.raf.A = eir;
+ break;
+
+ case 0x59: // LD DE', BC
+ regs.aDE = regs.BC;
+ break;
+
+ case 0x5A: // ADC HL,DE
+ adc_HL_wordreg(regs.DE);
+ break;
+
+ case 0x5B: // LD DE,(nnnn)
+ tw = fetch2();
+ regs.DE = get2(tw);
+ vc.rd+= 2;
+ break;
+
+ case 0x5D: // ipres
+ ip = ((ip >> 2) & 0x3F) | ((ip & 0x03) << 6);
+ break;
+
+ // 0x5E: see 0x46
+
+ case 0x5F: // LD A,IIR
+ regs.raf.A = iir;
+ break;
+
+ case 0x61: // LD HL',DE
+ regs.aHL = regs.DE;
+ break;
+
+ case 0x62: // SBC HL,HL
+ sbc_HL_wordreg(regs.HL);
+ break;
+
+ case 0x63: // LD (nnnn),HL opcode 22 does the same faster
+ tw = fetch2();
+ store2(tw, regs.HL);
+ vc.wr+= 2;
+ break;
+
+ case 0x67: // LD XPC,A
+ mmu.xpc = regs.raf.A;
+ break;
+
+ case 0x69: // LD HL',BC
+ regs.aHL = regs.BC;
+ break;
+
+ case 0x6A: // ADC HL,HL
+ adc_HL_wordreg(regs.HL);
+ break;
+
+ case 0x6B: // LD HL,(nnnn) opcode 2A does the same faster
+ tw = fetch2();
+ regs.HL = get2(tw);
+ vc.rd+= 2;
+ break;
+
+ case 0x72: // SBC HL,SP
+ sbc_HL_wordreg(regs.SP);
+ break;
+ case 0x73: // LD (nnnn),SP
+ tw = fetch2();
+ store2(tw, regs.SP);
+ vc.wr+= 2;
+ break;
+
+ case 0x76: // PUSH IP
+ push1(ip);
+ vc.wr+= 2;
+ break;
+
+ case 0x77: // LD A,XPC
+ regs.raf.A = mmu.xpc;
+ break;
+
+ case 0x7A: // ADC HL,SP
+ adc_HL_wordreg(regs.SP);
+ break;
+ case 0x7B: // LD SP,(nnnn)
+ tw = fetch2();
+ regs.SP = get2(tw);
+ vc.rd+= 2;
+ break;
+
+ case 0x7D: // LD IY, HL
+ regs.IY = regs.HL;
+ break;
+
+ case 0x7E:
+ ip=get1(regs.SP); regs.SP+=1;
+ vc.rd++;
+ break;
+
+ case 0xA0: // LDI
+ // BC - count, sourc=HL, dest=DE. *DE++ = *HL++, --BC until zero
+ regs.raf.F &= ~(BIT_P | BIT_N | BIT_A); /* clear these */
+ store1(regs.DE, get1(regs.HL));
+ ++regs.HL;
+ ++regs.DE;
+ --regs.BC;
+ vc.rd++;
+ vc.wr++;
+ if (regs.BC != 0) regs.raf.F |= BIT_P;
+ return(resGO);
+
+ case 0xA8: // LDD
+ // BC - count, source=HL, dest=DE. *DE-- = *HL--, --BC until zero
+ regs.raf.F &= ~(BIT_P | BIT_N | BIT_A); /* clear these */
+ store1(regs.DE, get1(regs.HL));
+ --regs.HL;
+ --regs.DE;
+ --regs.BC;
+ vc.rd++;
+ vc.wr++;
+ if (regs.BC != 0) regs.raf.F |= BIT_P;
+ return(resGO);
+
+ case 0xB0: // LDIR
+ // BC - count, sourc=HL, dest=DE. *DE++ = *HL++, --BC until zero
+ regs.raf.F &= ~(BIT_P | BIT_N | BIT_A); /* clear these */
+
+ tw = get1(regs.HL);
+ store1(regs.DE, tw);
+ ++regs.HL;
+ ++regs.DE;
+ --regs.BC;
+ vc.rd++;
+ vc.wr++;
+ if (regs.BC != 0)
+ PC = ins_start;
+ return(resGO);
+
+ case 0xB8: // LDDR
+ // BC - count, source=HL, dest=DE. *DE-- = *HL--, --BC until zero
+ regs.raf.F &= ~(BIT_P | BIT_N | BIT_A); /* clear these */
+
+ tw = get1(regs.HL);
+ store1(regs.DE, tw);
+ --regs.HL;
+ --regs.DE;
+ --regs.BC;
+ vc.rd++;
+ vc.wr++;
+
+ if (regs.BC != 0)
+ PC = ins_start;
+ return(resGO);
+
+ case 0xEA: // CALL (HL)
+ push2(PC);
+ PC = regs.HL;
+ vc.wr+= 2;
+ return(resGO);
+
+
+ default:
+ return(resINV_INST);
+ }
+
+ return(resGO);
+}
+
+int cl_r3ka::inst_ed_(t_mem code)
+{
+ u8_t tb;
+
+ switch(code)
+ {
+ case 0x66: // PUSH SU
+ push1(SU);
+ vc.wr++;
+ return(resGO);
+
+ case 0x6E: // POP SU
+ SU = get1(regs.SP);
+ regs.SP++;
+ vc.rd++;
+ return(resGO);
+
+ case 0x6F: // SETUSR
+ SU = ((SU << 2) & 0xFC) | 0x01;
+ return(resGO);
+
+ case 0x7D: // SURES
+ SU = ((SU >> 2) & 0x3F) | ((SU << 6) & 0xC0);
+ return(resGO);
+
+ case 0x7F: // RDMODE
+ regs.raf.F &= ~(BIT_C);
+ if (SU & 0x01)
+ regs.raf.F |= BIT_C;
+ return(resGO);
+
+ case 0x90: // LDISR
+ // repeat (cnt=BC) { (DE) <= (HL++) } /* normally has io prefix */
+ /* TODO: fix IOI/IOE behavior */
+ tb = get1(regs.HL);
+ store1( regs.DE, tb );
+ regs.HL++;
+ regs.BC--;
+ vc.rd++;
+ vc.wr++;
+ if (regs.BC)
+ PC = ins_start;
+ return(resGO);
+
+ case 0x98: // LDDSR
+ /* TODO: fix IOI/IOE behavior */
+ // repeat (cnt=BC) { (DE) <= (HL--) } /* normally has io prefix */
+ tb = get1(regs.HL);
+ store1( regs.DE, tb );
+ regs.HL--;
+ regs.BC--;
+ vc.rd++;
+ vc.wr++;
+ if (regs.BC)
+ PC = ins_start;
+ return(resGO);
+
+ case 0xC0: // UMA
+ // repeat while BC != 0:
+ // {CF:DE':(HL)} <= (IX) + [(IY)*DE + DE' + CF];
+ // BC--; IX++; IY++; HL++;
+ {
+ u32_t tmp;
+
+ /* scale a sum for operand pointed to by IY */
+ tmp = get1(regs.IY);
+ tmp *= regs.DE;
+ tmp += regs.aDE;
+ tmp += (regs.raf.F & BIT_C) ? 1 : 0;
+
+ /* simple add for operand pointed to by IX */
+ tmp += get1(regs.IX);
+
+ /* store the result(s) */
+ store1( regs.HL, tmp & 0xFF );
+ regs.aDE = ((tmp >> 8) & 0xFFFF);
+ regs.raf.F &= ~(BIT_C);
+ regs.raf.F |= (tmp >> 24) ? BIT_C : 0;
+ vc.rd+= 2;
+ vc.wr++;
+ }
+
+ regs.IX++;
+ regs.IY++;
+ regs.HL++;
+ regs.BC--;
+ if (regs.BC)
+ PC = ins_start;
+ return(resGO);
+
+ case 0xC8: // UMS
+ // repeat while BC != 0:
+ // {CF:DE':(HL)} <= (IX) - [(IY)*DE + DE' + CF];
+ // BC--; IX++; IY++; HL++;
+ {
+ u32_t tmp;
+
+ /* scale a sum for operand pointed to by IY */
+ tmp = get1(regs.IY);
+ tmp *= regs.DE;
+ tmp += regs.aDE;
+ tmp += (regs.raf.F & BIT_C) ? 1 : 0;
+
+ /* subtract above from operand pointed to by IX */
+ tmp = get1(regs.IX) - tmp;
+
+ /* store the result(s) */
+ store1( regs.HL, tmp & 0xFF );
+ regs.aDE = ((tmp >> 8) & 0xFFFF);
+ regs.raf.F &= ~(BIT_C);
+ regs.raf.F |= (tmp >> 24) ? BIT_C : 0;
+ vc.rd+= 2;
+ vc.wr++;
+ }
+
+ regs.IX++;
+ regs.IY++;
+ regs.HL++;
+ regs.BC--;
+ if (regs.BC)
+ PC = ins_start;
+ return(resGO);
+
+ case 0xD0: // LSIDR
+ /* TODO: fix IOI/IOE behavior */
+ // repeat (cnt=BC) { (DE++) <= (HL) } /* normally has io prefix */
+ tb = get1( regs.HL );
+ store1( regs.DE, tb );
+ regs.DE++;
+ regs.BC--;
+ vc.rd++;
+ vc.wr++;
+ if (regs.BC)
+ PC = ins_start;
+ return(resGO);
+
+ case 0xD8: // LSDDR
+ /* TODO: fix IOI/IOE behavior */
+ // repeat (cnt=BC) { (DE--) <= (HL) } /* normally has io prefix */
+ tb = get1( regs.HL );
+ store1( regs.DE, tb );
+ regs.DE--;
+ regs.BC--;
+ vc.rd++;
+ vc.wr++;
+ if (regs.BC)
+ PC = ins_start;
+ return(resGO);
+
+ case 0xF0: // LSIR
+ /* TODO: fix IOI/IOE behavior */
+ // repeat (cnt=BC) { (DE++) <= (HL++) }
+ tb = get1( regs.HL );
+ store1( regs.DE, tb );
+ regs.DE++;
+ regs.HL++;
+ regs.BC--;
+ vc.rd++;
+ vc.wr++;
+ if (regs.BC)
+ PC = ins_start;
+ return(resGO);
+
+ case 0xF8: // LSDR
+ /* TODO: fix IOI/IOE behavior */
+ // repeat (cnt=BC) { (DE--) <= (HL--) }
+ tb = get1( regs.HL );
+ store1( regs.DE, tb );
+ regs.DE--;
+ regs.HL--;
+ regs.BC--;
+ vc.rd++;
+ vc.wr++;
+ if (regs.BC)
+ PC = ins_start;
+ return(resGO);
+
+ default:
+ return cl_r2k::inst_ed_(code);
+ }
+}
+
+//IDET system mode violation interrupt if in user mode
+
diff --git a/sim/ucsim/z80.src/inst_fd.cc b/sim/ucsim/z80.src/inst_fd.cc new file mode 100644 index 0000000..29aaa79 --- /dev/null +++ b/sim/ucsim/z80.src/inst_fd.cc @@ -0,0 +1,54 @@ +/* + * Simulator of microcontrollers (inst_fd.cc) + * FD escaped multi-byte opcodes. + * + * + * Copyright (C) 1999,2001 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + * some z80 code base from Karl Bongers karl@turbobit.com + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#include "ddconfig.h" + +// local +#include "z80cl.h" +#include "regsz80.h" +#include "z80mac.h" + +#define regs_iX_h regs.iy.h +#define regs_iX_l regs.iy.l +#define regs_IX_OR_IY regs.IY +#define inst_Xd_ld inst_fd_ld +#define inst_Xd_add inst_fd_add +#define inst_Xd_push inst_fd_push +#define inst_Xd_inc inst_fd_inc +#define inst_Xd_dec inst_fd_dec +#define inst_Xd_misc inst_fd_misc +#define inst_Xd inst_fd +#define inst_Xdcb inst_fdcb + +#define inst_Xfix 0xFD + +#include "inst_xd.cc" + +/* End of z80.src/inst_fd.cc */ diff --git a/sim/ucsim/z80.src/inst_fdcb.cc b/sim/ucsim/z80.src/inst_fdcb.cc new file mode 100644 index 0000000..cbd5e3d --- /dev/null +++ b/sim/ucsim/z80.src/inst_fdcb.cc @@ -0,0 +1,52 @@ +/* + * Simulator of microcontrollers (inst_fdcb.cc) + * FD CB escaped multi-byte opcodes for Z80. + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#include "ddconfig.h" + +// local +#include "z80cl.h" +#include "regsz80.h" +#include "z80mac.h" + +#define regs_IX_OR_IY regs.IY +#define inst_XXcb_rlc inst_fdcb_rlc +#define inst_XXcb_rrc inst_fdcb_rrc +#define inst_XXcb_rl inst_fdcb_rl +#define inst_XXcb_rr inst_fdcb_rr +#define inst_XXcb_sla inst_fdcb_sla +#define inst_XXcb_sra inst_fdcb_sra +#define inst_XXcb_slia inst_fdcb_slia +#define inst_XXcb_srl inst_fdcb_srl +#define inst_XXcb_bit inst_fdcb_bit +#define inst_XXcb_res inst_fdcb_res +#define inst_XXcb_set inst_fdcb_set +#define inst_XXcb inst_fdcb + +#include "inst_xxcb.cc" + +/* End of z80.src/inst_fdcb.cc */ diff --git a/sim/ucsim/z80.src/inst_lr35902.cc b/sim/ucsim/z80.src/inst_lr35902.cc new file mode 100755 index 0000000..c5c1916 --- /dev/null +++ b/sim/ucsim/z80.src/inst_lr35902.cc @@ -0,0 +1,188 @@ +/*
+ * Simulated instructions specific to the LR35902, the Z-80 derivative used
+ * in the gameboy.
+ *
+ * 2011-12-21 created by Leland Morrison
+ *
+ *
+
+This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING. If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+#include "ddconfig.h"
+
+#include "lr35902cl.h"
+
+static u8_t swap_nibbles(u8_t val) {
+ return ((val >> 4) & 0x0f) | ((val << 4) & 0xf0);
+}
+
+int cl_lr35902::inst_cb(void) {
+ u8_t result;
+ t_mem code;
+
+ if ( (peek1( ) & 0xf8) != 0x30 )
+ return cl_z80::inst_cb( );
+
+ code = fetch1();
+
+ /* perform SWAP instead of slia */
+ switch(code) {
+ case 0x30: result = regs.bc.h = swap_nibbles(regs.bc.h); break; /* b */
+ case 0x31: result = regs.bc.l = swap_nibbles(regs.bc.l); break; /* c */
+ case 0x32: result = regs.de.h = swap_nibbles(regs.de.h); break; /* d */
+ case 0x33: result = regs.de.l = swap_nibbles(regs.de.l); break; /* e */
+ case 0x34: result = regs.hl.l = swap_nibbles(regs.hl.h); break; /* h */
+ case 0x35: result = regs.hl.h = swap_nibbles(regs.hl.l); break; /* l */
+ case 0x36: /* SWAP (HL) */
+ {
+ result = swap_nibbles(get1(regs.HL));
+ store1(regs.HL, result);
+ vc.rd++;
+ vc.wr++;
+ }
+ break;
+
+ case 0x37: result = regs.raf.A = swap_nibbles(regs.raf.A); break; /* swap a */
+ default: return resINV_INST;
+ }
+ regs.raf.F = (result)?0:0x80; // all except zero are simply cleared
+ return(resGO);
+}
+
+int cl_lr35902::inst_st_sp_abs(t_mem code) {
+ if (code == 0x08) {
+ u16_t addr = fetch2( );
+ store2( addr, regs.SP );
+ vc.wr+= 2;
+ return(resGO);
+ }
+
+ return resINV_INST;
+}
+
+int cl_lr35902::inst_stop0 (t_mem code) {
+ // TODO: change to wait for a signal for simulated hardware
+ return resHALT;
+}
+
+int cl_lr35902::inst_ldi (t_mem code) {
+ if (code == 0x22) {
+ store1( regs.HL, regs.raf.A );
+ regs.HL ++;
+ vc.wr++;
+ return resGO;
+ } else if (code == 0x2A) {
+ regs.raf.A = get1( regs.HL );
+ regs.HL ++;
+ vc.rd++;
+ return resGO;
+ }
+
+ return resINV_INST;
+}
+
+int cl_lr35902::inst_ldd (t_mem code) {
+ if (code == 0x32) {
+ store1( regs.HL, regs.raf.A );
+ regs.HL --;
+ vc.wr++;
+ return resGO;
+ } else if (code == 0x3A) {
+ regs.raf.A = get1( regs.HL );
+ regs.HL --;
+ vc.rd++;
+ return resGO;
+ }
+
+ return resINV_INST;
+}
+
+int cl_lr35902::inst_ldh (t_mem code) {
+ u16_t addr = 0xFF00 + fetch1( );
+
+ if (code == 0xE0) {
+ store1( addr, regs.raf.A );
+ vc.wr++;
+ return resGO;
+ } else if (code == 0xF0) {
+ regs.raf.A = get1( addr );
+ vc.rd++;
+ return resGO;
+ }
+
+ return resINV_INST;
+}
+
+int cl_lr35902::inst_reti (t_mem code) {
+ /* enable interrupts */
+ cl_z80::inst_ei(0xFB);
+
+ /* pop2(PC); */
+ PC=get2(regs.SP);
+ regs.SP+=2;
+ vc.rd+= 2;
+
+ return resGO;
+}
+
+int cl_lr35902::inst_add_sp_d(t_mem code) {
+ u16_t d = fetch( );
+ /* sign-extend d from 8-bits to 16-bits */
+ d |= (d>>7)*0xFF00;
+
+ regs.raf.F &= ~(BIT_ALL); /* clear these */
+ if ((regs.SP & 0x0FFF) + (d & 0x0FFF) > 0x0FFF)
+ regs.raf.F |= BIT_A;
+ if (regs.SP + (int)(d) > 0xffff)
+ regs.raf.F |= BIT_C;
+
+ regs.SP = (regs.SP + d) & 0xffff;
+
+ return(resGO);
+}
+
+int cl_lr35902::inst_ld16 (t_mem code) {
+ u16_t addr = fetch2( );
+ if (code == 0xEA) {
+ store1( addr, regs.raf.A );
+ vc.wr++;
+ return resGO;
+ } else if (code == 0xFA) {
+ regs.raf.A = get1( addr );
+ vc.rd++;
+ return resGO;
+ }
+
+ return resINV_INST;
+}
+
+int cl_lr35902::inst_ldhl_sp (t_mem code) {
+ u16_t d = fetch( );
+ /* sign-extend d from 8-bits to 16-bits */
+ d |= (d>>7)*0xFF00;
+
+ regs.raf.F &= ~(BIT_ALL); /* clear these */
+ if ((regs.SP & 0x0FFF) + (d & 0x0FFF) > 0x0FFF)
+ regs.raf.F |= BIT_A;
+ if (regs.SP + (int)(d) > 0xffff)
+ regs.raf.F |= BIT_C;
+
+ regs.HL = (regs.SP + d) & 0xffff;
+ return resGO;
+}
+
diff --git a/sim/ucsim/z80.src/inst_r2k.cc b/sim/ucsim/z80.src/inst_r2k.cc new file mode 100644 index 0000000..3210a66 --- /dev/null +++ b/sim/ucsim/z80.src/inst_r2k.cc @@ -0,0 +1,606 @@ +/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING. If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#include "ddconfig.h"
+
+// local
+#include "r2kcl.h"
+#include "z80mac.h"
+
+
+unsigned word_parity( u16_t x ) {
+ // bitcount(x) performed by shift-and-add
+ u16_t tmp = (x & 0x5555) + ((x & 0xAAAA) >> 1);
+ tmp = (tmp & 0x3333) + ((tmp & 0xCCCC) >> 2);
+ tmp = (tmp & 0x0F0F) + ((tmp & 0xF0F0) >> 4);
+ tmp = (tmp & 0x000F) + ((tmp & 0x0F00) >> 8);
+
+ // parity determined by count being odd or even
+ return 0x01 ^ (tmp & 1);
+}
+
+/******** rabbit 2000 memory access helper functions *****************/
+u32_t rabbit_mmu::logical_addr_to_phys( u16_t logical_addr ) {
+ u32_t phys_addr = logical_addr;
+ unsigned segnib = logical_addr >> 12;
+
+ if (segnib >= 0xE000)
+ {
+ phys_addr += ((u32_t)xpc) << 12;
+ }
+ else if (segnib >= ((segsize >> 4) & 0x0F))
+ {
+ phys_addr += ((u32_t)stackseg) << 12;
+ }
+ else if (segnib >= (segsize & 0x0F))
+ {
+ phys_addr += ((u32_t)dataseg) << 12;
+ }
+
+ return phys_addr;
+}
+
+void cl_r2k::store1( u16_t addr, t_mem val ) {
+ u32_t phys_addr;
+
+ if (mmu.io_flag == IOI) {
+ if ((mmu.mmidr ^ 0x80) & 0x80)
+ /* bit 7 = 0 --> use only 8-bits for internal I/O addresses */
+ addr = addr & 0x0ff;
+
+ if (addr == MMIDR) {
+ mmu.mmidr = val;
+ return;
+ }
+
+ if (addr == SADR) {
+ /* serial A (console when using the rabbit programming cable) */
+ putchar(val);
+ fflush(stdout);
+ }
+ return;
+ }
+ if (mmu.io_flag == IOE) {
+ /* I/O operation for external device (such as an ethernet controller) */
+ return;
+ }
+
+ phys_addr = mmu.logical_addr_to_phys( addr );
+ ram->write(phys_addr, val);
+}
+
+void cl_r2k::store2( u16_t addr, u16_t val ) {
+ u32_t phys_addr;
+
+ if (mmu.io_flag == IOI) {
+ /* I/O operation for on-chip device (serial ports, timers, etc) */
+ return;
+ }
+
+ if (mmu.io_flag == IOE) {
+ /* I/O operation for external device (such as an ethernet controller) */
+ return;
+ }
+
+ phys_addr = mmu.logical_addr_to_phys( addr );
+
+ ram->write(phys_addr, val & 0xff);
+ ram->write(phys_addr+1, (val >> 8) & 0xff);
+}
+
+u8_t cl_r2k::get1( u16_t addr ) {
+ u32_t phys_addr = mmu.logical_addr_to_phys( addr );
+
+ if (mmu.io_flag == IOI) {
+ /* stub for on-chip device I/O */
+ return 0;
+ }
+ if (mmu.io_flag == IOE) {
+ /* stub for external device I/O */
+ return 0;
+ }
+
+ return ram->read(phys_addr);
+}
+
+u16_t cl_r2k::get2( u16_t addr ) {
+ u32_t phys_addr = mmu.logical_addr_to_phys( addr );
+ u16_t l, h;
+
+ if (mmu.io_flag == IOI) {
+ /* stub for on-chip device I/O */
+ return 0;
+ }
+ if (mmu.io_flag == IOE) {
+ /* stub for external device I/O */
+ return 0;
+ }
+
+ l = ram->read(phys_addr );
+ h = ram->read(phys_addr+1);
+
+ return (h << 8) | l;
+}
+
+t_mem cl_r2k::fetch1( void ) {
+ return fetch( );
+}
+
+u16_t cl_r2k::fetch2( void ) {
+ u16_t c1, c2;
+
+ c1 = fetch( );
+ c2 = fetch( );
+ return (c2 << 8) | c1;
+}
+
+t_mem cl_r2k::fetch(void) {
+ /*
+ * Fetch without checking for breakpoint hit
+ *
+ * Used by bool cl_uc::fetch(t_mem *code) in sim.src/uc.cc
+ * which does check for a breakpoint hit
+ */
+
+ u32_t phys_addr = mmu.logical_addr_to_phys( PC );
+ ulong code;
+
+ if (!rom)
+ return(0);
+
+ code= rom->read(phys_addr);
+ PC = (PC + 1) & 0xffffUL;
+ vc.fetch++;
+ return(code);
+}
+
+/******** start rabbit 2000 specific codes *****************/
+int cl_r2k::inst_add_sp_d(t_mem code) {
+ u16_t d = fetch( );
+ /* sign-extend d from 8-bits to 16-bits */
+ d |= (d>>7)*0xFF00;
+ regs.SP = (regs.SP + d) & 0xffff;
+ return(resGO);
+}
+
+int cl_r2k::inst_altd(t_mem code) {
+ // stub
+ return(resGO);
+}
+
+int
+cl_r2k::inst_r2k_ld(t_mem code)
+{
+ /* 0xC4 ld hl,(sp+n)
+ * 0xD4 ld (sp+n),hl
+ * 0xE4 ld hl,(ix+d)
+ * DD E4 = ld hl,(hl+d) [note: (hl+d) breaks the normal prefix pattern]
+ * FD E4 = ld hl,(iy+d)
+ * 0xF4 ld (ix+d),hl
+ * DD F4 = ld (hl+d),hl
+ * FD F4 = ld (iy+d),hl
+ */
+ switch(code) {
+ case 0xC4: regs.HL = get2( add_u16_disp(regs.SP, fetch()) ); vc.rd+= 2; break;
+ case 0xD4: store2( add_u16_disp(regs.SP, fetch()), regs.HL ); vc.wr+= 2; break;
+ case 0xE4: regs.HL = get2( add_u16_disp(regs.IX, fetch()) ); vc.rd+= 2; break;
+ case 0xF4: store2( add_u16_disp(regs.IX, fetch()), regs.HL ); vc.wr+= 2; break;
+ default:
+ return(resINV_INST);
+ }
+
+ return(resGO);
+}
+
+int cl_r2k::inst_r2k_ex (t_mem code) {
+ u16_t tempw;
+
+ switch(code) {
+ case 0xE3:
+ // EX DE', HL on rabbit processors
+ tempw = regs.aDE;
+ regs.aDE = regs.HL;
+ regs.HL = tempw;
+ return(resGO);
+
+ default:
+ return(resINV_INST);
+ }
+}
+
+int cl_r2k::inst_ljp(t_mem code) {
+ u16_t mn;
+
+ mn = fetch2(); /* don't clobber PC before the fetch for xmem page */
+ mmu.xpc = fetch1();
+ PC = mn;
+
+ return(resGO);
+}
+
+int cl_r2k::inst_lcall(t_mem code) {
+ u16_t mn;
+
+ push1(mmu.xpc);
+ push2(PC+2);
+ vc.wr+= 2;
+
+ mn = fetch2(); /* don't clobber PC before the fetch for xmem page */
+ mmu.xpc = fetch1();
+ PC = mn;
+
+ return(resGO);
+}
+
+int cl_r2k::inst_bool(t_mem code) {
+ regs.raf.F &= ~BIT_ALL;
+ if (regs.HL)
+ regs.HL = 1;
+ else
+ regs.raf.F |= BIT_Z;
+ return(resGO);
+}
+
+int cl_r2k::inst_r2k_and(t_mem code) { // AND HL,DE
+ regs.HL &= regs.DE;
+
+ regs.raf.F &= ~BIT_ALL;
+ if (regs.DE & 0x8000)
+ regs.raf.F |= BIT_S;
+ if (regs.DE == 0)
+ regs.raf.F |= BIT_Z;
+ if (word_parity(regs.DE))
+ regs.raf.F |= BIT_P;
+ return(resGO);
+}
+
+int cl_r2k::inst_r2k_or (t_mem code) { // OR HL,DE
+ regs.HL |= regs.DE;
+
+ regs.raf.F &= ~BIT_ALL;
+ if (regs.DE & 0x8000)
+ regs.raf.F |= BIT_S;
+ if (regs.DE == 0)
+ regs.raf.F |= BIT_Z;
+ if (word_parity(regs.DE))
+ regs.raf.F |= BIT_P;
+ return(resGO);
+}
+
+int cl_r2k::inst_mul(t_mem code) {
+ long m;
+ long m1 = (long)(regs.BC & 0x7fff);
+ long m2 = (long)(regs.DE & 0x7fff);
+ if (regs.BC & 0x8000)
+ m1 -= (1 << 15);
+ if (regs.DE & 0x8000)
+ m2 -= (1 << 15);
+ m = m1 * m2;
+ regs.BC = ((unsigned long)(m) & 0xffff);
+ regs.HL = ((unsigned long)(m) >> 16) & 0xffff;
+ return(resGO);
+}
+
+int cl_r2k::inst_rl_de(t_mem code) {
+ unsigned int oldcarry = (regs.raf.F & BIT_C);
+
+ regs.raf.F &= ~BIT_ALL;
+ regs.raf.F |= (((regs.DE >> 15) & 1U) << BITPOS_C);
+ regs.DE = (regs.DE << 1) | (oldcarry >> BITPOS_C);
+
+ if (regs.DE & 0x8000)
+ regs.raf.F |= BIT_S;
+ if (regs.DE == 0)
+ regs.raf.F |= BIT_Z;
+ if (word_parity(regs.DE))
+ regs.raf.F |= BIT_P;
+ return(resGO);
+}
+
+int cl_r2k::inst_rr_de(t_mem code) {
+ unsigned int oldcarry = (regs.raf.F & BIT_C);
+
+ regs.raf.F &= ~BIT_ALL;
+ regs.raf.F |= ((regs.DE & 1) << BITPOS_C);
+ regs.DE = (regs.DE >> 1) | (oldcarry << (15 - BITPOS_C));
+
+ if (regs.DE & 0x8000)
+ regs.raf.F |= BIT_S;
+ if (regs.DE == 0)
+ regs.raf.F |= BIT_Z;
+ if (word_parity(regs.DE))
+ regs.raf.F |= BIT_P;
+ return(resGO);
+}
+
+int cl_r2k::inst_rr_hl(t_mem code) // RR HL
+{
+ unsigned int oldcarry = (regs.raf.F & BIT_C);
+
+ regs.raf.F &= ~BIT_ALL;
+ regs.raf.F |= ((regs.HL & 1) << BITPOS_C);
+ regs.HL = (regs.HL >> 1) | (oldcarry << (15 - BITPOS_C));
+
+ if (regs.HL & 0x8000)
+ regs.raf.F |= BIT_S;
+ if (regs.HL == 0)
+ regs.raf.F |= BIT_Z;
+ if (word_parity(regs.HL))
+ regs.raf.F |= BIT_P;
+ return(resGO);
+}
+
+
+int
+cl_r2k::inst_rst(t_mem code)
+{
+ switch(code) {
+ case 0xC7: // RST 0
+ push2(PC+2);
+ PC = 0x0;
+ vc.wr+= 2;
+ break;
+ case 0xCF: // RST 8
+ return(resINV_INST);
+
+ case 0xD7: // RST 10H
+ push2(PC+2);
+ PC = 0x10;
+ vc.wr+= 2;
+ break;
+ case 0xDF: // RST 18H
+ push2(PC+2);
+ PC = 0x18;
+ vc.wr+= 2;
+ break;
+ case 0xE7: // RST 20H
+ push2(PC+2);
+ PC = 0x20;
+ vc.wr+= 2;
+ break;
+ case 0xEF: // RST 28H
+ //PC = 0x28;
+ switch (regs.raf.A) {
+ case 0:
+ return(resBREAKPOINT);
+// ::exit(0);
+ break;
+
+ case 1:
+ //printf("PUTCHAR-----> %xH\n", regs.hl.l);
+ putchar(regs.hl.l);
+ fflush(stdout);
+ break;
+ }
+ break;
+ case 0xF7: // RST 30H
+ return(resINV_INST); // opcode is used for MUL on rabbit 2000+
+ break;
+ case 0xFF: // RST 38H
+ push2(PC+2);
+ PC = 0x38;
+ vc.wr+= 2;
+ break;
+ default:
+ return(resINV_INST);
+ break;
+ }
+ return(resGO);
+}
+
+int cl_r2k::inst_xd(t_mem prefix)
+{
+ u16_t *regs_IX_OR_IY = (prefix==0xdd)?(®s.IX):(®s.IY);
+ t_mem code;
+
+ if (fetch(&code))
+ return(resBREAKPOINT);
+
+ switch (code) {
+
+ // 0x06 LD A,(IX+A) is r4k+ instruction
+ case 0x21: // LD IX,nnnn
+ case 0x22: // LD (nnnn),IX
+
+ case 0x2A: // LD IX,(nnnn)
+ case 0x2E: // LD LX,nn
+ case 0x36: // LD (IX+dd),nn
+ case 0x46: // LD B,(IX+dd)
+ case 0x4E: // LD C,(IX+dd)
+ case 0x56: // LD D,(IX+dd)
+ case 0x5E: // LD E,(IX+dd)
+ case 0x66: // LD H,(IX+dd)
+ case 0x6E: // LD L,(IX+dd)
+
+ case 0x70: // LD (IX+dd),B
+ case 0x71: // LD (IX+dd),C
+ case 0x72: // LD (IX+dd),D
+ case 0x73: // LD (IX+dd),E
+ case 0x74: // LD (IX+dd),H
+ case 0x75: // LD (IX+dd),L
+ case 0x77: // LD (IX+dd),A
+ case 0x7E: // LD A,(IX+dd)
+ case 0xF9: // LD SP,IX
+ if (prefix == 0xdd)
+ return(inst_dd_ld(code));
+ else
+ return(inst_fd_ld(code));
+
+ case 0x7C: // LD HL,IX
+ regs.HL = *regs_IX_OR_IY; // LD HL, IX|IY for rabbit processors
+ return(resGO);
+ case 0x7D: // LD IX,HL
+ *regs_IX_OR_IY = regs.HL; // LD IX|IY,HL for rabbit processors
+ return(resGO);
+
+ case 0x23: // INC IX
+ case 0x34: // INC (IX+dd)
+ if (prefix == 0xdd)
+ return(inst_dd_inc(code));
+ else
+ return(inst_fd_inc(code));
+
+ case 0x09: // ADD IX,BC
+ case 0x19: // ADD IX,DE
+ case 0x29: // ADD IX,IX
+ case 0x39: // ADD IX,SP
+ case 0x86: // ADD A,(IX)
+ if (prefix == 0xdd)
+ return(inst_dd_add(code));
+ else
+ return(inst_fd_add(code));
+
+ case 0x2B: // DEC IX
+ case 0x35: // DEC (IX+dd)
+ if (prefix == 0xdd)
+ return(inst_dd_dec(code));
+ else
+ return(inst_fd_dec(code));
+
+ // 0x4C TEST IX is r4k+
+
+ case 0x8E: // ADC A,(IX)
+ case 0x96: // SUB (IX+dd)
+ case 0x9E: // SBC A,(IX+dd)
+ case 0xA6: // AND (IX+dd)
+ case 0xAE: // XOR (IX+dd)
+ case 0xB6: // OR (IX+dd)
+ case 0xBE: // CP (IX+dd)
+ if (prefix == 0xdd)
+ return(inst_dd_misc(code));
+ else
+ return(inst_fd_misc(code));
+
+ case 0xC4: // LD IX,(SP+n)
+ *regs_IX_OR_IY = get2( add_u16_disp(regs.SP, fetch()) );
+ vc.rd+= 2;
+ return(resGO);
+
+ case 0xCB: // escape, IX prefix to CB commands
+ // fixme: limit the opcodes passed through to those officially
+ // documented as present on the rabbit processors
+ if (prefix == 0xdd)
+ return(inst_ddcb()); /* see inst_ddcb.cc */
+ else
+ return(inst_fdcb()); /* see inst_fdcb.cc */
+
+ case 0xCC: // BOOL IX|IY
+ if (*regs_IX_OR_IY)
+ *regs_IX_OR_IY = 1;
+
+ // update flags
+ regs.raf.F &= ~BIT_ALL;
+ // bit 15 will never be set, so S<=0
+ if (*regs_IX_OR_IY == 0)
+ regs.raf.F |= BIT_Z;
+ // L/V and C are always cleared
+ return(resGO);
+
+ case 0xD4: // LD (SP+n),IX|IY
+ store2( add_u16_disp(regs.SP, fetch()), *regs_IX_OR_IY );
+ vc.wr+= 2;
+ return(resGO);
+
+ case 0xE1: // POP IX
+ *regs_IX_OR_IY = get2(regs.SP);
+ regs.SP+=2;
+ vc.rd+= 2;
+ return(resGO);
+
+ case 0xE3: // EX (SP),IX
+ {
+ u16_t tempw;
+
+ tempw = *regs_IX_OR_IY;
+ *regs_IX_OR_IY = get2(regs.SP);
+ store2(regs.SP, tempw);
+ vc.rd+= 2;
+ vc.wr+= 2;
+ }
+ return(resGO);
+
+ case 0xE4:
+ if (prefix == 0xDD)
+ regs.HL = get2( add_u16_disp(regs.HL, fetch()) );
+ else
+ regs.HL = get2( add_u16_disp(regs.IY, fetch()) );
+ vc.rd+= 2;
+ return(resGO);
+
+ case 0xE5: // PUSH IX
+ push2(*regs_IX_OR_IY);
+ vc.wr+= 2;
+ return(resGO);
+
+ case 0xE9: // JP (IX)
+ PC = *regs_IX_OR_IY;
+ return(resGO);
+
+ case 0xEA:
+ push2(PC);
+ PC = *regs_IX_OR_IY;
+ vc.wr+= 2;
+ return(resGO);
+
+ case 0xDC: // AND IX|IY,DE for rabbit processors
+ case 0xEC: // OR IX|IY,DE for rabbit processors
+ if (code == 0xDC)
+ *regs_IX_OR_IY &= regs.DE;
+ else
+ *regs_IX_OR_IY |= regs.DE;
+
+ // update flags
+ regs.raf.F &= ~BIT_ALL;
+ if (*regs_IX_OR_IY & 0x8000)
+ regs.raf.F |= BIT_S;
+ if (regs_IX_OR_IY == 0)
+ regs.raf.F |= BIT_Z;
+ if (word_parity(*regs_IX_OR_IY))
+ regs.raf.F |= BIT_P;
+ return(resGO);
+
+ case 0xF4: // LD (HL|IY+d),HL
+ if (prefix == 0xDD)
+ store2( add_u16_disp(regs.HL, fetch()), regs.HL );
+ else
+ store2( add_u16_disp(regs.IY, fetch()), regs.HL );
+ vc.wr+= 2;
+ return(resGO);
+
+ case 0xFC: // RR IX|IY
+ {
+ u16_t tmp = (regs.raf.F & BIT_C) << (15 - BITPOS_C);
+ tmp |= (*regs_IX_OR_IY >> 1);
+
+ regs.raf.F = (regs.raf.F & ~BIT_C) | ((*regs_IX_OR_IY & 1) << BITPOS_C);
+
+ if (*regs_IX_OR_IY & 0x8000)
+ regs.raf.F |= BIT_S;
+ if (*regs_IX_OR_IY == 0)
+ regs.raf.F |= BIT_Z;
+ if (word_parity(*regs_IX_OR_IY))
+ regs.raf.F |= BIT_P;
+ return(resGO);
+ }
+
+ default:
+ return(resINV_INST);
+ }
+
+ return(resINV_INST);
+}
diff --git a/sim/ucsim/z80.src/inst_xd.cc b/sim/ucsim/z80.src/inst_xd.cc new file mode 100644 index 0000000..666795a --- /dev/null +++ b/sim/ucsim/z80.src/inst_xd.cc @@ -0,0 +1,567 @@ +/* + * Simulator of microcontrollers (inst_xd.cc) + * dd or fd escaped multi-byte opcodes. + * + * This module gets pulled in and pre-processed to create + * two modules. DD prefixed opcodes reference + * IX register, while FD prefixes reference IY register. + * See inst_ddcb.cc and inst_fdcb.cc + * + * Copyright (C) 1999,2002 Drotos Daniel, Talker Bt. + * some z80 coding from Karl Bongers karl@turbobit.com + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +int +cl_z80::inst_Xd_ld(t_mem code) +{ + unsigned short tw; + + switch (code) { + case 0x21: // LD IX,nnnn + regs_IX_OR_IY = fetch2(); + return(resGO); + case 0x22: // LD (nnnn),IX + tw = fetch2(); + store2(tw, regs_IX_OR_IY); + vc.wr+= 2; + return(resGO); + case 0x26: // LD HX,nn + regs_iX_h = fetch1(); + return(resGO); + case 0x2A: // LD IX,(nnnn) + tw = fetch2(); + regs_IX_OR_IY = get2(tw); + vc.rd+= 2; + return(resGO); + case 0x2E: // LD LX,nn + regs_iX_l = fetch1(); + return(resGO); + case 0x36: // LD (IX+dd),nn + tw = add_u16_disp(regs_IX_OR_IY, fetch()); + store1(tw, fetch()); + vc.wr++; + return(resGO); + case 0x44: // LD B,HX + regs.bc.h = regs_iX_h; + return(resGO); + case 0x45: // LD B,LX + regs.bc.h = regs_iX_l; + return(resGO); + case 0x46: // LD B,(IX+dd) + regs.bc.h = get1(add_u16_disp(regs_IX_OR_IY,fetch())); + vc.rd++; + return(resGO); + case 0x4C: // LD C,HX + regs.bc.l = regs_iX_h; + return(resGO); + case 0x4D: // LD C,LX + regs.bc.l = regs_iX_l; + return(resGO); + case 0x4E: // LD C,(IX+dd) + regs.bc.l = get1(add_u16_disp(regs_IX_OR_IY,fetch())); + vc.rd++; + return(resGO); + case 0x54: // LD D,HX + regs.de.h = regs_iX_h; + return(resGO); + case 0x55: // LD D,LX + regs.de.h = regs_iX_l; + return(resGO); + case 0x56: // LD D,(IX+dd) + regs.de.h = get1(add_u16_disp(regs_IX_OR_IY,fetch())); + vc.rd++; + return(resGO); + case 0x5C: // LD E,H + regs.de.l = regs.hl.h; + return(resGO); + case 0x5D: // LD E,L + regs.de.l = regs.hl.l; + return(resGO); + case 0x5E: // LD E,(IX+dd) + regs.de.l = get1(add_u16_disp(regs_IX_OR_IY,fetch())); + vc.rd++; + return(resGO); + case 0x60: // LD HX,B + regs_iX_h = regs.bc.h; + return(resGO); + case 0x61: // LD HX,C + regs_iX_h = regs.bc.l; + return(resGO); + case 0x62: // LD HX,D + regs_iX_h = regs.de.h; + return(resGO); + case 0x63: // LD HX,E + regs_iX_h = regs.de.l; + return(resGO); + case 0x64: // LD HX,HX + return(resGO); + case 0x65: // LD HX,LX + regs_iX_h = regs_iX_l; + return(resGO); + case 0x66: // LD H,(IX+dd) + regs.hl.h = get1(add_u16_disp(regs_IX_OR_IY,fetch())); + vc.rd++; + return(resGO); + case 0x67: // LD HX,A + regs_iX_h = regs.raf.A; + return(resGO); + case 0x68: // LD LX,B + regs_iX_l = regs.bc.h; + return(resGO); + case 0x69: // LD LX,C + regs_iX_l = regs.bc.l; + return(resGO); + case 0x6A: // LD LX,D + regs_iX_l = regs.de.h; + return(resGO); + case 0x6B: // LD LX,E + regs_iX_l = regs.de.l; + return(resGO); + case 0x6C: // LD LX,HX + regs_iX_l = regs.hl.h; + return(resGO); + case 0x6D: // LD LX,LX + return(resGO); + case 0x6E: // LD L,(IX+dd) + regs.hl.l = get1(add_u16_disp(regs_IX_OR_IY,fetch())); + vc.rd++; + return(resGO); + case 0x6F: // LD LX,A + regs_iX_l = regs.raf.A; + return(resGO); + case 0x70: // LD (IX+dd),B + store1(add_u16_disp(regs_IX_OR_IY,fetch()), regs.bc.h); + vc.wr++; + return(resGO); + case 0x71: // LD (IX+dd),C + store1(add_u16_disp(regs_IX_OR_IY,fetch()), regs.bc.l); + vc.wr++; + return(resGO); + case 0x72: // LD (IX+dd),D + store1(add_u16_disp(regs_IX_OR_IY,fetch()), regs.de.h); + vc.wr++; + return(resGO); + case 0x73: // LD (IX+dd),E + store1(add_u16_disp(regs_IX_OR_IY,fetch()), regs.de.l); + vc.wr++; + return(resGO); + case 0x74: // LD (IX+dd),H + store1(add_u16_disp(regs_IX_OR_IY,fetch()), regs.hl.h); + vc.wr++; + return(resGO); + case 0x75: // LD (IX+dd),L + store1(add_u16_disp(regs_IX_OR_IY,fetch()), regs.hl.l); + vc.wr++; + return(resGO); + case 0x77: // LD (IX+dd),A + store1(add_u16_disp(regs_IX_OR_IY,fetch()), regs.raf.A); + vc.wr++; + return(resGO); + case 0x7C: // LD A,HX + regs.raf.A = regs_iX_h; + return(resGO); + case 0x7D: // LD A,LX + regs.raf.A = regs_iX_l; + return(resGO); + case 0x7E: // LD A,(IX+dd) + regs.raf.A = get1(add_u16_disp(regs_IX_OR_IY,fetch())); + vc.rd++; + return(resGO); + case 0xF9: // LD SP,IX + regs.SP = regs_IX_OR_IY; + return(resGO); + } + return(resINV_INST); +} + +int +cl_z80::inst_Xd_add(t_mem code) +{ + switch (code) { + case 0x09: // ADD IX,BC + add_IX_Word(regs.BC); + return(resGO); + case 0x19: // ADD IX,DE + add_IX_Word(regs.DE); + return(resGO); + case 0x29: // ADD IX,IX + add_IX_Word(regs_IX_OR_IY); + return(resGO); + case 0x39: // ADD IX,SP + add_IX_Word(regs.SP); + return(resGO); + case 0x84: // ADD A,HX + add_A_bytereg(regs_iX_h); + return(resGO); + case 0x85: // ADD A,LX + add_A_bytereg(regs_iX_l); + return(resGO); + case 0x86: // ADD A,(IX+dd) + { unsigned char ourtmp; + t_addr addr; + addr = add_u16_disp(regs_IX_OR_IY, fetch()); + ourtmp = get1(addr); + add_A_bytereg(ourtmp); + vc.rd++; + } + return(resGO); + } + return(resINV_INST); +} + +int +cl_z80::inst_Xd_push(t_mem code) +{ + switch (code) { + case 0xe5: // PUSH IX + push2(regs_IX_OR_IY); + vc.wr+= 2; + return(resGO); + } + return(resINV_INST); +} + +int +cl_z80::inst_Xd_inc(t_mem code) +{ + switch(code) { + case 0x23: // INC IX + ++regs_IX_OR_IY; + break; + case 0x24: // INC HX + inc(regs_iX_h); + break; + case 0x2C: // INC LX + inc(regs_iX_l); + break; + case 0x34: // INC (IX+dd) + { + t_addr addr; + unsigned char tmp; + addr = add_u16_disp(regs_IX_OR_IY,fetch()); + tmp = get1(addr); + inc(tmp); + store1(addr, tmp); + vc.rd++; + vc.wr++; + } + break; + default: + return(resINV_INST); + break; + } + return(resGO); +} + +int +cl_z80::inst_Xd_dec(t_mem code) +{ + switch(code) { + case 0x25: // DEC HX + dec(regs_iX_h); + break; + case 0x2B: // DEC IX + --regs_IX_OR_IY; + break; + case 0x2D: // DEC LX + dec(regs_iX_l); + break; + case 0x35: // DEC (IX+dd) + { + t_addr addr; + unsigned char tmp; + addr = add_u16_disp(regs_IX_OR_IY,fetch()); + tmp = get1(addr); + dec(tmp); + store1(addr, tmp); + vc.rd++; + vc.wr++; + } + break; + default: + return(resINV_INST); + break; + } + return(resGO); +} + + +/* need ADC, SUB, SBC, AND, XOR, OR, CP */ +int +cl_z80::inst_Xd_misc(t_mem code) +{ + switch(code) { + case 0x8C: // ADC A,HX + adc_A_bytereg(regs_iX_h); + return(resGO); + case 0x8D: // ADC A,LX + adc_A_bytereg(regs_iX_l); + return(resGO); + case 0x8E: // ADC A,(IX+dd) + { unsigned char utmp; + t_addr addr; + addr = add_u16_disp(regs_IX_OR_IY, fetch()); + utmp = get1(addr); + adc_A_bytereg(utmp); + vc.rd++; + } + return(resGO); + + case 0x94: // SUB HX + sub_A_bytereg(regs_iX_h); + return(resGO); + case 0x95: // SUB LX + sub_A_bytereg(regs_iX_l); + return(resGO); + case 0x96: // SUB (IX+dd) + { unsigned char tmp1; + tmp1 = get1(add_u16_disp(regs_IX_OR_IY, fetch())); + sub_A_bytereg(tmp1); + vc.rd++; + } + return(resGO); + + case 0x9C: // SBC A,HX + sbc_A_bytereg(regs_iX_h); + return(resGO); + case 0x9D: // SBC A,LX + sbc_A_bytereg(regs_iX_l); + return(resGO); + case 0x9E: // SBC A,(IX+dd) + { unsigned char utmp; + utmp = get1(add_u16_disp(regs_IX_OR_IY, fetch())); + sbc_A_bytereg(utmp); + vc.rd++; + } + return(resGO); + + case 0xA4: // AND HX + and_A_bytereg(regs_iX_h); + return(resGO); + case 0xA5: // AND LX + and_A_bytereg(regs_iX_l); + return(resGO); + case 0xA6: // AND (IX+dd) + { unsigned char utmp; + utmp = get1(add_u16_disp(regs_IX_OR_IY, fetch())); + and_A_bytereg(utmp); + vc.rd++; + } + return(resGO); + + case 0xAC: // XOR HX + xor_A_bytereg(regs_iX_h); + return(resGO); + case 0xAD: // XOR LX + xor_A_bytereg(regs_iX_l); + return(resGO); + case 0xAE: // XOR (IX+dd) + { unsigned char utmp; + utmp = get1(add_u16_disp(regs_IX_OR_IY, fetch())); + xor_A_bytereg(utmp); + vc.rd++; + } + return(resGO); + + case 0xB4: // OR HX + or_A_bytereg(regs_iX_h); + return(resGO); + case 0xB5: // OR LX + or_A_bytereg(regs_iX_l); + return(resGO); + case 0xB6: // OR (IX+dd) + { unsigned char utmp; + utmp = get1(add_u16_disp(regs_IX_OR_IY, fetch())); + or_A_bytereg(utmp); + vc.rd++; + } + return(resGO); + + case 0xBC: // CP HX + cp_bytereg(regs_iX_h); + return(resGO); + case 0xBD: // CP LX + cp_bytereg(regs_iX_l); + return(resGO); + case 0xBE: // CP (IX+dd) + { unsigned char utmp; + utmp = get1(add_u16_disp(regs_IX_OR_IY, fetch())); + cp_bytereg(utmp); + vc.rd++; + } + return(resGO); + } + return(resINV_INST); +} + +int +cl_z80::inst_Xd(t_mem prefix) +{ + t_mem code; + int i; + + if (fetch(&code)) + return(resBREAKPOINT); + + switch (prefix) + { + case 0xdd: + if ((i= inst_dd_spec(code)) >= 0) + return i; + case 0xfd: + if ((i= inst_fd_spec(code)) >= 0) + return i; + } + + switch (code) + { + case 0x21: // LD IX,nnnn + case 0x22: // LD (nnnn),IX + case 0x26: // LD HX,nn + case 0x2A: // LD IX,(nnnn) + case 0x2E: // LD LX,nn + case 0x36: // LD (IX+dd),nn + case 0x44: // LD B,HX + case 0x45: // LD B,LX + case 0x46: // LD B,(IX+dd) + case 0x4C: // LD C,HX + case 0x4D: // LD C,LX + case 0x4E: // LD C,(IX+dd) + case 0x54: // LD D,HX + case 0x55: // LD D,LX + case 0x56: // LD D,(IX+dd) + case 0x5C: // LD E,H + case 0x5D: // LD E,L + case 0x5E: // LD E,(IX+dd) + case 0x60: // LD HX,B + case 0x61: // LD HX,C + case 0x62: // LD HX,D + case 0x63: // LD HX,E + case 0x64: // LD HX,HX + case 0x66: // LD H,(IX+dd) + case 0x67: // LD HX,A + case 0x68: // LD LX,B + case 0x69: // LD LX,C + case 0x6A: // LD LX,D + case 0x6B: // LD LX,E + case 0x6C: // LD LX,HX + case 0x6D: // LD LX,LX + case 0x6E: // LD L,(IX+dd) + case 0x6F: // LD LX,A + case 0x70: // LD (IX+dd),B + case 0x71: // LD (IX+dd),C + case 0x72: // LD (IX+dd),D + case 0x73: // LD (IX+dd),E + case 0x74: // LD (IX+dd),H + case 0x75: // LD (IX+dd),L + case 0x77: // LD (IX+dd),A + case 0x7C: // LD A,HX + case 0x7D: // LD A,LX + case 0x7E: // LD A,(IX+dd) + case 0xF9: // LD SP,IX + return(inst_Xd_ld(code)); + + case 0x23: // INC IX + case 0x24: // INC HX + case 0x2C: // INC LX + case 0x34: // INC (IX+dd) + return(inst_Xd_inc(code)); + + case 0x09: // ADD IX,BC + case 0x19: // ADD IX,DE + case 0x29: // ADD IX,IX + case 0x39: // ADD IX,SP + case 0x84: // ADD A,HX + case 0x85: // ADD A,LX + case 0x86: // ADD A,(IX) + return(inst_Xd_add(code)); + + case 0x25: // DEC HX + case 0x2B: // DEC IX + case 0x2D: // DEC LX + case 0x35: // DEC (IX+dd) + return(inst_Xd_dec(code)); + + case 0x8C: // ADC A,HX + case 0x8D: // ADC A,LX + case 0x8E: // ADC A,(IX) + case 0x94: // SUB HX + case 0x95: // SUB LX + case 0x96: // SUB (IX+dd) + case 0x9C: // SBC A,HX + case 0x9D: // SBC A,LX + case 0x9E: // SBC A,(IX+dd) + case 0xA4: // AND HX + case 0xA5: // AND LX + case 0xA6: // AND (IX+dd) + case 0xAC: // XOR HX + case 0xAD: // XOR LX + case 0xAE: // XOR (IX+dd) + case 0xB4: // OR HX + case 0xB5: // OR LX + case 0xB6: // OR (IX+dd) + case 0xBC: // CP HX + case 0xBD: // CP LX + case 0xBE: // CP (IX+dd) + return(inst_Xd_misc(code)); + break; + + case 0xCB: // escape, IX prefix to CB commands + return(inst_Xdcb()); /* see inst_ddcb.cc */ + break; + + case 0xE1: // POP IX + regs_IX_OR_IY = get2(regs.SP); + regs.SP+=2; + vc.rd+= 2; + return(resGO); + + case 0xE3: // EX (SP),IX + { + u16_t tempw; + + tempw = regs_IX_OR_IY; + regs_IX_OR_IY = get2(regs.SP); + store2(regs.SP, tempw); + vc.rd+= 2; + vc.wr+= 2; + } + return(resGO); + + case 0xE5: // PUSH IX + push2(regs_IX_OR_IY); + vc.wr+= 2; + return(resGO); + + case 0xE9: // JP (IX) + PC = regs_IX_OR_IY; + return(resGO); + + default: + return(resINV_INST); + } + return(resINV_INST); +} + +/* End of z80.src/inst_xd.cc */ diff --git a/sim/ucsim/z80.src/inst_xxcb.cc b/sim/ucsim/z80.src/inst_xxcb.cc new file mode 100644 index 0000000..944b544 --- /dev/null +++ b/sim/ucsim/z80.src/inst_xxcb.cc @@ -0,0 +1,722 @@ +/* + * Simulator of microcontrollers (inst_xxcb.cc) + * DD CB or FD CB escaped multi-byte opcodes for Z80. + * + * This module gets pulled in and pre-processed to create + * two modules. DD CB prefixed opcodes reference + * IX register, while FD CB prefixes reference IY register. + * See inst_ddcb.cc and inst_fdcb.cc + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +static unsigned char n_offset; + +int +cl_z80::inst_XXcb_rlc(t_mem code) +{ + unsigned char tmp; + unsigned short addr; + + addr = add_u16_disp(regs_IX_OR_IY, n_offset); + tmp = get1(addr); + rlc_byte(tmp); + vc.rd++; + + switch(code) { + case 0x00: // RLC B + regs.bc.h = tmp; + break; + case 0x01: // RLC C + regs.bc.l = tmp; + break; + case 0x02: // RLC D + regs.de.h = tmp; + break; + case 0x03: // RLC E + regs.de.l = tmp; + break; + case 0x04: // RLC H + regs.hl.h = tmp; + break; + case 0x05: // RLC L + regs.hl.l = tmp; + break; + case 0x06: // RLC (HL) + break; + case 0x07: // RLC A + regs.raf.A = tmp; + break; + default: + return(resINV_INST); + break; + } + store1(addr, tmp); + vc.wr++; + + return(resGO); +} + +int +cl_z80::inst_XXcb_rrc(t_mem code) +{ + unsigned char tmp; + unsigned short addr; + addr = add_u16_disp(regs_IX_OR_IY, n_offset); + tmp = get1(addr); + rrc_byte(tmp); + vc.rd++; + + switch(code) { + case 0x08: // RRC B + regs.bc.h = tmp; + break; + case 0x09: // RRC C + regs.bc.l = tmp; + break; + case 0x0A: // RRC D + regs.de.h = tmp; + break; + case 0x0B: // RRC E + regs.de.l = tmp; + break; + case 0x0C: // RRC H + regs.hl.h = tmp; + break; + case 0x0D: // RRC L + regs.hl.l = tmp; + break; + case 0x0E: // RRC (HL) + break; + case 0x0F: // RRC A + regs.raf.A = tmp; + break; + default: + return(resINV_INST); + break; + } + store1(addr, tmp); + vc.wr++; + + return(resGO); +} + +int +cl_z80::inst_XXcb_rl(t_mem code) +{ + unsigned char tmp; + unsigned short addr; + addr = add_u16_disp(regs_IX_OR_IY, n_offset); + tmp = get1(addr); + rl_byte(tmp); + vc.rd++; + + switch(code) { + case 0x10: // RL B + regs.bc.h = tmp; + break; + case 0x11: // RL C + regs.bc.l = tmp; + break; + case 0x12: // RL D + regs.de.h = tmp; + break; + case 0x13: // RL E + regs.de.l = tmp; + break; + case 0x14: // RL H + regs.hl.h = tmp; + break; + case 0x15: // RL L + regs.hl.l = tmp; + break; + case 0x16: // RL (HL) + break; + case 0x17: // RL A + regs.raf.A = tmp; + break; + default: + return(resINV_INST); + break; + } + store1(addr, tmp); + vc.wr++; + + return(resGO); +} + +int +cl_z80::inst_XXcb_rr(t_mem code) +{ + unsigned char tmp; + unsigned short addr; + addr = add_u16_disp(regs_IX_OR_IY, n_offset); + tmp = get1(addr); + rr_byte(tmp); + vc.rd++; + + switch(code) { + case 0x18: // RR B + regs.bc.h = tmp; + break; + case 0x19: // RR C + regs.bc.l = tmp; + break; + case 0x1A: // RR D + regs.de.h = tmp; + break; + case 0x1B: // RR E + regs.de.l = tmp; + break; + case 0x1C: // RR H + regs.hl.h = tmp; + break; + case 0x1D: // RR L + regs.hl.l = tmp; + break; + case 0x1E: // RR (HL) + break; + case 0x1F: // RR A + regs.raf.A = tmp; + break; + default: + return(resINV_INST); + break; + } + store1(addr, tmp); + vc.wr++; + + return(resGO); +} + +int +cl_z80::inst_XXcb_sla(t_mem code) +{ + unsigned char tmp; + unsigned short addr; + addr = add_u16_disp(regs_IX_OR_IY, n_offset); + tmp = get1(addr); + sla_byte(tmp); + vc.rd++; + + switch(code) { + case 0x20: // SLA B + regs.bc.h = tmp; + break; + case 0x21: // SLA C + regs.bc.l = tmp; + break; + case 0x22: // SLA D + regs.de.h = tmp; + break; + case 0x23: // SLA E + regs.de.l = tmp; + break; + case 0x24: // SLA H + regs.hl.h = tmp; + break; + case 0x25: // SLA L + regs.hl.l = tmp; + break; + case 0x26: // SLA (HL) + break; + case 0x27: // SLA A + regs.raf.A = tmp; + break; + default: + return(resINV_INST); + break; + } + store1(addr, tmp); + vc.wr++; + + return(resGO); +} + +int +cl_z80::inst_XXcb_sra(t_mem code) +{ + unsigned char tmp; + unsigned short addr; + addr = add_u16_disp(regs_IX_OR_IY, n_offset); + tmp = get1(addr); + sra_byte(tmp); + vc.rd++; + + switch(code) { + case 0x28: // SRA B + regs.bc.h = tmp; + break; + case 0x29: // SRA C + regs.bc.l = tmp; + break; + case 0x2A: // SRA D + regs.de.h = tmp; + break; + case 0x2B: // SRA E + regs.de.l = tmp; + break; + case 0x2C: // SRA H + regs.hl.h = tmp; + break; + case 0x2D: // SRA L + regs.hl.l = tmp; + break; + case 0x2E: // SRA (HL) + break; + case 0x2F: // SRA A + regs.raf.A = tmp; + break; + default: + return(resINV_INST); + break; + } + store1(addr, tmp); + vc.wr++; + + return(resGO); +} + +int +cl_z80::inst_XXcb_slia(t_mem code) +{ + unsigned char tmp; + unsigned short addr; + addr = add_u16_disp(regs_IX_OR_IY, n_offset); + tmp = get1(addr); + slia_byte(tmp); + vc.rd++; + + switch(code) { + case 0x30: // SLIA B (Shift Left Inverted Arithmetic) + regs.bc.h = tmp; + break; + case 0x31: // SLIA C like SLA, but shifts in a 1 bit + regs.bc.l = tmp; + break; + case 0x32: // SLIA D + regs.de.h = tmp; + break; + case 0x33: // SLIA E + regs.de.l = tmp; + break; + case 0x34: // SLIA H + regs.hl.h = tmp; + break; + case 0x35: // SLIA L + regs.hl.l = tmp; + break; + case 0x36: // SLIA (HL) + break; + case 0x37: // SLIA A + regs.raf.A = tmp; + break; + default: + return(resINV_INST); + break; + } + store1(addr, tmp); + vc.wr++; + + return(resGO); +} + +int +cl_z80::inst_XXcb_srl(t_mem code) +{ + unsigned char tmp; + unsigned short addr; + addr = add_u16_disp(regs_IX_OR_IY, n_offset); + tmp = get1(addr); + srl_byte(tmp); + vc.rd++; + + switch(code) { + case 0x38: // SRL B + regs.bc.h = tmp; + break; + case 0x39: // SRL C + regs.bc.l = tmp; + break; + case 0x3A: // SRL D + regs.de.h = tmp; + break; + case 0x3B: // SRL E + regs.de.l = tmp; + break; + case 0x3C: // SRL H + regs.hl.h = tmp; + break; + case 0x3D: // SRL L + regs.hl.l = tmp; + break; + case 0x3E: // SRL (HL) + break; + case 0x3F: // SRL A + regs.raf.A = tmp; + break; + default: + return(resINV_INST); + break; + } + store1(addr, tmp); + vc.wr++; + + return(resGO); +} + + +int +cl_z80::inst_XXcb_bit(t_mem code) +{ + unsigned char tmp; + unsigned short addr; + +#define bit_bitnum ((code >> 3) & 7) + + addr = add_u16_disp(regs_IX_OR_IY, n_offset); + tmp = get1(addr); + bit_byte(tmp, bit_bitnum); + vc.rd++; + + store1(addr, tmp); + vc.wr++; + + return(resGO); +} + +int +cl_z80::inst_XXcb_res(t_mem code) +{ + unsigned char tmp; + unsigned short addr; + +#define bit_bitnum ((code >> 3) & 7) + + addr = add_u16_disp(regs_IX_OR_IY, n_offset); + tmp = get1(addr); + tmp &= ~(1 << bit_bitnum); + vc.rd++; + + switch(code & 0x7) { + case 0x0: // RES x,B + regs.bc.h = tmp; break; + case 0x1: // RES x,C + regs.bc.l = tmp; break; + case 0x2: // RES x,D + regs.de.h = tmp; break; + case 0x3: // RES x,E + regs.de.l = tmp; break; + case 0x4: // RES x,H + regs.hl.h = tmp; break; + case 0x5: // RES x,L + regs.hl.l = tmp; break; + case 0x6: // RES x,(HL) + break; + case 0x7: // RES x,A + regs.raf.A = tmp; break; + default: + return(resINV_INST); + } + store1(addr, tmp); + vc.wr++; + + return(resGO); +} + +int +cl_z80::inst_XXcb_set(t_mem code) +{ + unsigned char tmp; + unsigned short addr; + +#define bit_bitnum ((code >> 3) & 7) + + addr = add_u16_disp(regs_IX_OR_IY, n_offset); + tmp = get1(addr); + tmp |= (1 << bit_bitnum); + vc.rd++; + + switch(code & 0x7) { + case 0x0: // SET x,B + regs.bc.h = tmp; break; + case 0x1: // SET x,C + regs.bc.l = tmp; break; + case 0x2: // SET x,D + regs.de.h = tmp; break; + case 0x3: // SET x,E + regs.de.l = tmp; break; + case 0x4: // SET x,H + regs.hl.h = tmp; break; + case 0x5: // SET x,L + regs.hl.h = tmp; break; + case 0x6: // SET x,(HL) + break; + case 0x7: // SET x,A + regs.raf.A = tmp; break; + default: + return(resINV_INST); + } + store1(addr, tmp); + vc.wr++; + + return(resGO); +} + +/******** start CB codes *****************/ +int +cl_z80::inst_XXcb(void) +{ + t_mem code; + + // all DD CB escaped opcodes have a 3rd byte which is a displacement, + // 4th byte is opcode extension. + n_offset = fetch(); + + if (fetch(&code)) + return(resBREAKPOINT); + tick(1); + switch (code) + { + case 0x00: // RLC B + case 0x01: // RLC C + case 0x02: // RLC D + case 0x03: // RLC E + case 0x04: // RLC H + case 0x05: // RLC L + case 0x06: // RLC (HL) + case 0x07: // RLC A + return (inst_XXcb_rlc(code)); + case 0x08: // RRC B + case 0x09: // RRC C + case 0x0A: // RRC D + case 0x0B: // RRC E + case 0x0C: // RRC H + case 0x0D: // RRC L + case 0x0E: // RRC (HL) + case 0x0F: // RRC A + return (inst_XXcb_rrc(code)); + case 0x10: // RL B + case 0x11: // RL C + case 0x12: // RL D + case 0x13: // RL E + case 0x14: // RL H + case 0x15: // RL L + case 0x16: // RL (HL) + case 0x17: // RL A + return (inst_XXcb_rl(code)); + case 0x18: // RR B + case 0x19: // RR C + case 0x1A: // RR D + case 0x1B: // RR E + case 0x1C: // RR H + case 0x1D: // RR L + case 0x1E: // RR (HL) + case 0x1F: // RR A + return (inst_XXcb_rr(code)); + case 0x20: // SLA B + case 0x21: // SLA C + case 0x22: // SLA D + case 0x23: // SLA E + case 0x24: // SLA H + case 0x25: // SLA L + case 0x26: // SLA (HL) + case 0x27: // SLA A + return (inst_XXcb_sla(code)); + case 0x28: // SRA B + case 0x29: // SRA C + case 0x2A: // SRA D + case 0x2B: // SRA E + case 0x2C: // SRA H + case 0x2D: // SRA L + case 0x2E: // SRA (HL) + case 0x2F: // SRA A + return (inst_XXcb_sra(code)); + case 0x30: // SLIA B (Shift Left Inverted Arithmetic) + case 0x31: // SLIA C like SLA, but shifts in a 1 bit + case 0x32: // SLIA D + case 0x33: // SLIA E + case 0x34: // SLIA H + case 0x35: // SLIA L + case 0x36: // SLIA (HL) + case 0x37: // SLIA A + return (inst_XXcb_slia(code)); + case 0x38: // SRL B + case 0x39: // SRL C + case 0x3A: // SRL D + case 0x3B: // SRL E + case 0x3C: // SRL H + case 0x3D: // SRL L + case 0x3E: // SRL (HL) + case 0x3F: // SRL A + return (inst_XXcb_srl(code)); + case 0x46: // BIT 0,(HL) + case 0x4E: // BIT 1,(HL) + case 0x56: // BIT 2,(HL) + case 0x5E: // BIT 3,(HL) + case 0x66: // BIT 4,(HL) + case 0x6E: // BIT 5,(HL) + case 0x76: // BIT 6,(HL) + case 0x7E: // BIT 7,(HL) + return (inst_XXcb_bit(code)); + case 0x80: // RES 0,B + case 0x81: // RES 0,C + case 0x82: // RES 0,D + case 0x83: // RES 0,E + case 0x84: // RES 0,H + case 0x85: // RES 0,L + case 0x86: // RES 0,(HL) + case 0x87: // RES 0,A + case 0x88: // RES 1,B + case 0x89: // RES 1,C + case 0x8A: // RES 1,D + case 0x8B: // RES 1,E + case 0x8C: // RES 1,H + case 0x8D: // RES 1,L + case 0x8E: // RES 1,(HL) + case 0x8F: // RES 1,A + case 0x90: // RES 2,B + case 0x91: // RES 2,C + case 0x92: // RES 2,D + case 0x93: // RES 2,E + case 0x94: // RES 2,H + case 0x95: // RES 2,L + case 0x96: // RES 2,(HL) + case 0x97: // RES 2,A + case 0x98: // RES 3,B + case 0x99: // RES 3,C + case 0x9A: // RES 3,D + case 0x9B: // RES 3,E + case 0x9C: // RES 3,H + case 0x9D: // RES 3,L + case 0x9E: // RES 3,(HL) + case 0x9F: // RES 3,A + case 0xA0: // RES 4,B + case 0xA1: // RES 4,C + case 0xA2: // RES 4,D + case 0xA3: // RES 4,E + case 0xA4: // RES 4,H + case 0xA5: // RES 4,L + case 0xA6: // RES 4,(HL) + case 0xA7: // RES 4,A + case 0xA8: // RES 5,B + case 0xA9: // RES 5,C + case 0xAA: // RES 5,D + case 0xAB: // RES 5,E + case 0xAC: // RES 5,H + case 0xAD: // RES 5,L + case 0xAE: // RES 5,(HL) + case 0xAF: // RES 5,A + case 0xB0: // RES 6,B + case 0xB1: // RES 6,C + case 0xB2: // RES 6,D + case 0xB3: // RES 6,E + case 0xB4: // RES 6,H + case 0xB5: // RES 6,L + case 0xB6: // RES 6,(HL) + case 0xB7: // RES 6,A + case 0xB8: // RES 7,B + case 0xB9: // RES 7,C + case 0xBA: // RES 7,D + case 0xBB: // RES 7,E + case 0xBC: // RES 7,H + case 0xBD: // RES 7,L + case 0xBE: // RES 7,(HL) + case 0xBF: // RES 7,A + return (inst_XXcb_res(code)); + case 0xC0: // SET 0,B + case 0xC1: // SET 0,C + case 0xC2: // SET 0,D + case 0xC3: // SET 0,E + case 0xC4: // SET 0,H + case 0xC5: // SET 0,L + case 0xC6: // SET 0,(HL) + case 0xC7: // SET 0,A + case 0xC8: // SET 1,B + case 0xC9: // SET 1,C + case 0xCA: // SET 1,D + case 0xCB: // SET 1,E + case 0xCC: // SET 1,H + case 0xCD: // SET 1,L + case 0xCE: // SET 1,(HL) + case 0xCF: // SET 1,A + case 0xD0: // SET 2,B + case 0xD1: // SET 2,C + case 0xD2: // SET 2,D + case 0xD3: // SET 2,E + case 0xD4: // SET 2,H + case 0xD5: // SET 2,L + case 0xD6: // SET 2,(HL) + case 0xD7: // SET 2,A + case 0xD8: // SET 3,B + case 0xD9: // SET 3,C + case 0xDA: // SET 3,D + case 0xDB: // SET 3,E + case 0xDC: // SET 3,H + case 0xDD: // SET 3,L + case 0xDE: // SET 3,(HL) + case 0xDF: // SET 3,A + case 0xE0: // SET 4,B + case 0xE1: // SET 4,C + case 0xE2: // SET 4,D + case 0xE3: // SET 4,E + case 0xE4: // SET 4,H + case 0xE5: // SET 4,L + case 0xE6: // SET 4,(HL) + case 0xE7: // SET 4,A + case 0xE8: // SET 5,B + case 0xE9: // SET 5,C + case 0xEA: // SET 5,D + case 0xEB: // SET 5,E + case 0xEC: // SET 5,H + case 0xED: // SET 5,L + case 0xEE: // SET 5,(HL) + case 0xEF: // SET 5,A + case 0xF0: // SET 6,B + case 0xF1: // SET 6,C + case 0xF2: // SET 6,D + case 0xF3: // SET 6,E + case 0xF4: // SET 6,H + case 0xF5: // SET 6,L + case 0xF6: // SET 6,(HL) + case 0xF7: // SET 6,A + case 0xF8: // SET 7,B + case 0xF9: // SET 7,C + case 0xFA: // SET 7,D + case 0xFB: // SET 7,E + case 0xFC: // SET 7,H + case 0xFD: // SET 7,L + case 0xFE: // SET 7,(HL) + case 0xFF: // SET 7,A + return (inst_XXcb_set(code)); + } + /*if (PC) + PC--; + else + PC= get_mem_size(MEM_ROM_ID)-1;*/ + PC= rom->inc_address(PC, -1); + return(resINV_INST); +} + +/* End of z80.src/inst_xxcb.cc */ diff --git a/sim/ucsim/z80.src/instcl.h b/sim/ucsim/z80.src/instcl.h new file mode 100644 index 0000000..8a457e9 --- /dev/null +++ b/sim/ucsim/z80.src/instcl.h @@ -0,0 +1,97 @@ +/* z80.src/instcl.h */ + + virtual int inst_nop(t_mem code); + virtual int inst_ld(t_mem code); + virtual int inst_inc(t_mem code); + virtual int inst_dec(t_mem code); + virtual int inst_rlca(t_mem code); + virtual int inst_rrca(t_mem code); + virtual int inst_ex(t_mem code); + virtual int inst_add(t_mem code); + virtual int inst_djnz(t_mem code); + virtual int inst_jr(t_mem code); + virtual int inst_rla(t_mem code); + virtual int inst_rra(t_mem code); + virtual int inst_daa(t_mem code); + virtual int inst_cpl(t_mem code); + virtual int inst_scf(t_mem code); + virtual int inst_ccf(t_mem code); + virtual int inst_halt(t_mem code); + virtual int inst_adc(t_mem code); + virtual int inst_sbc(t_mem code); + virtual int inst_and(t_mem code); + virtual int inst_xor(t_mem code); + virtual int inst_or(t_mem code); + virtual int inst_cp(t_mem code); + virtual int inst_rst(t_mem code); + virtual int inst_ret(t_mem code); + virtual int inst_call(t_mem code); + virtual int inst_out(t_mem code); + virtual int inst_push(t_mem code); + virtual int inst_exx(t_mem code); + virtual int inst_in(t_mem code); + virtual int inst_sub(t_mem code); + virtual int inst_pop(t_mem code); + virtual int inst_jp(t_mem code); + virtual int inst_di(t_mem code); + virtual int inst_ei(t_mem code); + + virtual int inst_fd(t_mem prefix); + virtual int inst_fd_ld(t_mem code); + virtual int inst_fd_add(t_mem code); + virtual int inst_fd_push(t_mem code); + virtual int inst_fd_inc(t_mem code); + virtual int inst_fd_dec(t_mem code); + virtual int inst_fd_misc(t_mem code); + + virtual int inst_dd(t_mem prefix); + virtual int inst_dd_ld(t_mem code); + virtual int inst_dd_add(t_mem code); + virtual int inst_dd_push(t_mem code); + virtual int inst_dd_inc(t_mem code); + virtual int inst_dd_dec(t_mem code); + virtual int inst_dd_misc(t_mem code); + + virtual int inst_ed(t_mem prefix); + virtual int inst_ed_(t_mem code); + + virtual int inst_cb(void); + virtual int inst_cb_rlc(t_mem code); + virtual int inst_cb_rrc(t_mem code); + virtual int inst_cb_rl(t_mem code); + virtual int inst_cb_rr(t_mem code); + virtual int inst_cb_sla(t_mem code); + virtual int inst_cb_sra(t_mem code); + virtual int inst_cb_slia(t_mem code); + virtual int inst_cb_srl(t_mem code); + virtual int inst_cb_bit(t_mem code); + virtual int inst_cb_res(t_mem code); + virtual int inst_cb_set(t_mem code); + + virtual int inst_ddcb(void); + virtual int inst_ddcb_rlc(t_mem code); + virtual int inst_ddcb_rrc(t_mem code); + virtual int inst_ddcb_rl(t_mem code); + virtual int inst_ddcb_rr(t_mem code); + virtual int inst_ddcb_sla(t_mem code); + virtual int inst_ddcb_sra(t_mem code); + virtual int inst_ddcb_slia(t_mem code); + virtual int inst_ddcb_srl(t_mem code); + virtual int inst_ddcb_bit(t_mem code); + virtual int inst_ddcb_res(t_mem code); + virtual int inst_ddcb_set(t_mem code); + + virtual int inst_fdcb(void); + virtual int inst_fdcb_rlc(t_mem code); + virtual int inst_fdcb_rrc(t_mem code); + virtual int inst_fdcb_rl(t_mem code); + virtual int inst_fdcb_rr(t_mem code); + virtual int inst_fdcb_sla(t_mem code); + virtual int inst_fdcb_sra(t_mem code); + virtual int inst_fdcb_slia(t_mem code); + virtual int inst_fdcb_srl(t_mem code); + virtual int inst_fdcb_bit(t_mem code); + virtual int inst_fdcb_res(t_mem code); + virtual int inst_fdcb_set(t_mem code); + +/* End of z80.src/instcl.h */ diff --git a/sim/ucsim/z80.src/lr35902.cc b/sim/ucsim/z80.src/lr35902.cc new file mode 100755 index 0000000..3513248 --- /dev/null +++ b/sim/ucsim/z80.src/lr35902.cc @@ -0,0 +1,670 @@ +/*
+ * Simulator for the LR35902 used in the gb console.
+ * The processor is closely related to the Z-80, so the C++
+ * emulator object inherits from it.
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+ UCSIM is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
+
+ UCSIM is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with UCSIM; see the file COPYING. If not, write to the Free
+ Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+ 02111-1307, USA. */
+/*@1@*/
+
+#include "ddconfig.h"
+
+#include <stdarg.h> /* for va_list */
+#include <stdio.h>
+#include <stdlib.h>
+#include <ctype.h>
+#include "i_string.h"
+
+// prj
+#include "pobjcl.h"
+
+// sim
+#include "simcl.h"
+
+// local
+#include "z80cl.h"
+#include "lr35902cl.h"
+#include "glob.h"
+
+#define uint32 t_addr
+#define uint8 unsigned char
+
+/*******************************************************************/
+
+lr35902_memory::lr35902_memory( cl_uc &uc_parent_ref ):uc_r(uc_parent_ref) { }
+
+cl_lr35902::cl_lr35902(struct cpu_entry *Itype, class cl_sim *asim):
+ cl_z80(Itype, asim), mem(*this)
+{
+ type= Itype;
+}
+
+int
+cl_lr35902::init(void)
+{
+ cl_uc::init(); /* Memories now exist */
+
+ //rom= address_space(MEM_ROM_ID); // code goes here...
+
+ // ram= mem(MEM_XRAM);
+ //ram= address_space(MEM_XRAM_ID); // data goes here...
+
+
+ // zero out ram(this is assumed in regression tests)
+ for (int i=0xA000; i<0xFF80; i++) {
+ ram->set((t_addr) i, 0);
+ }
+
+ return(0);
+}
+
+char *
+cl_lr35902::id_string(void)
+{
+ return((char*)"LR35902");
+}
+
+
+void
+cl_lr35902::mk_hw_elements(void)
+{
+ //class cl_base *o;
+ cl_uc::mk_hw_elements();
+}
+
+void lr35902_memory::init(void) {
+ cl_address_space *as_rom;
+ cl_address_space *as_ram;
+
+ as_rom = new cl_address_space("rom"/*MEM_ROM_ID*/,
+ lr35902_rom_start, lr35902_rom_size, 8);
+ as_rom->init();
+ uc_r.address_spaces->add(as_rom);
+ rom = as_rom;
+
+ as_ram = new cl_address_space(MEM_XRAM_ID,
+ lr35902_ram_start, lr35902_ram_size, 8);
+ as_ram->init();
+ uc_r.address_spaces->add(as_ram);
+ ram = as_ram;
+}
+
+void
+cl_lr35902::make_memories(void)
+{
+ mem.init( );
+ rom= mem.rom;
+ ram= mem.ram;
+
+ regs8= new cl_address_space("regs8", 0, 16, 8);
+ regs8->init();
+ regs8->get_cell(0)->decode((t_mem*)®s.raf.A);
+ regs8->get_cell(1)->decode((t_mem*)®s.raf.F);
+ regs8->get_cell(2)->decode((t_mem*)®s.bc.h);
+ regs8->get_cell(3)->decode((t_mem*)®s.bc.l);
+ regs8->get_cell(4)->decode((t_mem*)®s.de.h);
+ regs8->get_cell(5)->decode((t_mem*)®s.de.l);
+ regs8->get_cell(6)->decode((t_mem*)®s.hl.h);
+ regs8->get_cell(7)->decode((t_mem*)®s.hl.l);
+
+ regs8->get_cell(8)->decode((t_mem*)®s.ralt_af.aA);
+ regs8->get_cell(9)->decode((t_mem*)®s.ralt_af.aF);
+ regs8->get_cell(10)->decode((t_mem*)®s.a_bc.h);
+ regs8->get_cell(11)->decode((t_mem*)®s.a_bc.l);
+ regs8->get_cell(12)->decode((t_mem*)®s.a_de.h);
+ regs8->get_cell(13)->decode((t_mem*)®s.a_de.l);
+ regs8->get_cell(14)->decode((t_mem*)®s.a_hl.h);
+ regs8->get_cell(15)->decode((t_mem*)®s.a_hl.l);
+
+ regs16= new cl_address_space("regs16", 0, 11, 16);
+ regs16->init();
+
+ regs16->get_cell(0)->decode((t_mem*)®s.AF);
+ regs16->get_cell(1)->decode((t_mem*)®s.BC);
+ regs16->get_cell(2)->decode((t_mem*)®s.DE);
+ regs16->get_cell(3)->decode((t_mem*)®s.HL);
+ regs16->get_cell(4)->decode((t_mem*)®s.IX);
+ regs16->get_cell(5)->decode((t_mem*)®s.IY);
+ regs16->get_cell(6)->decode((t_mem*)®s.SP);
+ regs16->get_cell(7)->decode((t_mem*)®s.aAF);
+ regs16->get_cell(8)->decode((t_mem*)®s.aBC);
+ regs16->get_cell(9)->decode((t_mem*)®s.aDE);
+ regs16->get_cell(10)->decode((t_mem*)®s.aHL);
+
+ address_spaces->add(regs8);
+ address_spaces->add(regs16);
+
+ class cl_var *v;
+ vars->add(v= new cl_var(cchars("A"), regs8, 0, ""));
+ v->init();
+ vars->add(v= new cl_var(cchars("F"), regs8, 1, ""));
+ v->init();
+ vars->add(v= new cl_var(cchars("B"), regs8, 2, ""));
+ v->init();
+ vars->add(v= new cl_var(cchars("C"), regs8, 3, ""));
+ v->init();
+ vars->add(v= new cl_var(cchars("D"), regs8, 4, ""));
+ v->init();
+ vars->add(v= new cl_var(cchars("E"), regs8, 5, ""));
+ v->init();
+ vars->add(v= new cl_var(cchars("H"), regs8, 6, ""));
+ v->init();
+ vars->add(v= new cl_var(cchars("L"), regs8, 7, ""));
+ v->init();
+
+ vars->add(v= new cl_var(cchars("ALT_A"), regs8, 8, ""));
+ v->init();
+ vars->add(v= new cl_var(cchars("ALT_F"), regs8, 9, ""));
+ v->init();
+ vars->add(v= new cl_var(cchars("ALT_B"), regs8, 10, ""));
+ v->init();
+ vars->add(v= new cl_var(cchars("ALT_C"), regs8, 11, ""));
+ v->init();
+ vars->add(v= new cl_var(cchars("ALT_D"), regs8, 12, ""));
+ v->init();
+ vars->add(v= new cl_var(cchars("ALT_E"), regs8, 13, ""));
+ v->init();
+ vars->add(v= new cl_var(cchars("ALT_H"), regs8, 14, ""));
+ v->init();
+ vars->add(v= new cl_var(cchars("ALT_L"), regs8, 15, ""));
+ v->init();
+
+ vars->add(v= new cl_var(cchars("AF"), regs16, 0, ""));
+ v->init();
+ vars->add(v= new cl_var(cchars("BC"), regs16, 1, ""));
+ v->init();
+ vars->add(v= new cl_var(cchars("DE"), regs16, 2, ""));
+ v->init();
+ vars->add(v= new cl_var(cchars("HL"), regs16, 3, ""));
+ v->init();
+ vars->add(v= new cl_var(cchars("IX"), regs16, 4, ""));
+ v->init();
+ vars->add(v= new cl_var(cchars("IY"), regs16, 5, ""));
+ v->init();
+ vars->add(v= new cl_var(cchars("SP"), regs16, 6, ""));
+ v->init();
+ vars->add(v= new cl_var(cchars("ALT_AF"), regs16, 7, ""));
+ v->init();
+ vars->add(v= new cl_var(cchars("ALT_BC"), regs16, 8, ""));
+ v->init();
+ vars->add(v= new cl_var(cchars("ALT_DE"), regs16, 9, ""));
+ v->init();
+ vars->add(v= new cl_var(cchars("ALT_HL"), regs16, 10, ""));
+ v->init();
+}
+
+
+void cl_lr35902::store1( u16_t addr, t_mem val ) {
+ mem.store1( addr, val );
+}
+
+void cl_lr35902::store2( u16_t addr, u16_t val ) {
+ mem.store2( addr, val );
+}
+
+u8_t cl_lr35902::get1( u16_t addr ) {
+ return mem.get1( addr );
+}
+
+u16_t cl_lr35902::get2( u16_t addr ) {
+ return mem.get2( addr );
+}
+
+void lr35902_memory::store1( u16_t addr, t_mem val ) {
+ if (addr < lr35902_ram_start) {
+ /* flag illegal operation ? */
+ return;
+ }
+
+ if ((addr- lr35902_ram_start) < lr35902_ram_size) {
+ ram->write(addr, val);
+ }
+}
+
+void lr35902_memory::store2( u16_t addr, u16_t val ) {
+ store1(addr, val & 0xff);
+ store1(addr+1, (val >> 8) & 0xff);
+}
+
+u8_t lr35902_memory::get1( u16_t addr ) {
+ if (addr < lr35902_rom_size) {
+ return rom->read(addr);
+ }
+
+ if (addr < lr35902_ram_start) {
+ /* flag illegal operation ? */
+ return (addr & 0xff);
+ }
+
+ if ((addr-lr35902_ram_start) < lr35902_ram_size) {
+ return ram->read(addr);
+ }
+
+ return (addr & 0xff);
+}
+
+u16_t lr35902_memory::get2( u16_t addr ) {
+ u16_t l, h;
+
+ l = get1(addr );
+ h = get1(addr+1);
+
+ return (h << 8) | l;
+}
+
+/*
+ * Help command interpreter
+ */
+
+struct dis_entry *
+cl_lr35902::dis_tbl(void)
+{
+ return(disass_lr35902);
+}
+
+
+int
+cl_lr35902::inst_length(t_addr addr)
+{
+ int len = 0;
+
+ get_disasm_info(addr, &len, NULL, NULL);
+
+ return len;
+}
+
+int
+cl_lr35902::inst_branch(t_addr addr)
+{
+ int b;
+
+ get_disasm_info(addr, NULL, &b, NULL);
+
+ return b;
+}
+
+int
+cl_lr35902::longest_inst(void)
+{
+ return 4;
+}
+
+
+const char *
+cl_lr35902::get_disasm_info(t_addr addr,
+ int *ret_len,
+ int *ret_branch,
+ int *immed_offset)
+{
+ const char *b = NULL;
+ uint code;
+ int len = 0;
+ int immed_n = 0;
+ int i;
+ int start_addr = addr;
+ struct dis_entry *dis_e;
+
+ code= rom->get(addr++);
+ dis_e = NULL;
+
+ switch(code) {
+ case 0xcb: /* ESC code to lots of op-codes, all 2-byte */
+ code= rom->get(addr++);
+ i= 0;
+ while ((code & disass_lr35902_cb[i].mask) != disass_lr35902_cb[i].code &&
+ disass_lr35902_cb[i].mnemonic)
+ i++;
+ dis_e = &disass_lr35902_cb[i];
+ b= disass_lr35902_cb[i].mnemonic;
+ if (b != NULL)
+ len += (disass_lr35902_cb[i].length + 1);
+ break;
+
+ default:
+ i= 0;
+ while ((code & disass_lr35902[i].mask) != disass_lr35902[i].code &&
+ disass_lr35902[i].mnemonic)
+ i++;
+ dis_e = &disass_lr35902[i];
+ b= disass_lr35902[i].mnemonic;
+ if (b != NULL)
+ len += (disass_lr35902[i].length);
+ break;
+ }
+
+
+ if (ret_branch) {
+ *ret_branch = dis_e->branch;
+ }
+
+ if (immed_offset) {
+ if (immed_n > 0)
+ *immed_offset = immed_n;
+ else *immed_offset = (addr - start_addr);
+ }
+
+ if (len == 0)
+ len = 1;
+
+ if (ret_len)
+ *ret_len = len;
+
+ return b;
+}
+
+char *
+cl_lr35902::disass(t_addr addr, const char *sep)
+{
+ char work[256], temp[20];
+ const char *b;
+ char *buf, *p, *t;
+ int len = 0;
+ int immed_offset = 0;
+
+ p= work;
+
+ b = get_disasm_info(addr, &len, NULL, &immed_offset);
+
+ if (b == NULL) {
+ buf= (char*)malloc(30);
+ strcpy(buf, "UNKNOWN/INVALID");
+ return(buf);
+ }
+
+ while (*b)
+ {
+ if (*b == '%')
+ {
+ b++;
+ switch (*(b++))
+ {
+ case 'd': // d jump relative target, signed? byte immediate operand
+ sprintf(temp, "#%d", (char)rom->get(addr+immed_offset));
+ ++immed_offset;
+ break;
+ case 'w': // w word immediate operand
+ sprintf(temp, "#0x%04x",
+ (uint)((rom->get(addr+immed_offset)) |
+ (rom->get(addr+immed_offset+1)<<8)) );
+ ++immed_offset;
+ ++immed_offset;
+ break;
+ case 'b': // b byte immediate operand
+ sprintf(temp, "#0x%02x", (uint)rom->get(addr+immed_offset));
+ ++immed_offset;
+ break;
+ default:
+ strcpy(temp, "?");
+ break;
+ }
+ t= temp;
+ while (*t)
+ *(p++)= *(t++);
+ }
+ else
+ *(p++)= *(b++);
+ }
+ *p= '\0';
+
+ p= strchr(work, ' ');
+ if (!p)
+ {
+ buf= strdup(work);
+ return(buf);
+ }
+ if (sep == NULL)
+ buf= (char *)malloc(6+strlen(p)+1);
+ else
+ buf= (char *)malloc((p-work)+strlen(sep)+strlen(p)+1);
+ for (p= work, t= buf; *p != ' '; p++, t++)
+ *t= *p;
+ p++;
+ *t= '\0';
+ if (sep == NULL)
+ {
+ while (strlen(buf) < 6)
+ strcat(buf, " ");
+ }
+ else
+ strcat(buf, sep);
+ strcat(buf, p);
+ return(buf);
+}
+
+
+void
+cl_lr35902::print_regs(class cl_console_base *con)
+{
+ con->dd_printf("SZ-A-PNC Flags= 0x%02x %3d %c ",
+ regs.raf.F, regs.raf.F, isprint(regs.raf.F)?regs.raf.F:'.');
+ con->dd_printf("A= 0x%02x %3d %c\n",
+ regs.raf.A, regs.raf.A, isprint(regs.raf.A)?regs.raf.A:'.');
+ con->dd_printf("%c%c-%c-%c%c%c\n",
+ (regs.raf.F&BIT_S)?'1':'0',
+ (regs.raf.F&BIT_Z)?'1':'0',
+ (regs.raf.F&BIT_A)?'1':'0',
+ (regs.raf.F&BIT_P)?'1':'0',
+ (regs.raf.F&BIT_N)?'1':'0',
+ (regs.raf.F&BIT_C)?'1':'0');
+ con->dd_printf("BC= 0x%04x [BC]= %02x %3d %c ",
+ regs.BC, ram->get(regs.BC), ram->get(regs.BC),
+ isprint(ram->get(regs.BC))?ram->get(regs.BC):'.');
+ con->dd_printf("DE= 0x%04x [DE]= %02x %3d %c ",
+ regs.DE, ram->get(regs.DE), ram->get(regs.DE),
+ isprint(ram->get(regs.DE))?ram->get(regs.DE):'.');
+ con->dd_printf("HL= 0x%04x [HL]= %02x %3d %c\n",
+ regs.HL, ram->get(regs.HL), ram->get(regs.HL),
+ isprint(ram->get(regs.HL))?ram->get(regs.HL):'.');
+ con->dd_printf("SP= 0x%04x [SP]= %02x %3d %c\n",
+ regs.SP, ram->get(regs.SP), ram->get(regs.SP),
+ isprint(ram->get(regs.SP))?ram->get(regs.SP):'.');
+
+ print_disass(PC, con);
+}
+
+/*
+ * Execution
+ */
+
+int
+cl_lr35902::exec_inst(void)
+{
+ t_mem code;
+
+ instPC= PC;
+
+ if (fetch(&code))
+ return(resBREAKPOINT);
+ tick(1);
+ switch (code)
+ {
+ case 0x00: return(inst_nop(code));
+ case 0x01: case 0x02: case 0x06: return(inst_ld(code));
+ case 0x03: case 0x04: return(inst_inc(code));
+ case 0x05: return(inst_dec(code));
+ case 0x07: return(inst_rlca(code));
+
+ case 0x08: return(inst_st_sp_abs(code));
+ case 0x09: return(inst_add(code));
+ case 0x0a: case 0x0e: return(inst_ld(code));
+ case 0x0b: case 0x0d: return(inst_dec(code));
+ case 0x0c: return(inst_inc(code));
+ case 0x0f: return(inst_rrca(code));
+
+
+ case 0x10: return(inst_stop0(code));
+ case 0x11: case 0x12: case 0x16: return(inst_ld(code));
+ case 0x13: case 0x14: return(inst_inc(code));
+ case 0x15: return(inst_dec(code));
+ case 0x17: return(inst_rla(code));
+
+ case 0x18: return(inst_jr(code));
+ case 0x19: return(inst_add(code));
+ case 0x1a: case 0x1e: return(inst_ld(code));
+ case 0x1b: case 0x1d: return(inst_dec(code));
+ case 0x1c: return(inst_inc(code));
+ case 0x1f: return(inst_rra(code));
+
+
+ case 0x20: return(inst_jr(code));
+ case 0x21: case 0x26: return(inst_ld(code));
+ case 0x22: return inst_ldi(code);
+ case 0x23: case 0x24: return(inst_inc(code));
+ case 0x25: return(inst_dec(code));
+ case 0x27: return(inst_daa(code));
+
+ case 0x28: return(inst_jr(code));
+ case 0x29: return(inst_add(code));
+ case 0x2a: return(inst_ldi(code));
+ case 0x2b: case 0x2d: return(inst_dec(code));
+ case 0x2c: return(inst_inc(code));
+ case 0x2e: return(inst_ld(code));
+ case 0x2f: return(inst_cpl(code));
+
+ case 0x30: return(inst_jr(code));
+ case 0x31: case 0x36: return(inst_ld(code));
+ case 0x32: return(inst_ldd(code));
+ case 0x33: case 0x34: return(inst_inc(code));
+ case 0x35: return(inst_dec(code));
+ case 0x37: return(inst_scf(code));
+
+ case 0x38: return(inst_jr(code));
+ case 0x39: return(inst_add(code));
+ case 0x3a: return inst_ldd(code);
+ case 0x3b: case 0x3d: return(inst_dec(code));
+ case 0x3c: return(inst_inc(code));
+ case 0x3e: return(inst_ld(code));
+ case 0x3f: return(inst_ccf(code));
+
+ case 0x40: case 0x41: case 0x42: case 0x43: case 0x44: case 0x45: case 0x46: case 0x47:
+ case 0x48: case 0x49: case 0x4a: case 0x4b: case 0x4c: case 0x4d: case 0x4e: case 0x4f:
+ return(inst_ld(code));
+
+ case 0x50: case 0x51: case 0x52: case 0x53: case 0x54: case 0x55: case 0x56: case 0x57:
+ case 0x58: case 0x59: case 0x5a: case 0x5b: case 0x5c: case 0x5d: case 0x5e: case 0x5f:
+ return(inst_ld(code));
+
+ case 0x60: case 0x61: case 0x62: case 0x63: case 0x64: case 0x65: case 0x66: case 0x67:
+ case 0x68: case 0x69: case 0x6a: case 0x6b: case 0x6c: case 0x6d: case 0x6e: case 0x6f:
+ return(inst_ld(code));
+
+ case 0x70: case 0x71: case 0x72: case 0x73: case 0x74: case 0x75: case 0x77:
+ case 0x78: case 0x79: case 0x7a: case 0x7b: case 0x7c: case 0x7d: case 0x7e: case 0x7f:
+ return(inst_ld(code));
+ case 0x76: return(inst_halt(code));
+
+ case 0x80: case 0x81: case 0x82: case 0x83: case 0x84: case 0x85: case 0x86: case 0x87:
+ return(inst_add(code));
+ case 0x88: case 0x89: case 0x8a: case 0x8b: case 0x8c: case 0x8d: case 0x8e: case 0x8f:
+ return(inst_adc(code));
+
+ case 0x90: case 0x91: case 0x92: case 0x93: case 0x94: case 0x95: case 0x96: case 0x97:
+ return(inst_sub(code));
+ case 0x98: case 0x99: case 0x9a: case 0x9b: case 0x9c: case 0x9d: case 0x9e: case 0x9f:
+ return(inst_sbc(code));
+
+ case 0xa0: case 0xa1: case 0xa2: case 0xa3: case 0xa4: case 0xa5: case 0xa6: case 0xa7:
+ return(inst_and(code));
+ case 0xa8: case 0xa9: case 0xaa: case 0xab: case 0xac: case 0xad: case 0xae: case 0xaf:
+ return(inst_xor(code));
+
+ case 0xb0: case 0xb1: case 0xb2: case 0xb3: case 0xb4: case 0xb5: case 0xb6: case 0xb7:
+ return(inst_or(code));
+ case 0xb8: case 0xb9: case 0xba: case 0xbb: case 0xbc: case 0xbd: case 0xbe: case 0xbf:
+ return(inst_cp(code));
+
+ case 0xc0: return(inst_ret(code));
+ case 0xc1: return(inst_pop(code));
+ case 0xc2: case 0xc3: return(inst_jp(code));
+ case 0xc4: return(inst_call(code));
+ case 0xc5: return(inst_push(code));
+ case 0xc6: return(inst_add(code));
+ case 0xc7: return(inst_rst(code));
+
+ case 0xc8: case 0xc9: return(inst_ret(code));
+ case 0xca: return(inst_jp(code));
+
+ /* CB escapes out to 2 byte opcodes(CB include), opcodes
+ to do register bit manipulations */
+ case 0xcb: return(inst_cb( ));
+ case 0xcc: case 0xcd: return(inst_call(code));
+ case 0xce: return(inst_adc(code));
+ case 0xcf: return(inst_rst(code));
+
+ case 0xd0: return(inst_ret(code));
+ case 0xd1: return(inst_pop(code));
+ case 0xd2: return(inst_jp(code));
+ case 0xd3: break;
+ case 0xd4: return(inst_call(code));
+ case 0xd5: return(inst_push(code));
+ case 0xd6: return(inst_sub(code));
+ case 0xd7: return(inst_rst(code));
+
+ case 0xd8: return(inst_ret(code));
+ case 0xd9: return(inst_reti(code));
+ case 0xda: return(inst_jp(code));
+ case 0xdb: break;
+ case 0xdc: return(inst_call(code));
+
+ case 0xdd: break; /* IX register doesn't exist on the LR35902 */
+ case 0xde: return(inst_sbc(code));
+ case 0xdf: return(inst_rst(code));
+
+
+ case 0xe0: return(inst_ldh(code));
+ case 0xe1: return(inst_pop(code));
+ case 0xe2: return(inst_ldh(code));
+ case 0xe3:
+ case 0xe4: break;
+ case 0xe5: return(inst_push(code));
+ case 0xe6: return(inst_and(code));
+ case 0xe7: return(inst_rst(code));
+
+ case 0xe8: return(inst_add_sp_d(code));
+ case 0xe9: return(inst_jp(code));
+ case 0xea: return(inst_ld16(code));
+ case 0xeb:
+ case 0xec: case 0xed: break;
+ case 0xee: return(inst_xor(code));
+ case 0xef: return(inst_rst(code));
+
+ case 0xf0: return(inst_ldh(code));
+ case 0xf1: return(inst_pop(code));
+ case 0xf2: return(inst_ldh(code));
+ case 0xf3: return(inst_di(code));
+ case 0xf4: break;
+ case 0xf5: return(inst_push(code));
+ case 0xf6: return(inst_or(code));
+ case 0xf7: return(inst_rst(code));
+
+ case 0xf8: return(inst_ldhl_sp(code));
+ case 0xf9: return(inst_ld(code));
+ case 0xfa: return(inst_ld16(code));
+ case 0xfb: return(inst_ei(code));
+ case 0xfc:
+ case 0xfd: break;
+ case 0xfe: return(inst_cp(code));
+ case 0xff: return(inst_rst(code));
+ }
+
+ PC= rom->inc_address(PC, -1);
+
+ sim->stop(resINV_INST);
+ return(resINV_INST);
+}
diff --git a/sim/ucsim/z80.src/lr35902cl.h b/sim/ucsim/z80.src/lr35902cl.h new file mode 100755 index 0000000..b22ec2a --- /dev/null +++ b/sim/ucsim/z80.src/lr35902cl.h @@ -0,0 +1,116 @@ +/*
+ * Simulator of microcontrollers (lr35902cl.h)
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING. If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#ifndef LR35902_CL
+#define LR35902_CL
+
+#include "z80cl.h"
+
+class cl_lr35902;
+
+const t_addr lr35902_rom_start = 0x0000;
+const t_addr lr35902_rom_size = 0x6000;
+
+const t_addr lr35902_ram_start = 0xA000;
+const t_addr lr35902_ram_size = 0x5F80;
+
+class lr35902_memory
+{
+ protected:
+ cl_uc &uc_r;
+
+ public:
+ cl_memory *rom;
+ cl_memory *ram;
+
+ lr35902_memory( cl_uc &uc_p );
+
+ virtual void init( void );
+
+
+ virtual void store1( u16_t addr, t_mem val );
+ virtual void store2( u16_t addr, u16_t val );
+
+ virtual u8_t get1( u16_t addr );
+ virtual u16_t get2( u16_t addr );
+
+ // fetch not included b/c it only uses the rom
+};
+
+
+class cl_lr35902: public cl_z80
+{
+public:
+ lr35902_memory mem;
+
+public:
+ cl_lr35902(struct cpu_entry *Itype, class cl_sim *asim);
+ virtual int init(void);
+ virtual char *id_string(void);
+
+ //virtual t_addr get_mem_size(enum mem_class type);
+ virtual void mk_hw_elements(void);
+ virtual void make_memories(void);
+
+ virtual struct dis_entry *dis_tbl(void);
+ virtual int inst_length(t_addr addr);
+ virtual int inst_branch(t_addr addr);
+ virtual int longest_inst(void);
+ virtual char *disass(t_addr addr, const char *sep);
+ virtual void print_regs(class cl_console_base *con);
+
+ virtual int exec_inst(void);
+
+ virtual const char *get_disasm_info(t_addr addr,
+ int *ret_len,
+ int *ret_branch,
+ int *immed_offset);
+
+
+ // memory access altered to use the 'mem' object
+ virtual void store1( u16_t addr, t_mem val );
+ virtual void store2( u16_t addr, u16_t val );
+
+ virtual u8_t get1( u16_t addr );
+ virtual u16_t get2( u16_t addr );
+
+
+ // see #include "instcl.h" for Z80 versions
+ /* instruction function that are add / modified from the Z80 versions */
+ virtual int inst_cb(void);
+
+ virtual int inst_st_sp_abs(t_mem code);
+ virtual int inst_stop0 (t_mem code);
+
+ virtual int inst_ldi (t_mem code);
+ virtual int inst_ldd (t_mem code);
+ virtual int inst_ldh (t_mem code);
+
+ virtual int inst_reti (t_mem code);
+ virtual int inst_add_sp_d(t_mem code);
+ virtual int inst_ld16 (t_mem code);
+ virtual int inst_ldhl_sp (t_mem code);
+
+};
+
+#endif /* LR35902_CL */
diff --git a/sim/ucsim/z80.src/r2k.cc b/sim/ucsim/z80.src/r2k.cc new file mode 100644 index 0000000..f0ab131 --- /dev/null +++ b/sim/ucsim/z80.src/r2k.cc @@ -0,0 +1,778 @@ +/* + * Simulator of microcontrollers (r2k.cc) + * + * Derived from ucSim z80.src/z80.cc + * Modified for rabbit 2000 by Leland Morrison 2011 + * + * some z80 code base from Karl Bongers karl@turbobit.com + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#include "ddconfig.h" + +#include <stdarg.h> /* for va_list */ +#include <stdio.h> +#include <stdlib.h> +#include <ctype.h> +#include "i_string.h" + +// prj +#include "pobjcl.h" + +// sim +#include "simcl.h" + +// local +#include "z80cl.h" +#include "r2kcl.h" +#include "glob.h" + +#define uint32 t_addr +#define uint8 unsigned char + +/*******************************************************************/ + + +/* + * Rabbit 2000 micro-controller object + * (base for Rabbit 3000/4000/5000) + */ + +cl_r2k::cl_r2k(struct cpu_entry *Itype, class cl_sim *asim): + cl_z80(Itype, asim), mmu(this) +{ + type= Itype; +} + +cl_r3ka::cl_r3ka(struct cpu_entry *Itype, class cl_sim *asim): + cl_r2k(Itype, asim) +{ + SU = 0; +} + +int +cl_r2k::init(void) +{ + cl_uc::init(); /* Memories now exist */ + + //rom= address_space(MEM_ROM_ID); +// ram= mem(MEM_XRAM); + //ram= rom; + + // zero out ram(this is assumed in regression tests) + for (int i=0x8000; i<0x10000; i++) { + ram->set((t_addr) i, 0); + } + + return(0); +} + +char * +cl_r2k::id_string(void) +{ + return((char*)"rabbit 2000"); +} + +char * +cl_r3ka::id_string(void) +{ + return((char*)"rabbit 3000A"); +} + +/* + * Making elements of the controller + */ +/* +t_addr +cl_r2k::get_mem_size(enum mem_class type) +{ + switch(type) + { + case MEM_ROM: return(0x10000); + case MEM_XRAM: return(0x10000); + default: return(0); + } + return(cl_uc::get_mem_size(type)); +} +*/ + +void +cl_r2k::mk_hw_elements(void) +{ + //class cl_base *o; + cl_uc::mk_hw_elements(); +} + +void +cl_r2k::make_memories(void) +{ + class cl_address_space *as; + + rom= ram= as= new cl_address_space("rom", 0, 0x10000, 8); + as->init(); + address_spaces->add(as); + + class cl_address_decoder *ad; + class cl_memory_chip *chip; + + chip= new cl_memory_chip("rom_chip", 0x10000, 8); + chip->init(); + memchips->add(chip); + ad= new cl_address_decoder(as= address_space("rom"), chip, 0, 0xffff, 0); + ad->init(); + as->decoders->add(ad); + ad->activate(0); + + regs8= new cl_address_space("regs8", 0, 18, 8); + regs8->init(); + regs8->get_cell(0)->decode((t_mem*)®s.raf.A); + regs8->get_cell(1)->decode((t_mem*)®s.raf.F); + regs8->get_cell(2)->decode((t_mem*)®s.bc.h); + regs8->get_cell(3)->decode((t_mem*)®s.bc.l); + regs8->get_cell(4)->decode((t_mem*)®s.de.h); + regs8->get_cell(5)->decode((t_mem*)®s.de.l); + regs8->get_cell(6)->decode((t_mem*)®s.hl.h); + regs8->get_cell(7)->decode((t_mem*)®s.hl.l); + regs8->get_cell(8)->decode((t_mem*)&iir); + regs8->get_cell(9)->decode((t_mem*)&eir); + + regs8->get_cell(9)->decode((t_mem*)®s.ralt_af.aA); + regs8->get_cell(10)->decode((t_mem*)®s.ralt_af.aF); + regs8->get_cell(11)->decode((t_mem*)®s.a_bc.h); + regs8->get_cell(12)->decode((t_mem*)®s.a_bc.l); + regs8->get_cell(13)->decode((t_mem*)®s.a_de.h); + regs8->get_cell(14)->decode((t_mem*)®s.a_de.l); + regs8->get_cell(15)->decode((t_mem*)®s.a_hl.h); + regs8->get_cell(16)->decode((t_mem*)®s.a_hl.l); + + regs16= new cl_address_space("regs16", 0, 11, 16); + regs16->init(); + + regs16->get_cell(0)->decode((t_mem*)®s.AF); + regs16->get_cell(1)->decode((t_mem*)®s.BC); + regs16->get_cell(2)->decode((t_mem*)®s.DE); + regs16->get_cell(3)->decode((t_mem*)®s.HL); + regs16->get_cell(4)->decode((t_mem*)®s.IX); + regs16->get_cell(5)->decode((t_mem*)®s.IY); + regs16->get_cell(6)->decode((t_mem*)®s.SP); + regs16->get_cell(7)->decode((t_mem*)®s.aAF); + regs16->get_cell(8)->decode((t_mem*)®s.aBC); + regs16->get_cell(9)->decode((t_mem*)®s.aDE); + regs16->get_cell(10)->decode((t_mem*)®s.aHL); + + address_spaces->add(regs8); + address_spaces->add(regs16); + + class cl_var *v; + vars->add(v= new cl_var(cchars("A"), regs8, 0, "")); + v->init(); + vars->add(v= new cl_var(cchars("F"), regs8, 1, "")); + v->init(); + vars->add(v= new cl_var(cchars("B"), regs8, 2, "")); + v->init(); + vars->add(v= new cl_var(cchars("C"), regs8, 3, "")); + v->init(); + vars->add(v= new cl_var(cchars("D"), regs8, 4, "")); + v->init(); + vars->add(v= new cl_var(cchars("E"), regs8, 5, "")); + v->init(); + vars->add(v= new cl_var(cchars("H"), regs8, 6, "")); + v->init(); + vars->add(v= new cl_var(cchars("L"), regs8, 7, "")); + v->init(); + vars->add(v= new cl_var(cchars("IIR"), regs8, 8, "")); + v->init(); + vars->add(v= new cl_var(cchars("EIR"), regs8, 9, "")); + v->init(); + + vars->add(v= new cl_var(cchars("ALT_A"), regs8, 10, "")); + v->init(); + vars->add(v= new cl_var(cchars("ALT_F"), regs8, 11, "")); + v->init(); + vars->add(v= new cl_var(cchars("ALT_B"), regs8, 12, "")); + v->init(); + vars->add(v= new cl_var(cchars("ALT_C"), regs8, 13, "")); + v->init(); + vars->add(v= new cl_var(cchars("ALT_D"), regs8, 14, "")); + v->init(); + vars->add(v= new cl_var(cchars("ALT_E"), regs8, 15, "")); + v->init(); + vars->add(v= new cl_var(cchars("ALT_H"), regs8, 16, "")); + v->init(); + vars->add(v= new cl_var(cchars("ALT_L"), regs8, 17, "")); + v->init(); + + vars->add(v= new cl_var(cchars("AF"), regs16, 0, "")); + v->init(); + vars->add(v= new cl_var(cchars("BC"), regs16, 1, "")); + v->init(); + vars->add(v= new cl_var(cchars("DE"), regs16, 2, "")); + v->init(); + vars->add(v= new cl_var(cchars("HL"), regs16, 3, "")); + v->init(); + vars->add(v= new cl_var(cchars("IX"), regs16, 4, "")); + v->init(); + vars->add(v= new cl_var(cchars("IY"), regs16, 5, "")); + v->init(); + vars->add(v= new cl_var(cchars("SP"), regs16, 6, "")); + v->init(); + vars->add(v= new cl_var(cchars("ALT_AF"), regs16, 7, "")); + v->init(); + vars->add(v= new cl_var(cchars("ALT_BC"), regs16, 8, "")); + v->init(); + vars->add(v= new cl_var(cchars("ALT_DE"), regs16, 9, "")); + v->init(); + vars->add(v= new cl_var(cchars("ALT_HL"), regs16, 10, "")); + v->init(); +} + + +/* + * Help command interpreter + */ + +struct dis_entry * +cl_r2k::dis_tbl(void) +{ + return(disass_r2k); +} + +/*struct name_entry * +cl_r2k::sfr_tbl(void) +{ + return(0); +}*/ + +/*struct name_entry * +cl_r2k::bit_tbl(void) +{ + //FIXME + return(0); +}*/ + +int +cl_r2k::inst_length(t_addr addr) +{ + int len = 0; + + get_disasm_info(addr, &len, NULL, NULL); + + return len; +} + +int +cl_r2k::inst_branch(t_addr addr) +{ + int b; + + get_disasm_info(addr, NULL, &b, NULL); + + return b; +} + +int +cl_r2k::longest_inst(void) +{ + return 4; +} + + +const char * +cl_r2k::get_disasm_info(t_addr addr, + int *ret_len, + int *ret_branch, + int *immed_offset) +{ + const char *b = NULL; + uint code; + int len = 0; + int immed_n = 0; + int i; + int start_addr = addr; + struct dis_entry *dis_e; + + code= rom->get/*_mem*/(/*MEM_ROM_ID,*/ addr++); + dis_e = NULL; + + switch(code) { + case 0xcb: /* ESC code to lots of op-codes, all 2-byte */ + code= rom->get/*_mem*/(/*MEM_ROM_ID,*/ addr++); + i= 0; + while ((code & disass_r2k_cb[i].mask) != disass_r2k_cb[i].code && + disass_r2k_cb[i].mnemonic) + i++; + dis_e = &disass_r2k_cb[i]; + b= disass_r2k_cb[i].mnemonic; + if (b != NULL) + len += (disass_r2k_cb[i].length + 1); + break; + + case 0xed: /* ESC code to about 80 opcodes of various lengths */ + code= rom->get/*_mem*/(/*MEM_ROM_ID,*/ addr++); + i= 0; + while ((code & disass_r2k_ed[i].mask) != disass_r2k_ed[i].code && + disass_r2k_ed[i].mnemonic) + i++; + dis_e = &disass_r2k_ed[i]; + b= disass_r2k_ed[i].mnemonic; + if (b != NULL) + len += (disass_r2k_ed[i].length + 1); + break; + + case 0xdd: /* ESC codes,about 284, vary lengths, IX centric */ + code= rom->get(addr++); + if (code == 0xcb) { + immed_n = 2; + addr++; // pass up immed data + code= rom->get(addr++); + i= 0; + while ((code & disass_r2k_ddcb[i].mask) != disass_r2k_ddcb[i].code && + disass_r2k_ddcb[i].mnemonic) + i++; + dis_e = &disass_r2k_ddcb[i]; + b= disass_r2k_ddcb[i].mnemonic; + if (b != NULL) + len += (disass_r2k_ddcb[i].length + 2); + } else { + i= 0; + while ((code & disass_r2k_dd[i].mask) != disass_r2k_dd[i].code && + disass_r2k_dd[i].mnemonic) + i++; + dis_e = &disass_r2k_dd[i]; + b= disass_r2k_dd[i].mnemonic; + if (b != NULL) + len += (disass_r2k_dd[i].length + 1); + } + break; + + case 0xfd: /* ESC codes,sme as dd but IY centric */ + code= rom->get(addr++); + if (code == 0xcb) { + immed_n = 2; + addr++; // pass up immed data + code= rom->get(addr++); + i= 0; + while ((code & disass_r2k_fdcb[i].mask) != disass_r2k_fdcb[i].code && + disass_r2k_fdcb[i].mnemonic) + i++; + dis_e = &disass_r2k_fdcb[i]; + b= disass_r2k_fdcb[i].mnemonic; + if (b != NULL) + len += (disass_r2k_fdcb[i].length + 2); + } else { + i= 0; + while ((code & disass_r2k_fd[i].mask) != disass_r2k_fd[i].code && + disass_r2k_fd[i].mnemonic) + i++; + dis_e = &disass_r2k_fd[i]; + b= disass_r2k_fd[i].mnemonic; + if (b != NULL) + len += (disass_r2k_fd[i].length + 1); + } + break; + + default: + i= 0; + while ((code & disass_r2k[i].mask) != disass_r2k[i].code && + disass_r2k[i].mnemonic) + i++; + dis_e = &disass_r2k[i]; + b= disass_r2k[i].mnemonic; + if (b != NULL) + len += (disass_r2k[i].length); + break; + } + + + if (ret_branch) { + *ret_branch = dis_e->branch; + } + + if (immed_offset) { + if (immed_n > 0) + *immed_offset = immed_n; + else *immed_offset = (addr - start_addr); + } + + if (len == 0) + len = 1; + + if (ret_len) + *ret_len = len; + + return b; +} + +char * +cl_r2k::disass(t_addr addr, const char *sep) +{ + char work[256], temp[20]; + const char *b; + char *buf, *p, *t; + int len = 0; + int immed_offset = 0; + + p= work; + + b = get_disasm_info(addr, &len, NULL, &immed_offset); + + if (b == NULL) { + buf= (char*)malloc(30); + strcpy(buf, "UNKNOWN/INVALID"); + return(buf); + } + + while (*b) + { + if (*b == '%') + { + b++; + switch (*(b++)) + { + case 'd': // d jump relative target, signed? byte immediate operand + sprintf(temp, "#%d", (char)rom->get(addr+immed_offset)); + ++immed_offset; + break; + case 'w': // w word immediate operand + sprintf(temp, "#0x%04x", + (uint)((rom->get(addr+immed_offset)) | + (rom->get(addr+immed_offset+1)<<8)) ); + ++immed_offset; + ++immed_offset; + break; + case 'b': // b byte immediate operand + sprintf(temp, "#0x%02x", (uint)rom->get(addr+immed_offset)); + ++immed_offset; + break; + default: + strcpy(temp, "?"); + break; + } + t= temp; + while (*t) + *(p++)= *(t++); + } + else + *(p++)= *(b++); + } + *p= '\0'; + + p= strchr(work, ' '); + if (!p) + { + buf= strdup(work); + return(buf); + } + if (sep == NULL) + buf= (char *)malloc(6+strlen(p)+1); + else + buf= (char *)malloc((p-work)+strlen(sep)+strlen(p)+1); + for (p= work, t= buf; *p != ' '; p++, t++) + *t= *p; + p++; + *t= '\0'; + if (sep == NULL) + { + while (strlen(buf) < 6) + strcat(buf, " "); + } + else + strcat(buf, sep); + strcat(buf, p); + return(buf); +} + + +void +cl_r2k::print_regs(class cl_console_base *con) +{ + con->dd_printf("SZ-A-PNC Flags= 0x%02x %3d %c ", + regs.raf.F, regs.raf.F, isprint(regs.raf.F)?regs.raf.F:'.'); + con->dd_printf("A= 0x%02x %3d %c\n", + regs.raf.A, regs.raf.A, isprint(regs.raf.A)?regs.raf.A:'.'); + con->dd_printf("%c%c-%c-%c%c%c\n", + (regs.raf.F&BIT_S)?'1':'0', + (regs.raf.F&BIT_Z)?'1':'0', + (regs.raf.F&BIT_A)?'1':'0', + (regs.raf.F&BIT_P)?'1':'0', + (regs.raf.F&BIT_N)?'1':'0', + (regs.raf.F&BIT_C)?'1':'0'); + con->dd_printf("BC= 0x%04x [BC]= %02x %3d %c ", + regs.BC, ram->get(regs.BC), ram->get(regs.BC), + isprint(ram->get(regs.BC))?ram->get(regs.BC):'.'); + con->dd_printf("DE= 0x%04x [DE]= %02x %3d %c ", + regs.DE, ram->get(regs.DE), ram->get(regs.DE), + isprint(ram->get(regs.DE))?ram->get(regs.DE):'.'); + con->dd_printf("HL= 0x%04x [HL]= %02x %3d %c\n", + regs.HL, ram->get(regs.HL), ram->get(regs.HL), + isprint(ram->get(regs.HL))?ram->get(regs.HL):'.'); + con->dd_printf("IX= 0x%04x [IX]= %02x %3d %c ", + regs.IX, ram->get(regs.IX), ram->get(regs.IX), + isprint(ram->get(regs.IX))?ram->get(regs.IX):'.'); + con->dd_printf("IY= 0x%04x [IY]= %02x %3d %c ", + regs.IY, ram->get(regs.IY), ram->get(regs.IY), + isprint(ram->get(regs.IY))?ram->get(regs.IY):'.'); + con->dd_printf("SP= 0x%04x [SP]= %02x %3d %c\n", + regs.SP, ram->get(regs.SP), ram->get(regs.SP), + isprint(ram->get(regs.SP))?ram->get(regs.SP):'.'); + + print_disass(PC, con); +} + +/* + * Execution + */ + +int +cl_r2k::exec_inst(void) +{ + t_mem code; + + ins_start = PC; + instPC = PC; + + if (fetch(&code)) + return(resBREAKPOINT); + tick(1); + + /* handling for IOI and IOE prefixes */ + mmu.io_flag = 0; + if ((code == 0xd3) || (code == 0xdb)) { + mmu.io_flag = (code == 0xd3) ? IOI : IOE; + + if (fetch(&code)) + return(resBREAKPOINT); + tick(1); + } + + return exec_code( code ); +} + +int cl_r2k::exec_code(t_mem code) +{ + switch (code) + { + case 0x00: return(inst_nop(code)); + case 0x01: case 0x02: case 0x06: return(inst_ld(code)); + case 0x03: case 0x04: return(inst_inc(code)); + case 0x05: return(inst_dec(code)); + case 0x07: return(inst_rlca(code)); + + case 0x08: return(inst_ex(code)); + case 0x09: return(inst_add(code)); + case 0x0a: case 0x0e: return(inst_ld(code)); + case 0x0b: case 0x0d: return(inst_dec(code)); + case 0x0c: return(inst_inc(code)); + case 0x0f: return(inst_rrca(code)); + + case 0x10: return(inst_djnz(code)); + case 0x11: case 0x12: case 0x16: return(inst_ld(code)); + case 0x13: case 0x14: return(inst_inc(code)); + case 0x15: return(inst_dec(code)); + case 0x17: return(inst_rla(code)); + + case 0x18: return(inst_jr(code)); + case 0x19: return(inst_add(code)); + case 0x1a: case 0x1e: return(inst_ld(code)); + case 0x1b: case 0x1d: return(inst_dec(code)); + case 0x1c: return(inst_inc(code)); + case 0x1f: return(inst_rra(code)); + + + case 0x20: return(inst_jr(code)); + case 0x21: case 0x22: case 0x26: return(inst_ld(code)); + case 0x23: case 0x24: return(inst_inc(code)); + case 0x25: return(inst_dec(code)); + + //case 0x27: return(inst_daa(code)); + case 0x27: return(inst_add_sp_d(code)); + + case 0x28: return(inst_jr(code)); + case 0x29: return(inst_add(code)); + case 0x2a: case 0x2e: return(inst_ld(code)); + case 0x2b: case 0x2d: return(inst_dec(code)); + case 0x2c: return(inst_inc(code)); + case 0x2f: return(inst_cpl(code)); + + + case 0x30: return(inst_jr(code)); + case 0x31: case 0x32: case 0x36: return(inst_ld(code)); + case 0x33: case 0x34: return(inst_inc(code)); + case 0x35: return(inst_dec(code)); + case 0x37: return(inst_scf(code)); + + case 0x38: return(inst_jr(code)); + case 0x39: return(inst_add(code)); + case 0x3a: case 0x3e: return(inst_ld(code)); + case 0x3b: case 0x3d: return(inst_dec(code)); + case 0x3c: return(inst_inc(code)); + case 0x3f: return(inst_ccf(code)); + + case 0x40: case 0x41: case 0x42: case 0x43: case 0x44: case 0x45: case 0x46: case 0x47: + case 0x48: case 0x49: case 0x4a: case 0x4b: case 0x4c: case 0x4d: case 0x4e: case 0x4f: + return(inst_ld(code)); + + case 0x50: case 0x51: case 0x52: case 0x53: case 0x54: case 0x55: case 0x56: case 0x57: + case 0x58: case 0x59: case 0x5a: case 0x5b: case 0x5c: case 0x5d: case 0x5e: case 0x5f: + return(inst_ld(code)); + + case 0x60: case 0x61: case 0x62: case 0x63: case 0x64: case 0x65: case 0x66: case 0x67: + case 0x68: case 0x69: case 0x6a: case 0x6b: case 0x6c: case 0x6d: case 0x6e: case 0x6f: + return(inst_ld(code)); + + case 0x70: case 0x71: case 0x72: case 0x73: case 0x74: case 0x75: case 0x77: + case 0x78: case 0x79: case 0x7a: case 0x7b: case 0x7c: case 0x7d: case 0x7e: case 0x7f: + return(inst_ld(code)); + case 0x76: + //return(inst_halt(code)); + return(inst_altd(code)); + + case 0x80: case 0x81: case 0x82: case 0x83: case 0x84: case 0x85: case 0x86: case 0x87: + return(inst_add(code)); + case 0x88: case 0x89: case 0x8a: case 0x8b: case 0x8c: case 0x8d: case 0x8e: case 0x8f: + return(inst_adc(code)); + + case 0x90: case 0x91: case 0x92: case 0x93: case 0x94: case 0x95: case 0x96: case 0x97: + return(inst_sub(code)); + case 0x98: case 0x99: case 0x9a: case 0x9b: case 0x9c: case 0x9d: case 0x9e: case 0x9f: + return(inst_sbc(code)); + + case 0xa0: case 0xa1: case 0xa2: case 0xa3: case 0xa4: case 0xa5: case 0xa6: case 0xa7: + return(inst_and(code)); + case 0xa8: case 0xa9: case 0xaa: case 0xab: case 0xac: case 0xad: case 0xae: case 0xaf: + return(inst_xor(code)); + + case 0xb0: case 0xb1: case 0xb2: case 0xb3: case 0xb4: case 0xb5: case 0xb6: case 0xb7: + return(inst_or(code)); + case 0xb8: case 0xb9: case 0xba: case 0xbb: case 0xbc: case 0xbd: case 0xbe: case 0xbf: + return(inst_cp(code)); + + case 0xc0: return(inst_ret(code)); + case 0xc1: return(inst_pop(code)); + case 0xc2: case 0xc3: return(inst_jp(code)); + case 0xc4: return(inst_r2k_ld(code)); + case 0xc5: return(inst_push(code)); + case 0xc6: return(inst_add(code)); + case 0xc7: return(inst_ljp(code)); + + case 0xc8: case 0xc9: return(inst_ret(code)); + case 0xca: return(inst_jp(code)); + + /* CB escapes out to 2 byte opcodes(CB include), opcodes + to do register bit manipulations */ + case 0xcb: return(inst_cb()); + case 0xcc: return(inst_bool(code)); + case 0xcd: return(inst_call(code)); + case 0xce: return(inst_adc(code)); + case 0xcf: return(inst_lcall(code)); + + + case 0xd0: return(inst_ret(code)); + case 0xd1: return(inst_pop(code)); + case 0xd2: return(inst_jp(code)); + case 0xd3: /* error (ioi prefix) */ break; + case 0xd4: return(inst_r2k_ld(code)); + case 0xd5: return(inst_push(code)); + case 0xd6: return(inst_sub(code)); + case 0xd7: return(inst_rst(code)); + + case 0xd8: return(inst_ret(code)); + case 0xd9: return(inst_exx(code)); + case 0xda: return(inst_jp(code)); + case 0xdb: /* error (ioe prefix) */ break; + case 0xdc: return(inst_r2k_and(code)); + /* DD escapes out to 2 to 4 byte opcodes(DD included) + with a variety of uses. It can precede the CB escape + sequence to extend CB codes with IX+immed_byte */ + case 0xdd: return(inst_xd(code)); + case 0xde: return(inst_sbc(code)); + case 0xdf: return(inst_rst(code)); + + + case 0xe0: return(inst_ret(code)); + case 0xe1: return(inst_pop(code)); + case 0xe2: return(inst_jp(code)); + case 0xe3: return(inst_r2k_ex(code)); + case 0xe4: return(inst_r2k_ld(code)); + case 0xe5: return(inst_push(code)); + case 0xe6: return(inst_and(code)); + case 0xe7: return(inst_rst(code)); + + case 0xe8: return(inst_ret(code)); + case 0xe9: return(inst_jp(code)); + case 0xea: return(inst_jp(code)); + case 0xeb: return(inst_ex(code)); + case 0xec: return(inst_r2k_or (code)); + /* ED escapes out to other oddball opcodes */ + case 0xed: return(inst_ed(0xed)); + case 0xee: return(inst_xor(code)); + case 0xef: return(inst_rst(code)); + + case 0xf0: return(inst_ret(code)); + case 0xf1: return(inst_pop(code)); + case 0xf2: return(inst_jp(code)); + case 0xf3: return(inst_rl_de(code)); + case 0xf4: return(inst_r2k_ld(code)); + case 0xf5: return(inst_push(code)); + case 0xf6: return(inst_or(code)); + case 0xf7: return(inst_mul(code)); + + case 0xf8: return(inst_ret(code)); + case 0xf9: return(inst_ld(code)); + case 0xfa: return(inst_jp(code)); + case 0xfb: return(inst_rr_de(code)); + case 0xfc: return(inst_rr_hl(code)); + /* FD escapes out to 2 to 4 byte opcodes(DD included) + with a variety of uses. It can precede the CB escape + sequence to extend CB codes with IX+immed_byte */ + case 0xfd: return(inst_xd(code)); + case 0xfe: return(inst_cp(code)); + case 0xff: return(inst_rst(code)); + } + + /*if (PC) + PC--; + else + PC= get_mem_size(MEM_ROM_ID)-1;*/ + PC= rom->inc_address(PC, -1); + + sim->stop(resINV_INST); + return(resINV_INST); +} + +int cl_r3ka::exec_code(t_mem code) +{ + if (code == 0x5B) + { + // IDET + // if (EDMR && (SU & 0x01)) + // system violation interrupt... + ; + } + + return cl_r2k::exec_code(code); +} + +/* End of z80.src/z80.cc */ diff --git a/sim/ucsim/z80.src/r2kcl.h b/sim/ucsim/z80.src/r2kcl.h new file mode 100644 index 0000000..845a89c --- /dev/null +++ b/sim/ucsim/z80.src/r2kcl.h @@ -0,0 +1,167 @@ +/*
+ * Simulator of microcontrollers (z80cl.h)
+ *
+ * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
+ *
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING. If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#ifndef R2KCL_HEADER
+#define R2KCL_HEADER
+
+#include "z80cl.h"
+
+ /* TODO: maybe this should become an enum */
+#define IOI 1 // next instruction uses internal I/O space
+#define IOE 2 // next instruction uses external I/O space
+
+#define MMIDR 0x10 /* MMU Instruction/Data Register */
+#define SADR 0xC0 /* Serial A Data Register in IOI (internal I/O space) */
+
+
+class cl_r2k;
+
+class rabbit_mmu {
+public:
+ cl_r2k *parent_p;
+
+ /* Note: DEF_REGPAIR is defined in regsz80.h */
+
+ u8_t xpc;
+ u8_t dataseg;
+ u8_t stackseg;
+ u8_t segsize;
+
+ u8_t io_flag; /* pseudo register for ioi/ioe prefixes */
+
+ u8_t mmidr; /* MMU Instruction/Data Register __at 0x10 */
+
+ rabbit_mmu( cl_r2k *parent_ip ):parent_p(parent_ip),
+ xpc(0), dataseg(0), stackseg(0), segsize(0xFF)
+ { }
+
+ u32_t/*TYPE_UDWORD*/ logical_addr_to_phys( u16_t logical_addr );
+};
+
+
+class cl_r2k: public cl_z80
+{
+public:
+ // from cl_z80:
+ //class cl_memory *ram;
+ //class cl_memory *rom;
+ //struct t_regs regs;
+
+ rabbit_mmu mmu;
+
+ u16_t ins_start; /* PC value for start of the current instruction */
+ u8_t ip; /* interrupt priority register */
+
+ /* iir, eir registers are not full supported */
+ u8_t iir;
+ u8_t eir;
+
+ /* see Rabbit Family of Microprocessors: Instruction Reference Manual */
+ /* 019-0098 * 090409-L */
+
+
+public:
+ cl_r2k(struct cpu_entry *Itype, class cl_sim *asim);
+ virtual int init(void);
+ virtual char *id_string(void);
+
+ //virtual t_addr get_mem_size(enum mem_class type);
+ virtual void mk_hw_elements(void);
+ virtual void make_memories(void);
+
+ virtual struct dis_entry *dis_tbl(void);
+ virtual int inst_length(t_addr addr);
+ virtual int inst_branch(t_addr addr);
+ virtual int longest_inst(void);
+ virtual char *disass(t_addr addr, const char *sep);
+ virtual void print_regs(class cl_console_base *con);
+
+ virtual int exec_inst(void);
+ virtual int exec_code(t_mem code);
+
+ virtual const char *get_disasm_info(t_addr addr,
+ int *ret_len,
+ int *ret_branch,
+ int *immed_offset);
+
+
+ virtual void store1( u16_t addr, t_mem val );
+ virtual void store2( u16_t addr, u16_t val );
+
+ virtual u8_t get1( u16_t addr );
+ virtual u16_t get2( u16_t addr );
+
+ virtual t_mem fetch1( void );
+ virtual u16_t fetch2( void );
+
+ virtual t_mem fetch(void);
+ virtual bool fetch(t_mem *code) {
+ return cl_uc::fetch(code);
+ }
+
+ // see #include "instcl.h" for Z80 versions
+ /* instruction function that are add / modified from the Z80 versions */
+ virtual int inst_rst(t_mem code);
+
+ virtual int inst_add_sp_d(t_mem code);
+ virtual int inst_altd(t_mem code);
+
+ virtual int inst_bool (t_mem code);
+ virtual int inst_r2k_ld (t_mem code);
+ virtual int inst_r2k_and(t_mem code);
+ virtual int inst_r2k_or (t_mem code);
+ virtual int inst_r2k_ex (t_mem code);
+
+ virtual int inst_ljp(t_mem code);
+ virtual int inst_lcall(t_mem code);
+ virtual int inst_mul(t_mem code);
+
+ virtual int inst_rl_de(t_mem code);
+ virtual int inst_rr_de(t_mem code);
+ virtual int inst_rr_hl(t_mem code);
+
+ virtual int inst_xd(t_mem prefix);
+
+ //virtual int inst_ed(void);
+ virtual int inst_ed_(t_mem code);
+
+};
+
+class cl_r3ka: public cl_r2k {
+ public:
+
+ u8_t SU;
+
+ cl_r3ka(struct cpu_entry *Itype, class cl_sim *asim);
+ virtual char *id_string(void);
+
+ virtual int exec_code(t_mem code);
+
+ virtual int inst_ed_(t_mem code);
+};
+
+#endif /* R2KCL_HEADER */
diff --git a/sim/ucsim/z80.src/regsz80.h b/sim/ucsim/z80.src/regsz80.h new file mode 100644 index 0000000..a494951 --- /dev/null +++ b/sim/ucsim/z80.src/regsz80.h @@ -0,0 +1,119 @@ +/* + * Simulator of microcontrollers (regsz80.h) + * + * some z80 code base from Karl Bongers karl@turbobit.com + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#ifndef REGSZ80_HEADER +#define REGSZ80_HEADER + +#include "ddconfig.h" + + +struct t_regpair +{ +#ifdef WORDS_BIGENDIAN + u8_t/*TYPE_UBYTE*/ h; + u8_t/*TYPE_UBYTE*/ l; +#else + u8_t/*TYPE_UBYTE*/ l; + u8_t/*TYPE_UBYTE*/ h; +#endif +}; + +#define DEF_REGPAIR(BIGNAME,smallname) \ + union { \ + u16_t/*TYPE_UWORD*/ BIGNAME; \ + struct t_regpair smallname; \ + } + +struct t_regs +{ + //TYPE_UBYTE A; + //TYPE_UBYTE F; + union { + u16_t AF; + struct { +#ifdef WORDS_BIGENDIAN + u8_t/*TYPE_UBYTE*/ A; + u8_t/*TYPE_UBYTE*/ F; +#else + u8_t/*TYPE_UBYTE*/ F; + u8_t/*TYPE_UBYTE*/ A; +#endif + } raf; + }; + DEF_REGPAIR(BC, bc); + DEF_REGPAIR(DE, de); + DEF_REGPAIR(HL, hl); + DEF_REGPAIR(IX, ix); + DEF_REGPAIR(IY, iy); + u16_t/*TYPE_UWORD*/ SP; + /* there are alternate AF,BC,DE,HL register sets, and a few instructions + that swap one for the other */ + //TYPE_UBYTE aA; + //TYPE_UBYTE aF; + union { + u16_t aAF; + struct { +#ifdef WORDS_BIGENDIAN + u8_t/*TYPE_UBYTE*/ aA; + u8_t/*TYPE_UBYTE*/ aF; +#else + u8_t/*TYPE_UBYTE*/ aF; + u8_t/*TYPE_UBYTE*/ aA; +#endif + } ralt_af; + }; + DEF_REGPAIR(aBC, a_bc); + DEF_REGPAIR(aDE, a_de); + DEF_REGPAIR(aHL, a_hl); + + u8_t/*TYPE_UBYTE*/ iv; /* interrupt vector, see ed 47 ld A,IV.. */ +}; + +enum { + BIT_C= 0x01, // carry status(out of bit 7) + BIT_N= 0x02, // Not addition: subtract status(1 after subtract). + BIT_P= 0x04, // parity/overflow, 1=even, 0=odd parity. arith:1=overflow + BIT_A= 0x10, // aux carry status(out of bit 3) + BIT_Z= 0x40, // zero status, 1=zero, 0=nonzero + BIT_S= 0x80, // sign status(value of bit 7) + BIT_ALL= (BIT_C |BIT_N |BIT_P |BIT_A |BIT_Z |BIT_S) // all bits +}; + +enum { + BITPOS_C= 0, // 1 + BITPOS_SUB= 1, // 2H + BITPOS_P= 2, // 4H + BITPOS_A= 4, // 10H + BITPOS_Z= 6, // 40H + BITPOS_S= 7 // 80H +}; + +#endif + +/* End of z80.src/regsz80.h */ diff --git a/sim/ucsim/z80.src/simz80.cc b/sim/ucsim/z80.src/simz80.cc new file mode 100644 index 0000000..f5c5dbc --- /dev/null +++ b/sim/ucsim/z80.src/simz80.cc @@ -0,0 +1,91 @@ +/* + * Simulator of microcontrollers (simz80.cc) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#include "globals.h" + +// local +#include "simz80cl.h" +#include "z80cl.h" +#include "r2kcl.h" +#include "lr35902cl.h" +#include "ez80cl.h" + +cl_simz80::cl_simz80(class cl_app *the_app): + cl_sim(the_app) +{} + +class cl_uc * +cl_simz80::mk_controller(void) +{ + int i; + const char *typ= NIL; + class cl_optref type_option(this); + + type_option.init(); + type_option.use("cpu_type"); + i= 0; + if ((typ= type_option.get_value(typ)) == NIL) + typ= "Z80"; + + while ((cpus_z80[i].type_str != NULL) && + (strcmp(typ, cpus_z80[i].type_str) != 0)) + i++; + if (cpus_z80[i].type_str == NULL) + { + fprintf(stderr, "Unknown processor type. " + "Use -H option to see known types.\n"); + return(NULL); + } + + switch (cpus_z80[i].type) + { + case CPU_Z80: + case CPU_Z180: + return(new cl_z80(&cpus_z80[i], this)); + // Add Rabbits, etc here. + + case CPU_R2K: + return(new cl_r2k (&cpus_z80[i], this)); + + case CPU_R3KA: + return(new cl_r3ka(&cpus_z80[i], this)); + + case CPU_LR35902: + return(new cl_lr35902(&cpus_z80[i], this)); + + case CPU_EZ80: + return(new cl_ez80(&cpus_z80[i], this)); + + default: + return NULL; + } + + return(NULL); +} + + +/* End of z80.src/simz80.cc */ diff --git a/sim/ucsim/z80.src/simz80cl.h b/sim/ucsim/z80.src/simz80cl.h new file mode 100644 index 0000000..d9b7ea1 --- /dev/null +++ b/sim/ucsim/z80.src/simz80cl.h @@ -0,0 +1,45 @@ +/* + * Simulator of microcontrollers (simz80cl.h) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#ifndef SIMZ80CL_HEADER +#define SIMZ80CL_HEADER + +#include "simcl.h" + + +class cl_simz80: public cl_sim +{ +public: + cl_simz80(class cl_app *the_app); + + virtual class cl_uc *mk_controller(void); +}; + + +#endif + +/* End of z80.src/simz80cl.h */ diff --git a/sim/ucsim/z80.src/sz80.cc b/sim/ucsim/z80.src/sz80.cc new file mode 100644 index 0000000..381ac8f --- /dev/null +++ b/sim/ucsim/z80.src/sz80.cc @@ -0,0 +1,57 @@ +/* + * Simulator of microcontrollers (sz80.cc) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +// prj +#include "globals.h" + +// sim.src +#include "appcl.h" + +// local +#include "simz80cl.h" + + +int +main(int argc, char *argv[]) +{ + class cl_sim *sim; + + cpus= cpus_z80; + application= new cl_app(); + application->init(argc, argv); + sim= new cl_simz80(application); + if (sim->init()) + sim->state|= SIM_QUIT; + application->set_simulator(sim); + application->run(); + application->done(); + delete application; + return(0); +} + + +/* End of z80.src/sz80.cc */ diff --git a/sim/ucsim/z80.src/test/Makefile b/sim/ucsim/z80.src/test/Makefile new file mode 100644 index 0000000..1d5f10e --- /dev/null +++ b/sim/ucsim/z80.src/test/Makefile @@ -0,0 +1,11 @@ +PRJ = t0 t1 t2 + +all: + for p in $(PRJ); do \ + $(MAKE) -f $$p.mk ;\ + done + +clean: + for p in $(PRJ); do \ + $(MAKE) -f $$p.mk clean ;\ + done diff --git a/sim/ucsim/z80.src/test/conf.cmd b/sim/ucsim/z80.src/test/conf.cmd new file mode 100644 index 0000000..6989cea --- /dev/null +++ b/sim/ucsim/z80.src/test/conf.cmd @@ -0,0 +1 @@ +set hw simif nas 0xffff diff --git a/sim/ucsim/z80.src/test/dummy.h b/sim/ucsim/z80.src/test/dummy.h new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/sim/ucsim/z80.src/test/dummy.h diff --git a/sim/ucsim/z80.src/test/run.cmd b/sim/ucsim/z80.src/test/run.cmd new file mode 100644 index 0000000..972da4f --- /dev/null +++ b/sim/ucsim/z80.src/test/run.cmd @@ -0,0 +1,2 @@ +run +state diff --git a/sim/ucsim/z80.src/test/run.sh b/sim/ucsim/z80.src/test/run.sh new file mode 100755 index 0000000..57d6d88 --- /dev/null +++ b/sim/ucsim/z80.src/test/run.sh @@ -0,0 +1,7 @@ +PRJ=$1 + +if [ -z "$PRJ" ]; then + PRJ=t1 +fi + +../sz80 -C conf.cmd ${PRJ}.ihx <run.cmd diff --git a/sim/ucsim/z80.src/test/sdcc.mk b/sim/ucsim/z80.src/test/sdcc.mk new file mode 100644 index 0000000..ea3bcd7 --- /dev/null +++ b/sim/ucsim/z80.src/test/sdcc.mk @@ -0,0 +1,41 @@ +CC = sdcc -mz80 + +CPPFLAGS = +CFLAGS = --debug +LDFLAGS = +LIBS = + +ALL = $(MAIN) $(OTHERS) +OBJECTS = $(MAIN).rel $(OTHERS:=.rel) + +all: $(MAIN).hex + +dep: $(MAIN).dep + +$(MAIN).dep: $(OBJECTS:.rel=.c) *.h + @>$(MAIN).dep + @for c in $(OBJECTS:.rel=.c); do \ + $(CC) -MM $(CPPFALGS) $$c >>$(MAIN).dep ;\ + done + +include $(MAIN).dep + +$(MAIN).ihx: $(OBJECTS) + $(CC) $(CFLAGS) $(LDFLAGS) $(OBJECTS) -o $@ + +.SUFFIXES: .rel .ihx .hex + +.c.rel: + $(CC) -c $(CPPFLAGS) $(CFLAGS) $< + +.ihx.hex: + packihx $< >$@ + +clean: + rm -f $(ALL:=.rel) $(ALL:=.asm) $(ALL:=.lst) $(ALL:=.rst) $(ALL:=.sym) $(ALL:=.adb) + rm -f $(MAIN).ihx $(MAIN).hex $(MAIN).lk $(MAIN).map $(MAIN).mem $(MAIN).cdb $(MAIN).omf $(MAIN).noi + rm -f *~ + rm -f $(MAIN).dep + + +# End of sdcc.mk diff --git a/sim/ucsim/z80.src/test/t0.c b/sim/ucsim/z80.src/test/t0.c new file mode 100644 index 0000000..f64e179 --- /dev/null +++ b/sim/ucsim/z80.src/test/t0.c @@ -0,0 +1,6 @@ +void main(void) +{ + unsigned int i, j; + for (i=0; i<0x2233; i++) + j= i; +} diff --git a/sim/ucsim/z80.src/test/t0.mk b/sim/ucsim/z80.src/test/t0.mk new file mode 100644 index 0000000..6f11fe4 --- /dev/null +++ b/sim/ucsim/z80.src/test/t0.mk @@ -0,0 +1,3 @@ +MAIN = t0 + +include sdcc.mk diff --git a/sim/ucsim/z80.src/test/t1.c b/sim/ucsim/z80.src/test/t1.c new file mode 100644 index 0000000..83cd784 --- /dev/null +++ b/sim/ucsim/z80.src/test/t1.c @@ -0,0 +1,37 @@ +static unsigned char * volatile sif= (unsigned char *)0xffff; + +volatile unsigned char x; + +void +putchar(unsigned char c) +{ + *sif= 'p'; + *sif= c; +} + +void +prints(char *s) +{ + while (*s) + putchar(*s++); +} + +void +main(void) +{ + unsigned char i; + unsigned int j; + + prints("Start.\n"); + for (j= 0; j<41000; j++) + { + x= j; + i= j; + putchar('a'); + } + + prints("Done.\n"); + *sif= 's'; + for (;;) + ; +} diff --git a/sim/ucsim/z80.src/test/t1.mk b/sim/ucsim/z80.src/test/t1.mk new file mode 100644 index 0000000..dee0618 --- /dev/null +++ b/sim/ucsim/z80.src/test/t1.mk @@ -0,0 +1,3 @@ +MAIN = t1 + +include sdcc.mk diff --git a/sim/ucsim/z80.src/test/t2.c b/sim/ucsim/z80.src/test/t2.c new file mode 100644 index 0000000..50debbb --- /dev/null +++ b/sim/ucsim/z80.src/test/t2.c @@ -0,0 +1,36 @@ +static unsigned char * volatile sif= (unsigned char *)0xffff; + +volatile unsigned char x; + +void +putchar(unsigned char c) +{ + *sif= 'p'; + *sif= c; +} + +void +prints(char *s) +{ + while (*s) + putchar(*s++); +} + +void +main(void) +{ + unsigned int i; + unsigned int j; + + prints("Start.\n"); + for (j= 0; j<200; j++) + { + for (i= 1000; i; i--) + putchar('a'); + } + + prints("Done.\n"); + *sif= 's'; + for (;;) + ; +} diff --git a/sim/ucsim/z80.src/test/t2.mk b/sim/ucsim/z80.src/test/t2.mk new file mode 100644 index 0000000..c2dd6e7 --- /dev/null +++ b/sim/ucsim/z80.src/test/t2.mk @@ -0,0 +1,3 @@ +MAIN = t2 + +include sdcc.mk diff --git a/sim/ucsim/z80.src/z80.cc b/sim/ucsim/z80.src/z80.cc new file mode 100644 index 0000000..c711f8e --- /dev/null +++ b/sim/ucsim/z80.src/z80.cc @@ -0,0 +1,843 @@ +/* + * Simulator of microcontrollers (z80.cc) + * + * some z80 code base from Karl Bongers karl@turbobit.com + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#include "ddconfig.h" + +#include <stdarg.h> /* for va_list */ +#include <stdio.h> +#include <stdlib.h> +#include <ctype.h> +#include "i_string.h" + +// prj +#include "pobjcl.h" + +// sim +#include "simcl.h" + +// local +#include "z80cl.h" +#include "glob.h" +#include "regsz80.h" + +#define uint32 t_addr +#define uint8 unsigned char + +/*******************************************************************/ + + +/* + * Base type of Z80 controllers + */ + +cl_z80::cl_z80(struct cpu_entry *Itype, class cl_sim *asim): + cl_uc(asim) +{ + type= Itype; +} + +int +cl_z80::init(void) +{ + + cl_uc::init(); /* Memories now exist */ + + //rom= address_space(MEM_ROM_ID); +// ram= mem(MEM_XRAM); + //ram= rom; + + // zero out ram(this is assumed in regression tests) + for (int i=0x8000; i<0x10000; i++) { + ram->set((t_addr) i, 0); + } + + return(0); +} + +char * +cl_z80::id_string(void) +{ + return((char*)"unspecified Z80"); +} + + +/* + * Making elements of the controller + */ +/* +t_addr +cl_z80::get_mem_size(enum mem_class type) +{ + switch(type) + { + case MEM_ROM: return(0x10000); + case MEM_XRAM: return(0x10000); + default: return(0); + } + return(cl_uc::get_mem_size(type)); +} +*/ + +void +cl_z80::mk_hw_elements(void) +{ + //class cl_base *o; + cl_uc::mk_hw_elements(); +} + +void +cl_z80::make_memories(void) +{ + class cl_address_space *as; + + rom= ram= as= new cl_address_space("rom", 0, 0x10000, 8); + as->init(); + address_spaces->add(as); + + class cl_address_decoder *ad; + class cl_memory_chip *chip; + + chip= new cl_memory_chip("rom_chip", 0x10000, 8); + chip->init(); + memchips->add(chip); + ad= new cl_address_decoder(as= address_space("rom"), chip, 0, 0xffff, 0); + ad->init(); + as->decoders->add(ad); + ad->activate(0); + + inputs= new cl_address_space("inputs", 0, 0x10000, 8); + inputs->init(); + chip= new cl_memory_chip("in_chip", 0x10000, 8); + chip->init(); + memchips->add(chip); + ad= new cl_address_decoder(inputs, chip, 0, 0xffff, 0); + ad->init(); + inputs->decoders->add(ad); + address_spaces->add(inputs); + outputs= new cl_address_space("outputs", 0, 0x10000, 8); + outputs->init(); + chip= new cl_memory_chip("out_chip", 0x10000, 8); + chip->init(); + memchips->add(chip); + ad= new cl_address_decoder(outputs, chip, 0, 0xffff, 0); + ad->init(); + outputs->decoders->add(ad); + address_spaces->add(outputs); + + regs8= new cl_address_space("regs8", 0, 16, 8); + regs8->init(); + regs8->get_cell(0)->decode((t_mem*)®s.raf.A); + regs8->get_cell(1)->decode((t_mem*)®s.raf.F); + regs8->get_cell(2)->decode((t_mem*)®s.bc.h); + regs8->get_cell(3)->decode((t_mem*)®s.bc.l); + regs8->get_cell(4)->decode((t_mem*)®s.de.h); + regs8->get_cell(5)->decode((t_mem*)®s.de.l); + regs8->get_cell(6)->decode((t_mem*)®s.hl.h); + regs8->get_cell(7)->decode((t_mem*)®s.hl.l); + + regs8->get_cell(8)->decode((t_mem*)®s.ralt_af.aA); + regs8->get_cell(9)->decode((t_mem*)®s.ralt_af.aF); + regs8->get_cell(10)->decode((t_mem*)®s.a_bc.h); + regs8->get_cell(11)->decode((t_mem*)®s.a_bc.l); + regs8->get_cell(12)->decode((t_mem*)®s.a_de.h); + regs8->get_cell(13)->decode((t_mem*)®s.a_de.l); + regs8->get_cell(14)->decode((t_mem*)®s.a_hl.h); + regs8->get_cell(15)->decode((t_mem*)®s.a_hl.l); + + regs16= new cl_address_space("regs16", 0, 11, 16); + regs16->init(); + + regs16->get_cell(0)->decode((t_mem*)®s.AF); + regs16->get_cell(1)->decode((t_mem*)®s.BC); + regs16->get_cell(2)->decode((t_mem*)®s.DE); + regs16->get_cell(3)->decode((t_mem*)®s.HL); + regs16->get_cell(4)->decode((t_mem*)®s.IX); + regs16->get_cell(5)->decode((t_mem*)®s.IY); + regs16->get_cell(6)->decode((t_mem*)®s.SP); + regs16->get_cell(7)->decode((t_mem*)®s.aAF); + regs16->get_cell(8)->decode((t_mem*)®s.aBC); + regs16->get_cell(9)->decode((t_mem*)®s.aDE); + regs16->get_cell(10)->decode((t_mem*)®s.aHL); + + address_spaces->add(regs8); + address_spaces->add(regs16); + + class cl_var *v; + vars->add(v= new cl_var(cchars("A"), regs8, 0, "")); + v->init(); + vars->add(v= new cl_var(cchars("F"), regs8, 1, "")); + v->init(); + vars->add(v= new cl_var(cchars("B"), regs8, 2, "")); + v->init(); + vars->add(v= new cl_var(cchars("C"), regs8, 3, "")); + v->init(); + vars->add(v= new cl_var(cchars("D"), regs8, 4, "")); + v->init(); + vars->add(v= new cl_var(cchars("E"), regs8, 5, "")); + v->init(); + vars->add(v= new cl_var(cchars("H"), regs8, 6, "")); + v->init(); + vars->add(v= new cl_var(cchars("L"), regs8, 7, "")); + v->init(); + + vars->add(v= new cl_var(cchars("ALT_A"), regs8, 8, "")); + v->init(); + vars->add(v= new cl_var(cchars("ALT_F"), regs8, 9, "")); + v->init(); + vars->add(v= new cl_var(cchars("ALT_B"), regs8, 10, "")); + v->init(); + vars->add(v= new cl_var(cchars("ALT_C"), regs8, 11, "")); + v->init(); + vars->add(v= new cl_var(cchars("ALT_D"), regs8, 12, "")); + v->init(); + vars->add(v= new cl_var(cchars("ALT_E"), regs8, 13, "")); + v->init(); + vars->add(v= new cl_var(cchars("ALT_H"), regs8, 14, "")); + v->init(); + vars->add(v= new cl_var(cchars("ALT_L"), regs8, 15, "")); + v->init(); + + vars->add(v= new cl_var(cchars("AF"), regs16, 0, "")); + v->init(); + vars->add(v= new cl_var(cchars("BC"), regs16, 1, "")); + v->init(); + vars->add(v= new cl_var(cchars("DE"), regs16, 2, "")); + v->init(); + vars->add(v= new cl_var(cchars("HL"), regs16, 3, "")); + v->init(); + vars->add(v= new cl_var(cchars("IX"), regs16, 4, "")); + v->init(); + vars->add(v= new cl_var(cchars("IY"), regs16, 5, "")); + v->init(); + vars->add(v= new cl_var(cchars("SP"), regs16, 6, "")); + v->init(); + vars->add(v= new cl_var(cchars("ALT_AF"), regs16, 7, "")); + v->init(); + vars->add(v= new cl_var(cchars("ALT_BC"), regs16, 8, "")); + v->init(); + vars->add(v= new cl_var(cchars("ALT_DE"), regs16, 9, "")); + v->init(); + vars->add(v= new cl_var(cchars("ALT_HL"), regs16, 10, "")); + v->init(); +} + + +/* + * Help command interpreter + */ + +struct dis_entry * +cl_z80::dis_tbl(void) +{ + return(disass_z80); +} + +/*struct name_entry * +cl_z80::sfr_tbl(void) +{ + return(0); +}*/ + +/*struct name_entry * +cl_z80::bit_tbl(void) +{ + //FIXME + return(0); +}*/ + +int +cl_z80::inst_length(t_addr addr) +{ + int len = 0; + + get_disasm_info(addr, &len, NULL, NULL, NULL); + + return len; +} + +int +cl_z80::inst_branch(t_addr addr) +{ + int b; + + get_disasm_info(addr, NULL, &b, NULL, NULL); + + return b; +} + +bool +cl_z80::is_call(t_addr addr) +{ + struct dis_entry *e; + + get_disasm_info(addr, NULL, NULL, NULL, &e); + + return e?(e->is_call):false; +} + +int +cl_z80::longest_inst(void) +{ + return 4; +} + + +const char * +cl_z80::get_disasm_info(t_addr addr, + int *ret_len, + int *ret_branch, + int *immed_offset, + struct dis_entry **dentry) +{ + const char *b = NULL; + uint code; + int len = 0; + int immed_n = 0; + int i; + int start_addr = addr; + struct dis_entry *dis_e; + + code= rom->get(addr++); + dis_e = NULL; + + switch(code) { + case 0xcb: /* ESC code to lots of op-codes, all 2-byte */ + code= rom->get(addr++); + i= 0; + while ((code & disass_z80_cb[i].mask) != disass_z80_cb[i].code && + disass_z80_cb[i].mnemonic) + i++; + dis_e = &disass_z80_cb[i]; + b= disass_z80_cb[i].mnemonic; + if (b != NULL) + len += (disass_z80_cb[i].length + 1); + break; + + case 0xed: /* ESC code to about 80 opcodes of various lengths */ + code= rom->get(addr++); + i= 0; + while ((code & disass_z80_ed[i].mask) != disass_z80_ed[i].code && + disass_z80_ed[i].mnemonic) + i++; + dis_e = &disass_z80_ed[i]; + b= disass_z80_ed[i].mnemonic; + if (b != NULL) + len += (disass_z80_ed[i].length + 1); + break; + + case 0xdd: /* ESC codes,about 284, vary lengths, IX centric */ + code= rom->get(addr++); + if (code == 0xcb) { + immed_n = 2; + addr++; // pass up immed data + code= rom->get(addr++); + i= 0; + while ((code & disass_z80_ddcb[i].mask) != disass_z80_ddcb[i].code && + disass_z80_ddcb[i].mnemonic) + i++; + dis_e = &disass_z80_ddcb[i]; + b= disass_z80_ddcb[i].mnemonic; + if (b != NULL) + len += (disass_z80_ddcb[i].length + 2); + } else { + i= 0; + while ((code & disass_z80_dd[i].mask) != disass_z80_dd[i].code && + disass_z80_dd[i].mnemonic) + i++; + dis_e = &disass_z80_dd[i]; + b= disass_z80_dd[i].mnemonic; + if (b != NULL) + len += (disass_z80_dd[i].length + 1); + } + break; + + case 0xfd: /* ESC codes,sme as dd but IY centric */ + code= rom->get(addr++); + if (code == 0xcb) { + immed_n = 2; + addr++; // pass up immed data + code= rom->get(addr++); + i= 0; + while ((code & disass_z80_fdcb[i].mask) != disass_z80_fdcb[i].code && + disass_z80_fdcb[i].mnemonic) + i++; + dis_e = &disass_z80_fdcb[i]; + b= disass_z80_fdcb[i].mnemonic; + if (b != NULL) + len += (disass_z80_fdcb[i].length + 2); + } else { + i= 0; + while ((code & disass_z80_fd[i].mask) != disass_z80_fd[i].code && + disass_z80_fd[i].mnemonic) + i++; + dis_e = &disass_z80_fd[i]; + b= disass_z80_fd[i].mnemonic; + if (b != NULL) + len += (disass_z80_fd[i].length + 1); + } + break; + + default: + i= 0; + while ((code & disass_z80[i].mask) != disass_z80[i].code && + disass_z80[i].mnemonic) + i++; + dis_e = &disass_z80[i]; + b= disass_z80[i].mnemonic; + if (b != NULL) + len += (disass_z80[i].length); + break; + } + + + if (ret_branch) { + *ret_branch = dis_e->branch; + } + + if (immed_offset) { + if (immed_n > 0) + *immed_offset = immed_n; + else *immed_offset = (addr - start_addr); + } + + if (len == 0) + len = 1; + + if (ret_len) + *ret_len = len; + + if (dentry) + *dentry= dis_e; + + return b; +} + +char * +cl_z80::disass(t_addr addr, const char *sep) +{ + char work[256], temp[20]; + const char *b; + char *buf, *p, *t; + int len = 0; + int immed_offset = 0; + + p= work; + + b = get_disasm_info(addr, &len, NULL, &immed_offset, NULL); + + if (b == NULL) { + buf= (char*)malloc(30); + strcpy(buf, "UNKNOWN/INVALID"); + return(buf); + } + + while (*b) + { + if (*b == '%') + { + b++; + switch (*(b++)) + { + case 'd': // d jump relative target, signed? byte immediate operand + sprintf(temp, "#%d", (signed char)(rom->get(addr+immed_offset))); + ++immed_offset; + break; + case 'w': // w word immediate operand + sprintf(temp, "#0x%04x", + (uint)((rom->get(addr+immed_offset)) | + (rom->get(addr+immed_offset+1)<<8)) ); + ++immed_offset; + ++immed_offset; + break; + case 'b': // b byte immediate operand + sprintf(temp, "#0x%02x", (uint)rom->get(addr+immed_offset)); + ++immed_offset; + break; + default: + strcpy(temp, "?"); + break; + } + t= temp; + while (*t) + *(p++)= *(t++); + } + else + *(p++)= *(b++); + } + *p= '\0'; + + p= strchr(work, ' '); + if (!p) + { + buf= strdup(work); + return(buf); + } + if (sep == NULL) + buf= (char *)malloc(6+strlen(p)+1); + else + buf= (char *)malloc((p-work)+strlen(sep)+strlen(p)+1); + for (p= work, t= buf; *p != ' '; p++, t++) + *t= *p; + p++; + *t= '\0'; + if (sep == NULL) + { + while (strlen(buf) < 6) + strcat(buf, " "); + } + else + strcat(buf, sep); + strcat(buf, p); + return(buf); +} + + +void +cl_z80::print_regs(class cl_console_base *con) +{ + con->dd_printf("SZ-A-PNC Flags= 0x%02x %3d %c ", + regs.raf.F, regs.raf.F, isprint(regs.raf.F)?regs.raf.F:'.'); + con->dd_printf("A= 0x%02x %3d %c\n", + regs.raf.A, regs.raf.A, isprint(regs.raf.A)?regs.raf.A:'.'); + con->dd_printf("%c%c-%c-%c%c%c\n", + (regs.raf.F&BIT_S)?'1':'0', + (regs.raf.F&BIT_Z)?'1':'0', + (regs.raf.F&BIT_A)?'1':'0', + (regs.raf.F&BIT_P)?'1':'0', + (regs.raf.F&BIT_N)?'1':'0', + (regs.raf.F&BIT_C)?'1':'0'); + con->dd_printf("BC= 0x%04x [BC]= %02x %3d %c ", + regs.BC, ram->get(regs.BC), ram->get(regs.BC), + isprint(ram->get(regs.BC))?ram->get(regs.BC):'.'); + con->dd_printf("DE= 0x%04x [DE]= %02x %3d %c ", + regs.DE, ram->get(regs.DE), ram->get(regs.DE), + isprint(ram->get(regs.DE))?ram->get(regs.DE):'.'); + con->dd_printf("HL= 0x%04x [HL]= %02x %3d %c\n", + regs.HL, ram->get(regs.HL), ram->get(regs.HL), + isprint(ram->get(regs.HL))?ram->get(regs.HL):'.'); + con->dd_printf("IX= 0x%04x [IX]= %02x %3d %c ", + regs.IX, ram->get(regs.IX), ram->get(regs.IX), + isprint(ram->get(regs.IX))?ram->get(regs.IX):'.'); + con->dd_printf("IY= 0x%04x [IY]= %02x %3d %c ", + regs.IY, ram->get(regs.IY), ram->get(regs.IY), + isprint(ram->get(regs.IY))?ram->get(regs.IY):'.'); + con->dd_printf("SP= 0x%04x [SP]= %02x %3d %c\n", + regs.SP, ram->get(regs.SP), ram->get(regs.SP), + isprint(ram->get(regs.SP))?ram->get(regs.SP):'.'); + + print_disass(PC, con); +} + +/* + * Execution + */ + +int +cl_z80::exec_inst(void) +{ + t_mem code; + + instPC= PC; + + if (fetch(&code)) + return(resBREAKPOINT); + tick(1); + switch (code) + { + case 0x00: return(inst_nop(code)); + case 0x01: case 0x02: case 0x06: return(inst_ld(code)); + case 0x03: case 0x04: return(inst_inc(code)); + case 0x05: return(inst_dec(code)); + case 0x07: return(inst_rlca(code)); + + case 0x08: return(inst_ex(code)); + case 0x09: return(inst_add(code)); + case 0x0a: case 0x0e: return(inst_ld(code)); + case 0x0b: case 0x0d: return(inst_dec(code)); + case 0x0c: return(inst_inc(code)); + case 0x0f: return(inst_rrca(code)); + + + case 0x10: return(inst_djnz(code)); + case 0x11: case 0x12: case 0x16: return(inst_ld(code)); + case 0x13: case 0x14: return(inst_inc(code)); + case 0x15: return(inst_dec(code)); + case 0x17: return(inst_rla(code)); + + case 0x18: return(inst_jr(code)); + case 0x19: return(inst_add(code)); + case 0x1a: case 0x1e: return(inst_ld(code)); + case 0x1b: case 0x1d: return(inst_dec(code)); + case 0x1c: return(inst_inc(code)); + case 0x1f: return(inst_rra(code)); + + + case 0x20: return(inst_jr(code)); + case 0x21: case 0x22: case 0x26: return(inst_ld(code)); + case 0x23: case 0x24: return(inst_inc(code)); + case 0x25: return(inst_dec(code)); + case 0x27: return(inst_daa(code)); + + case 0x28: return(inst_jr(code)); + case 0x29: return(inst_add(code)); + case 0x2a: case 0x2e: return(inst_ld(code)); + case 0x2b: case 0x2d: return(inst_dec(code)); + case 0x2c: return(inst_inc(code)); + case 0x2f: return(inst_cpl(code)); + + + case 0x30: return(inst_jr(code)); + case 0x31: case 0x32: case 0x36: return(inst_ld(code)); + case 0x33: case 0x34: return(inst_inc(code)); + case 0x35: return(inst_dec(code)); + case 0x37: return(inst_scf(code)); + + case 0x38: return(inst_jr(code)); + case 0x39: return(inst_add(code)); + case 0x3a: case 0x3e: return(inst_ld(code)); + case 0x3b: case 0x3d: return(inst_dec(code)); + case 0x3c: return(inst_inc(code)); + case 0x3f: return(inst_ccf(code)); + + case 0x40: case 0x41: case 0x42: case 0x43: case 0x44: case 0x45: case 0x46: case 0x47: + case 0x48: case 0x49: case 0x4a: case 0x4b: case 0x4c: case 0x4d: case 0x4e: case 0x4f: + return(inst_ld(code)); + + case 0x50: case 0x51: case 0x52: case 0x53: case 0x54: case 0x55: case 0x56: case 0x57: + case 0x58: case 0x59: case 0x5a: case 0x5b: case 0x5c: case 0x5d: case 0x5e: case 0x5f: + return(inst_ld(code)); + + case 0x60: case 0x61: case 0x62: case 0x63: case 0x64: case 0x65: case 0x66: case 0x67: + case 0x68: case 0x69: case 0x6a: case 0x6b: case 0x6c: case 0x6d: case 0x6e: case 0x6f: + return(inst_ld(code)); + + case 0x70: case 0x71: case 0x72: case 0x73: case 0x74: case 0x75: case 0x77: + case 0x78: case 0x79: case 0x7a: case 0x7b: case 0x7c: case 0x7d: case 0x7e: case 0x7f: + return(inst_ld(code)); + case 0x76: + return(inst_halt(code)); + + case 0x80: case 0x81: case 0x82: case 0x83: case 0x84: case 0x85: case 0x86: case 0x87: + return(inst_add(code)); + case 0x88: case 0x89: case 0x8a: case 0x8b: case 0x8c: case 0x8d: case 0x8e: case 0x8f: + return(inst_adc(code)); + + case 0x90: case 0x91: case 0x92: case 0x93: case 0x94: case 0x95: case 0x96: case 0x97: + return(inst_sub(code)); + case 0x98: case 0x99: case 0x9a: case 0x9b: case 0x9c: case 0x9d: case 0x9e: case 0x9f: + return(inst_sbc(code)); + + case 0xa0: case 0xa1: case 0xa2: case 0xa3: case 0xa4: case 0xa5: case 0xa6: case 0xa7: + return(inst_and(code)); + case 0xa8: case 0xa9: case 0xaa: case 0xab: case 0xac: case 0xad: case 0xae: case 0xaf: + return(inst_xor(code)); + + case 0xb0: case 0xb1: case 0xb2: case 0xb3: case 0xb4: case 0xb5: case 0xb6: case 0xb7: + return(inst_or(code)); + case 0xb8: case 0xb9: case 0xba: case 0xbb: case 0xbc: case 0xbd: case 0xbe: case 0xbf: + return(inst_cp(code)); + + case 0xc0: return(inst_ret(code)); + case 0xc1: return(inst_pop(code)); + case 0xc2: case 0xc3: return(inst_jp(code)); + case 0xc4: return(inst_call(code)); + case 0xc5: return(inst_push(code)); + case 0xc6: return(inst_add(code)); + case 0xc7: return(inst_rst(code)); + + case 0xc8: case 0xc9: return(inst_ret(code)); + case 0xca: return(inst_jp(code)); + + /* CB escapes out to 2 byte opcodes(CB include), opcodes + to do register bit manipulations */ + case 0xcb: return(inst_cb()); + case 0xcc: case 0xcd: return(inst_call(code)); + case 0xce: return(inst_adc(code)); + case 0xcf: return(inst_rst(code)); + + + case 0xd0: return(inst_ret(code)); + case 0xd1: return(inst_pop(code)); + case 0xd2: return(inst_jp(code)); + case 0xd3: return(inst_out(code)); + case 0xd4: return(inst_call(code)); + case 0xd5: return(inst_push(code)); + case 0xd6: return(inst_sub(code)); + case 0xd7: return(inst_rst(code)); + + case 0xd8: return(inst_ret(code)); + case 0xd9: return(inst_exx(code)); + case 0xda: return(inst_jp(code)); + case 0xdb: return(inst_in(code)); + case 0xdc: return(inst_call(code)); + /* DD escapes out to 2 to 4 byte opcodes(DD included) + with a variety of uses. It can precede the CB escape + sequence to extend CB codes with IX+immed_byte */ + case 0xdd: return(inst_dd(0xdd)); + case 0xde: return(inst_sbc(code)); + case 0xdf: return(inst_rst(code)); + + + case 0xe0: return(inst_ret(code)); + case 0xe1: return(inst_pop(code)); + case 0xe2: return(inst_jp(code)); + case 0xe3: return(inst_ex(code)); + case 0xe4: return(inst_call(code)); + case 0xe5: return(inst_push(code)); + case 0xe6: return(inst_and(code)); + case 0xe7: return(inst_rst(code)); + + case 0xe8: return(inst_ret(code)); + case 0xe9: return(inst_jp(code)); + case 0xea: return(inst_jp(code)); + case 0xeb: return(inst_ex(code)); + case 0xec: return(inst_call(code)); + /* ED escapes out to misc IN, OUT and other oddball opcodes */ + case 0xed: return(inst_ed(0xed)); + case 0xee: return(inst_xor(code)); + case 0xef: return(inst_rst(code)); + + + case 0xf0: return(inst_ret(code)); + case 0xf1: return(inst_pop(code)); + case 0xf2: return(inst_jp(code)); + case 0xf3: return(inst_di(code)); + case 0xf4: return(inst_call(code)); + case 0xf5: return(inst_push(code)); + case 0xf6: return(inst_or(code)); + case 0xf7: return(inst_rst(code)); + + case 0xf8: return(inst_ret(code)); + case 0xf9: return(inst_ld(code)); + case 0xfa: return(inst_jp(code)); + case 0xfb: return(inst_ei(code)); + case 0xfc: return(inst_call(code)); + /* DD escapes out to 2 to 4 byte opcodes(DD included) + with a variety of uses. It can precede the CB escape + sequence to extend CB codes with IX+immed_byte */ + case 0xfd: return(inst_fd(0xfd)); + case 0xfe: return(inst_cp(code)); + case 0xff: return(inst_rst(code)); + } + + /*if (PC) + PC--; + else + PC= get_mem_size(MEM_ROM_ID)-1;*/ + PC= rom->inc_address(PC, -1); + + sim->stop(resINV_INST); + return(resINV_INST); +} + +void cl_z80::store1( u16_t addr, t_mem val ) { + ram->write(addr, val); +} + +void cl_z80::store2( u16_t addr, u16_t val ) { + ram->write(addr, val & 0xff); + ram->write(addr+1, (val >> 8) & 0xff); +} + +u8_t cl_z80::get1( u16_t addr ) { + return ram->read(addr); +} + +u16_t cl_z80::get2( u16_t addr ) { + u16_t l, h; + + l = ram->read(addr ); + h = ram->read(addr+1); + + return (h << 8) | l; +} + +t_mem cl_z80::fetch1( void ) { + return fetch( ); +} + +u16_t cl_z80::fetch2( void ) { + u16_t c1, c2; + + c1 = fetch( ); + c2 = fetch( ); + return (c2 << 8) | c1; +} + +t_mem cl_z80::peek1 ( void ) { + return rom->read(PC); +} + +u8_t cl_z80:: in_byte( u16_t ioaddr ) +{ + return inputs->read(ioaddr); +} + +void cl_z80::out_byte( u16_t ioaddr, u8_t io_val ) +{ + outputs->write(ioaddr, io_val); + return; +} + +u8_t cl_z80::reg_g_read ( t_mem g ) +{ + switch( g ) + { + case 0: return regs.bc.h; + case 1: return regs.bc.l; + case 2: return regs.de.h; + case 3: return regs.de.l; + case 4: return regs.hl.h; + case 5: return regs.hl.l; + case 6: return get1( regs.HL ); + case 7: return regs.raf.A; + default: + return 0xffU; + } +} + +void cl_z80::reg_g_store( t_mem g, u8_t new_val ) +{ + switch( g ) + { + case 0: regs.bc.h = new_val; break; /* write to b */ + case 1: regs.bc.l = new_val; break; /* write to c */ + case 2: regs.de.h = new_val; break; /* write to d */ + case 3: regs.de.l = new_val; break; /* write to e */ + case 4: regs.hl.h = new_val; break; /* write to h */ + case 5: regs.hl.l = new_val; break; /* write to l */ + case 6: /* write to (hl) */ + store1( regs.HL, new_val ); + break; + + case 7: regs.raf.A = new_val; break; /* write to a */ + } +} + +/* End of z80.src/z80.cc */ diff --git a/sim/ucsim/z80.src/z80.txt b/sim/ucsim/z80.src/z80.txt new file mode 100644 index 0000000..4b1be26 --- /dev/null +++ b/sim/ucsim/z80.src/z80.txt @@ -0,0 +1,1402 @@ + +Last week somebody asked for a list of opcodes. +Well, here is mine. Have fun! + +| Herbert Oppmann | email: htoppman@cip.informatik.uni-erlangen.de | +| irc: mtx | mail: Drausnickstrasse 29, D-8520 Erlangen | + +------------ 8< ---------- 8< --------------- +8080/Z80/HD64180 opcodes + +Legend: +HX, LX highbyte/lowbyte of IX +HY, LY dito IY + + 8080 subset +* Z80 only +/ "illegal" Z80 ++ HD 64180 (reacts with a trap to illegal Z80 opcodes) + +Hex Instruction Comment (applies to Z80 only) +----------------------------------------------- +00 NOP +01 nnnn LD BC,nnnn +02 LD (BC),A +03 INC BC +04 INC B +05 DEC B +06 nn LD B,nn +07 RLCA +08 * EX AF,AF' +09 ADD HL,BC +0A LD A,(BC) +0B DEC BC +0C INC C +0D DEC C +0E nn LD C,nn +0F RRCA +10 dd * DJNZ dd +11 nnnn LD DE,nnnn +12 LD (DE),A +13 INC DE +14 INC D +15 DEC D +16 nn LD D,nn +17 RLA +18 dd * JR dd +19 ADD HL,DE +1A LD A,(DE) +1B DEC DE +1C INC E +1D DEC E +1E nn LD E,nn +1F RRA +20 dd * JR NZ,dd +21 nnnn LD HL,nnnn +22 nnnn LD (nnnn),HL +23 INC HL +24 INC H +25 DEC H +26 nn LD H,nn +27 DAA +28 dd * JR Z,dd +29 ADD HL,HL +2A nnnn LD HL,(nnnn) +2B DEC HL +2C INC L +2D DEC L +2E nn LD L,nn +2F CPL +30 dd * JR NC,dd +31 nnnn LD SP,nnnn +32 nnnn LD (nnnn),A +33 INC SP +34 INC (HL) +35 DEC (HL) +36 nn LD (HL),nn +37 SCF +38 dd * JR C,dd +39 ADD HL,SP +3A nnnn LD A,(nnnn) +3B DEC SP +3C INC A +3D DEC A +3E nn LD A,nn +3F CCF +40 LD B,B +41 LD B,C +42 LD B,D +43 LD B,E +44 LD B,H +45 LD B,L +46 LD B,(HL) +47 LD B,A +48 LD C,B +49 LD C,C +4A LD C,D +4B LD C,E +4C LD C,H +4D LD C,L +4E LD C,(HL) +4F LD C,A +50 LD D,B +51 LD D,C +52 LD D,D +53 LD D,E +54 LD D,H +55 LD D,L +56 LD D,(HL) +57 LD D,A +58 LD E,B +59 LD E,C +5A LD E,D +5B LD E,E +5C LD E,H +5D LD E,L +5E LD E,(HL) +5F LD E,A +60 LD H,B +61 LD H,C +62 LD H,D +63 LD H,E +64 LD H,H +65 LD H,L +66 LD H,(HL) +67 LD H,A +68 LD L,B +69 LD L,C +6A LD L,D +6B LD L,E +6C LD L,H +6D LD L,L +6E LD L,(HL) +6F LD L,A +70 LD (HL),B +71 LD (HL),C +72 LD (HL),D +73 LD (HL),E +74 LD (HL),H +75 LD (HL),L +76 HALT +77 LD (HL),A +78 LD A,B +79 LD A,C +7A LD A,D +7B LD A,E +7C LD A,H +7D LD A,L +7E LD A,(HL) +7F LD A,A +80 ADD A,B +81 ADD A,C +82 ADD A,D +83 ADD A,E +84 ADD A,H +85 ADD A,L +86 ADD A,(HL) +87 ADD A,A +88 ADC A,B +89 ADC A,C +8A ADC A,D +8B ADC A,E +8C ADC A,H +8D ADC A,L +8E ADC A,(HL) +8F ADC A,A +90 SUB B +91 SUB C +92 SUB D +93 SUB E +94 SUB H +95 SUB L +96 SUB (HL) +97 SUB A +98 SBC A,B +99 SBC A,C +9A SBC A,D +9B SBC A,E +9C SBC A,H +9D SBC A,L +9E SBC A,(HL) +9F SBC A,A +A0 AND B +A1 AND C +A2 AND D +A3 AND E +A4 AND H +A5 AND L +A6 AND (HL) +A7 AND A +A8 XOR B +A9 XOR C +AA XOR D +AB XOR E +AC XOR H +AD XOR L +AE XOR (HL) +AF XOR A +B0 OR B +B1 OR C +B2 OR D +B3 OR E +B4 OR H +B5 OR L +B6 OR (HL) +B7 OR A +B8 CP B +B9 CP C +BA CP D +BB CP E +BC CP H +BD CP L +BE CP (HL) +BF CP A +C0 RET NZ +C1 POP BC +C2 nnnn JP NZ,nnnn +C3 nnnn JP nnnn +C4 nnnn CALL NZ,nnnn +C5 PUSH BC +C6 nn ADD A,nn +C7 RST 0 +C8 RET Z +C9 RET +CA nnnn JP Z,nnnn +CB 00 * RLC B +CB 01 * RLC C +CB 02 * RLC D +CB 03 * RLC E +CB 04 * RLC H +CB 05 * RLC L +CB 06 * RLC (HL) +CB 07 * RLC A +CB 08 * RRC B +CB 09 * RRC C +CB 0A * RRC D +CB 0B * RRC E +CB 0C * RRC H +CB 0D * RRC L +CB 0E * RRC (HL) +CB 0F * RRC A +CB 10 * RL B +CB 11 * RL C +CB 12 * RL D +CB 13 * RL E +CB 14 * RL H +CB 15 * RL L +CB 16 * RL (HL) +CB 17 * RL A +CB 18 * RR B +CB 19 * RR C +CB 1A * RR D +CB 1B * RR E +CB 1C * RR H +CB 1D * RR L +CB 1E * RR (HL) +CB 1F * RR A +CB 20 * SLA B +CB 21 * SLA C +CB 22 * SLA D +CB 23 * SLA E +CB 24 * SLA H +CB 25 * SLA L +CB 26 * SLA (HL) +CB 27 * SLA A +CB 28 * SRA B +CB 29 * SRA C +CB 2A * SRA D +CB 2B * SRA E +CB 2C * SRA H +CB 2D * SRA L +CB 2E * SRA (HL) +CB 2F * SRA A +CB 30 / SLIA B (Shift Left Inverted Arithmetic) +CB 31 / SLIA C like SLA, but shifts in a 1 bit +CB 32 / SLIA D +CB 33 / SLIA E +CB 34 / SLIA H +CB 35 / SLIA L +CB 36 / SLIA (HL) +CB 37 / SLIA A +CB 38 * SRL B +CB 39 * SRL C +CB 3A * SRL D +CB 3B * SRL E +CB 3C * SRL H +CB 3D * SRL L +CB 3E * SRL (HL) +CB 3F * SRL A +CB 40 * BIT 0,B +CB 41 * BIT 0,C +CB 42 * BIT 0,D +CB 43 * BIT 0,E +CB 44 * BIT 0,H +CB 45 * BIT 0,L +CB 46 * BIT 0,(HL) +CB 47 * BIT 0,A +CB 48 * BIT 1,B +CB 49 * BIT 1,C +CB 4A * BIT 1,D +CB 4B * BIT 1,E +CB 4C * BIT 1,H +CB 4D * BIT 1,L +CB 4E * BIT 1,(HL) +CB 4F * BIT 1,A +CB 50 * BIT 2,B +CB 51 * BIT 2,C +CB 52 * BIT 2,D +CB 53 * BIT 2,E +CB 54 * BIT 2,H +CB 55 * BIT 2,L +CB 56 * BIT 2,(HL) +CB 57 * BIT 2,A +CB 58 * BIT 3,B +CB 59 * BIT 3,C +CB 5A * BIT 3,D +CB 5B * BIT 3,E +CB 5C * BIT 3,H +CB 5D * BIT 3,L +CB 5E * BIT 3,(HL) +CB 5F * BIT 3,A +CB 60 * BIT 4,B +CB 61 * BIT 4,C +CB 62 * BIT 4,D +CB 63 * BIT 4,E +CB 64 * BIT 4,H +CB 65 * BIT 4,L +CB 66 * BIT 4,(HL) +CB 67 * BIT 4,A +CB 68 * BIT 5,B +CB 69 * BIT 5,C +CB 6A * BIT 5,D +CB 6B * BIT 5,E +CB 6C * BIT 5,H +CB 6D * BIT 5,L +CB 6E * BIT 5,(HL) +CB 6F * BIT 5,A +CB 70 * BIT 6,B +CB 71 * BIT 6,C +CB 72 * BIT 6,D +CB 73 * BIT 6,E +CB 74 * BIT 6,H +CB 75 * BIT 6,L +CB 76 * BIT 6,(HL) +CB 77 * BIT 6,A +CB 78 * BIT 7,B +CB 79 * BIT 7,C +CB 7A * BIT 7,D +CB 7B * BIT 7,E +CB 7C * BIT 7,H +CB 7D * BIT 7,L +CB 7E * BIT 7,(HL) +CB 7F * BIT 7,A +CB 80 * RES 0,B +CB 81 * RES 0,C +CB 82 * RES 0,D +CB 83 * RES 0,E +CB 84 * RES 0,H +CB 85 * RES 0,L +CB 86 * RES 0,(HL) +CB 87 * RES 0,A +CB 88 * RES 1,B +CB 89 * RES 1,C +CB 8A * RES 1,D +CB 8B * RES 1,E +CB 8C * RES 1,H +CB 8D * RES 1,L +CB 8E * RES 1,(HL) +CB 8F * RES 1,A +CB 90 * RES 2,B +CB 91 * RES 2,C +CB 92 * RES 2,D +CB 93 * RES 2,E +CB 94 * RES 2,H +CB 95 * RES 2,L +CB 96 * RES 2,(HL) +CB 97 * RES 2,A +CB 98 * RES 3,B +CB 99 * RES 3,C +CB 9A * RES 3,D +CB 9B * RES 3,E +CB 9C * RES 3,H +CB 9D * RES 3,L +CB 9E * RES 3,(HL) +CB 9F * RES 3,A +CB A0 * RES 4,B +CB A1 * RES 4,C +CB A2 * RES 4,D +CB A3 * RES 4,E +CB A4 * RES 4,H +CB A5 * RES 4,L +CB A6 * RES 4,(HL) +CB A7 * RES 4,A +CB A8 * RES 5,B +CB A9 * RES 5,C +CB AA * RES 5,D +CB AB * RES 5,E +CB AC * RES 5,H +CB AD * RES 5,L +CB AE * RES 5,(HL) +CB AF * RES 5,A +CB B0 * RES 6,B +CB B1 * RES 6,C +CB B2 * RES 6,D +CB B3 * RES 6,E +CB B4 * RES 6,H +CB B5 * RES 6,L +CB B6 * RES 6,(HL) +CB B7 * RES 6,A +CB B8 * RES 7,B +CB B9 * RES 7,C +CB BA * RES 7,D +CB BB * RES 7,E +CB BC * RES 7,H +CB BD * RES 7,L +CB BE * RES 7,(HL) +CB BF * RES 7,A +CB C0 * SET 0,B +CB C1 * SET 0,C +CB C2 * SET 0,D +CB C3 * SET 0,E +CB C4 * SET 0,H +CB C5 * SET 0,L +CB C6 * SET 0,(HL) +CB C7 * SET 0,A +CB C8 * SET 1,B +CB C9 * SET 1,C +CB CA * SET 1,D +CB CB * SET 1,E +CB CC * SET 1,H +CB CD * SET 1,L +CB CE * SET 1,(HL) +CB CF * SET 1,A +CB D0 * SET 2,B +CB D1 * SET 2,C +CB D2 * SET 2,D +CB D3 * SET 2,E +CB D4 * SET 2,H +CB D5 * SET 2,L +CB D6 * SET 2,(HL) +CB D7 * SET 2,A +CB D8 * SET 3,B +CB D9 * SET 3,C +CB DA * SET 3,D +CB DB * SET 3,E +CB DC * SET 3,H +CB DD * SET 3,L +CB DE * SET 3,(HL) +CB DF * SET 3,A +CB E0 * SET 4,B +CB E1 * SET 4,C +CB E2 * SET 4,D +CB E3 * SET 4,E +CB E4 * SET 4,H +CB E5 * SET 4,L +CB E6 * SET 4,(HL) +CB E7 * SET 4,A +CB E8 * SET 5,B +CB E9 * SET 5,C +CB EA * SET 5,D +CB EB * SET 5,E +CB EC * SET 5,H +CB ED * SET 5,L +CB EE * SET 5,(HL) +CB EF * SET 5,A +CB F0 * SET 6,B +CB F1 * SET 6,C +CB F2 * SET 6,D +CB F3 * SET 6,E +CB F4 * SET 6,H +CB F5 * SET 6,L +CB F6 * SET 6,(HL) +CB F7 * SET 6,A +CB F8 * SET 7,B +CB F9 * SET 7,C +CB FA * SET 7,D +CB FB * SET 7,E +CB FC * SET 7,H +CB FD * SET 7,L +CB FE * SET 7,(HL) +CB FF * SET 7,A +CC nnnn CALL Z,nnnn +CD nnnn CALL nnnn +CE nn ADC A,nn +CF RST 8 +D0 RET NC +D1 POP DE +D2 nnnn JP NC,nnnn +D3 nn OUT (nn),A +D4 nnnn CALL NC,nnnn +D5 PUSH DE +D6 nn SUB nn +D7 RST 10H +D8 RET C +D9 * EXX +DA nnnn JP C,nnnn +DB nn IN A,(nn) +DC nnnn CALL C,nnnn +All other DD combinations not listed below: + DD is ignored, all following bytes are treated as instructions +DD 09 * ADD IX,BC +DD 19 * ADD IX,DE +DD 21 nnnn * LD IX,nnnn +DD 22 nnnn * LD (nnnn),IX +DD 23 * INC IX +DD 24 / INC HX +DD 25 / DEC HX +DD 26 nn / LD HX,nn +DD 29 * ADD IX,IX +DD 2A nnnn * LD IX,(nnnn) +DD 2B * DEC IX +DD 2C / INC LX +DD 2D / DEC LX +DD 2E nn / LD LX,nn +DD 34 dd * INC (IX+dd) +DD 35 dd * DEC (IX+dd) +DD 36 dd nn * LD (IX+dd),nn +DD 39 * ADD IX,SP +DD 44 / LD B,HX +DD 45 / LD B,LX +DD 46 dd * LD B,(IX+dd) +DD 4C / LD C,HX +DD 4D / LD C,LX +DD 4E dd * LD C,(IX+dd) +DD 54 / LD D,HX +DD 55 / LD D,LX +DD 56 dd * LD D,(IX+dd) +DD 5C / LD E,H +DD 5D / LD E,L +DD 5E dd * LD E,(IX+dd) +DD 60 / LD HX,B +DD 61 / LD HX,C +DD 62 / LD HX,D +DD 63 / LD HX,E +DD 64 / LD HX,HX +DD 65 / LD HX,LX +DD 66 dd * LD H,(IX+dd) +DD 67 / LD HX,A +DD 68 / LD LX,B +DD 69 / LD LX,C +DD 6A / LD LX,D +DD 6B / LD LX,E +DD 6C / LD LX,HX +DD 6D / LD LX,LX +DD 6E dd * LD L,(IX+dd) +DD 6F / LD LX,A +DD 70 dd * LD (IX+dd),B +DD 71 dd * LD (IX+dd),C +DD 72 dd * LD (IX+dd),D +DD 73 dd * LD (IX+dd),E +DD 74 dd * LD (IX+dd),H +DD 75 dd * LD (IX+dd),L +DD 77 dd * LD (IX+dd),A +DD 7C / LD A,HX +DD 7D / LD A,LX +DD 7E dd * LD A,(IX+dd) +DD 84 / ADD A,HX +DD 85 / ADD A,LX +DD 86 dd * ADD A,(IX+dd) /* add +dd, kpb */ +DD 8C / ADC A,HX +DD 8D / ADC A,LX +DD 8E dd * ADC A,(IX+dd) /* add +dd, kpb */ +DD 94 / SUB HX +DD 95 / SUB LX +DD 96 dd * SUB (IX+dd) +DD 9C / SBC A,HX +DD 9D / SBC A,LX +DD 9E dd * SBC A,(IX+dd) +DD A4 / AND HX +DD A5 / AND LX +DD A6 dd * AND (IX+dd) +DD AC / XOR HX +DD AD / XOR LX +DD AE dd * XOR (IX+dd) +DD B4 / OR HX +DD B5 / OR LX +DD B6 dd * OR (IX+dd) +DD BC / CP HX +DD BD / CP LX +DD BE dd * CP (IX+dd) +DD CB dd 00 / RLC (IX+dd)->B result is placed in a register +DD CB dd 01 / RLC (IX+dd)->C additionally +DD CB dd 02 / RLC (IX+dd)->D +DD CB dd 03 / RLC (IX+dd)->E +DD CB dd 04 / RLC (IX+dd)->H +DD CB dd 05 / RLC (IX+dd)->L +DD CB dd 06 * RLC (IX+dd) +DD CB dd 07 / RLC (IX+dd)->A +DD CB dd 08 / RRC (IX+dd)->B +DD CB dd 09 / RRC (IX+dd)->C +DD CB dd 0A / RRC (IX+dd)->D +DD CB dd 0B / RRC (IX+dd)->E +DD CB dd 0C / RRC (IX+dd)->H +DD CB dd 0D / RRC (IX+dd)->L +DD CB dd 0E * RRC (IX+dd) +DD CB dd 0F / RRC (IX+dd)->A +DD CB dd 10 / RL (IX+dd)->B +DD CB dd 11 / RL (IX+dd)->C +DD CB dd 12 / RL (IX+dd)->D +DD CB dd 13 / RL (IX+dd)->E +DD CB dd 14 / RL (IX+dd)->H +DD CB dd 15 / RL (IX+dd)->L +DD CB dd 16 * RL (IX+dd) +DD CB dd 17 / RL (IX+dd)->A +DD CB dd 18 / RR (IX+dd)->B +DD CB dd 19 / RR (IX+dd)->C +DD CB dd 1A / RR (IX+dd)->D +DD CB dd 1B / RR (IX+dd)->E +DD CB dd 1C / RR (IX+dd)->H +DD CB dd 1D / RR (IX+dd)->L +DD CB dd 1E * RR (IX+dd) +DD CB dd 1F / RR (IX+dd)->A +DD CB dd 20 / SLA (IX+dd)->B +DD CB dd 21 / SLA (IX+dd)->C +DD CB dd 22 / SLA (IX+dd)->D +DD CB dd 23 / SLA (IX+dd)->E +DD CB dd 24 / SLA (IX+dd)->H +DD CB dd 25 / SLA (IX+dd)->L +DD CB dd 26 * SLA (IX+dd) +DD CB dd 27 / SLA (IX+dd)->A +DD CB dd 28 / SRA (IX+dd)->B +DD CB dd 29 / SRA (IX+dd)->C +DD CB dd 2A / SRA (IX+dd)->D +DD CB dd 2B / SRA (IX+dd)->E +DD CB dd 2C / SRA (IX+dd)->H +DD CB dd 2D / SRA (IX+dd)->L +DD CB dd 2E * SRA (IX+dd) +DD CB dd 2F / SRA (IX+dd)->A +DD CB dd 30 / SLIA (IX+dd)->B +DD CB dd 31 / SLIA (IX+dd)->C +DD CB dd 32 / SLIA (IX+dd)->D +DD CB dd 33 / SLIA (IX+dd)->E +DD CB dd 34 / SLIA (IX+dd)->H +DD CB dd 35 / SLIA (IX+dd)->L +DD CB dd 36 / SLIA (IX+dd) +DD CB dd 37 / SLIA (IX+dd)->A +DD CB dd 38 / SRL (IX+dd)->B +DD CB dd 39 / SRL (IX+dd)->C +DD CB dd 3A / SRL (IX+dd)->D +DD CB dd 3B / SRL (IX+dd)->E +DD CB dd 3C / SRL (IX+dd)->H +DD CB dd 3D / SRL (IX+dd)->L +DD CB dd 3E * SRL (IX+dd) +DD CB dd 3F / SRL (IX+dd)->A +DD CB dd 46 * BIT 0,(IX+dd) all other BIT combinations +DD CB dd 4E * BIT 1,(IX+dd) react like the documented ones +DD CB dd 56 * BIT 2,(IX+dd) because there is no write +DD CB dd 5E * BIT 3,(IX+dd) +DD CB dd 66 * BIT 4,(IX+dd) +DD CB dd 6E * BIT 5,(IX+dd) +DD CB dd 76 * BIT 6,(IX+dd) +DD CB dd 7E * BIT 7,(IX+dd) +DD CB dd 80 / RES 0,(IX+dd)->B +DD CB dd 81 / RES 0,(IX+dd)->C +DD CB dd 82 / RES 0,(IX+dd)->D +DD CB dd 83 / RES 0,(IX+dd)->E +DD CB dd 84 / RES 0,(IX+dd)->H +DD CB dd 85 / RES 0,(IX+dd)->L +DD CB dd 86 * RES 0,(IX+dd) +DD CB dd 87 / RES 0,(IX+dd)->A +DD CB dd 88 / RES 1,(IX+dd)->B +DD CB dd 89 / RES 1,(IX+dd)->C +DD CB dd 8A / RES 1,(IX+dd)->D +DD CB dd 8B / RES 1,(IX+dd)->E +DD CB dd 8C / RES 1,(IX+dd)->H +DD CB dd 8D / RES 1,(IX+dd)->L +DD CB dd 8E * RES 1,(IX+dd) +DD CB dd 8F / RES 1,(IX+dd)->A +DD CB dd 90 / RES 2,(IX+dd)->B +DD CB dd 91 / RES 2,(IX+dd)->C +DD CB dd 92 / RES 2,(IX+dd)->D +DD CB dd 93 / RES 2,(IX+dd)->E +DD CB dd 94 / RES 2,(IX+dd)->H +DD CB dd 95 / RES 2,(IX+dd)->L +DD CB dd 96 * RES 2,(IX+dd) +DD CB dd 97 / RES 2,(IX+dd)->A +DD CB dd 98 / RES 3,(IX+dd)->B +DD CB dd 99 / RES 3,(IX+dd)->C +DD CB dd 9A / RES 3,(IX+dd)->D +DD CB dd 9B / RES 3,(IX+dd)->E +DD CB dd 9C / RES 3,(IX+dd)->H +DD CB dd 9D / RES 3,(IX+dd)->L +DD CB dd 9E * RES 3,(IX+dd) +DD CB dd 9F / RES 3,(IX+dd)->A +DD CB dd A0 / RES 4,(IX+dd)->B +DD CB dd A1 / RES 4,(IX+dd)->C +DD CB dd A2 / RES 4,(IX+dd)->D +DD CB dd A3 / RES 4,(IX+dd)->E +DD CB dd A4 / RES 4,(IX+dd)->H +DD CB dd A5 / RES 4,(IX+dd)->L +DD CB dd A6 * RES 4,(IX+dd) +DD CB dd A7 / RES 4,(IX+dd)->A +DD CB dd A8 / RES 5,(IX+dd)->B +DD CB dd A9 / RES 5,(IX+dd)->C +DD CB dd AA / RES 5,(IX+dd)->D +DD CB dd AB / RES 5,(IX+dd)->E +DD CB dd AC / RES 5,(IX+dd)->H +DD CB dd AD / RES 5,(IX+dd)->L +DD CB dd AE * RES 5,(IX+dd) +DD CB dd AF / RES 5,(IX+dd)->A +DD CB dd B0 / RES 6,(IX+dd)->B +DD CB dd B1 / RES 6,(IX+dd)->C +DD CB dd B2 / RES 6,(IX+dd)->D +DD CB dd B3 / RES 6,(IX+dd)->E +DD CB dd B4 / RES 6,(IX+dd)->H +DD CB dd B5 / RES 6,(IX+dd)->L +DD CB dd B6 * RES 6,(IX+dd) +DD CB dd B7 / RES 6,(IX+dd)->A +DD CB dd B8 / RES 7,(IX+dd)->B +DD CB dd B9 / RES 7,(IX+dd)->C +DD CB dd BA / RES 7,(IX+dd)->D +DD CB dd BB / RES 7,(IX+dd)->E +DD CB dd BC / RES 7,(IX+dd)->H +DD CB dd BD / RES 7,(IX+dd)->L +DD CB dd BE * RES 7,(IX+dd) +DD CB dd BF / RES 7,(IX+dd)->A +DD CB dd C0 / SET 0,(IX+dd)->B +DD CB dd C1 / SET 0,(IX+dd)->C +DD CB dd C2 / SET 0,(IX+dd)->D +DD CB dd C3 / SET 0,(IX+dd)->E +DD CB dd C4 / SET 0,(IX+dd)->H +DD CB dd C5 / SET 0,(IX+dd)->L +DD CB dd C6 * SET 0,(IX+dd) +DD CB dd C7 / SET 0,(IX+dd)->A +DD CB dd C8 / SET 1,(IX+dd)->B +DD CB dd C9 / SET 1,(IX+dd)->C +DD CB dd CA / SET 1,(IX+dd)->D +DD CB dd CB / SET 1,(IX+dd)->E +DD CB dd CC / SET 1,(IX+dd)->H +DD CB dd CD / SET 1,(IX+dd)->L +DD CB dd CE * SET 1,(IX+dd) +DD CB dd CF / SET 1,(IX+dd)->A +DD CB dd D0 / SET 2,(IX+dd)->B +DD CB dd D1 / SET 2,(IX+dd)->C +DD CB dd D2 / SET 2,(IX+dd)->D +DD CB dd D3 / SET 2,(IX+dd)->E +DD CB dd D4 / SET 2,(IX+dd)->H +DD CB dd D5 / SET 2,(IX+dd)->L +DD CB dd D6 * SET 2,(IX+dd) +DD CB dd D7 / SET 2,(IX+dd)->A +DD CB dd D8 / SET 3,(IX+dd)->B +DD CB dd D9 / SET 3,(IX+dd)->C +DD CB dd DA / SET 3,(IX+dd)->D +DD CB dd DB / SET 3,(IX+dd)->E +DD CB dd DC / SET 3,(IX+dd)->H +DD CB dd DD / SET 3,(IX+dd)->L +DD CB dd DE * SET 3,(IX+dd) +DD CB dd DF / SET 3,(IX+dd)->A +DD CB dd E0 / SET 4,(IX+dd)->B +DD CB dd E1 / SET 4,(IX+dd)->C +DD CB dd E2 / SET 4,(IX+dd)->D +DD CB dd E3 / SET 4,(IX+dd)->E +DD CB dd E4 / SET 4,(IX+dd)->H +DD CB dd E5 / SET 4,(IX+dd)->L +DD CB dd E6 * SET 4,(IX+dd) +DD CB dd E7 / SET 4,(IX+dd)->A +DD CB dd E8 / SET 5,(IX+dd)->B +DD CB dd E9 / SET 5,(IX+dd)->C +DD CB dd EA / SET 5,(IX+dd)->D +DD CB dd EB / SET 5,(IX+dd)->E +DD CB dd EC / SET 5,(IX+dd)->H +DD CB dd ED / SET 5,(IX+dd)->L +DD CB dd EE * SET 5,(IX+dd) +DD CB dd EF / SET 5,(IX+dd)->A +DD CB dd F0 / SET 6,(IX+dd)->B +DD CB dd F1 / SET 6,(IX+dd)->C +DD CB dd F2 / SET 6,(IX+dd)->D +DD CB dd F3 / SET 6,(IX+dd)->E +DD CB dd F4 / SET 6,(IX+dd)->H +DD CB dd F5 / SET 6,(IX+dd)->L +DD CB dd F6 * SET 6,(IX+dd) +DD CB dd F7 / SET 6,(IX+dd)->A +DD CB dd F8 / SET 7,(IX+dd)->B +DD CB dd F9 / SET 7,(IX+dd)->C +DD CB dd FA / SET 7,(IX+dd)->D +DD CB dd FB / SET 7,(IX+dd)->E +DD CB dd FC / SET 7,(IX+dd)->H +DD CB dd FD / SET 7,(IX+dd)->L +DD CB dd FE * SET 7,(IX+dd) +DD CB dd FF / SET 7,(IX+dd)->A +DD E1 * POP IX +DD E3 * EX (SP),IX +DD E5 * PUSH IX +DD E9 * JP (IX) +DD F9 * LD SP,IX +DE nn SBC A,nn +DF RST 18H +E0 RET PO +E1 POP HL +E2 nnnn JP PO,nnnn +E3 EX (SP),HL +E4 nnnn CALL PO,nnnn +E5 PUSH HL +E6 nn AND nn +E7 RST 20H +E8 RET PE +E9 JP (HL) +EA nnnn JP PE,nnnn +EB EX DE,HL +EC nnnn CALL PE,nnnn +All other ED combinations not listed below: + in the range ED40 - ED7F: valid opcodes are mirrored + elsewhere: ED and the next byte is ignored, + all following bytes treated as instructions +ED 00 nn + IN0 B,(nn) +ED 01 nn + OUT0 (nn),B +ED 04 + TST B +ED 08 nn + IN0 C,(nn) +ED 09 nn + OUT0 (nn),C +ED 0C + TST C +ED 10 nn + IN0 D,(nn) +ED 11 nn + OUT0 (nn),D +ED 14 + TST D +ED 18 nn + IN0 E,(nn) +ED 19 nn + OUT0 (nn),E +ED 1C + TST E +ED 20 nn + IN0 H,(nn) +ED 21 nn + OUT0 (nn),H +ED 24 + TST H +ED 28 nn + IN0 L,(nn) +ED 29 nn + OUT0 (nn),L +ED 2C + TST L +ED 30 nn + IN0 (nn) set flags only +ED 34 + TST (HL) +ED 38 nn + IN0 A,(nn) +ED 39 nn + OUT0 (nn),A +ED 3C + TST A +ED 40 * IN B,(C) +ED 41 * OUT (C),B +ED 42 * SBC HL,BC +ED 43 nnnn * LD (nnnn),BC +ED 44 * NEG +ED 45 * RETN +ED 46 * IM 0 +ED 47 * LD I,A +ED 48 * IN C,(C) +ED 49 * OUT (C),C +ED 4A * ADC HL,BC +ED 4B nnnn * LD BC,(nnnn) +ED 4C + MULT BC +ED 4D * RETI +ED 4F * LD R,A +ED 50 * IN D,(C) +ED 51 * OUT (C),D +ED 52 * SBC HL,DE +ED 53 nnnn * LD (nnnn),DE +ED 56 * IM 1 +ED 57 * LD A,I +ED 58 * IN E,(C) +ED 59 * OUT (C),E +ED 5A * ADC HL,DE +ED 5B nnnn * LD DE,(nnnn) +ED 5C + MULT DE +ED 5E * IM 2 +ED 5F * LD A,R +ED 60 * IN H,(C) +ED 61 * OUT (C),H +ED 62 * SBC HL,HL +ED 63 nnnn * LD (nnnn),HL opcode 22 does the same faster +ED 64 nn + TST nn +ED 67 * RRD +ED 68 * IN L,(C) +ED 69 * OUT (C),L +ED 6A * ADC HL,HL +ED 6B nnnn * LD HL,(nnnn) opcode 2A does the same faster +ED 6C + MULT HL +ED 6F * RLD +ED 70 / IN (C) set flags only (TSTI) + ^--- can be viewed as *, because SGS manual and HD64180 + manual list this instruction as valid Z80 +ED 71 / OUT (C),0 +ED 72 * SBC HL,SP +ED 73 nnnn * LD (nnnn),SP +ED 74 nn + TSTIO nn +ED 76 + SLP +ED 78 * IN A,(C) +ED 79 * OUT (C),A +ED 7A * ADC HL,SP +ED 7B nnnn * LD SP,(nnnn) +ED 7C + MULT SP +ED 83 + OTIM +ED 8B + OTDM +ED 93 + OTIMR +ED 9B + OTDMR +ED A0 * LDI +ED A1 * CPI +ED A2 * INI +ED A3 * OUTI +ED A8 * LDD +ED A9 * CPD +ED AA * IND +ED AB * OUTD +ED B0 * LDIR +ED B1 * CPIR +ED B2 * INIR +ED B3 * OTIR +ED B8 * LDDR +ED B9 * CPDR +ED BA * INDR +ED BB * OTDR +EE nn XOR nn +EF RST 28H +F0 RET P +F1 POP AF +F2 nnnn JP P,nnnn +F3 DI +F4 nnnn CALL P,nnnn +F5 PUSH AF +F6 nn OR nn +F7 RST 30H +F8 RET M +F9 LD SP,HL +FA nnnn JP M,nnnn +FB EI +FC nnnn CALL M,nnnn +FD ... * like DD ..., with IY instead of IX +FE nn CP nn +FF RST 38H + + +From: peterm@maths.grace.cri.nz (Peter McGavin) +Newsgroups: comp.sys.sinclair +Subject: Re: Undocumented Z80 opcodes +Date: 05 Jan 1994 20:44:15 GMT +Organization: Applied Maths, Industrial Research Ltd, NZ +NNTP-Posting-Host: kea.grace.cri.nz +In-reply-to: agulbra@tigern.nvg.unit.no's message of 5 Jan 1994 17:47:59 +0100 + +In article, <2geqvv$nlq@tigern.nvg.unit.no>, +agulbra@tigern.nvg.unit.no (Arnt Gulbrandsen) wrote: +>I believe that list originally was written by from David Librik +><librik@cory.eecs.berkeley.edu>. David (with someone else, I think) +>reverse-engineered the Z80 and wrote a list of what he found, a list +>which I think I sent to Peter. + +Actually I got it from Simon Owen (S.N.Owen@newcastle.ac.uk). + +Here it is: (sorry it's a bit wide) +------------------------------------------------------------------------------ + +Key: + + Instruction is unchanged by index prefix + * Instruction thought of as 'undocumented' + +Notes: + + IM * - is either IM 0 or IM 1 (more likely IM 0), hard to decide which + + IN X,(C) reads into nowhere (not even (HL)) but affects the flags. + OUT (C),X performs OUT (C),0 + + *NOP indicated instruction has no effect on anything [ 2M cycles delay ? ] + + instructions with an ED prefix cannot have a preceding DD prefix as well. + + Instructions like LD B,RL (IX+d) perform RL (IX+d) and load B with the result + AS WELL AS affecting the contents of (IX+d). 2 for price of 1 ! + +List: + ++-------------------------------+-------------------+------------------+------------------+-------------------------+ +| Hex | Dec | Normal | DD Prefix | CB Prefix | ED Prefix | DDCB prefix | ++-------------------------------+-------------------+------------------+------------------+-------------------------+ +|[ 00 | 000 ] | NOP | +NOP | RLC B | *NOP | *LD B,RLC (IX+d) | +|[ 01 | 001 ] | LD BC,nn | +LD BC,nn | RLC C | *NOP | *LD C,RLC (IX+d) | +|[ 02 | 002 ] | LD (BC),A | +LD (BC),A | RLC D | *NOP | *LD D,RLC (IX+d) | +|[ 03 | 003 ] | INC BC | +INC BC | RLC E | *NOP | *LD E,RLC (IX+d) | +|[ 04 | 004 ] | INC B | +INC B | RLC H | *NOP | *LD H,RLC (IX+d) | +|[ 05 | 005 ] | DEC B | +DEC B | RLC L | *NOP | *LD L,RLC (IX+d) | +|[ 06 | 006 ] | LD B,n | +LD B,n | RLC (HL) | *NOP | RLC (IX+d) | +|[ 07 | 007 ] | RLCA | +RLCA | RLC A | *NOP | *LD A,RLC (IX+d) | +|[ 08 | 008 ] | EX AF,AF' | +EX AF,AF' | RRC B | *NOP | *LD B,RRC (IX+d) | +|[ 09 | 009 ] | ADD HL,BC | ADD IX,BC | RRC C | *NOP | *LD C,RRC (IX+d) | +|[ 0a | 010 ] | LD A,(BC) | +LD A,(BC) | RRC D | *NOP | *LD D,RRC (IX+d) | +|[ 0b | 011 ] | DEC BC | +DEC BC | RRC E | *NOP | *LD E,RRC (IX+d) | +|[ 0c | 012 ] | INC C | +INC C | RRC H | *NOP | *LD H,RRC (IX+d) | +|[ 0d | 013 ] | DEC C | +DEC C | RRC L | *NOP | *LD L,RRC (IX+d) | +|[ 0e | 014 ] | LD C,n | +LD C,n | RRC (HL) | *NOP | RRC (IX+d) | +|[ 0f | 015 ] | RRCA | +RRCA | RRC A | *NOP | *LD A,RRC (IX+d) | +|[ 10 | 016 ] | DJNZ d | +DJNZ d | RL B | *NOP | *LD B,RL (IX+d) | +|[ 11 | 017 ] | LD DE,nn | +LD DE,nn | RL C | *NOP | *LD C,RL (IX+d) | +|[ 12 | 018 ] | LD (DE),A | +LD (DE),A | RL D | *NOP | *LD D,RL (IX+d) | +|[ 13 | 019 ] | INC DE | +INC DE | RL E | *NOP | *LD E,RL (IX+d) | +|[ 14 | 020 ] | INC D | +INC D | RL H | *NOP | *LD H,RL (IX+d) | +|[ 15 | 021 ] | DEC D | +DEC D | RL L | *NOP | *LD L,RL (IX+d) | +|[ 16 | 022 ] | LD D,n | +LD D,n | RL (HL) | *NOP | RL (IX+d) | +|[ 17 | 023 ] | RLA | +RLA | RL A | *NOP | *LD A,RL (IX+d) | +|[ 18 | 024 ] | JR d | +JR d | RR B | *NOP | *LD B,RR (IX+d) | +|[ 19 | 025 ] | ADD HL,DE | ADD IX,DE | RR C | *NOP | *LD C,RR (IX+d) | +|[ 1a | 026 ] | LD A,(DE) | +LD A,(DE) | RR D | *NOP | *LD D,RR (IX+d) | +|[ 1b | 027 ] | DEC DE | +DEC DE | RR E | *NOP | *LD E,RR (IX+d) | +|[ 1c | 028 ] | INC E | +INC E | RR H | *NOP | *LD H,RR (IX+d) | +|[ 1d | 029 ] | DEC E | +DEC E | RR L | *NOP | *LD L,RR (IX+d) | +|[ 1e | 030 ] | LD E,n | +LD E,n | RR (HL) | *NOP | RR (IX+d) | +|[ 1f | 031 ] | RRA | +RRA | RR A | *NOP | *LD A,RR (IX+d) | +|[ 20 | 032 ] | JR NZ,d | +JR NZ,d | SLA B | *NOP | *LD B,SLA (IX+d) | +|[ 21 | 033 ] | LD HL,nn | LD IX,nn | SLA C | *NOP | *LD C,SLA (IX+d) | +|[ 22 | 034 ] | LD (nn),HL | LD (nn),IX | SLA D | *NOP | *LD D,SLA (IX+d) | +|[ 23 | 035 ] | INC HL | INC IX | SLA E | *NOP | *LD E,SLA (IX+d) | +|[ 24 | 036 ] | INC H | *INC IXh | SLA H | *NOP | *LD H,SLA (IX+d) | +|[ 25 | 037 ] | DEC H | *DEC IXh | SLA L | *NOP | *LD L,SLA (IX+d) | +|[ 26 | 038 ] | LD H,n | *LD IXh,n | SLA (HL) | *NOP | SLA (IX+d) | +|[ 27 | 039 ] | DAA | +DAA | SLA A | *NOP | *LD A,SLA (IX+d) | +|[ 28 | 040 ] | JR Z,d | +JR Z,d | SRA B | *NOP | *LD B,SRA (IX+d) | +|[ 29 | 041 ] | ADD HL,HL | ADD IX,IX | SRA C | *NOP | *LD C,SRA (IX+d) | +|[ 2a | 042 ] | LD HL,(nn) | LD IX,(nn) | SRA D | *NOP | *LD D,SRA (IX+d) | +|[ 2b | 043 ] | DEC HL | DEC IX | SRA E | *NOP | *LD E,SRA (IX+d) | +|[ 2c | 044 ] | INC L | *INC IXl | SRA H | *NOP | *LD H,SRA (IX+d) | +|[ 2d | 045 ] | DEC L | *DEC IXl | SRA L | *NOP | *LD L,SRA (IX+d) | +|[ 2e | 046 ] | LD L,n | *LD IXl,n | SRA (HL) | *NOP | SRA (IX+d) | +|[ 2f | 047 ] | CPL | +CPL | SRA A | *NOP | *LD A,SRA (IX+d) | +|[ 30 | 048 ] | JR NC,d | +JR NC,d | SLL B | *NOP | *LD B,SLL (IX+d) | +|[ 31 | 049 ] | LD SP,nn | +LD SP,nn | SLL C | *NOP | *LD C,SLL (IX+d) | +|[ 32 | 050 ] | LD (nn),A | +LD (nn),A | SLL D | *NOP | *LD D,SLL (IX+d) | +|[ 33 | 051 ] | INC SP | +INC SP | SLL E | *NOP | *LD E,SLL (IX+d) | +|[ 34 | 052 ] | INC (HL) | INC (IX+d) | SLL H | *NOP | *LD H,SLL (IX+d) | +|[ 35 | 053 ] | DEC (HL) | DEC (IX+d) | SLL L | *NOP | *LD L,SLL (IX+d) | +|[ 36 | 054 ] | LD (HL),n | LD (IX+d),n | SLL (HL) | *NOP | SLL (IX+d) | +|[ 37 | 055 ] | SCF | +SCF | SLL A | *NOP | *LD A,SLL (IX+d) | +|[ 38 | 056 ] | JR C,d | +JR C,d | SRL B | *NOP | *LD B,SRL (IX+d) | +|[ 39 | 057 ] | ADD HL,SP | ADD IX,SP | SRL C | *NOP | *LD C,SRL (IX+d) | +|[ 3a | 058 ] | LD A,(nn) | +LD A,(nn) | SRL D | *NOP | *LD D,SRL (IX+d) | +|[ 3b | 059 ] | DEC SP | +DEC SP | SRL E | *NOP | *LD E,SRL (IX+d) | +|[ 3c | 060 ] | INC A | +INC A | SRL H | *NOP | *LD H,SRL (IX+d) | +|[ 3d | 061 ] | DEC A | +DEC A | SRL L | *NOP | *LD L,SRL (IX+d) | +|[ 3e | 062 ] | LD A,n | +LD A,n | SRL (HL) | *NOP | SRL (IX+d) | +|[ 3f | 063 ] | CCF | +CCF | SRL A | *NOP | *LD A,SRL (IX+d) | +|[ 40 | 064 ] | LD B,B | +LD B,B | BIT 0,B | IN B,(C) | *BIT 0,(IX+d) | +|[ 41 | 065 ] | LD B,C | +LD B,C | BIT 0,C | OUT (C),B | *BIT 0,(IX+d) | +|[ 42 | 066 ] | LD B,D | +LD B,D | BIT 0,D | SBC HL,BC | *BIT 0,(IX+d) | +|[ 43 | 067 ] | LD B,E | +LD B,E | BIT 0,E | LD (nn),BC | *BIT 0,(IX+d) | +|[ 44 | 068 ] | LD B,H | *LD B,IXh | BIT 0,H | NEG | *BIT 0,(IX+d) | +|[ 45 | 069 ] | LD B,L | *LD B,IXl | BIT 0,L | RETN | *BIT 0,(IX+d) | +|[ 46 | 070 ] | LD B,(HL) | LD B,(IX+d) | BIT 0,(HL) | IM 0 | BIT 0,(IX+d) | +|[ 47 | 071 ] | LD B,A | +LD B,A | BIT 0,A | LD I,A | *BIT 0,(IX+d) | +|[ 48 | 072 ] | LD C,B | +LD C,B | BIT 1,B | IN C,(C) | *BIT 1,(IX+d) | +|[ 49 | 073 ] | LD C,C | +LD C,C | BIT 1,C | OUT (C),C | *BIT 1,(IX+d) | +|[ 4a | 074 ] | LD C,D | +LD C,D | BIT 1,D | ADC HL,BC | *BIT 1,(IX+d) | +|[ 4b | 075 ] | LD C,E | +LD C,E | BIT 1,E | LD BC,(nn) | *BIT 1,(IX+d) | +|[ 4c | 076 ] | LD C,H | *LD C,IXh | BIT 1,H | *NEG | *BIT 1,(IX+d) | +|[ 4d | 077 ] | LD C,L | *LD C,IXl | BIT 1,L | RETI | *BIT 1,(IX+d) | +|[ 4e | 078 ] | LD C,(HL) | LD C,(IX+d) | BIT 1,(HL) | *IM * (0?) | BIT 1,(IX+d) | +|[ 4f | 079 ] | LD C,A | +LD C,A | BIT 1,A | LD R,A | *BIT 1,(IX+d) | +|[ 50 | 080 ] | LD D,B | +LD D,B | BIT 2,B | IN D,(C) | *BIT 2,(IX+d) | +|[ 51 | 081 ] | LD D,C | +LD D,C | BIT 2,C | OUT (C),D | *BIT 2,(IX+d) | +|[ 52 | 082 ] | LD D,D | +LD D,D | BIT 2,D | SBC HL,DE | *BIT 2,(IX+d) | +|[ 53 | 083 ] | LD D,E | +LD D,E | BIT 2,E | LD (nn),DE | *BIT 2,(IX+d) | +|[ 54 | 084 ] | LD D,H | *LD D,IXh | BIT 2,H | *NEG | *BIT 2,(IX+d) | +|[ 55 | 085 ] | LD D,L | *LD D,IXl | BIT 2,L | *RETN | *BIT 2,(IX+d) | +|[ 56 | 086 ] | LD D,(HL) | LD D,(IX+d) | BIT 2,(HL) | IM 1 | BIT 2,(IX+d) | +|[ 57 | 087 ] | LD D,A | +LD D,A | BIT 2,A | LD A,I | *BIT 2,(IX+d) | +|[ 58 | 088 ] | LD E,B | +LD E,B | BIT 3,B | IN E,(C) | *BIT 3,(IX+d) | +|[ 59 | 089 ] | LD E,C | +LD E,C | BIT 3,C | OUT (C),E | *BIT 3,(IX+d) | +|[ 5a | 090 ] | LD E,D | +LD E,D | BIT 3,D | ADC HL,DE | *BIT 3,(IX+d) | +|[ 5b | 091 ] | LD E,E | +LD E,E | BIT 3,E | LD DE,(nn) | *BIT 3,(IX+d) | +|[ 5c | 092 ] | LD E,H | *LD E,IXh | BIT 3,H | *NEG | *BIT 3,(IX+d) | +|[ 5d | 093 ] | LD E,L | *LD E,IXl | BIT 3,L | *RETI | *BIT 3,(IX+d) | +|[ 5e | 094 ] | LD E,(HL) | LD E,(IX+d) | BIT 3,(HL) | IM 2 | BIT 3,(IX+d) | +|[ 5f | 095 ] | LD E,A | +LD E,A | BIT 3,A | LD A,R | *BIT 3,(IX+d) | +|[ 60 | 096 ] | LD H,B | *LD IXh,B | BIT 4,B | IN H,(C) | *BIT 4,(IX+d) | +|[ 61 | 097 ] | LD H,C | *LD IXh,C | BIT 4,C | OUT (C),H | *BIT 4,(IX+d) | +|[ 62 | 098 ] | LD H,D | *LD IXh,D | BIT 4,D | SBC HL,HL | *BIT 4,(IX+d) | +|[ 63 | 099 ] | LD H,E | *LD IXh,E | BIT 4,E | LD (nn),HL | *BIT 4,(IX+d) | +|[ 64 | 100 ] | LD H,H | *LD IXh,IXh | BIT 4,H | *NEG | *BIT 4,(IX+d) | +|[ 65 | 101 ] | LD H,L | *LD IXh,IXl | BIT 4,L | *RETN | *BIT 4,(IX+d) | +|[ 66 | 102 ] | LD H,(HL) | LD H,(IX+d) | BIT 4,(HL) | *IM 0 | BIT 4,(IX+d) | +|[ 67 | 103 ] | LD H,A | *LD IXh,A | BIT 4,A | RRD | *BIT 4,(IX+d) | +|[ 68 | 104 ] | LD L,B | *LD IXl,B | BIT 5,B | IN L,(C) | *BIT 5,(IX+d) | +|[ 69 | 105 ] | LD L,C | *LD IXl,C | BIT 5,C | OUT (C),L | *BIT 5,(IX+d) | +|[ 6a | 106 ] | LD L,D | *LD IXl,D | BIT 5,D | ADC HL,HL | *BIT 5,(IX+d) | +|[ 6b | 107 ] | LD L,E | *LD IXl,E | BIT 5,E | LD HL,(nn) | *BIT 5,(IX+d) | +|[ 6c | 108 ] | LD L,H | *LD IXl,IXh | BIT 5,H | *NEG | *BIT 5,(IX+d) | +|[ 6d | 109 ] | LD L,L | *LD IXl,IXl | BIT 5,L | *RETI | *BIT 5,(IX+d) | +|[ 6e | 110 ] | LD L,(HL) | LD L,(IX+d) | BIT 5,(HL) | *IM * (0?) | BIT 5,(IX+d) | +|[ 6f | 111 ] | LD L,A | *LD IXl,A | BIT 5,A | RLD | *BIT 5,(IX+d) | +|[ 70 | 112 ] | LD (HL),B | LD (IX+d),B | BIT 6,B | *IN X,(C) | *BIT 6,(IX+d) | +|[ 71 | 113 ] | LD (HL),C | LD (IX+d),C | BIT 6,C | *OUT (C),X(0)| *BIT 6,(IX+d) | +|[ 72 | 114 ] | LD (HL),D | LD (IX+d),D | BIT 6,D | SBC HL,SP | *BIT 6,(IX+d) | +|[ 73 | 115 ] | LD (HL),E | LD (IX+d),E | BIT 6,E | LD (nn),SP | *BIT 6,(IX+d) | +|[ 74 | 116 ] | LD (HL),H | LD (IX+d),H | BIT 6,H | *NEG | *BIT 6,(IX+d) | +|[ 75 | 117 ] | LD (HL),L | LD (IX+d),L | BIT 6,L | *RETN | *BIT 6,(IX+d) | +|[ 76 | 118 ] | HALT | +HALT | BIT 6,(HL) | *IM 1 | BIT 6,(IX+d) | +|[ 77 | 119 ] | LD (HL),A | LD (IX+d),A | BIT 6,A | *NOP | *BIT 6,(IX+d) | +|[ 78 | 120 ] | LD A,B | +LD A,B | BIT 7,B | IN A,(C) | *BIT 7,(IX+d) | +|[ 79 | 121 ] | LD A,C | +LD A,C | BIT 7,C | OUT (C),A | *BIT 7,(IX+d) | +|[ 7a | 122 ] | LD A,D | +LD A,D | BIT 7,D | ADC HL,SP | *BIT 7,(IX+d) | +|[ 7b | 123 ] | LD A,E | +LD A,E | BIT 7,E | LD SP,(nn) | *BIT 7,(IX+d) | +|[ 7c | 124 ] | LD A,H | *LD A,IXh | BIT 7,H | *NEG | *BIT 7,(IX+d) | +|[ 7d | 125 ] | LD A,L | *LD A,IXl | BIT 7,L | *RETI | *BIT 7,(IX+d) | +|[ 7e | 126 ] | LD A,(HL) | LD A,(IX+d) | BIT 7,(HL) | *IM 2 | BIT 7,(IX+d) | +|[ 7f | 127 ] | LD A,A | +LD A,A | BIT 7,A | *NOP | *BIT 7,(IX+d) | +|[ 80 | 128 ] | ADD A,B | +ADD A,B | RES 0,B | *NOP | *LD B,RES 0,(IX+d) | +|[ 81 | 129 ] | ADD A,C | +ADD A,C | RES 0,C | *NOP | *LD C,RES 0,(IX+d) | +|[ 82 | 130 ] | ADD A,D | +ADD A,D | RES 0,D | *NOP | *LD D,RES 0,(IX+d) | +|[ 83 | 131 ] | ADD A,E | +ADD A,E | RES 0,E | *NOP | *LD E,RES 0,(IX+d) | +|[ 84 | 132 ] | ADD A,H | *ADD A,IXh | RES 0,H | *NOP | *LD H,RES 0,(IX+d) | +|[ 85 | 133 ] | ADD A,L | *ADD A,IXl | RES 0,L | *NOP | *LD L,RES 0,(IX+d) | +|[ 86 | 134 ] | ADD A,(HL) | ADD A,(IX+d) | RES 0,(HL) | *NOP | RES 0,(IX+d) | +|[ 87 | 135 ] | ADD A,A | +ADD A,A | RES 0,A | *NOP | *LD A,RES 0,(IX+d) | +|[ 88 | 136 ] | ADC A,B | +ADC A,B | RES 1,B | *NOP | *LD B,RES 1,(IX+d) | +|[ 89 | 137 ] | ADC A,C | +ADC A,C | RES 1,C | *NOP | *LD C,RES 1,(IX+d) | +|[ 8a | 138 ] | ADC A,D | +ADC A,D | RES 1,D | *NOP | *LD D,RES 1,(IX+d) | +|[ 8b | 139 ] | ADC A,E | +ADC A,E | RES 1,E | *NOP | *LD E,RES 1,(IX+d) | +|[ 8c | 140 ] | ADC A,H | *ADC A,IXh | RES 1,H | *NOP | *LD H,RES 1,(IX+d) | +|[ 8d | 141 ] | ADC A,L | *ADC A,IXl | RES 1,L | *NOP | *LD L,RES 1,(IX+d) | +|[ 8e | 142 ] | ADC A,(HL) | ADC A,(IX+d) | RES 1,(HL) | *NOP | RES 1,(IX+d) | +|[ 8f | 143 ] | ADC A,A | +ADC A,A | RES 1,A | *NOP | *LD A,RES 1,(IX+d) | +|[ 90 | 144 ] | SUB B | +SUB B | RES 2,B | *NOP | *LD B,RES 2,(IX+d) | +|[ 91 | 145 ] | SUB C | +SUB C | RES 2,C | *NOP | *LD C,RES 2,(IX+d) | +|[ 92 | 146 ] | SUB D | +SUB D | RES 2,D | *NOP | *LD D,RES 2,(IX+d) | +|[ 93 | 147 ] | SUB E | +SUB E | RES 2,E | *NOP | *LD E,RES 2,(IX+d) | +|[ 94 | 148 ] | SUB H | *SUB IXh | RES 2,H | *NOP | *LD H,RES 2,(IX+d) | +|[ 95 | 149 ] | SUB L | *SUB IXl | RES 2,L | *NOP | *LD L,RES 2,(IX+d) | +|[ 96 | 150 ] | SUB (HL) | SUB (IX+d) | RES 2,(HL) | *NOP | RES 2,(IX+d) | +|[ 97 | 151 ] | SUB A | +SUB A | RES 2,A | *NOP | *LD A,RES 2,(IX+d) | +|[ 98 | 152 ] | SBC A,B | +SBC A,B | RES 3,B | *NOP | *LD B,RES 3,(IX+d) | +|[ 99 | 153 ] | SBC A,C | +SBC A,C | RES 3,C | *NOP | *LD C,RES 3,(IX+d) | +|[ 9a | 154 ] | SBC A,D | +SBC A,D | RES 3,D | *NOP | *LD D,RES 3,(IX+d) | +|[ 9b | 155 ] | SBC A,E | +SBC A,E | RES 3,E | *NOP | *LD E,RES 3,(IX+d) | +|[ 9c | 156 ] | SBC A,H | *SBC A,IXh | RES 3,H | *NOP | *LD H,RES 3,(IX+d) | +|[ 9d | 157 ] | SBC A,L | *SBC A,IXl | RES 3,L | *NOP | *LD L,RES 3,(IX+d) | +|[ 9e | 158 ] | SBC A,(HL) | SBC A,(IX+d) | RES 3,(HL) | *NOP | RES 3,(IX+d) | +|[ 9f | 159 ] | SBC A,A | +SBC A,A | RES 3,A | *NOP | *LD A,RES 3,(IX+d) | +|[ a0 | 160 ] | AND B | +AND B | RES 4,B | LDI | *LD B,RES 4,(IX+d) | +|[ a1 | 161 ] | AND C | +AND C | RES 4,C | CPI | *LD C,RES 4,(IX+d) | +|[ a2 | 162 ] | AND D | +AND D | RES 4,D | INI | *LD D,RES 4,(IX+d) | +|[ a3 | 163 ] | AND E | +AND E | RES 4,E | OUTI | *LD E,RES 4,(IX+d) | +|[ a4 | 164 ] | AND H | *AND IXh | RES 4,H | *NOP | *LD H,RES 4,(IX+d) | +|[ a5 | 165 ] | AND L | *AND IXl | RES 4,L | *NOP | *LD L,RES 4,(IX+d) | +|[ a6 | 166 ] | AND (HL) | AND (IX+d) | RES 4,(HL) | *NOP | RES 4,(IX+d) | +|[ a7 | 167 ] | AND A | +AND A | RES 4,A | *NOP | *LD A,RES 4,(IX+d) | +|[ a8 | 168 ] | XOR B | +XOR B | RES 5,B | LDD | *LD B,RES 5,(IX+d) | +|[ a9 | 169 ] | XOR C | +XOR C | RES 5,C | CPD | *LD C,RES 5,(IX+d) | +|[ aa | 170 ] | XOR D | +XOR D | RES 5,D | IND | *LD D,RES 5,(IX+d) | +|[ ab | 171 ] | XOR E | +XOR E | RES 5,E | OUTD | *LD E,RES 5,(IX+d) | +|[ ac | 172 ] | XOR H | *XOR IXh | RES 5,H | *NOP | *LD H,RES 5,(IX+d) | +|[ ad | 173 ] | XOR L | *XOR IXl | RES 5,L | *NOP | *LD L,RES 5,(IX+d) | +|[ ae | 174 ] | XOR (HL) | XOR (IX+d) | RES 5,(HL) | *NOP | RES 5,(IX+d) | +|[ af | 175 ] | XOR A | +XOR A | RES 5,A | *NOP | *LD A,RES 5,(IX+d) | +|[ b0 | 176 ] | OR B | +OR B | RES 6,B | LDIR | *LD B,RES 6,(IX+d) | +|[ b1 | 177 ] | OR C | +OR C | RES 6,C | CPIR | *LD C,RES 6,(IX+d) | +|[ b2 | 178 ] | OR D | +OR D | RES 6,D | INIR | *LD D,RES 6,(IX+d) | +|[ b3 | 179 ] | OR E | +OR E | RES 6,E | OTIR | *LD E,RES 6,(IX+d) | +|[ b4 | 180 ] | OR H | *OR IXh | RES 6,H | *NOP | *LD H,RES 6,(IX+d) | +|[ b5 | 181 ] | OR L | *OR IXl | RES 6,L | *NOP | *LD L,RES 6,(IX+d) | +|[ b6 | 182 ] | OR (HL) | OR (IX+d) | RES 6,(HL) | *NOP | RES 6,(IX+d) | +|[ b7 | 183 ] | OR A | +OR A | RES 6,A | *NOP | *LD A,RES 6,(IX+d) | +|[ b8 | 184 ] | CP B | +CP B | RES 7,B | LDDR | *LD B,RES 7,(IX+d) | +|[ b9 | 185 ] | CP C | +CP C | RES 7,C | CPDR | *LD C,RES 7,(IX+d) | +|[ ba | 186 ] | CP D | +CP D | RES 7,D | INDR | *LD D,RES 7,(IX+d) | +|[ bb | 187 ] | CP E | +CP E | RES 7,E | OTDR | *LD E,RES 7,(IX+d) | +|[ bc | 188 ] | CP H | *CP IXh | RES 7,H | *NOP | *LD H,RES 7,(IX+d) | +|[ bd | 189 ] | CP L | *CP IXl | RES 7,L | *NOP | *LD L,RES 7,(IX+d) | +|[ be | 190 ] | CP (HL) | CP (IX+d) | RES 7,(HL) | *NOP | RES 7,(IX+d) | +|[ bf | 191 ] | CP A | +CP A | RES 7,A | *NOP | *LD A,RES 7,(IX+d) | +|[ c0 | 192 ] | RET NZ | +RET NZ | SET 0,B | *NOP | *LD B,SET 0,(IX+d) | +|[ c1 | 193 ] | POP BC | +POP BC | SET 0,C | *NOP | *LD C,SET 0,(IX+d) | +|[ c2 | 194 ] | JP NZ,nn | +JP NZ,nn | SET 0,D | *NOP | *LD D,SET 0,(IX+d) | +|[ c3 | 195 ] | JP nn | +JP nn | SET 0,E | *NOP | *LD E,SET 0,(IX+d) | +|[ c4 | 196 ] | CALL NZ,nn | +CALL NZ,nn | SET 0,H | *NOP | *LD H,SET 0,(IX+d) | +|[ c5 | 197 ] | PUSH BC | +PUSH BC | SET 0,L | *NOP | *LD L,SET 0,(IX+d) | +|[ c6 | 198 ] | ADD A,n | +ADD A,n | SET 0,(HL) | *NOP | SET 0,(IX+d) | +|[ c7 | 199 ] | RST 0 | +RST 0 | SET 0,A | *NOP | *LD A,SET 0,(IX+d) | +|[ c8 | 100 ] | RET Z | +RET Z | SET 1,B | *NOP | *LD B,SET 1,(IX+d) | +|[ c9 | 201 ] | RET | +RET | SET 1,C | *NOP | *LD C,SET 1,(IX+d) | +|[ ca | 202 ] | JP Z,nn | +JP Z,nn | SET 1,D | *NOP | *LD D,SET 1,(IX+d) | +|[ cb | 203 ] | [Prefix] | *[See DDCB info]| SET 1,E | *NOP | *LD E,SET 1,(IX+d) | +|[ cc | 204 ] | CALL Z,nn | +CALL Z,nn | SET 1,H | *NOP | *LD H,SET 1,(IX+d) | +|[ cd | 205 ] | CALL nn | +CALL nn | SET 1,L | *NOP | *LD L,SET 1,(IX+d) | +|[ ce | 206 ] | ADC A,n | +ADC A,n | SET 1,(HL) | *NOP | SET 1,(IX+d) | +|[ cf | 207 ] | RST 8 | +RST 8 | SET 1,A | *NOP | *LD A,SET 1,(IX+d) | +|[ d0 | 208 ] | RET NC | +RET NC | SET 2,B | *NOP | *LD B,SET 2,(IX+d) | +|[ d1 | 209 ] | POP DE | +POP DE | SET 2,C | *NOP | *LD C,SET 2,(IX+d) | +|[ d2 | 210 ] | JP NC,nn | +JP NC,nn | SET 2,D | *NOP | *LD D,SET 2,(IX+d) | +|[ d3 | 211 ] | OUT (n),A | +OUT (n),A | SET 2,E | *NOP | *LD E,SET 2,(IX+d) | +|[ d4 | 212 ] | CALL NC,nn | +CALL NC,nn | SET 2,H | *NOP | *LD H,SET 2,(IX+d) | +|[ d5 | 213 ] | PUSH DE | +PUSH DE | SET 2,L | *NOP | *LD L,SET 2,(IX+d) | +|[ d6 | 214 ] | SUB n | +SUB n | SET 2,(HL) | *NOP | SET 2,(IX+d) | +|[ d7 | 215 ] | RST 10H | +RST 10H | SET 2,A | *NOP | *LD A,SET 2,(IX+d) | +|[ d8 | 216 ] | RET C | +RET C | SET 3,B | *NOP | *LD B,SET 3,(IX+d) | +|[ d9 | 217 ] | EXX | +EXX | SET 3,C | *NOP | *LD C,SET 3,(IX+d) | +|[ da | 218 ] | JP C,nn | +JP C,nn | SET 3,D | *NOP | *LD D,SET 3,(IX+d) | +|[ db | 219 ] | IN A,(n) | +IN A,(n) | SET 3,E | *NOP | *LD E,SET 3,(IX+d) | +|[ dc | 220 ] | CALL C,nn | +CALL C,nn | SET 3,H | *NOP | *LD H,SET 3,(IX+d) | +|[ dd | 221 ] | [IX Prefix] | +[IX Prefix] | SET 3,L | *NOP | *LD L,SET 3,(IX+d) | +|[ de | 222 ] | SBC A,n | +SBC A,n | SET 3,(HL) | *NOP | SET 3,(IX+d) | +|[ df | 223 ] | RST 18H | +RST 18H | SET 3,A | *NOP | *LD A,SET 3,(IX+d) | +|[ e0 | 224 ] | RET PO | +RET PO | SET 4,B | *NOP | *LD B,SET 4,(IX+d) | +|[ e1 | 225 ] | POP HL | POP IX | SET 4,C | *NOP | *LD C,SET 4,(IX+d) | +|[ e2 | 226 ] | JP PO,nn | +JP PO,nn | SET 4,D | *NOP | *LD D,SET 4,(IX+d) | +|[ e3 | 227 ] | EX (SP),HL | EX (SP),IX | SET 4,E | *NOP | *LD E,SET 4,(IX+d) | +|[ e4 | 228 ] | CALL PO,nn | +CALL PO,nn | SET 4,H | *NOP | *LD H,SET 4,(IX+d) | +|[ e5 | 229 ] | PUSH HL | PUSH IX | SET 4,L | *NOP | *LD L,SET 4,(IX+d) | +|[ e6 | 230 ] | AND n | +AND n | SET 4,(HL) | *NOP | SET 4,(IX+d) | +|[ e7 | 231 ] | RST 20H | +RST 20H | SET 4,A | *NOP | *LD A,SET 4,(IX+d) | +|[ e8 | 232 ] | RET PE | +RET PE | SET 5,B | *NOP | *LD B,SET 5,(IX+d) | +|[ e9 | 233 ] | JP (HL) | JP (IX) | SET 5,C | *NOP | *LD C,SET 5,(IX+d) | +|[ ea | 234 ] | JP PE,nn | +JP PE,nn | SET 5,D | *NOP | *LD D,SET 5,(IX+d) | +|[ eb | 235 ] | EX DE,HL | +EX DE,HL | SET 5,E | *NOP | *LD E,SET 5,(IX+d) | +|[ ec | 236 ] | CALL PE,nn | +CALL PE,nn | SET 5,H | *NOP | *LD H,SET 5,(IX+d) | +|[ ed | 237 ] | [Prefix] | +[Prefix] | SET 5,L | *NOP | *LD L,SET 5,(IX+d) | +|[ ee | 238 ] | XOR n | +XOR n | SET 5,(HL) | *NOP | SET 5,(IX+d) | +|[ ef | 239 ] | RST 28H | +RST 28H | SET 5,A | *NOP | *LD A,SET 5,(IX+d) | +|[ f0 | 240 ] | RET P | +RET P | SET 6,B | *NOP | *LD B,SET 6,(IX+d) | +|[ f1 | 241 ] | POP AF | +POP AF | SET 6,C | *NOP | *LD C,SET 6,(IX+d) | +|[ f2 | 242 ] | JP P,nn | +JP P,nn | SET 6,D | *NOP | *LD D,SET 6,(IX+d) | +|[ f3 | 243 ] | DI | +DI | SET 6,E | *NOP | *LD E,SET 6,(IX+d) | +|[ f4 | 244 ] | CALL P,nn | +CALL P,nn | SET 6,H | *NOP | *LD H,SET 6,(IX+d) | +|[ f5 | 245 ] | PUSH AF | +PUSH AF | SET 6,L | *NOP | *LD L,SET 6,(IX+d) | +|[ f6 | 246 ] | OR n | +OR n | SET 6,(HL) | *NOP | SET 6,(IX+d) | +|[ f7 | 247 ] | RST 30H | +RST 30H | SET 6,A | *NOP | *LD A,SET 6,(IX+d) | +|[ f8 | 248 ] | RET M | +RET M | SET 7,B | *NOP | *LD B,SET 7,(IX+d) | +|[ f9 | 249 ] | LD SP,HL | LD SP,IX | SET 7,C | *NOP | *LD C,SET 7,(IX+d) | +|[ fa | 250 ] | JP M,nn | +JP M,nn | SET 7,D | *NOP | *LD D,SET 7,(IX+d) | +|[ fb | 251 ] | EI | +EI | SET 7,E | *NOP | *LD E,SET 7,(IX+d) | +|[ fc | 252 ] | CALL M,nn | +CALL M,nn | SET 7,H | *NOP | *LD H,SET 7,(IX+d) | +|[ fd | 253 ] | [IY Prefix] | +[IY Prefix] | SET 7,L | *NOP | *LD L,SET 7,(IX+d) | +|[ fe | 254 ] | CP n | +CP n | SET 7,(HL) | *NOP | SET 7,(IX+d) | +|[ ff | 255 ] | RST 38H | +RST 38H | SET 7,A | *NOP | *LD A,SET 7,(IX+d) | ++-------------+-----------------+-------------------+------------------+------------------+-------------------------+ +-- +Peter McGavin. (peterm@maths.grace.cri.nz) + +From: agulbra@tigern.nvg.unit.no (Arnt Gulbrandsen) +Newsgroups: comp.sys.sinclair +Subject: Re: Undocumented Z80 opcodes +Date: 6 Jan 1994 13:31:44 +0100 +Organization: University of Trondheim, Norway +NNTP-Posting-Host: tigern.nvg.unit.no + +In article <PETERM.94Jan6094415@kea.grace.cri.nz>, +Peter McGavin <peterm@maths.grace.cri.nz> wrote: +>In article, <2geqvv$nlq@tigern.nvg.unit.no>, +>agulbra@tigern.nvg.unit.no (Arnt Gulbrandsen) wrote: +>>I believe that list originally was written by from David Librik +>><librik@cory.eecs.berkeley.edu>. David (with someone else, I think) +>>reverse-engineered the Z80 and wrote a list of what he found, a list +>>which I think I sent to Peter. +> +>Actually I got it from Simon Owen (S.N.Owen@newcastle.ac.uk). +> +>Here it is: (sorry it's a bit wide) + +Not the same. Here's the big one. + +--Arnt + +Date: Fri, 19 Nov 1993 00:40:23 -0800 +From: David Librik <librik@cory.EECS.Berkeley.EDU> +Message-Id: <199311190840.AAA06896@cory.EECS.Berkeley.EDU> +Subject: Undocumented Z-80 Instructions + + +Here is my article on undocumented Z-80 instructions. Please go over +your data and add anything you can to this list, and send it back to me. +Thanks! + +- David Librik +librik@cs.Berkeley.edu + + ------------------ + +There's been some discussion about the so-called "undocumented" opcodes +of the Z-80 microprocessor. These are officially-undefined machine- +language instructions that often have powerful and useful effects; +they are so often used by Z-80 system programmers that they are de-facto +"documented". Here is an article I posted a few years ago on another +computer system. + +By the way, the reason these instructions exist even though they were +not part of the original CPU design: the Z-80 was the most complex +microprocessor ever to be completely hard-wired (no microcode). As a +result -- as anyone who's ever taken a logic design course can tell +you -- it's much easier to have "undefined states" do whatever-comes- +easiest. + +* 2/28/88 2:37 pm librik / pega / cerl * + +The undocumented Z80 opcodes. While Zilog claims that +these should not be "trusted", I have yet to hear of a +Z80 that does not support them; and at least one operating +system uses them. + +* HX and LX instructions. These instructions manipulate + the high- and low-order 8 bits of the sixteen bit IX and + IY registers. (Here, I give the opcodes for HX and LX, + to get HY and LY, use FD instead of DD in the opcodes.) + +* SLL. This instruction shifts an 8-bit quantity left + (logical), then inserts 1 into the low-order bit. + +* Shift/Bit Set/Bit Reset with autocopy. These instructions + perform bit shifts (RLC, RRC, RL, RR, SLA, SRA, SLL, SRL), + bit set (SET) and bit reset (RES) operations on (IX+jj) + [and (IY+jj)], but also automatically copy the result + into an 8-bit register. + +* Null port accesses. IN and OUT without data. + +dd24 inc hx dd62 ld hx,d dd8c adc a,hx +dd25 dec hx dd63 ld hx,e dd8d adc a,lx +dd26nn ld hx,nn dd64 ld hx,hx dd94 sub hx +dd2c inc lx dd65 ld hx,lx dd95 sub lx +dd2d dec lx dd67 ld hx,a dd9c sbc a,hx +dd2enn ld lx,nn dd68 ld lx,b dd9d sbc a,lx +dd44 ld b,hx dd69 ld lx,c dda4 and hx +dd45 ld b,lx dd6a ld lx,d dda5 and lx +dd4c ld c,hx dd6b ld lx,e ddac xor hx +dd4d ld c,lx dd6c ld lx,hx ddad xor lx +dd54 ld d,hx dd6d ld lx,lx ddb4 or hx +dd55 ld d,lx dd6f ld lx,a ddb5 or lx +dd5c ld e,hx dd7c ld a,hx ddbc cp hx +dd5d ld e,lx dd7d ld a,lx ddbd cp lx +dd60 ld hx,b dd84 add a,hx +dd61 ld hx,c dd85 add a,lx + +The corresponding instructions for HY and LY may be obtained +by using FD in place of DD. + +cb30 sll b cb34 sll h +cb31 sll c cb35 sll l +cb32 sll d cb36 sll (hl) +cb33 sll e cb37 sll a + +* The following instructions perform the indicated operation +* on (ix+jj) and copy results into register 'r' (see below). +ddcbjj00-ddcbjj07 rlc r,(ix+jj) +ddcbjj08-ddcbjj0f rrc r,(ix+jj) +ddcbjj10-ddcbjj17 rl r,(ix+jj) +ddcbjj18-ddcbjj1f rr r,(ix+jj) +ddcbjj20-ddcbjj27 sla r,(ix+jj) +ddcbjj28-ddcbjj2f sra r,(ix+jj) +ddcbjj30-ddcbjj37 sll r,(ix+jj) +ddcbjj38-ddcbjj3f srl r,(ix+jj) + +ddcbjj80-ddcbjj87 res r,0,(ix+jj) +ddcbjj88-ddcbjj8f res r,1,(ix+jj) +ddcbjj90-ddcbjj97 res r,2,(ix+jj) +ddcbjj98-ddcbjj9f res r,3,(ix+jj) +ddcbjja0-ddcbjja7 res r,4,(ix+jj) +ddcbjja8-ddcbjjaf res r,5,(ix+jj) +ddcbjjb0-ddcbjjb7 res r,6,(ix+jj) +ddcbjjb8-ddcbjjbf res r,7,(ix+jj) + +ddcbjjc0-ddcbjjc7 set r,0,(ix+jj) +ddcbjjc8-ddcbjjcf set r,1,(ix+jj) +ddcbjjd0-ddcbjjd7 set r,2,(ix+jj) +ddcbjjd8-ddcbjjdf set r,3,(ix+jj) +ddcbjje0-ddcbjje7 set r,4,(ix+jj) +ddcbjje8-ddcbjjef set r,5,(ix+jj) +ddcbjjf0-ddcbjjf7 set r,6,(ix+jj) +ddcbjjf8-ddcbjjff set r,7,(ix+jj) + +In the last 3 tables, the corresponding instructions for +(IY+jj) may be obtained by using FD in place of DD. + +The value for 'r' is determined as follows: + Last digit of opcode: register 'r': + 0 or 8 B + 1 or 9 C + 2 or A D + 3 or B E + 4 or C H + 5 or D L + 6 or E (no effect) + 7 or F A + +* +ed70 in --,(c) +* gets input from port stored in (c), but does not store it. +* another reference claims this is: in (hl),(c) but I see no +* evidence for that, other than symmetry. +* +ed71 out (c),-- +* seems to send a 00 to port stored in (c). +* the same reference as as above calls this: out (hl),(c). + +A full article on this material is available upon request. +This information from NORTHERN BYTES, volume 5 number 8. + + -------- + +In addition to the information in the above article, I should mention +for completeness' sake all the other undefined opcodes and their +(generally redundant) effects. I shall list the ordinary Z-80 +instructions which they mimic. + +ed63nnnn ld (nnnn),hl +ed6bnnnn ld hl,(nnnn) +ed4c, ed54, ed5c, ed64, ed6c, ed74, ed7c neg + ed55, ed5d, ed65, ed6d, ed75, ed7d retn + +The following are no-ops: + +ed80-9f, eda4-a7, edac-af, edb4-b7, edbc-bf, ed00-3f, edc0-ff, +ed4e, ed66, ed6e, ed76, ed77, ed7e, ed7f + +Additional information from NANOS' Reference Card for the Z-80 microprocessor. + +David Librik +librik/pega/nova (on PLATO/NovaNET) + + diff --git a/sim/ucsim/z80.src/z80cl.h b/sim/ucsim/z80.src/z80cl.h new file mode 100644 index 0000000..80637b6 --- /dev/null +++ b/sim/ucsim/z80.src/z80cl.h @@ -0,0 +1,195 @@ +/* + * Simulator of microcontrollers (z80cl.h) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#ifndef Z80CL_HEADER +#define Z80CL_HEADER + +#include "uccl.h" + +#include "regsz80.h" + +/* + * Base type of Z80 microcontrollers + */ + +class cl_z80: public cl_uc +{ +public: + class cl_memory *ram; + class cl_memory *rom; + struct t_regs regs; + class cl_address_space *regs8; + class cl_address_space *regs16; + class cl_address_space *inputs; + class cl_address_space *outputs; +public: + cl_z80(struct cpu_entry *Itype, class cl_sim *asim); + virtual int init(void); + virtual char *id_string(void); + + //virtual t_addr get_mem_size(enum mem_class type); + virtual void mk_hw_elements(void); + virtual void make_memories(void); + + virtual struct dis_entry *dis_tbl(void); + virtual int inst_length(t_addr addr); + virtual int inst_branch(t_addr addr); + virtual int longest_inst(void); + virtual char *disass(t_addr addr, const char *sep); + virtual void print_regs(class cl_console_base *con); + + virtual int exec_inst(void); + + virtual const char *get_disasm_info(t_addr addr, + int *ret_len, + int *ret_branch, + int *immed_offset, + struct dis_entry **dentry); + virtual bool is_call(t_addr addr); + + virtual void store1( u16_t addr, t_mem val ); + virtual void store2( u16_t addr, u16_t val ); + + virtual u8_t get1( u16_t addr ); + virtual u16_t get2( u16_t addr ); + + virtual t_mem fetch1( void ); + virtual u16_t fetch2( void ); + virtual t_mem peek1 ( void ); + + virtual u8_t in_byte( u16_t ioaddr ); + virtual void out_byte( u16_t ioaddr, u8_t io_val ); + + //virtual t_mem fetch(void); + virtual u8_t reg_g_read ( t_mem g ); + virtual void reg_g_store( t_mem g, u8_t new_val ); + + virtual int inst_nop(t_mem code); + virtual int inst_ld(t_mem code); + virtual int inst_inc(t_mem code); + virtual int inst_dec(t_mem code); + virtual int inst_rlca(t_mem code); + virtual int inst_rrca(t_mem code); + virtual int inst_ex(t_mem code); + virtual int inst_add(t_mem code); + virtual int inst_djnz(t_mem code); + virtual int inst_jr(t_mem code); + virtual int inst_rla(t_mem code); + virtual int inst_rra(t_mem code); + virtual int inst_daa(t_mem code); + virtual int inst_cpl(t_mem code); + virtual int inst_scf(t_mem code); + virtual int inst_ccf(t_mem code); + virtual int inst_halt(t_mem code); + virtual int inst_adc(t_mem code); + virtual int inst_sbc(t_mem code); + virtual int inst_and(t_mem code); + virtual int inst_xor(t_mem code); + virtual int inst_or(t_mem code); + virtual int inst_cp(t_mem code); + virtual int inst_rst(t_mem code); + virtual int inst_ret(t_mem code); + virtual int inst_call(t_mem code); + virtual int inst_out(t_mem code); + virtual int inst_push(t_mem code); + virtual int inst_exx(t_mem code); + virtual int inst_in(t_mem code); + virtual int inst_sub(t_mem code); + virtual int inst_pop(t_mem code); + virtual int inst_jp(t_mem code); + virtual int inst_di(t_mem code); + virtual int inst_ei(t_mem code); + + virtual int inst_fd(t_mem prefix); + virtual int inst_fd_ld(t_mem code); + virtual int inst_fd_add(t_mem code); + virtual int inst_fd_push(t_mem code); + virtual int inst_fd_inc(t_mem code); + virtual int inst_fd_dec(t_mem code); + virtual int inst_fd_misc(t_mem code); + + virtual int inst_dd(t_mem prefix); + virtual int inst_dd_ld(t_mem code); + virtual int inst_dd_add(t_mem code); + virtual int inst_dd_push(t_mem code); + virtual int inst_dd_inc(t_mem code); + virtual int inst_dd_dec(t_mem code); + virtual int inst_dd_misc(t_mem code); + + virtual int inst_ed(t_mem prefix); + virtual int inst_ed_(t_mem code); + + virtual int inst_cb(void); + virtual int inst_cb_rlc(t_mem code); + virtual int inst_cb_rrc(t_mem code); + virtual int inst_cb_rl(t_mem code); + virtual int inst_cb_rr(t_mem code); + virtual int inst_cb_sla(t_mem code); + virtual int inst_cb_sra(t_mem code); + virtual int inst_cb_slia(t_mem code); + virtual int inst_cb_srl(t_mem code); + virtual int inst_cb_bit(t_mem code); + virtual int inst_cb_res(t_mem code); + virtual int inst_cb_set(t_mem code); + + virtual int inst_ddcb(void); + virtual int inst_ddcb_rlc(t_mem code); + virtual int inst_ddcb_rrc(t_mem code); + virtual int inst_ddcb_rl(t_mem code); + virtual int inst_ddcb_rr(t_mem code); + virtual int inst_ddcb_sla(t_mem code); + virtual int inst_ddcb_sra(t_mem code); + virtual int inst_ddcb_slia(t_mem code); + virtual int inst_ddcb_srl(t_mem code); + virtual int inst_ddcb_bit(t_mem code); + virtual int inst_ddcb_res(t_mem code); + virtual int inst_ddcb_set(t_mem code); + + virtual int inst_fdcb(void); + virtual int inst_fdcb_rlc(t_mem code); + virtual int inst_fdcb_rrc(t_mem code); + virtual int inst_fdcb_rl(t_mem code); + virtual int inst_fdcb_rr(t_mem code); + virtual int inst_fdcb_sla(t_mem code); + virtual int inst_fdcb_sra(t_mem code); + virtual int inst_fdcb_slia(t_mem code); + virtual int inst_fdcb_srl(t_mem code); + virtual int inst_fdcb_bit(t_mem code); + virtual int inst_fdcb_res(t_mem code); + virtual int inst_fdcb_set(t_mem code); + + virtual int inst_dd_spec(t_mem code) { return -1; } + virtual int inst_fd_spec(t_mem code) { return -1; } +}; + + +unsigned word_parity( u16_t x ); +/* returns parity for a 16-bit value */ + +#endif + +/* End of z80.src/z80cl.h */ diff --git a/sim/ucsim/z80.src/z80mac.h b/sim/ucsim/z80.src/z80mac.h new file mode 100644 index 0000000..f454efb --- /dev/null +++ b/sim/ucsim/z80.src/z80mac.h @@ -0,0 +1,309 @@ +/* + * Simulator of microcontrollers (z80mac.h) + * + * some z80 code base from Karl Bongers karl@turbobit.com + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +#if 0 +/* made into virtual function in z80_cl class to make integrating + * banking and/or memory mapped devices easier + * -Leland Morrison 2011-09-29 + */ + +#define store2(addr, val) { ram->write((t_addr) (addr), val & 0xff); \ + ram->write((t_addr) (addr+1), (val >> 8) & 0xff); } +#define store1(addr, val) ram->write((t_addr) (addr), val) +#define get1(addr) ram->read((t_addr) (addr)) +#define get2(addr) (ram->read((t_addr) (addr)) | (ram->read((t_addr) (addr+1)) << 8) ) +#define fetch2() (fetch() | (fetch() << 8)) +#define fetch1() fetch() +#endif + +#define push2(val) {regs.SP-=2; store2(regs.SP,(val));} +#define push1(val) {regs.SP-=1; store1(regs.SP,(val));} +#define pop2(var) {var=get2(regs.SP),regs.SP+=2;} +//#define pop1(var) {var=get1(regs.SP),regs.SP+=1;} +#define add_u16_disp(_w, _d) (( (unsigned short)(_w) + (signed char)(_d) ) & 0xffff) +#define parity(val) ( ((val>>7)&1) ^ ((val>>6)&1) ^ ((val>>5)&1) ^ ((val>>4)&1) ^ ((val>>3)&1) ^ ((val>>2)&1) ^ ((val>>1)&1) ^ ((val>>0)&1) ^ 1 ) + +#define add_A_bytereg(br) { \ + unsigned int accu = (unsigned int)regs.raf.A; \ + unsigned int oper = (unsigned int)(br); \ + signed int res = (signed char)regs.raf.A + (signed char)(br); \ + regs.raf.F &= ~(BIT_ALL); /* clear these */ \ + regs.raf.F &= ~BIT_N; /* addition */ \ + if ((accu & 0x0F) + (oper & 0x0F) > 0x0F) regs.raf.F |= BIT_A; \ + if ((res < -128) || (res > 127)) regs.raf.F |= BIT_P; \ + if (accu + oper > 0xFF) regs.raf.F |= BIT_C; \ + regs.raf.A += oper; \ + if (regs.raf.A == 0) regs.raf.F |= BIT_Z; \ + if (regs.raf.A & 0x80) regs.raf.F |= BIT_S; \ +} + +#define adc_A_bytereg(br) { \ + unsigned int accu = (unsigned int)regs.raf.A; \ + unsigned int oper = (unsigned int)(br); \ + signed int res = (signed char)regs.raf.A + (signed char)(br); \ + if (regs.raf.F & BIT_C) { ++oper; ++res; } \ + regs.raf.F &= ~(BIT_ALL); /* clear these */ \ + regs.raf.F &= ~BIT_N; /* addition */ \ + if ((accu & 0x0F) + (oper & 0x0F) > 0x0F) regs.raf.F |= BIT_A; \ + if ((res < -128) || (res > 127)) regs.raf.F |= BIT_P; \ + if (accu + oper > 0xFF) regs.raf.F |= BIT_C; \ + regs.raf.A += oper; \ + if (regs.raf.A == 0) regs.raf.F |= BIT_Z; \ + if (regs.raf.A & 0x80) regs.raf.F |= BIT_S; \ +} + +#define add_HL_Word(wr) { \ + unsigned int accu = (unsigned int)regs.HL; \ + unsigned int oper = (unsigned int)(wr); \ + regs.raf.F &= ~(BIT_A | BIT_C); /* clear these */ \ + regs.raf.F &= ~BIT_N; /* addition */ \ + if ((accu & 0x0FFF) + (oper & 0x0FFF) > 0x0FFF) regs.raf.F |= BIT_A; \ + if (accu + oper > 0xFFFF) regs.raf.F |= BIT_C; \ + regs.HL += oper; \ +} + +#define add_IX_Word(wr) { \ + unsigned int accu = (unsigned int)regs_IX_OR_IY; \ + unsigned int oper = (unsigned int)(wr); \ + regs.raf.F &= ~(BIT_A | BIT_C); /* clear these */ \ + regs.raf.F &= ~BIT_N; /* addition */ \ + if ((accu & 0x0FFF) + (oper & 0x0FFF) > 0x0FFF) regs.raf.F |= BIT_A; \ + if (accu + oper > 0xFFFF) regs.raf.F |= BIT_C; \ + regs_IX_OR_IY += oper; \ +} + +#define adc_HL_wordreg(reg) { \ + unsigned int accu = (unsigned int)regs.HL; \ + unsigned int oper = (unsigned int)(reg); \ + signed int res = (signed short)regs.HL + (signed short)(reg); \ + if (regs.raf.F & BIT_C) { ++oper; ++res; } \ + regs.raf.F &= ~(BIT_ALL); /* clear these */ \ + regs.raf.F &= ~BIT_N; /* addition */ \ + if ((accu & 0x0FFF) + (oper & 0x0FFF) > 0x0FFF) regs.raf.F |= BIT_A; \ + if ((res < -32768) || (res > 32767)) regs.raf.F |= BIT_P; \ + if (accu + oper > 0xFFFF) regs.raf.F |= BIT_C; \ + regs.HL += oper; \ + if (regs.HL == 0) regs.raf.F |= BIT_Z; \ + if (regs.HL & 0x8000) regs.raf.F |= BIT_S; \ +} + +#define sub_A_bytereg(br) { \ + unsigned int accu = (unsigned int)regs.raf.A; \ + unsigned int oper = (unsigned int)(br); \ + signed int res = (signed char)regs.raf.A - (signed char)(br); \ + regs.raf.F &= ~(BIT_ALL); /* clear these */ \ + regs.raf.F |= BIT_N; /* not addition */ \ + if ((accu & 0x0F) < (oper & 0x0F)) regs.raf.F |= BIT_A; \ + if ((res < -128) || (res > 127)) regs.raf.F |= BIT_P; \ + if (accu < oper) regs.raf.F |= BIT_C; \ + regs.raf.A -= oper; \ + if (regs.raf.A == 0) regs.raf.F |= BIT_Z; \ + if (regs.raf.A & 0x80) regs.raf.F |= BIT_S; \ +} + +#define sbc_A_bytereg(br) { \ + unsigned int accu = (unsigned int)regs.raf.A; \ + unsigned int oper = (unsigned int)(br); \ + signed int res = (signed char)regs.raf.A - (signed char)(br); \ + if (regs.raf.F & BIT_C) { ++oper; --res; } \ + regs.raf.F &= ~(BIT_ALL); /* clear these */ \ + regs.raf.F |= BIT_N; /* not addition */ \ + if ((accu & 0x0F) < (oper & 0x0F)) regs.raf.F |= BIT_A; \ + if ((res < -128) || (res > 127)) regs.raf.F |= BIT_P; \ + if (accu < oper) regs.raf.F |= BIT_C; \ + regs.raf.A -= oper; \ + if (regs.raf.A == 0) regs.raf.F |= BIT_Z; \ + if (regs.raf.A & 0x80) regs.raf.F |= BIT_S; \ +} + +#define sbc_HL_wordreg(reg) { \ + unsigned int accu = (unsigned int)regs.HL; \ + unsigned int oper = (unsigned int)reg; \ + signed int res = (signed short)regs.HL - (signed short)(reg);\ + if (regs.raf.F & BIT_C) { ++oper; --res; } \ + regs.raf.F &= ~(BIT_ALL); /* clear these */ \ + regs.raf.F |= BIT_N; /* not addition */ \ + if ((accu & 0x0FFF) < (oper & 0x0FFF)) regs.raf.F |= BIT_A; \ + if ((res < -32768) || (res > 32767)) regs.raf.F |= BIT_P; \ + if (accu < oper) regs.raf.F |= BIT_C; \ + regs.HL -= oper; \ + if (regs.HL == 0) regs.raf.F |= BIT_Z; \ + if (regs.HL & 0x8000) regs.raf.F |= BIT_S; \ +} + +#define cp_bytereg(br) { \ + unsigned int accu = (unsigned int)regs.raf.A; \ + unsigned int oper = (unsigned int)(br); \ + regs.raf.F &= ~(BIT_ALL); /* clear these */ \ + regs.raf.F |= BIT_N; /* not addition */ \ + if ((accu & 0x0F) < (oper & 0x0F)) regs.raf.F |= BIT_A; \ + if ((accu & 0x7F) < (oper & 0x7F)) regs.raf.F |= BIT_P; \ + if (accu < oper) { regs.raf.F |= BIT_C; regs.raf.F ^= BIT_P; } \ + accu -= oper; \ + if (accu == 0) regs.raf.F |= BIT_Z; \ + if (accu & 0x80) regs.raf.F |= BIT_S; \ +} + +#define rr_byte(reg) { \ + if (regs.raf.F & BIT_C) { \ + regs.raf.F &= ~(BIT_ALL); /* clear these */ \ + if (reg & 0x01) \ + regs.raf.F |= BIT_C; \ + reg = (reg >> 1) | 0x80; \ + } else { \ + regs.raf.F &= ~(BIT_ALL); /* clear these */ \ + if (reg & 0x01) \ + regs.raf.F |= BIT_C; \ + reg = (reg >> 1); \ + } \ + if (reg == 0) regs.raf.F |= BIT_Z; \ + if (reg & 0x80) regs.raf.F |= BIT_S; \ + if (parity(regs.raf.A)) regs.raf.F |= BIT_P; \ +} + +#define rrc_byte(reg) { \ + regs.raf.F &= ~(BIT_ALL); /* clear these */ \ + if (reg & 0x01) { \ + regs.raf.F |= BIT_C; \ + reg = (reg >> 1) | 0x80; \ + } \ + else \ + reg = (reg >> 1); \ + if (reg == 0) regs.raf.F |= BIT_Z; \ + if (reg & 0x80) regs.raf.F |= BIT_S; \ + if (parity(regs.raf.A)) regs.raf.F |= BIT_P; \ +} + +#define rl_byte(reg) { \ + if (regs.raf.F & BIT_C) { \ + regs.raf.F &= ~(BIT_ALL); /* clear these */ \ + if (reg & 0x80) \ + regs.raf.F |= BIT_C; \ + reg = (reg << 1) | 0x01; \ + } else { \ + regs.raf.F &= ~(BIT_ALL); /* clear these */ \ + if (reg & 0x80) \ + regs.raf.F |= BIT_C; \ + reg = (reg << 1); \ + } \ + if (reg == 0) regs.raf.F |= BIT_Z; \ + if (reg & 0x80) regs.raf.F |= BIT_S; \ + if (parity(regs.raf.A)) regs.raf.F |= BIT_P; \ +} + +#define rlc_byte(reg) { \ + regs.raf.F &= ~(BIT_ALL); /* clear these */ \ + if (reg & 0x80) { \ + regs.raf.F |= BIT_C; \ + reg = (reg << 1) | 0x01; \ + } else \ + reg = (reg << 1); \ + if (reg == 0) regs.raf.F |= BIT_Z; \ + if (reg & 0x80) regs.raf.F |= BIT_S; \ + if (parity(regs.raf.A)) regs.raf.F |= BIT_P; \ +} + +#define sla_byte(reg) { \ + regs.raf.F &= ~(BIT_ALL); /* clear these */ \ + if (reg & 0x80) \ + regs.raf.F |= BIT_C; \ + reg = (reg << 1); \ + if (reg == 0) regs.raf.F |= BIT_Z; \ + if (reg & 0x80) regs.raf.F |= BIT_S; \ + if (parity(regs.raf.A)) regs.raf.F |= BIT_P; \ +} + +#define sra_byte(reg) { \ + regs.raf.F &= ~(BIT_ALL); /* clear these */ \ + if (reg & 0x80) { \ + if (reg & 0x01) \ + regs.raf.F |= BIT_C; \ + reg = (reg >> 1) | 0x80; \ + } else { \ + if (reg & 0x01) \ + regs.raf.F |= BIT_C; \ + reg = (reg >> 1); \ + } \ + if (reg == 0) regs.raf.F |= BIT_Z; \ + if (reg & 0x80) regs.raf.F |= BIT_S; \ + if (parity(regs.raf.A)) regs.raf.F |= BIT_P; \ +} + +#define srl_byte(reg) { \ + regs.raf.F &= ~(BIT_ALL); /* clear these */ \ + if (reg & 0x01) \ + regs.raf.F |= BIT_C; \ + reg = (reg >> 1); \ + if (reg == 0) regs.raf.F |= BIT_Z; \ + if (reg & 0x80) regs.raf.F |= BIT_S; \ + if (parity(regs.raf.A)) regs.raf.F |= BIT_P; \ +} + +/* following not in my book, best guess based on z80.txt comments */ +#define slia_byte(reg) { \ + regs.raf.F &= ~(BIT_ALL); /* clear these */ \ + if (reg & 0x80) \ + regs.raf.F |= BIT_C; \ + reg = (reg << 1) | 1; \ + if (reg == 0) regs.raf.F |= BIT_Z; \ + if (reg & 0x80) regs.raf.F |= BIT_S; \ + if (parity(regs.raf.A)) regs.raf.F |= BIT_P; \ +} + +#define and_A_bytereg(br) { \ + regs.raf.A &= (br); \ + regs.raf.F &= ~(BIT_ALL); /* clear these */ \ + if (regs.raf.A == 0) regs.raf.F |= BIT_Z; \ + if (regs.raf.A & 0x80) regs.raf.F |= BIT_S; \ + if (parity(regs.raf.A)) regs.raf.F |= BIT_P; \ +} + +#define xor_A_bytereg(br) { \ + regs.raf.A ^= (br); \ + regs.raf.F &= ~(BIT_ALL); /* clear these */ \ + if (regs.raf.A == 0) regs.raf.F |= BIT_Z; \ + if (regs.raf.A & 0x80) regs.raf.F |= BIT_S; \ + if (parity(regs.raf.A)) regs.raf.F |= BIT_P; \ +} + +#define or_A_bytereg(br) { \ + regs.raf.A |= (br); \ + regs.raf.F &= ~(BIT_ALL); /* clear these */ \ + if (regs.raf.A == 0) regs.raf.F |= BIT_Z; \ + if (regs.raf.A & 0x80) regs.raf.F |= BIT_S; \ + if (parity(regs.raf.A)) regs.raf.F |= BIT_P; \ +} + +#define inc(var) /* 8-bit increment */ { var++; \ + regs.raf.F &= ~(BIT_N |BIT_P |BIT_A |BIT_Z |BIT_S); /* clear these */ \ + if (var == 0) regs.raf.F |= BIT_Z; \ + if (var == 0x80) regs.raf.F |= BIT_P; \ + if (var & 0x80) regs.raf.F |= BIT_S; \ + if ((var & 0x0f) == 0) regs.raf.F |= BIT_A; \ +} + +#define dec(var) { \ + --var; \ + regs.raf.F &= ~(BIT_N |BIT_P |BIT_A |BIT_Z |BIT_S); /* clear these */ \ + regs.raf.F |= BIT_N; /* Not add */ \ + if (var == 0) regs.raf.F |= BIT_Z; \ + if (var == 0x7f) regs.raf.F |= BIT_P; \ + if (var & 0x80) regs.raf.F |= BIT_S; \ + if ((var & 0x0f) == 0) regs.raf.F |= BIT_A; \ +} + +#define bit_byte(reg, _bitnum) { \ + regs.raf.F &= ~(BIT_N |BIT_P |BIT_A |BIT_Z |BIT_S); /* clear these */ \ + regs.raf.F |= BIT_A; \ + if (!(reg & (1 << (_bitnum)))) \ + regs.raf.F |= BIT_Z; \ + /* book shows BIT_S & BIT_P as unknown state */ \ +} |