sdcc-3.9.0 fork implementing GNU assembler syntax

This fork aims to provide better support for stm8-binutils

50 files changed, 5785 insertions, 0 deletions

diff --git a/sim/ucsim/tlcs.src/(c).1 b/sim/ucsim/tlcs.src/(c).1
new file mode 100644
index 0000000..d673f9f
--- /dev/null
+++ b/sim/ucsim/tlcs.src/(c).1
@@ -0,0 +1,25 @@
+/*
+ * Simulator of microcontrollers (@@F@@)
+ *
+ * Copyright (C) @@S@@,@@Y@@ Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
diff --git a/sim/ucsim/tlcs.src/Makefile b/sim/ucsim/tlcs.src/Makefile
new file mode 100644
index 0000000..2883956
--- /dev/null
+++ b/sim/ucsim/tlcs.src/Makefile
@@ -0,0 +1,154 @@
+#
+# uCsim tlcs.src/Makefile
+#
+# (c) Drotos Daniel, Talker Bt. 1997
+#
+#
+
+STARTYEAR	= 2016
+
+SHELL		= /bin/sh
+CXX		= g++
+CPP		= gcc -E
+CXXCPP		= g++ -E
+RANLIB		= ranlib
+INSTALL		= /usr/bin/install -c
+STRIP		= strip
+MAKEDEP         = g++ -MM
+
+top_builddir	= ..
+top_srcdir	= ..
+
+transform	= s,x,x,
+
+DEFS            = $(subs -DHAVE_CONFIG_H,,-DHAVE_CONFIG_H)
+CPPFLAGS        =  -I$(srcdir) -I$(top_srcdir) -I$(top_builddir) \
+		  -I$(top_srcdir)/cmd.src -I$(top_srcdir)/sim.src \
+		  -I$(top_srcdir)/gui.src
+CFLAGS          = -g -O2 -Wall
+CXXFLAGS        = -g -O2 -g -Wall
+LDFLAGS         = 
+PICOPT		=  -fPIC -DPIC
+SHAREDLIB	= yes
+EXEEXT		= 
+
+LIBS		= -L$(top_builddir) -lsim -lucsimutil -lguiucsim -lcmd -lsim -lrt -lnsl 
+DL		= -ldl
+dl_ok		= yes
+
+prefix          = /usr/local
+exec_prefix     = ${prefix}
+bindir          = ${exec_prefix}/bin
+libdir          = ${exec_prefix}/lib
+datadir         = ${datarootdir}
+datarootdir     = ${prefix}/share
+includedir      = ${prefix}/include
+mandir          = ${datarootdir}/man
+man1dir         = $(mandir)/man1
+man2dir         = $(mandir)/man2
+infodir         = ${datarootdir}/info
+srcdir          = .
+
+
+OBJECTS_SHARED	= glob.o \
+		  simtlcs.o tlcs.o \
+		  inst_block.o inst_cpu_others.o inst_rot_sh.o \
+		  inst_jump.o inst_move.o inst_arith.o inst_bit.o
+OBJECTS_EXE	= stlcs.o
+OBJECTS		= $(OBJECTS_SHARED) $(OBJECTS_EXE)
+
+enable_dlso	= no
+dlso_ok		= no
+
+
+# Compiling entire program or any subproject
+# ------------------------------------------
+all: checkconf otherlibs tlcs.src
+
+
+# Compiling and installing everything and runing test
+# ---------------------------------------------------
+install: all installdirs
+	$(INSTALL) stlcs$(EXEEXT) $(DESTDIR)$(bindir)/`echo stlcs|sed '$(transform)'`$(EXEEXT)
+	$(STRIP) $(DESTDIR)$(bindir)/`echo stlcs|sed '$(transform)'`$(EXEEXT)
+
+
+# Deleting all the installed files
+# --------------------------------
+uninstall:
+	rm -f $(DESTDIR)$(bindir)/stlcs
+	rm -f $(DESTDIR)$(bindir)/`echo stlcs|sed '$(transform)'`$(EXEEXT)
+
+
+# Performing self-test
+# --------------------
+check: $(TEST_OBJ)
+
+test:
+
+
+# Performing installation test
+# ----------------------------
+installcheck:
+
+
+# Creating installation directories
+# ---------------------------------
+installdirs:
+	test -d $(DESTDIR)$(bindir) || $(INSTALL) -d $(DESTDIR)$(bindir)
+
+
+# Creating dependencies
+# ---------------------
+dep: Makefile.dep
+
+Makefile.dep: $(srcdir)/*.cc $(srcdir)/*.h
+	$(MAKEDEP) $(CPPFLAGS) $(filter %.cc,$^) >Makefile.dep
+
+-include Makefile.dep
+include $(srcdir)/clean.mk
+
+# My rules
+# --------
+tlcs.src: stlcs$(EXEEXT) shared_lib
+
+stlcs$(EXEEXT): $(OBJECTS) $(top_builddir)/libcmd.a $(top_builddir)/libguiucsim.a $(top_builddir)/libsim.a $(top_builddir)/libucsimutil.a
+	$(CXX) $(CXXFLAGS) $(LDFLAGS) $(OBJECTS) $(LIBS) -o $@
+
+ifeq ($(dlso_ok),yes)
+shared_lib: $(top_builddir)/stlcs.so
+else
+shared_lib:
+	@$(top_srcdir)/mkecho $(top_builddir) "No TLCS shared lib made."
+	@$(top_srcdir)/mkecho $(top_builddir) "(SHAREDLIB="$(SHAREDLIB)",dl_ok="$(dl_ok)",enable_dlso="$(enable_dlso)")"
+endif
+
+$(top_builddir)/stlcs.so: $(OBJECTS_SHARED)
+	$(CXX) -shared $(LDFLAGS) $(OBJECTS_SHARED) -o $@
+
+otherlibs: $(top_builddir)/libcmd.a $(top_builddir)/libguiucsim.a $(top_builddir)/libsim.a $(top_builddir)/libucsimutil.a
+
+$(top_builddir)/libcmd.a:
+	$(MAKE) -C $(top_builddir)/cmd.src all
+
+$(top_builddir)/libguiucsim.a:
+	$(MAKE) -C $(top_builddir)/gui.src checkconf ucsim_lib
+
+$(top_builddir)/libsim.a:
+	$(MAKE) -C $(top_builddir)/sim.src all
+
+$(top_builddir)/libucsimutil.a:
+	$(MAKE) -C $(top_builddir) -f main.mk
+
+.cc.o:
+	$(CXX) $(CXXFLAGS) $(PICOPT) $(CPPFLAGS) $(TARGET_ARCH) -c $< -o $@
+
+
+# Remaking configuration
+# ----------------------
+checkconf:
+	@if [ -f $(top_builddir)/devel ]; then\
+	  $(MAKE) -C $(top_builddir) -f conf.mk srcdir="$(srcdir)" top_builddir="$(top_builddir)" freshconf;\
+	fi
+
+# End of tlcs.src/Makefile.in
diff --git a/sim/ucsim/tlcs.src/Makefile.dep b/sim/ucsim/tlcs.src/Makefile.dep
new file mode 100644
index 0000000..dd01b32
--- /dev/null
+++ b/sim/ucsim/tlcs.src/Makefile.dep
@@ -0,0 +1,90 @@
+inst_block.o: inst_block.cc tlcscl.h ../sim.src/uccl.h ../stypes.h \
+ ../ddconfig.h ../pobjcl.h ../pobjt.h ../eventcl.h ../charscl.h \
+ ../pobjt.h ../sim.src/hwcl.h ../sim.src/guiobjcl.h ../ddconfig.h \
+ ../cmd.src/newcmdcl.h ../optioncl.h ../pobjcl.h ../stypes.h \
+ ../cmd.src/commandcl.h ../cmd.src/newcmdcl.h ../cmd.src/newcmdposixcl.h \
+ ../fiocl.h ../cmd.src/cmdutil.h ../sim.src/memcl.h ../eventcl.h \
+ ../errorcl.h ../sim.src/uccl.h ../sim.src/brkcl.h ../sim.src/stackcl.h \
+ ../sim.src/varcl.h ../sim.src/uccl_instructions.h ../sim.src/memcl.h
+inst_cpu_others.o: inst_cpu_others.cc tlcscl.h ../sim.src/uccl.h \
+ ../stypes.h ../ddconfig.h ../pobjcl.h ../pobjt.h ../eventcl.h \
+ ../charscl.h ../pobjt.h ../sim.src/hwcl.h ../sim.src/guiobjcl.h \
+ ../ddconfig.h ../cmd.src/newcmdcl.h ../optioncl.h ../pobjcl.h \
+ ../stypes.h ../cmd.src/commandcl.h ../cmd.src/newcmdcl.h \
+ ../cmd.src/newcmdposixcl.h ../fiocl.h ../cmd.src/cmdutil.h \
+ ../sim.src/memcl.h ../eventcl.h ../errorcl.h ../sim.src/uccl.h \
+ ../sim.src/brkcl.h ../sim.src/stackcl.h ../sim.src/varcl.h \
+ ../sim.src/uccl_instructions.h ../sim.src/memcl.h
+inst_rot_sh.o: inst_rot_sh.cc tlcscl.h ../sim.src/uccl.h ../stypes.h \
+ ../ddconfig.h ../pobjcl.h ../pobjt.h ../eventcl.h ../charscl.h \
+ ../pobjt.h ../sim.src/hwcl.h ../sim.src/guiobjcl.h ../ddconfig.h \
+ ../cmd.src/newcmdcl.h ../optioncl.h ../pobjcl.h ../stypes.h \
+ ../cmd.src/commandcl.h ../cmd.src/newcmdcl.h ../cmd.src/newcmdposixcl.h \
+ ../fiocl.h ../cmd.src/cmdutil.h ../sim.src/memcl.h ../eventcl.h \
+ ../errorcl.h ../sim.src/uccl.h ../sim.src/brkcl.h ../sim.src/stackcl.h \
+ ../sim.src/varcl.h ../sim.src/uccl_instructions.h ../sim.src/memcl.h
+tlcs.o: tlcs.cc ../ddconfig.h ../i_string.h ../ddconfig.h ../pobjcl.h \
+ ../pobjt.h ../eventcl.h ../charscl.h ../sim.src/simcl.h \
+ ../cmd.src/newcmdcl.h ../optioncl.h ../pobjcl.h ../stypes.h \
+ ../cmd.src/commandcl.h ../cmd.src/newcmdcl.h ../gui.src/guicl.h \
+ ../gui.src/ifcl.h ../sim.src/guiobjcl.h ../sim.src/uccl.h ../stypes.h \
+ ../pobjt.h ../sim.src/hwcl.h ../sim.src/guiobjcl.h \
+ ../cmd.src/newcmdposixcl.h ../fiocl.h ../cmd.src/cmdutil.h \
+ ../sim.src/memcl.h ../eventcl.h ../errorcl.h ../sim.src/brkcl.h \
+ ../sim.src/stackcl.h ../sim.src/varcl.h ../sim.src/uccl_instructions.h \
+ ../sim.src/argcl.h ../sim.src/memcl.h ../sim.src/stackcl.h tlcscl.h \
+ ../sim.src/uccl.h glob.h
+inst_arith.o: inst_arith.cc tlcscl.h ../sim.src/uccl.h ../stypes.h \
+ ../ddconfig.h ../pobjcl.h ../pobjt.h ../eventcl.h ../charscl.h \
+ ../pobjt.h ../sim.src/hwcl.h ../sim.src/guiobjcl.h ../ddconfig.h \
+ ../cmd.src/newcmdcl.h ../optioncl.h ../pobjcl.h ../stypes.h \
+ ../cmd.src/commandcl.h ../cmd.src/newcmdcl.h ../cmd.src/newcmdposixcl.h \
+ ../fiocl.h ../cmd.src/cmdutil.h ../sim.src/memcl.h ../eventcl.h \
+ ../errorcl.h ../sim.src/uccl.h ../sim.src/brkcl.h ../sim.src/stackcl.h \
+ ../sim.src/varcl.h ../sim.src/uccl_instructions.h ../sim.src/memcl.h
+inst_jump.o: inst_jump.cc tlcscl.h ../sim.src/uccl.h ../stypes.h \
+ ../ddconfig.h ../pobjcl.h ../pobjt.h ../eventcl.h ../charscl.h \
+ ../pobjt.h ../sim.src/hwcl.h ../sim.src/guiobjcl.h ../ddconfig.h \
+ ../cmd.src/newcmdcl.h ../optioncl.h ../pobjcl.h ../stypes.h \
+ ../cmd.src/commandcl.h ../cmd.src/newcmdcl.h ../cmd.src/newcmdposixcl.h \
+ ../fiocl.h ../cmd.src/cmdutil.h ../sim.src/memcl.h ../eventcl.h \
+ ../errorcl.h ../sim.src/uccl.h ../sim.src/brkcl.h ../sim.src/stackcl.h \
+ ../sim.src/varcl.h ../sim.src/uccl_instructions.h ../sim.src/memcl.h
+simtlcs.o: simtlcs.cc ../appcl.h ../ddconfig.h ../pobjcl.h ../pobjt.h \
+ ../eventcl.h ../charscl.h ../optioncl.h ../stypes.h ../sim.src/argcl.h \
+ ../pobjcl.h ../stypes.h ../sim.src/simcl.h ../cmd.src/newcmdcl.h \
+ ../ddconfig.h ../optioncl.h ../cmd.src/commandcl.h ../cmd.src/newcmdcl.h \
+ ../gui.src/guicl.h ../gui.src/ifcl.h ../sim.src/guiobjcl.h \
+ ../sim.src/uccl.h ../pobjt.h ../sim.src/hwcl.h ../sim.src/guiobjcl.h \
+ ../cmd.src/newcmdposixcl.h ../fiocl.h ../cmd.src/cmdutil.h \
+ ../sim.src/memcl.h ../eventcl.h ../errorcl.h ../sim.src/brkcl.h \
+ ../sim.src/stackcl.h ../sim.src/varcl.h ../sim.src/uccl_instructions.h \
+ ../sim.src/argcl.h simtlcscl.h tlcscl.h ../sim.src/uccl.h \
+ ../sim.src/memcl.h
+glob.o: glob.cc glob.h ../stypes.h ../ddconfig.h
+inst_bit.o: inst_bit.cc tlcscl.h ../sim.src/uccl.h ../stypes.h \
+ ../ddconfig.h ../pobjcl.h ../pobjt.h ../eventcl.h ../charscl.h \
+ ../pobjt.h ../sim.src/hwcl.h ../sim.src/guiobjcl.h ../ddconfig.h \
+ ../cmd.src/newcmdcl.h ../optioncl.h ../pobjcl.h ../stypes.h \
+ ../cmd.src/commandcl.h ../cmd.src/newcmdcl.h ../cmd.src/newcmdposixcl.h \
+ ../fiocl.h ../cmd.src/cmdutil.h ../sim.src/memcl.h ../eventcl.h \
+ ../errorcl.h ../sim.src/uccl.h ../sim.src/brkcl.h ../sim.src/stackcl.h \
+ ../sim.src/varcl.h ../sim.src/uccl_instructions.h ../sim.src/memcl.h
+stlcs.o: stlcs.cc ../globals.h ../ddconfig.h ../stypes.h ../appcl.h \
+ ../pobjcl.h ../pobjt.h ../eventcl.h ../charscl.h ../optioncl.h \
+ ../sim.src/argcl.h ../pobjcl.h ../stypes.h ../sim.src/simcl.h \
+ ../cmd.src/newcmdcl.h ../ddconfig.h ../optioncl.h ../cmd.src/commandcl.h \
+ ../cmd.src/newcmdcl.h ../gui.src/guicl.h ../gui.src/ifcl.h \
+ ../sim.src/guiobjcl.h ../sim.src/uccl.h ../pobjt.h ../sim.src/hwcl.h \
+ ../sim.src/guiobjcl.h ../cmd.src/newcmdposixcl.h ../fiocl.h \
+ ../cmd.src/cmdutil.h ../sim.src/memcl.h ../eventcl.h ../errorcl.h \
+ ../sim.src/brkcl.h ../sim.src/stackcl.h ../sim.src/varcl.h \
+ ../sim.src/uccl_instructions.h ../sim.src/argcl.h ../appcl.h simtlcscl.h
+inst_move.o: inst_move.cc tlcscl.h ../sim.src/uccl.h ../stypes.h \
+ ../ddconfig.h ../pobjcl.h ../pobjt.h ../eventcl.h ../charscl.h \
+ ../pobjt.h ../sim.src/hwcl.h ../sim.src/guiobjcl.h ../ddconfig.h \
+ ../cmd.src/newcmdcl.h ../optioncl.h ../pobjcl.h ../stypes.h \
+ ../cmd.src/commandcl.h ../cmd.src/newcmdcl.h ../cmd.src/newcmdposixcl.h \
+ ../fiocl.h ../cmd.src/cmdutil.h ../sim.src/memcl.h ../eventcl.h \
+ ../errorcl.h ../sim.src/uccl.h ../sim.src/brkcl.h ../sim.src/stackcl.h \
+ ../sim.src/varcl.h ../sim.src/uccl_instructions.h ../sim.src/memcl.h
diff --git a/sim/ucsim/tlcs.src/Makefile.in b/sim/ucsim/tlcs.src/Makefile.in
new file mode 100644
index 0000000..0562723
--- /dev/null
+++ b/sim/ucsim/tlcs.src/Makefile.in
@@ -0,0 +1,154 @@
+#
+# uCsim tlcs.src/Makefile
+#
+# (c) Drotos Daniel, Talker Bt. 1997
+#
+#
+
+STARTYEAR	= 2016
+
+SHELL		= /bin/sh
+CXX		= @CXX@
+CPP		= @CPP@
+CXXCPP		= @CXXCPP@
+RANLIB		= @RANLIB@
+INSTALL		= @INSTALL@
+STRIP		= @STRIP@
+MAKEDEP         = @MAKEDEP@
+
+top_builddir	= @top_builddir@
+top_srcdir	= @top_srcdir@
+
+transform	= @program_transform_name@
+
+DEFS            = $(subs -DHAVE_CONFIG_H,,@DEFS@)
+CPPFLAGS        = @CPPFLAGS@ -I$(srcdir) -I$(top_srcdir) -I$(top_builddir) \
+		  -I$(top_srcdir)/cmd.src -I$(top_srcdir)/sim.src \
+		  -I$(top_srcdir)/gui.src
+CFLAGS          = @CFLAGS@ @WALL_FLAG@
+CXXFLAGS        = @CXXFLAGS@ @WALL_FLAG@
+LDFLAGS         = @LDFLAGS@
+PICOPT		= @PICOPT@
+SHAREDLIB	= @SHAREDLIB@
+EXEEXT		= @EXEEXT@
+
+LIBS		= -L$(top_builddir) -lsim -lucsimutil -lguiucsim -lcmd -lsim @LIBS@
+DL		= @DL@
+dl_ok		= @dl_ok@
+
+prefix          = @prefix@
+exec_prefix     = @exec_prefix@
+bindir          = @bindir@
+libdir          = @libdir@
+datadir         = @datadir@
+datarootdir     = @datarootdir@
+includedir      = @includedir@
+mandir          = @mandir@
+man1dir         = $(mandir)/man1
+man2dir         = $(mandir)/man2
+infodir         = @infodir@
+srcdir          = @srcdir@
+VPATH           = @srcdir@
+
+OBJECTS_SHARED	= glob.o \
+		  simtlcs.o tlcs.o \
+		  inst_block.o inst_cpu_others.o inst_rot_sh.o \
+		  inst_jump.o inst_move.o inst_arith.o inst_bit.o
+OBJECTS_EXE	= stlcs.o
+OBJECTS		= $(OBJECTS_SHARED) $(OBJECTS_EXE)
+
+enable_dlso	= @enable_dlso@
+dlso_ok		= @dlso_ok@
+
+
+# Compiling entire program or any subproject
+# ------------------------------------------
+all: checkconf otherlibs tlcs.src
+
+
+# Compiling and installing everything and runing test
+# ---------------------------------------------------
+install: all installdirs
+	$(INSTALL) stlcs$(EXEEXT) $(DESTDIR)$(bindir)/`echo stlcs|sed '$(transform)'`$(EXEEXT)
+	$(STRIP) $(DESTDIR)$(bindir)/`echo stlcs|sed '$(transform)'`$(EXEEXT)
+
+
+# Deleting all the installed files
+# --------------------------------
+uninstall:
+	rm -f $(DESTDIR)$(bindir)/stlcs
+	rm -f $(DESTDIR)$(bindir)/`echo stlcs|sed '$(transform)'`$(EXEEXT)
+
+
+# Performing self-test
+# --------------------
+check: $(TEST_OBJ)
+
+test:
+
+
+# Performing installation test
+# ----------------------------
+installcheck:
+
+
+# Creating installation directories
+# ---------------------------------
+installdirs:
+	test -d $(DESTDIR)$(bindir) || $(INSTALL) -d $(DESTDIR)$(bindir)
+
+
+# Creating dependencies
+# ---------------------
+dep: Makefile.dep
+
+Makefile.dep: $(srcdir)/*.cc $(srcdir)/*.h
+	$(MAKEDEP) $(CPPFLAGS) $(filter %.cc,$^) >Makefile.dep
+
+-include Makefile.dep
+include $(srcdir)/clean.mk
+
+# My rules
+# --------
+tlcs.src: stlcs$(EXEEXT) shared_lib
+
+stlcs$(EXEEXT): $(OBJECTS) $(top_builddir)/libcmd.a $(top_builddir)/libguiucsim.a $(top_builddir)/libsim.a $(top_builddir)/libucsimutil.a
+	$(CXX) $(CXXFLAGS) $(LDFLAGS) $(OBJECTS) $(LIBS) -o $@
+
+ifeq ($(dlso_ok),yes)
+shared_lib: $(top_builddir)/stlcs.so
+else
+shared_lib:
+	@$(top_srcdir)/mkecho $(top_builddir) "No TLCS shared lib made."
+	@$(top_srcdir)/mkecho $(top_builddir) "(SHAREDLIB="$(SHAREDLIB)",dl_ok="$(dl_ok)",enable_dlso="$(enable_dlso)")"
+endif
+
+$(top_builddir)/stlcs.so: $(OBJECTS_SHARED)
+	$(CXX) -shared $(LDFLAGS) $(OBJECTS_SHARED) -o $@
+
+otherlibs: $(top_builddir)/libcmd.a $(top_builddir)/libguiucsim.a $(top_builddir)/libsim.a $(top_builddir)/libucsimutil.a
+
+$(top_builddir)/libcmd.a:
+	$(MAKE) -C $(top_builddir)/cmd.src all
+
+$(top_builddir)/libguiucsim.a:
+	$(MAKE) -C $(top_builddir)/gui.src checkconf ucsim_lib
+
+$(top_builddir)/libsim.a:
+	$(MAKE) -C $(top_builddir)/sim.src all
+
+$(top_builddir)/libucsimutil.a:
+	$(MAKE) -C $(top_builddir) -f main.mk
+
+.cc.o:
+	$(CXX) $(CXXFLAGS) $(PICOPT) $(CPPFLAGS) $(TARGET_ARCH) -c $< -o $@
+
+
+# Remaking configuration
+# ----------------------
+checkconf:
+	@if [ -f $(top_builddir)/devel ]; then\
+	  $(MAKE) -C $(top_builddir) -f conf.mk srcdir="$(srcdir)" top_builddir="$(top_builddir)" freshconf;\
+	fi
+
+# End of tlcs.src/Makefile.in
diff --git a/sim/ucsim/tlcs.src/clean.mk b/sim/ucsim/tlcs.src/clean.mk
new file mode 100644
index 0000000..8324859
--- /dev/null
+++ b/sim/ucsim/tlcs.src/clean.mk
@@ -0,0 +1,31 @@
+# tlcs.src/clean.mk
+#
+#
+
+# Deleting all files created by building the program
+# --------------------------------------------------
+clean:
+	rm -f *core *[%~] *.[oa] *.map
+	rm -f .[a-z]*~
+	rm -f stlcs$(EXEEXT)
+
+
+# Deleting all files created by configuring or building the program
+# -----------------------------------------------------------------
+distclean: clean
+	rm -f config.cache config.log config.status
+	rm -f Makefile *.dep
+	rm -f *.obj *.list *.lst *.hex
+
+
+# Like clean but some files may still exist
+# -----------------------------------------
+mostlyclean: clean
+
+
+# Deleting everything that can reconstructed by this Makefile. It deletes
+# everything deleted by distclean plus files created by bison, etc.
+# -----------------------------------------------------------------------
+realclean: distclean
+
+# End of tlcs.src/clean.mk
diff --git a/sim/ucsim/tlcs.src/conf.mk b/sim/ucsim/tlcs.src/conf.mk
new file mode 100644
index 0000000..000486e
--- /dev/null
+++ b/sim/ucsim/tlcs.src/conf.mk
@@ -0,0 +1,11 @@
+# tlcs.src/conf.mk
+#
+# Makefile targets to remake configuration
+#
+
+freshconf: Makefile
+
+Makefile: $(srcdir)/Makefile.in $(top_srcdir)/configure.ac
+	cd $(top_builddir) && $(SHELL) ./config.status
+
+# End of tlcs.src/conf.mk
diff --git a/sim/ucsim/tlcs.src/glob.cc b/sim/ucsim/tlcs.src/glob.cc
new file mode 100644
index 0000000..1948ed4
--- /dev/null
+++ b/sim/ucsim/tlcs.src/glob.cc
@@ -0,0 +1,487 @@
+/*
+ * Simulator of microcontrollers (tlcs.src/glob.cc)
+ *
+ * Copyright (C) 2016,16 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#include <stdio.h>
+
+#include "glob.h"
+
+struct dis_entry disass_tlcs[]= {
+  { 0x00, 0xff, ' ', 1, "NOP" },
+  { 0x01, 0xff, ' ', 1, "HALT" },
+  { 0x02, 0xff, ' ', 1, "DI" },
+  { 0x03, 0xff, ' ', 1, "EI" },
+  { 0x08, 0xff, ' ', 1, "EX DE,HL" },
+  { 0x09, 0xff, ' ', 1, "EX AF,AF'" },
+  { 0x0a, 0xff, ' ', 1, "EXX" },
+  { 0x0b, 0xff, ' ', 1, "DAA A" },
+  { 0x0c, 0xff, ' ', 1, "RCF" },
+  { 0x0d, 0xff, ' ', 1, "SCF" },
+  { 0x0e, 0xff, ' ', 1, "CCF" },
+  { 0x10, 0xff, ' ', 1, "CPL A" },
+  { 0x11, 0xff, ' ', 1, "NEG A" },
+  { 0x000017, 0x0000ff, 'D', 3, "LDAR HL,%D" },
+  { 0x1e, 0xff, ' ', 1, "RET" },
+  { 0x1f, 0xff, ' ', 1, "RETI" },
+  { 0x000037, 0x0000ff, 'n', 3, "LD (0xff%n),%N" },
+  { 0x00003f, 0x0000ff, 'm', 3, "LDW (0xff%n),%m" },
+  { 0x0097, 0x00ff, 'n', 2, "INCW (0xff%n)" },
+  { 0x009F, 0x00ff, 'n', 2, "DECW (0xff%n)" },
+  { 0xa0, 0xff, ' ', 1, "RLCA" },
+  { 0xa1, 0xff, ' ', 1, "RRCA" },
+  { 0xa2, 0xff, ' ', 1, "RLA" },
+  { 0xa3, 0xff, ' ', 1, "RRA" },
+  { 0xa4, 0xff, ' ', 1, "SLAA" },
+  { 0xa5, 0xff, ' ', 1, "SRAA" },
+  { 0xa6, 0xff, ' ', 1, "SLLA" },
+  { 0xa7, 0xff, ' ', 1, "SRLA" },
+  { 0xff, 0xff, ' ', 1, "SWI", true },
+  /* E3 group */
+  { 0x100000e3, 0xff0000ff, ' ', 4, "RLD (%M)" },
+  { 0x110000e3, 0xff0000ff, ' ', 4, "RRD (%M)" },
+  { 0x120000e3, 0xff0000ff, ' ', 4, "MUL HL,(%M)" },
+  { 0x130000e3, 0xff0000ff, ' ', 4, "DIV HL,(%M)" },
+  { 0x600000e3, 0xff0000ff, ' ', 4, "ADD A,(%M)" },
+  { 0x610000e3, 0xff0000ff, ' ', 4, "ADC A,(%M)" },
+  { 0x620000e3, 0xff0000ff, ' ', 4, "SUB A,(%M)" },
+  { 0x630000e3, 0xff0000ff, ' ', 4, "SBC A,(%M)" },
+  { 0x640000e3, 0xff0000ff, ' ', 4, "AND A,(%M)" },
+  { 0x650000e3, 0xff0000ff, ' ', 4, "XOR A,(%M)" },
+  { 0x660000e3, 0xff0000ff, ' ', 4, "OR A,(%M)" },
+  { 0x670000e3, 0xff0000ff, ' ', 4, "CP A,(%M)" },
+  { 0x700000e3, 0xff0000ff, ' ', 4, "ADD HL,(%M)" },
+  { 0x710000e3, 0xff0000ff, ' ', 4, "ADC HL,(%M)" },
+  { 0x720000e3, 0xff0000ff, ' ', 4, "SUB HL,(%M)" },
+  { 0x730000e3, 0xff0000ff, ' ', 4, "SBC HL,(%M)" },
+  { 0x740000e3, 0xff0000ff, ' ', 4, "AND HL,(%M)" },
+  { 0x750000e3, 0xff0000ff, ' ', 4, "XOR HL,(%M)" },
+  { 0x760000e3, 0xff0000ff, ' ', 4, "OR HL,(%M)" },
+  { 0x770000e3, 0xff0000ff, ' ', 4, "CP HL,(%M)" },
+  { 0x870000e3, 0xff0000ff, ' ', 4, "INC (%M)" },
+  { 0x8F0000e3, 0xff0000ff, ' ', 4, "DEC (%M)" },
+  { 0x970000e3, 0xff0000ff, ' ', 4, "INCW (%M)" },
+  { 0x9F0000e3, 0xff0000ff, ' ', 4, "DECW (%M)" },
+  { 0xA00000e3, 0xff0000ff, ' ', 4, "RLC (%M)" },
+  { 0xA10000e3, 0xff0000ff, ' ', 4, "RRC (%M)" },
+  { 0xA20000e3, 0xff0000ff, ' ', 4, "RL (%M)" },
+  { 0xA30000e3, 0xff0000ff, ' ', 4, "RR (%M)" },
+  { 0xA40000e3, 0xff0000ff, ' ', 4, "SLA (%M)" },
+  { 0xA50000e3, 0xff0000ff, ' ', 4, "SRA (%M)" },
+  { 0xA60000e3, 0xff0000ff, ' ', 4, "SLL (%M)" },
+  { 0xA70000e3, 0xff0000ff, ' ', 4, "SRL (%M)" },
+  { 0x140000e3, 0xfc0000ff, ' ', 4, "ADD %J,(%M)" },
+  { 0x180000e3, 0xf80000ff, ' ', 4, "TSET %e,(%M)" },
+  { 0x280000e3, 0xf80000ff, ' ', 4, "LD %T,(%M)" },
+  { 0x480000e3, 0xf80000ff, ' ', 4, "LD %U,(nm)" },
+  { 0x500000e3, 0xf80000ff, ' ', 4, "ex (%M),rr" },
+  { 0xA80000e3, 0xf80000ff, ' ', 4, "BIT %e,(%M)" },
+  { 0xB00000e3, 0xf80000ff, ' ', 4, "RES %e,(%M)" },
+  { 0xB80000e3, 0xf80000ff, ' ', 4, "SET %e,(%M)" }, 
+  /* E7 group */
+  { 0x1000e7, 0xff00ff, 'n', 3, "RLD (0xff%n)" },
+  { 0x1100e7, 0xff00ff, 'n', 3, "RRD (0xff%n)" },
+  { 0x1200e7, 0xff00ff, 'n', 3, "MUL HL,(0xff%n)" },
+  { 0x1300e7, 0xff00ff, 'n', 3, "DIV HL,(0xff%n)" },
+  { 0xA000e7, 0xff00ff, 'n', 3, "RLC (0xff%n)" },
+  { 0xA100e7, 0xff00ff, 'n', 3, "RRC (0xff%n)" },
+  { 0xA200e7, 0xff00ff, 'n', 3, "RL (0xff%n)" },
+  { 0xA300e7, 0xff00ff, 'n', 3, "RR (0xff%n)" },
+  { 0xA400e7, 0xff00ff, 'n', 3, "SLA (0xff%n)" },
+  { 0xA500e7, 0xff00ff, 'n', 3, "SRA (0xff%n)" },
+  { 0xA600e7, 0xff00ff, 'n', 3, "SLL (0xff%n)" },
+  { 0xA700e7, 0xff00ff, 'n', 3, "SRL (0xff%n)" },
+  { 0x1400e7, 0xfc00ff, 'n', 3, "ADD %j,(0xff%n)" },
+  { 0x1800e7, 0xf800ff, 'n', 3, "TSET %B,(0xff%n)" },
+  { 0x2800e7, 0xf800ff, 'n', 3, "LD %t,(0xff%n)" },
+  { 0x4800e7, 0xf800ff, 'n', 3, "LD %u,(0xff%n)" },
+  { 0x5000e7, 0xf800ff, 'n', 3, "EX (0xff%n),%u" },
+  /* EB group */
+  {   0x00370000eb,   0x00ff0000ff, ' ', 5, "LD (%M),%O" },
+  { 0x00003F0000eb, 0x0000ff0000ff, ' ', 6, "LDW (%M),%x" },
+  {   0x00680000eb,   0x00ff0000ff, ' ', 5, "ADD (%M),%O" },
+  {   0x00690000eb,   0x00ff0000ff, ' ', 5, "ADC (%M),%O" },
+  {   0x006A0000eb,   0x00ff0000ff, ' ', 5, "SUB (%M),%O" },
+  {   0x006B0000eb,   0x00ff0000ff, ' ', 5, "SBC (%M),%O" },
+  {   0x006C0000eb,   0x00ff0000ff, ' ', 5, "AND (%M),%O" },
+  {   0x006D0000eb,   0x00ff0000ff, ' ', 5, "XOR (%M),%O" },
+  {   0x006E0000eb,   0x00ff0000ff, ' ', 5, "OR (%M),%O" },
+  {   0x006F0000eb,   0x00ff0000ff, ' ', 5, "CP (%M),%O" },
+  {     0x200000eb,     0xf80000ff, ' ', 4, "LD (%M),%T" },
+  {     0x400000eb,     0xf80000ff, ' ', 4, "LD (%M),%U" },
+  {     0xC00000eb,   0x00f00000ff, ' ', 4, "JP %f%M" },
+  {     0xD00000eb,   0x00f00000ff, ' ', 4, "CALL %f%M", true },
+  /* EF group */
+  { 0x006800ef, 0x00ff00ff, ' ', 4, "ADD (0xff%n),%o" },
+  { 0x006900ef, 0x00ff00ff, ' ', 4, "ADC (0xff%n),%o" },
+  { 0x006a00ef, 0x00ff00ff, ' ', 4, "SUB (0xff%n),%o" },
+  { 0x006b00ef, 0x00ff00ff, ' ', 4, "SBC (0xff%n),%o" },
+  { 0x006c00ef, 0x00ff00ff, ' ', 4, "AND (0xff%n),%o" },
+  { 0x006d00ef, 0x00ff00ff, ' ', 4, "XOR (0xff%n),%o" },
+  { 0x006e00ef, 0x00ff00ff, ' ', 4, "OR (0xff%n),%o" },
+  { 0x006f00ef, 0x00ff00ff, ' ', 4, "CP (0xff%n),%o" },
+  {   0x2000ef,   0xf800ff, ' ', 3, "LD (0xff%n),%t" },
+  {   0x4000ef,   0xf800ff, ' ', 3, "LD (0xff%n),%u" },
+  /* F3 group */
+  { 0x10f3, 0xffff, ' ', 2, "RLD (HL+A)" },
+  { 0x11f3, 0xffff, ' ', 2, "RRD (HL+A)" },
+  { 0x12f3, 0xffff, ' ', 2, "MUL HL,(HL+A)" },
+  { 0x13f3, 0xffff, ' ', 2, "DIV HL,(HL+A)" },
+  { 0x60f3, 0xffff, ' ', 2, "ADD A,(HL+A)" },
+  { 0x61f3, 0xffff, ' ', 2, "ADC A,(HL+A)" },
+  { 0x62f3, 0xffff, ' ', 2, "SUB A,(HL+A)" },
+  { 0x63f3, 0xffff, ' ', 2, "SBC A,(HL+A)" },
+  { 0x64f3, 0xffff, ' ', 2, "AND A,(HL+A)" },
+  { 0x65f3, 0xffff, ' ', 2, "XOR A,(HL+A)" },
+  { 0x66f3, 0xffff, ' ', 2, "OR A,(HL+A)" },
+  { 0x67f3, 0xffff, ' ', 2, "CP A,(HL+A)" },
+  { 0x70f3, 0xffff, ' ', 2, "ADD HL,(HL+A)" },
+  { 0x71f3, 0xffff, ' ', 2, "ADC HL,(HL+A)" },
+  { 0x72f3, 0xffff, ' ', 2, "SUB HL,(HL+A)" },
+  { 0x73f3, 0xffff, ' ', 2, "SBC HL,(HL+A)" },
+  { 0x74f3, 0xffff, ' ', 2, "AND HL,(HL+A)" },
+  { 0x75f3, 0xffff, ' ', 2, "XOR HL,(HL+A)" },
+  { 0x76f3, 0xffff, ' ', 2, "OR HL,(HL+A)" },
+  { 0x77f3, 0xffff, ' ', 2, "CP HL,(HL+A)" },
+  { 0x87f3, 0xffff, ' ', 2, "INC (HL+A)" },
+  { 0x8ff3, 0xffff, ' ', 2, "DEC (HL+A)" },
+  { 0x97f3, 0xffff, ' ', 2, "INCW (HL+A)" },
+  { 0x9ff3, 0xffff, ' ', 2, "DECW (HL+A)" },
+  { 0xa0f3, 0xffff, ' ', 2, "RLC (HL+A)" },
+  { 0xa1f3, 0xffff, ' ', 2, "RRC (HL+A)" },
+  { 0xa2f3, 0xffff, ' ', 2, "RL (HL+A)" },
+  { 0xa3f3, 0xffff, ' ', 2, "RR (HL+A)" },
+  { 0xa4f3, 0xffff, ' ', 2, "SLA (HL+A)" },
+  { 0xa5f3, 0xffff, ' ', 2, "SRA (HL+A)" },
+  { 0xa6f3, 0xffff, ' ', 2, "SLL (HL+A)" },
+  { 0xa7f3, 0xffff, ' ', 2, "SRL (HL+A)" },
+  { 0x14f3, 0xfcff, 'i', 2, "ADD %i,(HL+A)" },
+  { 0x18f3, 0xf8ff, 'b', 2, "TSET %b,(HL+A)" },
+  { 0x28f3, 0xf8ff, 'p', 2, "LD %p,(HL+A)" },
+  { 0x48f3, 0xf8ff, 's', 2, "LD %s,(HL+A)" },
+  { 0x50f3, 0xf8ff, 's', 2, "EX (HL+A),%s" },
+  { 0xa8f3, 0xf8ff, 'b', 2, "BIT %b,(HL+A)" },
+  { 0xb0f3, 0xf8ff, 'b', 2, "RES %b,(HL+A)" },
+  { 0xb8f3, 0xf8ff, 'b', 2, "SET %b,(HL+A)" },
+  /* F7 group */
+  { 0x0037f7, 0x00ffff, 'n', 3, "LD (HL+A),%N" },
+  { 0x00003Ff7, 0x0000ffff, 'm', 4, "LDW (HL+A),%m" },
+  { 0x0068f7, 0x00ffff, 'n', 3, "ADD (HL+A),%N" },
+  { 0x0069f7, 0x00ffff, 'n', 3, "ADC (HL+A),%N" },
+  { 0x006Af7, 0x00ffff, 'n', 3, "SUB (HL+A),%N" },
+  { 0x006Bf7, 0x00ffff, 'n', 3, "SBC (HL+A),%N" },
+  { 0x006Cf7, 0x00ffff, 'n', 3, "AND (HL+A),%N" },
+  { 0x006Df7, 0x00ffff, 'n', 3, "XOR (HL+A),%N" },
+  { 0x006Ef7, 0x00ffff, 'n', 3, "OR (HL+A),%N" },
+  { 0x006Ff7, 0x00ffff, 'n', 3, "CP (HL+A),%N" },
+  { 0xc0f7, 0xf0ff, 'c', 2, "JP %cHL+A" },
+  { 0xd0f7, 0xf0ff, 'c', 2, "CALL %cHL+A", true },
+  { 0x20f7, 0xf8ff, 'p', 2, "LD (HL+A),%p" },
+  { 0x38f7, 0xf8ff, 's', 2, "LDA %s,HL+A" },
+  { 0x40f7, 0xf8ff, 's', 2, "LD (HL+A),%s" },
+  /* FE group */
+  { 0x58fe, 0xffff, ' ', 2, "LDI" },
+  { 0x59fe, 0xffff, ' ', 2, "LDIR" },
+  { 0x5afe, 0xffff, ' ', 2, "LDD" },
+  { 0x5bfe, 0xffff, ' ', 2, "LDDR" },
+  { 0x5cfe, 0xffff, ' ', 2, "CPI" },
+  { 0x5dfe, 0xffff, ' ', 2, "CPIR" },
+  { 0x5efe, 0xffff, ' ', 2, "CPD" },
+  { 0x5ffe, 0xffff, ' ', 2, "CPDR" },
+  { 0xd0fe, 0xf0ff, 'C', 2, "RET %C" },
+
+  /* Others in exec_inst: c1&0xfc */
+  { 0x000014, 0x0000fc, 'm', 3, "ADD %I,%M" },
+  /* F0+ix group */
+  { 0x1000f0, 0xff00fc, 'd', 3, "RLD (%I%d)" },
+  { 0x1100f0, 0xff00fc, 'd', 3, "RRD (%I%d)" },
+  { 0x1200f0, 0xff00fc, 'd', 3, "MUL HL,(%I%d)" },
+  { 0x1300f0, 0xff00fc, 'd', 3, "DIV HL,(%I%d)" },
+  { 0x6000f0, 0xff00fc, 'd', 3, "ADD A,(%I%d)" },
+  { 0x6100f0, 0xff00fc, 'd', 3, "ADC A,(%I%d)" },
+  { 0x6200f0, 0xff00fc, 'd', 3, "SUB A,(%I%d)" },
+  { 0x6300f0, 0xff00fc, 'd', 3, "SBC A,(%I%d)" },
+  { 0x6400f0, 0xff00fc, 'd', 3, "AND A,(%I%d)" },
+  { 0x6500f0, 0xff00fc, 'd', 3, "XOR A,(%I%d)" },
+  { 0x6600f0, 0xff00fc, 'd', 3, "OR A,(%I%d)" },
+  { 0x6700f0, 0xff00fc, 'd', 3, "CP A,(%I%d)" },
+  { 0x7000f0, 0xff00fc, 'd', 3, "ADD HL,(%I%d)" },
+  { 0x7100f0, 0xff00fc, 'd', 3, "ADC HL,(%I%d)" },
+  { 0x7200f0, 0xff00fc, 'd', 3, "SUB HL,(%I%d)" },
+  { 0x7300f0, 0xff00fc, 'd', 3, "SBC HL,(%I%d)" },
+  { 0x7400f0, 0xff00fc, 'd', 3, "AND HL,(%I%d)" },
+  { 0x7500f0, 0xff00fc, 'd', 3, "XOR HL,(%I%d)" },
+  { 0x7600f0, 0xff00fc, 'd', 3, "OR HL,(%I%d)" },
+  { 0x7700f0, 0xff00fc, 'd', 3, "CP HL,(%I%d)" },
+  { 0x8700f0, 0xff00fc, 'd', 3, "INC (%I%d)" },
+  { 0x8F00f0, 0xff00fc, 'd', 3, "DEC (%I%d)" },
+  { 0x9700f0, 0xff00fc, 'd', 3, "INCW (%I%d)" },
+  { 0x9F00f0, 0xff00fc, 'd', 3, "DECW (%I%d)" },
+  { 0xA000f0, 0xff00fc, 'd', 3, "RLC (%I%d)" },
+  { 0xA100f0, 0xff00fc, 'd', 3, "RRC (%I%d)" },
+  { 0xA200f0, 0xff00fc, 'd', 3, "RL (%I%d)" },
+  { 0xA300f0, 0xff00fc, 'd', 3, "RR (%I%d)" },
+  { 0xA400f0, 0xff00fc, 'd', 3, "SLA (%I%d)" },
+  { 0xA500f0, 0xff00fc, 'd', 3, "SRA (%I%d)" },
+  { 0xA600f0, 0xff00fc, 'd', 3, "SLL (%I%d)" },
+  { 0xA700f0, 0xff00fc, 'd', 3, "SRL (%I%d)" },
+  { 0x1400f0, 0xfc00fc, 'd', 3, "ADD %j,(%I%d)" },
+  { 0x1800f0, 0xf800fc, 'd', 3, "TSET %B,(%I%d)" },
+  { 0x2800f0, 0xf800fc, 'd', 3, "LD %t,(%I%d)" },
+  { 0x4800f0, 0xf800fc, 'd', 3, "LD %u,(%I%d)" },
+  { 0x5000f0, 0xf800fc, 'd', 3, "EX (%I%d),%u" },
+  { 0xA800f0, 0xf800fc, 'd', 3, "BIT %B,(%I%d)" },
+  { 0xB000f0, 0xf800fc, 'd', 3, "RES %B,(%I%d)" },
+  { 0xB800f0, 0xf800fc, 'd', 3, "SET %B,(%I%d)" },
+  /* F4+ix group */
+  {   0x003700f4,   0x00ff00fc, ' ', 4, "LD (%I%d),%o" },
+  { 0x00003F00f4, 0x0000ff00fc, ' ', 5, "LDW (%I%d),%X" },
+  {   0x006800f4,   0x00ff00fc, ' ', 4, "ADD (%I%d),%o" },
+  {   0x006900f4,   0x00ff00fc, ' ', 4, "ADC (%I%d),%o" },
+  {   0x006A00f4,   0x00ff00fc, ' ', 4, "SUB (%I%d),%o" },
+  {   0x006B00f4,   0x00ff00fc, ' ', 4, "SBC (%I%d),%o" },
+  {   0x006C00f4,   0x00ff00fc, ' ', 4, "AND (%I%d),%o" },
+  {   0x006D00f4,   0x00ff00fc, ' ', 4, "XOR (%I%d),%o" },
+  {   0x006E00f4,   0x00ff00fc, ' ', 4, "OR (%I%d),%o" },
+  {   0x006F00f4,   0x00ff00fc, ' ', 4, "CP (%I%d),%o" },
+  {     0xC000f4,     0xf000fc, ' ', 3, "JP %F%I%d" },
+  {     0xD000f4,     0xf000fc, ' ', 3, "CALL %F%I%d", true },
+  {     0x2000f4,     0xf800fc, ' ', 3, "LD (%I%d),%t" },
+  {     0x3800f4,     0xf800fc, ' ', 3, "LDA %u,%I%d" },
+  {     0x4000f4,     0xf800fc, ' ', 4, "LD (%I%d),%u" },
+  /* Others in exec_inst: c1&0xf8 */
+  { 0x20, 0xf8, 'r', 1, "LD A,%r" },
+  { 0x28, 0xf8, 'r', 1, "LD %r,A" },
+  { 0x000038, 0x0000f8, 'm', 3, "LD %R,%M" },
+  { 0x40, 0xf8, 'R', 1, "LD HL,%R" },
+  { 0x48, 0xf8, 'R', 1, "LD %R,HL" },
+  { 0x50, 0xf8, 'Q', 1, "PUSH %Q" },
+  { 0x58, 0xf8, 'Q', 1, "POP %Q" },
+  { 0x80, 0xf8, 'r', 1, "INC %r" },
+  { 0x88, 0xf8, 'r', 1, "DEC %r" },
+  { 0x90, 0xf8, 'R', 1, "INC %R" },
+  { 0x98, 0xf8, 'R', 1, "DEC %R" },
+
+  /* exec_inst2 */
+  { 0x0007, 0x00ff, 'n', 2, "INCX (0xff%n)" },
+  { 0x000F, 0x00ff, 'n', 2, "DECX (0xff%n)" },
+  { 0x0012, 0x00ff, 'n', 2, "MUL HL,%n" },
+  { 0x0013, 0x00ff, 'n', 2, "DIV HL,%n" },
+  { 0x0018, 0x00ff, 'd', 2, "DJNZ %1" },
+  { 0x0019, 0x00ff, 'd', 2, "DJNZ BC,%1" },
+  { 0x0027, 0x00ff, 'n', 2, "LD A,(0xff%n)" },
+  { 0x002F, 0x00ff, 'n', 2, "LD (0xff%n),A" },
+  { 0x0047, 0x00ff, 'n', 2, "LD HL,(0xff%n)" },
+  { 0x004f, 0x00ff, ' ', 2, "LD (0xff%n),HL" },
+  { 0x0060, 0x00ff, 'n', 2, "ADD A,(0xff%n)" },
+  { 0x0061, 0x00ff, 'n', 2, "ADC A,(0xff%n)" },
+  { 0x0062, 0x00ff, 'n', 2, "SUB A,(0xff%n)" },
+  { 0x0063, 0x00ff, 'n', 2, "SBC A,(0xff%n)" },
+  { 0x0064, 0x00ff, 'n', 2, "AND A,(0xff%n)" },
+  { 0x0065, 0x00ff, 'n', 2, "XOR A,(0xff%n)" },
+  { 0x0066, 0x00ff, 'n', 2, "OR A,(0xff%n)" },
+  { 0x0067, 0x00ff, 'n', 2, "CP A,(0xff%n)" },
+  { 0x0068, 0x00ff, 'n', 2, "ADD A,%n" },
+  { 0x0069, 0x00ff, 'n', 2, "ADC A,%n" },
+  { 0x006A, 0x00ff, 'n', 2, "SUB A,%n" },
+  { 0x006B, 0x00ff, 'n', 2, "SBC A,%n" },
+  { 0x006C, 0x00ff, 'n', 2, "AND A,%n" },
+  { 0x006D, 0x00ff, 'n', 2, "XOR A,%n" },
+  { 0x006E, 0x00ff, 'n', 2, "OR A,%n" },
+  { 0x006F, 0x00ff, 'n', 2, "CP A,%n" },
+  { 0x0070, 0x00ff, 'n', 2, "ADD HL,(0xff%n)" },
+  { 0x0071, 0x00ff, 'n', 2, "ADC HL,(0xff%n)" },
+  { 0x0072, 0x00ff, 'n', 2, "SUB HL,(0xff%n)" },
+  { 0x0073, 0x00ff, 'n', 2, "SBC HL,(0xff%n)" },
+  { 0x0074, 0x00ff, 'n', 2, "AND HL,(0xff%n)" },
+  { 0x0075, 0x00ff, 'n', 2, "XOR HL,(0xff%n)" },
+  { 0x0076, 0x00ff, 'n', 2, "OR HL,(0xff%n)" },
+  { 0x0077, 0x00ff, 'n', 2, "CP HL,(0xff%n)" },
+  { 0x0087, 0x00ff, 'n', 2, "INC (0xff%n)" },
+  { 0x008F, 0x00ff, 'n', 2, "DEC (0xff%n)" },
+  { 0x0030, 0x00f8, ' ', 2, "LD %r,%n" },
+  { 0x00a8, 0x00f8, ' ', 2, "BIT %a,(0xff%n)" },
+  { 0x00b0, 0x00f8, ' ', 2, "RES %a,(0xff%n)" },
+  { 0x00b8, 0x00f8, ' ', 2, "SET %a,(0xff%n)" },
+  /* E0+gg group in exec_inst2 */
+  { 0x10e0, 0xfff8, 'R', 2, "RLD (%R)" },
+  { 0x11e0, 0xfff8, 'R', 2, "RRD (%R)" },
+  { 0x12e0, 0xfff8, 'R', 2, "MUL HL,(%R)" },
+  { 0x13e0, 0xfff8, 'R', 2, "DIV HL,(%R)" },
+  { 0x14e0, 0xfcf8, 'R', 2, "ADD %i,(%R)" },
+  { 0x18e0, 0xf8f8, 'R', 2, "TSET %b,(%R)" },
+  { 0x28e0, 0xf8f8, 'R', 2, "LD %p,(%R)" },
+  { 0x48e0, 0xf8f8, 'R', 2, "LD %s,(%R)" },
+  { 0x50e0, 0xf8f8, 'R', 2, "EX (%R),%s" },
+  { 0xa8e0, 0xf8f8, 'R', 2, "BIT %b,(%R)" },
+  { 0xb0e0, 0xf8f8, 'R', 2, "RES %b,(%R)" },
+  { 0xb8e0, 0xf8f8, 'R', 2, "SET %b,(%R)" },
+  { 0x60e0, 0xfff8, 'R', 2, "ADD A,(%R)" },
+  { 0x61e0, 0xfff8, 'R', 2, "ADC A,(%R)" },
+  { 0x62e0, 0xfff8, 'R', 2, "SUB A,(%R)" },
+  { 0x63e0, 0xfff8, 'R', 2, "SBC A,(%R)" },
+  { 0x64e0, 0xfff8, 'R', 2, "AND A,(%R)" },
+  { 0x65e0, 0xfff8, 'R', 2, "XOR A,(%R)" },
+  { 0x66e0, 0xfff8, 'R', 2, "OR A,(%R)" },
+  { 0x67e0, 0xfff8, 'R', 2, "CP A,(%R)" },
+  { 0x70e0, 0xfff8, 'R', 2, "ADD HL,(%R)" },
+  { 0x71e0, 0xfff8, 'R', 2, "ADC HL,(%R)" },
+  { 0x72e0, 0xfff8, 'R', 2, "SUB HL,(%R)" },
+  { 0x73e0, 0xfff8, 'R', 2, "SBC HL,(%R)" },
+  { 0x70e0, 0xfff8, 'R', 2, "AND HL,(%R)" },
+  { 0x75e0, 0xfff8, 'R', 2, "XOR HL,(%R)" },
+  { 0x76e0, 0xfff8, 'R', 2, "OR HL,(%R)" },
+  { 0x77e0, 0xfff8, 'R', 2, "CP HL,(%R)" },
+  { 0x87e0, 0xfff8, 'R', 2, "INC (%R)" },
+  { 0x8fe0, 0xfff8, 'R', 2, "DEC (%R)" },
+  { 0x97e0, 0xfff8, 'R', 2, "INCW (%R)" },
+  { 0x9fe0, 0xfff8, 'R', 2, "DECW (%R)" },
+  { 0xa0e0, 0xfff8, 'R', 2, "RLC (%R)" },
+  { 0xa1e0, 0xfff8, 'R', 2, "RRC (%R)" },
+  { 0xa2e0, 0xfff8, 'R', 2, "RL (%R)" },
+  { 0xa3e0, 0xfff8, 'R', 2, "RR (%R)" },
+  { 0xa4e0, 0xfff8, 'R', 2, "SLA (%R)" },
+  { 0xa5e0, 0xfff8, 'R', 2, "SRA (%R)" },
+  { 0xa6e0, 0xfff8, 'R', 2, "SLL (%R)" },
+  { 0xa7e0, 0xfff8, 'R', 2, "SRL (%R)" },
+  { 0x14e0, 0xfcf8, ' ', 2, "ADD %i,(%R)" },
+  { 0x18e0, 0xf8f8, ' ', 2, "TSET %b,(%R)" },
+  { 0x28e0, 0xf8f8, ' ', 2, "LD %p,(%R)" },
+  { 0x48e0, 0xf8f8, ' ', 2, "LD %s,(%R)" },
+  { 0x50e0, 0xf8f8, ' ', 2, "EX (%R),rr" },
+  { 0xa8e0, 0xf8f8, ' ', 2, "BIT %b,(%R)" },
+  { 0xb0e0, 0xf8f8, ' ', 2, "RES %b,(%R)" },
+  { 0xb8e0, 0xf8f8, ' ', 2, "SET %b,(%R)" },  
+  /* E8+gg group in exec_inst2 */
+  { 0x0037e8, 0x00fff8, 'n', 3,	"LD (%R),%N" },
+  { 0x00003Fe8, 0x0000fff8, 'n', 4, "LDW (%R),%m" },
+  { 0x0068e8, 0x00fff8, 'n', 3,	"ADD (%R),%N" },
+  { 0x0069e8, 0x00fff8, 'n', 3,	"ADC (%R),%N" },
+  { 0x006Ae8, 0x00fff8, 'n', 3,	"SUB (%R),%N" },
+  { 0x006Be8, 0x00fff8, 'n', 3,	"SBC (%R),%N" },
+  { 0x006Ce8, 0x00fff8, 'n', 3,	"AND (%R),%N" },
+  { 0x006De8, 0x00fff8, 'n', 3,	"XOR (%R),%N" },
+  { 0x006Ee8, 0x00fff8, 'n', 3,	"OR (%R),%N" },
+  { 0x006Fe8, 0x00fff8, 'n', 3,	"CP (%R),%N" },
+  { 0xc0e8, 0xf0f8, 'R', 2, "JP %c%R" },
+  { 0xd0e8, 0xf0f8, 'R', 2, "CALL %c%R", true },
+  { 0x20e8, 0xf8f8, 'R', 2, "LD (%R),%p" },
+  { 0x40e8, 0xf8f8, 'R', 2, "LD (%R),%s" },
+  /* F8+gg group in exec_inst2 */
+  { 0x12f8, 0xfff8, 'g', 2, "MUL HL,%r" },
+  { 0x13f8, 0xfff8, 'g', 2, "DIV HL,%r" },
+  { 0x60f8, 0xfff8, 'g', 2, "ADD A,%r" },
+  { 0x61f8, 0xfff8, 'g', 2, "ADC A,%r" },
+  { 0x62f8, 0xfff8, 'g', 2, "SUB A,%r" },
+  { 0x63f8, 0xfff8, 'g', 2, "SBC A,%r" },
+  { 0x64f8, 0xfff8, 'g', 2, "AND A,%r" },
+  { 0x65f8, 0xfff8, 'g', 2, "XOR A,%r" },
+  { 0x66f8, 0xfff8, 'g', 2, "OR A,%r" },
+  { 0x67f8, 0xfff8, 'g', 2, "CP A,%r" },
+  { 0x70f8, 0xfff8, 'g', 2, "ADD HL,%R" },
+  { 0x71f8, 0xfff8, 'g', 2, "ADC HL,%R" },
+  { 0x72f8, 0xfff8, 'g', 2, "SUB HL,%R" },
+  { 0x73f8, 0xfff8, 'g', 2, "SBC HL,%R" },
+  { 0x74f8, 0xfff8, 'g', 2, "AND HL,%R" },
+  { 0x75f8, 0xfff8, 'g', 2, "XOR HL,%R" },
+  { 0x76f8, 0xfff8, 'g', 2, "OR HL,%R" },
+  { 0x77f8, 0xfff8, 'g', 2, "CP HL,%R" },
+  { 0xA0f8, 0xfff8, 'g', 2, "RLC %r" },
+  { 0xA1f8, 0xfff8, 'g', 2, "RRC %r" },
+  { 0xA2f8, 0xfff8, 'g', 2, "RL %r" },
+  { 0xA3f8, 0xfff8, 'g', 2, "RR %r" },
+  { 0xA4f8, 0xfff8, 'g', 2, "SLA %r" },
+  { 0xA5f8, 0xfff8, 'g', 2, "SRA %r" },
+  { 0xA6f8, 0xfff8, 'g', 2, "SLL %r" },
+  { 0xA7f8, 0xfff8, 'g', 2, "SRL %r" },
+  { 0x0068f8, 0x00fff8, 'n', 3, "ADD %r,%N" },
+  { 0x0069f8, 0x00fff8, 'n', 3, "ADC %r,%N" },
+  { 0x006af8, 0x00fff8, 'n', 3, "SUB %r,%N" },
+  { 0x006bf8, 0x00fff8, 'n', 3, "SBC %r,%N" },
+  { 0x006cf8, 0x00fff8, 'n', 3, "AND %r,%N" },
+  { 0x006df8, 0x00fff8, 'n', 3, "XOR %r,%N" },
+  { 0x006ef8, 0x00fff8, 'n', 3, "OR %r,%N" },
+  { 0x006ff8, 0x00fff8, 'n', 3, "CP %r,%N" },
+  { 0x14f8, 0xfcf8, 'g', 2, "ADD %i,%R" },
+  { 0x18f8, 0xf8f8, 'g', 2, "TSET %b,%r" },
+  { 0x30f8, 0xf8f8, 'g', 2, "LD %p,%r" },
+  { 0x38f8, 0xf8f8, 'g', 2, "LD %s,%R" },
+  { 0xA8f8, 0xf8f8, 'g', 2, "BIT %b,%r" },
+  { 0xB0f8, 0xf8f8, 'g', 2, "RES %b,%r" },
+  { 0xB8f8, 0xf8f8, 'g', 2, "SET %b,%r" },
+  /* Others in exec_inst2 */
+  { 0x00c0, 0x00f0, ' ', 2, "JR %y%1" },
+
+  /* exec_inst3 */
+  { 0x00001a, 0x0000ff, 'm', 3, "JP %M" },
+  { 0x00001b, 0x0000ff, 'D', 3, "JRL %D" },
+  { 0x00001c, 0x0000ff, 'M', 3, "CALL %M", true },
+  { 0x00001d, 0x0000ff, 'D', 3, "CALR %D", true },
+  { 0x000078, 0x0000ff, 'm', 3, "ADD HL,%M" },
+  { 0x000079, 0x0000ff, 'm', 3, "ADC HL,%M" },
+  { 0x00007a, 0x0000ff, 'm', 3, "SUB HL,%M" },
+  { 0x00007b, 0x0000ff, 'm', 3, "SBC HL,%M" },
+  { 0x00007c, 0x0000ff, 'm', 3, "AND HL,%M" },
+  { 0x00007d, 0x0000ff, 'm', 3, "XOR HL,%M" },
+  { 0x00007e, 0x0000ff, 'm', 3, "OR HL,%M" },
+  { 0x00007f, 0x0000ff, 'm', 3, "CP HL,%M" },
+
+  { 0, 0, ' ', 0, NULL }
+};
+
+//	    case 'r': /*  r in 1st byte */ s+= regname_r(c); break;
+//	    case 'p': /*  r in 2nd byte */ s+= regname_r(c>>8); break;
+//	    case 't': /*  r in 3rd byte */ s+= regname_r(c>>16); break;
+//	    case 'T': /*  r in 4th byte */ s+= regname_r(c>>24); break;
+//	    case 'R': /* rr in 1st byte */ s+= regname_R(c); break;
+//	    case 's': /* rr in 2nd byte */ s+= regname_R(c>>8); break;
+//	    case 'u': /* rr in 3rd byte */ s+= regname_R(c>>16); break;
+//	    case 'U': /* rr in 4th byte */ s+= regname_R(c>>24); break;
+//	    case 'Q': /* qq in 1st byte */ s+= regname_Q(c); break;
+//	    case 'I': /* ix in 1st byte */ s+= regname_i(c); break;
+//	    case 'i': /* ix in 2nd byte */ s+= regname_i(c>>8); break;
+//	    case 'j': /* ix in 3rd byte */ s+= regname_i(c>>16); break;
+//	    case 'J': /* ix in 4th byte */ s+= regname_i(c>>24); break;
+//	    case 'b': /*  b in 2nd byte */ s+= bitname(c>>8); break;
+//	    case 'B': /*  b in 3rd byte */ s+= bitname(c>>16); break;
+//	    case 'e': /*  b in 4th byte */ s+= bitname(c>>24); break;
+//	    case 'y': /* cc in 1st byte */ s+= condname_cc(c); break; // with ,
+//	    case 'c': /* cc in 2nd byte */ s+= condname_cc(c>>8); break; // with ,
+//	    case 'C': /* cc in 2nd byte */ s+= condname_C(c>>8); break; // without ,
+//	    case 'F': /* cc in 3rd byte */ s+= condname_cc(c>>16); break; // with ,
+//	    case 'f': /* cc in 4th byte */ s+= condname_cc(c>>24); break; // with ,
+//	    case 'n': /*  n in 2nd byte */ snprintf(l,19,"%02x",(int)(c>>8));s+= l; break;
+//	    case 'N': /*  n in 3dd byte */ snprintf(l,19,"%02x",(int)((c>>16)&0xff));s+= l; break;
+//	    case 'o': /*  n in 4th byte */ snprintf(l,19,"%02x",(int)((c>>24)&0xff));s+= l; break;
+//	    case 'O': /*  n in 5th byte */ snprintf(l,19,"%02x",(int)((c>>32)&0xff));s+= l; break;
+//	    case 'd': /*  d in 2nd byte */ snprintf(l,19,"0x%04x", addr+2+((c>>8)&0xff)); s+= l; break;
+//	    case 'D': /* cd in 2,3 byte */ snprintf(l,19,"0x%04x",(int)(addr+3+int16_t((c>>8)&0xffff))); s+= l; break;	      
+//	    case 'D': /* cd in 2,3 byte */ snprintf(l,19,"0x%04x", addr+2+((c>>8)&0xffff)); s+= l; break;
+//	    case 'M': /* mn in 2,3 byte */ snprintf(l,19,"0x%04x",(int)((c>>8)&0xffff)); s+= l; break;
+//	    case 'm': /* mn in 3,4 byte */ snprintf(l,19,"0x%04x",(int)((c>>16)&0xffff)); s+= l; break;
+//	    case 'X': /* mn in 4,5 byte */ snprintf(l,19,"0x%04x",(int)((c>>24)&0xffff)); s+= l; break;
+//	    case 'x': /* mn in 5,6 byte */ snprintf(l,19,"0x%04x",(int)((c>>32)&0xffff)); s+= l; break;
+
+/* End of tlcs.src/glob.cc */
diff --git a/sim/ucsim/tlcs.src/glob.h b/sim/ucsim/tlcs.src/glob.h
new file mode 100644
index 0000000..8ce0543
--- /dev/null
+++ b/sim/ucsim/tlcs.src/glob.h
@@ -0,0 +1,37 @@
+/*
+ * Simulator of microcontrollers (tlcs.src/glob.h)
+ *
+ * Copyright (C) 2016,16 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#ifndef TLCS_GLOB_HEADER
+#define TLCS_GLOB_HEADER
+
+#include "stypes.h"
+
+extern struct dis_entry disass_tlcs[];
+
+#endif
+
+/* End of tlcs.src/glob.h */
diff --git a/sim/ucsim/tlcs.src/glob.o b/sim/ucsim/tlcs.src/glob.o
new file mode 100644
index 0000000..c3eb9a8
--- /dev/null
+++ b/sim/ucsim/tlcs.src/glob.o
diff --git a/sim/ucsim/tlcs.src/inst_arith.cc b/sim/ucsim/tlcs.src/inst_arith.cc
new file mode 100644
index 0000000..8ab6f79
--- /dev/null
+++ b/sim/ucsim/tlcs.src/inst_arith.cc
@@ -0,0 +1,872 @@
+/*
+ * Simulator of microcontrollers (tlcs.src/inst_arith.cc)
+ *
+ * Copyright (C) 2016,16 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#include "tlcscl.h"
+
+
+// INC 8-bit
+u8_t
+cl_tlcs::op_inc(u8_t data)
+{
+  u16_t n= data+1;
+  reg.raf.f&= ~(FLAG_S|FLAG_Z|FLAG_H|FLAG_X);
+
+  if (n > 255)
+    reg.raf.f|= FLAG_X;
+  if (n & 0x80)
+    reg.raf.f|= FLAG_S;
+  if ((n & 0xff) == 0)
+    reg.raf.f|= FLAG_Z;
+  if (data == 0x7f)
+    reg.raf.f|= FLAG_V;
+  if ((n & 0x0f) == 0x00)
+    reg.raf.f|= FLAG_H;
+
+  return n;
+}
+
+
+// INC mem
+void
+cl_tlcs::inst_inc(cl_memory_cell *cell)
+{
+  u8_t d= cell->read();
+  d= op_inc(d);
+  cell->write(d);
+  vc.rd++;
+  vc.wr++;
+}
+
+
+// INCX mem
+void
+cl_tlcs::inst_incx(cl_memory_cell *cell)
+{
+  if (reg.raf.f & FLAG_X)
+    {
+      u8_t d= cell->read();
+      d= op_inc(d);
+      cell->write(d);
+      vc.rd++;
+      vc.wr++;
+    }
+}
+
+
+// INC 8-bit
+u8_t
+cl_tlcs::op_dec(u8_t data)
+{
+  u16_t n= data-1;
+  reg.raf.f&= ~(FLAG_S|FLAG_Z|FLAG_H|FLAG_X);
+  reg.raf.f|= FLAG_N;
+  
+  if (n > 255)
+    reg.raf.f|= FLAG_X;
+  if (n & 0x80)
+    reg.raf.f|= FLAG_S;
+  if ((n & 0xff) == 0)
+    reg.raf.f|= FLAG_Z;
+  if (data == 0x80)
+    reg.raf.f|= FLAG_V;
+  if ((n & 0x0f) == 0x00)
+    reg.raf.f|= FLAG_H;
+
+  return n & 0xff;
+}
+
+
+// DEC mem
+void
+cl_tlcs::inst_dec(cl_memory_cell *cell)
+{
+  u8_t d= cell->read();
+  d= op_dec(d);
+  cell->write(d);
+  vc.rd++;
+  vc.wr++;
+}
+
+
+// DECX mem
+void
+cl_tlcs::inst_decx(cl_memory_cell *cell)
+{
+  if (reg.raf.f & FLAG_X)
+    {
+      u8_t d= cell->read();
+      d= op_dec(d);
+      cell->write(d);
+      vc.rd++;
+      vc.wr++;
+    }
+}
+
+
+// INC 16-bit
+u16_t
+cl_tlcs::op_inc16(u16_t data)
+{
+  u16_t n= data+1;
+  reg.raf.f&= ~(FLAG_X);
+
+  if (n == 0)
+    reg.raf.f|= FLAG_X;
+
+  return n;
+}
+
+
+// INCW mem
+u16_t
+cl_tlcs::inst_inc16gg(u8_t gg, t_addr addr)
+{
+  cl_address_space *as= nas;
+
+  if ((gg&7)==4)
+    as= xas;
+  else if ((gg&7)==5)
+    as= yas;
+  u8_t l= as->read(addr);
+  u8_t h= as->read(addr+1);
+  vc.rd+= 2;
+  u16_t d= h*256 + l;
+
+  if (((int)d + 1) > 0xffff)
+    reg.raf.f|= FLAG_V;
+  
+  d= op_inc16(d);
+  reg.raf.f&= ~FLAG_N;
+  if (d & 0x8000)
+    reg.raf.f|= FLAG_S;
+  if (d == 0)
+    reg.raf.f|= FLAG_Z;
+
+  as->write(addr, d & 0xff);
+  as->write(addr+1, d >> 8);
+  vc.wr+= 2;
+  
+  return d;
+}
+
+
+// INCW mem
+u16_t
+cl_tlcs::inst_inc16(t_addr addr)
+{
+  return inst_inc16gg(0, addr);
+}
+
+
+// INCW mem
+u16_t
+cl_tlcs::inst_inc16ix(u8_t ix, t_addr addr)
+{
+  if ((ix&3) == 0)
+    return inst_inc16gg(4, addr);
+  else if ((ix&3) == 1)
+    return inst_inc16gg(5, addr);
+  return inst_inc16gg(0, addr);
+}
+
+
+// DEC 16-bit
+u16_t
+cl_tlcs::op_dec16(t_mem data)
+{
+  u16_t n= data-1;
+  reg.raf.f&= ~(FLAG_X);
+
+  if (n == 0xffff)
+    reg.raf.f|= FLAG_X;
+
+  return n;
+}
+
+
+// DECW mem
+u16_t
+cl_tlcs::inst_dec16gg(u8_t gg, t_addr addr)
+{
+  class cl_address_space *as= nas;
+
+  if ((gg&7)==4)
+    as= xas;
+  else if ((gg&7)==5)
+    as= yas;
+  u8_t l= as->read(addr);
+  u8_t h= as->read(addr+1);
+  vc.rd+= 2;
+  u16_t d= h*256 + l;
+
+  if (((int)d - 1) < 0)
+    reg.raf.f|= FLAG_V;
+  
+  d= op_dec16(d);
+  reg.raf.f&= ~FLAG_N;
+  if (d & 0x8000)
+    reg.raf.f|= FLAG_S;
+  if (d == 0)
+    reg.raf.f|= FLAG_Z;
+
+  as->write(addr, d & 0xff);
+  as->write(addr+1, d >> 8);
+  vc.wr+= 2;
+  
+  return d;
+}
+
+
+// DECW mem
+u16_t
+cl_tlcs::inst_dec16(t_addr addr)
+{
+  return inst_dec16gg(0, addr);
+}
+
+
+// DECW mem
+u16_t
+cl_tlcs::inst_dec16ix(u8_t ix, t_addr addr)
+{
+  if ((ix&3)==0)
+    return inst_dec16gg(4, addr);
+  else if ((ix&3)==1)
+    return inst_dec16gg(5, addr);
+  return inst_dec16gg(0, addr);
+}
+
+
+// ADD 8-bit
+u8_t
+cl_tlcs::op_add8(u8_t d1, u8_t d2)
+{
+  reg.raf.f&= ~(FLAG_S|FLAG_Z|FLAG_H|FLAG_X|FLAG_V|FLAG_N|FLAG_C);
+
+  int r= d1 + d2;
+  int new_c= 0, new_c6;
+  
+  if (((d1 & 0xf) + (d2 & 0xf)) > 0xf)
+    reg.raf.f|= FLAG_H;
+  new_c6= (((d1&0x7f) + (d2&0x7f)) > 0x7f)?1:0;
+  
+  if (r & 0x80)
+    reg.raf.f|= FLAG_S;
+  if ((r&0xff) == 0)
+    reg.raf.f|= FLAG_Z;
+  if (r > 255)
+    {
+      reg.raf.f|= FLAG_X|FLAG_C;
+      new_c= 1;
+    }
+  if (new_c ^ new_c6)
+    reg.raf.f|= FLAG_V;
+
+  return r & 0xff;
+}
+
+
+// ADD A,8-bit
+u8_t
+cl_tlcs::op_add_a(u8_t d)
+{
+  return op_add8(reg.raf.a, d);
+}
+
+
+// ADD A,mem
+int
+cl_tlcs::inst_add_a(class cl_memory_cell *cell)
+{
+  reg.raf.a= op_add_a((u8_t)(cell->read()));
+  vc.rd++;
+  return resGO;
+}
+
+
+// ADC 8-bit
+u8_t
+cl_tlcs::op_adc8(u8_t d1, u8_t d2)
+{
+  int oldc= (reg.raf.f&FLAG_C)?1:0;
+  reg.raf.f&= ~(FLAG_S|FLAG_Z|FLAG_H|FLAG_X|FLAG_V|FLAG_N|FLAG_C);
+
+  int r= d1 + d2 + oldc;
+  int new_c= 0, new_c6;
+  
+  if (((d1 & 0xf) + (d2 & 0xf) + oldc) > 0xf)
+    reg.raf.f|= FLAG_H;
+  new_c6= (((d1&0x7f) + (d2&0x7f) + oldc) > 0x7f)?1:0;
+  
+  if (r & 0x80)
+    reg.raf.f|= FLAG_S;
+  if ((r & 0xff) == 0)
+    reg.raf.f|= FLAG_Z;
+  if (r > 255)
+    {
+      reg.raf.f|= FLAG_X|FLAG_C;
+      new_c= 1;
+    }
+  if (new_c ^ new_c6)
+    reg.raf.f|= FLAG_V;
+
+  return r;
+}
+
+
+// ADC A,8-bit
+int
+cl_tlcs::inst_adc_a(u8_t d)
+{
+  reg.raf.a= op_adc8(reg.raf.a, d);
+  return resGO;
+}
+
+
+// ADC A,mem
+int
+cl_tlcs::inst_adc_a(class cl_memory_cell *cell)
+{
+  vc.rd++;
+  return inst_adc_a((u8_t)(cell->read()));
+}
+
+
+// SUB 8-bit
+u8_t
+cl_tlcs::op_sub8(u8_t d1, u8_t d2)
+{
+  unsigned int op1= (unsigned int)d1;
+  unsigned int op2= (unsigned int)d2;
+  signed int res= (signed char)d1 - (signed char)d2;
+  u8_t r;
+  
+  reg.raf.f&= ~(FLAG_H|FLAG_V|FLAG_C|FLAG_Z|FLAG_S);
+  reg.raf.f|= FLAG_N;
+
+  if ((op1 & 0xf) < (op2 & 0xf))
+    reg.raf.f|= FLAG_H;
+  if ((res < -128) || (res > 127))
+    reg.raf.f|= FLAG_V;
+  if (op1 < op2)
+    reg.raf.f|= FLAG_C|FLAG_X;
+
+  r= d1 - op2;
+  //r= op_add8(d1, ~d2 + 1);
+  if (r == 0)
+    reg.raf.f|= FLAG_Z;
+  if (r & 0x80)
+    reg.raf.f|= FLAG_S;
+  
+  //reg.raf.f|= FLAG_N;
+  return r;
+}
+
+
+// SUB A,8-bit
+int
+cl_tlcs::inst_sub_a(u8_t d)
+{
+  reg.raf.a= op_sub8(reg.raf.a, d);
+  return resGO;
+}
+
+
+// SUB A,mem
+int
+cl_tlcs::inst_sub_a(class cl_memory_cell *cell)
+{
+  vc.rd++;
+  return inst_sub_a((u8_t)(cell->read()));
+}
+
+
+// SBC 8-bit
+u8_t
+cl_tlcs::op_sbc8(u8_t d1, u8_t d2)
+{
+  u8_t r;
+  unsigned int op1= (unsigned int)d1;
+  unsigned int op2= (unsigned int)d2;
+  signed int res= (signed char)d1 - (signed char)d2;
+
+  if (reg.raf.f & FLAG_C)
+    {
+      ++op2;
+      --res;
+    }
+  reg.raf.f&= ~(FLAG_H|FLAG_V|FLAG_C|FLAG_S|FLAG_Z);
+  reg.raf.f|= FLAG_N;
+
+  if ((op1 & 0xf) < (op2 & 0xf))
+    reg.raf.f|= FLAG_H;
+  if ((res < -128) || (res > 127))
+    reg.raf.f|= FLAG_V;
+  if (d1 < op2)
+    reg.raf.f|= FLAG_C;
+
+  r= d1 - op2;
+
+  if (r == 0)
+    reg.raf.f|= FLAG_Z;
+  if (r & 0x80)
+    reg.raf.f|= FLAG_S;
+  
+  //r= op_adc8(d1, ~d2 + 1);
+  //reg.raf.f|= FLAG_N;
+  return r;
+}
+
+
+// SBC A,8-bit
+int
+cl_tlcs::inst_sbc_a(u8_t d)
+{
+  reg.raf.a= op_sbc8(reg.raf.a, d);
+  return resGO;
+}
+
+
+// SBC A,mem
+int
+cl_tlcs::inst_sbc_a(class cl_memory_cell *cell)
+{
+  vc.rd++;
+  return inst_sbc_a((u8_t)(cell->read()));
+}
+
+
+// AND 8-bit
+u8_t
+cl_tlcs::op_and8(u8_t d1, u8_t d2)
+{
+  reg.raf.f&= ~(FLAG_S|FLAG_Z|FLAG_X|FLAG_N|FLAG_C);
+  reg.raf.f|= FLAG_H;
+
+  u8_t r= d1 & d2;
+  set_p(r);
+  if (r & 0x80)
+    reg.raf.f|= FLAG_S;
+  if (r == 0)
+    reg.raf.f|= FLAG_Z;
+
+  return r;
+}
+
+
+// AND A,8-bit
+int
+cl_tlcs::inst_and_a(u8_t d)
+{
+  reg.raf.a= op_and8(reg.raf.a, d);
+  return resGO;
+}
+
+
+// AND A,mem
+int
+cl_tlcs::inst_and_a(class cl_memory_cell *cell)
+{
+  vc.rd++;
+  return inst_and_a((u8_t)(cell->read()));
+}
+
+
+// XOR 8-bit
+u8_t
+cl_tlcs::op_xor8(u8_t d1, u8_t d2)
+{
+  reg.raf.f&= ~(FLAG_S|FLAG_Z|FLAG_H|FLAG_X|FLAG_N|FLAG_C);
+
+  u8_t r= d1 ^ d2;
+  set_p(r);
+  if (r & 0x80)
+    reg.raf.f|= FLAG_S;
+  if (r == 0)
+    reg.raf.f|= FLAG_Z;
+
+  return r;
+}
+
+
+// XOR A,8-bit
+int
+cl_tlcs::inst_xor_a(u8_t d)
+{
+  reg.raf.a= op_xor8(reg.raf.a, d);
+  return resGO;
+}
+
+
+// XOR A,mem
+int
+cl_tlcs::inst_xor_a(class cl_memory_cell *cell)
+{
+  vc.rd++;
+  return inst_xor_a((u8_t)(cell->read()));
+}
+
+
+// OR 8-bit
+u8_t
+cl_tlcs::op_or8(u8_t d1, u8_t d2)
+{
+  reg.raf.f&= ~(FLAG_S|FLAG_Z|FLAG_H|FLAG_X|FLAG_N|FLAG_C);
+
+  u8_t r= d1 | d2;
+  set_p(r);
+  if (r & 0x80)
+    reg.raf.f|= FLAG_S;
+  if (r == 0)
+    reg.raf.f|= FLAG_Z;
+
+  return r;
+}
+
+
+// OR A,8-bit
+int
+cl_tlcs::inst_or_a(u8_t d)
+{
+  reg.raf.a= op_or8(reg.raf.a, d);
+  return resGO;
+}
+
+
+// OR A,mem
+int
+cl_tlcs::inst_or_a(class cl_memory_cell *cell)
+{
+  vc.rd++;
+  return inst_or_a((u8_t)(cell->read()));
+}
+
+
+// CP 8-bit
+u8_t
+cl_tlcs::op_cp8(u8_t d1, u8_t d2)
+{
+  u8_t r= op_sub8(d1, d2);
+  reg.raf.f|= FLAG_N;
+  return r;
+}
+
+
+// CP A,8-bit
+int
+cl_tlcs::op_cp_a(u8_t d)
+{
+  op_cp8(reg.raf.a, d);
+  return resGO;
+}
+
+
+// CP A,mem
+int
+cl_tlcs::op_cp_a(class cl_memory_cell *cell)
+{
+  vc.rd++;
+  return op_cp_a((u8_t)(cell->read()));
+}
+
+
+// ADD 16-bit
+u16_t
+cl_tlcs::op_add16(t_mem op1, t_mem op2)
+{
+  u16_t d1, d;
+  int r, newc15;
+  
+  reg.raf.f&= ~(FLAG_S|FLAG_Z|FLAG_X|FLAG_N|FLAG_C);
+
+  d1= op1;
+  d= op2;
+
+  r= d1 + d;
+  newc15= (((d1&0x7fff)+(d&0x7fff)) > 0x7fff)?0x10000:0;
+  
+  if (r & 0x8000)
+    reg.raf.f|= FLAG_S;
+  if ((r & 0xffff) == 0)
+    reg.raf.f|= FLAG_Z;
+  if (r > 0xffff)
+    reg.raf.f|= FLAG_C|FLAG_X;
+  if (newc15 ^ (r&0x10000))
+    reg.raf.f|= FLAG_V;
+  
+  return r & 0xffff;
+}
+
+
+// ADD HL,mem
+u16_t
+cl_tlcs::op_add_hl(t_addr addr)
+{
+  u8_t dh, dl;
+  u16_t d;
+  
+  dl= nas->read(addr);
+  dh= nas->read(addr+1);
+  d= dh*256 + dl;
+  vc.rd+= 2;
+  
+  return op_add16(reg.hl, d);
+}
+
+
+// ADD HL,16-bit
+u16_t
+cl_tlcs::op_add_hl(t_mem val)
+{
+  return op_add16(reg.hl, val);
+}
+
+
+// ADC HL,mem
+u16_t
+cl_tlcs::op_adc_hl(t_mem val)
+{
+  u8_t dl= val & 0xff;
+  u8_t dh= val / 256;
+  u16_t d= dh*256 + dl;
+  int oldc= (reg.raf.f & FLAG_C)?1:0;
+  
+  return op_add_hl((t_mem)d + oldc);
+}
+
+
+// ADC HL,mem
+u16_t
+cl_tlcs::op_adc_hl(t_addr addr)
+{
+  u8_t dl= nas->read(addr);
+  u8_t dh= nas->read(addr+1);
+  u16_t d= dh*256 + dl;
+  int oldc= (reg.raf.f & FLAG_C)?1:0;
+  vc.rd+= 2;
+  
+  return op_add_hl((t_mem)d + oldc);
+}
+
+
+// SUB 16-bit
+u16_t
+cl_tlcs::op_sub16(t_mem d1, t_mem d2)
+{
+  u16_t r;
+
+  unsigned int op1= (unsigned int)d1;
+  unsigned int op2= (unsigned int)d2;
+  signed int res= (i16_t)d1 - (i16_t)d2;
+
+  reg.raf.f&= ~(FLAG_C|FLAG_V|FLAG_Z|FLAG_S);
+  reg.raf.f|= FLAG_N;
+  
+  if ((res < -32768) || (res > 32767))
+    reg.raf.f|= FLAG_V;
+  if (op1 < op2)
+    reg.raf.f|= FLAG_C|FLAG_X;
+
+  r= d1 - op2;
+
+  if (r == 0)
+    reg.raf.f|= FLAG_Z;
+  if (r & 0x8000)
+    reg.raf.f|= FLAG_S;
+  
+  return r;
+}
+
+
+// SUB HL,16-bit
+u16_t
+cl_tlcs::op_sub_hl(t_mem val)
+{
+  return op_sub16(reg.hl, val);
+}
+
+
+// SUB HL,mem
+u16_t
+cl_tlcs::op_sub_hl(t_addr addr)
+{
+  u8_t dl= nas->read(addr);
+  u8_t dh= nas->read(addr+1);
+  u16_t d= dh*256 + dl;
+  vc.rd+= 2;
+  
+  return op_sub16(reg.hl, d);
+}
+
+
+// SBC HL,16-bit
+u16_t
+cl_tlcs::op_sbc_hl(t_mem val)
+{
+  u16_t r;
+
+  unsigned int op1= (unsigned int)reg.hl;
+  unsigned int op2= (unsigned int)val;
+  signed int res= (i16_t)reg.hl - (i16_t)val;
+
+  if (reg.raf.f & FLAG_C)
+    {
+      ++op2;
+      --res;
+    }
+  reg.raf.f&= ~(FLAG_C|FLAG_V|FLAG_Z|FLAG_S);
+  reg.raf.f|= FLAG_N;
+  
+  if ((op1 & 0xfff) < (op2 & 0xfff))
+    reg.raf.f|= FLAG_H;
+  if ((res < -32768) || (res > 32767))
+    reg.raf.f|= FLAG_V;
+  if (op1 < op2)
+    reg.raf.f|= FLAG_C;
+
+  r= reg.hl - op2;
+
+  if (r == 0)
+    reg.raf.f|= FLAG_Z;
+  if (r & 0x8000)
+    reg.raf.f|= FLAG_S;
+  
+  return r;
+}
+
+
+// SBC HL,mem
+u16_t
+cl_tlcs::op_sbc_hl(t_addr addr)
+{
+  u8_t dl= nas->read(addr);
+  u8_t dh= nas->read(addr+1);
+  u16_t d= dh*256 + dl;
+  vc.rd+= 2;
+  
+  return op_sbc_hl((t_mem)d);
+}
+
+
+// AND HL,16-bit
+u16_t
+cl_tlcs::op_and_hl(t_mem val)
+{
+  u16_t d= val;
+  u16_t r;
+
+  reg.raf.f&= ~(FLAG_S|FLAG_Z|FLAG_X|FLAG_N|FLAG_C);
+  reg.raf.f|= FLAG_H;
+  
+  r= reg.hl & d;
+  if (r & 0x8000)
+    reg.raf.f|= FLAG_S;
+  if (r == 0)
+    reg.raf.f|= FLAG_Z;
+  
+  return r;
+}
+
+
+// AND HL,mem
+u16_t
+cl_tlcs::op_and_hl(t_addr addr)
+{
+  u8_t dl= nas->read(addr);
+  u8_t dh= nas->read(addr+1);
+  u16_t d= dh*256 + dl;
+  vc.rd+= 2;
+  
+  return op_and_hl((t_mem)d);
+}
+
+
+// XOR HL,16-bit
+u16_t
+cl_tlcs::op_xor_hl(t_mem val)
+{
+  u16_t d= val;
+  u16_t r;
+
+  reg.raf.f&= ~(FLAG_S|FLAG_Z|FLAG_H|FLAG_X|FLAG_N|FLAG_C);
+  
+  r= reg.hl ^ d;
+  if (r & 0x8000)
+    reg.raf.f|= FLAG_S;
+  if (r == 0)
+    reg.raf.f|= FLAG_Z;
+  
+  return r;
+}
+
+
+// XOR HL,mem
+u16_t
+cl_tlcs::op_xor_hl(t_addr addr)
+{
+  u8_t dl= nas->read(addr);
+  u8_t dh= nas->read(addr+1);
+  u16_t d= dh*256 + dl;
+  vc.rd+= 2;
+  
+  return op_xor_hl((t_mem)d);
+}
+
+
+// OR HL,16-bit
+u16_t
+cl_tlcs::op_or_hl(t_mem val)
+{
+  u16_t d= val;
+  u16_t r;
+
+  reg.raf.f&= ~(FLAG_S|FLAG_Z|FLAG_H|FLAG_X|FLAG_N|FLAG_C);
+  
+  r= reg.hl | d;
+  if (r & 0x8000)
+    reg.raf.f|= FLAG_S;
+  if (r == 0)
+    reg.raf.f|= FLAG_Z;
+  
+  return r;
+}
+
+
+// OR HL,mem
+u16_t
+cl_tlcs::op_or_hl(t_addr addr)
+{
+  u8_t dl= nas->read(addr);
+  u8_t dh= nas->read(addr+1);
+  u16_t d= dh*256 + dl;
+  vc.rd+= 2;
+  
+  return op_or_hl((t_mem)d);
+}
+
+
+/* End of tlcs/inst_arith.cc */
diff --git a/sim/ucsim/tlcs.src/inst_arith.o b/sim/ucsim/tlcs.src/inst_arith.o
new file mode 100644
index 0000000..af73348
--- /dev/null
+++ b/sim/ucsim/tlcs.src/inst_arith.o
diff --git a/sim/ucsim/tlcs.src/inst_bit.cc b/sim/ucsim/tlcs.src/inst_bit.cc
new file mode 100644
index 0000000..1ac2932
--- /dev/null
+++ b/sim/ucsim/tlcs.src/inst_bit.cc
@@ -0,0 +1,138 @@
+/*
+ * Simulator of microcontrollers (tlcs.src/inst_bit.cc)
+ *
+ * Copyright (C) 2016,16 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#include "tlcscl.h"
+
+
+// TSET 8-bit
+u8_t
+cl_tlcs::op_tset(u8_t val, u8_t bitnr)
+{
+  reg.raf.f&= ~(FLAG_Z|FLAG_N);
+  reg.raf.f|= FLAG_H;
+  
+  bitnr&= 0x07;
+  if ((val & (1 << bitnr)) == 0)
+    reg.raf.f|= FLAG_Z;
+  val|= (1 << bitnr);
+  return val;
+}
+
+
+// TSET mem
+u8_t
+cl_tlcs::inst_tset(cl_memory_cell *cell, u8_t bitnr)
+{
+  u8_t v= cell->read();
+  vc.rd++;
+  v= op_tset(v, bitnr);
+  cell->write(v);
+  vc.wr++;
+  return v;
+}
+
+
+// BIT 8-bit
+u8_t
+cl_tlcs::op_bit(u8_t val, u8_t bitnr)
+{
+  reg.raf.f&= ~(FLAG_Z|FLAG_N);
+  reg.raf.f|= FLAG_H;
+
+  bitnr&= 7;
+
+  if ((val & (1 << bitnr)) == 0)
+    reg.raf.f|= FLAG_Z;
+
+  return val;
+}
+
+
+// BIT mem
+u8_t
+cl_tlcs::inst_bit(cl_memory_cell *cell, u8_t bitnr)
+{
+  u8_t v= cell->read();
+  vc.rd++;
+  v= op_bit(v, bitnr);
+  cell->write(v);
+  vc.wr++;
+  return v;
+}
+
+
+// RES 8-bit
+u8_t
+cl_tlcs::op_res(u8_t val, u8_t bitnr)
+{
+  bitnr&= 7;
+
+  val&= ~(1 << bitnr);
+
+  return val;
+}
+
+
+// RES mem
+u8_t
+cl_tlcs::inst_res(cl_memory_cell *cell, u8_t bitnr)
+{
+  u8_t v= cell->read();
+  vc.rd++;
+  v= op_res(v, bitnr);
+  cell->write(v);
+  vc.wr++;
+  return v;
+}
+
+
+// SET 8-bit
+u8_t
+cl_tlcs::op_set(u8_t val, u8_t bitnr)
+{
+  bitnr&= 7;
+
+  val|= (1 << bitnr);
+
+  return val;
+}
+
+
+// SET mem
+u8_t
+cl_tlcs::inst_set(cl_memory_cell *cell, u8_t bitnr)
+{
+  u8_t v= cell->read();
+  vc.rd++;
+  v= op_set(v, bitnr);
+  cell->write(v);
+  vc.wr++;
+  return v;
+}
+
+
+/* End of tlcs.src/inst_bit.cc */
diff --git a/sim/ucsim/tlcs.src/inst_bit.o b/sim/ucsim/tlcs.src/inst_bit.o
new file mode 100644
index 0000000..a3f6710
--- /dev/null
+++ b/sim/ucsim/tlcs.src/inst_bit.o
diff --git a/sim/ucsim/tlcs.src/inst_block.cc b/sim/ucsim/tlcs.src/inst_block.cc
new file mode 100644
index 0000000..420822b
--- /dev/null
+++ b/sim/ucsim/tlcs.src/inst_block.cc
@@ -0,0 +1,212 @@
+/*
+ * Simulator of microcontrollers (tlcs.src/inst_block.cc)
+ *
+ * Copyright (C) 2016,16 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#include "tlcscl.h"
+
+
+// 08
+int
+cl_tlcs::ex_de_hl()
+{
+  u16_t temp= reg.de;
+  reg.de= reg.hl;
+  reg.hl= temp;
+  return resGO;
+}
+
+
+// 09
+int
+cl_tlcs::ex_af_alt_af()
+{
+  u16_t temp= reg.af;
+  reg.af= reg.alt_af;
+  reg.alt_af= temp;
+  return resGO;
+}
+
+
+// 0A
+int
+cl_tlcs::exx()
+{
+  u16_t temp= reg.bc;
+  reg.bc= reg.alt_bc;
+  reg.alt_bc= temp;
+  temp= reg.de;
+  reg.de= reg.alt_de;
+  reg.alt_de= temp;
+  temp= reg.hl;
+  reg.hl= reg.alt_hl;
+  reg.alt_hl= temp;
+  return resGO;
+}
+
+
+// FE 58
+int
+cl_tlcs::ldi()
+{
+  nas->write(reg.de, nas->read(reg.hl));
+  vc.rd++;
+  vc.wr++;
+  reg.de++;
+  reg.hl++;
+  reg.bc--;
+  reg.raf.f&= ~(FLAG_H|FLAG_N|FLAG_V);
+  if (reg.bc)
+    reg.raf.f|= FLAG_V;
+  return resGO;
+}
+
+
+// FE 59
+int
+cl_tlcs::ldir()
+{
+  ldi();
+  if (reg.bc)
+    PC-= 2;
+  return resGO;
+}
+
+
+// FE 5a
+int
+cl_tlcs::ldd()
+{
+  nas->write(reg.de, nas->read(reg.hl));
+  vc.rd++;
+  vc.wr++;
+  reg.de--;
+  reg.hl--;
+  reg.bc--;
+  reg.raf.f&= ~(FLAG_H|FLAG_N|FLAG_V);
+  if (reg.bc)
+    reg.raf.f|= FLAG_V;
+  return resGO;
+}
+
+
+// FE 5a
+int
+cl_tlcs::lddr()
+{
+  ldd();
+  if (reg.bc)
+    PC-= 2;
+  return resGO;
+}
+
+
+// FE 5C
+int
+cl_tlcs::cpi()
+{
+  reg.raf.f&= ~(FLAG_Z|FLAG_S|FLAG_N|FLAG_H|FLAG_X|FLAG_V);
+  reg.raf.f|= FLAG_N;
+  int a= reg.raf.a;
+  int d= nas->read(reg.hl);
+  vc.rd++;
+  int r= a-d;
+  
+  reg.hl++;
+  reg.bc--;
+
+  if (r == 0)
+    reg.raf.f|= FLAG_Z;
+  if (reg.bc != 0)
+    reg.raf.f|= FLAG_V;
+  if (a == d)
+    reg.raf.f|= FLAG_N;
+  if (r & 0x80)
+    reg.raf.f|= FLAG_S;
+  if (((a&0xf) + ((~d+1)&0xf)) > 0xf)
+    reg.raf.f|= FLAG_H;
+  if ((unsigned int)r > 0xff)
+    reg.raf.f|= FLAG_X;
+
+  return resGO;
+}
+
+
+// FE 5D
+int
+cl_tlcs::cpir()
+{
+  cpi();
+  if ((reg.bc != 0) &&
+      ((reg.raf.f&FLAG_Z) == 0))
+    PC-= 2;
+  return resGO;
+}
+
+
+// FE 5E
+int
+cl_tlcs::cpd()
+{
+  reg.raf.f&= ~(FLAG_Z|FLAG_S|FLAG_N|FLAG_H|FLAG_X|FLAG_V);
+  reg.raf.f|= FLAG_N;
+  int a= reg.raf.a;
+  int d= nas->read(reg.hl);
+  int r= a-d;
+  vc.rd++;
+  
+  reg.hl--;
+  reg.bc--;
+
+  if (r == 0)
+    reg.raf.f|= FLAG_Z;
+  if (reg.bc != 0)
+    reg.raf.f|= FLAG_V;
+  if (a == d)
+    reg.raf.f|= FLAG_N;
+  if (r & 0x80)
+    reg.raf.f|= FLAG_S;
+  if (((a&0xf) + ((~d+1)&0xf)) > 0xf)
+    reg.raf.f|= FLAG_H;
+  if ((unsigned int)r > 0xff)
+    reg.raf.f|= FLAG_X;
+
+  return resGO;
+}
+
+
+// FE 5D
+int
+cl_tlcs::cpdr()
+{
+  cpd();
+  if ((reg.bc != 0) &&
+      ((reg.raf.f&FLAG_Z) == 0))
+    PC-= 2;
+  return resGO;
+}
+
+
+/* End of tlcs.src/inst_block.cc */
diff --git a/sim/ucsim/tlcs.src/inst_block.o b/sim/ucsim/tlcs.src/inst_block.o
new file mode 100644
index 0000000..a25fb45
--- /dev/null
+++ b/sim/ucsim/tlcs.src/inst_block.o
diff --git a/sim/ucsim/tlcs.src/inst_cpu_others.cc b/sim/ucsim/tlcs.src/inst_cpu_others.cc
new file mode 100644
index 0000000..8911a68
--- /dev/null
+++ b/sim/ucsim/tlcs.src/inst_cpu_others.cc
@@ -0,0 +1,182 @@
+/*
+ * Simulator of microcontrollers (tlcs.src/inst_cpu_others.cc)
+ *
+ * Copyright (C) 2016,16 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#include "tlcscl.h"
+
+
+// 0B
+int
+cl_tlcs::inst_daa_a()
+{
+  if (((reg.raf.a & 0x0f) > 9) ||
+      (reg.raf.f & FLAG_H))
+    {
+      int al= reg.raf.a & 0x0f;
+      if (al + 6 > 15)
+	reg.raf.f|= FLAG_H;
+      else
+	reg.raf.f&= ~FLAG_H;
+      if ((int)reg.raf.a + 6 > 255)
+	reg.raf.f|= FLAG_C|FLAG_X;
+      else
+	reg.raf.f&= ~(FLAG_C|FLAG_X);
+      reg.raf.a+= 6;
+    }
+  if (((reg.raf.a & 0xf0) > 0x90) ||
+      (reg.raf.f & FLAG_C))
+    {
+      if ((int)reg.raf.a + 0x60 > 255)
+	reg.raf.f|= FLAG_C;
+      else
+	reg.raf.f&= ~FLAG_C;
+      reg.raf.a+= 0x60;
+    }
+  return resGO;
+}
+
+
+// 10
+int
+cl_tlcs::inst_cpl_a()
+{
+  reg.raf.a= ~reg.raf.a;
+  reg.raf.f|= FLAG_H|FLAG_N;
+  return resGO;
+}
+
+
+// 11
+int
+cl_tlcs::inst_neg_a()
+{
+  reg.raf.f&= ~(FLAG_S|FLAG_Z|FLAG_H/*|FLAG_X*/|FLAG_V|FLAG_C);
+  reg.raf.f|= FLAG_N;
+  if (reg.raf.a == 0x80)
+    reg.raf.f|= FLAG_V;
+  if (reg.raf.a)
+    reg.raf.f|= (FLAG_C|FLAG_X);
+
+  //uint8_t a= ~reg.raf.a;
+  if ((reg.raf.a & 0x0f) == 0)//if (a&0xf + 1 > 15)
+    reg.raf.f|= FLAG_H;
+  reg.raf.a= 0-reg.raf.a;
+
+  if (reg.raf.a & 0x80)
+    reg.raf.f|= FLAG_S;
+  if (!reg.raf.a)
+    reg.raf.f|= FLAG_Z;
+  
+  return resGO;
+}
+
+
+// 0e
+int
+cl_tlcs::inst_ccf()
+{
+  if (reg.raf.f & FLAG_C)
+    reg.raf.f&= ~(FLAG_C);
+  else
+    reg.raf.f|= FLAG_C;
+  if (reg.raf.f & FLAG_X)
+    reg.raf.f&= ~(FLAG_X);
+  else
+    reg.raf.f|= FLAG_X;
+  reg.raf.f&= ~FLAG_N;
+  return resGO;
+}
+
+
+// 0d
+int
+cl_tlcs::inst_scf()
+{
+  reg.raf.f|= FLAG_C|FLAG_X;
+  reg.raf.f&= ~(FLAG_N|FLAG_H);
+  return resGO;
+}
+
+
+// 0c
+int
+cl_tlcs::inst_rcf()
+{
+  reg.raf.f&= ~(FLAG_C|FLAG_X|FLAG_N|FLAG_H);
+  return resGO;
+}
+
+
+// ff
+int
+cl_tlcs::inst_swi()
+{
+  t_addr iPC= PC-1;
+  reg.raf.f&= ~FLAG_I;
+  exec_intr(iPC, 0x0010, PC);
+  exec_push(iPC, reg.af);
+  PC= 0x0010;
+  return resGO;
+}
+
+
+// MUL HL,mem
+int
+cl_tlcs::inst_mul_hl(class cl_memory_cell *cell)
+{
+  reg.hl= reg.rhl.l * cell->read();
+  vc.rd++;
+  return resGO;
+}
+
+
+// DIV HL,mem
+int
+cl_tlcs::inst_div_hl(class cl_memory_cell *cell)
+{
+  u8_t m= cell->read();
+  vc.rd++;
+  return inst_div_hl(m);
+}
+
+
+// DIV HL,val
+int
+cl_tlcs::inst_div_hl(u8_t d)
+{
+  u8_t m= d;
+  reg.raf.f&= ~FLAG_V;
+  if ((m == 0) ||
+      ((reg.hl / m) > 255))
+    reg.raf.f|= FLAG_V;
+  else
+    reg.rhl.l= reg.hl / m;
+  reg.rhl.h= reg.hl % m;
+  return resGO;
+}
+
+
+/* End of tlcs.src/inst_cpu_others.cc */
diff --git a/sim/ucsim/tlcs.src/inst_cpu_others.o b/sim/ucsim/tlcs.src/inst_cpu_others.o
new file mode 100644
index 0000000..7bf6c10
--- /dev/null
+++ b/sim/ucsim/tlcs.src/inst_cpu_others.o
diff --git a/sim/ucsim/tlcs.src/inst_jump.cc b/sim/ucsim/tlcs.src/inst_jump.cc
new file mode 100644
index 0000000..7771e07
--- /dev/null
+++ b/sim/ucsim/tlcs.src/inst_jump.cc
@@ -0,0 +1,89 @@
+/*
+ * Simulator of microcontrollers (tlcs.src/inst_jmp.cc)
+ *
+ * Copyright (C) 2016,16 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#include "tlcscl.h"
+
+
+// 1e
+int
+cl_tlcs::inst_ret()
+{
+  t_mem pushed_pc;
+
+  exec_ret(PC-1, &pushed_pc);
+  PC= pushed_pc;
+  return resGO;
+}
+
+
+// 1f
+int
+cl_tlcs::inst_reti()
+{
+  t_mem pushed_pc, pushed_af;
+  
+  exec_pop(PC-1, &pushed_af);
+  exec_reti(PC-1, &pushed_pc);
+  reg.af= pushed_af;
+  PC= pushed_pc;
+  return resGO;
+}
+
+
+// CALL
+int
+cl_tlcs::inst_call(t_addr PC_of_inst, u16_t addr)
+{
+  exec_call(PC_of_inst, addr, PC);
+  PC= addr;
+  return resGO;
+}
+
+
+// DJNZ
+int
+cl_tlcs::inst_djnz_b(i8_t d)
+{
+  reg.rbc.b--;
+  if (reg.rbc.b != 0)
+    PC+= d;
+  return resGO;
+}
+
+
+// DJNZ BC
+int
+cl_tlcs::inst_djnz_bc(i8_t d)
+{
+  reg.bc--;
+  if (reg.bc != 0)
+    PC+= d;
+  return resGO;
+}
+
+
+/* End of tlcs.src/inst_jmp.cc */
diff --git a/sim/ucsim/tlcs.src/inst_jump.o b/sim/ucsim/tlcs.src/inst_jump.o
new file mode 100644
index 0000000..cf958e9
--- /dev/null
+++ b/sim/ucsim/tlcs.src/inst_jump.o
diff --git a/sim/ucsim/tlcs.src/inst_move.cc b/sim/ucsim/tlcs.src/inst_move.cc
new file mode 100644
index 0000000..103d0e0
--- /dev/null
+++ b/sim/ucsim/tlcs.src/inst_move.cc
@@ -0,0 +1,41 @@
+/*
+ * Simulator of microcontrollers (tlcs.src/inst_move.cc)
+ *
+ * Copyright (C) 2016,16 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#include "tlcscl.h"
+
+
+// 58+qq
+int
+cl_tlcs::inst_pop(t_mem c1)
+{
+  t_mem data;
+  exec_pop(PC-1, &data);
+  *aof_reg16_qq(c1)= data;
+  return resGO;
+}
+
+/* End of tlcs/inst_move.cc */
diff --git a/sim/ucsim/tlcs.src/inst_move.o b/sim/ucsim/tlcs.src/inst_move.o
new file mode 100644
index 0000000..e764ab7
--- /dev/null
+++ b/sim/ucsim/tlcs.src/inst_move.o
diff --git a/sim/ucsim/tlcs.src/inst_rot_sh.cc b/sim/ucsim/tlcs.src/inst_rot_sh.cc
new file mode 100644
index 0000000..056af8e
--- /dev/null
+++ b/sim/ucsim/tlcs.src/inst_rot_sh.cc
@@ -0,0 +1,322 @@
+/*
+ * Simulator of microcontrollers (tlcs.src/inst_rot_sh.cc)
+ *
+ * Copyright (C) 2016,16 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#include "tlcscl.h"
+
+
+// RLC 8-bit
+u8_t
+cl_tlcs::op_rlc(u8_t data, bool set_sz)
+{
+  u8_t c= data & 0x80;
+  reg.raf.f&= ~((set_sz?(FLAG_S|FLAG_Z):0)|FLAG_H|FLAG_N|FLAG_C);
+  data<<= 1;
+  if (c)
+    {
+      data|= 1;
+      reg.raf.f|= FLAG_C;
+    }
+
+  if (set_sz)
+    {
+      if (!data)
+	reg.raf.f|= FLAG_Z;
+      if (data&0x80)
+	reg.raf.f|= FLAG_S;
+      set_p(data);
+    }
+  
+  return data;
+}
+
+
+// RLC mem
+u8_t
+cl_tlcs::inst_rlc(cl_memory_cell *cell)
+{
+  u8_t d= op_rlc(cell->read(), true);
+  vc.rd++;
+  cell->write(d);
+  vc.wr++;
+  return d;
+}
+
+
+// RRC 8-bit
+u8_t
+cl_tlcs::op_rrc(u8_t data, bool set_sz)
+{
+  u8_t c= data & 0x01;
+  reg.raf.f&= ~((set_sz?(FLAG_S|FLAG_Z):0)|FLAG_H|FLAG_N|FLAG_C);
+  data>>= 1;
+  if (c)
+    {
+      data|= 0x80;
+      reg.raf.f|= FLAG_C;
+    }
+
+  if (set_sz)
+    {
+      if (!data)
+	reg.raf.f|= FLAG_Z;
+      if (data&0x80)
+	reg.raf.f|= FLAG_S;
+      set_p(data);
+    }
+  
+  return data;
+}
+
+
+// RRC mem
+u8_t
+cl_tlcs::inst_rrc(cl_memory_cell *cell)
+{
+  u8_t d= op_rrc(cell->read(), true);
+  vc.rd++;
+  cell->write(d);
+  vc.wr++;
+  return d;
+}
+
+
+// RL 8-bit
+u8_t
+cl_tlcs::op_rl(u8_t data, bool set_sz)
+{
+  u8_t c= data & 0x80;
+  data<<= 1;
+  if (reg.raf.f & FLAG_C)
+    data|= 1;
+  reg.raf.f&= ~((set_sz?(FLAG_S|FLAG_Z):0)|FLAG_H|FLAG_N|FLAG_C);
+  if (c)
+    reg.raf.f|= FLAG_C;
+
+  if (set_sz)
+    {
+      if (!data)
+	reg.raf.f|= FLAG_Z;
+      if (data&0x80)
+	reg.raf.f|= FLAG_S;
+      set_p(data);
+    }
+  
+  return data;
+}
+
+
+// RL mem
+u8_t
+cl_tlcs::inst_rl(cl_memory_cell *cell)
+{
+  u8_t d= op_rl(cell->read(), true);
+  vc.rd++;
+  cell->write(d);
+  vc.wr++;
+  return d;
+}
+
+
+// RR 8-bit
+u8_t
+cl_tlcs::op_rr(u8_t data, bool set_sz)
+{
+  u8_t c= data & 0x01;
+  data>>= 1;
+  if (reg.raf.f & FLAG_C)
+    data|= 0x80;
+  reg.raf.f&= ~((set_sz?(FLAG_S|FLAG_Z):0)|FLAG_H|FLAG_N|FLAG_C);
+  if (c)
+    reg.raf.f|= FLAG_C;
+
+  if (set_sz)
+    {
+      if (!data)
+	reg.raf.f|= FLAG_Z;
+      if (data&0x80)
+	reg.raf.f|= FLAG_S;
+      set_p(data);
+    }
+  
+  return data;
+}
+
+
+// RR mem
+u8_t
+cl_tlcs::inst_rr(cl_memory_cell *cell)
+{
+  u8_t d= op_rr(cell->read(), true);
+  vc.rd++;
+  cell->write(d);
+  vc.wr++;
+  return d;
+}
+
+
+// SLA 8-bit
+u8_t
+cl_tlcs::op_sla(u8_t data, bool set_sz)
+{
+  u8_t c= data & 0x80;
+  data<<= 1;
+  reg.raf.f&= ~((set_sz?(FLAG_S|FLAG_Z):0)|FLAG_H|FLAG_N|FLAG_C);
+  if (c)
+    reg.raf.f|= FLAG_C;
+
+  if (set_sz)
+    {
+      if (!data)
+	reg.raf.f|= FLAG_Z;
+      if (data&0x80)
+	reg.raf.f|= FLAG_S;
+      set_p(data);
+    }
+  
+  return data;
+}
+
+
+// SLA mem
+u8_t
+cl_tlcs::inst_sla(cl_memory_cell *cell)
+{
+  u8_t d= op_sla(cell->read(), true);
+  vc.rd++;
+  cell->write(d);
+  vc.wr++;
+  return d;
+}
+
+
+// SRA 8-bit
+u8_t
+cl_tlcs::op_sra(u8_t data, bool set_sz)
+{
+  u8_t c7= data & 0x80;
+  u8_t c0= data & 0x01;
+  data>>= 1;
+  reg.raf.f&= ~((set_sz?(FLAG_S|FLAG_Z):0)|FLAG_H|FLAG_N|FLAG_C);
+  if (c0)
+    reg.raf.f|= FLAG_C;
+  data|= c7;
+  
+  if (set_sz)
+    {
+      if (!data)
+	reg.raf.f|= FLAG_Z;
+      if (data&0x80)
+	reg.raf.f|= FLAG_S;
+      set_p(data);
+    }
+  
+  return data;
+}
+
+
+// SRA mem
+u8_t
+cl_tlcs::inst_sra(cl_memory_cell *cell)
+{
+  u8_t d= op_sra(cell->read(), true);
+  vc.rd++;
+  cell->write(d);
+  vc.wr++;
+  return d;
+}
+
+
+// SRL 8-bit
+u8_t
+cl_tlcs::op_srl(u8_t data, bool set_sz)
+{
+  u8_t c0= data & 0x01;
+  data>>= 1;
+  reg.raf.f&= ~((set_sz?(FLAG_S|FLAG_Z):0)|FLAG_H|FLAG_N|FLAG_C);
+  if (c0)
+    reg.raf.f|= FLAG_C;
+  
+  if (set_sz)
+    {
+      if (!data)
+	reg.raf.f|= FLAG_Z;
+      if (data&0x80)
+	reg.raf.f|= FLAG_S;
+      set_p(data);
+    }
+  
+  return data;
+}
+
+
+// SRL mem
+u8_t
+cl_tlcs::inst_srl(cl_memory_cell *cell)
+{
+  u8_t d= op_srl(cell->read(), true);
+  vc.rd++;
+  cell->write(d);
+  vc.wr++;
+  return d;
+}
+
+
+// RLD mem
+int
+cl_tlcs::inst_rld(class cl_memory_cell *cell)
+{
+  reg.raf.f&= ~(FLAG_H|FLAG_X|FLAG_N);
+
+  u8_t c= cell->read();
+  vc.rd++;
+  u8_t temp= reg.raf.a & 0x0f;
+  reg.raf.a= (reg.raf.a & 0xf0) + (c >> 4);
+  cell->write((c << 4) + temp);
+  vc.wr++;
+  set_p(reg.raf.a);
+  return resGO;
+}
+
+
+// RRD mem
+int
+cl_tlcs::inst_rrd(class cl_memory_cell *cell)
+{
+  reg.raf.f&= ~(FLAG_H|FLAG_X|FLAG_N);
+
+  u8_t c= cell->read();
+  vc.rd++;
+  u8_t temp= reg.raf.a & 0x0f;
+  reg.raf.a= (reg.raf.a & 0xf0) + (c & 0x0f);
+  cell->write((temp << 4) + (c >> 4));
+  vc.wr++;
+  set_p(reg.raf.a);
+  return resGO;
+}
+
+
+/* End of tlcs.src/inst_rot_sh.cc */
diff --git a/sim/ucsim/tlcs.src/inst_rot_sh.o b/sim/ucsim/tlcs.src/inst_rot_sh.o
new file mode 100644
index 0000000..cf0a619
--- /dev/null
+++ b/sim/ucsim/tlcs.src/inst_rot_sh.o
diff --git a/sim/ucsim/tlcs.src/mulibyte_instructions.txt b/sim/ucsim/tlcs.src/mulibyte_instructions.txt
new file mode 100644
index 0000000..5ab5639
--- /dev/null
+++ b/sim/ucsim/tlcs.src/mulibyte_instructions.txt
@@ -0,0 +1,381 @@
+-07	n					INCX (0ffn)
+-0F	n					DECX (0ffn)
+
+-12	n					MUL HL,n
+-13	n					DIV HL,n
+-14+ix	n	m				ADD ix,mn
+-17	d	c				LDAR HL,$+2+cd
+-18	d					DJNZ $+2+d
+-19	d					DJNZ BC,$+2+d
+-1A	n	m				JP mn
+-1B	d	c				JRL $+2+cd
+-1C	n	m				CALL mn
+-1D	d	c				CALR $+2+cd
+
+-27	n					LD A,(0ffn)
+-2F	n					LD (0ffn),A
+
+-30+r	n					LD r,n
+-37	w	n				LD (0ffw),n
+-38+rr	n	m				LD rr,mn
+-3F	w	n	m			LDW (0ffw),mn
+
+-47	n					LD HL,(0ffn)
+-4F	n					LD (0ffn),HL
+
+-60	n					ADD A,(0ffn)
+-61	n					ADC A,(0ffn)
+-62	n					SUB A,(0ffn)
+-63	n					SBC A,(0ffn)
+-64	n					AND A,(0ffn)
+-65	n					XOR A,(0ffn)
+-66	n					OR A,(0ffn)
+-67	n					CP A,(0ffn)
+-68	n					ADD A,n
+-69	n					ADC A,n
+-6A	n					SUB A,n
+-6B	n					SBC A,n
+-6C	n					AND A,n
+-6D	n					XOR A,n
+-6E	n					OR A,n
+-6F	n					CP A,n
+
+-70	n					ADD HL,(0ffn)
+-71	n					ADC HL,(0ffn)
+-72	n					SUB HL,(0ffn)
+-73	n					SBC HL,(0ffn)
+-74	n					AND HL,(0ffn)
+-75	n					XOR HL,(0ffn)
+-76	n					OR HL,(0ffn)
+-77	n					CP HL,(0ffn)
+-78	n	m				ADD HL,mn
+-79	n	m				ADC HL,mn
+-7A	n	m				SUB HL,mn
+-7B	n	m				SBC HL,mn
+-7C	n	m				AND HL,mn
+-7D	n	m				XOR HL,mn
+-7E	n	m				OR HL,mn
+-7F	n	m				CP HL,mn
+
+-87	n					INC (0ffn)
+-8F	n					DEC (0ffn)
+
+-90+rr						INC rr
+-97	n					INCW (0ffn)
+-98+rr						DEC rr
+-9F	n					DECW (0ffn)
+
+-A8+b	n					BIT b,(0ffn)
+
+-B0+b	n					RES b,(0ffn)
+
+-B8+b	n					SET b,(0ffn)
+
+-C0+cc	d					JR [cc,]$+2+d
+
+-E0+gg	10					RLD (gg)
+-E0+gg	11					RRD (gg)
+-E0+gg	12					MUL HL,(gg)
+-E0+gg	13					DIV HL,(gg)
+-E0+gg	14+ix					ADD ix,(gg)
+-E0+gg	18+b					TSET b,(gg)
+-E0+gg	28+r					LD r,(gg)
+-E0+gg	48+rr					LD rr,(gg)
+-E0+gg	50+rr					EX (gg),rr
+-E0+gg	60					ADD A,(gg)
+-E0+gg	61					ADC A,(gg)
+-E0+gg	62					SUB A,(gg)
+-E0+gg	63					SBC A,(gg)
+-E0+gg	64					AND A,(gg)
+-E0+gg	65					XOR A,(gg)
+-E0+gg	66					OR A,(gg)
+-E0+gg	67					CP A,(gg)
+-E0+gg	70					ADD HL,(gg)
+-E0+gg	71					ADC HL,(gg)
+-E0+gg	72					SUB HL,(gg)
+-E0+gg	73					SBC HL,(gg)
+-E0+gg	74					AND HL,(gg)
+-E0+gg	75					XOR HL,(gg)
+-E0+gg	76					OR HL,(gg)
+-E0+gg	77					CP HL,(gg)
+-E0+gg	87					INC (gg)
+-E0+gg	8F					DEC (gg)
+-E0+gg	97					INCW (gg)
+-E0+gg	9F					DECW (gg)
+-E0+gg	A0					RLC (gg)
+-E0+gg	A1					RRC (gg)
+-E0+gg	A2					RL (gg)
+-E0+gg	A3					RR (gg)
+-E0+gg	A4					SLA (gg)
+-E0+gg	A5					SRA (gg)
+-E0+gg	A6					SLL (gg)
+-E0+gg	A7					SRL (gg)
+-E0+gg	A8+b					BIT b,(gg)
+-E0+gg	B0+b					RES b,(gg)
+-E0+gg	B8+b					SET b,(gg)
+
+-E3	n	m	10			RLD (mn)
+-E3	n	m	11			RRD (mn)
+-E3	n	m	12			MUL HL,(mn)
+-E3	n	m	13			DIV HL,(mn)
+-E3	n	m	14+ix			ADD ix,(mn)
+-E3	n	m	18+b			TSET b,(mn)
+-E3	n	m	28+r			LD r,(mn)
+-E3	n	m	48+rr			LD rr,(nm)
+-E3	n	m	50+rr			EX (mn),rr
+-E3	n	m	60			ADD A,(mn)
+-E3	n	m	61			ADC A,(mn)
+-E3	n	m	62			SUB A,(mn)
+-E3	n	m	63			SBC A,(mn)
+-E3	n	m	64			AND A,(mn)
+-E3	n	m	65			XOR A,(mn)
+-E3	n	m	66			OR A,(mn)
+-E3	n	m	67			CP A,(mn)
+-E3	n	m	70			ADD HL,(mn)
+-E3	n	m	71			ADC HL,(mn)
+-E3	n	m	72			SUB HL,(mn)
+-E3	n	m	73			SBC HL,(mn)
+-E3	n	m	74			AND HL,(mn)
+-E3	n	m	75			XOR HL,(mn)
+-E3	n	m	76			OR HL,(mn)
+-E3	n	m	77			CP HL,(mn)
+-E3	n	m	87			INC (mn)
+-E3	n	m	8F			DEC (mn)
+-E3	n	m	97			INCW (mn)
+-E3	n	m	9F			DECW (mn)
+-E3	n	m	A0			RLC (mn)
+-E3	n	m	A1			RRC (mn)
+-E3	n	m	A2			RL (mn)
+-E3	n	m	A3			RR (mn)
+-E3	n	m	A4			SLA (mn)
+-E3	n	m	A5			SRA (mn)
+-E3	n	m	A6			SLL (mn)
+-E3	n	m	A7			SRL (mn)
+-E3	n	m	A8+b			BIT b,(mn)
+-E3	n	m	B0+b			RES b,(mn)
+-E3	n	m	B8+b			SET b,(mn)
+
+-E7	n	10				RLD (0ffn)
+-E7	n	11				RRD (0ffn)
+-E7	n	12				MUL HL,(0ffn)
+-E7	n	13				DIV HL,(0ffn)
+-E7	n	14+ix				ADD ix,(0ffn)
+-E7	n	18+b				TSET b,(0ffn)
+-E7	n	28+r				LD r,(0ffn)
+-E7	n	48+rr				LD rr,(0ffn)
+-E7	n	50+rr				EX (0ffn),rr
+-E7	n	A0				RLC (0ffn)
+-E7	n	A1				RRC (0ffn)
+-E7	n	A2				RL (0ffn)
+-E7	n	A3				RR (0ffn)
+-E7	n	A4				SLA (0ffn)
+-E7	n	A5				SRA (0ffn)
+-E7	n	A6				SLL (0ffn)
+-E7	n	A7				SRL (0ffn)
+
+-E8+gg	20+r					LD (gg),r
+-E8+gg	37	n				LD (gg),n
+-E8+gg	3F	n	m			LDW (gg),mn
+-E8+gg	40+rr					LD (gg),rr
+-E8+gg	68	n				ADD (gg),n
+-E8+gg	69	n				ADC (gg),n
+-E8+gg	6A	n				SUB (gg),n
+-E8+gg	6B	n				SBC (gg),n
+-E8+gg	6C	n				AND (gg),n
+-E8+gg	6D	n				XOR (gg),n
+-E8+gg	6E	n				OR (gg),n
+-E8+gg	6F	n				CP (gg),n
+-E8+gg	C0+cc					JP [cc,]gg
+-E8+gg	D0+cc					CALL [cc,]gg
+
+-EB	n	m	20+r			LD (mn),r
+-EB	w	v	37	n		LD (vw),n
+-EB	w	v	3F	n	m	LDW (vw),mn
+-EB	n	m	40+rr			LD (mn),rr
+-EB	w	v	68	n		ADD (vw),n
+-EB	w	v	69	n		ADC (vw),n
+-EB	w	v	6A	n		SUB (vw),n
+-EB	w	v	6B	n		SBC (vw),n
+-EB	w	v	6C	n		AND (vw),n
+-EB	w	v	6D	n		XOR (vw),n
+-EB	w	v	6E	n		OR (vw),n
+-EB	w	v	6F	n		CP (vw),n
+-EB	n	m	C0+cc			JP cc,mn
+-EB	n	m	D0+cc			CALL cc,mn
+
+-EF	n	20+r				LD (0ffn),r
+-EF	n	40+rr				LD (0ffn),rr
+-EF	w	68	n			ADD (0ffw),n
+-EF	w	69	n			ADC (0ffw),n
+-EF	w	6A	n			SUB (0ffw),n
+-EF	w	6B	n			SBC (0ffw),n
+-EF	w	6C	n			AND (0ffw),n
+-EF	w	6D	n			XOR (0ffw),n
+-EF	w	6E	n			OR (0ffw),n
+-EF	w	6F	n			CP (0ffw),n
+
+-F0+ix	d	10				RLD (ix+d)
+-F0+ix	d	11				RRD (ix+d)
+-F0+ix	d	12				MUL HL,(ix+d)
+-F0+ix	d	13				DIV HL,(ix+d)
+-F0+jx	d	14+ix				ADD ix,(jx+d)
+-F0+ix	d	18+b				TSET b,(ix+d)
+-F0+ix	d	28+r				LD r,(ix+d)
+-F0+ix	d	48+rr				LD rr,(ix+d)
+-F0+ix	d	50+rr				EX (ix+d),rr
+-F0+ix	d	60				ADD A,(ix+d)
+-F0+ix	d	61				ADC A,(ix+d)
+-F0+ix	d	62				SUB A,(ix+d)
+-F0+ix	d	63				SBC A,(ix+d)
+-F0+ix	d	64				AND A,(ix+d)
+-F0+ix	d	65				XOR A,(ix+d)
+-F0+ix	d	66				OR A,(ix+d)
+-F0+ix	d	67				CP A,(ix+d)
+-F0+ix	d	70				ADD HL,(ix+d)
+-F0+ix	d	71				ADC HL,(ix+d)
+-F0+ix	d	72				SUB HL,(ix+d)
+-F0+ix	d	73				SBC HL,(ix+d)
+-F0+ix	d	74				AND HL,(ix+d)
+-F0+ix	d	75				XOR HL,(ix+d)
+-F0+ix	d	76				OR HL,(ix+d)
+-F0+ix	d	77				CP HL,(ix+d)
+-F0+ix	d	87				INC (ix+d)
+-F0+ix	d	8F				DEC (ix+d)
+-F0+ix	d	97				INCW (ix+d)
+-F0+ix	d	9F				DECW (ix+d)
+-F0+ix	d	A0				RLC (ix+d)
+-F0+ix	d	A1				RRC (ix+d)
+-F0+ix	d	A2				RL (ix+d)
+-F0+ix	d	A3				RR (ix+d)
+-F0+ix	d	A4				SLA (ix+d)
+-F0+ix	d	A5				SRA (ix+d)
+-F0+ix	d	A6				SLL (ix+d)
+-F0+ix	d	A7				SRL (ix+d)
+-F0+ix	d	A8+b				BIT b,(ix+d)
+-F0+ix	d	B0+b				RES b,(ix+d)
+-F0+ix	d	B8+b				SET b,(ix+d)
+
+-F3	10					RLD (HL+A)
+-F3	11					RRD (HL+A)
+-F3	12					MUL HL,(HL+A)
+-F3	13					DIV HL,(HL+A)
+-F3	14+ix					ADD ix,(HL+A)
+-F3	18+b					TSET b,(HL+A)
+-F3	28+r					LD r,(HL+A)
+-F3	48+rr					LD rr,(HL+A)
+-F3	50+rr					EX (HL+A),rr
+-F3	60					ADD A,(HL+A)
+-F3	61					ADC A,(HL+A)
+-F3	62					SUB A,(HL+A)
+-F3	63					SBC A,(HL+A)
+-F3	64					AND A,(HL+A)
+-F3	65					XOR A,(HL+A)
+-F3	66					OR A,(HL+A)
+-F3	67					CP A,(HL+A)
+-F3	70					ADD HL,(HL+A)
+-F3	71					ADC HL,(HL+A)
+-F3	72					SUB HL,(HL+A)
+-F3	73					SBC HL,(HL+A)
+-F3	74					AND HL,(HL+A)
+-F3	75					XOR HL,(HL+A)
+-F3	76					OR HL,(HL+A)
+-F3	77					CP HL,(HL+A)
+-F3	87					INC (HL+A)
+-F3	8F					DEC (HL+A)
+-F3	97					INCW (HL+A)
+-F3	9F					DECW (HL+A)
+-F3	A0					RLC (HL+A)
+-F3	A1					RRC (HL+A)
+-F3	A2					RL (HL+A)
+-F3	A3					RR (HL+A)
+-F3	A4					SLA (HL+A)
+-F3	A5					SRA (HL+A)
+-F3	A6					SLL (HL+A)
+-F3	A7					SRL (HL+A)
+-F3	A8+b					BIT b,(HL+A)
+-F3	B0+b					RES b,(HL+A)
+-F3	B8+b					SET b,(HL+A)
+
+-F4+ix	d	20+r				LD (ix+d),r
+-F4+ix	d	37	n			LD (ix+d),n
+-F4+ix	d	38+rr				LDA rr,ix+d
+-F4+ix	d	3F	n	m		LDW (ix+d),mn
+-F4+ix	d	40+rr				LD (ix+d),rr
+-F4+ix	d	68	n			ADD (ix+d),n
+-F4+ix	d	69	n			ADC (ix+d),n
+-F4+ix	d	6A	n			SUB (ix+d),n
+-F4+ix	d	6B	n			SBC (ix+d),n
+-F4+ix	d	6C	n			AND (ix+d),n
+-F4+ix	d	6D	n			XOR (ix+d),n
+-F4+ix	d	6E	n			OR (ix+d),n
+-F4+ix	d	6F	n			CP (ix+d),n
+-F4+ix	d	C0+cc				JP [cc,]ix+d
+-F4+ix	d	D0+cc				CALL [cc,]ix+d
+
+-F7	20+r					LD (HL+A),r
+-F7	37	n				LD (HL+A),n
+-F7	38+rr					LDA rr,HL+A
+-F7	3F	n	m			LDW (HL+A),mn
+-F7	40+rr					LD (HL+A),rr
+-F7	68	n				ADD (HL+A),n
+-F7	69	n				ADC (HL+A),n
+-F7	6A	n				SUB (HL+A),n
+-F7	6B	n				SBC (HL+A),n
+-F7	6C	n				AND (HL+A),n
+-F7	6D	n				XOR (HL+A),n
+-F7	6E	n				OR (HL+A),n
+-F7	6F	n				CP (HL+A),n
+-F7	C0+cc					JP [cc,]HL+A
+-F7	D0+cc					CALL [cc,]HL+A
+
+-F8+g	12					MUL HL,g
+-F8+g	13					DIV HL,g
+-F8+gg	14+ix					ADD ix,gg
+-F8+g	18+b					TSET b,g
+-F8+g	30+r					LD r,g
+-F8+gg	38+rr					LD rr,gg
+-F8+g	60					ADD A,g
+-F8+g	61					ADC A,g
+-F8+g	62					SUB A,g
+-F8+g	63					SBC A,g
+-F8+g	64					AND A,g
+-F8+g	65					XOR A,g
+-F8+g	66					OR A,g
+-F8+g	67					CP A,g
+-F8+g	68	n				ADD g,n
+-F8+g	69	n				ADC g,n
+-F8+g	6A	n				SUB g,n
+-F8+g	6B	n				SBC g,n
+-F8+g	6C	n				AND g,n
+-F8+g	6D	n				XOR g,n
+-F8+g	6E	n				OR g,n
+-F8+g	6F	n				CP g,n
+-F8+gg	70					ADD HL,gg
+-F8+gg	71					ADC HL,gg
+-F8+gg	72					SUB HL,gg
+-F8+gg	73					SBC HL,gg
+-F8+gg	74					AND HL,gg
+-F8+gg	75					XOR HL,gg
+-F8+gg	76					OR HL,gg
+-F8+gg	77					CP HL,gg
+-F8+g	A0					RLC g
+-F8+g	A1					RRC g
+-F8+g	A2					RL g
+-F8+g	A3					RR g
+-F8+g	A4					SLA g
+-F8+g	A5					SRA g
+-F8+g	A6					SLL g
+-F8+g	A7					SRL g
+-F8+g	A8+b					BIT b,g
+-F8+g	B0+b					RES b,g
+-F8+g	B8+b					SET b,g
+
+-FE	58					LDI
+-FE	59					LDIR
+-FE	5A					LDD
+-FE	5B					LDDR
+-FE	5C					CPI
+-FE	5D					CPIR
+-FE	5E					CPD
+-FE	5F					CPDR
+-FE	D0+cc					RET cc
diff --git a/sim/ucsim/tlcs.src/regression.txt b/sim/ucsim/tlcs.src/regression.txt
new file mode 100644
index 0000000..9ea8430
--- /dev/null
+++ b/sim/ucsim/tlcs.src/regression.txt
@@ -0,0 +1,18 @@
+
+Summary for 'tlcs90': 88 failures, 9594 tests, 1783 test cases, 2805727 bytes, 14862813 ticks
+   Failure: gen/tlcs90/bug1057979/bug1057979
+   Failure: gen/tlcs90/bug3474855/bug3474855
+   Failure: gen/tlcs90/gcc-torture-execute-20010224-1/gcc-torture-execute-20010224-1
+   Failure: gen/tlcs90/gcc-torture-execute-20030221-1/gcc-torture-execute-20030221-1
+   Failure: gen/tlcs90/gcc-torture-execute-20030626-2/gcc-torture-execute-20030626-2
+   Failure: gen/tlcs90/gcc-torture-execute-20031012-1/gcc-torture-execute-20031012-1
+   Failure: gen/tlcs90/gcc-torture-execute-20111208-1/gcc-torture-execute-20111208-1
+   Failure: gen/tlcs90/gcc-torture-execute-950426-1/gcc-torture-execute-950426-1
+   Failure: gen/tlcs90/gcc-torture-execute-980506-3/gcc-torture-execute-980506-3
+   Failure: gen/tlcs90/gcc-torture-execute-string-opt-5/gcc-torture-execute-string-opt-5
+   Failure: gen/tlcs90/memory/memory
+   Failure: results/tlcs90/setjmp.out
+   Failure: gen/tlcs90/snprintf/snprintf_type_STRING
+   Failure: gen/tlcs90/string/string
+
+drdani@anb:~/prj/s6/support/regression$ 
diff --git a/sim/ucsim/tlcs.src/simtlcs.cc b/sim/ucsim/tlcs.src/simtlcs.cc
new file mode 100644
index 0000000..d6a6ad2
--- /dev/null
+++ b/sim/ucsim/tlcs.src/simtlcs.cc
@@ -0,0 +1,47 @@
+/*
+ * Simulator of microcontrollers (tlcs.src/simtlcs.cc)
+ *
+ * Copyright (C) 2016,16 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+// sim.src
+#include "appcl.h"
+
+// local
+#include "simtlcscl.h"
+#include "tlcscl.h"
+
+
+cl_simtlcs::cl_simtlcs(class cl_app *the_app):
+  cl_sim(the_app)
+{}
+
+class cl_uc *
+cl_simtlcs::mk_controller(void)
+{
+  return(new cl_tlcs(this));
+}
+
+
+/* End of tlcs.src/simtlcs.cc */
diff --git a/sim/ucsim/tlcs.src/simtlcs.o b/sim/ucsim/tlcs.src/simtlcs.o
new file mode 100644
index 0000000..affd092
--- /dev/null
+++ b/sim/ucsim/tlcs.src/simtlcs.o
diff --git a/sim/ucsim/tlcs.src/simtlcscl.h b/sim/ucsim/tlcs.src/simtlcscl.h
new file mode 100644
index 0000000..b93f25a
--- /dev/null
+++ b/sim/ucsim/tlcs.src/simtlcscl.h
@@ -0,0 +1,45 @@
+/*
+ * Simulator of microcontrollers (tlcs.src/simtlcscl.h)
+ *
+ * Copyright (C) 2016,16 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#ifndef SIMTLCSCL_HEADER
+#define SIMTLCSCL_HEADER
+
+#include "simcl.h"
+
+
+class cl_simtlcs: public cl_sim
+{
+ public:
+  cl_simtlcs(class cl_app *the_app);
+
+  virtual class cl_uc *mk_controller(void);
+};
+
+
+#endif
+
+/* End of tlcs.src/simtlcscl.h */
diff --git a/sim/ucsim/tlcs.src/stlcs b/sim/ucsim/tlcs.src/stlcs
new file mode 100755
index 0000000..ee76b2b
--- /dev/null
+++ b/sim/ucsim/tlcs.src/stlcs
diff --git a/sim/ucsim/tlcs.src/stlcs.cc b/sim/ucsim/tlcs.src/stlcs.cc
new file mode 100644
index 0000000..08e3c56
--- /dev/null
+++ b/sim/ucsim/tlcs.src/stlcs.cc
@@ -0,0 +1,58 @@
+/*
+ * Simulator of microcontrollers (tlcs.src/stlcs.cc)
+ *
+ * Copyright (C) 2016,16 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#include <stdio.h>
+
+// prj
+#include "globals.h"
+
+// sim.src
+#include "appcl.h"
+
+// local
+#include "simtlcscl.h"
+
+int
+main(int argc, char *argv[])
+{
+  int retval;
+  class cl_sim *sim;
+  
+  application= new cl_app();
+  application->init(argc, argv);
+  sim= new cl_simtlcs(application);
+  if (sim->init())
+    sim->state|= SIM_QUIT;
+  application->set_simulator(sim);
+  retval= application->run();
+  application->done();
+  delete application;
+  
+  return(retval);
+}
+
+/* End of tlcs.src/stlcs.cc */
diff --git a/sim/ucsim/tlcs.src/stlcs.o b/sim/ucsim/tlcs.src/stlcs.o
new file mode 100644
index 0000000..e2231aa
--- /dev/null
+++ b/sim/ucsim/tlcs.src/stlcs.o
diff --git a/sim/ucsim/tlcs.src/test/Makefile b/sim/ucsim/tlcs.src/test/Makefile
new file mode 100644
index 0000000..0db0fb2
--- /dev/null
+++ b/sim/ucsim/tlcs.src/test/Makefile
@@ -0,0 +1,11 @@
+PRJ		= t0 t1 t2 t3 b2385
+
+all:
+	for p in $(PRJ); do \
+		$(MAKE) -f $$p.mk ;\
+	done
+
+clean:
+	for p in $(PRJ); do \
+		$(MAKE) -f $$p.mk clean ;\
+	done
diff --git a/sim/ucsim/tlcs.src/test/b2385.c b/sim/ucsim/tlcs.src/test/b2385.c
new file mode 100644
index 0000000..2af8aed
--- /dev/null
+++ b/sim/ucsim/tlcs.src/test/b2385.c
@@ -0,0 +1,18 @@
+struct ts { int a; };
+
+typedef struct ts *pts;
+
+pts s;
+
+int test(void)
+{
+  pts ps;
+  ps= s;
+  //return ps->a; // GOOD
+  return (ps= s)->a; // FAIL
+}
+
+void main(void)
+{
+  test();
+}
diff --git a/sim/ucsim/tlcs.src/test/b2385.mk b/sim/ucsim/tlcs.src/test/b2385.mk
new file mode 100644
index 0000000..f3c4ba4
--- /dev/null
+++ b/sim/ucsim/tlcs.src/test/b2385.mk
@@ -0,0 +1,3 @@
+MAIN		= b2385
+
+include sdcc.mk
diff --git a/sim/ucsim/tlcs.src/test/conf.cmd b/sim/ucsim/tlcs.src/test/conf.cmd
new file mode 100644
index 0000000..29c9c01
--- /dev/null
+++ b/sim/ucsim/tlcs.src/test/conf.cmd
@@ -0,0 +1 @@
+set hw simif nas 0x7fff
diff --git a/sim/ucsim/tlcs.src/test/dummy.h b/sim/ucsim/tlcs.src/test/dummy.h
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/sim/ucsim/tlcs.src/test/dummy.h
diff --git a/sim/ucsim/tlcs.src/test/run.cmd b/sim/ucsim/tlcs.src/test/run.cmd
new file mode 100644
index 0000000..972da4f
--- /dev/null
+++ b/sim/ucsim/tlcs.src/test/run.cmd
@@ -0,0 +1,2 @@
+run
+state
diff --git a/sim/ucsim/tlcs.src/test/run.sh b/sim/ucsim/tlcs.src/test/run.sh
new file mode 100755
index 0000000..eb223eb
--- /dev/null
+++ b/sim/ucsim/tlcs.src/test/run.sh
@@ -0,0 +1,7 @@
+PRJ=$1
+
+if [ -z "$PRJ" ]; then
+   PRJ=t1
+fi
+
+../stlcs -C conf.cmd ${PRJ}.ihx <run.cmd
diff --git a/sim/ucsim/tlcs.src/test/sdcc.mk b/sim/ucsim/tlcs.src/test/sdcc.mk
new file mode 100644
index 0000000..a5470f2
--- /dev/null
+++ b/sim/ucsim/tlcs.src/test/sdcc.mk
@@ -0,0 +1,43 @@
+TARGET		= tlcs90
+
+CC		= sdcc -m$(TARGET)
+
+CPPFLAGS	=
+CFLAGS		= --fverbose-asm -DNO_VARARGS --debug
+LDFLAGS		=
+LIBS		=
+
+ALL		= $(MAIN) $(OTHERS)
+OBJECTS		= $(MAIN).rel $(OTHERS:=.rel)
+
+all: $(MAIN).hex
+
+dep: $(MAIN).dep
+
+$(MAIN).dep: $(OBJECTS:.rel=.c) *.h
+	@>$(MAIN).dep
+	@for c in $(OBJECTS:.rel=.c); do \
+		$(CC) -MM $(CPPFALGS) $$c >>$(MAIN).dep ;\
+	done
+
+include $(MAIN).dep
+
+$(MAIN).ihx: $(OBJECTS)
+	$(CC) $(CFLAGS) $(LDFLAGS) $(OBJECTS) -o $@
+
+.SUFFIXES: .rel .ihx .hex
+
+.c.rel:
+	$(CC) -c $(CPPFLAGS) $(CFLAGS) $<
+
+.ihx.hex:
+	packihx $< >$@
+
+clean:
+	rm -f $(ALL:=.rel) $(ALL:=.asm) $(ALL:=.lst) $(ALL:=.rst) $(ALL:=.sym) $(ALL:=.adb)
+	rm -f $(MAIN).ihx $(MAIN).hex $(MAIN).lk $(MAIN).map $(MAIN).mem $(MAIN).cdb $(MAIN).omf $(MAIN).noi
+	rm -f *~
+	rm -f $(MAIN).dep
+
+
+# End of sdcc.mk
diff --git a/sim/ucsim/tlcs.src/test/t0.c b/sim/ucsim/tlcs.src/test/t0.c
new file mode 100644
index 0000000..59cedb3
--- /dev/null
+++ b/sim/ucsim/tlcs.src/test/t0.c
@@ -0,0 +1,12 @@
+static unsigned char * volatile sif= (unsigned char *)0xffff;
+
+void main(void)
+{
+  unsigned int i, j;
+
+  for (i=0; i<0x2233; i++)
+    j= i;
+  *sif= 's';
+  for (;;)
+    ;
+}
diff --git a/sim/ucsim/tlcs.src/test/t0.mk b/sim/ucsim/tlcs.src/test/t0.mk
new file mode 100644
index 0000000..6f11fe4
--- /dev/null
+++ b/sim/ucsim/tlcs.src/test/t0.mk
@@ -0,0 +1,3 @@
+MAIN		= t0
+
+include sdcc.mk
diff --git a/sim/ucsim/tlcs.src/test/t1.c b/sim/ucsim/tlcs.src/test/t1.c
new file mode 100644
index 0000000..071bf52
--- /dev/null
+++ b/sim/ucsim/tlcs.src/test/t1.c
@@ -0,0 +1,37 @@
+static unsigned char * volatile sif= (unsigned char *)0x7fff;
+
+volatile unsigned char x;
+
+void
+putchar(unsigned char c)
+{
+  *sif= 'p';
+  *sif= c;
+}
+
+void
+prints(char *s)
+{
+  while (*s)
+    putchar(*s++);
+}
+
+void
+main(void)
+{
+  unsigned char i;
+  unsigned int j;
+
+  prints("Start.\n");
+  for (j= 0; j<41000; j++)
+    {
+      x= j;
+      i= j;
+      putchar('a');
+    }
+
+  prints("Done.\n");
+  *sif= 's';
+  for (;;)
+    ;
+}
diff --git a/sim/ucsim/tlcs.src/test/t1.mk b/sim/ucsim/tlcs.src/test/t1.mk
new file mode 100644
index 0000000..dee0618
--- /dev/null
+++ b/sim/ucsim/tlcs.src/test/t1.mk
@@ -0,0 +1,3 @@
+MAIN		= t1
+
+include sdcc.mk
diff --git a/sim/ucsim/tlcs.src/test/t2.c b/sim/ucsim/tlcs.src/test/t2.c
new file mode 100644
index 0000000..50debbb
--- /dev/null
+++ b/sim/ucsim/tlcs.src/test/t2.c
@@ -0,0 +1,36 @@
+static unsigned char * volatile sif= (unsigned char *)0xffff;
+
+volatile unsigned char x;
+
+void
+putchar(unsigned char c)
+{
+  *sif= 'p';
+  *sif= c;
+}
+
+void
+prints(char *s)
+{
+  while (*s)
+    putchar(*s++);
+}
+
+void
+main(void)
+{
+  unsigned int i;
+  unsigned int j;
+
+  prints("Start.\n");
+  for (j= 0; j<200; j++)
+    {
+      for (i= 1000; i; i--)
+	putchar('a');
+    }
+
+  prints("Done.\n");
+  *sif= 's';
+  for (;;)
+    ;
+}
diff --git a/sim/ucsim/tlcs.src/test/t2.mk b/sim/ucsim/tlcs.src/test/t2.mk
new file mode 100644
index 0000000..c2dd6e7
--- /dev/null
+++ b/sim/ucsim/tlcs.src/test/t2.mk
@@ -0,0 +1,3 @@
+MAIN		= t2
+
+include sdcc.mk
diff --git a/sim/ucsim/tlcs.src/test/t3.c b/sim/ucsim/tlcs.src/test/t3.c
new file mode 100644
index 0000000..9482115
--- /dev/null
+++ b/sim/ucsim/tlcs.src/test/t3.c
@@ -0,0 +1,17 @@
+const unsigned char a[2]= { 0x11, 0x22 };
+
+void __fail(char *s)
+{
+}
+
+#define ASSERT(_a)  ((_a) ? (void)0 : __fail ("Assertion failed", #_a, __FILE__, __LINE__))
+
+volatile unsigned char idx;
+
+void main(void)
+{
+  volatile unsigned char c;
+  idx= 1;
+  (a[idx]==0x22)?(void)0:__fail("s");
+  while (1) ;
+}
diff --git a/sim/ucsim/tlcs.src/test/t3.mk b/sim/ucsim/tlcs.src/test/t3.mk
new file mode 100644
index 0000000..f651106
--- /dev/null
+++ b/sim/ucsim/tlcs.src/test/t3.mk
@@ -0,0 +1,3 @@
+MAIN		= t3
+
+include sdcc.mk
diff --git a/sim/ucsim/tlcs.src/tlcs.cc b/sim/ucsim/tlcs.src/tlcs.cc
new file mode 100644
index 0000000..235ba26
--- /dev/null
+++ b/sim/ucsim/tlcs.src/tlcs.cc
@@ -0,0 +1,1827 @@
+/*
+ * Simulator of microcontrollers (tlcs.src/tlcs.cc)
+ *
+ * Copyright (C) 2016,16 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#include "ddconfig.h"
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <ctype.h>
+#include "i_string.h"
+
+// prj
+#include "pobjcl.h"
+
+// sim
+#include "simcl.h"
+#include "memcl.h"
+#include "stackcl.h"
+
+// local
+#include "tlcscl.h"
+#include "glob.h"
+
+
+/*
+ * Base type of TLCS microcontrollers
+ */
+
+cl_tlcs::cl_tlcs(class cl_sim *asim):
+  cl_uc(asim)
+{
+  //type= CPU_TLCS;
+  //sleep_executed= 0;
+  regs8= new cl_address_space("regs8", 0, 16, 8);
+  regs8->init();
+  regs8->get_cell(0)->decode((t_mem*)&reg.raf.a);
+  regs8->get_cell(1)->decode((t_mem*)&reg.raf.f);
+  regs8->get_cell(2)->decode((t_mem*)&reg.rbc.b);
+  regs8->get_cell(3)->decode((t_mem*)&reg.rbc.c);
+  regs8->get_cell(4)->decode((t_mem*)&reg.rde.d);
+  regs8->get_cell(5)->decode((t_mem*)&reg.rde.e);
+  regs8->get_cell(6)->decode((t_mem*)&reg.rhl.h);
+  regs8->get_cell(7)->decode((t_mem*)&reg.rhl.l);
+
+  regs8->get_cell(8)->decode((t_mem*)&reg.ralt_af.alt_a);
+  regs8->get_cell(9)->decode((t_mem*)&reg.ralt_af.alt_f);
+  regs8->get_cell(10)->decode((t_mem*)&reg.ralt_bc.alt_b);
+  regs8->get_cell(11)->decode((t_mem*)&reg.ralt_bc.alt_c);
+  regs8->get_cell(12)->decode((t_mem*)&reg.ralt_de.alt_d);
+  regs8->get_cell(13)->decode((t_mem*)&reg.ralt_de.alt_e);
+  regs8->get_cell(14)->decode((t_mem*)&reg.ralt_hl.alt_h);
+  regs8->get_cell(15)->decode((t_mem*)&reg.ralt_hl.alt_l);
+
+  regs16= new cl_address_space("regs16", 0, 11, 16);
+  regs16->init();
+
+  regs16->get_cell(0)->decode((t_mem*)&reg.af);
+  regs16->get_cell(1)->decode((t_mem*)&reg.bc);
+  regs16->get_cell(2)->decode((t_mem*)&reg.de);
+  regs16->get_cell(3)->decode((t_mem*)&reg.hl);
+  regs16->get_cell(4)->decode((t_mem*)&reg.ix);
+  regs16->get_cell(5)->decode((t_mem*)&reg.iy);
+  regs16->get_cell(6)->decode((t_mem*)&reg.sp);
+  regs16->get_cell(7)->decode((t_mem*)&reg.alt_af);
+  regs16->get_cell(8)->decode((t_mem*)&reg.alt_bc);
+  regs16->get_cell(9)->decode((t_mem*)&reg.alt_de);
+  regs16->get_cell(10)->decode((t_mem*)&reg.alt_hl);
+
+  address_spaces->add(regs8);
+  address_spaces->add(regs16);
+}
+
+int
+cl_tlcs::init(void)
+{
+  class cl_var *v;
+
+  cl_uc::init(); /* Memories now exist */
+  //ram= address_space(MEM_IRAM_ID);
+  //rom= address_space(MEM_ROM_ID);
+
+  // zero out ram(this is assumed in regression tests)
+  for (int i=0x8000; i<0x10000; i++) {
+    nas->set((t_addr) i, 0);
+  }
+
+  vars->add(v= new cl_var(cchars("A"), regs8, 0, ""));
+  v->init();
+  vars->add(v= new cl_var(cchars("F"), regs8, 1, ""));
+  v->init();
+  vars->add(v= new cl_var(cchars("B"), regs8, 2, ""));
+  v->init();
+  vars->add(v= new cl_var(cchars("C"), regs8, 3, ""));
+  v->init();
+  vars->add(v= new cl_var(cchars("D"), regs8, 4, ""));
+  v->init();
+  vars->add(v= new cl_var(cchars("E"), regs8, 5, ""));
+  v->init();
+  vars->add(v= new cl_var(cchars("H"), regs8, 6, ""));
+  v->init();
+  vars->add(v= new cl_var(cchars("L"), regs8, 7, ""));
+  v->init();
+
+  vars->add(v= new cl_var(cchars("ALT_A"), regs8, 8, ""));
+  v->init();
+  vars->add(v= new cl_var(cchars("ALT_F"), regs8, 9, ""));
+  v->init();
+  vars->add(v= new cl_var(cchars("ALT_B"), regs8, 10, ""));
+  v->init();
+  vars->add(v= new cl_var(cchars("ALT_C"), regs8, 11, ""));
+  v->init();
+  vars->add(v= new cl_var(cchars("ALT_D"), regs8, 12, ""));
+  v->init();
+  vars->add(v= new cl_var(cchars("ALT_E"), regs8, 13, ""));
+  v->init();
+  vars->add(v= new cl_var(cchars("ALT_H"), regs8, 14, ""));
+  v->init();
+  vars->add(v= new cl_var(cchars("ALT_L"), regs8, 15, ""));
+  v->init();
+
+  vars->add(v= new cl_var(cchars("AF"), regs16, 0, ""));
+  v->init();
+  vars->add(v= new cl_var(cchars("BC"), regs16, 1, ""));
+  v->init();
+  vars->add(v= new cl_var(cchars("DE"), regs16, 2, ""));
+  v->init();
+  vars->add(v= new cl_var(cchars("HL"), regs16, 3, ""));
+  v->init();
+  vars->add(v= new cl_var(cchars("IX"), regs16, 4, ""));
+  v->init();
+  vars->add(v= new cl_var(cchars("IY"), regs16, 5, ""));
+  v->init();
+  vars->add(v= new cl_var(cchars("SP"), regs16, 6, ""));
+  v->init();
+  vars->add(v= new cl_var(cchars("ALT_AF"), regs16, 7, ""));
+  v->init();
+  vars->add(v= new cl_var(cchars("ALT_BC"), regs16, 8, ""));
+  v->init();
+  vars->add(v= new cl_var(cchars("ALT_DE"), regs16, 9, ""));
+  v->init();
+  vars->add(v= new cl_var(cchars("ALT_HL"), regs16, 11, ""));
+  v->init();
+
+  return(0);
+}
+
+char *
+cl_tlcs::id_string(void)
+{
+  return((char*)"unspecified TLCS");
+}
+
+
+void
+cl_tlcs::mk_hw_elements(void)
+{
+  //class cl_base *o;
+  //hws->add(o= new cl_port(this));
+  //o->init();
+  cl_uc::mk_hw_elements();
+}
+
+
+void
+cl_tlcs::make_memories(void)
+{
+  class cl_address_space *as;
+
+  rom= nas= as= new cl_address_space(cchars("nas"), 0, 0x10000, 8);
+  as->init();
+  address_spaces->add(as);
+  xas= as= new cl_address_space(cchars("xas"), 0, 0x10000, 8);
+  as->init();
+  address_spaces->add(as);
+  yas= as= new cl_address_space(cchars("yas"), 0, 0x10000, 8);
+  as->init();
+  address_spaces->add(as);
+
+  class cl_address_decoder *ad;
+  class cl_memory_chip *chip;
+
+  chip= new cl_memory_chip("nas_chip", 0x10000, 8);
+  chip->init();
+  memchips->add(chip);
+  ad= new cl_address_decoder(as= nas,
+			     chip, 0, 0xffff, 0);
+  ad->init();
+  as->decoders->add(ad);
+  ad->activate(0);
+
+  //chip= new cl_memory_chip("das_chip", 0x10000, 8);
+  //chip->init();
+  //memchips->add(chip);
+  ad= new cl_address_decoder(as= xas,
+			     chip, 0, 0xffff, 0);
+  ad->init();
+  as->decoders->add(ad);
+  ad->activate(0);
+
+  ad= new cl_address_decoder(as= yas,
+			     chip, 0, 0xffff, 0);
+  ad->init();
+  as->decoders->add(ad);
+  ad->activate(0);
+}
+
+
+struct dis_entry *
+cl_tlcs::dis_tbl(void)
+{
+  return disass_tlcs;
+}
+
+//virtual struct name_entry *sfr_tbl(void);
+//virtual struct name_entry *bit_tbl(void);
+
+const char *
+cl_tlcs::regname_r(u8_t r)
+{
+  switch (r & 7)
+    {
+    case 0: return "B";
+    case 1: return "C";
+    case 2: return "D";
+    case 3: return "E";
+    case 4: return "H";
+    case 5: return "L";
+    case 6: return "A";
+    default: return "?";
+    }
+}
+
+const char *
+cl_tlcs::regname_R(u8_t R)
+{
+  switch (R & 7)
+    {
+    case 0: return "BC";
+    case 1: return "DE";
+    case 2: return "HL";
+    case 4: return "IX";
+    case 5: return "IY";
+    case 6: return "SP";
+    default: return "?";
+    }
+}
+
+const char *
+cl_tlcs::regname_Q(u8_t Q)
+{
+  switch (Q & 7)
+    {
+    case 0: return "BC";
+    case 1: return "DE";
+    case 2: return "HL";
+    case 4: return "IX";
+    case 5: return "IY";
+    case 6: return "AF";
+    default: return "?";
+    }
+}
+
+const char *
+cl_tlcs::regname_i(u8_t i)
+{
+  switch (i & 3)
+    {
+    case 0: return "IX";
+    case 1: return "IY";
+    case 2: return "SP";
+    default: return "?";
+    }
+}
+
+const char *
+cl_tlcs::bitname(u8_t b)
+{
+  switch (b & 0x07)
+    {
+    case 0: return "0";
+    case 1: return "1";
+    case 2: return "2";
+    case 3: return "3";
+    case 4: return "4";
+    case 5: return "5";
+    case 6: return "6";
+    case 7: return "7";
+    }
+  return "?";
+}
+
+const char *
+cl_tlcs::condname_cc(u8_t cc)
+{
+  switch (cc & 0xf)
+    {
+    case 0: return "F,";
+    case 1: return "LT,";
+    case 2: return "LE,";
+    case 3: return "ULE,";
+    case 4: return "OV,";
+    case 5: return "M,";
+    case 6: return "Z,";
+    case 7: return "C,";
+    case 8: return "";
+    case 9: return "GE,";
+    case 10: return "GT,";
+    case 11: return "UGT,";
+    case 12: return "NOV,";
+    case 13: return "P,";
+    case 14: return "NZ,";
+    case 15: return "NC,";
+    }
+  return "?";
+}
+
+const char *
+cl_tlcs::condname_C(u8_t cc)
+{
+  switch (cc & 0xf)
+    {
+    case 0: return "F";
+    case 1: return "LT";
+    case 2: return "LE";
+    case 3: return "ULE";
+    case 4: return "OV";
+    case 5: return "M";
+    case 6: return "Z";
+    case 7: return "C";
+    case 8: return "";
+    case 9: return "GE";
+    case 10: return "GT";
+    case 11: return "UGT";
+    case 12: return "NOV";
+    case 13: return "P";
+    case 14: return "NZ";
+    case 15: return "NC";
+    }
+  return "?";
+}
+
+char *
+cl_tlcs::disass(t_addr addr, const char *sep)
+{
+  struct dis_entry *de;
+  u64_t c;
+  int i;
+  chars s("");
+  char *buf, *t, l[20];
+  
+  c= 0;
+  for (i= 7; i>=0; i--)
+    {
+      u8_t cb= rom->get(addr+i);
+      c<<= 8;
+      c|= cb;
+    }
+
+  de= dis_tbl();
+  while (de->mnemonic != NULL)
+    {
+      if ((c & de->mask) == u64_t(de->code))
+	break;
+      de++;
+    }
+  if (de->mnemonic == NULL)
+    return strdup("?");
+
+  for (t= (char*)de->mnemonic; *t; t++)
+    {
+      if (*t == '%')
+	{
+	  t++;
+	  switch (*t)
+	    {
+	    case 'r': /*  r in 1st byte */ s+= regname_r(c); break;
+	    case 'p': /*  r in 2nd byte */ s+= regname_r(c>>8); break;
+	    case 't': /*  r in 3rd byte */ s+= regname_r(c>>16); break;
+	    case 'T': /*  r in 4th byte */ s+= regname_r(c>>24); break;
+	    case 'R': /* rr in 1st byte */ s+= regname_R(c); break;
+	    case 's': /* rr in 2nd byte */ s+= regname_R(c>>8); break;
+	    case 'u': /* rr in 3rd byte */ s+= regname_R(c>>16); break;
+	    case 'U': /* rr in 4th byte */ s+= regname_R(c>>24); break;
+	    case 'Q': /* qq in 1st byte */ s+= regname_Q(c); break;
+	    case 'I': /* ix in 1st byte */ s+= regname_i(c); break;
+	    case 'i': /* ix in 2nd byte */ s+= regname_i(c>>8); break;
+	    case 'j': /* ix in 3rd byte */ s+= regname_i(c>>16); break;
+	    case 'J': /* ix in 4th byte */ s+= regname_i(c>>24); break;
+	    case 'a': /*  b in 1st byte */ s+= bitname(c); break;
+	    case 'b': /*  b in 2nd byte */ s+= bitname(c>>8); break;
+	    case 'B': /*  b in 3rd byte */ s+= bitname(c>>16); break;
+	    case 'e': /*  b in 4th byte */ s+= bitname(c>>24); break;
+	    case 'y': /* cc in 1st byte */ s+= condname_cc(c); break; // with ,
+	    case 'c': /* cc in 2nd byte */ s+= condname_cc(c>>8); break; // with ,
+	    case 'C': /* cc in 2nd byte */ s+= condname_C(c>>8); break; // without ,
+	    case 'f': /* cc in 4th byte */ s+= condname_cc(c>>24); break; // with ,
+	    case 'F': /* cc in 3rd byte */ s+= condname_cc(c>>16); break; // with ,
+	    case 'n': /*  n in 2nd byte */ snprintf(l,19,"%02x",(int)((c>>8)&0xff));s+= l; break;
+	    case 'N': /*  n in 3rd byte */ snprintf(l,19,"%02x",(int)((c>>16)&0xff));s+= l; break;
+	    case 'o': /*  n in 4th byte */ snprintf(l,19,"%02x",(int)((c>>24)&0xff));s+= l; break;
+	    case 'O': /*  n in 5th byte */ snprintf(l,19,"%02x",(int)((c>>32)&0xff));s+= l; break;
+	    case '1': /*  PC+2+d in 2nd byte */ snprintf(l,19,"0x%04x",(int)(addr+2+i8_t((c>>8)&0xff))); s+= l; break;
+	    case 'd': /*  d in 2nd byte */ snprintf(l,19,"%+d",(int)(i8_t((c>>8)&0xff))); s+= l; break;
+	    case 'D': /* cd in 2,3 byte */ snprintf(l,19,"0x%04x",(int)(addr+3+i16_t((c>>8)&0xffff))); s+= l; break;	      
+	    case 'M': /* mn in 2,3 byte */ snprintf(l,19,"0x%04x",(int)((c>>8)&0xffff)); s+= l; break;
+	    case 'm': /* mn in 3,4 byte */ snprintf(l,19,"0x%04x",(int)((c>>16)&0xffff)); s+= l; break;
+	    case 'X': /* mn in 4,5 byte */ snprintf(l,19,"0x%04x",(int)((c>>24)&0xffff)); s+= l; break;
+	    case 'x': /* mn in 5,6 byte */ snprintf(l,19,"0x%04x",(int)((c>>32)&0xffff)); s+= l; break;
+	    default: s+= '?'; break;
+	    }
+	}
+      else
+	s+= *t;
+    }
+  
+  buf= strdup(s);
+  return buf;
+}
+
+int
+cl_tlcs::inst_length(t_addr addr)
+{
+  struct dis_entry *de;
+  u64_t c;
+  int i;
+  
+  c= 0;
+  for (i= 7; i>=0; i--)
+    {
+      u8_t cb= rom->get(addr+i);
+      c<<= 8;
+      c|= cb;
+    }
+
+  de= dis_tbl();
+  while (de->mnemonic != NULL)
+    {
+      if ((c & de->mask) == u64_t(de->code))
+	break;
+      de++;
+    }
+  if (de->mnemonic == NULL)
+    return 1;
+  if (de->length == 1)
+    return 1;
+  else
+    return de->length;
+}
+
+void
+cl_tlcs::print_regs(class cl_console_base *con)
+{
+  con->dd_printf("SZIHXVNC  Flags= 0x%02x %3d %c  ",
+                 reg.raf.f, reg.raf.f, isprint(reg.raf.f)?reg.raf.f:'.');
+  con->dd_printf("A= 0x%02x %3d %c\n",
+                 reg.raf.a, reg.raf.a, isprint(reg.raf.a)?reg.raf.a:'.');
+  con->dd_printf("%c%c%c%c%c%c%c%c\n",
+                 (reg.raf.f&FLAG_S)?'1':'0',
+                 (reg.raf.f&FLAG_Z)?'1':'0',
+		 (reg.raf.f&FLAG_I)?'1':'0',
+                 (reg.raf.f&FLAG_H)?'1':'0',
+                 (reg.raf.f&FLAG_X)?'1':'0',
+                 (reg.raf.f&FLAG_V)?'1':'0',
+                 (reg.raf.f&FLAG_N)?'1':'0',
+                 (reg.raf.f&FLAG_C)?'1':'0');
+  con->dd_printf("BC= 0x%04x [BC]= %02x %3d %c  ",
+                 reg.bc, nas->get(reg.bc), nas->get(reg.bc),
+                 isprint(nas->get(reg.bc))?nas->get(reg.bc):'.');
+  con->dd_printf("DE= 0x%04x [DE]= %02x %3d %c  ",
+                 reg.de, nas->get(reg.de), nas->get(reg.de),
+                 isprint(nas->get(reg.de))?nas->get(reg.de):'.');
+  con->dd_printf("HL= 0x%04x [HL]= %02x %3d %c\n",
+                 reg.hl, nas->get(reg.hl), nas->get(reg.hl),
+                 isprint(nas->get(reg.hl))?nas->get(reg.hl):'.');
+  con->dd_printf("IX= 0x%04x [IX]= %02x %3d %c  ",
+                 reg.ix, xas->get(reg.ix), xas->get(reg.ix),
+                 isprint(xas->get(reg.ix))?xas->get(reg.ix):'.');
+  con->dd_printf("IY= 0x%04x [IY]= %02x %3d %c  ",
+                 reg.iy, yas->get(reg.iy), yas->get(reg.iy),
+                 isprint(yas->get(reg.iy))?yas->get(reg.iy):'.');
+  con->dd_printf("SP= 0x%04x [SP]= %02x %3d %c\n",
+                 reg.sp, nas->get(reg.sp), nas->get(reg.sp),
+                 isprint(nas->get(reg.sp))?nas->get(reg.sp):'.');
+
+  print_disass(PC, con);
+}
+
+int
+cl_tlcs::exec_inst(void)
+{
+  t_mem c1, c2, c3, c4;//, c5, c6;
+  int res= resGO;
+
+  instPC= PC;
+
+  if (fetch(&c1))
+    return resBREAKPOINT;
+  tick(1);
+
+  switch (c1)
+    {
+    case 0x00: break; // NOP //res= resGO;
+    case 0x01: res= resHALT; break; // HALT
+    case 0x02: reg.raf.f&= ~FLAG_I; break; // DI
+    case 0x03: reg.raf.f|= FLAG_I; break; // EI
+    case 0x08: res= ex_de_hl(); break;
+    case 0x09: res= ex_af_alt_af(); break;
+    case 0x0a: res= exx(); break;
+    case 0x0b: res= inst_daa_a(); break;
+    case 0x0d: res= inst_scf(); break;
+    case 0x0c: res= inst_rcf(); break;
+    case 0x0e: res= inst_ccf(); break;
+    case 0x10: res= inst_cpl_a(); break;
+    case 0x11: res= inst_neg_a(); break;
+    case 0x17: // LDAR HL,$+2+cd
+      c2= fetch();
+      c3= fetch();
+      reg.hl= PC + i16_t(c3*256 + c2);
+      break;
+    case 0x1e: res= inst_ret(); break;
+    case 0x1f: res= inst_reti(); break;
+    case 0x37:  // LD (0ffw),n
+      c2= fetch();
+      c3= fetch();
+      cell_n(c2)->write(c3);
+      vc.wr++;
+      break;
+    case 0x3F: // LDW (0ffw),mn
+      c2= fetch();
+      c3= fetch();
+      c4= fetch();
+      write16(0xff00+c2, c4*256 + c3);
+      vc.wr+= 2;
+      break;
+    case 0x97: c2= fetch(); inst_inc16(t_addr(0xff00+c2)); break; // INCW (0ffn)
+    case 0x9F: c2= fetch(); inst_dec16(t_addr(0xff00+c2)); break; // DECW (0ffn)
+    case 0xa0: reg.raf.a= op_rlc(reg.raf.a, false); break; // RLCA
+    case 0xa1: reg.raf.a= op_rrc(reg.raf.a, false); break; // RRCA
+    case 0xa2: reg.raf.a= op_rl(reg.raf.a, false); break; // RLA
+    case 0xa3: reg.raf.a= op_rr(reg.raf.a, false); break; // RRA
+    case 0xa4: reg.raf.a= op_sla(reg.raf.a, false); break; // SLAA
+    case 0xa5: reg.raf.a= op_sra(reg.raf.a, false); break; // SRAA
+    case 0xa6: reg.raf.a= op_sla(reg.raf.a, false); break; // SLLA (=SLAA)
+    case 0xa7: reg.raf.a= op_srl(reg.raf.a, false); break; // SRLA
+    case 0xff: res= inst_swi(); break;
+    case 0xe3:
+      c2= fetch();
+      c3= fetch();
+      c4= fetch();
+      res= exec_inst4_e3(c1, c2, c3, c4);
+      break;
+    case 0xe7:
+      c2= fetch();
+      c3= fetch();
+      res= exec_inst3_e7(c1, c2, c3);
+      break;
+    case 0xeb:
+      c2= fetch();
+      c3= fetch();
+      c4= fetch();
+      res= exec_inst4_eb(c1, c2, c3, c4);
+      break;
+    case 0xef:
+      c2= fetch();
+      c3= fetch();
+      res= exec_inst4_ef(c1, c2, c3);
+      break;
+    case 0xf3: // c1
+      c2= fetch();
+      res= exec_inst2_f3(c2);
+      break;
+    case 0xf7: // c1
+      c2= fetch();
+      res= exec_inst2_f7(c2);
+      break;
+      //case 0xfe: // c1
+      //c2= fetch();
+      //res= exec_inst2_fe(c2);
+      //break;
+    default:
+      {
+	switch (c1 & 0xfc) // c1= XX+ix
+	  {
+	  case 0x14: // ADD ix,mn
+	    {
+	      u16_t *ra= aof_reg16_ix(c1);
+	      c2= fetch();
+	      c3= fetch();
+	      *ra= op_add16(*ra, c3*256 + c2);
+	      break;
+	    }
+	  case 0xf0: res= exec_inst3_f0ix(c1); break; // F0+ix d XX
+	  case 0xf4: // F4+ix d XX [n [m]]
+	    c2= fetch();
+	    c3= fetch();
+	    res= exec_inst4_f4ix(c1, c2, c3);
+	    break;
+	  default:
+	    switch (c1 & 0xf8) // c1= XX+r,rr,...
+	      {
+		// r, g, etc coded in single byte instruction
+	      case 0x20: reg.raf.a= *aof_reg8(c1); break; // LD A,r
+	      case 0x28: *aof_reg8(c1)= reg.raf.a; break; // LD r,A
+	      case 0x38: // LD rr,mn
+		c2= fetch();
+		c3= fetch();
+		*aof_reg16_rr(c1)= c2 + c3*256;
+		break;
+	      case 0x40: reg.hl= *aof_reg16_rr(c1); break; // LD HL,rr
+	      case 0x48: *aof_reg16_rr(c1)= reg.hl; break; // LD rr,HL
+	      case 0x50: exec_push(PC-1, *aof_reg16_qq(c1)); break; // PUSH qq
+	      case 0x58: res= inst_pop(c1); break; // POP qq
+	      case 0x80: *aof_reg8(c1)= op_inc(*aof_reg8(c1)); break; // INC r
+	      case 0x88: *aof_reg8(c1)= op_dec(*aof_reg8(c1)); break; // DEC r
+	      case 0x90: *aof_reg16_rr(c1)= op_inc16(*aof_reg16_rr(c1)); break; // INC rr
+	      case 0x98: *aof_reg16_rr(c1)= op_dec16(*aof_reg16_rr(c1)); break; // DEC rr
+	      default:
+		// no more left, check for two byte instructions
+		res= exec_inst2(c1);
+		break;
+	      }
+	    break;
+	  }
+	break;
+      }
+    }
+
+  return res;
+}
+
+/*
+ *                                                       Decode two byte instructions
+ ************************************************************************************
+ */
+
+int
+cl_tlcs::exec_inst2(u8_t c1)
+{
+  u8_t c2= fetch();
+  int res= resGO;
+  class cl_memory_cell *n= cell_n(c2);
+  
+  // first, handle cases where first byte is fix
+  switch (c1)
+    {
+    case 0x07: inst_incx(n); break; // INCX (0ffn)
+    case 0x0F: inst_decx(n); break; // DECX (0ffn)
+    case 0x12: reg.hl= reg.rhl.l * c2; break; // MUL HL,n
+    case 0x13: inst_div_hl(c2); break; // DIV HL,n
+    case 0x18: inst_djnz_b(i8_t(c2)); break; // DJNZ $+2+d
+    case 0x19: inst_djnz_bc(i8_t(c2)); break; // DJNZ BC,$+2+d
+    case 0x27: reg.raf.a= n->read(); break; // LD A,(0ffn)
+    case 0x2F: n->write(reg.raf.a); vc.wr++; break; // LD (0ffn),A
+    case 0x47: reg.hl= mem16(0xff00 + c2); vc.rd+= 2; break; // LD HL,(0ffn)
+    case 0x4f: write16(0xff00+c2, reg.hl); vc.wr+= 2; break; // LD (0xffn),HL
+    case 0x60: inst_add_a(n); break; // ADD A,(0ffn)
+    case 0x61: inst_adc_a(n); break; // ADC A,(0ffn)
+    case 0x62: inst_sub_a(n); break; // SUB A,(0ffn)
+    case 0x63: inst_sbc_a(n); break; // SBC A,(0ffn)
+    case 0x64: inst_and_a(n); break; // AND A,(0ffn)
+    case 0x65: inst_xor_a(n); break; // XOR A,(0ffn)
+    case 0x66: inst_or_a(n); break; // OR A,(0ffn)
+    case 0x67: op_cp_a(n); break; // CP A,(0ffn)
+    case 0x68: reg.raf.a= op_add_a(c2); break; // ADD A,n
+    case 0x69: inst_adc_a(c2); break; // ADC A,n
+    case 0x6A: inst_sub_a(c2); break; // SUB A,n
+    case 0x6B: inst_sbc_a(c2); break; // SBC A,n
+    case 0x6C: inst_and_a(c2); break; // AND A,n
+    case 0x6D: inst_xor_a(c2); break; // XOR A,n
+    case 0x6E: inst_or_a(c2); break; // OR A,n
+    case 0x6F: op_cp_a(c2); break; // CP A,n
+    case 0x70: reg.hl= op_add_hl(t_addr(0xff00+c2)); break; // ADD HL,(0ffn)
+    case 0x71: reg.hl= op_adc_hl(t_addr(0xff00+c2)); break; // ADC HL,(0ffn)
+    case 0x72: reg.hl= op_sub_hl(t_addr(0xff00+c2)); break; // SUB HL,(0ffn)
+    case 0x73: reg.hl= op_sbc_hl(t_addr(0xff00+c2)); break; // SBC HL,(0ffn)
+    case 0x74: reg.hl= op_and_hl(t_addr(0xff00+c2)); break; // AND HL,(0ffn)
+    case 0x75: reg.hl= op_xor_hl(t_addr(0xff00+c2)); break; // XOR HL,(0ffn)
+    case 0x76: reg.hl= op_or_hl(t_addr(0xff00+c2)); break; // OR HL,(0ffn)
+    case 0x77: op_sub_hl(t_addr(0xff00+c2)); break; // CP HL,(0ffn)
+    case 0x87: inst_inc(n); break; // INC (0ffn)
+    case 0x8F: inst_dec(n); break; // DEC (0ffn)
+    default:
+      // now handle cases where first byte is not fix
+      switch (c1 & 0xf8)
+	{
+	case 0x30: *aof_reg8(c1)= c2; break; // LD r,n
+	case 0xa8: inst_bit(n, c1); break; // BIT b,(0ffn)
+	case 0xb0: inst_res(n, c1); break; // RES b,(0ffn)
+	case 0xb8: inst_set(n, c1); break; // SET b,(0ffn)
+	case 0xe0: // e0+gg
+	  res= exec_inst2_e0gg(c1, c2);
+	  break;
+	case 0xe8: // e8+gg
+	  res= exec_inst2_e8gg(c1, c2);
+	  break;
+	case 0xf8: // f8+g, f8+gg
+	  res= exec_inst2_f8gg(c1, c2);
+	  break;
+	default: // pass others to 3 byte decoder
+	  if ((c1 & 0xf0) == 0xc0) // JR [cc,]$+2+d
+	    {
+	      i8_t d= c2;
+	      if (cc(c1))
+		PC+= d;
+	    }
+	  else
+	    res= exec_inst3(c1, c2);
+	  break;
+	}
+      break;
+    }
+  
+  return res;
+}
+
+
+/*                                                                              F3 XX
+ */
+
+int
+cl_tlcs::exec_inst2_f3(u8_t c2)
+{
+  int res= resGO;
+  
+  switch (c2)
+    {
+      // handle c1==f3 cases where second byte is fix
+    case 0x10: res= inst_rld(cell_hl_a()); break; // RLD (HL+A)
+    case 0x11: res= inst_rrd(cell_hl_a()); break; // RRD (HL+A)
+    case 0x12: res= inst_mul_hl(cell_hl_a()); break; // MUL HL,(HL+A)
+    case 0x13: res= inst_div_hl(cell_hl_a()); break; // DIV HL,(HL+A)
+    case 0x60: res= inst_add_a(cell_hl_a()); break; // ADD A,(HL+A)
+    case 0x61: res= inst_adc_a(cell_hl_a()); break; // ADC A,(HL+A)
+    case 0x62: res= inst_sub_a(cell_hl_a()); break; // SUB A,(HL+A)
+    case 0x63: res= inst_sbc_a(cell_hl_a()); break; // SBC A,(HL+A)
+    case 0x64: res= inst_and_a(cell_hl_a()); break; // AND A,(HL+A)
+    case 0x65: res= inst_xor_a(cell_hl_a()); break; // XOR A,(HL+A)
+    case 0x66: res= inst_or_a(cell_hl_a()); break; // OR A,(HL+A)
+    case 0x67: res= op_cp_a(cell_hl_a()); break; // CP A,(HL+A)
+    case 0x70: reg.hl= op_add_hl((t_addr)(reg.hl+reg.raf.a)); break; // ADD HL,(HL+A)
+    case 0x71: reg.hl= op_adc_hl((t_addr)(reg.hl+reg.raf.a)); break; // ADC HL,(HL+A)
+    case 0x72: reg.hl= op_sub_hl((t_addr)(reg.hl+reg.raf.a)); break; // SUB HL,(HL+A)
+    case 0x73: reg.hl= op_sbc_hl((t_addr)(reg.hl+reg.raf.a)); break; // SBC HL,(HL+A)
+    case 0x74: reg.hl= op_and_hl((t_addr)(reg.hl+reg.raf.a)); break; // AND HL,(HL+A)
+    case 0x75: reg.hl= op_xor_hl((t_addr)(reg.hl+reg.raf.a)); break; // XOR HL,(HL+A)
+    case 0x76: reg.hl= op_or_hl((t_addr)(reg.hl+reg.raf.a)); break; // OR HL,(HL+A)
+    case 0x77: reg.hl= op_sub_hl((t_addr)(reg.hl+reg.raf.a)); break; // CP HL,(HL+A)
+    case 0x87: inst_inc(cell_hl_a()); break; // INC (HL+A)
+    case 0x8f: inst_dec(cell_hl_a()); break; // DEC (HL+A)
+    case 0x97: inst_inc16((t_addr)(reg.hl+reg.raf.a)); break; // INCW (HL+A)
+    case 0x9f: inst_dec16((t_addr)(reg.hl+reg.raf.a)); break; // DECW (HL+A)
+    case 0xa0: inst_rlc(cell_hl_a()); break; // RLC (HL+A)
+    case 0xa1: inst_rrc(cell_hl_a()); break; // RRC (HL+A)
+    case 0xa2: inst_rl(cell_hl_a()); break; // RL (HL+A)
+    case 0xa3: inst_rr(cell_hl_a()); break; // RR (HL+A)
+    case 0xa4: inst_sla(cell_hl_a()); break; // SLA (HL+A)
+    case 0xa5: inst_sra(cell_hl_a()); break; // SRA (HL+A)
+    case 0xa6: inst_sla(cell_hl_a()); break; // SLL (HL+A)
+    case 0xa7: inst_srl(cell_hl_a()); break; // SRL (HL+A)
+    default:
+      // handle c1==f3 cases where second byte is not fix
+      if ((c2 & 0xfc) == 0x14) // ADD ix,(HL+A)
+	{
+	  u16_t *op1= aof_reg16_ix(c2);
+	  u16_t op2= mem16(reg.hl+reg.raf.a);
+	  vc.rd+= 2;
+	  *op1= op_add16(*op1, op2);
+	}
+      else
+	switch (c2 & 0xf8)
+	  {
+	  case 0x18: // TSET b,(HL+A)
+	    {
+	      cl_memory_cell *c= cell_hl_a();
+	      u8_t v= c->read();
+	      vc.rd++;
+	      c->write(op_tset(v, c2));
+	      vc.wr++;
+	      break;
+	    }
+	  case 0x28: *aof_reg8(c2)= cell_hl_a()->read(); vc.rd++; break; // LD r,(HL+A)
+	  case 0x48: *aof_reg16_rr(c2)= mem16(reg.hl+reg.raf.a); vc.rd+= 2; break; // LD rr,(HL+A)
+	  case 0x50: // EX (HL+A),rr
+	    {
+	      cl_memory_cell *c= cell_hl_a();
+	      u16_t t= c->read(), *r= aof_reg16_rr(c2);
+	      vc.rd++;
+	      c->write(*r);
+	      vc.wr++;
+	      *r= t;
+	      break;
+	    }
+	  case 0xa8: op_bit(cell_hl_a()->read(), c2); vc.rd++; break; // BIT b,(HL+A)
+	  case 0xb0: // RES b,(HL+A)
+	    {
+	      cl_memory_cell *c= cell_hl_a();
+	      u8_t v= op_res(c->read(), c2);
+	      vc.rd++;
+	      c->write(v);
+	      vc.wr++;
+	      break;
+	    }
+	  case 0xb8: // SET b,(HL+A)
+	    {
+	      cl_memory_cell *c= cell_hl_a();
+	      u8_t v= op_set(c->read(), c2);
+	      vc.rd++;
+	      c->write(v);
+	      vc.wr++;
+	      break;
+	    }
+	  default:
+	    res= resINV_INST;
+	    break;
+	  }
+      break;
+    }
+  return res;
+}
+
+/*                                                                              F7 XX
+ */
+
+int
+cl_tlcs::exec_inst2_f7(u8_t c2)
+{
+  int res= resGO;
+  u8_t n, m;
+  
+  switch (c2)
+    {
+    case 0x37: n= fetch(); cell_hl_a()->write(n); vc.wr++; break; // LD (HL+A),n
+    case 0x3f: n= fetch(); m= fetch(); write16(reg.hl+reg.raf.a, m*256+n); vc.wr+= 2; break; // LDW (HL+A),mn
+    case 0x68: n= fetch(); cell_hl_a()->write(op_add8(cell_hl_a()->read(), n)); vc.rd++; vc.wr++; break; // ADD (HL+A),n
+    case 0x69: n= fetch(); cell_hl_a()->write(op_adc8(cell_hl_a()->read(), n)); vc.rd++; vc.wr++; break; // ADC (HL+A),n
+    case 0x6a: n= fetch(); cell_hl_a()->write(op_sub8(cell_hl_a()->read(), n)); vc.rd++; vc.wr++; break; // SUB (HL+A),n
+    case 0x6b: n= fetch(); cell_hl_a()->write(op_sbc8(cell_hl_a()->read(), n)); vc.rd++; vc.wr++; break; // SBC (HL+A),n
+    case 0x6c: n= fetch(); cell_hl_a()->write(op_and8(cell_hl_a()->read(), n)); vc.rd++; vc.wr++; break; // AND (HL+A),n
+    case 0x6d: n= fetch(); cell_hl_a()->write(op_xor8(cell_hl_a()->read(), n)); vc.rd++; vc.wr++; break; // XOR (HL+A),n
+    case 0x6e: n= fetch(); cell_hl_a()->write(op_or8(cell_hl_a()->read(), n)); vc.rd++; vc.wr++; break; // OR (HL+A),n
+    case 0x6f: n= fetch(); op_cp8(cell_hl_a()->read(), n); vc.rd++; break; // CP (HL+A),n
+    default:
+      switch (c2 & 0xf0)
+	{
+	case 0xc0: if (cc(c2)) PC= reg.hl|reg.raf.a; break; // JP [cc,]HL+A
+	case 0xd0: if (cc(c2)) inst_call(PC-2, reg.hl+reg.raf.a); break; // CALL [cc,]HL+A
+	default:
+	  switch (c2 & 0xf8)
+	    {
+	    case 0x20: cell_hl_a()->write(*aof_reg8(c2)); vc.wr++; break; // LD (HL+A),r
+	    case 0x38: *aof_reg16_rr(c2)= reg.hl+reg.raf.a; break; // LDA rr,HL+A
+	    case 0x40: write16(reg.hl+reg.raf.a, *aof_reg16_rr(c2)); vc.wr+= 2; break; // LD (HL+A),rr
+	    default:
+	      res= resINV_INST;
+	      break;
+	    }
+	  break;
+	}
+    }
+  return res;
+}
+
+/*                                                                              FE XX
+ */
+
+int
+cl_tlcs::exec_inst2_fe(u8_t c2)
+{
+  int res= resGO;
+  
+  if ((c2 & 0xf0) == 0xd0) // RET cc
+    {
+      if (cc(c2)) inst_ret();
+    }
+  else
+    switch (c2)
+      {
+      case 0x58: ldi(); break;
+      case 0x59: ldir(); break;
+      case 0x5a: ldd(); break;
+      case 0x5b: lddr(); break;
+      case 0x5c: cpi(); break;
+      case 0x5d: cpir(); break;
+      case 0x5e: cpd(); break;
+      case 0x5f: cpdr(); break;
+      default:
+	res= resINV_INST;
+	break;
+      }
+  return res;
+}
+
+/*                                                                           E0+gg XX
+ */
+
+int
+cl_tlcs::exec_inst2_e0gg(u8_t c1, u8_t c2)
+{
+  int res= resGO;
+  cl_memory_cell *gg= cell_gg(c1);
+  
+  switch (c2)
+    {
+    case 0x10: inst_rld(gg); break; // RLD (gg)
+    case 0x11: inst_rrd(gg); break; // RRD (gg)
+    case 0x12: inst_mul_hl(gg); break; // MUL HL,(gg)
+    case 0x13: inst_div_hl(gg); break; // DIV HL,(gg)
+    case 0x60: inst_add_a(gg); break; // ADD A,(gg)
+    case 0x61: inst_adc_a(gg); break; // ADC A,(gg)
+    case 0x62: inst_sub_a(gg); break; // SUB,A(gg)
+    case 0x63: inst_sbc_a(gg); break; // SBC A,(gg)
+    case 0x64: inst_and_a(gg); break; // AND A(gg)
+    case 0x65: inst_xor_a(gg); break; // XOR A(gg)
+    case 0x66: inst_or_a(gg); break; // OR A,(gg)
+    case 0x67: op_cp_a(gg); break; // CP A,(gg)
+    case 0x70: reg.hl= op_add_hl((t_addr)*aof_reg16_gg(c1)); break; // ADD HL,(gg)
+    case 0x71: reg.hl= op_adc_hl((t_addr)*aof_reg16_gg(c1)); break; // ADC HL,(gg)
+    case 0x72: reg.hl= op_sub_hl((t_addr)*aof_reg16_gg(c1)); break; // SUB HL,(gg)
+    case 0x73: reg.hl= op_sbc_hl((t_addr)*aof_reg16_gg(c1)); break; // SBC HL,(gg)
+    case 0x74: reg.hl= op_and_hl((t_addr)*aof_reg16_gg(c1)); break; // AND HL,(gg)
+    case 0x75: reg.hl= op_xor_hl((t_addr)*aof_reg16_gg(c1)); break; // XOR HL,(gg)
+    case 0x76: reg.hl= op_or_hl((t_addr)*aof_reg16_gg(c1)); break; // OR HL,(gg)
+    case 0x77: reg.hl= op_sub_hl((t_addr)*aof_reg16_gg(c1)); break; // CP HL,(gg)
+    case 0x87: inst_inc(gg); break; // INC (gg)
+    case 0x8f: inst_dec(gg); break; // DEC (gg)
+    case 0x97: inst_inc16gg(c1, *aof_reg16_gg(c1)); break; // INCW (gg)
+    case 0x9f: inst_dec16gg(c1, *aof_reg16_gg(c1)); break; // DECW (gg)
+    case 0xa0: inst_rlc(gg); break; // RLC (gg)
+    case 0xa1: inst_rrc(gg); break; // RRC (gg)
+    case 0xa2: inst_rl(gg); break; // RL (gg)
+    case 0xa3: inst_rr(gg); break; // RR (gg)
+    case 0xa4: inst_sla(gg); break; // SLA (gg)
+    case 0xa5: inst_sra(gg); break; // SRA (gg)
+    case 0xa6: inst_sla(gg); break; // SLL (gg)
+    case 0xa7: inst_srl(gg); break; // SRL (gg)
+    default:
+      if ((c2 & 0xfc) == 0x14) // ADD ix,(gg)
+	{
+	  u16_t *ix= aof_reg16_ix(c2);
+	  *ix= op_add16(*ix, mem16gg(c1));
+	}
+      else
+	switch (c2 & 0xf8)
+	  {
+	  case 0x18: inst_tset(gg, c2); break; // TSET b,(gg)
+	  case 0x28: *aof_reg8(c2)= gg->read(); vc.rd++; break; // LD r,(gg)
+	  case 0x48: *aof_reg16_rr(c2)= mem16gg(c1); vc.rd+= 2; break; // LD rr,(gg)
+	  case 0x50: // EX (gg),rr
+	    {
+	      u16_t *ra= aof_reg16_rr(c2);
+	      u16_t r= *ra;
+	      *ra= mem16gg(c1);
+	      vc.rd+= 2;
+	      write16gg(c1, r);
+	      vc.wr+= 2;
+	      break;
+	    }
+	  case 0xa8: inst_bit(gg, c2); break; // BIT b,(gg)
+	  case 0xb0: inst_res(gg, c2); break; // RES b,(gg)
+	  case 0xb8: inst_set(gg, c2); break; // SET b,(gg)
+	  default:
+	    res= resINV_INST;
+	    break;
+	  }
+    }
+  
+  return res;
+}
+
+/*                                                                           E8+gg XX
+ */
+
+int
+cl_tlcs::exec_inst2_e8gg(u8_t c1, u8_t c2)
+{
+  int res= resGO;
+  class cl_memory_cell *gg= cell_gg(c1);
+  t_addr gv= *aof_reg16_gg(c1);
+  u8_t n, m;
+  
+  switch (c2)
+    {
+    case 0x37: n= fetch(); gg->write(n); vc.wr++; break; // LD (gg),n
+    case 0x3F: n= fetch(); m= fetch(); write16gg(c1, m*256+n); vc.wr+= 2; break; // LDW (gg),mn
+    case 0x68: n= fetch(); gg->write(op_add8(gg->read(), n)); vc.rd++; vc.wr++; break; // ADD (gg),n
+    case 0x69: n= fetch(); gg->write(op_adc8(gg->read(), n)); vc.rd++; vc.wr++; break; // ADC (gg),n
+    case 0x6a: n= fetch(); gg->write(op_sub8(gg->read(), n)); vc.rd++; vc.wr++; break; // SUB (gg),n
+    case 0x6b: n= fetch(); gg->write(op_sbc8(gg->read(), n)); vc.rd++; vc.wr++; break; // SBC (gg),n
+    case 0x6c: n= fetch(); gg->write(op_and8(gg->read(), n)); vc.rd++; vc.wr++; break; // AND (gg),n
+    case 0x6d: n= fetch(); gg->write(op_xor8(gg->read(), n)); vc.rd++; vc.wr++; break; // XOR (gg),n
+    case 0x6e: n= fetch(); gg->write(op_or8(gg->read(), n)); vc.rd++; vc.wr++; break; // OR (gg),n
+    case 0x6f: n= fetch(); op_cp8(gg->read(), n); vc.rd++; break; // CP (gg),n
+    default:
+      switch (c2 & 0xf0)
+	{
+	case 0xc0: if (cc(c2)) PC= gv; break; // JP [cc,]gg
+	case 0xd0: if (cc(c2)) inst_call(PC-2, gv); break; // CALL [cc,]gg
+	default:
+	  switch (c2 & 0xf8)
+	    {
+	    case 0x20: gg->write(*aof_reg8(c2)); vc.wr++; break; // LD (gg),r
+	    case 0x40: write16gg(c1, *aof_reg16_rr(c2)); vc.wr+= 2; break; // LD (gg),rr
+	    default:
+	      res= resINV_INST;
+	      break;
+	    }
+	  break;
+	}
+      break;
+    }
+  return res;
+}
+
+/*                                                                  F8+g XX, F8+gg XX
+ */
+
+int
+cl_tlcs::exec_inst2_f8gg(u8_t c1, u8_t c2)
+{
+  int res= resGO;
+  u8_t *ga= aof_reg8(c1), n;
+  u16_t *gga= aof_reg16_gg(c1);
+
+  if ((c1 == 0xfe) &&
+      (
+       ((c2>=0x58)&&(c2<=0x5f)) ||
+       ((c2&0xf0)==0xd0)
+       )
+      )
+    res= exec_inst2_fe(c2);
+  else
+    {
+      switch (c2)
+	{
+	case 0x12: reg.hl= reg.rhl.l * (*ga); break; // MUL HL,g
+	case 0x13: inst_div_hl(*ga); break; // DIV HL,g
+	case 0x60: reg.raf.a= op_add_a(*ga); break; // ADD A,g
+	case 0x61: inst_adc_a(*ga); break; // ADC A,g
+	case 0x62: inst_sub_a(*ga); break; // SUB A,g
+	case 0x63: inst_sbc_a(*ga); break; // SBC A,g
+	case 0x64: inst_and_a(*ga); break; // AND A,g
+	case 0x65: inst_xor_a(*ga); break; // XOR A,g
+	case 0x66: inst_or_a(*ga); break; // OR A,g
+	case 0x67: op_cp_a(*ga); break; // CP A,g
+	case 0x70: reg.hl= op_add_hl((t_mem)*gga); break; // ADD HL,gg
+	case 0x71: reg.hl= op_adc_hl((t_mem)*gga); break; // ADC HL,gg
+	case 0x72: reg.hl= op_sub_hl((t_mem)*gga); break; // SUB HL,gg
+	case 0x73: reg.hl= op_sbc_hl((t_mem)*gga); break; // SBC HL,gg
+	case 0x74: reg.hl= op_and_hl((t_mem)*gga); break; // AND HL,gg
+	case 0x75: reg.hl= op_xor_hl((t_mem)*gga); break; // XOR HL,gg
+	case 0x76: reg.hl= op_or_hl((t_mem)*gga); break; // OR HL,gg
+	case 0x77: op_sub_hl((t_mem)*gga); break; // CP HL,gg
+	case 0xA0: *ga= op_rlc(*ga, true); break; // RLC g
+	case 0xA1: *ga= op_rrc(*ga, true); break; // RRC g
+	case 0xA2: *ga= op_rl(*ga, true); break; // RL g
+	case 0xA3: *ga= op_rr(*ga, true); break; // RR g
+	case 0xA4: *ga= op_sla(*ga, true); break; // SLA g
+	case 0xA5: *ga= op_sra(*ga, true); break; // SRA g
+	case 0xA6: *ga= op_sla(*ga, true); break; // SLL g
+	case 0xA7: *ga= op_srl(*ga, true); break; // SRL g
+	  // some 3 byte cases
+	case 0x68: n= fetch(); *ga= op_add8(*ga, n); break; // ADD g,n
+	case 0x69: n= fetch(); *ga= op_adc8(*ga, n); break; // ADC g,n
+	case 0x6a: n= fetch(); *ga= op_sub8(*ga, n); break; // SUB g,n
+	case 0x6b: n= fetch(); *ga= op_sbc8(*ga, n); break; // SBC g,n
+	case 0x6c: n= fetch(); *ga= op_and8(*ga, n); break; // AND g,n
+	case 0x6d: n= fetch(); *ga= op_xor8(*ga, n); break; // XOR g,n
+	case 0x6e: n= fetch(); *ga= op_or8(*ga, n); break; // OR g,n
+	case 0x6f: n= fetch(); *ga= op_cp8(*ga, n); break; // CP g,n
+	  // non-fix 2nd byte cases
+	default:
+	  if ((c2 & 0xfc) == 0x14) // ADD ix,gg
+	    *aof_reg16_ix(c2)= op_add16(*aof_reg16_ix(c2), *gga);
+	  else
+	    switch (c2 & 0xf8)
+	      {
+	      case 0x18: *ga= op_tset(*ga, c2); break; // TSET b,g
+	      case 0x30: *aof_reg8(c2)= *ga; break; // LD r,g
+	      case 0x38: *aof_reg16_rr(c2)= *gga; break; // LD rr,gg
+	      case 0xa8: *ga= op_bit(*ga, c2); break; // BIT b,g
+	      case 0xb0: *ga= op_res(*ga, c2); break; // RES b,g
+	      case 0xb8: *ga= op_set(*ga, c2); break; // SET b,g
+	      default:
+		res= resINV_INST;
+		break;
+	      }
+	  break;
+	}
+    }
+  
+  return res;
+}
+
+/*
+ */
+
+int
+cl_tlcs::exec_inst3(u8_t c1, u8_t c2)
+{
+  int res= resGO;
+  u8_t c3= fetch();
+  
+  switch (c1)
+    {
+    case 0x1a: PC= c3*256 + c2; break; // JP mn
+    case 0x1b: PC+= i16_t(c3*256 + c2); break; // JRL $+2+cd
+    case 0x1c: inst_call(PC-3, c3*256 + c2); break; // CALL mn
+    case 0x1d: inst_call(PC-3, PC + i16_t(c3*256 + c2)); break; // CALR $+2+cd
+    case 0x78: reg.hl= op_add_hl((t_mem)(c3*256+c2)); break; // ADD HL,mn
+    case 0x79: reg.hl= op_adc_hl((t_mem)(c3*256+c2)); break; // ADC HL,mn
+    case 0x7a: reg.hl= op_sub_hl((t_mem)(c3*256+c2)); break; // SUB HL,mn
+    case 0x7b: reg.hl= op_sbc_hl((t_mem)(c3*256+c2)); break; // SBC HL,mn
+    case 0x7c: reg.hl= op_and_hl((t_mem)(c3*256+c2)); break; // AND HL,mn
+    case 0x7d: reg.hl= op_xor_hl((t_mem)(c3*256+c2)); break; // XOR HL,mn
+    case 0x7e: reg.hl= op_or_hl((t_mem)(c3*256+c2)); break; // OR HL,mn
+    case 0x7f: op_sub_hl((t_mem)(c3*256+c2)); break; // CP HL,mn
+    default:
+      switch (c1 & 0xf8)
+	{
+	case 0x38: *aof_reg16_rr(c1)= c3*256 + c2; break; // LD rr,mn
+	default:
+	  res= resINV_INST;
+	  break;
+	}
+      break;
+    }
+
+  return res;
+}
+
+/*                                                                              E7 n XX
+ */
+
+int
+cl_tlcs::exec_inst3_e7(u8_t c1, u8_t c2, u8_t c3)
+{
+  int res= resGO;
+  cl_memory_cell *n= cell_n(c2);
+  
+  switch (c3)
+    {
+    case 0x10: inst_rld(n); break; // RLD (0ffn)
+    case 0x11: inst_rrd(n); break; // RRD (0ffn)
+    case 0x12: inst_mul_hl(n); break; // MUL HL,(0ffn)
+    case 0x13: inst_div_hl(n); break; // DIV HL,(0ffn)
+    case 0xa0: inst_rlc(n); break; // RLC (0ffn)
+    case 0xa1: inst_rrc(n); break; // RRC (0ffn)
+    case 0xa2: inst_rl(n); break; // RL (0ffn)
+    case 0xa3: inst_rr(n); break; // RR (0ffn)
+    case 0xa4: inst_sla(n); break; // SLA (0ffn)
+    case 0xa5: inst_sra(n); break; // SRA (0ffn)
+    case 0xa6: inst_sla(n); break; // SLL (0ffn)
+    case 0xa7: inst_srl(n); break; // SRL (0ffn)
+    default:
+      if ((c3 & 0xfc) == 0x14) // ADD ix,(0ffn)
+	{
+	  u16_t *aix= aof_reg16_ix(c3);
+	  *aix= op_add16(*aix, mem16(0xff00 + c2));
+	  vc.rd+= 2;
+	}
+      else
+	switch (c3 & 0xf8)
+	  {
+	  case 0x18: inst_tset(n, c3); break; // TSET b,(0ffn)
+	  case 0x28: *aof_reg8(c3)= n->read(); vc.rd++; break; // LD r,(0ffn)
+	  case 0x48: *aof_reg16_rr(c3)= mem16(0xff00 + c2); vc.rd+= 2; break; // LD rr,(0ffn);
+	  case 0x50: // EX (0ffn),rr
+	    {
+	      u16_t temp= mem16(0xff00+c2);
+	      vc.rd+= 2;
+	      u16_t *ar= aof_reg16_rr(c3);
+	      write16(0xff00+c2, *ar);
+	      vc.wr+= 2;
+	      *ar= temp;
+	      break;
+	    }
+	  default:
+	    res= resINV_INST;
+	    break;
+	  }
+    }
+  
+  return res;
+}
+
+/*
+ */
+
+int
+cl_tlcs::exec_inst3_f0ix(u8_t c1)
+{
+  i8_t d= fetch();
+  u8_t c3= fetch();
+  int res= resGO;
+  cl_memory_cell *c= cell_ixd(c1, d);
+  u16_t a= *aof_reg16_ix(c1)+d;
+  
+  switch (c3)
+    {
+    case 0x10: inst_rld(c); break; // RLD (ix+d)
+    case 0x11: inst_rrd(c); break; // RRD (ix+d)
+    case 0x12: inst_mul_hl(c); break; // MUL HL,(ix+d)
+    case 0x13: inst_div_hl(c); break; // DIV HL,(ix+d)
+    case 0x60: inst_add_a(c); break; // ADD A,(ix+d)
+    case 0x61: inst_adc_a(c); break; // ADC A,(ix+d)
+    case 0x62: inst_sub_a(c); break; // SUB A,(ix+d)
+    case 0x63: inst_sbc_a(c); break; // SBC A,(ix+d)
+    case 0x64: inst_and_a(c); break; // AND A,(ix+d)
+    case 0x65: inst_xor_a(c); break; // XOR A,(ix+d)
+    case 0x66: inst_or_a(c); break; // OR A,(ix+d)
+    case 0x67: op_cp_a(c); break; // CP A,(ix+d)
+    case 0x70: reg.hl= op_add_hl((t_mem)mem16ixd(c1,d)); vc.rd+= 2; break; // ADD HL,(ix+d)
+    case 0x71: reg.hl= op_adc_hl((t_mem)mem16ixd(c1,d)); vc.rd+= 2; break; // ADC HL,(ix+d)
+    case 0x72: reg.hl= op_sub_hl((t_mem)mem16ixd(c1,d)); vc.rd+= 2; break; // SUB HL,(ix+d)
+    case 0x73: reg.hl= op_sbc_hl((t_mem)mem16ixd(c1,d)); vc.rd+= 2; break; // SBC HL,(ix+d)
+    case 0x74: reg.hl= op_and_hl((t_mem)mem16ixd(c1,d)); vc.rd+= 2; break; // AND HL,(ix+d)
+    case 0x75: reg.hl= op_xor_hl((t_mem)mem16ixd(c1,d)); vc.rd+= 2; break; // XOR HL,(ix+d)
+    case 0x76: reg.hl= op_or_hl((t_mem)mem16ixd(c1,d)); vc.rd+= 2; break; // OR HL,(ix+d)
+    case 0x77: op_sub_hl((t_mem)mem16ixd(c1,d)); vc.rd+= 2; break; // CP HL,(ix+d)
+    case 0x87: inst_inc(c); break; // INC (ix+d)
+    case 0x8F: inst_dec(c); break; // DEC (ix+d)
+    case 0x97: inst_inc16ix(c1, a); break; // INCW (ix+d)
+    case 0x9F: inst_dec16ix(c1, a); break; // DECW (ix+d)
+    case 0xA0: inst_rlc(c); break; // RLC (ix+d)
+    case 0xA1: inst_rrc(c); break; // RRC (ix+d)
+    case 0xA2: inst_rl(c); break; // RL (ix+d)
+    case 0xA3: inst_rr(c); break; // RR (ix+d)
+    case 0xA4: inst_sla(c); break; // SLA (ix+d)
+    case 0xA5: inst_sra(c); break; // SRA (ix+d)
+    case 0xA6: inst_sla(c); break; // SLL (ix+d)
+    case 0xA7: inst_srl(c); break; // SRL (ix+d)
+    default:
+      if ((c3 & 0xfc) == 0x14) // ADD ix,(jx+d)
+	{
+	  u16_t *rp= aof_reg16_ix(c3);
+	  u16_t op= mem16ixd(c1, d);
+	  vc.rd+= 2;
+	  *rp= op_add16(*rp, op);
+	}
+      else
+	switch (c3 & 0xf8)
+	  {
+	  case 0x18: inst_tset(c, c3); break; // TSET b,(ix+d)
+	  case 0x28: *aof_reg8(c3)= c->read(); vc.rd++; break; // LD r,(ix+d)
+	  case 0x48: *aof_reg16_rr(c3)= mem16ixd(c1, d); vc.rd+= 2; break; // LD rr,(ix+d)
+	  case 0x50: // EX (ix+d),rr
+	    {
+	      u16_t temp= mem16ixd(c1, d);
+	      vc.rd+= 2;
+	      u16_t *ra= aof_reg16_rr(c3);
+	      write16ixd(c1, d, *ra);
+	      vc.wr+= 2;
+	      *ra= temp;
+	      break;
+	    }
+	  case 0xa8: inst_bit(c, c3); break; // BIT b,(ix+d)
+	  case 0xb0: inst_res(c, c3); break; // RES b,(ix+d)
+	  case 0xb8: inst_set(c, c3); break; // SET b,(ix+d)
+	  default:
+	    res= resINV_INST;
+	    break;
+	  }
+    }
+  
+  return res;
+}
+
+/*                                                                              E3 n m XX
+ */
+
+int
+cl_tlcs::exec_inst4_e3(u8_t c1, u8_t c2, u8_t c3, u8_t c4)
+{
+  int res= resGO;
+  u16_t mn= c3 * 256 + c2;
+  class cl_memory_cell *c= nas->get_cell(mn);
+
+  switch (c4)
+    {
+    case 0x10: inst_rld(c); break; // RLD (mn)
+    case 0x11: inst_rrd(c); break; // RRD (mn)
+    case 0x12: inst_mul_hl(c); break; // MUL HL,(mn)
+    case 0x13: inst_div_hl(c); break; // DIV HL,(mn)
+    case 0x60: inst_add_a(c); break; // ADD A,(mn)
+    case 0x61: inst_sbc_a(c); break; // ADC A,(mn)
+    case 0x62: inst_sub_a(c); break; // SUB A,(mn)
+    case 0x63: inst_sbc_a(c); break; // SBC A,(mn)
+    case 0x64: inst_and_a(c); break; // AND A,(mn)
+    case 0x65: inst_xor_a(c); break; // XOR A,(mn)
+    case 0x66: inst_or_a(c); break; // OR A,(mn)
+    case 0x67: op_cp_a(c); break; // CP A,(mn)
+    case 0x70: reg.hl= op_add_hl((t_addr)mn); break; // ADD HL,(mn)
+    case 0x71: reg.hl= op_adc_hl((t_addr)mn); break; // ADC HL,(mn)
+    case 0x72: reg.hl= op_sub_hl((t_addr)mn); break; // SUB HL,(mn)
+    case 0x73: reg.hl= op_sbc_hl((t_addr)mn); break; // SBC HL,(mn)
+    case 0x74: reg.hl= op_and_hl((t_addr)mn); break; // AND HL,(mn)
+    case 0x75: reg.hl= op_xor_hl((t_addr)mn); break; // XOR HL,(mn)
+    case 0x76: reg.hl= op_or_hl((t_addr)mn); break; // OR HL,(mn)
+    case 0x77: op_sub_hl((t_addr)mn); break; // CP HL,(mn)
+    case 0x87: inst_inc(c); break; // INC (mn)
+    case 0x8f: inst_dec(c); break; // DEC (mn)
+    case 0x97: inst_inc16((t_addr)mn); break; // INCW (mn)
+    case 0x9f: inst_dec16((t_addr)mn); break; // DECW (mn)
+    case 0xa0: inst_rlc(c); break; // RLC (mn)
+    case 0xa1: inst_rrc(c); break; // RRC (mn)
+    case 0xa2: inst_rl(c); break; // RL (mn)
+    case 0xa3: inst_rr(c); break; // RR (mn)
+    case 0xa4: inst_sla(c); break; // SLA (mn)
+    case 0xa5: inst_sra(c); break; // SRA (mn)
+    case 0xa6: inst_sla(c); break; // SLL (mn)
+    case 0xa7: inst_srl(c); break; // SRL (mn)
+    default:
+      if ((c4 & 0xfc) == 0x14) // ADD ix,(mn)
+	*aof_reg16_ix(c4)= op_add16(*aof_reg16_ix(c4), mem16(mn));
+      else
+	switch (c4 & 0xf8)
+	  {
+	  case 0x18: inst_tset(c, c4); break;; // TSET b,(mn)
+	  case 0x28: *aof_reg8(c4)= c->read(); vc.rd++; break; // LD r,(mn)
+	  case 0x48: *aof_reg16_rr(c4)= mem16(mn); vc.rd+= 2; break; // LD rr,(mn)
+	  case 0x50: // EX (mn),rr
+	    {
+	      u16_t temp= mem16(mn);
+	      vc.rd+= 2;
+	      u16_t *ar= aof_reg16_rr(c4);
+	      write16(mn, *ar);
+	      vc.wr+= 2;
+	      *ar= temp;
+	    }
+	  case 0xa8: inst_bit(c, c4); break; // BIT b,(mn)
+	  case 0xb0: inst_res(c, c4); break; // RES b,(mn)
+	  case 0xb8: inst_set(c, c4); break; // SET b,(mn)
+	  default:
+	    res= resINV_INST;
+	    break;
+	  }
+    }
+  
+  return res;
+}
+
+/* EF n|w X n
+ */
+
+int
+cl_tlcs::exec_inst4_ef(u8_t c1, u8_t c2, u8_t c3)
+{
+  int res= resGO;
+  u8_t n;
+  cl_memory_cell *wc= cell_n(c2);
+  u8_t wd= wc->read();
+  
+  switch (c3)
+    {
+    case 0x68: n= fetch(); wc->write(op_add8(wd, n)); vc.wr++; break; // ADD (0ffw),n
+    case 0x69: n= fetch(); wc->write(op_adc8(wd, n)); vc.wr++; break; // ADC (0ffw),n
+    case 0x6a: n= fetch(); wc->write(op_sub8(wd, n)); vc.wr++; break; // SUB (0ffw),n
+    case 0x6b: n= fetch(); wc->write(op_sbc8(wd, n)); vc.wr++; break; // SBC (0ffw),n
+    case 0x6c: n= fetch(); wc->write(op_and8(wd, n)); vc.wr++; break; // AND (0ffw),n
+    case 0x6d: n= fetch(); wc->write(op_xor8(wd, n)); vc.wr++; break; // XOR (0ffw),n
+    case 0x6e: n= fetch(); wc->write(op_or8(wd, n)); vc.wr++; break; // OR (0ffw),n
+    case 0x6f: n= fetch(); op_cp8(wd, n); break; // CP (0ffw),n
+    default:
+      switch (c3 & 0xf8) // EF n XX+r
+	{
+	case 0x20: wc->write(*aof_reg8(c3)); vc.wr++; break; // LD (0ffn),r
+	case 0x40: write16(0xff00+c2, *aof_reg16_rr(c3)); vc.wr+= 2; break; // LD (0ffn),rr
+	default:
+	  res= resINV_INST;
+	  break;
+	}
+      break;
+    }
+  
+  return res;
+}
+
+/*                                                                EB n|w m|v XX [n [m]]
+ */
+
+int
+cl_tlcs::exec_inst4_eb(u8_t c1, u8_t c2, u8_t c3, u8_t c4)
+{
+  int res= resGO;
+  u16_t nm23= c3*256 + c2;
+  u16_t vw23= nm23;
+  u8_t n5;
+  class cl_memory_cell *c= nas->get_cell(vw23);
+  
+  switch (c4)
+    {
+    case 0x37: n5= fetch(); c->write(n5); vc.wr++; break; // LD (vw),n
+    case 0x3f: n5= fetch(); write16(vw23, n5 + fetch()*256); vc.wr+= 2; break; // LDW (vw),mn
+    case 0x68: n5= fetch(); c->write(op_add8(c->read(), n5)); vc.wr++; break; // ADD (vw),n
+    case 0x69: n5= fetch(); c->write(op_adc8(c->read(), n5)); vc.wr++; break; // ADC (vw),n
+    case 0x6a: n5= fetch(); c->write(op_sub8(c->read(), n5)); vc.wr++; break; // SUB (vw),n
+    case 0x6b: n5= fetch(); c->write(op_sbc8(c->read(), n5)); vc.wr++; break; // SBC (vw),n
+    case 0x6c: n5= fetch(); c->write(op_and8(c->read(), n5)); vc.wr++; break; // AND (vw),n
+    case 0x6d: n5= fetch(); c->write(op_xor8(c->read(), n5)); vc.wr++; break; // XOR (vw),n
+    case 0x6e: n5= fetch(); c->write(op_or8(c->read(), n5)); vc.wr++; break; // OR (vw),n
+    case 0x6f: n5= fetch(); op_cp8(c->read(), n5); vc.rd++; break; // CP (vw),n
+    default:
+      switch (c4 & 0xf8)
+	{
+	case 0x20: c->write(*aof_reg8(c4)); vc.wr++; break; // LD (mn),r
+	case 0x40: write16(vw23, *aof_reg16_rr(c4)); vc.wr+= 2; break; // LD (mn),rr
+	default:
+	  switch (c4 & 0xf0)
+	    {
+	    case 0xc0: if (cc(c4)) PC= vw23; break; // JP cc,mn
+	    case 0xd0: if (cc(c4)) inst_call(PC-4, vw23); break; // CALL cc,mn
+	    default:
+	      res= resINV_INST;
+	      break;
+	    }
+	  break;
+	}
+      break;
+    }
+  
+  return res;
+}
+
+/*                                                                    F4+ix d XX [n [m]]
+ */
+
+int
+cl_tlcs::exec_inst4_f4ix(u8_t c1, u8_t c2, u8_t c3)
+{
+  int res= resGO;
+  i8_t d= c2;
+  u8_t n;
+  cl_memory_cell *c= cell_ixd(c1, d);
+  
+  switch (c3)
+    {
+    case 0x37: n= fetch(); c->write(n); vc.wr++; break; // LD (ix+d),n
+    case 0x3f: n= fetch(); write16ixd(c1, d, n+fetch()*256); vc.wr+= 2; break; // LDW (ix+d),mn
+    case 0x68: n= fetch(); c->write(op_add8(c->read(), n)); vc.rd++; vc.wr++; break; // ADD (ix+d),n
+    case 0x69: n= fetch(); c->write(op_adc8(c->read(), n)); vc.rd++; vc.wr++; break; // ADC (ix+d),n
+    case 0x6a: n= fetch(); c->write(op_sub8(c->read(), n)); vc.rd++; vc.wr++; break; // SUB (ix+d),n
+    case 0x6b: n= fetch(); c->write(op_sbc8(c->read(), n)); vc.rd++; vc.wr++; break; // SBC (ix+d),n
+    case 0x6c: n= fetch(); c->write(op_and8(c->read(), n)); vc.rd++; vc.wr++; break; // AND (ix+d),n
+    case 0x6d: n= fetch(); c->write(op_xor8(c->read(), n)); vc.rd++; vc.wr++; break; // XOR (ix+d),n
+    case 0x6e: n= fetch(); c->write(op_or8(c->read(), n)); vc.rd++; vc.wr++; break; // OR (ix+d),n
+    case 0x6f: n= fetch(); op_cp8(c->read(), n); vc.rd++; break; // CP (ix+d),n
+    default:
+      switch (c3 & 0xf0)
+	{
+	case 0xc0: if (cc(c3)) PC= *aof_reg16_ix(c1)+d; break; // JP [cc,]ix+d
+	case 0xd0: if (cc(c3)) inst_call(PC-4, *aof_reg16_ix(c1)+d); break; // CALL [cc,]ix+d
+	default:
+	  switch (c3 & 0xf8)
+	    {
+	    case 0x20: c->write(*aof_reg8(c3)); vc.wr++; break; // LD (ix+d),r
+	    case 0x38: *aof_reg16_rr(c3)= *aof_reg16_ix(c1)+d; break; // LDA rr,ix+d
+	    case 0x40: write16ixd(c1, d, *aof_reg16_rr(c3)); vc.wr+= 2; break; // LD (ix+d),rr
+	    default:
+	      res= resINV_INST;
+	      break;
+	    }
+	  break;
+	}
+      break;
+    }
+  
+  return res;
+}
+
+
+t_addr
+cl_tlcs::do_push(t_mem data)
+{
+  t_addr sp_before= reg.sp;
+  reg.sp-= 1;
+  nas->write(reg.sp, (data>>8)&0xff);
+  reg.sp-= 1;
+  nas->write(reg.sp, (data&0xff));
+  vc.wr+= 2;
+  return sp_before;
+}
+
+t_addr
+cl_tlcs::do_pop(t_mem *data)
+{
+  t_addr sp_before= reg.sp;
+  t_mem val;
+  val= nas->read(reg.sp);
+  reg.sp+= 1;
+  val= (nas->read(reg.sp) * 256) + val;
+  reg.sp+= 1;
+  if (data)
+    *data= val;
+  vc.rd+= 2;
+  return sp_before;
+}
+
+int
+cl_tlcs::exec_push(t_addr PC_of_inst, t_mem data)
+{
+  t_addr sp_before= do_push(data);
+  class cl_stack_push *o= new cl_stack_push(PC_of_inst, data, sp_before, reg.sp);
+  o->init();
+  stack_write(o);
+  return resGO;
+}
+
+int
+cl_tlcs::exec_ret(t_addr PC_of_inst, t_mem *data)
+{
+  t_addr sp_before= do_pop(data);
+  t_mem val= 0;
+  if (data)
+    val= *data;
+  class cl_stack_ret *o= new cl_stack_ret(PC_of_inst, val, sp_before, reg.sp);
+  o->init();
+  stack_read(o);
+  return resGO;
+}
+
+int
+cl_tlcs::exec_reti(t_addr PC_of_inst, t_mem *data)
+{
+  t_addr sp_before= do_pop(data);
+  t_mem val= 0;
+  if (data)
+    val= *data;
+  class cl_stack_iret *o= new cl_stack_iret(PC_of_inst, val, sp_before, reg.sp);
+  o->init();
+  stack_read(o);
+  return resGO;
+}
+
+int
+cl_tlcs::exec_pop(t_addr PC_of_inst, t_mem *data)
+{
+  t_addr sp_before= do_pop(data);
+  t_mem val= 0;
+  if (data)
+    val= *data;
+  class cl_stack_pop *o= new cl_stack_pop(PC_of_inst, val, sp_before, reg.sp);
+  o->init();
+  stack_read(o);
+  return resGO;
+}
+
+int
+cl_tlcs::exec_intr(t_addr PC_of_inst, t_addr called, t_mem data)
+{
+  t_addr sp_before= do_push(data);
+  class cl_stack_intr *o= new cl_stack_intr(PC_of_inst, called, data, sp_before, reg.sp);
+  o->init();
+  stack_write(o);
+  return resGO;
+}
+
+int
+cl_tlcs::exec_call(t_addr PC_of_inst, t_addr called, t_mem data)
+{
+  t_addr sp_before= do_push(data);
+  class cl_stack_call *o= new cl_stack_call(PC_of_inst, called, data, sp_before, reg.sp);
+  o->init();
+  stack_write(o);
+  return resGO;
+}
+
+void
+cl_tlcs::set_p(u8_t data)
+{
+  // P=1 means EVEN
+  int b= 0, i;
+
+  for (i= 0; i < 8; i++)
+    {
+      if (data & 1)
+	b++;
+      data>>= 1;
+    }
+  if (b&1)
+    // ODD, P <- 0
+    reg.raf.f&= ~FLAG_V;
+  else
+    // EVEN, P <- 1
+    reg.raf.f|= FLAG_V;
+}
+
+u8_t *
+cl_tlcs::aof_reg8(u8_t data_r)
+{
+  switch (data_r & 0x07)
+    {
+    case 0: return &reg.rbc.b;
+    case 1: return &reg.rbc.c;
+    case 2: return &reg.rde.d;
+    case 3: return &reg.rde.e;
+    case 4: return &reg.rhl.h;
+    case 5: return &reg.rhl.l;
+    case 6: return &reg.raf.a;
+    default: return &reg.dummy;
+    }
+}
+
+u16_t *
+cl_tlcs::aof_reg16_rr(u8_t data_rr)
+{
+  switch (data_rr & 0x07)
+    {
+    case 0: return &reg.bc;
+    case 1: return &reg.de;
+    case 2: return &reg.hl;
+    case 4: return &reg.ix;
+    case 5: return &reg.iy;
+    case 6: return &reg.sp;
+    default: return &reg.dummy16;
+    }
+}
+
+u16_t *
+cl_tlcs::aof_reg16_qq(u8_t data_qq)
+{
+  switch (data_qq & 0x07)
+    {
+    case 0: return &reg.bc;
+    case 1: return &reg.de;
+    case 2: return &reg.hl;
+    case 4: return &reg.ix;
+    case 5: return &reg.iy;
+    case 6: return &reg.af;
+    default: return &reg.dummy16;
+    }
+}
+
+u16_t *
+cl_tlcs::aof_reg16_ix(u8_t data_ix)
+{
+  switch (data_ix & 0x03)
+    {
+    case 0: return &reg.ix;
+    case 1: return &reg.iy;
+    case 2: return &reg.sp;
+    default: return &reg.dummy16;
+    }
+}
+
+u16_t *
+cl_tlcs::aof_reg16_gg(u8_t data_gg)
+{
+  return aof_reg16_rr(data_gg);
+}
+
+class cl_memory_cell *
+cl_tlcs::cell_hl_a()
+{
+  return nas->get_cell(reg.hl + reg.raf.a);
+}
+
+class cl_memory_cell *
+cl_tlcs::cell_gg(u8_t gg)
+{
+  if ((gg & 0x7) == 4)
+    return xas->get_cell(*aof_reg16_gg(gg));
+  if ((gg & 0x7) == 5)
+    return yas->get_cell(*aof_reg16_gg(gg));
+  return nas->get_cell(*aof_reg16_gg(gg));
+}
+
+class cl_memory_cell *
+cl_tlcs::cell_n(u8_t n)
+{
+  return nas->get_cell(0xff00 + n);
+}
+
+class cl_memory_cell *
+cl_tlcs::cell_ixd(u8_t ix, i8_t d)
+{
+  switch (ix & 0x03)
+    {
+    case 0: return xas->get_cell(reg.ix + d); break;
+    case 1: return yas->get_cell(reg.iy + d); break;
+    case 2: return nas->get_cell(reg.sp + d); break;
+    }
+  return nas->dummy;
+}
+
+u16_t
+cl_tlcs::mem16(t_addr addr)
+{
+  u8_t l, h;
+  
+  l= nas->read(addr);
+  h= nas->read(addr+1);
+
+  return h*256 + l;
+}
+
+u16_t
+cl_tlcs::mem16gg(u8_t gg)
+{
+  u8_t l, h;
+  cl_address_space *as= nas;
+  u16_t addr= *aof_reg16_gg(gg);
+  
+  if ((gg & 7) == 4)
+    as= xas;
+  if ((gg & 7) == 5)
+    as= yas;
+  
+  l= as->read(addr);
+  h= as->read(addr+1);
+
+  return h*256 + l;
+}
+
+u16_t
+cl_tlcs::mem16ixd(u8_t ix, i8_t d)
+{
+  u8_t l, h;
+  cl_address_space *as= nas;
+  u16_t addr= *aof_reg16_ix(ix) + d;
+  
+  if ((ix&3) == 0)
+    as= xas;
+  if ((ix&3) == 1)
+    as= yas;
+  
+  l= as->read(addr);
+  h= as->read(addr+1);
+
+  return h*256 + l;
+}
+
+void
+cl_tlcs::write16(t_addr addr, u16_t val)
+{
+  nas->write(addr, val & 0xff);
+  nas->write(addr+1, val / 256);
+}
+
+
+void
+cl_tlcs::write16gg(u8_t gg, u16_t val)
+{
+  cl_address_space *as= nas;
+  u16_t addr= *aof_reg16_gg(gg);
+  
+  if ((gg&7) == 4)
+    as = xas;
+  if ((gg&7) == 5)
+    as= yas;
+  as->write(addr, val & 0xff);
+  as->write(addr+1, val / 256);
+}
+
+
+void
+cl_tlcs::write16ixd(u8_t ix, i8_t d, u16_t val)
+{
+  cl_address_space *as= nas;
+  u16_t addr= *aof_reg16_ix(ix) + d;
+  
+  if ((ix&3) == 0)
+    as = xas;
+  if ((ix&3) == 1)
+    as= yas;
+  as->write(addr, val & 0xff);
+  as->write(addr+1, val / 256);
+}
+
+
+bool
+cl_tlcs::flag(enum tlcs_flags f)
+{
+  return (reg.raf.f & f)?true:false;
+}
+
+bool
+cl_tlcs::cc(u8_t cc)
+{
+  bool s= flag(FLAG_S);
+  bool v= flag(FLAG_V);
+  switch (cc & 0x0f)
+    {
+    case 0: return false;
+    case 1: return (s && !v) || (!s && v);
+    case 2: return flag(FLAG_Z) || ((s && !v) || (!s && v));
+    case 3: return flag(FLAG_C) || flag(FLAG_Z);
+    case 4: return v;
+    case 5: return s;
+    case 6: return reg.raf.f & FLAG_Z;
+    case 7: return reg.raf.f & FLAG_C;
+    case 8: return true;
+    case 9: return !((s && !v) || (!s && v));
+    case 10: return !(flag(FLAG_Z) || ((s && !v) || (!s && v)));
+    case 11: return !(flag(FLAG_C) || flag(FLAG_Z));
+    case 12: return !v;
+    case 13: return !s;
+    case 14: return !(reg.raf.f & FLAG_Z);
+    case 15: return !(reg.raf.f & FLAG_C);
+    }
+  return false;
+}
+
+
+/* End of tlcs.src/tlcs.cc */
diff --git a/sim/ucsim/tlcs.src/tlcs.o b/sim/ucsim/tlcs.src/tlcs.o
new file mode 100644
index 0000000..47fcaf2
--- /dev/null
+++ b/sim/ucsim/tlcs.src/tlcs.o
diff --git a/sim/ucsim/tlcs.src/tlcscl.h b/sim/ucsim/tlcs.src/tlcscl.h
new file mode 100644
index 0000000..a6a6169
--- /dev/null
+++ b/sim/ucsim/tlcs.src/tlcscl.h
@@ -0,0 +1,365 @@
+/*
+ * Simulator of microcontrollers (tlcs.src/tlcscl.h)
+ *
+ * Copyright (C) 2016,16 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#ifndef TLCSCL_HEADER
+#define TLCSCL_HEADER
+
+// sim.src
+#include "uccl.h"
+#include "memcl.h"
+
+
+enum tlcs_flags {
+  FLAG_S= 0x80,
+  FLAG_Z= 0x40,
+  FLAG_I= 0x20,
+  FLAG_H= 0x10,
+  FLAG_X= 0x08,
+  FLAG_V= 0x04,
+  FLAG_N= 0x02,
+  FLAG_C= 0x01
+};
+
+/*
+ * Base type of TLCS microcontrollers
+ */
+
+class cl_tlcs: public cl_uc
+{
+ protected:
+  struct {
+    union {
+      u16_t af;
+      struct {
+#ifdef WORDS_BIGENDIAN
+	u8_t a;
+	u8_t f;
+#else
+	u8_t f;
+	u8_t a;
+#endif
+      } raf;
+    };
+    union {
+      u16_t bc;
+      struct {
+#ifdef WORDS_BIGENDIAN
+	u8_t b;
+	u8_t c;
+#else
+	u8_t c;
+	u8_t b;
+#endif
+      } rbc;
+    };
+    union {
+      u16_t de;
+      struct {
+#ifdef WORDS_BIGENDIAN
+	u8_t d;
+	u8_t e;
+#else
+	u8_t e;
+	u8_t d;
+#endif
+       } rde;
+    };
+    union {
+      u16_t hl;
+      struct {
+#ifdef WORDS_BIGENDIAN
+	u8_t h;
+	u8_t l;
+#else
+	u8_t l;
+	u8_t h;
+#endif
+      } rhl;
+    };
+    u16_t ix;
+    u16_t iy;
+    u16_t sp;
+    u8_t dummy;
+    u16_t dummy16;
+    union {
+      u16_t alt_af;
+      struct {
+#ifdef WORDS_BIGENDIAN
+	u8_t alt_a;
+	u8_t alt_f;
+#else
+	u8_t alt_f;
+	u8_t alt_a;
+#endif
+      } ralt_af;
+    };
+    union {
+      u16_t alt_bc;
+      struct {
+#ifdef WORDS_BIGENDIAN
+	u8_t alt_b;
+	u8_t alt_c;
+#else
+	u8_t alt_c;
+	u8_t alt_b;
+#endif
+      } ralt_bc;
+    };
+    union {
+      u16_t alt_de;
+      struct {
+#ifdef WORDS_BIGENDIAN
+	u8_t alt_d;
+	u8_t alt_e;
+#else
+	u8_t alt_e;
+	u8_t alt_d;
+#endif
+      } ralt_de;
+    };
+    union {
+      u16_t alt_hl;
+      struct {
+#ifdef WORDS_BIGENDIAN
+	u8_t alt_h;
+	u8_t alt_l;
+#else
+	u8_t alt_l;
+	u8_t alt_h;
+#endif
+      } ralt_hl;
+    };
+  } reg;
+
+ public:
+  class cl_address_space *nas;
+  class cl_address_space *xas;
+  class cl_address_space *yas;
+  class cl_address_space *regs8;
+  class cl_address_space *regs16;
+ public:
+  cl_tlcs(class cl_sim *asim);
+  virtual int init(void);
+  virtual char *id_string(void);
+
+  //virtual t_addr get_mem_size(enum mem_class type);
+  //virtual int get_mem_width(enum mem_class type);
+  virtual void mk_hw_elements(void);
+  virtual void make_memories(void);
+
+  virtual struct dis_entry *dis_tbl(void);
+  //virtual struct name_entry *sfr_tbl(void);
+  //virtual struct name_entry *bit_tbl(void);
+  virtual const char *regname_r(u8_t r);
+  virtual const char *regname_Q(u8_t Q);
+  virtual const char *regname_R(u8_t R);
+  virtual const char *regname_i(u8_t i);
+  virtual const char *bitname(u8_t b);
+  virtual const char *condname_cc(u8_t cc);
+  virtual const char *condname_C(u8_t cc);
+  virtual char *disass(t_addr addr, const char *sep);
+  virtual void print_regs(class cl_console_base *con);
+  virtual int inst_length(t_addr addr);
+
+  virtual int exec_inst(void);
+  virtual int exec_inst2(u8_t c1);
+  virtual int exec_inst2_f3(u8_t c1);
+  virtual int exec_inst2_fe(u8_t c1);
+  virtual int exec_inst2_f7(u8_t c1);
+  virtual int exec_inst2_e0gg(u8_t c1, u8_t c2);
+  virtual int exec_inst2_e8gg(u8_t c1, u8_t c2);
+  virtual int exec_inst2_f8gg(u8_t c1, u8_t c2);
+  virtual int exec_inst3_e7(u8_t c1, u8_t c2, u8_t c3);
+  virtual int exec_inst3(u8_t c1, u8_t c2);
+  virtual int exec_inst3_f0ix(u8_t c1);
+  virtual int exec_inst4_f4ix(u8_t c1, u8_t c2, u8_t c3);
+  virtual int exec_inst4_e3(u8_t c1, u8_t c2, u8_t c3, u8_t c4);
+  virtual int exec_inst4_ef(u8_t c1, u8_t c2, u8_t c3);
+  virtual int exec_inst4_eb(u8_t c1, u8_t c2, u8_t c3, u8_t c4);
+  
+  virtual t_addr do_push(t_mem data);
+  virtual t_addr do_pop(t_mem *data);
+  virtual int exec_push(t_addr PC_of_inst, t_mem data);
+  virtual int exec_ret(t_addr PC_of_inst, t_mem *data);
+  virtual int exec_reti(t_addr PC_of_inst, t_mem *data);
+  virtual int exec_pop(t_addr PC_of_inst, t_mem *data);
+  virtual int exec_intr(t_addr PC_of_inst, t_addr called, t_mem data);
+  virtual int exec_call(t_addr PC_of_inst, t_addr called, t_mem data);
+  virtual void set_p(u8_t data);
+  virtual u8_t *aof_reg8(u8_t data_r);
+  virtual u16_t *aof_reg16_rr(u8_t data_rr);
+  virtual u16_t *aof_reg16_qq(u8_t data_qq);
+  virtual u16_t *aof_reg16_ix(u8_t data_ix);
+  virtual u16_t *aof_reg16_gg(u8_t data_gg);
+  virtual class cl_memory_cell *cell_hl_a();
+  virtual class cl_memory_cell *cell_gg(u8_t gg);
+  virtual class cl_memory_cell *cell_n(u8_t n);
+  virtual class cl_memory_cell *cell_ixd(u8_t ix, i8_t d);
+  
+  virtual u16_t mem16(t_addr addr);
+  virtual u16_t mem16gg(u8_t gg);
+  virtual u16_t mem16ixd(u8_t ix, i8_t d);
+  virtual void write16(t_addr addr, u16_t val);
+  virtual void write16gg(u8_t gg, u16_t val);
+  virtual void write16ixd(u8_t ix, i8_t d, u16_t val);
+  virtual bool flag(enum tlcs_flags f);
+  virtual bool cc(u8_t cc);
+  
+  // (1) 8-bit data transfer
+
+  // (2) 16-bit data transfer
+  virtual int inst_pop(t_mem c1);	// 58+qq
+  
+  // (3) exchange, block transfer and search
+  virtual int ex_de_hl();		// 08
+  virtual int ex_af_alt_af();		// 09
+  virtual int exx();			// 0a
+  virtual int ldi();			// Fe 58
+  virtual int ldir();			// Fe 59
+  virtual int ldd();			// Fe 5a
+  virtual int lddr();			// Fe 5b
+  virtual int cpi();			// Fe 5c
+  virtual int cpir();		       	// Fe 5d
+  virtual int cpd();			// Fe 5e
+  virtual int cpdr();			// Fe 5f
+  
+  // (4) 8-bit arithmetic and logic operation
+  virtual u8_t op_inc(u8_t data);			// INC 8 bit
+  virtual void inst_inc(cl_memory_cell *cell);		// INC mem
+  virtual void inst_incx(cl_memory_cell *cell);		// INCX mem
+  virtual u8_t op_dec(u8_t data);			// DEC 8 bit
+  virtual void inst_dec(cl_memory_cell *cell);		// DEC mem
+  virtual void inst_decx(cl_memory_cell *cell);		// DECX mem
+  virtual u8_t op_add8(u8_t d1, u8_t d2);	// ADD 8-bit
+  virtual u8_t op_add_a(u8_t d);			// ADD A,8-bit
+  virtual int inst_add_a(class cl_memory_cell *cell);	// ADD A,mem
+  virtual u8_t op_adc8(u8_t d1, u8_t d2);	// ADC 8-bit
+  virtual int inst_adc_a(u8_t d);			// ADC A,8-bit
+  virtual int inst_adc_a(class cl_memory_cell *cell);	// ADC A,mem
+  virtual u8_t op_sub8(u8_t d1, u8_t d2);	// SUB 8-bit
+  virtual int inst_sub_a(u8_t d);			// SUB A,8-bit
+  virtual int inst_sub_a(class cl_memory_cell *cell);	// SUB A,mem
+  virtual u8_t op_sbc8(u8_t d1, u8_t d2);	// SBC 8-bit
+  virtual int inst_sbc_a(u8_t d);			// SBC A,8-bit
+  virtual int inst_sbc_a(class cl_memory_cell *cell);	// SBC A,mem
+  virtual u8_t op_and8(u8_t d1, u8_t d2);	// AND 8-bit
+  virtual int inst_and_a(u8_t d);			// AND A,8-bit
+  virtual int inst_and_a(class cl_memory_cell *cell);	// AND A,mem
+  virtual u8_t op_xor8(u8_t d1, u8_t d2);	// XOR 8-bit
+  virtual int inst_xor_a(u8_t d);			// XOR A,8-bit
+  virtual int inst_xor_a(class cl_memory_cell *cell);	// XOR A,mem
+  virtual u8_t op_or8(u8_t d1, u8_t d2);	// OR 8-bit
+  virtual int inst_or_a(u8_t d);			// OR A,8-bit
+  virtual int inst_or_a(class cl_memory_cell *cell);	// OR A,mem
+  virtual u8_t op_cp8(u8_t d1, u8_t d2);	// CP 8-bit
+  virtual int op_cp_a(u8_t d);			// CP A,8-bit
+  virtual int op_cp_a(class cl_memory_cell *cell);	// CP A,mem
+
+  // (5) 16-bit arithmetic and logic operation
+  virtual u16_t op_inc16(u16_t data);		// INC 16 bit
+  virtual u16_t inst_inc16(t_addr addr);		// INCW mem
+  virtual u16_t inst_inc16gg(u8_t gg,t_addr addr);// INCW mem
+  virtual u16_t inst_inc16ix(u8_t ix,t_addr addr);// INCW mem
+  virtual u16_t op_dec16(t_mem data);		// DEC 16 bit
+  virtual u16_t inst_dec16(t_addr addr);		// DECW mem
+  virtual u16_t inst_dec16gg(u8_t gg,t_addr addr);// DECW mem
+  virtual u16_t inst_dec16ix(u8_t ix,t_addr addr);// DECW mem
+  virtual u16_t op_add_hl(t_mem val);		// ADD HL,16-bit
+  virtual u16_t op_add_hl(t_addr addr);		// ADD HL,mem
+  virtual u16_t op_adc_hl(t_mem val);		// ADC HL,16-bit
+  virtual u16_t op_adc_hl(t_addr addr);		// ADC HL,mem
+  virtual u16_t op_sub_hl(t_mem val);		// SUB HL,16-bit
+  virtual u16_t op_sub_hl(t_addr addr);		// SUB HL,mem
+  virtual u16_t op_sbc_hl(t_mem val);		// SBC HL,16-bit
+  virtual u16_t op_sbc_hl(t_addr addr);		// SBC HL,mem
+  virtual u16_t op_and_hl(t_mem val);		// AND HL,16-bit
+  virtual u16_t op_and_hl(t_addr addr);		// AND HL,mem
+  virtual u16_t op_xor_hl(t_mem val);		// XOR HL,16-bit
+  virtual u16_t op_xor_hl(t_addr addr);		// XOR HL,mem
+  virtual u16_t op_or_hl(t_mem val);			// OR HL,16-bit
+  virtual u16_t op_or_hl(t_addr addr);		// OR HL,mem
+  virtual u16_t op_add16(t_mem op1, t_mem op2);	// ADD 16-bit
+  virtual u16_t op_sub16(t_mem op1, t_mem op2);	// SUB 16-bit
+
+  // (6) cpu control and others
+  virtual int inst_daa_a();		// 0b
+  virtual int inst_cpl_a();		// 10
+  virtual int inst_neg_a();		// 11
+  virtual int inst_ccf();		// 0e
+  virtual int inst_scf();		// 0d
+  virtual int inst_rcf();		// 0c
+  //virtual int nop();			// 00
+  //virtual int halt();			// 01
+  //virtual int di();			// 02
+  //virtual int ei();			// 03
+  virtual int inst_swi();		// ff
+  virtual int inst_mul_hl(class cl_memory_cell *cell);
+  virtual int inst_div_hl(class cl_memory_cell *cell);
+  virtual int inst_div_hl(u8_t d);
+  
+  // (7) rotate and shift
+  virtual u8_t op_rlc(u8_t data, bool set_sz);	// RLC 8-bit
+  virtual u8_t inst_rlc(cl_memory_cell *cell);	// RLC mem
+  virtual u8_t op_rrc(u8_t data, bool set_sz);	// RRC 8-bit
+  virtual u8_t inst_rrc(cl_memory_cell *cell);	// RRC mem
+  virtual u8_t op_rl(u8_t data, bool set_sz);	// RL 8-bit
+  virtual u8_t inst_rl(cl_memory_cell *cell);	// RL mem
+  virtual u8_t op_rr(u8_t data, bool set_sz);	// RR 8-bit
+  virtual u8_t inst_rr(cl_memory_cell *cell);	// RR mem
+  virtual u8_t op_sla(u8_t data, bool set_sz);	// SLA 8-bit
+  virtual u8_t inst_sla(cl_memory_cell *cell);	// SLA mem
+  virtual u8_t op_sra(u8_t data, bool set_sz);	// SRA 8-bit
+  virtual u8_t inst_sra(cl_memory_cell *cell);	// SRA mem
+  virtual u8_t op_srl(u8_t data, bool set_sz);	// SRL 8-bit
+  virtual u8_t inst_srl(cl_memory_cell *cell);	// SRL mem
+  virtual int inst_rld(class cl_memory_cell *cell);	// RLD
+  virtual int inst_rrd(class cl_memory_cell *cell);	// RLD
+
+  // (8) bit manipulation
+  virtual u8_t op_tset(u8_t val, u8_t bitnr);	// TSET 8-bit
+  virtual u8_t inst_tset(cl_memory_cell *cell, u8_t bitnr);
+  virtual u8_t op_bit(u8_t val, u8_t bitnr);	// BIT 8-bit
+  virtual u8_t inst_bit(cl_memory_cell *cell, u8_t bitnr);
+  virtual u8_t op_res(u8_t val, u8_t bitnr);	// RES 8-bit
+  virtual u8_t inst_res(cl_memory_cell *cell, u8_t bitnr);
+  virtual u8_t op_set(u8_t val, u8_t bitnr);	// SET 8-bit
+  virtual u8_t inst_set(cl_memory_cell *cell, u8_t bitnr);
+
+  // (9) jump, call and return
+  virtual int inst_ret();			// 1e
+  virtual int inst_reti();			// 1f
+  virtual int inst_call(t_addr PC_of_inst, u16_t addr);	// CALL addr
+  virtual int inst_djnz_b(i8_t d);
+  virtual int inst_djnz_bc(i8_t d);
+  
+  // ?
+};
+
+
+#endif
+
+/* End of tlcs.src/tlcscl.h */