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| author | Xavier ASUS <xavi92psx@gmail.com> | 2019-10-18 00:31:54 +0200 |
|---|---|---|
| committer | Xavier ASUS <xavi92psx@gmail.com> | 2019-10-18 00:31:54 +0200 |
| commit | 268a53de823a6750d6256ee1fb1e7707b4b45740 (patch) | |
| tree | 42c1799a9a82b2f7d9790ee9fe181d72a7274751 /sim/ucsim/st7.src/st7mac.h | |
| download | sdcc-gas-268a53de823a6750d6256ee1fb1e7707b4b45740.tar.gz | |
sdcc-3.9.0 fork implementing GNU assembler syntax
This fork aims to provide better support for stm8-binutils
Diffstat (limited to 'sim/ucsim/st7.src/st7mac.h')
| -rw-r--r-- | sim/ucsim/st7.src/st7mac.h | 42 |
1 files changed, 42 insertions, 0 deletions
diff --git a/sim/ucsim/st7.src/st7mac.h b/sim/ucsim/st7.src/st7mac.h new file mode 100644 index 0000000..1431a16 --- /dev/null +++ b/sim/ucsim/st7.src/st7mac.h @@ -0,0 +1,42 @@ +/*
+ * Simulator of microcontrollers (st7mac.h)
+ *
+ * some z80 code base from Karl Bongers karl@turbobit.com
+ *
+ * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
+ *
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+// shift positions
+#define BITPOS_C 0 // 1
+#define BITPOS_Z 1 // 2H
+#define BITPOS_N 2 // 4H
+#define BITPOS_I 3 // 8H
+#define BITPOS_H 4 // 10H
+
+#define store2(addr, val) { ram->write((t_addr) (addr), (val >> 8) & 0xff); ram->write((t_addr) (addr+1), val & 0xff); vc.wr+= 2; }
+#define store1(addr, val) { ram->write((t_addr) (addr), val); vc.wr++; }
+#define get1(addr) get_1(addr)
+//ram->get((t_addr) (addr))
+#define get2(addr) get_2(addr)
+//((ram->get((t_addr) (addr)) << 8) | ram->get((t_addr) (addr+1)) )
+#define get3(addr) get_3(addr)
+//((ram->get((t_addr) (addr)) << 16) | (ram->get((t_addr) (addr+1)) << 8) |ram->get((t_addr) (addr+2)) )
+#define fetch2() ((fetch() << 8) | fetch() )
+#define fetch1() fetch()
+#define push2(val) {store2(regs.SP-1,(val)); regs.SP-=2; }
+#define push1(val) {store1(regs.SP,(val)); regs.SP-=1; }
+#define pop2(var) {var=get2(regs.SP+1); regs.SP+=2;}
+#define pop1(var) {var=get1(regs.SP+1); regs.SP+=1;}
+
+
+#define FLAG_SET(f) {regs.CC |= f;}
+#define FLAG_CLEAR(f) {regs.CC &= ~(f);}
+#define FLAG_ASSIGN(f,c) {regs.CC = (c) ? regs.CC | (f) : regs.CC & ~(f);}
+#define EA_IMM(c) ((((c) >> 4) & 0xf)==0xa)
+#define OPERAND(code,prefix) (EA_IMM(code) ? fetch() : get1(fetchea(code,prefix)))
+
+
+
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