sdcc-3.9.0 fork implementing GNU assembler syntax

This fork aims to provide better support for stm8-binutils

127 files changed, 16926 insertions, 0 deletions

diff --git a/sim/ucsim/s51.src/(c).1 b/sim/ucsim/s51.src/(c).1
new file mode 100644
index 0000000..d673f9f
--- /dev/null
+++ b/sim/ucsim/s51.src/(c).1
@@ -0,0 +1,25 @@
+/*
+ * Simulator of microcontrollers (@@F@@)
+ *
+ * Copyright (C) @@S@@,@@Y@@ Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
diff --git a/sim/ucsim/s51.src/Makefile b/sim/ucsim/s51.src/Makefile
new file mode 100644
index 0000000..056f378
--- /dev/null
+++ b/sim/ucsim/s51.src/Makefile
@@ -0,0 +1,170 @@
+#
+# uCsim s51.src/Makefile
+#
+# (c) Drotos Daniel, Talker Bt. 1997
+#
+
+STARTYEAR	= 1997
+
+SHELL		= /bin/sh
+CXX		= g++
+CPP		= gcc -E
+CXXCPP		= g++ -E
+RANLIB		= ranlib
+INSTALL		= /usr/bin/install -c
+STRIP		= strip
+MAKEDEP         = g++ -MM
+
+top_builddir	= ..
+top_srcdir	= ..
+
+transform	= s,x,x,
+
+DEFS            = $(subs -DHAVE_CONFIG_H,,-DHAVE_CONFIG_H)
+CPPFLAGS        =  -I$(srcdir) -I$(top_srcdir) -I$(top_builddir) \
+		  -I$(top_srcdir)/cmd.src -I$(top_srcdir)/sim.src \
+		  -I$(top_srcdir)/gui.src
+CFLAGS          = -g -O2 -Wall
+CXXFLAGS        = -g -O2 -g -Wall
+LDFLAGS         = 
+PICOPT		=  -fPIC -DPIC
+SHAREDLIB	= yes
+
+SDCC		= sdcc
+SDCFLAGS	= --debug --stack-after-data --model-small
+SDCPPFLAGS	= 
+
+LIBS		= -L$(top_builddir) -lsim -lucsimutil -lguiucsim -lcmd -lsim -lrt -lnsl 
+DL		= -ldl
+dl_ok		= yes
+
+prefix          = /usr/local
+exec_prefix     = ${prefix}
+bindir          = ${exec_prefix}/bin
+libdir          = ${exec_prefix}/lib
+datadir         = ${datarootdir}
+datarootdir     = ${prefix}/share
+includedir      = ${prefix}/include
+mandir          = ${datarootdir}/man
+man1dir         = $(mandir)/man1
+man2dir         = $(mandir)/man2
+infodir         = ${datarootdir}/info
+srcdir          = .
+
+
+EXEEXT		= 
+
+OBJECTS_SHARED	= glob.o sim51.o \
+		  inc.o jmp.o mov.o logic.o arith.o bit.o \
+		  timer0.o timer1.o timer2.o serial.o port.o interrupt.o \
+		  wdt.o pca.o mdu.o \
+		  uc51.o uc52.o uc51r.o uc89c51r.o uc251.o uc517.o \
+		  uc390.o uc390hw.o uc521.o uc88x.o uc320.o uc380.o
+OBJECTS_EXE	= s51.o 
+OBJECTS		= $(OBJECTS_SHARED) $(OBJECTS_EXE)
+
+enable_dlso	= no
+dlso_ok		= no
+
+
+# Compiling entire program or any subproject
+# ------------------------------------------
+all: checkconf otherlibs s51.src
+
+
+# Compiling and installing everything and runing test
+# ---------------------------------------------------
+install: all installdirs
+	$(INSTALL) s51$(EXEEXT) $(DESTDIR)$(bindir)/`echo s51|sed '$(transform)'`$(EXEEXT)
+	$(STRIP) $(DESTDIR)$(bindir)/`echo s51|sed '$(transform)'`$(EXEEXT)
+
+
+# Deleting all the installed files
+# --------------------------------
+uninstall:
+	rm -f $(DESTDIR)$(bindir)/`echo s51|sed '$(transform)'`$(EXEEXT)
+
+
+# Performing self-test
+# --------------------
+check: test
+
+test: test_ser.ihx
+
+test_ser.ihx: test_ser.rel
+	$(SDCC) $(SDCFLAGS) $<
+
+# Performing installation test
+# ----------------------------
+installcheck:
+
+
+# Creating installation directories
+# ---------------------------------
+installdirs:
+	test -d $(DESTDIR)$(bindir) || $(INSTALL) -d $(DESTDIR)$(bindir)
+
+
+# Creating dependencies
+# ---------------------
+dep: Makefile.dep
+
+Makefile.dep: $(srcdir)/*.cc $(srcdir)/*.h
+	$(MAKEDEP) $(CPPFLAGS) $(filter %.cc,$^) >Makefile.dep
+
+-include Makefile.dep
+include $(srcdir)/clean.mk
+
+#parser.cc: parser.y
+
+#plex.cc: plex.l
+
+# My rules
+# --------
+.SUFFIXES: .rel
+
+s51.src: s51$(EXEEXT) shared_lib
+
+s51$(EXEEXT): $(OBJECTS) $(top_builddir)/libcmd.a $(top_builddir)/libguiucsim.a $(top_builddir)/libsim.a $(top_builddir)/libucsimutil.a
+	$(CXX) $(CXXFLAGS) $(LDFLAGS) $(OBJECTS) $(LIBS) -o $@
+
+ifeq ($(dlso_ok),yes)
+shared_lib: $(top_builddir)/s51.so
+else
+shared_lib:
+	@$(top_srcdir)/mkecho $(top_builddir) "No 51 shared lib made."
+	@$(top_srcdir)/mkecho $(top_builddir) "(SHAREDLIB="$(SHAREDLIB)",dl_ok="$(dl_ok)",enable_dlso="$(enable_dlso)")"
+endif
+
+$(top_builddir)/s51.so: $(OBJECTS_SHARED)
+	$(CXX) -shared $(LDFLAGS) $(OBJECTS_SHARED) -o $@
+
+otherlibs: $(top_builddir)/libcmd.a $(top_builddir)/libguiucsim.a $(top_builddir)/libsim.a $(top_builddir)/libucsimutil.a
+
+$(top_builddir)/libcmd.a:
+	$(MAKE) -C $(top_builddir)/cmd.src all
+
+$(top_builddir)/libguiucsim.a:
+	$(MAKE) -C $(top_builddir)/gui.src checkconf ucsim_lib
+
+$(top_builddir)/libsim.a:
+	$(MAKE) -C $(top_builddir)/sim.src all
+
+$(top_builddir)/libucsimutil.a:
+	$(MAKE) -C $(top_builddir) -f main.mk
+
+.cc.o:
+	$(CXX) $(CXXFLAGS) $(PICOPT) $(CPPFLAGS) -c $< -o $@
+
+.c.rel:
+	$(SDCC) $(SDCFLAGS) $(SDCPPFLAGS) -c $<
+
+
+# Remaking configuration
+# ----------------------
+checkconf:
+	@if [ -f $(top_builddir)/devel ]; then\
+	  $(MAKE) -C $(top_builddir) -f conf.mk srcdir="$(srcdir)" top_builddir="$(top_builddir)" freshconf;\
+	fi
+
+# End of s51.src/Makefile.in
diff --git a/sim/ucsim/s51.src/Makefile.dep b/sim/ucsim/s51.src/Makefile.dep
new file mode 100644
index 0000000..3b45418
--- /dev/null
+++ b/sim/ucsim/s51.src/Makefile.dep
@@ -0,0 +1,328 @@
+arith.o: arith.cc ../ddconfig.h uc51cl.h ../pobjcl.h ../ddconfig.h \
+ ../pobjt.h ../eventcl.h ../charscl.h ../sim.src/simcl.h \
+ ../cmd.src/newcmdcl.h ../optioncl.h ../pobjcl.h ../stypes.h \
+ ../cmd.src/commandcl.h ../cmd.src/newcmdcl.h ../gui.src/guicl.h \
+ ../gui.src/ifcl.h ../sim.src/guiobjcl.h ../sim.src/uccl.h ../stypes.h \
+ ../pobjt.h ../sim.src/hwcl.h ../sim.src/guiobjcl.h \
+ ../cmd.src/newcmdposixcl.h ../fiocl.h ../cmd.src/cmdutil.h \
+ ../sim.src/memcl.h ../eventcl.h ../errorcl.h ../sim.src/brkcl.h \
+ ../sim.src/stackcl.h ../sim.src/varcl.h ../sim.src/uccl_instructions.h \
+ ../sim.src/argcl.h ../sim.src/memcl.h ../sim.src/uccl.h \
+ ../sim.src/itsrccl.h ../sim.src/brkcl.h interruptcl.h regs51.h types51.h
+bit.o: bit.cc ../ddconfig.h uc51cl.h ../pobjcl.h ../ddconfig.h ../pobjt.h \
+ ../eventcl.h ../charscl.h ../sim.src/simcl.h ../cmd.src/newcmdcl.h \
+ ../optioncl.h ../pobjcl.h ../stypes.h ../cmd.src/commandcl.h \
+ ../cmd.src/newcmdcl.h ../gui.src/guicl.h ../gui.src/ifcl.h \
+ ../sim.src/guiobjcl.h ../sim.src/uccl.h ../stypes.h ../pobjt.h \
+ ../sim.src/hwcl.h ../sim.src/guiobjcl.h ../cmd.src/newcmdposixcl.h \
+ ../fiocl.h ../cmd.src/cmdutil.h ../sim.src/memcl.h ../eventcl.h \
+ ../errorcl.h ../sim.src/brkcl.h ../sim.src/stackcl.h ../sim.src/varcl.h \
+ ../sim.src/uccl_instructions.h ../sim.src/argcl.h ../sim.src/memcl.h \
+ ../sim.src/uccl.h ../sim.src/itsrccl.h ../sim.src/brkcl.h interruptcl.h \
+ regs51.h types51.h
+sim51.o: sim51.cc ../ddconfig.h ../i_string.h ../ddconfig.h ../globals.h \
+ ../stypes.h ../appcl.h ../pobjcl.h ../pobjt.h ../eventcl.h ../charscl.h \
+ ../optioncl.h ../sim.src/argcl.h ../pobjcl.h ../stypes.h \
+ ../sim.src/simcl.h ../cmd.src/newcmdcl.h ../optioncl.h \
+ ../cmd.src/commandcl.h ../cmd.src/newcmdcl.h ../gui.src/guicl.h \
+ ../gui.src/ifcl.h ../sim.src/guiobjcl.h ../sim.src/uccl.h ../pobjt.h \
+ ../sim.src/hwcl.h ../sim.src/guiobjcl.h ../cmd.src/newcmdposixcl.h \
+ ../fiocl.h ../cmd.src/cmdutil.h ../sim.src/memcl.h ../eventcl.h \
+ ../errorcl.h ../sim.src/brkcl.h ../sim.src/stackcl.h ../sim.src/varcl.h \
+ ../sim.src/uccl_instructions.h ../sim.src/argcl.h ../utils.h ../fiocl.h \
+ ../cmd.src/cmdutil.h ../charscl.h sim51cl.h uc51cl.h ../sim.src/memcl.h \
+ ../sim.src/uccl.h ../sim.src/itsrccl.h ../sim.src/brkcl.h interruptcl.h \
+ uc52cl.h uc521cl.h uc517cl.h uc51rcl.h uc89c51rcl.h uc251cl.h uc390cl.h \
+ uc88xcl.h uc320cl.h uc380cl.h glob.h
+uc89c51r.o: uc89c51r.cc ../ddconfig.h uc89c51rcl.h uc51rcl.h uc52cl.h \
+ uc51cl.h ../pobjcl.h ../ddconfig.h ../pobjt.h ../eventcl.h ../charscl.h \
+ ../sim.src/simcl.h ../cmd.src/newcmdcl.h ../optioncl.h ../pobjcl.h \
+ ../stypes.h ../cmd.src/commandcl.h ../cmd.src/newcmdcl.h \
+ ../gui.src/guicl.h ../gui.src/ifcl.h ../sim.src/guiobjcl.h \
+ ../sim.src/uccl.h ../stypes.h ../pobjt.h ../sim.src/hwcl.h \
+ ../sim.src/guiobjcl.h ../cmd.src/newcmdposixcl.h ../fiocl.h \
+ ../cmd.src/cmdutil.h ../sim.src/memcl.h ../eventcl.h ../errorcl.h \
+ ../sim.src/brkcl.h ../sim.src/stackcl.h ../sim.src/varcl.h \
+ ../sim.src/uccl_instructions.h ../sim.src/argcl.h ../sim.src/memcl.h \
+ ../sim.src/uccl.h ../sim.src/itsrccl.h ../sim.src/brkcl.h interruptcl.h \
+ regs51.h pcacl.h wdtcl.h
+timer2.o: timer2.cc timer2cl.h ../stypes.h ../ddconfig.h ../pobjcl.h \
+ ../pobjt.h ../eventcl.h ../charscl.h ../sim.src/uccl.h ../pobjt.h \
+ ../sim.src/hwcl.h ../sim.src/guiobjcl.h ../ddconfig.h \
+ ../cmd.src/newcmdcl.h ../optioncl.h ../pobjcl.h ../stypes.h \
+ ../cmd.src/commandcl.h ../cmd.src/newcmdcl.h ../cmd.src/newcmdposixcl.h \
+ ../fiocl.h ../cmd.src/cmdutil.h ../sim.src/memcl.h ../eventcl.h \
+ ../errorcl.h ../sim.src/uccl.h ../sim.src/brkcl.h ../sim.src/stackcl.h \
+ ../sim.src/varcl.h ../sim.src/uccl_instructions.h timer0cl.h uc51cl.h \
+ ../sim.src/simcl.h ../gui.src/guicl.h ../gui.src/ifcl.h \
+ ../sim.src/guiobjcl.h ../sim.src/argcl.h ../sim.src/memcl.h \
+ ../sim.src/itsrccl.h ../sim.src/brkcl.h interruptcl.h regs51.h types51.h
+uc390.o: uc390.cc ../ddconfig.h ../i_string.h ../ddconfig.h glob.h \
+ uc390cl.h uc52cl.h uc51cl.h ../pobjcl.h ../pobjt.h ../eventcl.h \
+ ../charscl.h ../sim.src/simcl.h ../cmd.src/newcmdcl.h ../optioncl.h \
+ ../pobjcl.h ../stypes.h ../cmd.src/commandcl.h ../cmd.src/newcmdcl.h \
+ ../gui.src/guicl.h ../gui.src/ifcl.h ../sim.src/guiobjcl.h \
+ ../sim.src/uccl.h ../stypes.h ../pobjt.h ../sim.src/hwcl.h \
+ ../sim.src/guiobjcl.h ../cmd.src/newcmdposixcl.h ../fiocl.h \
+ ../cmd.src/cmdutil.h ../sim.src/memcl.h ../eventcl.h ../errorcl.h \
+ ../sim.src/brkcl.h ../sim.src/stackcl.h ../sim.src/varcl.h \
+ ../sim.src/uccl_instructions.h ../sim.src/argcl.h ../sim.src/memcl.h \
+ ../sim.src/uccl.h ../sim.src/itsrccl.h ../sim.src/brkcl.h interruptcl.h \
+ regs51.h uc390hwcl.h timer2cl.h timer0cl.h
+uc380.o: uc380.cc portcl.h ../stypes.h ../ddconfig.h ../pobjcl.h \
+ ../pobjt.h ../eventcl.h ../charscl.h ../sim.src/uccl.h ../pobjt.h \
+ ../sim.src/hwcl.h ../sim.src/guiobjcl.h ../ddconfig.h \
+ ../cmd.src/newcmdcl.h ../optioncl.h ../pobjcl.h ../stypes.h \
+ ../cmd.src/commandcl.h ../cmd.src/newcmdcl.h ../cmd.src/newcmdposixcl.h \
+ ../fiocl.h ../cmd.src/cmdutil.h ../sim.src/memcl.h ../eventcl.h \
+ ../errorcl.h ../sim.src/uccl.h ../sim.src/brkcl.h ../sim.src/stackcl.h \
+ ../sim.src/varcl.h ../sim.src/uccl_instructions.h ../sim.src/port_hwcl.h \
+ uc380cl.h uc52cl.h uc51cl.h ../sim.src/simcl.h ../gui.src/guicl.h \
+ ../gui.src/ifcl.h ../sim.src/guiobjcl.h ../sim.src/argcl.h \
+ ../sim.src/memcl.h ../sim.src/itsrccl.h ../sim.src/brkcl.h interruptcl.h
+uc51.o: uc51.cc ../ddconfig.h ../i_string.h ../ddconfig.h ../utils.h \
+ ../stypes.h ../charscl.h ../fiocl.h ../pobjcl.h ../pobjt.h ../eventcl.h \
+ ../globals.h ../appcl.h ../optioncl.h ../sim.src/argcl.h ../pobjcl.h \
+ ../stypes.h ../sim.src/simcl.h ../cmd.src/newcmdcl.h ../optioncl.h \
+ ../cmd.src/commandcl.h ../cmd.src/newcmdcl.h ../gui.src/guicl.h \
+ ../gui.src/ifcl.h ../sim.src/guiobjcl.h ../sim.src/uccl.h ../pobjt.h \
+ ../sim.src/hwcl.h ../sim.src/guiobjcl.h ../cmd.src/newcmdposixcl.h \
+ ../fiocl.h ../cmd.src/cmdutil.h ../sim.src/memcl.h ../eventcl.h \
+ ../errorcl.h ../sim.src/brkcl.h ../sim.src/stackcl.h ../sim.src/varcl.h \
+ ../sim.src/uccl_instructions.h ../sim.src/argcl.h ../sim.src/iwrap.h \
+ ../cmd.src/cmd_uccl.h uc51cl.h ../sim.src/memcl.h ../sim.src/uccl.h \
+ ../sim.src/itsrccl.h ../sim.src/brkcl.h interruptcl.h glob.h regs51.h \
+ timer0cl.h timer1cl.h serialcl.h ../sim.src/serial_hwcl.h portcl.h \
+ ../sim.src/port_hwcl.h types51.h
+interrupt.o: interrupt.cc ../utils.h ../stypes.h ../ddconfig.h \
+ ../charscl.h ../fiocl.h ../pobjcl.h ../pobjt.h ../eventcl.h \
+ ../sim.src/itsrccl.h ../pobjcl.h ../stypes.h ../sim.src/uccl.h \
+ ../pobjt.h ../sim.src/hwcl.h ../sim.src/guiobjcl.h ../ddconfig.h \
+ ../cmd.src/newcmdcl.h ../optioncl.h ../cmd.src/commandcl.h \
+ ../cmd.src/newcmdcl.h ../cmd.src/newcmdposixcl.h ../fiocl.h \
+ ../cmd.src/cmdutil.h ../sim.src/memcl.h ../eventcl.h ../errorcl.h \
+ ../sim.src/brkcl.h ../sim.src/stackcl.h ../sim.src/varcl.h \
+ ../sim.src/uccl_instructions.h interruptcl.h ../sim.src/uccl.h regs51.h \
+ types51.h
+inc.o: inc.cc ../ddconfig.h uc51cl.h ../pobjcl.h ../ddconfig.h ../pobjt.h \
+ ../eventcl.h ../charscl.h ../sim.src/simcl.h ../cmd.src/newcmdcl.h \
+ ../optioncl.h ../pobjcl.h ../stypes.h ../cmd.src/commandcl.h \
+ ../cmd.src/newcmdcl.h ../gui.src/guicl.h ../gui.src/ifcl.h \
+ ../sim.src/guiobjcl.h ../sim.src/uccl.h ../stypes.h ../pobjt.h \
+ ../sim.src/hwcl.h ../sim.src/guiobjcl.h ../cmd.src/newcmdposixcl.h \
+ ../fiocl.h ../cmd.src/cmdutil.h ../sim.src/memcl.h ../eventcl.h \
+ ../errorcl.h ../sim.src/brkcl.h ../sim.src/stackcl.h ../sim.src/varcl.h \
+ ../sim.src/uccl_instructions.h ../sim.src/argcl.h ../sim.src/memcl.h \
+ ../sim.src/uccl.h ../sim.src/itsrccl.h ../sim.src/brkcl.h interruptcl.h \
+ regs51.h
+uc390hw.o: uc390hw.cc ../ddconfig.h uc390hwcl.h ../sim.src/uccl.h \
+ ../stypes.h ../ddconfig.h ../pobjcl.h ../pobjt.h ../eventcl.h \
+ ../charscl.h ../pobjt.h ../sim.src/hwcl.h ../sim.src/guiobjcl.h \
+ ../cmd.src/newcmdcl.h ../optioncl.h ../pobjcl.h ../stypes.h \
+ ../cmd.src/commandcl.h ../cmd.src/newcmdcl.h ../cmd.src/newcmdposixcl.h \
+ ../fiocl.h ../cmd.src/cmdutil.h ../sim.src/memcl.h ../eventcl.h \
+ ../errorcl.h ../sim.src/uccl.h ../sim.src/brkcl.h ../sim.src/stackcl.h \
+ ../sim.src/varcl.h ../sim.src/uccl_instructions.h uc390cl.h uc52cl.h \
+ uc51cl.h ../sim.src/simcl.h ../gui.src/guicl.h ../gui.src/ifcl.h \
+ ../sim.src/guiobjcl.h ../sim.src/argcl.h ../sim.src/memcl.h \
+ ../sim.src/itsrccl.h ../sim.src/brkcl.h interruptcl.h regs51.h
+jmp.o: jmp.cc ../ddconfig.h uc51cl.h ../pobjcl.h ../ddconfig.h ../pobjt.h \
+ ../eventcl.h ../charscl.h ../sim.src/simcl.h ../cmd.src/newcmdcl.h \
+ ../optioncl.h ../pobjcl.h ../stypes.h ../cmd.src/commandcl.h \
+ ../cmd.src/newcmdcl.h ../gui.src/guicl.h ../gui.src/ifcl.h \
+ ../sim.src/guiobjcl.h ../sim.src/uccl.h ../stypes.h ../pobjt.h \
+ ../sim.src/hwcl.h ../sim.src/guiobjcl.h ../cmd.src/newcmdposixcl.h \
+ ../fiocl.h ../cmd.src/cmdutil.h ../sim.src/memcl.h ../eventcl.h \
+ ../errorcl.h ../sim.src/brkcl.h ../sim.src/stackcl.h ../sim.src/varcl.h \
+ ../sim.src/uccl_instructions.h ../sim.src/argcl.h ../sim.src/memcl.h \
+ ../sim.src/uccl.h ../sim.src/itsrccl.h ../sim.src/brkcl.h interruptcl.h \
+ regs51.h types51.h
+mov.o: mov.cc ../ddconfig.h ../sim.src/memcl.h ../stypes.h ../ddconfig.h \
+ ../pobjcl.h ../pobjt.h ../eventcl.h ../charscl.h ../sim.src/guiobjcl.h \
+ ../eventcl.h ../errorcl.h ../pobjcl.h ../stypes.h uc51cl.h \
+ ../sim.src/simcl.h ../cmd.src/newcmdcl.h ../optioncl.h \
+ ../cmd.src/commandcl.h ../cmd.src/newcmdcl.h ../gui.src/guicl.h \
+ ../gui.src/ifcl.h ../sim.src/guiobjcl.h ../sim.src/uccl.h ../pobjt.h \
+ ../sim.src/hwcl.h ../cmd.src/newcmdposixcl.h ../fiocl.h \
+ ../cmd.src/cmdutil.h ../sim.src/memcl.h ../sim.src/brkcl.h \
+ ../sim.src/stackcl.h ../sim.src/varcl.h ../sim.src/uccl_instructions.h \
+ ../sim.src/argcl.h ../sim.src/uccl.h ../sim.src/itsrccl.h \
+ ../sim.src/brkcl.h interruptcl.h regs51.h
+uc251.o: uc251.cc ../ddconfig.h uc251cl.h uc89c51rcl.h uc51rcl.h uc52cl.h \
+ uc51cl.h ../pobjcl.h ../ddconfig.h ../pobjt.h ../eventcl.h ../charscl.h \
+ ../sim.src/simcl.h ../cmd.src/newcmdcl.h ../optioncl.h ../pobjcl.h \
+ ../stypes.h ../cmd.src/commandcl.h ../cmd.src/newcmdcl.h \
+ ../gui.src/guicl.h ../gui.src/ifcl.h ../sim.src/guiobjcl.h \
+ ../sim.src/uccl.h ../stypes.h ../pobjt.h ../sim.src/hwcl.h \
+ ../sim.src/guiobjcl.h ../cmd.src/newcmdposixcl.h ../fiocl.h \
+ ../cmd.src/cmdutil.h ../sim.src/memcl.h ../eventcl.h ../errorcl.h \
+ ../sim.src/brkcl.h ../sim.src/stackcl.h ../sim.src/varcl.h \
+ ../sim.src/uccl_instructions.h ../sim.src/argcl.h ../sim.src/memcl.h \
+ ../sim.src/uccl.h ../sim.src/itsrccl.h ../sim.src/brkcl.h interruptcl.h
+uc52.o: uc52.cc ../ddconfig.h uc52cl.h uc51cl.h ../pobjcl.h ../ddconfig.h \
+ ../pobjt.h ../eventcl.h ../charscl.h ../sim.src/simcl.h \
+ ../cmd.src/newcmdcl.h ../optioncl.h ../pobjcl.h ../stypes.h \
+ ../cmd.src/commandcl.h ../cmd.src/newcmdcl.h ../gui.src/guicl.h \
+ ../gui.src/ifcl.h ../sim.src/guiobjcl.h ../sim.src/uccl.h ../stypes.h \
+ ../pobjt.h ../sim.src/hwcl.h ../sim.src/guiobjcl.h \
+ ../cmd.src/newcmdposixcl.h ../fiocl.h ../cmd.src/cmdutil.h \
+ ../sim.src/memcl.h ../eventcl.h ../errorcl.h ../sim.src/brkcl.h \
+ ../sim.src/stackcl.h ../sim.src/varcl.h ../sim.src/uccl_instructions.h \
+ ../sim.src/argcl.h ../sim.src/memcl.h ../sim.src/uccl.h \
+ ../sim.src/itsrccl.h ../sim.src/brkcl.h interruptcl.h regs51.h \
+ timer2cl.h timer0cl.h portcl.h ../sim.src/port_hwcl.h mducl.h \
+ ../sim.src/hwcl.h
+mdu.o: mdu.cc uc51cl.h ../pobjcl.h ../ddconfig.h ../pobjt.h ../eventcl.h \
+ ../charscl.h ../sim.src/simcl.h ../cmd.src/newcmdcl.h ../ddconfig.h \
+ ../optioncl.h ../pobjcl.h ../stypes.h ../cmd.src/commandcl.h \
+ ../cmd.src/newcmdcl.h ../gui.src/guicl.h ../gui.src/ifcl.h \
+ ../sim.src/guiobjcl.h ../sim.src/uccl.h ../stypes.h ../pobjt.h \
+ ../sim.src/hwcl.h ../sim.src/guiobjcl.h ../cmd.src/newcmdposixcl.h \
+ ../fiocl.h ../cmd.src/cmdutil.h ../sim.src/memcl.h ../eventcl.h \
+ ../errorcl.h ../sim.src/brkcl.h ../sim.src/stackcl.h ../sim.src/varcl.h \
+ ../sim.src/uccl_instructions.h ../sim.src/argcl.h ../sim.src/memcl.h \
+ ../sim.src/uccl.h ../sim.src/itsrccl.h ../sim.src/brkcl.h interruptcl.h \
+ mducl.h ../sim.src/hwcl.h
+logic.o: logic.cc ../ddconfig.h ../stypes.h ../ddconfig.h uc51cl.h \
+ ../pobjcl.h ../pobjt.h ../eventcl.h ../charscl.h ../sim.src/simcl.h \
+ ../cmd.src/newcmdcl.h ../optioncl.h ../pobjcl.h ../stypes.h \
+ ../cmd.src/commandcl.h ../cmd.src/newcmdcl.h ../gui.src/guicl.h \
+ ../gui.src/ifcl.h ../sim.src/guiobjcl.h ../sim.src/uccl.h ../pobjt.h \
+ ../sim.src/hwcl.h ../sim.src/guiobjcl.h ../cmd.src/newcmdposixcl.h \
+ ../fiocl.h ../cmd.src/cmdutil.h ../sim.src/memcl.h ../eventcl.h \
+ ../errorcl.h ../sim.src/brkcl.h ../sim.src/stackcl.h ../sim.src/varcl.h \
+ ../sim.src/uccl_instructions.h ../sim.src/argcl.h ../sim.src/memcl.h \
+ ../sim.src/uccl.h ../sim.src/itsrccl.h ../sim.src/brkcl.h interruptcl.h \
+ regs51.h
+serial.o: serial.cc ../ddconfig.h ../globals.h ../ddconfig.h ../stypes.h \
+ ../appcl.h ../pobjcl.h ../pobjt.h ../eventcl.h ../charscl.h \
+ ../optioncl.h ../sim.src/argcl.h ../pobjcl.h ../stypes.h \
+ ../sim.src/simcl.h ../cmd.src/newcmdcl.h ../optioncl.h \
+ ../cmd.src/commandcl.h ../cmd.src/newcmdcl.h ../gui.src/guicl.h \
+ ../gui.src/ifcl.h ../sim.src/guiobjcl.h ../sim.src/uccl.h ../pobjt.h \
+ ../sim.src/hwcl.h ../sim.src/guiobjcl.h ../cmd.src/newcmdposixcl.h \
+ ../fiocl.h ../cmd.src/cmdutil.h ../sim.src/memcl.h ../eventcl.h \
+ ../errorcl.h ../sim.src/brkcl.h ../sim.src/stackcl.h ../sim.src/varcl.h \
+ ../sim.src/uccl_instructions.h ../sim.src/argcl.h ../utils.h ../fiocl.h \
+ ../cmd.src/cmdutil.h serialcl.h ../sim.src/uccl.h \
+ ../sim.src/serial_hwcl.h regs51.h uc51cl.h ../sim.src/memcl.h \
+ ../sim.src/itsrccl.h ../sim.src/brkcl.h interruptcl.h
+uc521.o: uc521.cc uc521cl.h uc52cl.h ../ddconfig.h uc51cl.h ../pobjcl.h \
+ ../ddconfig.h ../pobjt.h ../eventcl.h ../charscl.h ../sim.src/simcl.h \
+ ../cmd.src/newcmdcl.h ../optioncl.h ../pobjcl.h ../stypes.h \
+ ../cmd.src/commandcl.h ../cmd.src/newcmdcl.h ../gui.src/guicl.h \
+ ../gui.src/ifcl.h ../sim.src/guiobjcl.h ../sim.src/uccl.h ../stypes.h \
+ ../pobjt.h ../sim.src/hwcl.h ../sim.src/guiobjcl.h \
+ ../cmd.src/newcmdposixcl.h ../fiocl.h ../cmd.src/cmdutil.h \
+ ../sim.src/memcl.h ../eventcl.h ../errorcl.h ../sim.src/brkcl.h \
+ ../sim.src/stackcl.h ../sim.src/varcl.h ../sim.src/uccl_instructions.h \
+ ../sim.src/argcl.h ../sim.src/memcl.h ../sim.src/uccl.h \
+ ../sim.src/itsrccl.h ../sim.src/brkcl.h interruptcl.h
+uc320.o: uc320.cc ../ddconfig.h ../i_string.h ../ddconfig.h glob.h \
+ uc320cl.h uc521cl.h uc52cl.h uc51cl.h ../pobjcl.h ../pobjt.h \
+ ../eventcl.h ../charscl.h ../sim.src/simcl.h ../cmd.src/newcmdcl.h \
+ ../optioncl.h ../pobjcl.h ../stypes.h ../cmd.src/commandcl.h \
+ ../cmd.src/newcmdcl.h ../gui.src/guicl.h ../gui.src/ifcl.h \
+ ../sim.src/guiobjcl.h ../sim.src/uccl.h ../stypes.h ../pobjt.h \
+ ../sim.src/hwcl.h ../sim.src/guiobjcl.h ../cmd.src/newcmdposixcl.h \
+ ../fiocl.h ../cmd.src/cmdutil.h ../sim.src/memcl.h ../eventcl.h \
+ ../errorcl.h ../sim.src/brkcl.h ../sim.src/stackcl.h ../sim.src/varcl.h \
+ ../sim.src/uccl_instructions.h ../sim.src/argcl.h ../sim.src/memcl.h \
+ ../sim.src/uccl.h ../sim.src/itsrccl.h ../sim.src/brkcl.h interruptcl.h \
+ regs51.h
+glob.o: glob.cc ../stypes.h ../ddconfig.h
+pca.o: pca.cc ../sim.src/itsrccl.h ../pobjcl.h ../ddconfig.h ../pobjt.h \
+ ../eventcl.h ../charscl.h ../stypes.h ../sim.src/uccl.h ../pobjt.h \
+ ../sim.src/hwcl.h ../sim.src/guiobjcl.h ../ddconfig.h \
+ ../cmd.src/newcmdcl.h ../optioncl.h ../pobjcl.h ../stypes.h \
+ ../cmd.src/commandcl.h ../cmd.src/newcmdcl.h ../cmd.src/newcmdposixcl.h \
+ ../fiocl.h ../cmd.src/cmdutil.h ../sim.src/memcl.h ../eventcl.h \
+ ../errorcl.h ../sim.src/brkcl.h ../sim.src/stackcl.h ../sim.src/varcl.h \
+ ../sim.src/uccl_instructions.h pcacl.h ../sim.src/uccl.h regs51.h \
+ types51.h
+uc51r.o: uc51r.cc ../ddconfig.h uc51rcl.h uc52cl.h uc51cl.h ../pobjcl.h \
+ ../ddconfig.h ../pobjt.h ../eventcl.h ../charscl.h ../sim.src/simcl.h \
+ ../cmd.src/newcmdcl.h ../optioncl.h ../pobjcl.h ../stypes.h \
+ ../cmd.src/commandcl.h ../cmd.src/newcmdcl.h ../gui.src/guicl.h \
+ ../gui.src/ifcl.h ../sim.src/guiobjcl.h ../sim.src/uccl.h ../stypes.h \
+ ../pobjt.h ../sim.src/hwcl.h ../sim.src/guiobjcl.h \
+ ../cmd.src/newcmdposixcl.h ../fiocl.h ../cmd.src/cmdutil.h \
+ ../sim.src/memcl.h ../eventcl.h ../errorcl.h ../sim.src/brkcl.h \
+ ../sim.src/stackcl.h ../sim.src/varcl.h ../sim.src/uccl_instructions.h \
+ ../sim.src/argcl.h ../sim.src/memcl.h ../sim.src/uccl.h \
+ ../sim.src/itsrccl.h ../sim.src/brkcl.h interruptcl.h regs51.h types51.h \
+ wdtcl.h
+port.o: port.cc ../sim.src/argcl.h ../pobjcl.h ../ddconfig.h ../pobjt.h \
+ ../eventcl.h ../charscl.h ../stypes.h regs51.h types51.h ../ddconfig.h \
+ portcl.h ../sim.src/uccl.h ../pobjt.h ../sim.src/hwcl.h \
+ ../sim.src/guiobjcl.h ../cmd.src/newcmdcl.h ../optioncl.h ../pobjcl.h \
+ ../stypes.h ../cmd.src/commandcl.h ../cmd.src/newcmdcl.h \
+ ../cmd.src/newcmdposixcl.h ../fiocl.h ../cmd.src/cmdutil.h \
+ ../sim.src/memcl.h ../eventcl.h ../errorcl.h ../sim.src/uccl.h \
+ ../sim.src/brkcl.h ../sim.src/stackcl.h ../sim.src/varcl.h \
+ ../sim.src/uccl_instructions.h ../sim.src/port_hwcl.h
+wdt.o: wdt.cc wdtcl.h ../sim.src/uccl.h ../stypes.h ../ddconfig.h \
+ ../pobjcl.h ../pobjt.h ../eventcl.h ../charscl.h ../pobjt.h \
+ ../sim.src/hwcl.h ../sim.src/guiobjcl.h ../ddconfig.h \
+ ../cmd.src/newcmdcl.h ../optioncl.h ../pobjcl.h ../stypes.h \
+ ../cmd.src/commandcl.h ../cmd.src/newcmdcl.h ../cmd.src/newcmdposixcl.h \
+ ../fiocl.h ../cmd.src/cmdutil.h ../sim.src/memcl.h ../eventcl.h \
+ ../errorcl.h ../sim.src/uccl.h ../sim.src/brkcl.h ../sim.src/stackcl.h \
+ ../sim.src/varcl.h ../sim.src/uccl_instructions.h uc51rcl.h uc52cl.h \
+ uc51cl.h ../sim.src/simcl.h ../gui.src/guicl.h ../gui.src/ifcl.h \
+ ../sim.src/guiobjcl.h ../sim.src/argcl.h ../sim.src/memcl.h \
+ ../sim.src/itsrccl.h ../sim.src/brkcl.h interruptcl.h regs51.h
+uc517.o: uc517.cc mducl.h ../sim.src/hwcl.h ../stypes.h ../ddconfig.h \
+ ../pobjcl.h ../pobjt.h ../eventcl.h ../charscl.h ../sim.src/guiobjcl.h \
+ ../ddconfig.h ../cmd.src/newcmdcl.h ../optioncl.h ../pobjcl.h \
+ ../stypes.h ../cmd.src/commandcl.h ../cmd.src/newcmdcl.h \
+ ../cmd.src/newcmdposixcl.h ../fiocl.h ../cmd.src/cmdutil.h \
+ ../sim.src/memcl.h ../eventcl.h ../errorcl.h ../sim.src/uccl.h \
+ ../pobjt.h ../sim.src/hwcl.h ../sim.src/brkcl.h ../sim.src/stackcl.h \
+ ../sim.src/varcl.h ../sim.src/uccl_instructions.h uc517cl.h uc52cl.h \
+ uc51cl.h ../sim.src/simcl.h ../gui.src/guicl.h ../gui.src/ifcl.h \
+ ../sim.src/guiobjcl.h ../sim.src/argcl.h ../sim.src/memcl.h \
+ ../sim.src/uccl.h ../sim.src/itsrccl.h ../sim.src/brkcl.h interruptcl.h
+s51.o: s51.cc ../ddconfig.h ../globals.h ../ddconfig.h ../stypes.h \
+ ../appcl.h ../pobjcl.h ../pobjt.h ../eventcl.h ../charscl.h \
+ ../optioncl.h ../sim.src/argcl.h ../pobjcl.h ../stypes.h \
+ ../sim.src/simcl.h ../cmd.src/newcmdcl.h ../optioncl.h \
+ ../cmd.src/commandcl.h ../cmd.src/newcmdcl.h ../gui.src/guicl.h \
+ ../gui.src/ifcl.h ../sim.src/guiobjcl.h ../sim.src/uccl.h ../pobjt.h \
+ ../sim.src/hwcl.h ../sim.src/guiobjcl.h ../cmd.src/newcmdposixcl.h \
+ ../fiocl.h ../cmd.src/cmdutil.h ../sim.src/memcl.h ../eventcl.h \
+ ../errorcl.h ../sim.src/brkcl.h ../sim.src/stackcl.h ../sim.src/varcl.h \
+ ../sim.src/uccl_instructions.h ../sim.src/argcl.h ../appcl.h sim51cl.h
+uc88x.o: uc88x.cc mducl.h ../sim.src/hwcl.h ../stypes.h ../ddconfig.h \
+ ../pobjcl.h ../pobjt.h ../eventcl.h ../charscl.h ../sim.src/guiobjcl.h \
+ ../ddconfig.h ../cmd.src/newcmdcl.h ../optioncl.h ../pobjcl.h \
+ ../stypes.h ../cmd.src/commandcl.h ../cmd.src/newcmdcl.h \
+ ../cmd.src/newcmdposixcl.h ../fiocl.h ../cmd.src/cmdutil.h \
+ ../sim.src/memcl.h ../eventcl.h ../errorcl.h ../sim.src/uccl.h \
+ ../pobjt.h ../sim.src/hwcl.h ../sim.src/brkcl.h ../sim.src/stackcl.h \
+ ../sim.src/varcl.h ../sim.src/uccl_instructions.h uc88xcl.h uc52cl.h \
+ uc51cl.h ../sim.src/simcl.h ../gui.src/guicl.h ../gui.src/ifcl.h \
+ ../sim.src/guiobjcl.h ../sim.src/argcl.h ../sim.src/memcl.h \
+ ../sim.src/uccl.h ../sim.src/itsrccl.h ../sim.src/brkcl.h interruptcl.h
+timer0.o: timer0.cc timer0cl.h ../stypes.h ../ddconfig.h ../pobjcl.h \
+ ../pobjt.h ../eventcl.h ../charscl.h ../sim.src/uccl.h ../pobjt.h \
+ ../sim.src/hwcl.h ../sim.src/guiobjcl.h ../ddconfig.h \
+ ../cmd.src/newcmdcl.h ../optioncl.h ../pobjcl.h ../stypes.h \
+ ../cmd.src/commandcl.h ../cmd.src/newcmdcl.h ../cmd.src/newcmdposixcl.h \
+ ../fiocl.h ../cmd.src/cmdutil.h ../sim.src/memcl.h ../eventcl.h \
+ ../errorcl.h ../sim.src/uccl.h ../sim.src/brkcl.h ../sim.src/stackcl.h \
+ ../sim.src/varcl.h ../sim.src/uccl_instructions.h uc51cl.h \
+ ../sim.src/simcl.h ../gui.src/guicl.h ../gui.src/ifcl.h \
+ ../sim.src/guiobjcl.h ../sim.src/argcl.h ../sim.src/memcl.h \
+ ../sim.src/itsrccl.h ../sim.src/brkcl.h interruptcl.h regs51.h types51.h
+timer1.o: timer1.cc timer1cl.h ../stypes.h ../ddconfig.h ../pobjcl.h \
+ ../pobjt.h ../eventcl.h ../charscl.h ../sim.src/uccl.h ../pobjt.h \
+ ../sim.src/hwcl.h ../sim.src/guiobjcl.h ../ddconfig.h \
+ ../cmd.src/newcmdcl.h ../optioncl.h ../pobjcl.h ../stypes.h \
+ ../cmd.src/commandcl.h ../cmd.src/newcmdcl.h ../cmd.src/newcmdposixcl.h \
+ ../fiocl.h ../cmd.src/cmdutil.h ../sim.src/memcl.h ../eventcl.h \
+ ../errorcl.h ../sim.src/uccl.h ../sim.src/brkcl.h ../sim.src/stackcl.h \
+ ../sim.src/varcl.h ../sim.src/uccl_instructions.h timer0cl.h uc51cl.h \
+ ../sim.src/simcl.h ../gui.src/guicl.h ../gui.src/ifcl.h \
+ ../sim.src/guiobjcl.h ../sim.src/argcl.h ../sim.src/memcl.h \
+ ../sim.src/itsrccl.h ../sim.src/brkcl.h interruptcl.h regs51.h
diff --git a/sim/ucsim/s51.src/Makefile.in b/sim/ucsim/s51.src/Makefile.in
new file mode 100644
index 0000000..b5748bd
--- /dev/null
+++ b/sim/ucsim/s51.src/Makefile.in
@@ -0,0 +1,170 @@
+#
+# uCsim s51.src/Makefile
+#
+# (c) Drotos Daniel, Talker Bt. 1997
+#
+
+STARTYEAR	= 1997
+
+SHELL		= /bin/sh
+CXX		= @CXX@
+CPP		= @CPP@
+CXXCPP		= @CXXCPP@
+RANLIB		= @RANLIB@
+INSTALL		= @INSTALL@
+STRIP		= @STRIP@
+MAKEDEP         = @MAKEDEP@
+
+top_builddir	= @top_builddir@
+top_srcdir	= @top_srcdir@
+
+transform	= @program_transform_name@
+
+DEFS            = $(subs -DHAVE_CONFIG_H,,@DEFS@)
+CPPFLAGS        = @CPPFLAGS@ -I$(srcdir) -I$(top_srcdir) -I$(top_builddir) \
+		  -I$(top_srcdir)/cmd.src -I$(top_srcdir)/sim.src \
+		  -I$(top_srcdir)/gui.src
+CFLAGS          = @CFLAGS@ @WALL_FLAG@
+CXXFLAGS        = @CXXFLAGS@ @WALL_FLAG@
+LDFLAGS         = @LDFLAGS@
+PICOPT		= @PICOPT@
+SHAREDLIB	= @SHAREDLIB@
+
+SDCC		= sdcc
+SDCFLAGS	= --debug --stack-after-data --model-small
+SDCPPFLAGS	= 
+
+LIBS		= -L$(top_builddir) -lsim -lucsimutil -lguiucsim -lcmd -lsim @LIBS@
+DL		= @DL@
+dl_ok		= @dl_ok@
+
+prefix          = @prefix@
+exec_prefix     = @exec_prefix@
+bindir          = @bindir@
+libdir          = @libdir@
+datadir         = @datadir@
+datarootdir     = @datarootdir@
+includedir      = @includedir@
+mandir          = @mandir@
+man1dir         = $(mandir)/man1
+man2dir         = $(mandir)/man2
+infodir         = @infodir@
+srcdir          = @srcdir@
+VPATH           = @srcdir@
+
+EXEEXT		= @EXEEXT@
+
+OBJECTS_SHARED	= glob.o sim51.o \
+		  inc.o jmp.o mov.o logic.o arith.o bit.o \
+		  timer0.o timer1.o timer2.o serial.o port.o interrupt.o \
+		  wdt.o pca.o mdu.o \
+		  uc51.o uc52.o uc51r.o uc89c51r.o uc251.o uc517.o \
+		  uc390.o uc390hw.o uc521.o uc88x.o uc320.o uc380.o
+OBJECTS_EXE	= s51.o 
+OBJECTS		= $(OBJECTS_SHARED) $(OBJECTS_EXE)
+
+enable_dlso	= @enable_dlso@
+dlso_ok		= @dlso_ok@
+
+
+# Compiling entire program or any subproject
+# ------------------------------------------
+all: checkconf otherlibs s51.src
+
+
+# Compiling and installing everything and runing test
+# ---------------------------------------------------
+install: all installdirs
+	$(INSTALL) s51$(EXEEXT) $(DESTDIR)$(bindir)/`echo s51|sed '$(transform)'`$(EXEEXT)
+	$(STRIP) $(DESTDIR)$(bindir)/`echo s51|sed '$(transform)'`$(EXEEXT)
+
+
+# Deleting all the installed files
+# --------------------------------
+uninstall:
+	rm -f $(DESTDIR)$(bindir)/`echo s51|sed '$(transform)'`$(EXEEXT)
+
+
+# Performing self-test
+# --------------------
+check: test
+
+test: test_ser.ihx
+
+test_ser.ihx: test_ser.rel
+	$(SDCC) $(SDCFLAGS) $<
+
+# Performing installation test
+# ----------------------------
+installcheck:
+
+
+# Creating installation directories
+# ---------------------------------
+installdirs:
+	test -d $(DESTDIR)$(bindir) || $(INSTALL) -d $(DESTDIR)$(bindir)
+
+
+# Creating dependencies
+# ---------------------
+dep: Makefile.dep
+
+Makefile.dep: $(srcdir)/*.cc $(srcdir)/*.h
+	$(MAKEDEP) $(CPPFLAGS) $(filter %.cc,$^) >Makefile.dep
+
+-include Makefile.dep
+include $(srcdir)/clean.mk
+
+#parser.cc: parser.y
+
+#plex.cc: plex.l
+
+# My rules
+# --------
+.SUFFIXES: .rel
+
+s51.src: s51$(EXEEXT) shared_lib
+
+s51$(EXEEXT): $(OBJECTS) $(top_builddir)/libcmd.a $(top_builddir)/libguiucsim.a $(top_builddir)/libsim.a $(top_builddir)/libucsimutil.a
+	$(CXX) $(CXXFLAGS) $(LDFLAGS) $(OBJECTS) $(LIBS) -o $@
+
+ifeq ($(dlso_ok),yes)
+shared_lib: $(top_builddir)/s51.so
+else
+shared_lib:
+	@$(top_srcdir)/mkecho $(top_builddir) "No 51 shared lib made."
+	@$(top_srcdir)/mkecho $(top_builddir) "(SHAREDLIB="$(SHAREDLIB)",dl_ok="$(dl_ok)",enable_dlso="$(enable_dlso)")"
+endif
+
+$(top_builddir)/s51.so: $(OBJECTS_SHARED)
+	$(CXX) -shared $(LDFLAGS) $(OBJECTS_SHARED) -o $@
+
+otherlibs: $(top_builddir)/libcmd.a $(top_builddir)/libguiucsim.a $(top_builddir)/libsim.a $(top_builddir)/libucsimutil.a
+
+$(top_builddir)/libcmd.a:
+	$(MAKE) -C $(top_builddir)/cmd.src all
+
+$(top_builddir)/libguiucsim.a:
+	$(MAKE) -C $(top_builddir)/gui.src checkconf ucsim_lib
+
+$(top_builddir)/libsim.a:
+	$(MAKE) -C $(top_builddir)/sim.src all
+
+$(top_builddir)/libucsimutil.a:
+	$(MAKE) -C $(top_builddir) -f main.mk
+
+.cc.o:
+	$(CXX) $(CXXFLAGS) $(PICOPT) $(CPPFLAGS) -c $< -o $@
+
+.c.rel:
+	$(SDCC) $(SDCFLAGS) $(SDCPPFLAGS) -c $<
+
+
+# Remaking configuration
+# ----------------------
+checkconf:
+	@if [ -f $(top_builddir)/devel ]; then\
+	  $(MAKE) -C $(top_builddir) -f conf.mk srcdir="$(srcdir)" top_builddir="$(top_builddir)" freshconf;\
+	fi
+
+# End of s51.src/Makefile.in
diff --git a/sim/ucsim/s51.src/arith.cc b/sim/ucsim/s51.src/arith.cc
new file mode 100644
index 0000000..8a1a5e3
--- /dev/null
+++ b/sim/ucsim/s51.src/arith.cc
@@ -0,0 +1,570 @@
+/*
+ * Simulator of microcontrollers (arith.cc)
+ *
+ * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#include "ddconfig.h"
+
+#include <stdio.h>
+
+// local
+#include "uc51cl.h"
+#include "regs51.h"
+#include "types51.h"
+
+
+/*
+ * 0x03 1 12 RR A
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_51core::instruction_03/*inst_rr*/(t_mem/*uchar*/ code)
+{
+  uchar ac;
+
+  ac= acc->read(); 
+  if (ac & 0x01)
+    acc->write((ac >> 1) | 0x80);
+  else
+    acc->write(ac >> 1);
+  //vc.rd++;
+  //vc.wr++;
+  return(resGO);
+}
+
+
+/*
+ * 0x13 1 12 RRC A
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_51core::instruction_13/*inst_rrc*/(t_mem/*uchar*/ code)
+{
+  bool cy;
+  uchar ac;
+
+  cy= /*SFR_GET_C*/bits->get(0xd7);
+  /*SFR_SET_C(*/bits->set(0xd7, (ac= acc->read()) & 0x01);
+  ac>>= 1;
+  if (cy)
+    ac|= 0x80;
+  sfr->write(ACC, ac);
+  //vc.rd++;
+  //vc.wr++;
+  return(resGO);
+}
+
+
+/*
+ * 0x23 1 12 RL A
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_51core::instruction_23/*inst_rl*/(t_mem/*uchar*/ code)
+{
+  uchar ac;
+
+  ac= acc->read();
+  if (ac & 0x80)
+    acc->write((ac << 1 ) | 0x01);
+  else
+    acc->write(ac << 1);
+  //vc.rd++;
+  //vc.wr++;
+  return(resGO);
+}
+
+
+/*
+ * 0x24 2 12 ADD A,#data
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_51core::instruction_24/*inst_add_a_Sdata*/(t_mem/*uchar*/ code)
+{
+  uchar data, ac;
+  u8_t newC, newA, c6;
+
+  data= fetch();
+  ac  = acc->read();
+  newC= (((uint)ac+(uint)(data)) > 255)?0x80:0;
+  newA= ((ac&0x0f)+(data&0x0f)) & 0xf0;
+  c6  = ((ac&0x7f)+(data&0x7f)) & 0x80;
+  acc->write(ac+data);
+  /*SFR_SET_C(*/bits->set(0xd7, newC);
+  SFR_SET_BIT(newC ^ c6, PSW, bmOV);
+  SFR_SET_BIT(newA, PSW, bmAC);
+  //vc.rd++;
+  //vc.wr++;
+  return(resGO);
+}
+
+
+/*
+ * 0x25 2 12 ADD A,addr
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_51core::instruction_25/*inst_add_a_addr*/(t_mem/*uchar*/ code)
+{
+  uchar data, ac;
+  u8_t newC, newA, c6;
+  class cl_memory_cell *cell;
+  t_addr a;
+
+  cell= get_direct(a= fetch());
+  data= cell->read();
+  ac  = acc->get();
+  newC= (((uint)ac+(uint)(data)) > 255)?0x80:0;
+  newA= ((ac&0x0f)+(data&0x0f)) & 0xf0;
+  c6  = ((ac&0x7f)+(data&0x7f)) & 0x80;
+  acc->write(ac+data);
+  /*SFR_SET_C(*/bits->set(0xd7, newC);
+  SFR_SET_BIT(newC ^ c6, PSW, bmOV);
+  SFR_SET_BIT(newA, PSW, bmAC);
+  vc.rd++;//= 2;
+  //vc.wr++;
+  return(resGO);
+}
+
+
+/*
+ * 0x26-0x27 1 12 ADD A,@Ri
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_51core::instruction_26/*inst_add_a_Sri*/(t_mem/*uchar*/ code)
+{
+  uchar data, ac;
+  u8_t newC, newA, c6;
+  class cl_memory_cell *cell;
+
+  cell= iram->get_cell(R[code & 0x01]->read());
+  ac  = acc->get();
+  data= cell->read();
+  newC= (((uint)ac+(uint)data) > 255)?0x80:0;
+  newA= ((ac&0x0f)+(data&0x0f)) & 0xf0;
+  c6  = ((ac&0x7f)+(data&0x7f)) & 0x80;
+  acc->write(ac+data);
+  /*SFR_SET_C(*/bits->set(0xd7, newC);
+  SFR_SET_BIT(newC ^ c6, PSW, bmOV);
+  SFR_SET_BIT(newA, PSW, bmAC);
+  vc.rd++;//= 3;
+  //vc.wr++;
+  return(resGO);
+}
+
+
+/*
+ * 0x28-0x2f 1 12 ADD A,Rn
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_51core::instruction_28/*inst_add_a_rn*/(t_mem/*uchar*/ code)
+{
+  uchar data, ac;
+  u8_t newC, newA, c6;
+
+  data= R[code & 0x07]->read();
+  ac  = acc->get();
+  newC= (((uint)ac+(uint)data) > 255)?0x80:0;
+  newA= ((ac&0x0f)+(data&0x0f)) & 0xf0;
+  c6  = ((ac&0x7f)+(data&0x7f)) & 0x80;
+  acc->write(ac+data);
+  /*SFR_SET_C(*/bits->set(0xd7, newC);
+  SFR_SET_BIT(newC ^ c6, PSW, bmOV);
+  SFR_SET_BIT(newA, PSW, bmAC);
+  //vc.rd+= 2;
+  //vc.wr++;
+  return(resGO);
+}
+
+
+/*
+ * 0x33 1 12 RLC A
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_51core::instruction_33/*inst_rlc*/(t_mem/*uchar*/ code)
+{
+  bool cy;
+  uchar ac;
+
+  cy= /*SFR_GET_C*/bits->get(0xd7);
+  /*SFR_SET_C(*/bits->set(0xd7, (ac= acc->get()) & 0x80);
+  ac<<= 1;
+  if (cy)
+    ac|= 0x01;
+  acc->write(ac);
+  //vc.rd++;
+  //vc.wr++;
+  return(resGO);
+}
+
+
+/*
+ * 0x34 2 12 ADDC A,#data
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_51core::instruction_34/*inst_addc_a_Sdata*/(t_mem/*uchar*/ code)
+{
+  uchar data, ac;
+  u8_t orgC, newC, newA, c6;
+
+  data= fetch();
+  ac  = acc->get();
+  newC= (((uint)ac+(uint)data+((orgC= /*SFR_GET_C*/bits->get(0xd7))?1:0)) > 255)?0x80:0;
+  newA= ((ac&0x0f)+(data&0x0f)+(orgC?1:0)) & 0xf0;
+  c6  = ((ac&0x7f)+(data&0x7f)+(orgC?1:0)) & 0x80;
+  acc->write(ac + data + (orgC?1:0));
+  /*SFR_SET_C(*/bits->set(0xd7, newC);
+  SFR_SET_BIT(newC ^ c6, PSW, bmOV);
+  SFR_SET_BIT(newA, PSW, bmAC);
+  //vc.rd++;
+  //vc.wr++;
+  return(resGO);
+}
+
+
+/*
+ * 0x35 2 12 ADDC A,addr
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_51core::instruction_35/*inst_addc_a_addr*/(t_mem/*uchar*/ code)
+{
+  uchar data, ac;
+  u8_t orgC, newC, newA, c6;
+  class cl_memory_cell *cell;
+  t_addr a;
+
+  cell= get_direct(a= fetch());
+  data= cell->read();
+  ac  = acc->get();
+  newC= (((uint)ac+(uint)data+((orgC= /*SFR_GET_C*/bits->get(0xd7))?1:0)) > 255)?0x80:0;
+  newA= ((ac&0x0f)+(data&0x0f)+(orgC?1:0)) & 0xf0;
+  c6  = ((ac&0x7f)+(data&0x7f)+(orgC?1:0)) & 0x80;
+  acc->write(ac + data + (orgC?1:0));
+  /*SFR_SET_C(*/bits->set(0xd7, newC);
+  SFR_SET_BIT(newC ^ c6, PSW, bmOV);
+  SFR_SET_BIT(newA, PSW, bmAC);
+  vc.rd++;//= 2;
+  //vc.wr++;
+  return(resGO);
+}
+
+
+/*
+ * 0x36-0x37 1 12 ADDC A,@Ri
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_51core::instruction_36/*inst_addc_a_Sri*/(t_mem/*uchar*/ code)
+{
+  uchar data, ac;
+  u8_t orgC, newC, newA, c6;
+  class cl_memory_cell *cell;
+  
+  cell= iram->get_cell(R[code & 0x01]->read());
+  ac  = acc->get();
+  data= cell->read();
+  newC= (((uint)ac+(uint)data+((orgC= /*SFR_GET_C*/bits->get(0xd7))?1:0)) > 255)?0x80:0;
+  newA= ((ac&0x0f)+(data&0x0f)+(orgC?1:0)) & 0xf0;
+  c6  = ((ac&0x7f)+(data&0x7f)+(orgC?1:0)) & 0x80;
+  acc->write(ac + data + (orgC?1:0));
+  /*SFR_SET_C(*/bits->set(0xd7, newC);
+  SFR_SET_BIT(newC ^ c6, PSW, bmOV);
+  SFR_SET_BIT(newA, PSW, bmAC);
+  vc.rd++;//= 3;
+  //vc.rd++;
+  return(resGO);
+}
+
+
+/*
+ * 0x38-0x3f 1 12 ADDC A,Rn
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_51core::instruction_38/*inst_addc_a_rn*/(t_mem/*uchar*/ code)
+{
+  uchar data, ac;
+  u8_t orgC, newC, newA, c6;
+
+  data= R[code & 0x07]->read();
+  ac  = acc->get();
+  newC= (((uint)ac+(uint)data+((orgC= /*SFR_GET_C*/bits->get(0xd7))?1:0)) > 255)?0x80:0;
+  newA= ((ac&0x0f)+(data&0x0f)+(orgC?1:0)) & 0xf0;
+  c6  = ((ac&0x7f)+(data&0x7f)+(orgC?1:0)) & 0x80;
+  acc->write(ac + data + (orgC?1:0));
+  /*SFR_SET_C(*/bits->set(0xd7, newC);
+  SFR_SET_BIT(newC ^ c6, PSW, bmOV);
+  SFR_SET_BIT(newA, PSW, bmAC);
+  //vc.rd+= 2;
+  //vc.wr++;
+  return(resGO);
+}
+
+
+/*
+ * 0x84 1 48 DIV AB
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_51core::instruction_84/*inst_div_ab*/(t_mem/*uchar*/ code)
+{
+  uchar temp, pw, b, ac;
+
+  pw= psw->get();
+  pw&= ~bmCY;
+  if (!(b= sfr->get(B)))
+    pw|= bmOV;
+  else
+    {
+      pw&= ~bmOV;
+      temp= (ac= acc->get()) / b;
+      sfr->write(B, ac % b);
+      acc->write(temp);
+    }
+  psw->write(pw);
+  tick(3);
+  vc.rd++;//= 2;
+  vc.wr++;//= 2;
+  return(resGO);
+}
+
+
+/*
+ * 0x94 2 12 SUBB A,#data
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_51core::instruction_94/*inst_subb_a_Sdata*/(t_mem/*uchar*/ code)
+{
+  uchar data, ac, result, pw, c;
+
+  data= fetch();
+  ac  = acc->get();
+  result= ac-data;
+  pw= psw->get();
+  if ((c= (pw & bmCY)?1:0))
+    result--;
+  acc->write(result);
+  psw->write((pw & ~(bmCY|bmOV|bmAC)) |
+	     (((unsigned int)ac < (unsigned int)(data+c))?bmCY:0) |
+	     (((ac<0x80 && data>0x7f && result>0x7f) ||
+	       (ac>0x7f && data<0x80 && result<0x80))?bmOV:0) |
+	     (((ac&0x0f) < ((data+c)&0x0f) ||
+	       (c && ((data&0x0f)==0x0f)))?bmAC:0));
+  //vc.rd++;
+  //vc.wr++;
+  return(resGO);
+}
+
+
+/*
+ * 0x95 2 12 SUBB A,addr
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_51core::instruction_95/*inst_subb_a_addr*/(t_mem/*uchar*/ code)
+{
+  uchar data, ac, result, pw, c;
+  class cl_memory_cell *cell;
+  
+  cell= get_direct(fetch());
+  ac  = acc->get();
+  data= cell->read();
+  result= ac-data;
+  pw= psw->get();
+  if ((c= (pw & bmCY)?1:0))
+    result--;
+  acc->write(result);
+  psw->set((pw & ~(bmCY|bmOV|bmAC)) |
+	   (((unsigned int)ac < (unsigned int)(data+c))?bmCY:0) |
+	   (((ac<0x80 && data>0x7f && result>0x7f) ||
+	     (ac>0x7f && data<0x80 && result<0x80))?bmOV:0) |
+	   (((ac&0x0f) < ((data+c)&0x0f) ||
+	     (c && ((data&0x0f)==0x0f)))?bmAC:0));
+  vc.rd++;//= 2;
+  //vc.rd++;
+  return(resGO);
+}
+
+
+/*
+ * 0x96-0x97 1 12 SUBB A,@Ri
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_51core::instruction_96/*inst_subb_a_Sri*/(t_mem/*uchar*/ code)
+{
+  uchar data, ac, result, pw, c;
+  class cl_memory_cell *cell;
+
+  cell= iram->get_cell(R[code & 0x01]->read());
+  data= cell->read();
+  ac  = acc->get();
+  result= ac-data;
+  pw= psw->get();
+  if ((c= (pw & bmCY)?1:0))
+    result--;
+  acc->write(result);
+  psw->write((pw & ~(bmCY|bmOV|bmAC)) |
+	     (((unsigned int)ac < (unsigned int)(data+c))?bmCY:0) |
+	     (((ac<0x80 && data>0x7f && result>0x7f) ||
+	       (ac>0x7f && data<0x80 && result<0x80))?bmOV:0) |
+	     (((ac&0x0f) < ((data+c)&0x0f) ||
+	       (c && ((data&0x0f)==0x0f)))?bmAC:0));
+  vc.rd++;//= 3;
+  //vc.wr++;
+  return(resGO);
+}
+
+
+/*
+ * 0x98-0x9f 1 12 SUBB A,Rn
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_51core::instruction_98/*inst_subb_a_rn*/(t_mem/*uchar*/ code)
+{
+  uchar data, ac, result, pw, c;
+
+  data= R[code & 0x07]->read();
+  ac  = acc->get();
+  result= ac-data;
+  pw= psw->get();
+  if ((c= (pw & bmCY)?1:0))
+    result--;
+  acc->write(result);
+  psw->write((pw & ~(bmCY|bmOV|bmAC)) |
+	     (((unsigned int)ac < (unsigned int)(data+c))?bmCY:0) |
+	     (((ac<0x80 && data>0x7f && result>0x7f) ||
+	       (ac>0x7f && data<0x80 && result<0x80))?bmOV:0) |
+	     (((ac&0x0f) < ((data+c)&0x0f) ||
+	       (c && ((data&0x0f)==0x0f)))?bmAC:0));
+  //vc.rd+= 2;
+  //vc.wr++;
+  return(resGO);
+}
+
+
+/*
+ * 0xa4 1 48 MUL AB
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_51core::instruction_a4/*inst_mul_ab*/(t_mem/*uchar*/ code)
+{
+  uint temp, pw, ac, b, x;
+
+  pw= psw->get();
+  pw&= ~bmCY;
+  temp= (ac= acc->read()) * (b= sfr->get(B));
+  acc->write(temp & 0xff);
+  x= sfr->write(B, (temp >> 8) & 0xff);
+  SFR_SET_BIT(x/*sfr->get(B)*/, PSW, bmOV);
+  SFR_SET_BIT(0, PSW, bmCY);
+  tick(3);
+  vc.rd++;//= 2;
+  vc.wr++;//= 2;
+  return(resGO);
+}
+
+
+/*
+ * 0xd4 1 12 DA A
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_51core::instruction_d4/*inst_da_a*/(t_mem/*uchar*/ code)
+{
+  uchar ac, pw;
+
+  ac= acc->get();
+  pw= psw->get();
+  if ((ac & 0x0f) > 9 ||
+      (pw & bmAC))
+    {
+      if (((uint)ac+(uint)0x06) > 255)
+	pw|= bmCY;
+      ac+= 0x06;
+    }
+  if ((ac & 0xf0) > 0x90 ||
+      (pw & bmCY))
+    {
+      if (((uint)ac+(uint)0x60) > 255)
+	pw|= bmCY;
+      ac+= 0x60;
+    }
+  acc->write(ac);
+  psw->write(pw);
+  //vc.rd++;
+  //vc.wr++;
+  return(resGO);
+}
+
+
+/* End of s51.src/arith.cc */
diff --git a/sim/ucsim/s51.src/bit.cc b/sim/ucsim/s51.src/bit.cc
new file mode 100644
index 0000000..48d5e5b
--- /dev/null
+++ b/sim/ucsim/s51.src/bit.cc
@@ -0,0 +1,301 @@
+/*
+ * Simulator of microcontrollers (bit.cc)
+ *
+ * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#include "ddconfig.h"
+
+// local
+#include "uc51cl.h"
+#include "regs51.h"
+#include "types51.h"
+
+
+/*
+ * 0x72 2 24 ORL C,bit
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_51core::instruction_72/*inst_orl_c_bit*/(t_mem/*uchar*/ code)
+{
+  uchar bitaddr;
+
+  //t_addr a;
+  //t_mem m;
+  //class cl_address_space *mem;
+  bitaddr= fetch();
+  //mem= bit2mem(bitaddr, &a, &m);
+  /*SFR_SET_C(*/bits->set(0xd7,/*SFR_GET_C*/bits->get(0xd7) ||
+	    /*(mem->read(a) & m)*/bits->read(bitaddr));
+  tick(1);
+  vc.rd++;
+  return(resGO);
+}
+
+
+/*
+ * 0x82 2 24 ANL C,bit
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_51core::instruction_82/*inst_anl_c_bit*/(t_mem/*uchar*/ code)
+{
+  //t_mem m;
+  //t_addr a;
+  //class cl_address_space *mem;
+  u8_t bitaddr= fetch(), c= bits->get(0xd7);
+  
+  //mem= bit2mem(bitaddr, &a, &m);
+  /*SFR_SET_C*/bits->set(0xd7,/*SFR_GET_C*/c &&
+	    /*(mem->read(a) & m)*/bits->read(bitaddr));
+  tick(1);
+  vc.rd++;
+  return(resGO);
+}
+
+
+/*
+ * 0x92 2 24 MOV bit,C
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_51core::instruction_92/*inst_mov_bit_c*/(t_mem/*uchar*/ code)
+{
+  //t_addr a;
+  //t_mem m, d;
+  //class cl_address_space *mem;
+  u8_t bitaddr= fetch();
+  
+  //mem= bit2mem(bitaddr, &a, &m);
+  /*d= mem->read(a, HW_PORT);
+  if (SFR_GET_C)
+    mem->write(a, d|m);
+  else
+  mem->write(a, d&~m);*/
+  bits->write(bitaddr, /*SFR_GET_C*/bits->get(0xd7));
+  tick(1);
+  vc.rd++;
+  vc.wr++;
+  return(resGO);
+}
+
+
+/*
+ * 0xa2 2 12 MOV C,bit
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_51core::instruction_a2/*inst_mov_c_bit*/(t_mem/*uchar*/ code)
+{
+  //t_addr a;
+  //t_mem m;
+  //class cl_address_space *mem;
+  u8_t bitaddr= fetch(), x;
+  
+  //mem= bit2mem(bitaddr, &a, &m);
+  //SFR_SET_C(/*mem->read(a) & m*/bits->read(bitaddr));
+  x= bits->read(bitaddr);
+  bits->set(0xd7, x);
+  vc.rd++;
+  return(resGO);
+}
+
+
+/*
+ * 0xa0 2 24 ORL C,/bit
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_51core::instruction_a0/*inst_orl_c_Sbit*/(t_mem/*uchar*/ code)
+{
+  //t_mem m;
+  //t_addr a;
+  //class cl_address_space *mem;
+  u8_t bitaddr= fetch();
+  
+  //mem= bit2mem(fetch(), &a, &m);
+  /*SFR_SET_C(*/bits->set(0xd7, /*SFR_GET_C*/bits->get(0xd7) ||
+			  !(/*mem->read(a) & m*/bits->read(bitaddr)));
+  tick(1);
+  vc.rd++;
+  return(resGO);
+}
+
+
+/*
+ * 0xb0 2 24 ANL C,/bit
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_51core::instruction_b0/*inst_anl_c_Sbit*/(t_mem/*uchar*/ code)
+{
+  //t_mem m;
+  //t_addr a;
+  //class cl_address_space *mem;
+  u8_t bitaddr= fetch();
+    
+  //mem= bit2mem(fetch(), &a, &m);
+  /*SFR_SET_C(*/bits->set(0xd7, /*SFR_GET_C*/bits->get(0xd7) &&
+			  !(/*mem->read(a) & m*/bits->read(bitaddr)));
+  tick(1);
+  vc.rd++;
+  return(resGO);
+}
+
+
+/*
+ * 0xb2 2 12 CPL bit
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_51core::instruction_b2/*inst_cpl_bit*/(t_mem/*uchar*/ code)
+{
+  //t_addr a;
+  //t_mem m, d;
+  //class cl_address_space *mem;
+  u8_t bitaddr= fetch(), b;
+  
+  //mem= bit2mem(fetch(), &a, &m);
+  //d= mem->read(a, HW_PORT);
+  //mem->write(a, d^m);
+  b= bits->/*read*/get(bitaddr);
+  bits->write(bitaddr, !b);
+  vc.rd++;
+  vc.wr++;
+  return(resGO);
+}
+
+
+/*
+ * 0xb3 1 12 CPL C
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_51core::instruction_b3/*inst_cpl_c*/(t_mem/*uchar*/ code)
+{
+  //psw->write(psw->read() ^ bmCY);
+  bits->write(0xd7, !bits->read(0xd7));
+  //vc.rd++;
+  //vc.wr++;
+  return(resGO);
+}
+
+
+/*
+ * 0xc2 2 12 CLR bit
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_51core::instruction_c2/*inst_clr_bit*/(t_mem/*uchar*/ code)
+{
+  //t_addr a;
+  //t_mem m;
+  //class cl_address_space *mem;
+  u8_t bitaddr= fetch();//, b;
+  
+  //b= bits->get(bitaddr);
+  //mem= bit2mem(bitaddr, &a, &m);
+  //t_mem d= mem->read(a, HW_PORT);
+  //mem->write(a, d&~m);
+  bits->write(bitaddr, 0);
+  vc.rd++;
+  vc.wr++;
+  return(resGO);
+}
+
+
+/*
+ * 0xc3 1 12 CLR C
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_51core::instruction_c3/*inst_clr_c*/(t_mem/*uchar*/ code)
+{
+  //psw->write(psw->read() & ~bmCY);
+  bits->write(0xd7, 0);
+  return(resGO);
+}
+
+
+/*
+ * 0xd2 2 12 SETB bit
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_51core::instruction_d2/*inst_setb_bit*/(t_mem/*uchar*/ code)
+{
+  //t_addr a;
+  //t_mem m, d;
+  //class cl_address_space *mem;
+  u8_t bitaddr= fetch();
+  
+  //mem= bit2mem(bitaddr, &a, &m);
+  //d= mem->read(a, HW_PORT);
+  //mem->write(a, d|m);
+  bits->write(bitaddr, 1);
+  vc.rd++;
+  vc.wr++;
+  return(resGO);
+}
+
+
+/*
+ * 0xd3 1 12 SETB C
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_51core::instruction_d3/*inst_setb_c*/(t_mem/*uchar*/ code)
+{
+  //psw->write(psw->read() | bmCY);
+  bits->write(0xd7, 1);
+  return(resGO);
+}
+
+
+/* End of s51.src/bit.cc */
diff --git a/sim/ucsim/s51.src/clean.mk b/sim/ucsim/s51.src/clean.mk
new file mode 100644
index 0000000..72a866e
--- /dev/null
+++ b/sim/ucsim/s51.src/clean.mk
@@ -0,0 +1,29 @@
+# uCsim s51.src/clean.mk
+
+# Deleting all files created by building the program
+# --------------------------------------------------
+clean:
+	rm -f *core *[%~] *.[oa]
+	rm -f test_*.??* '(null).cdb' *.lnk *.ihx
+	rm -f .[a-z]*~
+	rm -f s51$(EXEEXT)
+
+
+# Deleting all files created by configuring or building the program
+# -----------------------------------------------------------------
+distclean: clean
+	rm -f config.cache config.log config.status
+	rm -f Makefile *.dep
+
+
+# Like clean but some files may still exist
+# -----------------------------------------
+mostlyclean: clean
+
+
+# Deleting everything that can reconstructed by this Makefile. It deletes
+# everything deleted by distclean plus files created by bison, etc.
+# -----------------------------------------------------------------------
+realclean: distclean
+
+# End of s51.src/clean.mk
diff --git a/sim/ucsim/s51.src/conf.mk b/sim/ucsim/s51.src/conf.mk
new file mode 100644
index 0000000..6f02f95
--- /dev/null
+++ b/sim/ucsim/s51.src/conf.mk
@@ -0,0 +1,11 @@
+# uCsim s51.src/conf.mk
+#
+# Makefile targets to remake configuration
+#
+
+freshconf: Makefile
+
+Makefile: $(srcdir)/Makefile.in $(top_srcdir)/configure.ac
+	cd $(top_builddir) && $(SHELL) ./config.status
+
+# End of s51.src/conf.mk
diff --git a/sim/ucsim/s51.src/debugger b/sim/ucsim/s51.src/debugger
new file mode 100755
index 0000000..4a30ac9
--- /dev/null
+++ b/sim/ucsim/s51.src/debugger
@@ -0,0 +1 @@
+sdcdb -s /dev/ttyp1 "$@"
diff --git a/sim/ucsim/s51.src/glob.cc b/sim/ucsim/s51.src/glob.cc
new file mode 100644
index 0000000..ed181c6
--- /dev/null
+++ b/sim/ucsim/s51.src/glob.cc
@@ -0,0 +1,299 @@
+/*
+ * Simulator of microcontrollers (glob.cc)
+ *
+ * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+
+#include <stdio.h>
+
+#include "stypes.h"
+
+
+/*
+ * Names of instructions
+ */
+ 
+struct dis_entry disass_51[]= {
+  { 0x00, 0xff, ' ', 1, "NOP"},
+  { 0x01, 0xff, 'A', 2, "AJMP %A"},
+  { 0x02, 0xff, 'L', 3, "LJMP %l"},
+  { 0x03, 0xff, ' ', 1, "RR A"},
+  { 0x04, 0xff, ' ', 1, "INC A"},
+  { 0x05, 0xff, ' ', 2, "INC %a"},
+  { 0x06, 0xff, ' ', 1, "INC @R0"},
+  { 0x07, 0xff, ' ', 1, "INC @R1"},
+  { 0x08, 0xff, ' ', 1, "INC R0"},
+  { 0x09, 0xff, ' ', 1, "INC R1"},
+  { 0x0a, 0xff, ' ', 1, "INC R2"},
+  { 0x0b, 0xff, ' ', 1, "INC R3"},
+  { 0x0c, 0xff, ' ', 1, "INC R4"},
+  { 0x0d, 0xff, ' ', 1, "INC R5"},
+  { 0x0e, 0xff, ' ', 1, "INC R6"},
+  { 0x0f, 0xff, ' ', 1, "INC R7"},
+  { 0x10, 0xff, 'R', 3, "JBC %b,%R"},
+  { 0x11, 0xff, 'a', 2, "ACALL %A"},
+  { 0x12, 0xff, 'l', 3, "LCALL %l", true},
+  { 0x13, 0xff, ' ', 1, "RRC A"},
+  { 0x14, 0xff, ' ', 1, "DEC A"},
+  { 0x15, 0xff, ' ', 2, "DEC %a"},
+  { 0x16, 0xff, ' ', 1, "DEC @R0"},
+  { 0x17, 0xff, ' ', 1, "DEC @R1"},
+  { 0x18, 0xff, ' ', 1, "DEC R0"},
+  { 0x19, 0xff, ' ', 1, "DEC R1"},
+  { 0x1a, 0xff, ' ', 1, "DEC R2"},
+  { 0x1b, 0xff, ' ', 1, "DEC R3"},
+  { 0x1c, 0xff, ' ', 1, "DEC R4"},
+  { 0x1d, 0xff, ' ', 1, "DEC R5"},
+  { 0x1e, 0xff, ' ', 1, "DEC R6"},
+  { 0x1f, 0xff, ' ', 1, "DEC R7"},
+  { 0x20, 0xff, 'R', 3, "JB %b,%R"},
+  { 0x21, 0xff, 'A', 2, "AJMP %A"},
+  { 0x22, 0xff, '_', 1, "RET"},
+  { 0x23, 0xff, ' ', 1, "RL A"},
+  { 0x24, 0xff, ' ', 2, "ADD A,#%d"},
+  { 0x25, 0xff, ' ', 2, "ADD A,%a"},
+  { 0x26, 0xff, ' ', 1, "ADD A,@R0"},
+  { 0x27, 0xff, ' ', 1, "ADD A,@R1"},
+  { 0x28, 0xff, ' ', 1, "ADD A,R0"},
+  { 0x29, 0xff, ' ', 1, "ADD A,R1"},
+  { 0x2a, 0xff, ' ', 1, "ADD A,R2"},
+  { 0x2b, 0xff, ' ', 1, "ADD A,R3"},
+  { 0x2c, 0xff, ' ', 1, "ADD A,R4"},
+  { 0x2d, 0xff, ' ', 1, "ADD A,R5"},
+  { 0x2e, 0xff, ' ', 1, "ADD A,R6"},
+  { 0x2f, 0xff, ' ', 1, "ADD A,R7"},
+  { 0x30, 0xff, 'R', 3, "JNB %b,%R"},
+  { 0x31, 0xff, 'a', 2, "ACALL %A", true},
+  { 0x32, 0xff, '_', 1, "RETI"},
+  { 0x33, 0xff, ' ', 1, "RLC A"},
+  { 0x34, 0xff, ' ', 2, "ADDC A,#%d"},
+  { 0x35, 0xff, ' ', 2, "ADDC A,%a"},
+  { 0x36, 0xff, ' ', 1, "ADDC A,@R0"},
+  { 0x37, 0xff, ' ', 1, "ADDC A,@R1"},
+  { 0x38, 0xff, ' ', 1, "ADDC A,R0"},
+  { 0x39, 0xff, ' ', 1, "ADDC A,R1"},
+  { 0x3a, 0xff, ' ', 1, "ADDC A,R2"},
+  { 0x3b, 0xff, ' ', 1, "ADDC A,R3"},
+  { 0x3c, 0xff, ' ', 1, "ADDC A,R4"},
+  { 0x3d, 0xff, ' ', 1, "ADDC A,R5"},
+  { 0x3e, 0xff, ' ', 1, "ADDC A,R6"},
+  { 0x3f, 0xff, ' ', 1, "ADDC A,R7"},
+  { 0x40, 0xff, 'r', 2, "JC %r"},
+  { 0x41, 0xff, 'A', 2, "AJMP %A"},
+  { 0x42, 0xff, ' ', 2, "ORL %a,A"},
+  { 0x43, 0xff, ' ', 3, "ORL %a,#%D"},
+  { 0x44, 0xff, ' ', 2, "ORL A,#%d"},
+  { 0x45, 0xff, ' ', 2, "ORL A,%a"},
+  { 0x46, 0xff, ' ', 1, "ORL A,@R0"},
+  { 0x47, 0xff, ' ', 1, "ORL A,@R1"},
+  { 0x48, 0xff, ' ', 1, "ORL A,R0"},
+  { 0x49, 0xff, ' ', 1, "ORL A,R1"},
+  { 0x4a, 0xff, ' ', 1, "ORL A,R2"},
+  { 0x4b, 0xff, ' ', 1, "ORL A,R3"},
+  { 0x4c, 0xff, ' ', 1, "ORL A,R4"},
+  { 0x4d, 0xff, ' ', 1, "ORL A,R5"},
+  { 0x4e, 0xff, ' ', 1, "ORL A,R6"},
+  { 0x4f, 0xff, ' ', 1, "ORL A,R7"},
+  { 0x50, 0xff, 'r', 2, "JNC %r"},
+  { 0x51, 0xff, 'a', 2, "ACALL %A", true},
+  { 0x52, 0xff, ' ', 2, "ANL %a,A"},
+  { 0x53, 0xff, ' ', 3, "ANL %a,#%D"},
+  { 0x54, 0xff, ' ', 2, "ANL A,#%d"},
+  { 0x55, 0xff, ' ', 2, "ANL A,%a"},
+  { 0x56, 0xff, ' ', 1, "ANL A,@R0"},
+  { 0x57, 0xff, ' ', 1, "ANL A,@R1"},
+  { 0x58, 0xff, ' ', 1, "ANL A,R0"},
+  { 0x59, 0xff, ' ', 1, "ANL A,R1"},
+  { 0x5a, 0xff, ' ', 1, "ANL A,R2"},
+  { 0x5b, 0xff, ' ', 1, "ANL A,R3"},
+  { 0x5c, 0xff, ' ', 1, "ANL A,R4"},
+  { 0x5d, 0xff, ' ', 1, "ANL A,R5"},
+  { 0x5e, 0xff, ' ', 1, "ANL A,R6"},
+  { 0x5f, 0xff, ' ', 1, "ANL A,R7"},
+  { 0x60, 0xff, 'r', 2, "JZ %r"},
+  { 0x61, 0xff, 'A', 2, "AJMP %A"},
+  { 0x62, 0xff, ' ', 2, "XRL %a,A"},
+  { 0x63, 0xff, ' ', 3, "XRL %a,#%D"},
+  { 0x64, 0xff, ' ', 2, "XRL A,#%d"},
+  { 0x65, 0xff, ' ', 2, "XRL A,%a"},
+  { 0x66, 0xff, ' ', 1, "XRL A,@R0"},
+  { 0x67, 0xff, ' ', 1, "XRL A,@R1"},
+  { 0x68, 0xff, ' ', 1, "XRL A,R0"},
+  { 0x69, 0xff, ' ', 1, "XRL A,R1"},
+  { 0x6a, 0xff, ' ', 1, "XRL A,R2"},
+  { 0x6b, 0xff, ' ', 1, "XRL A,R3"},
+  { 0x6c, 0xff, ' ', 1, "XRL A,R4"},
+  { 0x6d, 0xff, ' ', 1, "XRL A,R5"},
+  { 0x6e, 0xff, ' ', 1, "XRL A,R6"},
+  { 0x6f, 0xff, ' ', 1, "XRL A,R7"},
+  { 0x70, 0xff, 'r', 2, "JNZ %r"},
+  { 0x71, 0xff, 'a', 2, "ACALL %A", true},
+  { 0x72, 0xff, ' ', 2, "ORL C,%b"},
+  { 0x73, 0xff, '_', 1, "JMP @A+DPTR"},
+  { 0x74, 0xff, ' ', 2, "MOV A,#%d"},
+  { 0x75, 0xff, ' ', 3, "MOV %a,#%D"},
+  { 0x76, 0xff, ' ', 2, "MOV @R0,#%d"},
+  { 0x77, 0xff, ' ', 2, "MOV @R1,#%d"},
+  { 0x78, 0xff, ' ', 2, "MOV R0,#%d"},
+  { 0x79, 0xff, ' ', 2, "MOV R1,#%d"},
+  { 0x7a, 0xff, ' ', 2, "MOV R2,#%d"},
+  { 0x7b, 0xff, ' ', 2, "MOV R3,#%d"},
+  { 0x7c, 0xff, ' ', 2, "MOV R4,#%d"},
+  { 0x7d, 0xff, ' ', 2, "MOV R5,#%d"},
+  { 0x7e, 0xff, ' ', 2, "MOV R6,#%d"},
+  { 0x7f, 0xff, ' ', 2, "MOV R7,#%d"},
+  { 0x80, 0xff, 's', 2, "SJMP %r"},
+  { 0x81, 0xff, 'A', 2, "AJMP %A"},
+  { 0x82, 0xff, ' ', 2, "ANL C,%b"},
+  { 0x83, 0xff, ' ', 1, "MOVC A,@A+PC"},
+  { 0x84, 0xff, ' ', 1, "DIV AB"},
+  { 0x85, 0xff, ' ', 3, "MOV %8,%a"},
+  { 0x86, 0xff, ' ', 2, "MOV %a,@R0"},
+  { 0x87, 0xff, ' ', 2, "MOV %a,@R1"},
+  { 0x88, 0xff, ' ', 2, "MOV %a,R0"},
+  { 0x89, 0xff, ' ', 2, "MOV %a,R1"},
+  { 0x8a, 0xff, ' ', 2, "MOV %a,R2"},
+  { 0x8b, 0xff, ' ', 2, "MOV %a,R3"},
+  { 0x8c, 0xff, ' ', 2, "MOV %a,R4"},
+  { 0x8d, 0xff, ' ', 2, "MOV %a,R5"},
+  { 0x8e, 0xff, ' ', 2, "MOV %a,R6"},
+  { 0x8f, 0xff, ' ', 2, "MOV %a,R7"},
+  { 0x90, 0xff, ' ', 3, "MOV DPTR,#%6"},
+  { 0x91, 0xff, 'a', 2, "ACALL %A", true},
+  { 0x92, 0xff, ' ', 2, "MOV %b,C"},
+  { 0x93, 0xff, ' ', 1, "MOVC A,@A+DPTR"},
+  { 0x94, 0xff, ' ', 2, "SUBB A,#%d"},
+  { 0x95, 0xff, ' ', 2, "SUBB A,%a"},
+  { 0x96, 0xff, ' ', 1, "SUBB A,@R0"},
+  { 0x97, 0xff, ' ', 1, "SUBB A,@R1"},
+  { 0x98, 0xff, ' ', 1, "SUBB A,R0"},
+  { 0x99, 0xff, ' ', 1, "SUBB A,R1"},
+  { 0x9a, 0xff, ' ', 1, "SUBB A,R2"},
+  { 0x9b, 0xff, ' ', 1, "SUBB A,R3"},
+  { 0x9c, 0xff, ' ', 1, "SUBB A,R4"},
+  { 0x9d, 0xff, ' ', 1, "SUBB A,R5"},
+  { 0x9e, 0xff, ' ', 1, "SUBB A,R6"},
+  { 0x9f, 0xff, ' ', 1, "SUBB A,R7"},
+  { 0xa0, 0xff, ' ', 2, "ORL C,/%b"},
+  { 0xa1, 0xff, 'A', 2, "AJMP %A"},
+  { 0xa2, 0xff, ' ', 2, "MOV C,%b"},
+  { 0xa3, 0xff, ' ', 1, "INC DPTR"},
+  { 0xa4, 0xff, ' ', 1, "MUL AB"},
+  { 0xa5, 0xff, '_', 1, "-"},
+  { 0xa6, 0xff, ' ', 2, "MOV @R0,%a"},
+  { 0xa7, 0xff, ' ', 2, "MOV @R1,%a"},
+  { 0xa8, 0xff, ' ', 2, "MOV R0,%a"},
+  { 0xa9, 0xff, ' ', 2, "MOV R1,%a"},
+  { 0xaa, 0xff, ' ', 2, "MOV R2,%a"},
+  { 0xab, 0xff, ' ', 2, "MOV R3,%a"},
+  { 0xac, 0xff, ' ', 2, "MOV R4,%a"},
+  { 0xad, 0xff, ' ', 2, "MOV R5,%a"},
+  { 0xae, 0xff, ' ', 2, "MOV R6,%a"},
+  { 0xaf, 0xff, ' ', 2, "MOV R7,%a"},
+  { 0xb0, 0xff, ' ', 2, "ANL C,/%b"},
+  { 0xb1, 0xff, 'a', 2, "ACALL %A", true},
+  { 0xb2, 0xff, ' ', 2, "CPL %b"},
+  { 0xb3, 0xff, ' ', 1, "CPL C"},
+  { 0xb4, 0xff, 'R', 3, "CJNE A,#%d,%R"},
+  { 0xb5, 0xff, 'R', 3, "CJNE A,%a,%R"},
+  { 0xb6, 0xff, 'R', 3, "CJNE @R0,#%d,%R"},
+  { 0xb7, 0xff, 'R', 3, "CJNE @R1,#%d,%R"},
+  { 0xb8, 0xff, 'R', 3, "CJNE R0,#%d,%R"},
+  { 0xb9, 0xff, 'R', 3, "CJNE R1,#%d,%R"},
+  { 0xba, 0xff, 'R', 3, "CJNE R2,#%d,%R"},
+  { 0xbb, 0xff, 'R', 3, "CJNE R3,#%d,%R"},
+  { 0xbc, 0xff, 'R', 3, "CJNE R4,#%d,%R"},
+  { 0xbd, 0xff, 'R', 3, "CJNE R5,#%d,%R"},
+  { 0xbe, 0xff, 'R', 3, "CJNE R6,#%d,%R"},
+  { 0xbf, 0xff, 'R', 3, "CJNE R7,#%d,%R"},
+  { 0xc0, 0xff, ' ', 2, "PUSH %a"},
+  { 0xc1, 0xff, 'A', 2, "AJMP %A"},
+  { 0xc2, 0xff, ' ', 2, "CLR %b"},
+  { 0xc3, 0xff, ' ', 1, "CLR C"},
+  { 0xc4, 0xff, ' ', 1, "SWAP A"},
+  { 0xc5, 0xff, ' ', 2, "XCH A,%a"},
+  { 0xc6, 0xff, ' ', 1, "XCH A,@R0"},
+  { 0xc7, 0xff, ' ', 1, "XCH A,@R1"},
+  { 0xc8, 0xff, ' ', 1, "XCH A,R0"},
+  { 0xc9, 0xff, ' ', 1, "XCH A,R1"},
+  { 0xca, 0xff, ' ', 1, "XCH A,R2"},
+  { 0xcb, 0xff, ' ', 1, "XCH A,R3"},
+  { 0xcc, 0xff, ' ', 1, "XCH A,R4"},
+  { 0xcd, 0xff, ' ', 1, "XCH A,R5"},
+  { 0xce, 0xff, ' ', 1, "XCH A,R6"},
+  { 0xcf, 0xff, ' ', 1, "XCH A,R7"},
+  { 0xd0, 0xff, ' ', 2, "POP %a"},
+  { 0xd1, 0xff, 'a', 2, "ACALL %A", true},
+  { 0xd2, 0xff, ' ', 2, "SETB %b"},
+  { 0xd3, 0xff, ' ', 1, "SETB C"},
+  { 0xd4, 0xff, ' ', 1, "DA A"},
+  { 0xd5, 0xff, 'R', 3, "DJNZ %a,%R"},
+  { 0xd6, 0xff, ' ', 1, "XCHD A,@R0"},
+  { 0xd7, 0xff, ' ', 1, "XCHD A,@R1"},
+  { 0xd8, 0xff, 'r', 2, "DJNZ R0,%r"},
+  { 0xd9, 0xff, 'r', 2, "DJNZ R1,%r"},
+  { 0xda, 0xff, 'r', 2, "DJNZ R2,%r"},
+  { 0xdb, 0xff, 'r', 2, "DJNZ R3,%r"},
+  { 0xdc, 0xff, 'r', 2, "DJNZ R4,%r"},
+  { 0xdd, 0xff, 'r', 2, "DJNZ R5,%r"},
+  { 0xde, 0xff, 'r', 2, "DJNZ R6,%r"},
+  { 0xdf, 0xff, 'r', 2, "DJNZ R7,%r"},
+  { 0xe0, 0xff, ' ', 1, "MOVX A,@DPTR"},
+  { 0xe1, 0xff, 'A', 2, "AJMP %A"},
+  { 0xe2, 0xff, ' ', 1, "MOVX A,@R0"},
+  { 0xe3, 0xff, ' ', 1, "MOVX A,@R1"},
+  { 0xe4, 0xff, ' ', 1, "CLR A"},
+  { 0xe5, 0xff, ' ', 2, "MOV A,%a"},
+  { 0xe6, 0xff, ' ', 1, "MOV A,@R0"},
+  { 0xe7, 0xff, ' ', 1, "MOV A,@R1"},
+  { 0xe8, 0xff, ' ', 1, "MOV A,R0"},
+  { 0xe9, 0xff, ' ', 1, "MOV A,R1"},
+  { 0xea, 0xff, ' ', 1, "MOV A,R2"},
+  { 0xeb, 0xff, ' ', 1, "MOV A,R3"},
+  { 0xec, 0xff, ' ', 1, "MOV A,R4"},
+  { 0xed, 0xff, ' ', 1, "MOV A,R5"},
+  { 0xee, 0xff, ' ', 1, "MOV A,R6"},
+  { 0xef, 0xff, ' ', 1, "MOV A,R7"},
+  { 0xf0, 0xff, ' ', 1, "MOVX @DPTR,A"},
+  { 0xf1, 0xff, 'a', 2, "ACALL %A", true},
+  { 0xf2, 0xff, ' ', 1, "MOVX @R0,A"},
+  { 0xf3, 0xff, ' ', 1, "MOVX @R1,A"},
+  { 0xf4, 0xff, ' ', 1, "CPL A"},
+  { 0xf5, 0xff, ' ', 2, "MOV %a,A"},
+  { 0xf6, 0xff, ' ', 1, "MOV @R0,A"},
+  { 0xf7, 0xff, ' ', 1, "MOV @R1,A"},
+  { 0xf8, 0xff, ' ', 1, "MOV R0,A"},
+  { 0xf9, 0xff, ' ', 1, "MOV R1,A"},
+  { 0xfa, 0xff, ' ', 1, "MOV R2,A"},
+  { 0xfb, 0xff, ' ', 1, "MOV R3,A"},
+  { 0xfc, 0xff, ' ', 1, "MOV R4,A"},
+  { 0xfd, 0xff, ' ', 1, "MOV R5,A"},
+  { 0xfe, 0xff, ' ', 1, "MOV R6,A"},
+  { 0xff, 0xff, ' ', 1, "MOV R7,A"},
+  { 0, 0, 0, 0, NULL }
+};
+
+
+/* End of s51.src/glob.cc */
diff --git a/sim/ucsim/s51.src/glob.h b/sim/ucsim/s51.src/glob.h
new file mode 100644
index 0000000..499d7aa
--- /dev/null
+++ b/sim/ucsim/s51.src/glob.h
@@ -0,0 +1,37 @@
+/*
+ * Simulator of microcontrollers (glob.h)
+ *
+ * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#ifndef GLOB_HEADER
+#define GLOB_HEADER
+
+
+extern struct dis_entry  disass_51[];
+
+
+#endif
+
+/* End of s51.src/glob.h */
diff --git a/sim/ucsim/s51.src/inc.cc b/sim/ucsim/s51.src/inc.cc
new file mode 100644
index 0000000..645f9cc
--- /dev/null
+++ b/sim/ucsim/s51.src/inc.cc
@@ -0,0 +1,201 @@
+/*
+ * Simulator of microcontrollers (inc.cc)
+ *
+ * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#include "ddconfig.h"
+
+// local
+#include "uc51cl.h"
+#include "regs51.h"
+
+
+/*
+ * 0x04 1 12 INC A
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_51core::instruction_04/*inst_inc_a*/(t_mem/*uchar*/ code)
+{
+  acc->wadd(1);
+  return(resGO);
+  //vc.rd++;
+  //vc.wr++;
+}
+
+
+/*
+ * 0x05 2 12 INC addr
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_51core::instruction_05/*inst_inc_addr*/(t_mem/*uchar*/ code)
+{
+  class cl_memory_cell *cell= get_direct(fetch());
+
+  t_mem d= cell->read(HW_PORT);
+  cell->write(d+1);
+  vc.rd++;
+  vc.wr++;
+  return(resGO);
+}
+
+
+/*
+ * 0x06-0x07 1 12 INC @Ri
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_51core::instruction_06/*inst_inc_Sri*/(t_mem/*uchar*/ code)
+{
+  class cl_memory_cell *cell;
+
+  cell= iram->get_cell(R[code & 0x01]->read());
+  cell->wadd(1);
+  vc.rd++;//= 2;
+  vc.wr++;
+  return(resGO);
+}
+
+
+/*
+ * 0x08-0x0f 1 12 INC Rn
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_51core::instruction_08/*inst_inc_rn*/(t_mem/*uchar*/ code)
+{
+  class cl_memory_cell *reg= R[code & 0x07];
+
+  reg->wadd(1);
+  //vc.rd++;
+  //vc.wr++;
+  return(resGO);
+}
+
+
+/*
+ * 0x14 1 12 DEC A
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_51core::instruction_14/*inst_dec_a*/(t_mem/*uchar*/ code)
+{
+  acc->wadd(-1);
+  //vc.rd++;
+  //vc.wr++;
+  return(resGO);
+}
+
+
+/*
+ * 0x15 2 12 DEC addr
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_51core::instruction_15/*inst_dec_addr*/(t_mem/*uchar*/ code)
+{
+  class cl_memory_cell *cell;
+
+  cell= get_direct(fetch());
+  t_mem d= cell->read(HW_PORT);
+  cell->write(d-1);
+  vc.rd++;
+  vc.wr++;
+  return(resGO);
+}
+
+
+/*
+ * 0x16-0x17 1 12 DEC @Ri
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_51core::instruction_16/*inst_dec_Sri*/(t_mem/*uchar*/ code)
+{
+  class cl_memory_cell *cell;
+
+  cell= iram->get_cell(R[code & 0x01]->read());
+  cell->add(-1);
+  vc.rd++;//= 2;
+  vc.wr++;
+  return(resGO);
+}
+
+
+/*
+ * 0x18-0x1f 1 12 DEC Rn
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_51core::instruction_18/*inst_dec_rn*/(t_mem/*uchar*/ code)
+{
+  class cl_memory_cell *reg= R[code & 0x07];
+
+  reg->wadd(-1);
+  //vc.rd++;
+  //vc.wr++;
+  return(resGO);
+}
+
+
+/*
+ * 0xa3 1 24 INC DPTR
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_51core::instruction_a3/*inst_inc_dptr*/(t_mem/*uchar*/ code)
+{
+  uint _dptr;
+
+  _dptr= /*sfr*/dptr->read(/*DPH*/1)*256 + /*sfr*/dptr->read(/*DPL*/0) + 1;
+  /*sfr*/dptr->write(/*DPH*/1, (_dptr >> 8) & 0xff);
+  /*sfr*/dptr->write(/*DPL*/0, _dptr & 0xff);
+  tick(1);
+  vc.rd+= 2;
+  vc.wr+= 2;
+  return(resGO);
+}
+
+
+/* End of s51.src/inc.cc */
diff --git a/sim/ucsim/s51.src/inst.list b/sim/ucsim/s51.src/inst.list
new file mode 100644
index 0000000..99286e4
--- /dev/null
+++ b/sim/ucsim/s51.src/inst.list
@@ -0,0 +1,256 @@
+0x00	NOP			1	12
+0x01	AJMP addr		2	24
+0x02	LJMP addr		3	24
+0x03	RR A			1	12
+0x04	INC A			1	12
+0x05	INC addr		2	12
+0x06	INC @R0			1	12
+0x07	INC @R1			1	12
+0x08	INC R0			1	12
+0x09	INC R1			1	12
+0x0a	INC R2			1	12
+0x0b	INC R3			1	12
+0x0c	INC R4			1	12
+0x0d	INC R5			1	12
+0x0e	INC R6			1	12
+0x0f	INC R7			1	12
+0x10	JBC bit,addr		3	12
+0x11	ACALL addr		2	24
+0x12	LCALL addr		3	24
+0x13	RRC A			1	12
+0x14	DEC A			1	12
+0x15	DEC addr		2	12
+0x16	DEC @R0			1	12
+0x17	DEC @R1			1	12
+0x18	DEC R0			1	12
+0x19	DEC R1			1	12
+0x1a	DEC R2			1	12
+0x1b	DEC R3			1	12
+0x1c	DEC R4			1	12
+0x1d	DEC R5			1	12
+0x1e	DEC R6			1	12
+0x1f	DEC R7			1	12
+0x20	JB bit,addr		3	24
+0x21	AJMP addr		2	24
+0x22	RET			1	24
+0x23	RL A			1	12
+0x24	ADD A,#data		2	12
+0x25	ADD A,addr		2	12
+0x26	ADD A,@R0		1	12
+0x27	ADD A,@R1		1	12
+0x28	ADD A,R0		1	12
+0x29	ADD A,R1		1	12
+0x2a	ADD A,R2		1	12
+0x2b	ADD A,R3		1	12
+0x2c	ADD A,R4		1	12
+0x2d	ADD A,R5		1	12
+0x2e	ADD A,R6		1	12
+0x2f	ADD A,R7		1	12
+0x30	JNB bit,addr		3	12(?)
+0x31	ACALL addr		2	24
+0x32	RETI			1	24
+0x33	RLC A			1	12
+0x34	ADDC A,#data		2	12
+0x35	ADDC A,addr		2	12
+0x36	ADDC A,@R0		1	12
+0x37	ADDC A,@R1		1	12
+0x38	ADDC A,R0		1	12
+0x39	ADDC A,R1		1	12
+0x3a	ADDC A,R2		1	12
+0x3b	ADDC A,R3		1	12
+0x3c	ADDC A,R4		1	12
+0x3d	ADDC A,R5		1	12
+0x3e	ADDC A,R6		1	12
+0x3f	ADDC A,R7		1	12
+0x40	JC addr			2	24
+0x41	AJMP addr		2	24
+0x42	ORL addr,A		2	12
+0x43	ORL addr,#data		3	24
+0x44	ORL A,#data		2	12
+0x45	ORL A,addr		2	12
+0x46	ORL A,@R0		1	12
+0x47	ORL A,@R1		1	12
+0x48	ORL A,R0		1	12
+0x49	ORL A,R1		1	12
+0x4a	ORL A,R2		1	12
+0x4b	ORL A,R3		1	12
+0x4c	ORL A,R4		1	12
+0x4d	ORL A,R5		1	12
+0x4e	ORL A,R6		1	12
+0x4f	ORL A,R7		1	12
+0x50	JNC addr		2	24
+0x51	ACALL addr		2	24
+0x52	ANL addr,A		2	12
+0x53	ANL addr,#data		3	24
+0x54	ANL A,#data		2	12
+0x55	ANL A,addr		2	12
+0x56	ANL A,@R0		1	12
+0x57	ANL A,@R1		1	12
+0x58	ANL A,R0		1	12
+0x59	ANL A,R1		1	12
+0x5a	ANL A,R2		1	12
+0x5b	ANL A,R3		1	12
+0x5c	ANL A,R4		1	12
+0x5d	ANL A,R5		1	12
+0x5e	ANL A,R6		1	12
+0x5f	ANL A,R7		1	12
+0x60	JZ addr			2	24
+0x61	AJMP addr		2	24
+0x62	XRL addr,A		2	12
+0x63	XRL addr,#data		3	24
+0x64	XRL A,#data		2	12
+0x65	XRL A,addr		2	12
+0x66	XRL A,@R0		1	12
+0x67	XRL A,@R1		1	12
+0x68	XRL A,R0		1	12
+0x69	XRL A,R1		1	12
+0x6a	XRL A,R2		1	12
+0x6b	XRL A,R3		1	12
+0x6c	XRL A,R4		1	12
+0x6d	XRL A,R5		1	12
+0x6e	XRL A,R6		1	12
+0x6f	XRL A,R7		1	12
+0x70	JNZ addr		2	24
+0x71	ACALL addr		2	24
+0x72	ORL C,addr		2	24
+0x73	JMP @A+DPTR		1	24
+0x74	MOV A,#data		2	12
+0x75	MOV addr,#data		3	24
+0x76	MOV @R0,#data		2	12
+0x77	MOV @R1,#data		2	12
+0x78	MOV R0,#data		2	12
+0x79	MOV R1,#data		2	12
+0x7a	MOV R2,#data		2	12
+0x7b	MOV R3,#data		2	12
+0x7c	MOV R4,#data		2	12
+0x7d	MOV R5,#data		2	12
+0x7e	MOV R6,#data		2	12
+0x7f	MOV R7,#data		2	12
+0x80	SJMP addr		2	24
+0x81	AJMP addr		2	24
+0x82	ANL C,addr		2	24
+0x83	MOVC A,@A+PC		1	24
+0x84	DIV AB			1	48
+0x85	MOV addr,addr		3	24
+0x86	MOV addr,@R0		2	24
+0x87	MOV addr,@R1		2	24
+0x88	MOV addr,R0		2	24
+0x89	MOV addr,R1		2	24
+0x8a	MOV addr,R2		2	24
+0x8b	MOV addr,R3		2	24
+0x8c	MOV addr,R4		2	24
+0x8d	MOV addr,R5		2	24
+0x8e	MOV addr,R6		2	24
+0x8f	MOV addr,R7		2	24
+0x90	MOV DPTR,#data		3	24
+0x91	ACALL addr		2	24
+0x92	MOV addr,C		2	24
+0x93	MOVC A,@A+DPTR		1	24
+0x94	SUBB A,#data		2	12
+0x95	SUBB A,addr		2	12
+0x96	SUBB A,@R0		1	12
+0x97	SUBB A,@R1		1	12
+0x98	SUBB A,R0		1	12
+0x99	SUBB A,R1		1	12
+0x9a	SUBB A,R2		1	12
+0x9b	SUBB A,R3		1	12
+0x9c	SUBB A,R4		1	12
+0x9d	SUBB A,R5		1	12
+0x9e	SUBB A,R6		1	12
+0x9f	SUBB A,R7		1	12
+0xa0	ORL C,/addr		2	24
+0xa1	AJMP addr		2	24
+0xa2	MOV C,addr		2	12
+0xa3	INC DPTR		1	24
+0xa4	MUL AB			1	48
+0xa5	****************Breakpoint
+0xa6	MOV @R0,addr		2	24
+0xa7	MOV @R1,addr		2	24
+0xa8	MOV R0,addr		2	24
+0xa9	MOV R1,addr		2	24
+0xaa	MOV R2,addr		2	24
+0xab	MOV R3,addr		2	24
+0xac	MOV R4,addr		2	24
+0xad	MOV R5,addr		2	24
+0xae	MOV R6,addr		2	24
+0xaf	MOV R7,addr		2	24
+0xb0	ANL C,/addr		2	24
+0xb1	ACALL addr		2	24
+0xb2	CPL bitaddr		2	12
+0xb3	CPL C			1	12
+0xb4	CJNE A,#data,addr	3	24
+0xb5	CJNE A,addr,addr	3	24
+0xb6	CJNE @R0,#data,addr	3	24
+0xb7	CJNE @R1,#data,addr	3	24
+0xb8	CJNE R0,#data,addr	3	24
+0xb9	CJNE R1,#data,addr	3	24
+0xba	CJNE R2,#data,addr	3	24
+0xbb	CJNE R3,#data,addr	3	24
+0xbc	CJNE R4,#data,addr	3	24
+0xbd	CJNE R5,#data,addr 	3	24
+0xbe	CJNE R6,#data,addr	3	24
+0xbf	CJNE R7,#data,addr	3	24
+0xc0	PUSH addr		2	24
+0xc1	AJMP addr		2	24
+0xc2	CLR bitaddr		2	12
+0xc3	CLR C			1	12
+0xc4	SWAP A			1	12
+0xc5	XCH A,addr		2	12
+0xc6	XCH A,@R0		1	12
+0xc7	XCH A,@R1		1	12
+0xc8	XCH A,R0		1	12
+0xc9	XCH A,R1		1	12
+0xca	XCH A,R2		1	12
+0xcb	XCH A,R3		1	12
+0xcc	XCH A,R4		1	12
+0xcd	XCH A,R5		1	12
+0xce	XCH A,R6		1	12
+0xcf	XCH A,R7		1	12
+0xd0	POP addr		2	24
+0xd1	ACALL addr		2	24
+0xd2	SETB addr		2	12
+0xd3	SETB C			1	12
+0xd4	DA A			1	12
+0xd5	DJNZ addr,addr		3	24
+0xd6	XCHD A,@R0		1	12
+0xd7	XCHD A,@R1		1	12
+0xd8	DJNZ R0,addr		2	24
+0xd9	DJNZ R1,addr		2	24
+0xda	DJNZ R2,addr		2	24
+0xdb	DJNZ R3,addr		2	24
+0xdc	DJNZ R4,addr		2	24
+0xdd	DJNZ R5,addr		2	24
+0xde	DJNZ R6,addr		2	24
+0xdf	DJNZ R7,addr		2	24
+0xe0	MOVX A,@DPTR		1	24
+0xe1	AJMP addr		2	24
+0xe2	MOVX A,@R0		1	24
+0xe3	MOVX A,@R1		1	24
+0xe4	CLR A			1	12
+0xe5	MOV A,addr		2	12
+0xe6	MOV A,@R0		1	12
+0xe7	MOV A,@R1		1	12
+0xe8	MOV A,R0		1	12
+0xe9	MOV A,R1		1	12
+0xea	MOV A,R2		1	12
+0xeb	MOV A,R3		1	12
+0xec	MOV A,R4		1	12
+0xed	MOV A,R5		1	12
+0xee	MOV A,R6		1	12
+0xef	MOV A,R7		1	12
+0xf0	MOVX @DPTR,A		1	24
+0xf1	ACALL addr		2	24
+0xf2	MOVX @R0,A		1	24
+0xf3	MOVX @R1,A		1	24
+0xf4	CPL A			1	12
+0xf5	MOV addr,A		2	12
+0xf6	MOV @R0,A		1	12
+0xf7	MOV @R1,A		1	12
+0xf8	MOV R0,A		1	12
+0xf9	MOV R1,A		1	12
+0xfa	MOV R2,A		1	12
+0xfb	MOV R3,A		1	12
+0xfc	MOV R4,A		1	12
+0xfd	MOV R5,A		1	12
+0xfe	MOV R6,A		1	12
+0xff	MOV R7,A		1	12
diff --git a/sim/ucsim/s51.src/interrupt.cc b/sim/ucsim/s51.src/interrupt.cc
new file mode 100644
index 0000000..b050045
--- /dev/null
+++ b/sim/ucsim/s51.src/interrupt.cc
@@ -0,0 +1,188 @@
+/*
+ * Simulator of microcontrollers (interrupt.cc)
+ *
+ * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+// prj
+#include <stdarg.h>
+#include "utils.h"
+
+// sim
+#include "itsrccl.h"
+
+// local
+#include "interruptcl.h"
+#include "regs51.h"
+//#include "uc51cl.h"
+#include "types51.h"
+
+
+cl_interrupt::cl_interrupt(class cl_uc *auc):
+  cl_hw(auc, HW_INTERRUPT, 0, "irq")
+{
+  was_reti= false;
+}
+
+int
+cl_interrupt::init(void)
+{
+  cl_hw::init();
+  sfr= uc->address_space(MEM_SFR_ID);
+  if (sfr)
+    {
+      register_cell(sfr, IE);
+      cell_tcon= register_cell(sfr, TCON);
+      bit_INT0= sfr->read(P3) & bm_INT0;
+      bit_INT1= sfr->read(P3) & bm_INT1;
+      cl_address_space *bas= uc->address_space("bits");
+      cell_it0= register_cell(bas, 0x88);
+      cell_it1= register_cell(bas, 0x8a);
+    }
+  return(0);
+}
+
+void
+cl_interrupt::added_to_uc(void)
+{
+  class cl_address_space *sfr= uc->address_space(MEM_SFR_ID);
+  class cl_it_src *is;
+  
+  uc->it_sources->add(is= new cl_it_src(uc, bmEX0,
+					sfr->get_cell(IE), bmEX0,
+					sfr->get_cell(TCON), bmIE0,
+					0x0003, true, false,
+					"external #0", 1));
+  is->init();
+  uc->it_sources->add(is= new cl_it_src(uc, bmEX1,
+					sfr->get_cell(IE), bmEX1,
+					sfr->get_cell(TCON), bmIE1,
+					0x0013, true, false,
+					"external #1", 3));
+  is->init();
+}
+
+void
+cl_interrupt::write(class cl_memory_cell *cell, t_mem *val)
+{
+  if (cell == cell_it0)
+    bit_IT0= *val;
+  else if (cell == cell_it1)
+    bit_IT1= *val;
+  else if (cell == cell_tcon)
+    {
+      bit_IT0= *val & bmIT0;
+      bit_IT1= *val & bmIT1;
+    }
+  else
+    // IE register
+    was_reti= true;
+}
+
+/*void
+cl_interrupt::mem_cell_changed(class cl_m *mem, t_addr addr)
+{
+}*/
+
+int
+cl_interrupt::tick(int cycles)
+{
+  if (!bit_IT0 && !bit_INT0)
+    cell_tcon->set_bit1(bmIE0);
+  if (!bit_IT1 && !bit_INT1)
+    cell_tcon->set_bit1(bmIE1);
+  return(resGO);
+}
+
+void
+cl_interrupt::reset(void)
+{
+  was_reti= false;
+}
+
+void
+cl_interrupt::happen(class cl_hw *where, enum hw_event he, void *params)
+{
+  struct ev_port_changed *ep= (struct ev_port_changed *)params;
+
+  if (where->cathegory == HW_PORT &&
+      he == EV_PORT_CHANGED &&
+      ep->id == 3)
+    {
+      t_mem p3n= ep->new_pins & ep->new_value;
+      t_mem p3o= ep->pins & ep->prev_value;
+      if (bit_IT0 &&
+	  !(p3n & bm_INT0) &&
+	  (p3o & bm_INT0))
+	cell_tcon->set_bit1(bmIE0);
+      if (bit_IT1 &&
+	  !(p3n & bm_INT1) &&
+	  (p3o & bm_INT1))
+	cell_tcon->set_bit1(bmIE1);
+      bit_INT0= p3n & bm_INT0;
+      bit_INT1= p3n & bm_INT1;
+    }
+}
+
+
+void
+cl_interrupt::print_info(class cl_console_base *con)
+{
+  //int ie= sfr->get(IE);
+  int i;
+
+  con->dd_printf("Interrupts are %s. Interrupt sources:\n",
+		 (uc->it_enabled())?"enabled":"disabled");
+  con->dd_printf("  Handler  En  Pr Req Act Name\n");
+  for (i= 0; i < uc->it_sources->count; i++)
+    {
+      class cl_it_src *is= (class cl_it_src *)(uc->it_sources->at(i));
+      con->dd_printf("  0x%06x", AU(is->addr));
+      con->dd_printf(" %-3s", (is->enabled())?"en":"dis");
+      con->dd_printf(" %2d", uc->priority_of(is->ie_mask));
+      con->dd_printf(" %-3s", (is->pending())?"YES":"no");
+      con->dd_printf(" %-3s", (is->active)?"act":"no");
+      con->dd_printf(" %s", object_name(is));
+      con->dd_printf("\n");
+    }
+  con->dd_printf("Active interrupt service(s):\n");
+  con->dd_printf("  Pr Handler  PC       Source\n");
+  for (i= 0; i < uc->it_levels->count; i++)
+    {
+      class it_level *il= (class it_level *)(uc->it_levels->at(i));
+      if (il->level >= 0)
+	{
+	  con->dd_printf("  %2d", il->level);
+	  con->dd_printf(" 0x%06x", AU(il->addr));
+	  con->dd_printf(" 0x%06x", AU(il->PC));
+	  con->dd_printf(" %s", (il->source)?(object_name(il->source)):
+			 "nothing");
+	  con->dd_printf("\n");
+	}
+    }
+  print_cfg_info(con);
+}
+
+
+/* End of s51.src/interrupt.cc */
diff --git a/sim/ucsim/s51.src/interruptcl.h b/sim/ucsim/s51.src/interruptcl.h
new file mode 100644
index 0000000..7e35cb2
--- /dev/null
+++ b/sim/ucsim/s51.src/interruptcl.h
@@ -0,0 +1,66 @@
+/*
+ * Simulator of microcontrollers (interruptcl.h)
+ *
+ * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#ifndef INTERRUPTCL_HEADER
+#define INTERRUPTCL_HEADER
+
+#include "stypes.h"
+#include "pobjcl.h"
+#include "uccl.h"
+
+#include "newcmdcl.h"
+
+
+class cl_interrupt: public cl_hw
+{
+public:
+  class cl_address_space *sfr;
+  bool was_reti, bit_IT0, bit_IT1, bit_INT0, bit_INT1;
+  class cl_memory_cell *cell_tcon, *cell_it0, *cell_it1;
+public:
+  cl_interrupt(class cl_uc *auc);
+  virtual int init(void);
+  //virtual char *cfg_help(t_addr addr);
+  
+  virtual void added_to_uc(void);
+
+  //virtual t_mem read(class cl_memory_cell *cell);
+  virtual void write(class cl_memory_cell *cell, t_mem *val);
+
+  //virtual void mem_cell_changed(class cl_m *mem, t_addr addr);
+
+  virtual int tick(int cycles);
+  virtual void reset(void);
+  virtual void happen(class cl_hw *where, enum hw_event he, void *params);
+
+  virtual void print_info(class cl_console_base *con);
+};
+
+
+#endif
+
+/* End of s51.src/interruptcl.h */
diff --git a/sim/ucsim/s51.src/jmp.cc b/sim/ucsim/s51.src/jmp.cc
new file mode 100644
index 0000000..01849f4
--- /dev/null
+++ b/sim/ucsim/s51.src/jmp.cc
@@ -0,0 +1,576 @@
+/*
+ * Simulator of microcontrollers (jmp.cc)
+ *
+ * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+/* Bugs fixed by Sandeep Dutta:
+ *	relative<->absolute jump in "jmp @a+dptr"
+ */
+
+#include "ddconfig.h"
+
+#include <stdio.h>
+#include <stdlib.h>
+
+// local
+#include "uc51cl.h"
+#include "regs51.h"
+#include "types51.h"
+#include "interruptcl.h"
+
+
+/*
+ * 0x[02468ace]1 2 24 AJMP addr
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_51core::instruction_01/*inst_ajmp_addr*/(t_mem/*uchar*/ code)
+{
+  uchar h, l;
+
+  h= (code >> 5) & 0x07;
+  l= fetch();
+  tick(1);
+  PC= (PC & 0xf800) | (h*256 + l);
+  return(resGO);
+}
+
+
+/*
+ * 0x10 3 12 JBC bit,addr
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_51core::instruction_10/*inst_jbc_bit_addr*/(t_mem/*uchar*/ code)
+{
+  uchar bitaddr, jaddr, b;
+
+  bitaddr= fetch();
+  jaddr  = fetch();
+  //t_addr a;
+  //t_mem m;
+  //class cl_address_space *mem;
+  //if ((mem= bit2mem(bitaddr, &a, &m)) == 0)
+  //return(resBITADDR);
+  //t_mem d= mem->read(a, HW_PORT);
+  //mem->write(a, d & ~m);
+  b= bits->get(bitaddr);
+  vc.rd++;
+  if (/*d & m*/b)
+    {
+      bits->write(bitaddr, 0);
+      PC= rom->validate_address(PC + (signed char)jaddr);
+      vc.wr++;
+    }
+  tick(1);
+  return(resGO);
+}
+
+
+/*
+ * 0x02 3 24 LJMP addr
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_51core::instruction_02/*inst_ljmp*/(t_mem code)
+{
+  PC= fetch()*256 + fetch();
+  tick(1);
+  return(resGO);
+}
+
+/*
+ * 0x[13579bdf]1 2 24 ACALL addr
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_51core::instruction_11/*inst_acall_addr*/(t_mem/*uchar*/ code)
+{
+  uchar h, l;
+  class cl_memory_cell *stck;
+  t_mem sp, sp_before/*, sp_after*/;
+
+  h= (code >> 5) & 0x07;
+  l= fetch();
+  sp_before= sfr->get(SP);
+  sp= sfr->wadd(SP, 1);
+  //proc_write_sp(sp);
+  stck= iram->get_cell(sp);
+  stck->write(PC & 0xff); // push low byte
+  tick(1);
+
+  sp= /*sp_after*= */sfr->wadd(SP, 1);
+  //proc_write_sp(sp);
+  stck= iram->get_cell(sp);
+  stck->write((PC >> 8) & 0xff); // push high byte
+  t_mem pushed= PC;
+  PC= (PC & 0xf800) | (h*256 + l);
+  class cl_stack_op *so= new cl_stack_call(instPC, PC, pushed, sp_before, sp);
+  so->init();
+  stack_write(so);
+  vc.wr+= 2;
+  return(resGO);
+}
+
+
+/*
+ * 0x12 3 24 LCALL addr
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_51core::inst_lcall(t_mem code, uint addr, bool intr)
+{
+  uchar h= 0, l= 0;
+  t_mem sp, sp_before/*, sp_after*/;
+  class cl_memory_cell *stck;
+
+  if (!addr)
+    {
+      h= fetch();
+      l= fetch();
+    }
+  sp_before= sfr->get(SP);
+  sp= sfr->wadd(SP, 1);
+  //proc_write_sp(sp);
+  stck= iram->get_cell(sp);
+  stck->write(PC & 0xff); // push low byte
+  if (!addr)
+    tick(1);
+
+  sp= sfr->wadd(SP, 1);
+  //proc_write_sp(sp);
+  stck= iram->get_cell(sp);
+  stck->write((PC >> 8) & 0xff); // push high byte
+  t_mem pushed= PC;
+  if (addr)
+    PC= addr;
+  else
+    PC= h*256 + l;
+  class cl_stack_op *so;
+  if (intr)
+    so= new cl_stack_intr(instPC, PC, pushed, sp_before, sp/*_after*/);
+  else
+    so= new cl_stack_call(instPC, PC, pushed, sp_before, sp/*_after*/);
+  so->init();
+  stack_write(so);
+  vc.wr+= 2;
+  return(resGO);
+}
+
+
+/*
+ * 0x20 3 24 JB bit,addr
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_51core::instruction_20/*inst_jb_bit_addr*/(t_mem/*uchar*/ code)
+{
+  uchar bitaddr, jaddr, b;
+  //t_addr a;
+  //t_mem m;
+
+  bitaddr= fetch();
+  //class cl_address_space *mem;
+  //if ((mem= bit2mem(bitaddr= fetch(), &a, &m)) == 0)
+  //return(resBITADDR);
+  tick(1);
+  jaddr= fetch();
+  b= bits->read(bitaddr);
+  if (/*mem->read(a) & m*/b)
+    PC= rom->validate_address(PC + (signed char)jaddr);
+  vc.rd++;
+  return(resGO);
+}
+
+
+/*
+ * 0x22 1 24 RET
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_51core::instruction_22/*inst_ret*/(t_mem/*uchar*/ code)
+{
+  uchar h= 0, l= 0;
+  t_mem sp, sp_before/*, sp_after*/;
+  class cl_memory_cell *stck;
+
+  sp= sp_before= sfr->read(SP);
+  stck= iram->get_cell(sp);
+  h= stck->read();
+  sp= sfr->wadd(SP, -1);
+  tick(1);
+
+  stck= iram->get_cell(sp);
+  l= stck->read();
+  sp= sfr->wadd(SP, -1);
+  PC= h*256 + l;
+  class cl_stack_op *so= new cl_stack_ret(instPC, PC, sp_before, sp/*_after*/);
+  so->init();
+  stack_read(so);
+  vc.rd+= 2;
+  return(resGO);
+}
+
+
+/*
+ * 0x30 3 24 JNB bit,addr
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_51core::instruction_30/*inst_jnb_bit_addr*/(t_mem/*uchar*/ code)
+{
+  uchar bitaddr, jaddr, b;
+  //t_mem m;
+  //t_addr a;
+  //class cl_address_space *mem;
+
+  //if ((mem= bit2mem(bitaddr= fetch(), &a, &m)) == 0)
+  //return(resBITADDR);
+  tick(1);
+  bitaddr= fetch();
+  jaddr= fetch();
+  b= bits->read(bitaddr);
+  if (!/*(mem->read(a) & m)*/b)
+    PC= rom->validate_address(PC + (signed char)jaddr);
+  vc.rd++;
+  return(resGO);
+}
+
+
+/*
+ * 0x32 1 24 RETI
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_51core::instruction_32/*inst_reti*/(t_mem/*uchar*/ code)
+{
+  uchar h= 0, l= 0;
+  t_mem sp, sp_before, sp_after;
+  class cl_memory_cell *stck;
+
+  sp= sp_before= sfr->read(SP);
+  stck= iram->get_cell(sp);
+  h= stck->read();
+  sp= sfr->wadd(SP, -1);
+  tick(1);
+
+  stck= iram->get_cell(sp);
+  l= stck->read();
+  sp= sp_after= sfr->wadd(SP, -1);
+  PC= h*256 + l;
+
+  interrupt->was_reti= true;
+  class it_level *il= (class it_level *)(it_levels->top());
+  if (il &&
+      il->level >= 0)
+    {
+      il= (class it_level *)(it_levels->pop());
+      delete il;
+    }
+  class cl_stack_op *so=
+    new cl_stack_iret(instPC, PC, sp_before, sp_after);
+  so->init();
+  stack_read(so);
+  vc.rd+= 2;
+  return(resGO);
+}
+
+
+/*
+ * 0x40 2 24 JC addr
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_51core::instruction_40/*inst_jc_addr*/(t_mem/*uchar*/ code)
+{
+  uchar jaddr;
+
+  jaddr= fetch();
+  tick(1);
+  if (/*SFR_GET_C*/bits->get(0xd7))
+    PC= rom->validate_address(PC + (signed char)jaddr);
+  return(resGO);
+}
+
+
+/*
+ * 0x50 2 24 JNC addr
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_51core::instruction_50/*inst_jnc_addr*/(t_mem/*uchar*/ code)
+{
+  uchar jaddr;
+
+  jaddr= fetch();
+  tick(1);
+  if (!/*SFR_GET_C*/bits->get(0xd7))
+    PC= rom->validate_address(PC + (signed char)jaddr);
+  return(resGO);
+}
+
+
+/*
+ * 0x60 2 24 JZ addr
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_51core::instruction_60/*inst_jz_addr*/(t_mem/*uchar*/ code)
+{
+  uchar jaddr;
+
+  jaddr= fetch();
+  tick(1);
+  if (!acc->read())
+    PC= rom->validate_address(PC + (signed char)jaddr);
+  return(resGO);
+}
+
+
+/*
+ * 0x70 2 24 JNZ addr
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_51core::instruction_70/*inst_jnz_addr*/(t_mem/*uchar*/ code)
+{
+  uchar jaddr;
+
+  jaddr= fetch();
+  tick(1);
+  if (acc->read())
+    PC= rom->validate_address(PC + (signed char)jaddr);
+  return(resGO);
+}
+
+
+/*
+ * 0x73 1 24 JMP @A+DPTR
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_51core::instruction_73/*inst_jmp_Sa_dptr*/(t_mem/*uchar*/ code)
+{
+  u16_t h= /*sfr*/dptr->read(/*DPH*/1);
+  u16_t l= /*sfr*/dptr->read(/*DPL*/0);
+  PC= rom->validate_address(h*256 + l + acc->read());
+  tick(1);
+  vc.rd+= 2;
+  return(resGO);
+}
+
+
+/*
+ * 0x80 2 24 SJMP addr
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_51core::instruction_80/*inst_sjmp*/(t_mem/*uchar*/ code)
+{
+  signed char target= fetch();
+
+  PC= rom->validate_address(PC + target);
+  tick(1);
+  return(resGO);
+}
+
+
+/*
+ * 0xb4 3 24 CJNE A,#data,addr
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_51core::instruction_b4/*inst_cjne_a_Sdata_addr*/(t_mem/*uchar*/ code)
+{
+  uchar data, jaddr, ac;
+
+  data = fetch();
+  jaddr= fetch();
+  tick(1);
+  /*SFR_SET_C(*/bits->set(0xd7, (ac= acc->read()) < data);
+  if (ac != data)
+    PC= rom->validate_address(PC + (signed char)jaddr);
+  vc.rd++;
+  return(resGO);
+}
+
+
+/*
+ * 0xb5 3 24 CJNE A,addr,addr
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_51core::instruction_b5/*inst_cjne_a_addr_addr*/(t_mem/*uchar*/ code)
+{
+  uchar data, jaddr;
+  t_addr a;
+  class cl_memory_cell *cell;
+
+  cell= get_direct(a= fetch());
+  jaddr= fetch();
+  tick(1);
+  data= cell->read();
+  /*SFR_SET_C(*/bits->set(0xd7, acc->get() < data);
+  if (acc->read() != data)
+    PC= rom->validate_address(PC + (signed char)jaddr);
+  vc.rd++;//= 2;
+  return(resGO);
+}
+
+
+/*
+ * 0xb6-0xb7 3 24 CJNE @Ri,#data,addr
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_51core::instruction_b6/*inst_cjne_Sri_Sdata_addr*/(t_mem/*uchar*/ code)
+{
+  uchar data, jaddr;
+  class cl_memory_cell *cell;
+
+  cell= iram->get_cell(R[code & 0x01]->read());
+  data = fetch();
+  jaddr= fetch();
+  tick(1);
+  t_mem d;
+  /*SFR_SET_C(*/bits->set(0xd7, (d= cell->read()) < data);
+  if (d != data)
+    PC= rom->validate_address(PC + (signed char)jaddr);
+  vc.rd++;//= 2;
+  return(resGO);
+}
+
+
+/*
+ * 0xb8-0xbf 3 24 CJNE Rn,#data,addr
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_51core::instruction_b8/*inst_cjne_rn_Sdata_addr*/(t_mem/*uchar*/ code)
+{
+  uchar data, jaddr;
+  class cl_memory_cell *reg;
+
+  reg  = R[code & 0x07];
+  data = fetch();
+  jaddr= fetch();
+  tick(1);
+  t_mem r;
+  /*SFR_SET_C(*/bits->set(0xd7, (r= reg->read()) < data);
+  if (r != data)
+    PC= rom->validate_address(PC + (signed char)jaddr);
+  //vc.rd++;
+  return(resGO);
+}
+
+
+/*
+ * 0xd5 3 24 DJNZ addr,addr
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_51core::instruction_d5/*inst_djnz_addr_addr*/(t_mem/*uchar*/ code)
+{
+  uchar jaddr;
+  class cl_memory_cell *cell;
+
+  cell = get_direct(fetch());
+  jaddr= fetch();
+  tick(1);
+  t_mem d= cell->read(HW_PORT);//cell->wadd(-1);
+  d= cell->write(d-1);
+  if (d)
+    PC= rom->validate_address(PC + (signed char)jaddr);
+  vc.rd++;
+  vc.wr++;
+  return(resGO);
+}
+
+
+/*
+ * 0xd8-0xdf 2 24 DJNZ Rn,addr
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_51core::instruction_d8/*inst_djnz_rn_addr*/(t_mem/*uchar*/ code)
+{
+  uchar jaddr;
+  class cl_memory_cell *reg;
+
+  reg  = R[code & 0x07];
+  jaddr= fetch();
+  tick(1);
+  t_mem r= reg->wadd(-1);
+  if (r)
+    PC= rom->validate_address(PC + (signed char)jaddr);
+  //vc.rd++;
+  //vc.wr++;
+  return(resGO);
+}
+
+
+/* End of s51.src/jmp.cc */
diff --git a/sim/ucsim/s51.src/logic.cc b/sim/ucsim/s51.src/logic.cc
new file mode 100644
index 0000000..afc7cf1
--- /dev/null
+++ b/sim/ucsim/s51.src/logic.cc
@@ -0,0 +1,415 @@
+/*
+ * Simulator of microcontrollers (logic.cc)
+ *
+ * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#include "ddconfig.h"
+
+// prj
+#include "stypes.h"
+
+// local
+#include "uc51cl.h"
+#include "regs51.h"
+
+
+/*
+ * 0x42 2 12 ORL addr,A
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_51core::instruction_42/*inst_orl_addr_a*/(t_mem/*uchar*/ code)
+{
+  class cl_memory_cell *cell;
+
+  cell= get_direct(fetch());
+  cell->write(cell->read(HW_PORT) | acc->read());
+  vc.rd++;//= 2;
+  vc.wr++;
+  return(resGO);
+}
+
+
+/*
+ * 0x43 3 24 ORL addr,#data
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_51core::instruction_43/*inst_orl_addr_Sdata*/(t_mem/*uchar*/ code)
+{
+  class cl_memory_cell *cell;
+  int res= resGO;
+
+  cell= get_direct(fetch());
+  t_mem d= fetch();
+  cell->write(cell->read(HW_PORT) | d);
+  tick(1);
+  vc.rd++;
+  vc.wr++;
+  return(res);
+}
+
+
+/*
+ * 0x44 2 12 ORL A,#data
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_51core::instruction_44/*inst_orl_a_Sdata*/(t_mem/*uchar*/ code)
+{
+  uchar d;
+
+  d= acc->read();
+  acc->write(d|= fetch());
+  //vc.rd++;
+  //vc.wr++;
+  return(resGO);
+}
+
+
+/*
+ * 0x45 2 12 ORL A,addr
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_51core::instruction_45/*inst_orl_a_addr*/(t_mem/*uchar*/ code)
+{
+  t_mem d;
+  class cl_memory_cell *cell;
+
+  cell= get_direct(fetch());
+  d= acc->read();
+  acc->write(d|= cell->read());
+  vc.rd++;//= 2;
+  //vc.wr++;
+  return(resGO);
+}
+
+
+/*
+ * 0x46-0x47 1 12 ORL A,@Ri
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_51core::instruction_46/*inst_orl_a_Sri*/(t_mem/*uchar*/ code)
+{
+  t_mem d;
+  class cl_memory_cell *cell;
+
+  cell= iram->get_cell(R[code & 0x01]->read());
+  d= acc->read();
+  acc->write(d|= cell->read());
+  vc.rd++;//= 3;
+  //vc.wr++;
+  return(resGO);
+}
+
+
+/*
+ * 0x48-0x4f 1 12 ORL A,Rn
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_51core::instruction_48/*inst_orl_a_rn*/(t_mem/*uchar*/ code)
+{
+  t_mem d;
+
+  d= acc->read();
+  acc->write(d|= R[code & 0x07]->read());
+  //vc.rd+= 2;
+  //vc.wr++;
+  return(resGO);
+}
+
+
+/*
+ * 0x52 2 12 ANL addr,A
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_51core::instruction_52/*inst_anl_addr_a*/(t_mem/*uchar*/ code)
+{
+  class cl_memory_cell *cell;
+  
+  cell= get_direct(fetch());
+  cell->write(cell->read(HW_PORT) & acc->read());
+  vc.rd++;//= 2;
+  vc.wr++;
+  return(resGO);
+}
+
+
+/*
+ * 0x53 3 24 ANL addr,#data
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_51core::instruction_53/*inst_anl_addr_Sdata*/(t_mem/*uchar*/ code)
+{
+  class cl_memory_cell *cell;
+  t_mem d;
+
+  cell= get_direct(fetch());
+  d= fetch();
+  cell->write(cell->read(HW_PORT) & d);
+  tick(1);
+  vc.rd++;
+  vc.wr++;
+  return(resGO);
+}
+
+
+/*
+ * 0x54 2 12 ANL A,#data
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_51core::instruction_54/*inst_anl_a_Sdata*/(t_mem/*uchar*/ code)
+{
+  uchar d;
+
+  d= acc->read();
+  acc->write(d & fetch());
+  //vc.rd++;
+  //vc.wr++;
+  return(resGO);
+}
+
+
+/*
+ * 0x55 2 12 ANL A,addr
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_51core::instruction_55/*inst_anl_a_addr*/(t_mem/*uchar*/ code)
+{
+  t_mem d;
+  class cl_memory_cell *cell;
+
+  cell= get_direct(fetch());
+  d= acc->read();
+  acc->write(d & cell->read());
+  vc.rd++;//= 2;
+  //vc.wr++;
+  return(resGO);
+}
+
+
+/*
+ * 0x56-0x57 1 12 ANL A,@Ri
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_51core::instruction_56/*inst_anl_a_Sri*/(t_mem/*uchar*/ code)
+{
+  t_mem d;
+  class cl_memory_cell *cell;
+
+  cell= iram->get_cell(R[code & 0x01]->read());
+  d= acc->read();
+  acc->write(d & cell->read());
+  vc.rd++;//= 3;
+  //vc.wr++;
+  return(resGO);
+}
+
+
+/*
+ * 0x58-0x5f 1 12 ANL A,Rn
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_51core::instruction_58/*inst_anl_a_rn*/(t_mem/*uchar*/ code)
+{
+  uchar d;
+
+  d= acc->read();
+  acc->write(d & R[code & 0x07]->read());
+  //vc.rd+= 2;
+  //vc.wr++;
+  return(resGO);
+}
+
+
+/*
+ * 0x62 2 12 XRL addr,A
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_51core::instruction_62/*inst_xrl_addr_a*/(t_mem/*uchar*/ code)
+{
+  class cl_memory_cell *cell;
+
+  cell= get_direct(fetch());
+  cell->write(cell->read(HW_PORT) ^ acc->read());
+  vc.rd++;//= 2;
+  vc.wr++;
+  return(resGO);
+}
+
+
+/*
+ * 0x63 3 24 XRL addr,#data
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_51core::instruction_63/*inst_xrl_addr_Sdata*/(t_mem/*uchar*/ code)
+{
+  class cl_memory_cell *cell;
+
+  cell= get_direct(fetch());
+  cell->write(cell->read(HW_PORT) ^ fetch());
+  tick(1);
+  vc.rd++;
+  vc.wr++;
+  return(resGO);
+}
+
+
+/*
+ * 0x64 2 12 XRL A,#data
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_51core::instruction_64/*inst_xrl_a_Sdata*/(t_mem/*uchar*/ code)
+{
+  uchar d;
+
+  d= acc->read();
+  acc->write(d ^ fetch());
+  //vc.rd++;
+  //vc.wr++;
+  return(resGO);
+}
+
+
+/*
+ * 0x65 2 12 XRL A,addr
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_51core::instruction_65/*inst_xrl_a_addr*/(t_mem/*uchar*/ code)
+{
+  t_mem d;
+  class cl_memory_cell *cell;
+
+  cell= get_direct(fetch());
+  d= acc->read();
+  acc->write(d ^ cell->read());
+  vc.rd++;//= 2;
+  //vc.wr++;
+  return(resGO);
+}
+
+
+/*
+ * 0x66-0x67 1 12 XRL A,@Ri
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_51core::instruction_66/*inst_xrl_a_Sri*/(t_mem/*uchar*/ code)
+{
+  t_mem d;
+  class cl_memory_cell *cell;
+
+  cell= iram->get_cell(R[code & 0x01]->read());
+  d= acc->read();
+  acc->write(d ^ cell->read());
+  vc.rd++;//= 3;
+  //vc.wr++;
+  return(resGO);
+}
+
+
+/*
+ * 0x68-0x6f 1 12 XRL A,Rn
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_51core::instruction_68/*inst_xrl_a_rn*/(t_mem/*uchar*/ code)
+{
+  t_mem d;
+
+  d= acc->read();
+  acc->write(d ^ R[code & 0x07]->read());
+  //vc.rd+= 2;
+  //vc.wr++;
+  return(resGO);
+}
+
+
+/*
+ * 0xf4 1 12 CPL A
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_51core::instruction_f4/*inst_cpl_a*/(t_mem/*uchar*/ code)
+{
+  acc->write(~(acc->read()));
+  //vc.rd++;
+  //vc.wr++;
+  return(resGO);
+}
+
+
+/* End of s51.src/logic.cc */
diff --git a/sim/ucsim/s51.src/lst2ls b/sim/ucsim/s51.src/lst2ls
new file mode 100755
index 0000000..2bd2752
--- /dev/null
+++ b/sim/ucsim/s51.src/lst2ls
@@ -0,0 +1,23 @@
+FNAME=$1
+
+awk -v FNAME=$FNAME 'BEGIN {
+  cfname= FNAME ".c";
+  i= 1;
+  while (getline csrc[i] <cfname)
+    i++;
+}
+
+$2 == ";" &&
+$3 ^ cfname &&
+NF == 4 {
+  print;
+  print csrc[$4];
+  next;
+}
+
+{
+  print;
+}' ${FNAME}.lst >${FNAME}.ls
+
+# End of lst2ls
+
diff --git a/sim/ucsim/s51.src/mdu.cc b/sim/ucsim/s51.src/mdu.cc
new file mode 100644
index 0000000..ad29f8d
--- /dev/null
+++ b/sim/ucsim/s51.src/mdu.cc
@@ -0,0 +1,656 @@
+/*
+ * Simulator of microcontrollers (s51.src/mdu.cc)
+ *
+ * Copyright (C) 2016,16 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#include "uc51cl.h"
+
+#include "mducl.h"
+
+cl_mdu::cl_mdu(class cl_uc *auc, int aid):
+  cl_hw(auc, HW_CALC, aid, "mdu")
+{
+}
+
+void
+cl_mdu::op_32udiv16(void)
+{
+  u32_t dend= v[3]*256*256*256 + v[2]*256*256 + v[1]*256 + v[0];
+  u16_t dor= v[5]*256 + v[4];
+  u32_t quo= 0;
+  u16_t rem= 0;
+  if (dor == 0)
+    set_ovr(true);
+  else
+    {
+      quo= dend / dor;
+      rem= dend % dor;
+      set_ovr(false);
+      //printf("\nSIM %u/%u=%u,%u %x,%x\n", dend, dor, quo, rem, quo, rem);
+    }
+  regs[0]->set(quo & 0xff);
+  regs[1]->set((quo>>8) & 0xff);
+  regs[2]->set((quo>>16) & 0xff);
+  regs[3]->set((quo>>24) & 0xff);
+  regs[4]->set(rem & 0xff);
+  regs[5]->set((rem>>8) & 0xff);
+  /*{
+    int j;
+    for (j=0;j<6;j++)
+    {
+    printf("  REG[%d]=%02x/%02x %p\n",j,regs[j]->get(),sfr->get(0xe9+j), regs[j]);
+    }
+    }*/
+}
+
+void
+cl_mdu::op_16udiv16(void)
+{
+  // 16/16
+  u16_t dend= v[1]*256 + v[0];
+  u16_t dor= v[5]*256 + v[4];
+  u16_t quo= 0;
+  u16_t rem= 0;
+  if (dor == 0)
+    set_ovr(true);
+  else
+    {
+      quo= dend / dor;
+      rem= dend % dor;
+      set_ovr(false);
+    }
+  regs[0]->set(quo & 0xff);
+  regs[1]->set((quo>>8) & 0xff);
+  regs[4]->set(rem & 0xff);
+  regs[5]->set((rem>>8) & 0xff);
+}
+
+void
+cl_mdu::op_16umul16(void)
+{
+  u16_t mand= v[1]*256 + v[0];
+  u16_t mor= v[5]*256 + v[4];
+  u32_t pr= mand * mor;
+  regs[0]->set(pr & 0xff);
+  regs[1]->set((pr>>8) & 0xff);
+  regs[2]->set((pr>>16) & 0xff);
+  regs[3]->set((pr>>24) & 0xff);
+  if (pr > 0xffff)
+    set_ovr(true);
+  else
+    set_ovr(false);
+  regs[4]->set(v[4]); // behavior of xc88x
+  regs[5]->set(v[5]);
+}
+
+void
+cl_mdu::op_norm(void)
+{
+  u32_t d;
+  
+  d= v[3]*256*256*256 + v[2]*256*256 + v[1]*256 + v[0];
+  if (d == 0)
+    set_steps(0);
+  else if (d & 0x80000000)
+    set_ovr(true);
+  else
+    {
+      int i;
+      for (i= 0; (d&0x80000000)==0; i++)
+	d<<= 1;
+      set_steps(i);
+      //printf("NORM d=%x i=%d\n", d, i);
+    }
+  regs[0]->set(d & 0xff);
+  regs[1]->set((d>>8) & 0xff);
+  regs[2]->set((d>>16) & 0xff);
+  regs[3]->set((d>>24) & 0xff);
+}
+
+/* Logical shift */
+
+void
+cl_mdu::op_lshift(void)
+{
+  u32_t d;
+  
+  d= v[3]*256*256*256 + v[2]*256*256 + v[1]*256 + v[0];
+  if (dir_right())
+    d<<= get_steps();
+  else
+    d>>= get_steps();
+  regs[0]->set(d & 0xff);
+  regs[1]->set((d>>8) & 0xff);
+  regs[2]->set((d>>16) & 0xff);
+  regs[3]->set((d>>24) & 0xff);
+}
+
+
+/*                                                                     517
+ */
+
+cl_mdu517::cl_mdu517(class cl_uc *auc, int aid):
+  cl_mdu(auc, aid)
+{
+}
+
+int
+cl_mdu517::init(void)
+{
+  int i;
+  class cl_51core *u= (cl_51core*)uc;
+
+  cl_hw::init();
+  
+  con= register_cell(u->sfr, 0xef);
+  for (i= 0; i<6; i++)
+    {
+      regs[i]= register_cell(u->sfr, 0xe9+i);
+      v[i]= regs[i]->get();
+    }
+  nuof_writes= 0;
+  writes= 0xffffffffffffULL;
+  //calcing= 0;
+  return 0;
+}
+
+t_mem
+cl_mdu517::read(class cl_memory_cell *cell)
+{
+  cl_address_space *sfr= ((cl_51core*)uc)->sfr;
+  t_addr a;
+  t_mem v= cell->get();
+  
+  if (conf(cell, NULL))
+    return v;
+  if (cell == con)
+    cell->set(v&= ~0x80);
+  else if (sfr->is_owned(cell, &a))
+    {
+      a-= 0xe9;
+      if ((a < 0) ||
+	  (a > 5))
+	return v;
+    }
+  return v;
+}
+
+void
+cl_mdu517::write(class cl_memory_cell *cell, t_mem *val)
+{
+  cl_address_space *sfr= ((cl_51core*)uc)->sfr;
+  t_addr a;
+  u8_t ar= con->get() & ~0x80;
+  
+  if (conf(cell, val))
+    return;
+
+  if (sfr->is_owned(cell, &a))
+    {
+      // if (a==0xee) printf(" WRITE EE %02x\n", *val);
+      a-= 0xe9;
+      if ((a < 0) ||
+	  (a > 6))
+	{
+	  return;
+	}
+      /*if (calcing)
+	{
+	  regs[6]->set(ar | 0x80);
+	  return;
+	  }*/
+      if (a == 0)
+	{
+	  writes= 0xffffffffffffULL;
+	  nuof_writes= 0;
+	  set_err(false);
+	}
+      if (nuof_writes > 5)
+	{
+	  set_err(true);
+	  return;
+	}
+      writes&= ~(0xffL << (nuof_writes*8));
+      writes|= ((u64_t)a << (nuof_writes*8));
+      if (a == 6)
+	{
+	  writes= 0xff0603020100ULL; // force norm/shift
+	  con->set(ar= *val & 0x7f);
+	  set_err(false);
+	}
+      else
+	{
+	  v[a]= *val;
+	  nuof_writes++;
+	}
+      
+      switch (writes)
+	{
+	  //   665544332211
+	case 0x050403020100ULL:
+	  {
+	    // 32/16
+	    op_32udiv16();
+	    //calcing= 6;
+	    writes= 0xffffffffffffULL;
+	    nuof_writes= 0;
+	    break;
+	  }
+	  //   665544332211
+	case 0xffff05040100ULL:
+	  {
+	    op_16udiv16();
+	    //calcing= 6;
+	    writes= 0xffffffffffffULL;
+	    nuof_writes= 0;
+	    break;
+	  }
+	  //   665544332211
+	case 0xffff05010400ULL:
+	  {
+	    // 16*16
+	    op_16umul16();
+	    writes= 0xffffffffffffULL;
+	    nuof_writes= 0;
+	    break;
+	  }
+	  //   665544332211
+	case 0xff0603020100ULL:
+	  {
+	    // norm, shift
+	    if ((ar & 0x1f) == 0)
+	      op_norm();
+	    else
+	      op_lshift();
+	    writes= 0xffffffffffffULL;
+	    nuof_writes= 0;
+	    break;
+	  }
+	default:
+	  if (nuof_writes > 5)
+	    {
+	      set_err(true);
+	      writes= 0xffffffffffffULL;
+	      nuof_writes= 0;
+	    }
+	  break;
+	}
+      if (a < 6)
+	*val= regs[a]->get();
+      else if (cell == con)
+	*val= con->get();
+    }
+}
+
+bool
+cl_mdu517::dir_right(void)
+{
+  return (con->get() & 0x20) != 0;
+}
+
+void
+cl_mdu517::set_steps(int steps)
+{
+  t_mem val= con->get();
+  val&= ~0x1f;
+  steps&= 0x1f;
+  con->set(val | steps);
+}
+
+int
+cl_mdu517::get_steps(void)
+{
+  return con->get() & 0x1f;
+}
+
+void
+cl_mdu517::set_ovr(bool val)
+{
+  if (val)
+    con->set_bit1(0x40);
+  else
+    con->set_bit0(0x40);
+}
+
+void
+cl_mdu517::set_err(bool val)
+{
+  if (val)
+    con->set_bit1(0x80);
+  else
+    con->set_bit0(0x80);
+}
+
+t_mem
+cl_mdu517::conf_op(cl_memory_cell *cell, t_addr addr, t_mem *val)
+{
+  return cell->get();
+}
+
+/*                                                            XC88X
+ */
+
+cl_mdu88x::cl_mdu88x(class cl_uc *auc, int aid):
+  cl_mdu(auc, aid)
+{
+}
+
+int
+cl_mdu88x::init(void)
+{
+  int i;
+  class cl_51core *u= (cl_51core*)uc;
+
+  cl_hw::init();
+  
+  stat= register_cell(u->sfr, 0xb0);
+  con= register_cell(u->sfr, 0xb1);
+  for (i= 0; i<6; i++)
+    {
+      regs[i]= register_cell(u->sfr, 0xb2+i);
+      v[i]= regs[i]->get();
+    }
+  //calcing= 0;
+  return 0;
+}
+
+t_mem
+cl_mdu88x::read(class cl_memory_cell *cell)
+{
+  cl_address_space *sfr= ((cl_51core*)uc)->sfr;
+  t_addr a;
+  t_mem val= cell->get();
+  
+  if (conf(cell, NULL))
+    return val;
+  if (cell == stat)
+    {}
+  else if (cell == con)
+    {}
+  else if (sfr->is_owned(cell, &a))
+    {
+      a-= 0xb2;
+      if ((a < 0) ||
+	  (a > 5))
+	{
+	  if (con->get() & 0x20)
+	    val= regs[a]->get();
+	  else
+	    val= v[a];
+	}
+    }
+  return val;
+}
+
+void
+cl_mdu88x::write(class cl_memory_cell *cell, t_mem *val)
+{
+  cl_address_space *sfr= ((cl_51core*)uc)->sfr;
+  t_addr a;
+  
+  if (conf(cell, val))
+    return;
+
+  if (cell == stat)
+    {}
+  else if (cell == con)
+    {
+      if (((con->get() & 0x10) == 0) &&
+	  (*val & 0x10))
+	{
+	  // START
+	  if (busy())
+	    // skip when already BUSY
+	    return;
+	  con->set(*val&= ~0x10);
+	  set_bsy(true);
+	  switch (*val & 0x0f)
+	    {
+	    case 0:
+	      op_16umul16();
+	      ticks= 16 / uc->clock_per_cycle();
+	      break;
+	    case 1:
+	      op_16udiv16();
+	      ticks= 16 / uc->clock_per_cycle();
+	      break;
+	    case 2:
+	      op_32udiv16();
+	      ticks= 32 / uc->clock_per_cycle();
+	      break;
+	    case 3:
+	      ticks= (get_steps()+1) / uc->clock_per_cycle();
+	      op_lshift();
+	      break;
+	    case 4:
+	      op_16smul16();
+	      ticks= 16 / uc->clock_per_cycle();
+	      break;
+	    case 5:
+	      op_16sdiv16();
+	      ticks= 16 / uc->clock_per_cycle();
+	      break;
+	    case 6:
+	      op_32sdiv16();
+	      ticks= 32 / uc->clock_per_cycle();
+	      break;
+	    case 7:
+	      ticks= (get_steps()+1) / uc->clock_per_cycle();
+	      op_ashift();
+	      break;
+	    case 8:
+	      op_norm();
+	      ticks= (get_steps()+1) / uc->clock_per_cycle();
+	      break;
+	    default:
+	      {
+		// ERROR, unknown opcode
+		set_bsy(false);
+		set_err(true);
+	      }
+	    }
+	}
+    }
+  else if (sfr->is_owned(cell, &a))
+    {
+      a-= 0xb2;
+      if ((a < 0) ||
+	  (a > 5))
+	return;
+      /*if (calcing)
+	{
+	  regs[6]->set(ar | 0x80);
+	  return;
+	  }*/
+      v[a]= *val;
+      if (cell == stat)
+	*val= stat->get();
+      else if (cell == con)
+	*val= con->get();
+      else if (a < 6)
+	*val= regs[a]->get();
+    }
+}
+
+int
+cl_mdu88x::tick(int cycles)
+{
+  if (busy())
+    {
+      ticks-= cycles;
+      if (ticks < 0)
+	ticks= 0;
+      set_bsy(false);
+    }
+  return 0;
+}
+
+
+void
+cl_mdu88x::op_32sdiv16(void)
+{
+  i32_t dend= v[3]*256*256*256 + v[2]*256*256 + v[1]*256 + v[0];
+  i16_t dor= v[5]*256 + v[4];
+  i32_t quo= 0;
+  i16_t rem= 0;
+  if (dor == 0)
+    set_ovr(true);
+  else
+    {
+      quo= dend / dor;
+      rem= dend % dor;
+      set_ovr(false);
+      //printf("\nSIM %d/%d=%d,%d %x,%x\n", dend, dor, quo, rem, quo, rem);
+    }
+  regs[0]->set(quo & 0xff);
+  regs[1]->set((quo>>8) & 0xff);
+  regs[2]->set((quo>>16) & 0xff);
+  regs[3]->set((quo>>24) & 0xff);
+  regs[4]->set(rem & 0xff);
+  regs[5]->set((rem>>8) & 0xff);
+  /*{
+    int j;
+    for (j=0;j<6;j++)
+    {
+    printf("  REG[%d]=%02x/%02x %p\n",j,regs[j]->get(),sfr->get(0xe9+j), regs[j]);
+    }
+    }*/
+}
+
+void
+cl_mdu88x::op_16sdiv16(void)
+{
+  // 16/16
+  i16_t dend= v[1]*256 + v[0];
+  i16_t dor= v[5]*256 + v[4];
+  i16_t quo= 0;
+  i16_t rem= 0;
+  if (dor == 0)
+    set_ovr(true);
+  else
+    {
+      quo= dend / dor;
+      rem= dend % dor;
+      set_ovr(false);
+    }
+  regs[0]->set(quo & 0xff);
+  regs[1]->set((quo>>8) & 0xff);
+  regs[4]->set(rem & 0xff);
+  regs[5]->set((rem>>8) & 0xff);
+}
+
+void
+cl_mdu88x::op_16smul16(void)
+{
+  i16_t mand= v[1]*256 + v[0];
+  i16_t mor= v[5]*256 + v[4];
+  i32_t pr= mand * mor;
+  regs[0]->set(pr & 0xff);
+  regs[1]->set((pr>>8) & 0xff);
+  regs[2]->set((pr>>16) & 0xff);
+  regs[3]->set((pr>>24) & 0xff);
+  if (pr > 0xffff)
+    set_ovr(true);
+  else
+    set_ovr(false);
+  regs[4]->set(v[4]); // behavior of xc88x
+  regs[5]->set(v[5]);
+}
+
+/* Arithmetic shift */
+
+void
+cl_mdu88x::op_ashift(void)
+{
+  i32_t d;
+  
+  d= v[3]*256*256*256 + v[2]*256*256 + v[1]*256 + v[0];
+  if (dir_right())
+    d<<= get_steps();
+  else
+    d>>= get_steps();
+  regs[0]->set(d & 0xff);
+  regs[1]->set((d>>8) & 0xff);
+  regs[2]->set((d>>16) & 0xff);
+  regs[3]->set((d>>24) & 0xff);
+}
+
+
+bool
+cl_mdu88x::dir_right(void)
+{
+  return (v[4] & 0x20) != 0;
+}
+
+void
+cl_mdu88x::set_steps(int steps)
+{
+  regs[4]->set(steps & 0x1f);
+}
+
+int
+cl_mdu88x::get_steps(void)
+{
+  return v[4] & 0x1f;
+}
+
+void
+cl_mdu88x::set_ovr(bool val)
+{
+}
+
+void
+cl_mdu88x::set_err(bool val)
+{
+  if (val)
+    stat->set_bit1(0x02);
+  else
+    stat->set_bit0(0x02);
+}
+
+void
+cl_mdu88x::set_bsy(bool val)
+{
+  if (val)
+    stat->set_bit1(0x04);
+  else
+    stat->set_bit0(0x04);
+}
+
+bool
+cl_mdu88x::busy(void)
+{
+  return (stat->get() & 0x04) != 0;
+}
+
+
+t_mem
+cl_mdu88x::conf_op(cl_memory_cell *cell, t_addr addr, t_mem *val)
+{
+  return cell->get();
+}
+
+
+/* End of s51.src/mdu.cc */
diff --git a/sim/ucsim/s51.src/mducl.h b/sim/ucsim/s51.src/mducl.h
new file mode 100644
index 0000000..f5bad8d
--- /dev/null
+++ b/sim/ucsim/s51.src/mducl.h
@@ -0,0 +1,109 @@
+/*
+ * Simulator of microcontrollers (s51.src/mducl.h)
+ *
+ * Copyright (C) 2016,16 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#ifndef MDUCL_HEADER
+#define MDUCL_HEADER
+
+#include "hwcl.h"
+
+
+class cl_mdu: public cl_hw
+{
+ protected:
+  u8_t v[6]; // values written to MDx data regs
+  class cl_memory_cell *regs[6]; // result (MRx in xc88x)
+  class cl_memory_cell *con; // CONTROL register
+ public:
+  cl_mdu(class cl_uc *auc, int aid);
+
+  virtual void op_32udiv16(void);
+  virtual void op_16udiv16(void);
+  virtual void op_16umul16(void);
+  virtual void op_norm(void);
+  virtual void op_lshift(void);
+  
+  virtual bool dir_right(void) { return false; }
+  virtual void set_steps(int steps) {}
+  virtual int get_steps(void) { return 0; }
+  virtual void set_ovr(bool val) {}
+  virtual void set_err(bool val) {}
+};
+
+class cl_mdu517: public cl_mdu
+{
+ protected:
+  u64_t writes;
+  int nuof_writes;
+  //bool calcing;
+ public:
+  cl_mdu517(class cl_uc *auc, int aid);
+  virtual int init(void);
+  
+  virtual t_mem read(class cl_memory_cell *cell);
+  virtual void write(class cl_memory_cell *cell, t_mem *val);
+  virtual t_mem conf_op(cl_memory_cell *cell, t_addr addr, t_mem *val);
+
+  virtual bool dir_right(void);
+  virtual void set_steps(int steps);
+  virtual int get_steps(void);
+  virtual void set_ovr(bool val);
+  virtual void set_err(bool val);
+};
+
+class cl_mdu88x: public cl_mdu
+{
+ protected:
+  class cl_memory_cell *stat; // STATUS register
+  int ticks; // ticks to count down
+ public:
+  cl_mdu88x(class cl_uc *auc, int aid);
+  virtual int init(void);
+  
+  virtual t_mem read(class cl_memory_cell *cell);
+  virtual void write(class cl_memory_cell *cell, t_mem *val);
+  virtual t_mem conf_op(cl_memory_cell *cell, t_addr addr, t_mem *val);
+
+  virtual int tick(int cycles);
+
+  virtual void op_32sdiv16(void);
+  virtual void op_16sdiv16(void);
+  virtual void op_16smul16(void);
+  virtual void op_ashift(void);
+  
+  virtual bool dir_right(void);
+  virtual void set_steps(int steps);
+  virtual int get_steps(void);
+  virtual void set_ovr(bool val);
+  virtual void set_err(bool val);
+  virtual void set_bsy(bool val);
+  virtual bool busy(void);
+};
+
+
+#endif
+
+/* End of s51.src/mducl.h */
diff --git a/sim/ucsim/s51.src/monitor1-2 b/sim/ucsim/s51.src/monitor1-2
new file mode 100755
index 0000000..1c3685d
--- /dev/null
+++ b/sim/ucsim/s51.src/monitor1-2
@@ -0,0 +1,5 @@
+#!/bin/sh
+
+cat 1_tee|tee /dev/tty >tee_2
+
+# End of monitor1-2
diff --git a/sim/ucsim/s51.src/monitor2-1 b/sim/ucsim/s51.src/monitor2-1
new file mode 100755
index 0000000..07def21
--- /dev/null
+++ b/sim/ucsim/s51.src/monitor2-1
@@ -0,0 +1,5 @@
+#!/bin/sh
+
+cat 2_tee|tee /dev/tty >tee_1
+
+# End of monitor2-1
diff --git a/sim/ucsim/s51.src/mov.cc b/sim/ucsim/s51.src/mov.cc
new file mode 100644
index 0000000..4794f67
--- /dev/null
+++ b/sim/ucsim/s51.src/mov.cc
@@ -0,0 +1,627 @@
+/*
+ * Simulator of microcontrollers (mov.cc)
+ *
+ * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+/* Bugs fixed by Sandeep Dutta:
+ *	source<->dest bug in "mov direct,direct"
+ *	get register in "mov @ri,address"
+ */
+ 
+#include "ddconfig.h"
+
+#include <stdio.h>
+
+// sim
+#include "memcl.h"
+
+// local
+#include "uc51cl.h"
+#include "regs51.h"
+
+
+/*
+ * 0x74 2 12 MOV A,#data
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_51core::instruction_74/*inst_mov_a_Sdata*/(t_mem/*uchar*/ code)
+{
+  acc->write(fetch());
+  //vc.wr++;
+  return(resGO);
+}
+
+
+/*
+ * 0x75 3 24 MOV addr,#data
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_51core::instruction_75/*inst_mov_addr_Sdata*/(t_mem/*uchar*/ code)
+{
+  class cl_memory_cell *cell;
+
+  cell= get_direct(fetch());
+  cell->write(fetch());
+  tick(1);
+  vc.wr++;
+  return(resGO);
+}
+
+
+/*
+ * 0x76-0x77 2 12 MOV @Ri,#data
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_51core::instruction_76/*inst_mov_Sri_Sdata*/(t_mem/*uchar*/ code)
+{
+  class cl_memory_cell *cell;
+  
+  cell= iram->get_cell(R[code & 0x01]->read());
+  t_mem d= fetch();
+  cell->write(d);
+  //vc.rd++;
+  vc.wr++;
+  return(resGO);
+}
+
+
+/*
+ * 0x78-0x7f 2 12 MOV Rn,#data
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_51core::instruction_78/*inst_mov_rn_Sdata*/(t_mem/*uchar*/ code)
+{
+  class cl_memory_cell *reg;
+
+  reg= R[code & 0x07];
+  reg->write(fetch());
+  //vc.wr++;
+  return(resGO);
+}
+
+
+/*
+ * 0x83 1 24 MOVC A,@A+PC
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_51core::instruction_83/*inst_movc_a_Sa_pc*/(t_mem/*uchar*/ code)
+{
+  acc->write(rom->read(PC + acc->read()));
+  tick(1);
+  vc.rd++;
+  //vc.wr++;
+  return(resGO);
+}
+
+
+/*
+ * 0x85 3 24 MOV addr,addr
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_51core::instruction_85/*inst_mov_addr_addr*/(t_mem/*uchar*/ code)
+{
+  class cl_memory_cell *d, *s;
+
+  /* SD reversed s & d here */
+  s= get_direct(fetch());
+  d= get_direct(fetch());
+  d->write(s->read());
+  tick(1);
+  vc.rd++;
+  vc.wr++;
+  return(resGO);
+}
+
+
+/*
+ * 0x86-0x87 2 24 MOV addr,@Ri
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_51core::instruction_86/*inst_mov_addr_Sri*/(t_mem/*uchar*/ code)
+{
+  class cl_memory_cell *d, *s;
+
+  d= get_direct(fetch());
+  s= iram->get_cell(R[code & 0x01]->read());
+  d->write(s->read());
+  tick(1);
+  vc.rd++;//= 2;
+  vc.wr++;
+  return(resGO);
+}
+
+
+/*
+ * 0x88-0x8f 2 24 MOV addr,Rn
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_51core::instruction_88/*inst_mov_addr_rn*/(t_mem/*uchar*/ code)
+{
+  class cl_memory_cell *cell;
+
+  cell= get_direct(fetch());
+  cell->write(R[code & 0x07]->read());
+  tick(1);
+  //vc.rd++;
+  vc.wr++;
+  return(resGO);
+}
+
+
+/*
+ * 0x90 3 24 MOV DPTR,#data
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_51core::instruction_90/*inst_mov_dptr_Sdata*/(t_mem/*uchar*/ code)
+{
+  /*sfr*/dptr->write(/*DPH*/1, fetch());
+  /*sfr*/dptr->write(/*DPL*/0, fetch());
+  tick(1);
+  vc.wr+= 2;
+  return(resGO);
+}
+
+
+/*
+ * 0x93 1 24 MOVC A,@A+DPTR
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_51core::instruction_93/*inst_movc_a_Sa_dptr*/(t_mem/*uchar*/ code)
+{
+  u16_t h= /*sfr*/dptr->read(/*DPH*/1);
+  u16_t l= /*sfr*/dptr->read(/*DPL*/0);
+  acc->write(rom->read(h*256 + l +  acc->read()));
+  tick(1);
+  vc.rd+= 3;//4;
+  //vc.wr++;
+  return(resGO);
+}
+
+
+/*
+ * 0xa6-0xa7 2 24 MOV @Ri,addr
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_51core::instruction_a6/*inst_mov_Sri_addr*/(t_mem/*uchar*/ code)
+{
+  class cl_memory_cell *d, *s;
+
+  d= iram->get_cell(R[code & 0x01]->read());
+  s= get_direct(fetch());
+  d->write(s->read());
+  tick(1);
+  vc.rd++;//= 2;
+  vc.wr++;
+  return(resGO);
+}
+
+
+/*
+ * 0xa8-0xaf 2 24 MOV Rn,addr
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_51core::instruction_a8/*inst_mov_rn_addr*/(t_mem/*uchar*/ code)
+{
+  class cl_memory_cell *reg, *cell;
+
+  reg = R[code & 0x07];
+  cell= get_direct(fetch());
+  reg->write(cell->read());
+  tick(1);
+  vc.rd++;
+  //vc.wr++;
+  return(resGO);
+}
+
+
+/*
+ * 0xc0 2 24 PUSH addr
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_51core::instruction_c0/*inst_push*/(t_mem/*uchar*/ code)
+{
+  t_addr sp, sp_before/*, sp_after*/;
+  t_mem data;
+  class cl_memory_cell *stck, *cell;
+
+  cell= get_direct(fetch());
+  sp_before= sfr->get(SP);
+  sp= /*sp_after= */sfr->wadd(SP, 1);
+  stck= iram->get_cell(sp);
+  stck->write(data= cell->read());
+  class cl_stack_op *so=
+    new cl_stack_push(instPC, data, sp_before, sp/*_after*/);
+  so->init();
+  stack_write(so);
+  tick(1);
+  vc.rd++;
+  vc.wr++;
+  return(resGO);
+}
+
+
+/*
+ * 0xc5 2 12 XCH A,addr
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_51core::instruction_c5/*inst_xch_a_addr*/(t_mem/*uchar*/ code)
+{
+  t_mem temp;
+  class cl_memory_cell *cell;
+
+  cell= get_direct(fetch());
+  temp= acc->read();
+  acc->write(cell->read());
+  cell->write(temp);
+  vc.rd++;
+  vc.wr++;
+  return(resGO);
+}
+
+
+/*
+ * 0xc6-0xc7 1 12 XCH A,@Ri
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_51core::instruction_c6/*inst_xch_a_Sri*/(t_mem/*uchar*/ code)
+{
+  t_mem temp;
+  class cl_memory_cell *cell;
+
+  cell= iram->get_cell(R[code & 0x01]->read());
+  temp= acc->read();
+  acc->write(cell->read());
+  cell->write(temp);
+  vc.rd++;//= 3;
+  vc.wr++;//= 2;
+  return(resGO);
+}
+
+
+/*
+ * 0xc8-0xcf 1 12 XCH A,Rn
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_51core::instruction_c8/*inst_xch_a_rn*/(t_mem/*uchar*/ code)
+{
+  t_mem temp;
+  class cl_memory_cell *reg;
+
+  reg = R[code & 0x07];
+  temp= acc->read();
+  acc->write(reg->read());
+  reg->write(temp);
+  //vc.rd+= 2;
+  //vc.wr+= 2;
+  return(resGO);
+}
+
+
+/*
+ * 0xd0 2 24 POP addr
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_51core::instruction_d0/*inst_pop*/(t_mem/*uchar*/ code)
+{
+  t_addr sp, sp_before/*, sp_after*/;
+  t_mem data;
+  class cl_memory_cell *cell, *stck;
+
+  sp_before= sfr->get(SP);
+  cell= get_direct(fetch());
+  stck= iram->get_cell(/*sfr->get(SP)*/sp_before);
+  /* Order of decrement and write changed to fix POP SP, reported by
+     Alexis Pavlov <alexis.pavlov@certess.com> */
+  sp= sfr->wadd(SP, -1);
+  cell->write(data= stck->read());
+  tick(1);
+  class cl_stack_op *so=
+    new cl_stack_pop(instPC, data, sp_before, sp/*_after*/);
+  so->init();
+  stack_read(so);
+  vc.rd++;
+  vc.wr++;
+  return(resGO);
+}
+
+
+/*
+ * 0xd6-0xd7 1 12 XCHD A,@Ri
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_51core::instruction_d6/*inst_xchd_a_Sri*/(t_mem/*uchar*/ code)
+{
+  t_mem temp, d;
+  class cl_memory_cell *cell;
+
+  cell= iram->get_cell(R[code & 0x01]->read());
+  temp= (d= cell->read()) & 0x0f;
+  cell->write((d & 0xf0) | (acc->read() & 0x0f));
+  acc->write((acc->get() & 0xf0) | temp);
+  vc.rd++;//= 3;
+  vc.wr++;//= 2;
+  return(resGO);
+}
+
+
+/*
+ * 0xe0 1 24 MOVX A,@DPTR
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_51core::instruction_e0/*inst_movx_a_Sdptr*/(t_mem/*uchar*/ code)
+{
+  u16_t h= /*sfr*/dptr->read(/*DPH*/1);
+  u16_t l= /*sfr*/dptr->read(/*DPL*/0);
+  acc->write(xram->read(h*256 + l));
+  tick(1);
+  vc.rd+= 3;
+  //vc.wr++;
+  return(resGO);
+}
+
+
+/*
+ * 0xe2-0xe3 1 24 MOVX A,@Ri
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_51core::instruction_e2/*inst_movx_a_Sri*/(t_mem/*uchar*/ code)
+{
+  t_mem d;
+
+  d= R[code & 0x01]->read();
+  acc->write(xram->read(sfr->read(P2)*256 + d));
+  tick(1);
+  vc.rd++;//= 2;
+  //vc.wr++;
+  return(resGO);
+}
+
+
+/*
+ * 0xe5 2 12 MOV A,addr
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_51core::instruction_e5/*inst_mov_a_addr*/(t_mem/*uchar*/ code)
+{
+  class cl_memory_cell *cell;
+  t_addr address= fetch();
+  
+  /* If this is ACC, it is an invalid instruction */
+  if (address == ACC)
+    {
+      //sim->app->get_commander()->
+      //debug("Invalid Instruction : E5 E0  MOV A,ACC  at  %06x\n", PC);
+      inst_unknown();
+    }
+  else
+    {
+      cell= get_direct(address);
+      acc->write(cell->read());
+      vc.rd++;
+      //vc.wr++;
+    }
+  
+  return(resGO);
+}
+
+
+/*
+ * 0xe6-0xe7 1 12 MOV A,@Ri
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_51core::instruction_e6/*inst_mov_a_Sri*/(t_mem/*uchar*/ code)
+{
+  class cl_memory_cell *cell;
+
+  cell= iram->get_cell(R[code & 0x01]->read());
+  acc->write(cell->read());
+  vc.rd++;//= 2;
+  //vc.wr++;
+  return(resGO);
+}
+
+
+/*
+ * 0xe8-0xef 1 12 MOV A,Rn
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_51core::instruction_e8/*inst_mov_a_rn*/(t_mem/*uchar*/ code)
+{
+  acc->write(R[code & 0x07]->read());
+  //vc.rd++;
+  //vc.wr++;
+  return(resGO);
+}
+
+
+/*
+ * 0xf0 1 24 MOVX @DPTR,A
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_51core::instruction_f0/*inst_movx_Sdptr_a*/(t_mem/*uchar*/ code)
+{
+  u16_t h= /*sfr*/dptr->read(/*DPH*/1);
+  u16_t l= /*sfr*/dptr->read(/*DPL*/0);  
+  xram->write(h*256 + l, acc->read());
+  tick(1);
+  vc.rd+= 2;//3;
+  vc.wr++;
+  return(resGO);
+}
+
+
+/*
+ * 0xf2-0xf3 1 24 MOVX @Ri,A
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_51core::instruction_f2/*inst_movx_Sri_a*/(t_mem/*uchar*/ code)
+{
+  t_mem d, v;
+  t_addr a;
+  
+  d= R[code & 0x01]->read();
+  a= sfr->read(P2)*256 + d;
+  v= acc->read();
+  xram->write(a, v);
+  tick(1);
+  vc.rd++;//= 2;
+  vc.wr++;
+  return(resGO);
+}
+
+
+/*
+ * 0xf5 2 12 MOV addr,A
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_51core::instruction_f5/*inst_mov_addr_a*/(t_mem/*uchar*/ code)
+{
+  class cl_memory_cell *cell;
+  
+  cell= get_direct(fetch());
+  cell->write(acc->read());
+  //vc.rd++;
+  vc.wr++;
+  return(resGO);
+}
+
+
+/*
+ * 0xf6-0xf7 1 12 MOV @Ri,A
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_51core::instruction_f6/*inst_mov_Sri_a*/(t_mem/*uchar*/ code)
+{
+  class cl_memory_cell *cell;
+
+  cell= iram->get_cell(R[code & 0x01]->read());
+  cell->write(acc->read());
+  //vc.rd+= 2;
+  vc.wr++;
+  return(resGO);
+}
+
+
+/*
+ * 0xf8-0xff 1 12 MOV Rn,A
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_51core::instruction_f8/*inst_mov_rn_a*/(t_mem/*uchar*/ code)
+{
+  class cl_memory_cell *reg;
+
+  reg= R[code & 0x07];
+  reg->write(acc->read());
+  //vc.rd++;
+  //vc.wr++;
+  return(resGO);
+}
+
+
+/* End of s51.src/mov.cc */
diff --git a/sim/ucsim/s51.src/pca.cc b/sim/ucsim/s51.src/pca.cc
new file mode 100644
index 0000000..2aa8899
--- /dev/null
+++ b/sim/ucsim/s51.src/pca.cc
@@ -0,0 +1,365 @@
+/*
+ * Simulator of microcontrollers (pca.cc)
+ *
+ * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#include <ctype.h>
+
+// sim.src
+#include "itsrccl.h"
+
+// local
+#include "pcacl.h"
+#include "regs51.h"
+#include "types51.h"
+
+
+cl_pca::cl_pca(class cl_uc *auc, int aid):
+  cl_hw(auc, HW_PCA, aid, "pca")
+{
+  t0_overflows= ECI_edge= 0;
+  int i;
+  for (i= 0; i < 5; cex_pos[i]= cex_neg[i]= false, i++) ;
+}
+
+int
+cl_pca::init(void)
+{
+  cl_hw::init();
+  sfr= uc->address_space(MEM_SFR_ID);
+  //t_addr CCAPL[5]= {CCAPL[0], CCAPL[1], CCAPL[2], CCAPL[3], CCAPL[4]};
+  //t_addr CCAPH[5]= {CCAPH[0], CCAPH[1], CCAPH[2], CCAPH[3], CCAPH[4]};
+  //t_addr CCAPM[5]= {CCAPM[0], CCAPM[1], CCAPM[2], CCAPM[3], CCAPM[4]};
+  t_addr CCAPL[5]= {CCAP0L, CCAP1L, CCAP2L, CCAP3L, CCAP4L};
+  t_addr CCAPH[5]= {CCAP0H, CCAP1H, CCAP2H, CCAP3H, CCAP4H};
+  t_addr CCAPM[5]= {CCAPM0, CCAPM1, CCAPM2, CCAPM3, CCAPM4};
+  int i;
+
+  if (!sfr)
+    {
+      fprintf(stderr, "No SFR to register PCA[%d] into\n", id);
+    }
+  cell_cmod= register_cell(sfr, CMOD);
+  cell_ccon= register_cell(sfr, CCON);
+  for (i= 0; i < 5; i++)
+    {
+      cell_ccapl[i]= sfr->get_cell(CCAPL[i]);//use_cell(sfr, CCAPL[i]);
+      cell_ccaph[i]= sfr->get_cell(CCAPH[i]);//use_cell(sfr, CCAPH[i]);
+      cell_ccapm[i]= register_cell(sfr, CCAPM[i]);
+    }
+  cell_cl= sfr->get_cell(CL);//use_cell(sfr, CL);
+  cell_ch= sfr->get_cell(CH);//use_cell(sfr, CH);
+  cl_address_space *bas= uc->address_space("bits");
+  cell_cr= register_cell(bas, 0xda);
+  return(0);
+}
+
+void
+cl_pca::added_to_uc(void)
+{
+  class cl_address_space *sfr= uc->address_space(MEM_SFR_ID);
+  class cl_it_src *is;
+  
+  uc->it_sources->add_at(4, is= new cl_it_src(uc, bmEC,
+					      sfr->get_cell(IE), bmEC,
+					      sfr->get_cell(CCON), bmCCF4,
+					      0x0033, false, false,
+					      "PCA module #4", 5));
+  is->init();
+  uc->it_sources->add_at(4, is= new cl_it_src(uc, bmEC,
+					      sfr->get_cell(IE), bmEC,
+					      sfr->get_cell(CCON), bmCCF3,
+					      0x0033, false, false,
+					      "PCA module #3", 5));
+  is->init();
+  uc->it_sources->add_at(4, is= new cl_it_src(uc, bmEC,
+					      sfr->get_cell(IE), bmEC,
+					      sfr->get_cell(CCON), bmCCF2,
+					      0x0033, false, false,
+					      "PCA module #2", 5));
+  is->init();
+  uc->it_sources->add_at(4, is= new cl_it_src(uc, bmEC,
+					      sfr->get_cell(IE), bmEC,
+					      sfr->get_cell(CCON), bmCCF1,
+					      0x0033, false, false,
+					      "PCA module #1", 5));
+  is->init();
+  uc->it_sources->add_at(4, is= new cl_it_src(uc, bmEC,
+					      sfr->get_cell(IE), bmEC,
+					      sfr->get_cell(CCON), bmCCF0,
+					      0x0033, false, false,
+					      "PCA module #0", 5));
+  is->init();
+  uc->it_sources->add_at(4, is= new cl_it_src(uc, bmEC,
+					      sfr->get_cell(IE), bmEC,
+					      sfr->get_cell(CCON), bmCF,
+					      0x0033, false, false,
+					      "PCA counter", 5));
+  is->init();
+}
+
+void
+cl_pca::write(class cl_memory_cell *cell, t_mem *val)
+{
+  //uchar bmCEX[5]= {bmCEX0, bmCEX1, bmCEX2, bmCEX3, bmCEX4};
+  //uchar bmCCF[5]= {bmCCF0, bmCCF1, bmCCF2, bmCCF3, bmCCF4};
+
+  if (cell == cell_cmod)
+    {
+      bit_CIDL= *val & bmCIDL;
+      bit_WDTE= *val & bmWDTE;
+      bit_ECF = *val & bmECF;
+      t_mem o= clk_source;
+      if ((clk_source= *val & (bmCPS1|bmCPS0)) != o)
+	t0_overflows= ECI_edge= 0;
+    }
+  else if (cell == cell_ccon)
+    {
+      bit_CR= *val & bmCR;
+    }
+  else if (cell == cell_cr)
+    {
+      bit_CR= *val;
+    }
+  else
+    {
+      int i;
+      for (i= 0; i < 5; i++)
+	{
+	  if (cell == cell_ccapm[i])
+	    {
+	      t_mem o= ccapm[i];
+	      ccapm[i]= *val & 0xff;
+	      if (o != ccapm[i])
+		cex_neg[i]= cex_pos[i]= false;
+	    }
+	  else
+	    {
+	      if (ccapm[i] & (bmMAT|bmTOG))
+	      {
+		if (cell == cell_ccapl[i])
+		  {
+		    cell_ccapm[i]->set_bit0(bmECOM);
+		    ccapm[i]= cell_ccapm[i]->get();
+		  }
+		else if (cell == cell_ccaph[i])
+		  {
+		    cell_ccapm[i]->set_bit1(bmECOM);
+		    ccapm[i]= cell_ccapm[i]->get();
+		  }
+	      }
+	    }
+	}
+    }
+}
+
+/*void
+cl_pca::mem_cell_changed(class cl_m *mem, t_addr addr)
+{
+  class cl_m *sfr= uc->mem(MEM_SFR);
+
+  if (mem && sfr && mem == sfr)
+    {
+      if (addr == addr_ccapXl)
+	ccapXl= sfr->get_cell(addr_ccapXl);
+      else if (addr == addr_ccapXh)
+	ccapXh= sfr->get_cell(addr_ccapXh);
+      else if (addr == addr_ccapmX)
+	ccapmX= sfr->get_cell(addr_ccapmX);
+    }
+}*/
+
+int
+cl_pca::tick(int cycles)
+{
+  int ret= resGO;
+
+  if (!bit_CR)
+    return(resGO);
+  if (uc->state == stIDLE &&
+      bit_CIDL)
+    return(resGO);
+
+  switch (clk_source)
+    {
+    case 0:
+      do_pca_counter(cycles);
+      break;
+    case bmCPS0:
+      do_pca_counter(cycles*3);
+      break;
+    case bmCPS1:
+      do_pca_counter(t0_overflows);
+      t0_overflows= 0;
+      break;
+    case (bmCPS0|bmCPS1):
+      do_pca_counter(ECI_edge);
+      ECI_edge= 0;
+      break;
+    }
+  return(ret);
+}
+
+void
+cl_pca::do_pca_counter(int cycles)
+{
+  //class cl_m *sfr= uc->mem(MEM_SFR);
+
+  while (cycles--)
+    {
+      if (cell_cl->add(1) == 0)
+	{
+	  int i;
+	  for (i= 0; i < 5; i++)
+	    if (ccapm[i] & bmPWM)
+	      cell_ccapl[i]->set(cell_ccaph[i]->get());
+	  if (cell_ch->add(1) == 0)
+	    {
+	      // CH,CL overflow
+	      cell_ccon->set_bit1(bmCF);
+	      do_pca_module(0);
+	      do_pca_module(1);
+	      do_pca_module(2);
+	      do_pca_module(3);
+	      do_pca_module(4);
+	    }
+	}
+    }
+}
+
+void
+cl_pca::do_pca_module(int nr)
+{
+  uchar bmCEX[5]= {bmCEX0, bmCEX1, bmCEX2, bmCEX3, bmCEX4};
+  uchar bmCCF[5]= {bmCCF0, bmCCF1, bmCCF2, bmCCF3, bmCCF4};
+  //uint p1= sfr->get(P1);
+
+  bool capture= false;
+  if ((ccapm[nr] & bmCAPP) &&
+      cex_pos[nr])
+    {
+      capture= true;
+      cex_pos[nr]= false;
+    }
+  if ((ccapm[nr] & bmCAPN) &&
+      cex_neg[nr])
+    {
+      capture= true;
+      cex_pos[nr]= false;
+    }
+  if (capture)
+    {
+      // Capture
+      cell_ccapl[nr]->set(cell_cl->get());
+      cell_ccaph[nr]->set(cell_ch->get());
+      cell_ccon->set_bit1(bmCCF[nr]);
+    }
+
+  if (ccapm[nr] & bmECOM)
+    {
+      // Comparator enabled
+      if (cell_cl->get() == cell_ccapl[nr]->get() &&
+	  cell_ch->get() == cell_ccaph[nr]->get())
+	{
+	  // Match
+	  if (nr == 4 &&
+	      (bit_WDTE))
+	    {
+	      reset();
+	      return;
+	    }
+	  cell_ccon->set_bit1(bmCCF[nr]);
+	  if (ccapm[nr] & bmTOG)
+	    {
+	      // Toggle
+	      sfr->set(P1, sfr->get(P1) ^ bmCEX[nr]);
+	    }
+	}
+      if (ccapm[nr] & bmPWM)
+	{
+	  // PWM
+	  /*if (cell_cl->get() == 0)
+	    cell_ccapl[nr]->set(cell_ccaph[nr]->get());*/
+	  if (cell_cl->get() < cell_ccapl[nr]->get())
+	    //sfr->set(P1, sfr->get(P1) & ~(bmCEX[nr]));
+	    sfr->set_bit1(P1, bmCEX[nr]);
+	  else
+	    sfr->set_bit1(P1, bmCEX[nr]);
+	}
+    }
+}
+
+void
+cl_pca::reset(void)
+{
+  t0_overflows= ECI_edge= 0;
+  int i;
+  for (i= 0; i < 5; cex_pos[i]= cex_neg[i]= false, i++) ;
+}
+
+void
+cl_pca::happen(class cl_hw *where, enum hw_event he, void *params)
+{
+  struct ev_port_changed *ep= (struct ev_port_changed *)params;
+  uchar bmCEX[5]= {bmCEX0, bmCEX1, bmCEX2, bmCEX3, bmCEX4};
+
+  if (where->cathegory == HW_PORT &&
+      he == EV_PORT_CHANGED &&
+      ep->id == 1)
+    {
+      t_mem p1n= ep->new_pins & ep->new_value;
+      t_mem p1o= ep->pins & ep->prev_value;
+      if (!(p1n & bmECI) &&
+	  (p1o & bmECI))
+	ECI_edge++;
+      int i;
+      for (i= 0; i < 5; i++)
+	{
+	  if (!(p1n & bmCEX[i]) &&
+	      (p1o & bmCEX[i]))
+	    cex_neg[i]= true;
+	  else if ((p1n & bmCEX[i]) &&
+		   !(p1o & bmCEX[i]))
+	    cex_pos[i]= true;
+	}
+    }
+  else if (where->cathegory == HW_TIMER &&
+	   he == EV_OVERFLOW &&
+	   where->id == 0)
+    {
+      t0_overflows++;
+    }
+}
+
+
+void
+cl_pca::print_info(class cl_console_base *con)
+{
+  con->dd_printf("%s[%d] FIXME\n", id_string, id);
+  print_cfg_info(con);
+}
+
+
+/* End of s51.src/pca.cc */
diff --git a/sim/ucsim/s51.src/pcacl.h b/sim/ucsim/s51.src/pcacl.h
new file mode 100644
index 0000000..808b5d5
--- /dev/null
+++ b/sim/ucsim/s51.src/pcacl.h
@@ -0,0 +1,77 @@
+/*
+ * Simulator of microcontrollers (pcacl.h)
+ *
+ * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#ifndef PORTCL_HEADER
+#define PORTCL_HEADER
+
+// sim.src
+//#include "stypes.h"
+//#include "pobjcl.h"
+#include "uccl.h"
+
+// local
+//#include "newcmdcl.h"
+
+
+class cl_pca: public cl_hw
+{
+public:
+  class cl_address_space *sfr;
+  class cl_memory_cell *cell_cl, *cell_ch;
+  class cl_memory_cell *cell_ccapl[5], *cell_ccaph[5], *cell_ccapm[5];
+  t_mem ccapm[5];
+  class cl_memory_cell *cell_cmod, *cell_ccon, *cell_cr;
+  long t0_overflows, ECI_edge;
+  t_mem clk_source;
+  bool bit_CIDL, bit_WDTE, bit_ECF, bit_CR;
+  bool cex_pos[5], cex_neg[5];
+public:
+  cl_pca(class cl_uc *auc, int aid);
+  virtual int init(void);
+  //virtual char *cfg_help(t_addr addr);
+  
+  virtual void added_to_uc(void);
+
+  //virtual t_mem read(class cl_memory_cell *cell);
+  virtual void write(class cl_memory_cell *cell, t_mem *val);
+
+  //virtual t_mem set_cmd(t_mem value);
+  //virtual void mem_cell_changed(class cl_m *mem, t_addr addr);
+ 
+  virtual int tick(int cycles);
+  virtual void do_pca_counter(int cycles);
+  virtual void do_pca_module(int nr);
+  virtual void reset(void);
+  virtual void happen(class cl_hw *where, enum hw_event he, void *params);
+ 
+  virtual void print_info(class cl_console_base *con);
+};
+
+
+#endif
+
+/* End of s51.src/pcacl.h */
diff --git a/sim/ucsim/s51.src/port.cc b/sim/ucsim/s51.src/port.cc
new file mode 100644
index 0000000..4e5f41e
--- /dev/null
+++ b/sim/ucsim/s51.src/port.cc
@@ -0,0 +1,299 @@
+/*
+ * Simulator of microcontrollers (port.cc)
+ *
+ * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#include <ctype.h>
+
+// cmd
+#include "argcl.h"
+
+// local
+#include "regs51.h"
+#include "types51.h"
+
+#include "portcl.h"
+
+
+cl_port::cl_port(class cl_uc *auc, int aid):
+  cl_hw(auc, HW_PORT, aid, "port")
+{
+  port_pins= 0xff;
+}
+
+cl_port::cl_port(class cl_uc *auc, int aid, t_addr the_addr):
+  cl_hw(auc, HW_PORT, aid, "port")
+{
+  port_pins= 0xff;
+  addr_p= the_addr;
+}
+
+int
+cl_port::init(void)
+{
+  cl_hw::init();
+  switch (id)
+    {
+    case 0: addr_p= P0; break;
+    case 1:
+      {
+	addr_p= P1;
+	/*class cl_hw *hw;
+	if ((hw= uc->get_hw(HW_TIMER, 2, 0)))
+	hws_to_inform->add(hw);*/
+	make_partner(HW_TIMER, 2);
+	make_partner(HW_PCA, 0);
+	break;
+      }
+    case 2: addr_p= P2; break;
+    case 3:
+      {
+	addr_p= P3;
+	//class cl_hw *hw;
+	/*if ((hw= uc->get_hw(HW_TIMER, 0, 0)))
+	  hws_to_inform->add(hw);
+	if ((hw= uc->get_hw(HW_TIMER, 1, 0)))
+	  hws_to_inform->add(hw);
+	if ((hw= uc->get_hw(HW_DUMMY, 0, 0)))
+	hws_to_inform->add(hw);*/
+	make_partner(HW_TIMER, 0);
+	make_partner(HW_TIMER, 1);
+	make_partner(HW_INTERRUPT, 0);
+	make_partner(HW_DUMMY, 0);
+	break;
+      }
+    default: break;//addr_p= P0; return(1);
+    }
+  class cl_address_space *sfr= uc->address_space(MEM_SFR_ID);
+  bas= uc->address_space("bits");
+  if (!sfr)
+    {
+      fprintf(stderr, "No SFR to register port into\n");
+    }
+  cell_p= register_cell(sfr, addr_p);
+  if ((addr_p % 8) == 0)
+    {
+      int i;
+      for (i= 0; i < 8; i++)
+	bit_cells[i]= register_cell(bas, addr_p+i);
+    }
+  prev= cell_p->get();
+  cell_in= cfg->get_cell(port_pin);
+  cfg->set(port_value, prev & cell_in->get());
+  
+  cl_var *v;
+  chars pn;
+  pn= cchars("port");
+  pn.append("%d_", id);
+  uc->vars->add(v= new cl_var(pn+chars("on"), cfg, port_on,
+			      cfg_help(port_on)));
+  v->init();
+  uc->vars->add(v= new cl_var(pn+chars("pin"), cfg, port_pin,
+			      cfg_help(port_pin)));
+  v->init();
+  uc->vars->add(v= new cl_var(pn+chars("pins"), cfg, port_pin,
+			      cfg_help(port_pin)));
+  v->init();
+  uc->vars->add(v= new cl_var(pn+chars("value"), cfg, port_value,
+			      cfg_help(port_value)));
+  v->init();
+  chars p= chars("pin");
+  p.append("%d", id);
+  uc->vars->add(v= new cl_var(p, cfg, port_pin,
+			      cfg_help(port_pin)));
+  v->init();
+  p= chars("pins");
+  p.append("%d", id);
+  uc->vars->add(v= new cl_var(p, cfg, port_pin,
+			      cfg_help(port_pin)));
+  v->init();
+  
+  return(0);
+}
+
+char *
+cl_port::cfg_help(t_addr addr)
+{
+  switch (addr)
+    {
+    case port_on: return (char*)"Turn/get on/off state (bool, RW)";
+    case port_pin: return (char*)"Outside value of port pins (int, RW)";
+    case port_value: return (char*)"Value of the port (int, RO)";
+    }
+  return (char*)"Not used";
+}
+
+t_mem
+cl_port::read(class cl_memory_cell *cell)
+{
+  if (cell == cell_p)
+    return(cell->get() & port_pins);
+  t_addr ba;
+  if (bas->is_owned(cell, &ba))
+    {
+      int bi= ba - addr_p;
+      bool cv= cell->get();
+      bool pv= port_pins & (1 << bi);
+      return (cv && pv)?1:0;
+    }
+  conf(cell, NULL);
+  return cell->get();
+}
+
+void
+cl_port::write(class cl_memory_cell *cell, t_mem *val)
+{
+  struct ev_port_changed ep;
+  u8_t nv= *val;
+  t_addr ba;
+  
+  if (cell == cell_p)
+    {
+      (*val)&= 0xff; // 8 bit port
+      nv= *val;
+      if ((port_pins & nv) != cfg->get(port_value))
+	cfg->write(port_value, port_pins & nv);
+    }
+  
+  if (bas->is_owned(cell, &ba))
+    {
+      int bi= ba - addr_p;
+      int m= 1 << bi;
+      nv= cell_p->get();
+      if (*val)
+	nv|= m;
+      else
+	nv&= ~m;
+      if ((port_pins & nv) != cfg->get(port_value))
+	cfg->write(port_value, port_pins & nv);
+    }
+
+  conf(cell, val);
+  
+  ep.id= id;
+  ep.addr= addr_p;
+  ep.prev_value= cell_p->get();
+  ep.new_value= nv;
+  ep.pins= ep.new_pins= port_pins;
+  if (ep.prev_value != ep.new_value)
+    inform_partners(EV_PORT_CHANGED, &ep);
+  prev= cell_p->get();
+}
+
+t_mem
+cl_port::conf_op(cl_memory_cell *cell, t_addr addr, t_mem *val)
+{
+  switch ((enum port_cfg)addr)
+    {
+    case port_on: // turn this HW on/off
+      if (val)
+	{
+	  if (*val)
+	    on= true;
+	  else
+	    on= false;
+	}
+      else
+	{
+	  cell->set(on?1:0);
+	}
+      break;
+    case port_pin: // get/set PINS
+      if (val)
+	set_pin(*val);
+      else
+	cell->set(port_pins);
+      break;
+    case port_value:
+      if (val)
+	*val= cell->get();//cell->set(*val);
+      break;
+    }
+  return cell->get();
+}
+
+void
+cl_port::set_pin(t_mem val)
+{
+  struct ev_port_changed ep;
+  t_mem value= val & 0xff;
+
+  ep.id= id;
+  ep.addr= addr_p;
+  ep.pins= port_pins;
+  port_pins= value;
+  ep.prev_value= cell_p->get();
+  ep.new_value= cell_p->get();
+  ep.new_pins= port_pins;
+  if (ep.pins != ep.new_pins)
+    inform_partners(EV_PORT_CHANGED, &ep);
+  if ((port_pins & ep.prev_value) != cfg->get(port_value))
+    cfg->write(port_value, port_pins & ep.prev_value);
+}
+
+void
+cl_port::set_cmd(class cl_cmdline *cmdline, class cl_console_base *con)
+{
+  class cl_cmd_arg *params[1]= { cmdline->param(0) };
+
+  if (cmdline->syntax_match(uc, NUMBER))
+    {
+      set_pin(params[0]->value.number);
+    }
+  else
+    {
+      con->dd_printf("set hardware port[%d] pins_value\n                   Set port pins\n",
+		     id);
+    }
+}
+
+void
+cl_port::print_info(class cl_console_base *con)
+{
+  uchar data;
+
+  con->dd_printf("%s[%d]\n", id_string, id);
+  data= cell_p->get();
+  con->dd_printf("P%d    ", id);
+  con->print_bin(data, 8);
+  con->dd_printf(" 0x%02x %3d %c (Value in SFR register)\n",
+		 data, data, isprint(data)?data:'.');
+
+  data= /*uc->*/port_pins/*[id]*/;
+  con->dd_printf("Pin%d  ", id);
+  con->print_bin(data, 8);
+  con->dd_printf(" 0x%02x %3d %c (Output of outside circuits)\n",
+		 data, data, isprint(data)?data:'.');
+
+  data= cell_p->read();
+  con->dd_printf("Port%d ", id);
+  con->print_bin(data, 8);
+  con->dd_printf(" 0x%02x %3d %c (Value on the port pins)\n",
+		 data, data, isprint(data)?data:'.');
+  print_cfg_info(con);
+}
+
+
+/* End of s51.src/port.cc */
diff --git a/sim/ucsim/s51.src/portcl.h b/sim/ucsim/s51.src/portcl.h
new file mode 100644
index 0000000..ad2daa8
--- /dev/null
+++ b/sim/ucsim/s51.src/portcl.h
@@ -0,0 +1,78 @@
+/*
+ * Simulator of microcontrollers (portcl.h)
+ *
+ * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#ifndef PORTCL_HEADER
+#define PORTCL_HEADER
+
+#include "stypes.h"
+#include "pobjcl.h"
+#include "uccl.h"
+
+#include "newcmdcl.h"
+
+#include "port_hwcl.h"
+
+
+enum port_cfg {
+  port_on		= 0, // RW
+  port_pin		= 1, // RW
+  port_value		= 2, // RO
+};
+
+class cl_port: public cl_hw
+{
+public:
+  t_addr addr_p;
+  t_mem port_pins;
+  t_mem prev;
+  class cl_address_space *bas;
+  class cl_memory_cell *cell_p, *cell_in, *bit_cells[8];
+public:
+  cl_port(class cl_uc *auc, int aid);
+  cl_port(class cl_uc *auc, int aid, t_addr the_addr);
+  virtual int init(void);
+  virtual int cfg_size(void) { return 3; }
+  virtual char *cfg_help(t_addr addr);
+  
+  virtual t_mem read(class cl_memory_cell *cell);
+  virtual void write(class cl_memory_cell *cell, t_mem *val);
+  virtual t_mem conf_op(cl_memory_cell *cell, t_addr addr, t_mem *val);
+
+  virtual void set_pin(t_mem val);
+    
+  virtual void set_cmd(class cl_cmdline *cmdline, class cl_console_base *con);
+  //virtual void mem_cell_changed(class cl_m *mem, t_addr addr);
+
+  virtual void make_io(void) {}
+  //virtual int tick(int cycles);
+  virtual void print_info(class cl_console_base *con);
+};
+
+
+#endif
+
+/* End of s51.src/portcl.h */
diff --git a/sim/ucsim/s51.src/regs51.h b/sim/ucsim/s51.src/regs51.h
new file mode 100644
index 0000000..5f6c8aa
--- /dev/null
+++ b/sim/ucsim/s51.src/regs51.h
@@ -0,0 +1,349 @@
+/*
+ * Simulator of microcontrollers (regs51.h)
+ *
+ * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#ifndef REGS51_HEADER
+#define REGS51_HEADER
+
+
+/* Address of SFR registers */
+
+#define ACC	0xe0 /* Accumulator */
+#define B	0xf0 /* B register (scondary accumulator) */
+#define PSW	0xd0 /* Program Status Word */
+#define SP	0x81 /* Stack Pointer */
+#define DPL	0x82 /* Data Pointer Low byte */
+#define DPH	0x83 /* Data Pointer High byte */
+#define DPL1	0x84 /* 2nd Data Pointer Low byte */
+#define DPH1	0x85 /* 2nd Data Pointer High byte */
+#define DPS	0x86 /* DPS 1H=DPTR is DPL1/DPH1, 2H=AUTO DPTR INCR */
+#define P0	0x80 /* Port #0 */
+#define P1	0x90 /* Port #1 */
+#define P2	0xa0 /* Port #2 */
+#define P3	0xb0 /* Port #3 */
+#define IP	0xb8 /* Intrrupt Priority */
+#define IE	0xa8 /* Interrupt Enable */
+#define TMOD	0x89 /* Timer MODe */
+#define TCON	0x88 /* Timer CONtrol */
+#define T2CON	0xc8 /* Timer #2 CONtrol */
+#define TH0	0x8c /* Timer #0 High byte */
+#define TL0	0x8a /* Timer #0 Low byte */
+#define TH1	0x8d /* Timer #1 High byte */
+#define TL1	0x8b /* Timer #1 Low byte */
+#define SCON	0x98 /* Serial line CONtrol */
+#define TH2	0xcd /* Timer #2 High byte */
+#define TL2	0xcc /* Timer #2 Low byte */
+#define RCAP2H	0xcb /* Capture Register of Timer #2 High byte */
+#define RCAP2L	0xca /* Capture Register of Timer #2 Low byte */
+#define SBUF	0x99 /* Serial line BUFfer */
+#define PCON	0x87 /* Power CONtrol */
+
+#define AUXR	0x8e /* Auxiliary Register */
+#define AUXR1	0xa2 /* Secondary Aux Register */
+
+#define P4      0x80
+#define DPXL	0x84 /* */
+//#define DPL1	0x84 /* 2nd Data Pointer Low byte */
+//#define DPH1	0x85 /* 2nd Data Pointer High byte */
+#define DPS	0x86 /* DPS 1H=DPTR is DPL1/DPH1,... */
+#define CKCON 0x8E /* Clock Control */
+#define EXIF    0x91 /* */
+#define P4CNT   0x92 /* */
+#define DPX     0x93 /* Data Pointer HHigh byte */
+#define DPX1    0x95 /* Data Pointer HHigh byte */
+#define R51_ESP     0x9b /* Extended Stack Pointer */
+#define AP      0x9c /* Address Page */
+#define ACON    0x9d /* */
+#define P5      0xa1
+#define P5CNT   0xa2 /* */
+#define C0C     0xa3 /* */
+#define WDTRST	0xa6 /* */
+#define IE0	0xa8 /* */
+#define SADDR	0xa9 /* */
+#define IPH0	0xb7 /* */
+#define IPH	0xb7
+#define IPL0	0xb8 /* */
+#define SADEN	0xb9 /* */
+#define SPH	0xbd /* */
+#define PMR	0xc4 /* */
+#define MCON    0xc6 /* */
+#define TA      0xc7 /* */
+#define T2MOD	0xc9 /* */
+#define COR     0xce /* */
+#define PSW1	0xd1 /* */
+#define MCNT0   0xd1
+#define MCNT1   0xd2
+#define MA      0xd3 /* MA register from math accelerator */
+#define MB      0xd4 /* MB register from math accelerator */
+#define MC      0xd5 /* MC register from math accelerator */
+#define CCON	0xd8 /* */
+#define CMOD	0xd9 /* */
+#define WDCON	0xd8 /* */
+#define CCAPM0	0xda /* */
+#define CCAPM1	0xdb /* */
+#define CCAPM2	0xdc /* */
+#define CCAPM3	0xdd /* */
+#define CCAPM4	0xde /* */
+#define C1C     0xe3 /* */
+#define CL	0xe9 /* */
+#define CCAP0L	0xea /* */
+#define CCAP1L	0xeb /* */
+#define CCAP2L	0xec /* */
+#define CCAP3L	0xed /* */
+#define CCAP4L	0xee /* */
+#define CH	0xf9 /* */
+#define CCAP0H	0xfa /* */
+#define CCAP1H	0xfb /* */
+#define CCAP2H	0xfc /* */
+#define CCAP3H	0xfd /* */
+#define CCAP4H	0xfe /* */
+
+/* Bit masks of flag bits in PSW (0xd0)*/
+
+#define bmCY	0x80 /* carry */
+#define bmAC	0x40 /* acarry */
+#define bmF0	0x20 /* flag 0 */
+#define bmRS1	0x10 /* register select 1 */
+#define bmRS0	0x08 /* register select 0 */
+#define bmOV	0x04 /* arithmetic overflow */
+#define bmP	0x01 /* parity, set by hardware */
+
+/* Bit masks in PCON (0x87) */
+
+#define bmSMOD1	0x80
+#define bmSMOD	0x80
+#define bmSMOD0	0x40
+#define bmPOF	0x10
+#define bmGF1	0x08
+#define bmGF0	0x04
+#define bmPD	0x02
+#define bmIDL	0x01
+
+/* Bit masks in IE (0xa8) */
+
+#define bmEA	0x80
+#define bmEC	0x40
+#define bmET2	0x20
+#define bmES	0x10
+#define bmET1	0x08
+#define bmEX1	0x04
+#define bmET0	0x02
+#define bmEX0	0x01
+
+/* Bit masks in IP (0xb8) */
+
+#define bmPPC	0x40
+#define bmPT2	0x20
+#define bmPS	0x10
+#define bmPT1	0x08
+#define bmPX1	0x04
+#define bmPT0	0x02
+#define bmPX0	0x01
+
+/* Bit masks in IPL0 (0xb8) */
+
+#define bmIPL0_6 0x40
+#define bmIPL0_5 0x20
+#define bmIPL0_4 0x10
+#define bmIPL0_3 0x08
+#define bmIPL0_2 0x04
+#define bmIPL0_1 0x02
+#define bmIPL0_0 0x01
+
+/* Bit masks in IPH0 (0xb7) */
+
+#define bmIPH0_6 0x40
+#define bmIPH0_5 0x20
+#define bmIPH0_4 0x10
+#define bmIPH0_3 0x08
+#define bmIPH0_2 0x04
+#define bmIPH0_1 0x02
+#define bmIPH0_0 0x01
+
+/* Bit masks in P1 (0x90) */
+
+#define bmCEX4	0x80
+#define bmCEX3	0x40
+#define bmCEX2	0x20
+#define bmCEX1	0x10
+#define bmCEX0	0x08
+#define bmECI	0x04
+#define bmT2EX	0x02
+#define bmT2	0x01
+
+/* Bit masks in P3 (0xb0) */
+
+#define bmRXD	0x01
+#define bmTXD	0x02
+#define bm_INT0	0x04
+#define bm_INT1	0x08
+#define bmT0	0x10
+#define bmT1	0x20
+#define bm_WR	0x40
+#define bm_RD	0x80
+
+/* Bit masks in TMOD (0x89) */
+
+#define bmGATE1	0x80
+#define bmC_T1	0x40
+#define bmM11	0x20
+#define bmM01	0x10
+#define bmGATE0	0x08
+#define bmC_T0	0x04
+#define bmM10	0x02
+#define bmM00	0x01
+
+/* Bit masks in TCON (0x88) */
+
+#define bmTF1	0x80
+#define bmTR1	0x40
+#define bmTF0	0x20
+#define bmTR0	0x10
+#define bmIE1	0x08
+#define bmIT1	0x04
+#define bmIE0	0x02
+#define bmIT0	0x01
+
+/* Bit masks in AUXR (0x8e) */
+
+#define bmEXTRAM  0x02
+#define bmDISABLE 0x01
+
+/* Bit masks in AUXR1 (0xa2) */
+
+#define bmENBOOT  0x20
+#define bmGF2     0x08
+#define bmDPS     0x01
+
+/* Bit masks in T2CON (0xc8) */
+
+#define bmTF2	 0x80
+#define bmEXF2	 0x40
+#define bmRCLK	 0x20
+#define bmTCLK	 0x10
+#define bmEXEN2	 0x08
+#define bmTR2	 0x04
+#define bmC_T2	 0x02
+#define bmCP_RL2 0x01
+
+/* Bit masks in SCON (0x98) */
+
+#define bmFE_SM0 0x80
+#define bmFE	0x80
+#define bmSM0	0x80
+#define bmSM1	0x40
+#define bmSM2	0x20
+#define bmREN	0x10
+#define bmTB8	0x08
+#define bmRB8	0x04
+#define bmTI	0x02
+#define bmRI	0x01
+
+/* Bit masks in T2MOD (0xc9) */
+
+#define bmT2OE	0x02
+#define bmDCEN	0x01
+
+/* Bit masks in CMOD (0xd9) */
+
+#define bmCIDL	0x80
+#define bmWDTE	0x40
+#define bmCPS1	0x04
+#define bmCPS0	0x02
+#define bmECF	0x01
+
+/* Bit masks in CCON (0xd8) */
+
+#define bmCF	0x80
+#define bmCR	0x40
+#define bmCCF4	0x10
+#define bmCCF3	0x08
+#define bmCCF2	0x04
+#define bmCCF1	0x02
+#define bmCCF0	0x01
+
+/* Bit masks in CCAPM0 (0xda) */
+
+#define bmECOM0	0x40
+#define bmCAPP0	0x20
+#define bmCAPN0	0x10
+#define bmMAT0	0x08
+#define bmTOG0	0x04
+#define bmPWM0	0x02
+#define bmECCF0	0x01
+
+/* Bit masks in CCAPM1 (0xdb) */
+
+#define bmECOM1	0x40
+#define bmCAPP1	0x20
+#define bmCAPN1	0x10
+#define bmMAT1	0x08
+#define bmTOG1	0x04
+#define bmPWM1	0x02
+#define bmECCF1	0x01
+
+/* Bit masks in CCAPM2 (0xdc) */
+
+#define bmECOM2	0x40
+#define bmCAPP2	0x20
+#define bmCAPN2	0x10
+#define bmMAT2	0x08
+#define bmTOG2	0x04
+#define bmPWM2	0x02
+#define bmECCF2	0x01
+
+/* Bit masks in CCAPM3 (0xdd) */
+
+#define bmECOM3	0x40
+#define bmCAPP3	0x20
+#define bmCAPN3	0x10
+#define bmMAT3	0x08
+#define bmTOG3	0x04
+#define bmPWM3	0x02
+#define bmECCF3	0x01
+
+/* Bit masks in CCAPM4 (0xde) */
+
+#define bmECOM4	0x40
+#define bmCAPP4	0x20
+#define bmCAPN4	0x10
+#define bmMAT4	0x08
+#define bmTOG4	0x04
+#define bmPWM4	0x02
+#define bmECCF4	0x01
+
+#define bmECOM	0x40
+#define bmCAPP	0x20
+#define bmCAPN	0x10
+#define bmMAT	0x08
+#define bmTOG	0x04
+#define bmPWM	0x02
+#define bmEDDF	0x01
+
+
+#endif
+
+/* End of s51.src/regs51.h */
diff --git a/sim/ucsim/s51.src/s51.cc b/sim/ucsim/s51.src/s51.cc
new file mode 100644
index 0000000..64d3da0
--- /dev/null
+++ b/sim/ucsim/s51.src/s51.cc
@@ -0,0 +1,65 @@
+/*
+ * Simulator of microcontrollers (s51.cc)
+ *
+ * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#include "ddconfig.h"
+
+// prj
+#include "globals.h"
+
+// sim.src
+#include "appcl.h"
+
+// local
+#include "sim51cl.h"
+
+
+/*
+ * Main function of the Simulator of MCS51. Everything starts here.
+ */
+
+int
+main(int argc, char *argv[])
+{
+  int retval;
+  class cl_sim *sim;
+
+  cpus= cpus_51;
+  application= new cl_app();
+  application->init(argc, argv);
+  sim= new cl_sim51(application);
+  if (sim->init())
+    sim->state|= SIM_QUIT;
+  application->set_simulator(sim);
+  retval= application->run();
+
+  application->done();
+  delete application;
+  
+  return(retval);
+}
+
+/* End of s51.src/s51.cc */
diff --git a/sim/ucsim/s51.src/serial.cc b/sim/ucsim/s51.src/serial.cc
new file mode 100644
index 0000000..a9cc8d3
--- /dev/null
+++ b/sim/ucsim/s51.src/serial.cc
@@ -0,0 +1,443 @@
+/*
+ * Simulator of microcontrollers (serial.cc)
+ *
+ * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#include "ddconfig.h"
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <ctype.h>
+#include <errno.h>
+#include <fcntl.h>
+#include <sys/time.h>
+#include <strings.h>
+
+// prj
+#include "globals.h"
+#include "utils.h"
+
+// cmd
+#include "cmdutil.h"
+
+// local
+#include "serialcl.h"
+#include "regs51.h"
+#include "uc51cl.h"
+
+
+cl_serial::cl_serial(class cl_uc *auc):
+  cl_serial_hw(auc, 0, "uart")
+{
+}
+
+cl_serial::~cl_serial(void)
+{
+}
+
+int
+cl_serial::init(void)
+{
+  set_name("mcs51_uart");
+  cl_serial_hw::init();
+  sfr= uc->address_space(MEM_SFR_ID);
+  bas= uc->address_space("bits");
+  if (sfr)
+    {
+      sbuf= register_cell(sfr, SBUF);
+      pcon= register_cell(sfr, PCON);
+      scon= register_cell(sfr, SCON);
+    }
+  int i;
+  for (i= 0; i < 8; i++)
+    {
+      scon_bits[i]= register_cell(bas, SCON+i);
+    }
+
+  class cl_hw *t2= uc->get_hw(HW_TIMER, 2, 0);
+  if ((there_is_t2= t2 != 0))
+    {
+      t_mem d= sfr->get(T2CON);
+      t2_baud= d & (bmRCLK | bmTCLK);
+    }
+  else
+    t2_baud= false;
+  /*
+  cl_var *v;
+  chars pn(id_string);
+  pn.append("%d_", id);
+  uc->vars->add(v= new cl_var(pn+chars("on"), cfg, serconf_on));
+  uc->vars->add(v= new cl_var(pn+chars("check_often"), cfg, serconf_check_often));
+  v->init();
+  */
+  return(0);
+}
+
+void
+cl_serial::new_hw_added(class cl_hw *new_hw)
+{
+  if (new_hw->cathegory == HW_TIMER &&
+      new_hw->id == 2)
+    {
+      there_is_t2= true;
+      t_mem d= sfr->get(T2CON);
+      t2_baud= d & (bmRCLK | bmTCLK);
+    }
+}
+
+void
+cl_serial::added_to_uc(void)
+{
+  class cl_address_space *sfr= uc->address_space(MEM_SFR_ID);
+  class cl_it_src *is;
+  
+  uc->it_sources->add(is= new cl_it_src(uc, bmES,
+					sfr->get_cell(IE), bmES,
+					sfr->get_cell(SCON), bmTI,
+					0x0023, false, false,
+					"serial transmit", 6));
+  is->init();
+  uc->it_sources->add(is= new cl_it_src(uc, bmES,
+					sfr->get_cell(IE), bmES,
+					sfr->get_cell(SCON), bmRI,
+					0x0023, false, false,
+					"serial receive", 6));
+  is->init();
+}
+
+t_mem
+cl_serial::read(class cl_memory_cell *cell)
+{
+  if (cell == sbuf)
+    {
+      cfg_set(serconf_able_receive, 1);
+      return(s_in);
+    }
+  conf(cell, NULL);
+  return(cell->get());
+}
+
+void
+cl_serial::write(class cl_memory_cell *cell, t_mem *val)
+{
+  t_addr ba;
+  bool b= bas->is_owned(cell, &ba);
+  u8_t n= *val;
+  
+  if (cell == sbuf)
+    {
+      s_out= *val;
+      s_sending= true;
+      s_tr_bit = 0;
+      s_tr_tick= 0;
+      s_tr_t1= 0;
+    }
+  if (b)
+    {
+      n= scon->get();
+      u8_t m= 1 << (ba - SCON);
+      if (*val)
+	n|= m;
+      else
+	n&= ~m;
+    }
+  if ((cell == scon) ||
+      b)
+    {
+      _mode= n >> 6;
+      _bmREN= n & bmREN;
+      _bits= 8;
+      switch (_mode)
+	{
+	case 0:
+	  _bits= 8;
+	  _divby= 12;
+	  break;
+	case 1:
+	  _bits= 10;
+	  _divby= _bmSMOD?16:32;
+	  break;
+	case 2:
+	  _bits= 11;
+	  _divby= _bmSMOD?16:32;
+	  break;
+	case 3:
+	  _bits= 11;
+	  _divby= _bmSMOD?16:32;
+	  break;
+	}
+    }
+  else if (cell == pcon)
+    {
+      _bmSMOD= *val & bmSMOD;
+      /*switch (_mode)
+	{
+	case 1:
+	  _divby= _bmSMOD?16:32;
+	  break;
+	case 2:
+	  _divby= _bmSMOD?16:32;
+	  break;
+	case 3:
+	  _divby= _bmSMOD?16:32;
+	  break;
+	  }*/
+      if (_mode)
+	_divby= _bmSMOD?16:32;
+    }
+  else
+    conf(cell, val);
+}
+
+t_mem
+cl_serial::conf_op(cl_memory_cell *cell, t_addr addr, t_mem *val)
+{
+  if (addr < serconf_common)
+    return cl_serial_hw::conf_op(cell, addr, val);
+  switch ((enum serial_cfg)addr)
+    {
+      /*
+    case serial_:
+      if (val)
+	{
+	  if (*val)
+	    on= true;
+	  else
+	    on= false;
+	}
+      else
+	{
+	  cell->set(on?1:0);
+	}
+      break;
+      */
+    default:
+      break;
+    }
+  return cell->get();
+}
+
+int
+cl_serial::serial_bit_cnt(void)
+{
+  //int divby= 12;
+  int *tr_src= 0, *rec_src= 0;
+
+  switch (_mode)
+    {
+    case 0:
+      //divby  = 12;
+      tr_src = &s_tr_tick;
+      rec_src= &s_rec_tick;
+      break;
+    case 1:
+    case 3:
+      //divby  = (/*pcon->get()&bmSMOD*/_bmSMOD)?16:32;
+      tr_src = &s_tr_t1;
+      rec_src= &s_rec_t1;
+      break;
+    case 2:
+      //divby  = (/*pcon->get()&bmSMOD*/_bmSMOD)?16:32;
+      tr_src = &s_tr_tick;
+      rec_src= &s_rec_tick;
+      break;
+    }
+  if (t2_baud)
+    _divby= 16;
+  if (s_sending)
+    {
+      while (*tr_src >= _divby)
+	{
+	  (*tr_src)-= _divby;
+	  s_tr_bit++;
+	}
+    }
+  if (s_receiving)
+    {
+      while (*rec_src >= _divby)
+	{
+	  (*rec_src)-= _divby;
+	  s_rec_bit++;
+	}
+    }
+  return(0);
+}
+
+int
+cl_serial::tick(int cycles)
+{
+  char c;
+
+  serial_bit_cnt(/*_mode*/);
+  if (s_sending &&
+      (s_tr_bit >= _bits))
+    {
+      s_sending= false;
+      scon->set_bit1(bmTI);
+      io->write((char*)(&s_out), 1);
+      s_tr_bit-= _bits;
+    }
+  if ((_bmREN) &&
+      io->get_fin() &&
+      !s_receiving)
+    {
+      if (cfg_get(serconf_check_often))
+	{
+	  if (io->input_avail())
+	    io->proc_input(0);
+	}
+      if (/*fin->*/input_avail/*()*/)
+	{
+	  s_receiving= true;
+	  s_rec_bit= 0;
+	  s_rec_tick= s_rec_t1= 0;
+	}
+    }
+  if (s_receiving &&
+      (s_rec_bit >= _bits))
+    {
+      //if (fin->read(&c, 1) == 1)
+	{
+	  c= input;
+	  uc->sim->app->debug("UART%d received %d,%c\n", id,
+			      c,isprint(c)?c:' ');
+	  input_avail= false;
+	  s_in= c;
+	  sbuf->set(s_in);
+	  received(c);
+	}
+      s_receiving= false;
+      s_rec_bit-= _bits;
+    }
+  
+  int l;
+  s_tr_tick+= (l= cycles * uc->clock_per_cycle());
+  s_rec_tick+= l;
+  return(0);
+}
+
+void
+cl_serial::received(int c)
+{
+  scon->set_bit1(bmRI);
+  cfg_write(serconf_received, c);
+}
+
+void
+cl_serial::reset(void)
+{
+  s_tr_t1    = 0;
+  s_rec_t1   = 0;
+  s_tr_tick  = 0;
+  s_rec_tick = 0;
+  s_in       = 0;
+  s_out      = 0;
+  s_sending  = false;
+  s_receiving= false;
+  s_rec_bit  = 0;
+  s_tr_bit   = 0;
+}
+
+void
+cl_serial::happen(class cl_hw *where, enum hw_event he, void *params)
+{
+  if (where->cathegory == HW_TIMER)
+    {
+      if (where->id == 1)
+	{
+	  s_rec_t1++;
+	  s_tr_t1++;
+	}
+      if (where->id == 2 /*&& there_is_t2*/)
+	{
+	  switch (he)
+	    {
+	    case EV_T2_MODE_CHANGED:
+	      {
+		if (!t2_baud)
+		  s_rec_t1= s_tr_t1= 0;
+		t_mem *d= (t_mem *)params;
+		t2_baud= *d & (bmRCLK | bmTCLK);
+		break;
+	      }
+	    case EV_OVERFLOW:
+	      s_rec_t1++;
+	      s_tr_t1++;
+	      break;
+	    default: break;
+	    }
+	}
+    }
+}
+
+
+void
+cl_serial::print_info(class cl_console_base *con)
+{
+  const char *modes[]= { "Shift, fixed clock",
+			 "8 bit UART timer clocked",
+			 "9 bit UART fixed clock",
+			 "9 bit UART timer clocked" };
+  int sc= scon->get();
+
+  con->dd_printf("%s[%d] %s\n", id_string, id, on?"on":"off");
+  con->dd_printf("Input: ");
+  class cl_f *fin= io->get_fin(), *fout= io->get_fout();  
+  if (fin)
+    con->dd_printf("%s/%d ", fin->get_file_name(), fin->file_id);
+  con->dd_printf("Output: ");
+  if (fout)
+    con->dd_printf("%s/%d", fout->get_file_name(), fout->file_id);
+  con->dd_printf("\n");
+  int mode= (sc&(bmSM0|bmSM1))>>6;
+  con->dd_printf("%s", modes[mode]);
+  if (mode == 1 || mode == 2)
+    con->dd_printf(" (timer%d)", (t2_baud)?2:1);
+  con->dd_printf(" MultiProc=%s",
+		 (mode&2)?((sc&bmSM2)?"ON":"OFF"):"none");
+  con->dd_printf(" irq=%s", (sfr->get(IE)&bmES)?"en":"dis");
+  con->dd_printf(" prio=%d", uc->priority_of(bmPS));
+  con->dd_printf("\n");
+
+  con->dd_printf("Receiver");
+  con->dd_printf(" %s", (sc&bmREN)?"ON":"OFF");
+  con->dd_printf(" RB8=%c", (sc&bmRB8)?'1':'0');
+  con->dd_printf(" irq=%c", (sc&bmRI)?'1':'0');
+  con->dd_printf("\n");
+
+  con->dd_printf("Transmitter");
+  con->dd_printf(" TB8=%c", (sc&bmTB8)?'1':'0');
+  con->dd_printf(" irq=%c", (sc&bmTI)?'1':'0');
+  con->dd_printf("\n");
+  /*con->dd_printf("s_rec_t1=%d s_rec_bit=%d s_rec_tick=%d\n",
+		 s_rec_t1, s_rec_bit, s_rec_tick);
+  con->dd_printf("s_tr_t1=%d s_tr_bit=%d s_tr_tick=%d\n",
+		 s_tr_t1, s_tr_bit, s_tr_tick);
+		 con->dd_printf("divby=%d bits=%d\n", _divby, _bits);*/
+  print_cfg_info(con);
+}
+
+
+/* End of s51.src/serial.cc */
diff --git a/sim/ucsim/s51.src/serialcl.h b/sim/ucsim/s51.src/serialcl.h
new file mode 100644
index 0000000..1568cfc
--- /dev/null
+++ b/sim/ucsim/s51.src/serialcl.h
@@ -0,0 +1,90 @@
+/*
+ * Simulator of microcontrollers (serialcl.h)
+ *
+ * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#ifndef SERIALCL_HEADER
+#define SERIALCL_HEADER
+
+#include "fiocl.h"
+#include "stypes.h"
+#include "pobjcl.h"
+
+#include "uccl.h"
+#include "serial_hwcl.h"
+
+#include "newcmdposixcl.h"
+
+//#include "newcmdcl.h"
+
+class cl_serial_listener;
+
+class cl_serial: public cl_serial_hw
+{
+protected:
+  class cl_address_space *sfr, *bas;
+  bool there_is_t2, t2_baud;
+  class cl_memory_cell *sbuf, *pcon, *scon, *scon_bits[8];
+  uchar s_in;		// Serial channel input reg
+  uchar s_out;		// Serial channel output reg
+  bool  s_sending;	// Transmitter is working
+  bool  s_receiving;	// Receiver is working
+  int   s_rec_bit;	// Bit counter of receiver
+  int   s_tr_bit;	// Bit counter of transmitter
+  int   s_rec_t1;	// T1 overflows for receiving
+  int   s_tr_t1;	// T1 overflows for sending
+  int   s_rec_tick;	// Machine cycles for receiving
+  int   s_tr_tick;	// Machine cycles for sending
+  uchar _mode;
+  uchar _bmREN;
+  uchar _bmSMOD;
+  uchar _bits;
+  uchar _divby;
+public:
+  cl_serial(class cl_uc *auc);
+  virtual ~cl_serial(void);
+  virtual int init(void);
+  virtual int cfg_size(void) { return 10; }
+
+  virtual void new_hw_added(class cl_hw *new_hw);
+  virtual void added_to_uc(void);
+  virtual t_mem read(class cl_memory_cell *cell);
+  virtual void write(class cl_memory_cell *cell, t_mem *val);
+  virtual t_mem conf_op(cl_memory_cell *cell, t_addr addr, t_mem *val);
+
+  virtual int  serial_bit_cnt(void);
+  virtual void received(int c);
+
+  virtual int tick(int cycles);
+  virtual void reset(void);
+  virtual void happen(class cl_hw *where, enum hw_event he, void *params);
+  
+  virtual void print_info(class cl_console_base *con);
+};
+
+
+#endif
+
+/* End of s51.src/serialcl.h */
diff --git a/sim/ucsim/s51.src/sim51.cc b/sim/ucsim/s51.src/sim51.cc
new file mode 100644
index 0000000..063249c
--- /dev/null
+++ b/sim/ucsim/s51.src/sim51.cc
@@ -0,0 +1,115 @@
+/*
+ * Simulator of microcontrollers (sim51.cc)
+ *
+ * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#include "ddconfig.h"
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <ctype.h>
+#include <errno.h>
+#include "i_string.h"
+
+#include "globals.h"
+#include "utils.h"
+#include "cmdutil.h"
+#include "charscl.h"
+
+#include "sim51cl.h"
+//#include "cmd51cl.h"
+#include "uc51cl.h"
+#include "uc52cl.h"
+#include "uc521cl.h"
+#include "uc517cl.h"
+#include "uc51rcl.h"
+#include "uc89c51rcl.h"
+#include "uc251cl.h"
+#include "uc390cl.h"
+#include "uc88xcl.h"
+#include "uc320cl.h"
+#include "uc380cl.h"
+#include "glob.h"
+
+
+cl_sim51::cl_sim51(class cl_app *the_app):
+  cl_sim(the_app)
+{}
+
+
+class cl_uc *
+cl_sim51::mk_controller(void)
+{
+  int i;
+  char *typ= 0;
+  class cl_optref type_option(this);
+
+  type_option.init();
+  type_option.use(cchars("cpu_type"));
+  i= 0;
+  if ((typ= type_option.get_value(typ)) == 0)
+    typ= cchars("C52");
+  while ((cpus_51[i].type_str != NULL) &&
+	 (strcasecmp(typ, cpus_51[i].type_str) != 0))
+    i++;
+  if (cpus_51[i].type_str == NULL)
+    {
+      fprintf(stderr, "Unknown processor type. "
+	      "Use -H option to see known types.\n");
+      return(NULL);
+    }
+  switch (cpus_51[i].type)
+    {
+    case CPU_51: case CPU_31:
+      return(new cl_51core(&cpus_51[i], this));
+    case CPU_52: case CPU_32:
+      return(new cl_uc52(&cpus_51[i], this));
+    case CPU_51R:
+      return(new cl_uc51r(&cpus_51[i], this));
+    case CPU_89C51R:
+      return(new cl_uc89c51r(&cpus_51[i], this));
+    case CPU_C521:
+      return(new cl_uc521(&cpus_51[i], this));
+    case CPU_517:
+      return(new cl_uc517(&cpus_51[i], this));
+    case CPU_XC88X:
+      return(new cl_uc88x(&cpus_51[i], this));
+    case CPU_F380:
+      return(new cl_uc380(&cpus_51[i], this));
+    case CPU_251:
+      return(new cl_uc251(&cpus_51[i], this));
+    case CPU_DS320:
+      return(new cl_uc320(&cpus_51[i], this));
+    case CPU_DS390: case CPU_DS390F:
+      return(new cl_uc390(&cpus_51[i], this));
+    default:
+      fprintf(stderr, "Unknown processor type\n");
+      return NULL;
+    }
+  return(NULL);
+}
+
+
+/* End of s51.src/sim51.cc */
diff --git a/sim/ucsim/s51.src/sim51cl.h b/sim/ucsim/s51.src/sim51cl.h
new file mode 100644
index 0000000..8a3d0db
--- /dev/null
+++ b/sim/ucsim/s51.src/sim51cl.h
@@ -0,0 +1,45 @@
+/*
+ * Simulator of microcontrollers (sim51cl.h)
+ *
+ * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#ifndef SIM51CL_HEADER
+#define SIM51CL_HEADER
+
+#include "simcl.h"
+
+
+class cl_sim51: public cl_sim
+{
+public:
+  cl_sim51(class cl_app *the_app);
+  //virtual int proc_arg(char optopt, char *optarg);
+  virtual class cl_uc *mk_controller(void);
+};
+
+
+#endif
+
+/* End of s51.src/sim51cl.h */
diff --git a/sim/ucsim/s51.src/start1 b/sim/ucsim/s51.src/start1
new file mode 100755
index 0000000..8bdf6aa
--- /dev/null
+++ b/sim/ucsim/s51.src/start1
@@ -0,0 +1,5 @@
+#!/bin/sh
+
+s51 -Sin=tee_1,out=1_tee "$@"
+
+# End of start1
diff --git a/sim/ucsim/s51.src/start2 b/sim/ucsim/s51.src/start2
new file mode 100755
index 0000000..15a0811
--- /dev/null
+++ b/sim/ucsim/s51.src/start2
@@ -0,0 +1,5 @@
+#!/bin/sh
+
+s51 -Sin=tee_2,out=2_tee "$@"
+
+# End of start2
diff --git a/sim/ucsim/s51.src/test/Makefile b/sim/ucsim/s51.src/test/Makefile
new file mode 100644
index 0000000..5f1ec23
--- /dev/null
+++ b/sim/ucsim/s51.src/test/Makefile
@@ -0,0 +1,16 @@
+PRJ		= test_mdu517 test_mdu88x \
+		  stn stp strr sts stt stxr stxrw stxw \
+		  stt_small stt_large \
+		  monitor test_ser tim_ser
+
+all:
+	for p in $(PRJ); do \
+		$(MAKE) -f $$p.mk clean all ;\
+	done
+
+clean:
+	for p in $(PRJ); do \
+		$(MAKE) -f $$p.mk clean ;\
+	done
+	rm -f *.out *.sout *.tim *.csv *.sim
+	rm -f st*[56][0-9][0-9].cmd st*[56]*.txt
diff --git a/sim/ucsim/s51.src/test/c517.h b/sim/ucsim/s51.src/test/c517.h
new file mode 100644
index 0000000..445c312
--- /dev/null
+++ b/sim/ucsim/s51.src/test/c517.h
@@ -0,0 +1,13 @@
+#ifndef C517_HEADER
+#define C517_HEADER
+
+__sfr __at (0xE9) MD0;
+__sfr __at (0xEA) MD1;
+__sfr __at (0xEB) MD2;
+__sfr __at (0xEC) MD3;
+__sfr __at (0xED) MD4;
+__sfr __at (0xEE) MD5;
+
+__sfr __at (0xEF) ARCON;
+
+#endif
diff --git a/sim/ucsim/s51.src/test/conf.cmd b/sim/ucsim/s51.src/test/conf.cmd
new file mode 100644
index 0000000..54ea949
--- /dev/null
+++ b/sim/ucsim/s51.src/test/conf.cmd
@@ -0,0 +1 @@
+set hw simif xram 0xffff
diff --git a/sim/ucsim/s51.src/test/dummy.h b/sim/ucsim/s51.src/test/dummy.h
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/sim/ucsim/s51.src/test/dummy.h
diff --git a/sim/ucsim/s51.src/test/hw.h b/sim/ucsim/s51.src/test/hw.h
new file mode 100644
index 0000000..a29d13e
--- /dev/null
+++ b/sim/ucsim/s51.src/test/hw.h
@@ -0,0 +1,47 @@
+#ifndef HW_HEADER

+#define HW_HEADER

+

+

+#if defined __SDCC || defined SDCC

+#include <mcs51/8052.h>

+#elif defined __C51__

+#include <reg52.h>

+#else /* IAR4 */

+#include <io51.h>

+#endif

+

+

+#if defined __SDCC || defined SDCC

+#define bit __bit

+#define CODE_PTR(TYPE) __code TYPE *

+#define XRAM_PTR(TYPE) __xdata TYPE *

+#elif defined __C51__

+#define __bit bit

+#define CODE_PTR(TYPE) TYPE code *

+#define XRAM_PTR(TYPE) TYPE xdata *

+#else /* IAR4 */

+#define __bit bit

+#endif

+

+#ifndef FALSE

+#define FALSE 0

+#endif

+#ifndef TRUE

+#define TRUE 1

+#endif

+

+#define XRAM_SIZE (0x1000)

+#define PAGE_SIZE (0x0200)

+#define RESERVED_SPACE (2*PAGE_SIZE)

+

+#define LOADER_START (0xe000)

+#define LOADER_SIZE (0x10000 - LOADER_START)

+

+#define INFO_BLOCK_SIZE (0x0040)

+

+#define BOARD_INFO ((LOADER_START - RESERVED_SPACE - PAGE_SIZE - INFO_BLOCK_SIZE) + LOADER_SIZE)

+

+

+#endif

+

+/* End of hw.h */

diff --git a/sim/ucsim/s51.src/test/mdu517.c b/sim/ucsim/s51.src/test/mdu517.c
new file mode 100644
index 0000000..6c6bed0
--- /dev/null
+++ b/sim/ucsim/s51.src/test/mdu517.c
@@ -0,0 +1,124 @@
+#include "c517.h"
+
+#include "mdu517.h"
+
+static uint16_t v;
+static uint32_t d;
+
+uint8_t
+mdu_32udiv16(uint32_t op1, uint16_t op2, uint32_t *res, uint16_t *rem)
+  __reentrant
+{
+  MD0= op1 & 0xff;
+  MD1= (op1 >> 8) & 0xff;
+  MD2= (op1 >> 16) & 0xff;
+  MD3= (op1 >> 24) & 0xff;
+
+  MD4= op2 & 0xff;
+  MD5= (op2 >> 8) & 0xff;
+
+  __asm__ ("nop");
+
+  d= (uint32_t)MD0 + (uint32_t)MD1*256l + (uint32_t)MD2*256l*256l + (uint32_t)MD3*256l*256l*256l;
+  if (res)
+    *res= d;
+  v= MD5*256 + MD4;
+  if (rem)
+    *rem= v;
+
+  return ARCON & 0xc0;
+}
+
+uint8_t
+mdu_16udiv16(uint16_t op1, uint16_t op2, uint16_t *res, uint16_t *rem)
+  __reentrant
+{
+  MD0= op1 & 0xff;
+  MD1= (op1 >> 8) & 0xff;
+  MD4= op2 & 0xff;
+  MD5= (op2 >> 8) & 0xff;
+
+  __asm__ ("nop");
+
+  v= MD1*256 + MD0;
+  if (res)
+    *res= v;
+  v= MD5*256 + MD4;
+  if (rem)
+    *rem= v;
+
+  return ARCON & 0xc0;
+}
+
+uint8_t
+mdu_16umul16(uint16_t op1, uint16_t op2, uint32_t *res)
+  __reentrant
+{
+  MD0= op1 & 0xff;
+  MD4= op2 & 0xff;
+  MD1= (op1 >> 8) & 0xff;
+  MD5= (op2 >> 8) & 0xff;
+
+  __asm__ ("nop");
+
+  d= (uint32_t)MD0 + (uint32_t)MD1*256l + (uint32_t)MD2*256l*256l + (uint32_t)MD3*256l*256l*256l;
+  if (res)
+    *res= d;
+
+  return ARCON & 0x80;
+}
+
+uint8_t
+mdu_norm(uint32_t op, uint32_t *res, uint8_t *nuof_shifts)
+  __reentrant
+{
+  uint8_t a;
+  
+  MD0= op & 0xff;
+  MD1= (op >> 8) & 0xff;
+  MD2= (op >> 16) & 0xff;
+  MD3= (op >> 24) & 0xff;
+  ARCON= 0;
+  
+  __asm__ ("nop");
+
+  d= (uint32_t)MD0 + (uint32_t)MD1*256l + (uint32_t)MD2*256l*256l + (uint32_t)MD3*256l*256l*256l;
+  if (res)
+    *res= d;
+  a= ARCON;
+  if (nuof_shifts)
+    *nuof_shifts= a & 0x1f;
+  return a & 0xc0;
+}
+
+uint8_t
+mdu_lshift(uint32_t op, uint8_t shifts, uint8_t right, uint32_t *res)
+  __reentrant
+{
+  MD0= op & 0xff;
+  MD1= (op >> 8) & 0xff;
+  MD2= (op >> 16) & 0xff;
+  MD3= (op >> 24) & 0xff;
+  ARCON= (right?0x20:0) + (shifts&0x1f);
+  
+  __asm__ ("nop");
+
+  d= (uint32_t)MD0 + (uint32_t)MD1*256l + (uint32_t)MD2*256l*256l + (uint32_t)MD3*256l*256l*256l;
+  if (res)
+    *res= d;
+  return ARCON & 0x80;
+}
+
+uint8_t
+mdu_lshift_left(uint32_t op, uint8_t shifts, uint32_t *res)
+  __reentrant
+{
+  return mdu_lshift(op, shifts, 0, res);
+}
+
+uint8_t
+mdu_lshift_right(uint32_t op, uint8_t shifts, uint32_t *res)
+  __reentrant
+{
+  return mdu_lshift(op, shifts, 1, res);
+}
diff --git a/sim/ucsim/s51.src/test/mdu517.h b/sim/ucsim/s51.src/test/mdu517.h
new file mode 100644
index 0000000..148017a
--- /dev/null
+++ b/sim/ucsim/s51.src/test/mdu517.h
@@ -0,0 +1,28 @@
+#ifndef MDU517_HEADER
+#define MDU517_HEADER
+
+#include <stdint.h>
+
+extern uint8_t mdu_32udiv16(uint32_t op1, uint16_t op2,
+			    uint32_t *res, uint16_t *rem)
+  __reentrant;
+extern uint8_t mdu_16udiv16(uint16_t op1, uint16_t op2,
+			    uint16_t *res, uint16_t *rem)
+    __reentrant;
+extern uint8_t mdu_16umul16(uint16_t op1, uint16_t op2,
+			    uint32_t *res)
+    __reentrant;
+extern uint8_t mdu_norm(uint32_t op,
+			uint32_t *res, uint8_t *nuof_shifts)
+    __reentrant;
+extern uint8_t mdu_lshift(uint32_t op, uint8_t shifts, uint8_t right,
+			  uint32_t *res)
+    __reentrant;
+extern uint8_t mdu_lshift_left(uint32_t op, uint8_t shifts,
+			       uint32_t *res)
+    __reentrant;
+extern uint8_t mdu_lshift_right(uint32_t op, uint8_t shifts,
+				uint32_t *res)
+    __reentrant;
+
+#endif
diff --git a/sim/ucsim/s51.src/test/mdu88x.c b/sim/ucsim/s51.src/test/mdu88x.c
new file mode 100644
index 0000000..248fef6
--- /dev/null
+++ b/sim/ucsim/s51.src/test/mdu88x.c
@@ -0,0 +1,234 @@
+#include "xc88x.h"
+
+#include "mdu88x.h"
+
+static uint16_t v;
+static uint32_t d;
+
+/* unsigned OPs */
+
+uint8_t
+mdu_32udiv16(uint32_t op1, uint16_t op2, uint32_t *res, uint16_t *rem)
+  __reentrant
+{
+  MD0= op1 & 0xff;
+  MD1= (op1 >> 8) & 0xff;
+  MD2= (op1 >> 16) & 0xff;
+  MD3= (op1 >> 24) & 0xff;
+
+  MD4= op2 & 0xff;
+  MD5= (op2 >> 8) & 0xff;
+
+  MDUCON= 0x10 + 0x02;
+  while (MDUSTAT & 0x04) ;
+  
+  d= (uint32_t)MD0 + (uint32_t)MD1*256l + (uint32_t)MD2*256l*256l + (uint32_t)MD3*256l*256l*256l;
+  if (res)
+    *res= d;
+  v= MD5*256 + MD4;
+  if (rem)
+    *rem= v;
+
+  return MDUSTAT & 0x02;
+}
+
+uint8_t
+mdu_16udiv16(uint16_t op1, uint16_t op2, uint16_t *res, uint16_t *rem)
+  __reentrant
+{
+  MD0= op1 & 0xff;
+  MD1= (op1 >> 8) & 0xff;
+  MD4= op2 & 0xff;
+  MD5= (op2 >> 8) & 0xff;
+
+  MDUCON= 0x10 + 0x01;
+  while (MDUSTAT & 0x04) ;
+  
+  v= MD1*256 + MD0;
+  if (res)
+    *res= v;
+  v= MD5*256 + MD4;
+  if (rem)
+    *rem= v;
+
+  return MDUSTAT & 0x02;
+}
+
+uint8_t
+mdu_16umul16(uint16_t op1, uint16_t op2, uint32_t *res)
+  __reentrant
+{
+  MD0= op1 & 0xff;
+  MD4= op2 & 0xff;
+  MD1= (op1 >> 8) & 0xff;
+  MD5= (op2 >> 8) & 0xff;
+
+  MDUCON= 0x10 + 0x00;
+  while (MDUSTAT & 0x04) ;
+  
+  d= (uint32_t)MD0 + (uint32_t)MD1*256l + (uint32_t)MD2*256l*256l + (uint32_t)MD3*256l*256l*256l;
+  if (res)
+    *res= d;
+
+  return MDUSTAT & 0x02;
+}
+
+/* signed OPs */
+
+uint8_t
+mdu_32sdiv16(int32_t op1, int16_t op2, int32_t *res, int16_t *rem)
+  __reentrant
+{
+  MD0= op1 & 0xff;
+  MD1= (op1 >> 8) & 0xff;
+  MD2= (op1 >> 16) & 0xff;
+  MD3= (op1 >> 24) & 0xff;
+
+  MD4= op2 & 0xff;
+  MD5= (op2 >> 8) & 0xff;
+
+  MDUCON= 0x10 + 0x06;
+  while (MDUSTAT & 0x04) ;
+  
+  d= (uint32_t)MD0 + (uint32_t)MD1*256l + (uint32_t)MD2*256l*256l + (uint32_t)MD3*256l*256l*256l;
+  if (res)
+    *res= d;
+  v= MD5*256 + MD4;
+  if (rem)
+    *rem= v;
+
+  return MDUSTAT & 0x02;
+}
+
+uint8_t
+mdu_16sdiv16(int16_t op1, int16_t op2, int16_t *res, int16_t *rem)
+  __reentrant
+{
+  MD0= op1 & 0xff;
+  MD1= (op1 >> 8) & 0xff;
+  MD4= op2 & 0xff;
+  MD5= (op2 >> 8) & 0xff;
+
+  MDUCON= 0x10 + 0x05;
+  while (MDUSTAT & 0x04) ;
+  
+  v= MD1*256 + MD0;
+  if (res)
+    *res= v;
+  v= MD5*256 + MD4;
+  if (rem)
+    *rem= v;
+
+  return MDUSTAT & 0x02;
+}
+
+uint8_t
+mdu_16smul16(int16_t op1, int16_t op2, int32_t *res)
+  __reentrant
+{
+  MD0= op1 & 0xff;
+  MD4= op2 & 0xff;
+  MD1= (op1 >> 8) & 0xff;
+  MD5= (op2 >> 8) & 0xff;
+
+  MDUCON= 0x10 + 0x04;
+  while (MDUSTAT & 0x04) ;
+  
+  d= (uint32_t)MD0 + (uint32_t)MD1*256l + (uint32_t)MD2*256l*256l + (uint32_t)MD3*256l*256l*256l;
+  if (res)
+    *res= d;
+
+  return MDUSTAT & 0x02;
+}
+
+/* normalize */
+
+uint8_t
+mdu_norm(uint32_t op, uint32_t *res, uint8_t *nuof_shifts)
+  __reentrant
+{
+  MD0= op & 0xff;
+  MD1= (op >> 8) & 0xff;
+  MD2= (op >> 16) & 0xff;
+  MD3= (op >> 24) & 0xff;
+  
+  MDUCON= 0x10 + 0x08;
+  while (MDUSTAT & 0x04) ;
+
+  d= (uint32_t)MD0 + (uint32_t)MD1*256l + (uint32_t)MD2*256l*256l + (uint32_t)MD3*256l*256l*256l;
+  if (res)
+    *res= d;
+  if (nuof_shifts)
+    *nuof_shifts= MD4 & 0x1f;
+  return MDUSTAT & 0x02;
+}
+
+/* logical shifts */
+
+uint8_t
+mdu_lshift(uint32_t op, uint8_t shifts, uint8_t right, uint32_t *res)
+  __reentrant
+{
+  MD0= op & 0xff;
+  MD1= (op >> 8) & 0xff;
+  MD2= (op >> 16) & 0xff;
+  MD3= (op >> 24) & 0xff;
+  MD4= (right?0x20:0) + (shifts&0x1f);
+  
+  MDUCON= 0x10 + 0x03;
+  while (MDUSTAT & 0x04) ;
+
+  d= (uint32_t)MD0 + (uint32_t)MD1*256l + (uint32_t)MD2*256l*256l + (uint32_t)MD3*256l*256l*256l;
+  if (res)
+    *res= d;
+  return MDUSTAT & 0x02;
+}
+
+uint8_t
+mdu_lshift_left(uint32_t op, uint8_t shifts, uint32_t *res)
+  __reentrant
+{
+  return mdu_lshift(op, shifts, 0, res);
+}
+
+uint8_t
+mdu_lshift_right(uint32_t op, uint8_t shifts, uint32_t *res)
+  __reentrant
+{
+  return mdu_lshift(op, shifts, 1, res);
+}
+
+/* arithmetic shifts */
+
+uint8_t
+mdu_ashift(int32_t op, int8_t shifts, int8_t right, int32_t *res)
+  __reentrant
+{
+  MD0= op & 0xff;
+  MD1= (op >> 8) & 0xff;
+  MD2= (op >> 16) & 0xff;
+  MD3= (op >> 24) & 0xff;
+  MD4= (right?0x20:0) + (shifts&0x1f);
+  
+  MDUCON= 0x10 + 0x07;
+  while (MDUSTAT & 0x04) ;
+
+  d= (uint32_t)MD0 + (uint32_t)MD1*256l + (uint32_t)MD2*256l*256l + (uint32_t)MD3*256l*256l*256l;
+  if (res)
+    *res= d;
+  return MDUSTAT & 0x02;
+}
+
+uint8_t
+mdu_ashift_left(int32_t op, int8_t shifts, int32_t *res)
+  __reentrant
+{
+  return mdu_lshift(op, shifts, 0, res);
+}
+
+uint8_t
+mdu_ashift_right(int32_t op, int8_t shifts, int32_t *res)
+  __reentrant
+{
+  return mdu_lshift(op, shifts, 1, res);
+}
diff --git a/sim/ucsim/s51.src/test/mdu88x.h b/sim/ucsim/s51.src/test/mdu88x.h
new file mode 100644
index 0000000..65d41b2
--- /dev/null
+++ b/sim/ucsim/s51.src/test/mdu88x.h
@@ -0,0 +1,60 @@
+#ifndef MDU88X_HEADER
+#define MDU88X_HEADER
+
+#include <stdint.h>
+
+/* unsigned OPs */
+
+extern uint8_t mdu_32udiv16(uint32_t op1, uint16_t op2,
+			    uint32_t *res, uint16_t *rem)
+  __reentrant;
+extern uint8_t mdu_16udiv16(uint16_t op1, uint16_t op2,
+			    uint16_t *res, uint16_t *rem)
+    __reentrant;
+extern uint8_t mdu_16umul16(uint16_t op1, uint16_t op2,
+			    uint32_t *res)
+    __reentrant;
+
+/* signed OPs */
+
+extern uint8_t mdu_32sdiv16(int32_t op1, int16_t op2,
+			    int32_t *res, int16_t *rem)
+  __reentrant;
+extern uint8_t mdu_16sdiv16(int16_t op1, int16_t op2,
+			    int16_t *res, int16_t *rem)
+    __reentrant;
+extern uint8_t mdu_16smul16(int16_t op1, int16_t op2,
+			    int32_t *res)
+    __reentrant;
+
+/* normalize */
+
+extern uint8_t mdu_norm(uint32_t op,
+			uint32_t *res, uint8_t *nuof_shifts)
+    __reentrant;
+
+/* logical shifts */
+
+extern uint8_t mdu_lshift(uint32_t op, uint8_t shifts, uint8_t right,
+			  uint32_t *res)
+    __reentrant;
+extern uint8_t mdu_lshift_left(uint32_t op, uint8_t shifts,
+			       uint32_t *res)
+    __reentrant;
+extern uint8_t mdu_lshift_right(uint32_t op, uint8_t shifts,
+				uint32_t *res)
+    __reentrant;
+
+/* arithmetic shifts */
+
+extern uint8_t mdu_ashift(int32_t op, int8_t shifts, int8_t right,
+			  int32_t *res)
+    __reentrant;
+extern uint8_t mdu_ashift_left(int32_t op, int8_t shifts,
+			       int32_t *res)
+    __reentrant;
+extern uint8_t mdu_ashift_right(int32_t op, int8_t shifts,
+				int32_t *res)
+    __reentrant;
+
+#endif
diff --git a/sim/ucsim/s51.src/test/monitor.c b/sim/ucsim/s51.src/test/monitor.c
new file mode 100644
index 0000000..319d5a2
--- /dev/null
+++ b/sim/ucsim/s51.src/test/monitor.c
@@ -0,0 +1,65 @@
+#include <string.h>
+#include "hw.h"
+
+#include "serial.h"
+#include "print.h"
+
+__xdata char *simif;
+
+int cnt;
+
+void process(char *cmd)
+{
+  if (strstr(cmd, "test") == cmd)
+    {
+      cnt++;
+      print_c('_');print(cmd);print_c('_');
+      print_f("This is a test %d\n", cnt);
+    }
+  else if (strstr(cmd, "dump") == cmd)
+    {
+      int i;
+      print_c('_');print(cmd);print_c('_');
+      for (i= 0; i<100; i++)
+	{
+	  print_cx(i);
+	  print(" ");
+	}
+      print("\n----\n");
+    }
+  else
+    {
+      print("Unknown command: \"");print(cmd);print("\"\n");
+    }
+}
+
+__xdata char cmd[40];
+char ptr;
+
+void main(void)
+{
+  simif= (__xdata char *)0xffff;
+  serial_init(9600);
+  cmd[ptr=0]= 0;
+  print("Hello World!\n");
+  P1= 0;
+  while (1)
+    {
+      if (serial_received())
+	{
+	  char c= serial_receive();
+	  if ((c == '\n') ||
+	      (c == '\r'))
+	    {
+	      process(cmd);
+	      cmd[ptr=0]= 0;
+	    }
+	  else if (ptr < 39)
+	    {
+	      cmd[ptr++]= c;
+	      cmd[ptr]= 0;
+	      print("cmd=");print(cmd);print_c('\n');
+	    }
+	}
+    }
+}
diff --git a/sim/ucsim/s51.src/test/monitor.mk b/sim/ucsim/s51.src/test/monitor.mk
new file mode 100644
index 0000000..6b5a99f
--- /dev/null
+++ b/sim/ucsim/s51.src/test/monitor.mk
@@ -0,0 +1,7 @@
+MAIN		= monitor
+
+OTHERS		= serial print
+
+include sdcc.mk
+
+MODEL		= small
diff --git a/sim/ucsim/s51.src/test/print.c b/sim/ucsim/s51.src/test/print.c
new file mode 100644
index 0000000..32d51e9
--- /dev/null
+++ b/sim/ucsim/s51.src/test/print.c
@@ -0,0 +1,189 @@
+#if defined __SDCC || defined SDCC

+#include <stdio.h>

+#elif defined __C51__

+#include <stdio.h>

+#endif

+

+#include "print.h"

+

+void

+print(char *s) __reentrant

+{

+  if (s)

+    for (; *s; putchar(*s++)) ;

+}

+

+void

+print_form(char *s, long l, void *p) __reentrant

+{

+  if (s)

+    for (; *s; s++)

+      if (*s != '%')

+	putchar(*s);

+      else

+	{

+	  s++;

+	  if (*s)

+	    switch (*s)

+	      {

+	      case 'u': print_u(l); break;

+	      case 'd': print_d(l); break;

+	      case 'p': print_p(p); break;

+	      case 'x': print_x(l); break;

+	      case '2': print_cx(l); break;

+	      case '4': print_lx(l); break;

+	      }

+	}

+}

+

+/* signed integer in decimal */

+

+void

+print_d(long i) __reentrant

+{

+  long x= 1000000000;

+  char in= 0;

+  if (i<0)

+    {

+      putchar('-');

+      i= -i;

+    }

+  while (x)

+    {

+      int j= i/x;

+      if (in || j || (x==1))

+	putchar(j+'0');

+      in= in || j;

+      i%= x;

+      x/= 10;

+    }

+}

+

+

+/* unsigned integer in decimal */

+

+void

+print_u(unsigned int i) __reentrant

+{

+  int x= 10000;

+  while (x)

+    {

+      int j= i/x;

+      putchar(j+'0');

+      i%= x;

+      x/= 10;

+    }

+}

+

+

+/* unsigned int in hex */

+

+void

+print_cx(unsigned char i)

+{

+  putchar((i/16)+(((i/16)<10)?'0':('A'-10)));

+  putchar((i&15)+(((i&15)<10)?'0':('A'-10)));

+}

+

+void

+print_x(unsigned int i) __reentrant

+{

+/*

+  unsigned char j;

+  for (j= 0; j<4; j++)

+    {

+      char v= (i&0xf000)>>12;

+      putchar(v+((v<10)?'0':('A'-10)));

+      i<<= 4;

+    }

+*/

+  print_cx(i/256);

+  print_cx(i&0xff);

+}

+

+void

+print_lx(unsigned long i) __reentrant

+{

+  print_x(i >> 16);

+  print_x(i & 0xffff);

+}

+

+void

+print_p(void *p) __reentrant

+{

+  unsigned char t= ((long)p)/0x10000;

+  if (t>=0x80)

+    putchar('C');

+  else if (t>=0x60)

+    putchar('P');

+  else if (t>=0x40)

+    putchar('I');

+  else

+    putchar('X');

+  putchar(':');

+  print_x(((long)p)&0xffff);

+}

+

+

+void

+print_c(char c)

+{

+  putchar(c);

+}

+

+

+void

+term_cls()

+{

+  print("\033[2J");

+}

+

+

+void

+term_xy(char x1, char y1)

+{

+  putchar('\033');

+  putchar('[');

+  print_u(y1);

+  putchar(';');

+  print_u(x1);

+  putchar('H');

+}

+

+

+void

+term_save()

+{

+  print("\033[s");

+}

+

+

+void

+term_restore()

+{

+  print("\033[u");

+}

+

+

+void

+term_hide()

+{

+  print("\033[?25l");

+}

+

+

+void

+term_show()

+{

+  print("\033[?25h");

+}

+

+

+void

+term_color(int bg, int fg) __reentrant

+{

+  if (bg >= 0)

+    print_form("\033[%um", bg+40, NULL);

+  if (fg >= 0)

+    print_form("\033[%um", fg+30, NULL);

+}

diff --git a/sim/ucsim/s51.src/test/print.h b/sim/ucsim/s51.src/test/print.h
new file mode 100644
index 0000000..3cd6ee2
--- /dev/null
+++ b/sim/ucsim/s51.src/test/print.h
@@ -0,0 +1,26 @@
+#ifndef PRINT_HEADER

+#define PRINT_HEADER

+

+

+extern void print(char *s) __reentrant;

+extern void print_form(char *s, long l, void *p) __reentrant;

+#define print_f(A,B) print_form((A),(B),0)

+#define print_fp(A,B) print_form((A),0,(B))

+extern void print_d(long i) __reentrant;

+extern void print_u(unsigned int i) __reentrant;

+extern void print_cx(unsigned char i);

+extern void print_x(unsigned int i) __reentrant;

+extern void print_lx(unsigned long i) __reentrant;

+extern void print_p(void *p) __reentrant;

+extern void print_c(char c);

+

+extern void term_cls();

+extern void term_xy(char x1, char y1);

+extern void term_save();

+extern void term_restore();

+extern void term_hide();

+extern void term_show();

+extern void term_color(int bg, int fg) __reentrant;

+

+  

+#endif

diff --git a/sim/ucsim/s51.src/test/run.cmd b/sim/ucsim/s51.src/test/run.cmd
new file mode 100644
index 0000000..972da4f
--- /dev/null
+++ b/sim/ucsim/s51.src/test/run.cmd
@@ -0,0 +1,2 @@
+run
+state
diff --git a/sim/ucsim/s51.src/test/run.sh b/sim/ucsim/s51.src/test/run.sh
new file mode 100755
index 0000000..1be2743
--- /dev/null
+++ b/sim/ucsim/s51.src/test/run.sh
@@ -0,0 +1,30 @@
+PRJ=$1
+
+if [ -z "$PRJ" ]; then
+   PRJ=test_mdu88x
+fi
+
+if [ -f ${PRJ}.ihx ]; then
+    if [ -f ${PRJ}_conf.cmd ]; then
+	CONF="-C ${PRJ}_conf.cmd"
+    elif [ -f conf.cmd ]; then
+	CONF="-C conf.cmd"
+    else
+	CONF=""
+    fi
+    if [ -f ${PRJ}.type ]; then
+	TYPE="-t $(cat ${PRJ}.type)"
+    else
+	TYPE="-t 52"
+    fi
+    if [ -f ${PRJ}.cmd ]; then
+	CMD="../s51 ${TYPE} ${CONF} -S in=/dev/null,out=${PRJ}.out ${PRJ}.ihx"
+	echo $CMD
+	$CMD <${PRJ}.cmd | tee ${PRJ}.sim
+    else
+	CMD="../s51 ${TYPE} ${CONF} -Z6666 -S in=/dev/null,out=${PRJ}.out -G ${PRJ}.ihx"
+	echo $CMD
+	$CMD|tee ${PRJ}.sim
+    fi
+    cat ${PRJ}.out
+fi
diff --git a/sim/ucsim/s51.src/test/sdcc.mk b/sim/ucsim/s51.src/test/sdcc.mk
new file mode 100644
index 0000000..3945642
--- /dev/null
+++ b/sim/ucsim/s51.src/test/sdcc.mk
@@ -0,0 +1,46 @@
+CC		= sdcc 
+
+MODEL		= large
+CPPFLAGS	=
+CFLAGS		= --debug --model-$(MODEL)
+LDFLAGS		=
+LIBS		=
+
+ALL		= $(MAIN) $(OTHERS)
+OBJECTS		= $(MAIN).rel $(OTHERS:=.rel)
+
+APP		?= $(MAIN)
+
+all: $(APP).hex
+
+dep: $(APP).dep
+
+$(APP).dep: $(OBJECTS:.rel=.c) *.h
+	@>$(APP).dep
+	@for c in $(OBJECTS:.rel=.c); do \
+		$(CC) -MM $(CPPFALGS) $$c >>$(APP).dep ;\
+	done
+
+include $(APP).dep
+
+$(APP).ihx: $(OBJECTS)
+	$(CC) $(CFLAGS) $(LDFLAGS) $(OBJECTS) -o $@
+
+.SUFFIXES: .rel .ihx .hex
+
+.c.rel:
+	$(CC) -c $(CPPFLAGS) $(CFLAGS) $<
+
+.ihx.hex:
+	packihx $< >$@
+
+clean:
+	rm -f $(ALL:=.rel) $(ALL:=.asm) $(ALL:=.lst) $(ALL:=.rst) $(ALL:=.sym) $(ALL:=.adb)
+	rm -f $(MAIN).ihx $(MAIN).hex $(MAIN).lk $(MAIN).map $(MAIN).mem $(MAIN).cdb $(MAIN).omf $(MAIN).noi
+	rm -f $(APP).ihx $(APP).hex $(APP).lk $(APP).map $(APP).mem $(APP).cdb $(APP).omf $(APP).noi
+	rm -f *~
+	rm -f $(MAIN).dep $(APP).dep
+	rm -f $(MAIN).sim $(APP).sim
+
+
+# End of sdcc.mk
diff --git a/sim/ucsim/s51.src/test/serial.c b/sim/ucsim/s51.src/test/serial.c
new file mode 100644
index 0000000..2c5f385
--- /dev/null
+++ b/sim/ucsim/s51.src/test/serial.c
@@ -0,0 +1,216 @@
+#include "hw.h"

+

+#if defined __SDCC || defined SDCC

+#elif defined __C51__

+

+#else /* IAR4 */

+#include <stdio.h>

+#endif

+

+#include "serial.h"

+

+extern __xdata char *simif;

+

+volatile unsigned char serial_buffer[SERIAL_BUFFER_SIZE];

+volatile unsigned char first_occupied, first_free;

+volatile bit serial_sent;

+

+unsigned char

+serial_nuof_received()

+{

+  if (first_free == first_occupied)

+    return 0;

+  else if (first_free > first_occupied)

+    return first_free - first_occupied;

+  else

+    return SERIAL_BUFFER_SIZE - (first_occupied - first_free);

+}

+

+/* Serial line ISR puts received chars into a ring buffer */

+

+#if defined __SDCC || defined SDCC

+void serial_isr(void) __interrupt (4)

+#elif defined __C51__

+void serial_isr(void) interrupt 4

+#else /* IAR4 */

+interrupt void SCON_int(void)

+#endif

+{

+  if (RI)

+    {

+      unsigned char c;

+      unsigned char new, nr;

+      c= SBUF;

+      new= first_free+1;

+      new= new % SERIAL_BUFFER_SIZE;

+      *simif= 'p';*simif= '|';

+      *simif= 'p';*simif= c;

+      *simif= 'p';*simif= '|';

+      if (new != first_occupied)

+	{

+	  serial_buffer[first_free]= c;

+	  first_free= new;

+	}

+      else

+	{

+	  *simif= 'p';*simif= '*';

+	  *simif= 'p';*simif= c;

+	  *simif= 'p';*simif= '*';

+	  P1++;

+	}

+      nr= serial_nuof_received();

+      *simif= 'p';*simif= '/';

+      *simif= 'p';*simif= nr+'0';

+      *simif= 'p';*simif= '/';

+      RI= 0;

+      P0= first_free<<4 + first_occupied;

+    }

+  else if (TI)

+    {

+      serial_sent= 1;

+      TI= 0;

+    }

+}

+

+

+#if defined __SDCC || defined SDCC

+static __sfr __at(0x97) s97;

+#elif defined __C51__

+static sfr s97= 0x97;

+#endif

+

+/* Initialization of serial line */

+

+void

+serial_init(long int br)

+{

+  /* Set  variables */

+  first_free= first_occupied= 0;

+  if (!(serial_sent= 1))

+    serial_dummy();

+  

+  /* Set USART mode: 8 bit variable speed */

+  SCON= 0x40;

+  ES= 1;

+  REN= 1;

+

+  s97= 0xf0;

+  s97= 0x55;

+  if (s97 == 0x55)

+    {

+      beallitas();

+      return;

+    }

+

+  /* Set Timer2 as baudrate generator, XTAL=11.0592MHz */

+  C_T2= 0;

+  CP_RL2= 0;

+  {

+    long int l= (3*115200)/br;

+    TL2= RCAP2L= (65536-l)&0xff; /* 3=115200,6=57600,9=38400,18=19200,36=9600 */

+    TH2= RCAP2H= (65536-l)/256;

+  }

+  RCLK= 1;

+  TCLK= 1;

+  TR2= 1;

+

+  /* Start */

+  EA= 1; /* Enable interrupts */

+}

+

+

+void

+beallitas(void)

+{

+  /* Valtozok beallitasa */

+  if (first_occupied= 0)

+    ;/*serial_dummy();*/

+  first_free= 0;

+  serial_sent= 1;

+

+  /* Timer1 beallitasa 9600 baud-os sebesseg generalasahoz */

+  TMOD= (TMOD & 0x0f) | 0x20;

+  TH1= 0xfd;

+  TL1= 0xfd;

+  PCON&= 0x7f; /* SMOD=0 */

+  ET1= 0;

+  

+  /* Soros vonal beallitasa, 8 bites valtoztathato sebessegu mod */

+  SCON= 0x40;

+  ES= 1;

+  REN= 1;

+  

+  /* Start */

+  TR1= 1;	/* Idozito indul */

+  EA= 1;	/* Megszakitasok engedelyezese */

+}

+

+

+/************************************************** Low level line handling */

+

+/* Blocking send */

+

+unsigned char

+serial_send(unsigned char c)

+{

+  while (!serial_sent) ;

+  SBUF= c;

+  serial_sent= 0;

+  return c;

+}

+

+void

+putchar(char c)

+{

+  serial_send(c);

+}

+

+

+/* Check for recived chars */

+

+unsigned char

+serial_received(void)

+{

+  return first_free != first_occupied;

+}

+

+

+/* Blocking receive */

+

+unsigned char

+serial_receive(void)

+{

+  unsigned char c, nr;

+  

+  while (!serial_received()) ;

+  ES= 0;

+  c= serial_buffer[first_occupied++];

+  first_occupied%= SERIAL_BUFFER_SIZE;

+  nr= serial_nuof_received();

+  *simif= 'p';*simif= '@';

+  *simif= 'p';*simif= nr+'0';

+  *simif= 'p';*simif= '@';

+  ES= 1;

+  return c;

+}

+

+char

+getchar(void)

+{

+  return serial_send(serial_receive());

+}

+

+

+void

+serial_dummy(void)

+{

+  serial_init(0);

+  beallitas();

+  serial_send(0);

+  serial_received();

+  putchar(0);

+  getchar();

+}

+

+

+/* End of serial.c */

diff --git a/sim/ucsim/s51.src/test/serial.h b/sim/ucsim/s51.src/test/serial.h
new file mode 100644
index 0000000..d9d9279
--- /dev/null
+++ b/sim/ucsim/s51.src/test/serial.h
@@ -0,0 +1,32 @@
+#ifndef SERIAL_HEADER

+#define SERIAL_HEADER

+

+

+#define SERIAL_BUFFER_SIZE 8

+

+#if defined __SDCC || defined SDCC

+extern void serial_isr(void) __interrupt(4);

+#elif defined __C51__

+extern void serial_isr(void);

+#else /* IAR4 */

+interrupt void SCON_int(void);

+#endif

+

+extern void serial_init(long int br);

+extern void beallitas(void);

+

+extern unsigned char serial_send(unsigned char c);

+extern unsigned char serial_received(void);

+extern unsigned char serial_receive(void);

+extern unsigned char serial_nuof_received();

+

+#define kikuld(c) serial_send(c)

+#define vetel_volt() serial_received()

+#define vett() serial_receive()

+

+extern void serial_dummy(void);

+

+

+#endif

+

+/* End of serial.h */

diff --git a/sim/ucsim/s51.src/test/st.cmd b/sim/ucsim/s51.src/test/st.cmd
new file mode 100644
index 0000000..746cf38
--- /dev/null
+++ b/sim/ucsim/s51.src/test/st.cmd
@@ -0,0 +1,4 @@
+break xram r 0xfffe
+run
+state
+quit
diff --git a/sim/ucsim/s51.src/test/st.sh b/sim/ucsim/s51.src/test/st.sh
new file mode 100755
index 0000000..df4426d
--- /dev/null
+++ b/sim/ucsim/s51.src/test/st.sh
@@ -0,0 +1,108 @@
+TEST=""
+S51v5=s515
+S51v6=s516
+VER=6
+S51=$S51v6
+
+PROF=""
+
+while [ -n "$1" ]; do
+    case "$1" in
+	-6)
+	    S51=$S51v6
+	    VER=6
+	    shift
+	    ;;
+	-5)
+	    S51=$S51v5
+	    VER=5
+	    shift
+	    ;;
+	-v)
+	    shift
+	    S51=s51-${1}
+	    VER="${1}"
+	    shift
+	    ;;
+	-X)
+	    S51=$S51vX
+	    VER=X
+	    shift
+	    ;;
+	-p)
+	    PROF="p"
+	    shift
+	    ;;
+	-P)
+	    shift
+	    TEST="$1"
+	    CMD="gprof ${S51}p st${TEST}_v${VER}_gmon.out"
+	    echo $CMD
+	    $CMD
+	    exit 0
+	    ;;
+	*)
+	    TEST="$1"
+	    shift
+	    ;;
+    esac
+done
+
+if [ -n "$PROF" ]; then
+    S51=${S51}p
+fi
+
+echo -e "*\n* st${TEST}\n*\n"
+
+make -f st${TEST}.mk clean all
+
+SIM=st${TEST}${VER}.sim
+OUT=st${TEST}${VER}.out
+TIM=st${TEST}${VER}.tim
+CSV=st${TEST}${VER}.csv
+CMD=st${TEST}${VER}.cmd
+
+rm -f $SIM $OUT $TIM $CSV
+
+>$CMD
+echo "set hardware simif xram 0xffff" >>$CMD
+echo "set hardware simif fout \"st${TEST}${VER}.sout\"" >>$CMD
+cat st.cmd >>$CMD
+
+ls -l st${TEST}.ihx
+
+/usr/bin/time -o $TIM -f '
+Elapsed\t%e
+Kernel\t%S
+User\t%U
+In\t%I
+Out\t%O
+SwT\t%c
+SwIO\t%w
+MaxFlt\t%F
+MinFlt\t%R
+Swaps\t%W
+Mem\t%M
+Unshr\t%D
+' $S51 -tC52 -Sin=/dev/null,out=$OUT st${TEST}.ihx <$CMD|tee $SIM
+tee -a $SIM <$TIM
+
+if [ -n "$PROF" ]; then
+    mv gmon.out st${TEST}_v${VER}_gmon.out
+fi
+
+E=$(grep Elapsed $SIM)
+#echo
+#echo $E
+
+E=$(echo $E|cut -d ' ' -f 2)
+C=$(grep 'Total time' $SIM|sed 's/^[^(]*(//'|sed 's/ .*//')
+S=$(echo "scale=3;${C}/${E}/1000000"|bc)
+ST=$(grep 'Simulated ' $SIM|cut -d' ' -f5)
+echo "st${TEST} speed= $S Mclk/sec"|tee -a $SIM
+
+echo "st${TEST},${VER},${E},${S}"|tee $CSV
+
+echo $E >st${TEST}${VER}_e.txt
+echo $ST >st${TEST}${VER}_st.txt
+echo $S >st${TEST}${VER}_s.txt
diff --git a/sim/ucsim/s51.src/test/st_list.txt b/sim/ucsim/s51.src/test/st_list.txt
new file mode 100644
index 0000000..c8e13e7
--- /dev/null
+++ b/sim/ucsim/s51.src/test/st_list.txt
@@ -0,0 +1,8 @@
+n
+p
+rr
+s
+t
+xr
+xrw
+xw
diff --git a/sim/ucsim/s51.src/test/stest.sh b/sim/ucsim/s51.src/test/stest.sh
new file mode 100755
index 0000000..4f60a55
--- /dev/null
+++ b/sim/ucsim/s51.src/test/stest.sh
@@ -0,0 +1,51 @@
+VERS="504 505 606 610 615 620 625 645"
+
+TESTS=$(cat st_list.txt)
+
+rm -f *.csv
+echo -n "versions " >st_e.csv
+echo -n "versions " >st_st.csv
+echo -n "versions " >st_s.csv
+for v in $VERS; do
+    echo -n ", v${v}" >>st_e.csv
+    echo -n ", v${v}" >>st_st.csv
+    echo -n ", v${v}" >>st_s.csv
+done
+echo >>st_e.csv
+echo >>st_st.csv
+echo >>st_s.csv
+
+for t in $TESTS; do
+    for v in $VERS; do
+	make -f st${t}.mk clean all
+	./st.sh -v $v $t
+    done
+
+    (
+	echo -n "st${t} "
+	for v in $VERS; do
+	     echo -n ", $(cat st${t}${v}_e.txt) "
+	done
+	echo
+    ) >st${t}_e.csv
+    cat st${t}_e.csv >>st_e.csv
+    
+    (
+	echo -n "st${t} "
+	for v in $VERS; do
+	     echo -n ", $(cat st${t}${v}_st.txt) "
+	done
+	echo
+    ) >st${t}_st.csv
+    cat st${t}_st.csv >>st_st.csv
+    
+    (
+	echo -n "st${t} "
+	for v in $VERS; do
+	     echo -n ", $(cat st${t}${v}_s.txt) "
+	done
+	echo
+    ) >st${t}_s.csv
+    cat st${t}_s.csv >>st_s.csv
+
+done
diff --git a/sim/ucsim/s51.src/test/stn.c b/sim/ucsim/s51.src/test/stn.c
new file mode 100644
index 0000000..b5048bf
--- /dev/null
+++ b/sim/ucsim/s51.src/test/stn.c
@@ -0,0 +1,35 @@
+char c1;
+char *ptr1_data;
+char *ptr2_idata;
+char *ptr3_pdata;
+char *ptr4_xdata;
+char *ptr5_code;
+char c2;
+
+unsigned char __xdata * volatile sif;
+
+void
+main(void)
+{
+  volatile unsigned int i, j;
+  volatile __xdata int xi;
+  volatile int __xdata xii;
+  
+  sif= (unsigned char __xdata *)0xffff;
+  xi= 1;
+  xii= 2;
+  c1= 'A';
+  c2= 'B';
+  
+  for (j= 0; j<10; j++)
+    for (i= 0; i<0xfff0; i++)
+      {
+	ptr1_data = (__data  char *)(0x1122); // 22 00 40
+	ptr2_idata= (__idata char *)(0x3344); // 44 00 40
+	ptr3_pdata= (__pdata char *)(0x5566); // 66 00 60
+	ptr4_xdata= (__xdata char *)(0x7788); // 88 77 00
+	ptr5_code = (__code  char *)(0x99aa); // aa 99 80
+      }
+  * (char __idata *) 0 = * (char __xdata *) 0xfffe;
+  *sif= 's';
+}
diff --git a/sim/ucsim/s51.src/test/stn.mk b/sim/ucsim/s51.src/test/stn.mk
new file mode 100644
index 0000000..697ba4f
--- /dev/null
+++ b/sim/ucsim/s51.src/test/stn.mk
@@ -0,0 +1,5 @@
+MAIN		= stn
+
+include sdcc.mk
+
+MODEL		= small
diff --git a/sim/ucsim/s51.src/test/stp.c b/sim/ucsim/s51.src/test/stp.c
new file mode 100644
index 0000000..12c31b5
--- /dev/null
+++ b/sim/ucsim/s51.src/test/stp.c
@@ -0,0 +1,20 @@
+#include "hw.h"
+
+unsigned char __xdata * volatile sif;
+
+void
+main(void)
+{
+  volatile unsigned int i, j;
+  sif= (unsigned char __xdata *)0xffff;
+  for (j= 0; j<10; j++)
+    for (i= 0; i<0xfff0; i++)
+      {
+	P0= P1+1;
+	P1++;
+	P2= P3+1;
+	P3++;
+      }
+  * (char __idata *) 0 = * (char __xdata *) 0xfffe;
+  *sif= 's';
+}
diff --git a/sim/ucsim/s51.src/test/stp.mk b/sim/ucsim/s51.src/test/stp.mk
new file mode 100644
index 0000000..d034b33
--- /dev/null
+++ b/sim/ucsim/s51.src/test/stp.mk
@@ -0,0 +1,5 @@
+MAIN		= stp
+
+include sdcc.mk
+
+MODEL		= small
diff --git a/sim/ucsim/s51.src/test/strr.c b/sim/ucsim/s51.src/test/strr.c
new file mode 100644
index 0000000..d1cc203
--- /dev/null
+++ b/sim/ucsim/s51.src/test/strr.c
@@ -0,0 +1,16 @@
+
+unsigned char __xdata * volatile sif;
+
+void
+main(void)
+{
+  volatile unsigned int i, j, x;
+  __code char *p= (__code char *)0;
+
+  sif= (unsigned char __xdata *)0xffff;
+  for (j= 0; j<10; j++)
+    for (i= 0; i<0xfff0; i++)
+      x= p[i];
+  * (char __idata *) 0 = * (char __xdata *) 0xfffe;
+  *sif= 's';
+}
diff --git a/sim/ucsim/s51.src/test/strr.mk b/sim/ucsim/s51.src/test/strr.mk
new file mode 100644
index 0000000..bb27978
--- /dev/null
+++ b/sim/ucsim/s51.src/test/strr.mk
@@ -0,0 +1,5 @@
+MAIN		= strr
+
+include sdcc.mk
+
+MODEL		= small
diff --git a/sim/ucsim/s51.src/test/sts.c b/sim/ucsim/s51.src/test/sts.c
new file mode 100644
index 0000000..3cd9ffa
--- /dev/null
+++ b/sim/ucsim/s51.src/test/sts.c
@@ -0,0 +1,22 @@
+#include <stdio.h>
+#include "serial.h"
+#include "print.h"
+
+unsigned char __xdata * volatile sif;
+
+void
+main(void)
+{
+  volatile unsigned int i;
+  __code char *p= (__code char *)0;
+
+  sif= (unsigned char __xdata *)0xffff;
+  serial_init(19200);
+  for (i= 1; i<0x4000; i++)
+    {
+      print_cx(p[i]);
+      putchar('\n');
+    }
+  * (char __idata *) 0 = * (char __xdata *) 0xfffe;
+  *sif= 's';
+}
diff --git a/sim/ucsim/s51.src/test/sts.mk b/sim/ucsim/s51.src/test/sts.mk
new file mode 100644
index 0000000..743aaac
--- /dev/null
+++ b/sim/ucsim/s51.src/test/sts.mk
@@ -0,0 +1,7 @@
+MAIN		= sts
+
+OTHERS		= serial print
+
+include sdcc.mk
+
+MODEL		= small
diff --git a/sim/ucsim/s51.src/test/stt.c b/sim/ucsim/s51.src/test/stt.c
new file mode 100644
index 0000000..a9905e1
--- /dev/null
+++ b/sim/ucsim/s51.src/test/stt.c
@@ -0,0 +1,68 @@
+#include "hw.h"
+#include "timer.h"
+#include "t0.h"
+
+unsigned char __xdata * volatile sif;
+
+volatile unsigned int tr;
+
+void t0_isr(void) __interrupt (1)
+{
+  T0set(tr);
+}
+
+int var;
+__data  int dvar;
+__idata int ivar;
+__xdata int xvar;
+__pdata int pvar;
+__code  int cvar;
+__sfr   __at(0x81) svar;
+__bit   bvar;
+
+void
+fn(void)
+{
+  volatile int fn_local;
+  volatile int fn_hide;
+  fn_local= fn_hide= 1;
+  {
+    volatile int fn_blocked, fn_hide;
+    fn_blocked= fn_hide= 2;
+  }
+}
+
+void
+sfun(void)
+{
+  return ;
+}
+
+void
+main(void)
+{
+  volatile unsigned int i, x= 0, j;
+  __xdata char *p= (__xdata char *)0;
+
+  bvar= 1;
+  sif= (unsigned char __xdata *)0xffff;
+  tr= T_kezdoertek(10);
+  T0idozito1(0);
+  T0beallit(tr);
+  T0start();
+  ET0= 1;
+  EA= 1;
+
+  for (j=0; j<10; j++)
+    for (i= 0; i<0xfff0; i++)
+      {
+	char c= p[i];
+	unsigned int t= TL0 + (TH0*256);
+	p[i]= t&0xff;
+	if (p[i] != t&0xff)
+	  x++;
+	p[i]= c;
+      }
+  * (char __idata *) 0 = * (char __xdata *) 0xfffe;
+  *sif= 's';
+}
diff --git a/sim/ucsim/s51.src/test/stt.mk b/sim/ucsim/s51.src/test/stt.mk
new file mode 100644
index 0000000..0bab42e
--- /dev/null
+++ b/sim/ucsim/s51.src/test/stt.mk
@@ -0,0 +1,7 @@
+MAIN		= stt
+
+OTHERS		= timer t0 serial
+
+include sdcc.mk
+
+MODEL		= small
diff --git a/sim/ucsim/s51.src/test/stt_large.mk b/sim/ucsim/s51.src/test/stt_large.mk
new file mode 100644
index 0000000..92da79b
--- /dev/null
+++ b/sim/ucsim/s51.src/test/stt_large.mk
@@ -0,0 +1,8 @@
+APP		= stt_large
+MAIN		= stt
+
+OTHERS		= timer t0 serial
+
+include sdcc.mk
+
+MODEL		= large
diff --git a/sim/ucsim/s51.src/test/stt_small.mk b/sim/ucsim/s51.src/test/stt_small.mk
new file mode 100644
index 0000000..71672be
--- /dev/null
+++ b/sim/ucsim/s51.src/test/stt_small.mk
@@ -0,0 +1,8 @@
+APP		= stt_small
+MAIN		= stt
+
+OTHERS		= timer t0 serial
+
+include sdcc.mk
+
+MODEL		= small
diff --git a/sim/ucsim/s51.src/test/stxr.c b/sim/ucsim/s51.src/test/stxr.c
new file mode 100644
index 0000000..93bc16d
--- /dev/null
+++ b/sim/ucsim/s51.src/test/stxr.c
@@ -0,0 +1,25 @@
+#include <stdio.h>
+
+unsigned char __xdata * volatile sif;
+
+int putchar(int c)
+{
+  *sif='p';*sif=c;
+}
+
+void
+main(void)
+{
+  volatile unsigned int i, x, j;
+  __xdata char *p= (__xdata char *)0;
+
+  sif= (unsigned char __xdata *)0xffff;
+  for (j= 0; j<10; j++)
+    for (i= 0; i<0xfff0; i++)
+      {
+	//printf("j=%4x i=%4x\n", j, i);
+	x= p[i];
+      }
+  * (char __idata *) 0 = * (char __xdata *) 0xfffe;
+  *sif= 's';
+}
diff --git a/sim/ucsim/s51.src/test/stxr.mk b/sim/ucsim/s51.src/test/stxr.mk
new file mode 100644
index 0000000..710a3e3
--- /dev/null
+++ b/sim/ucsim/s51.src/test/stxr.mk
@@ -0,0 +1,5 @@
+MAIN		= stxr
+
+include sdcc.mk
+
+MODEL		= small
diff --git a/sim/ucsim/s51.src/test/stxrw.c b/sim/ucsim/s51.src/test/stxrw.c
new file mode 100644
index 0000000..db12a80
--- /dev/null
+++ b/sim/ucsim/s51.src/test/stxrw.c
@@ -0,0 +1,22 @@
+
+unsigned char __xdata * volatile sif;
+
+void
+main(void)
+{
+  volatile unsigned int i, x= 0, j;
+  __xdata char *p= (__xdata char *)0;
+
+  sif= (unsigned char __xdata *)0xffff;
+  for (j=0; j<10; j++)
+    for (i= 0; i<0xfff0; i++)
+      {
+	char c= p[i];
+	p[i]= i&0xff;
+	if (p[i] != i&0xff)
+	  x++;
+	p[i]= c;
+      }
+  * (char __idata *) 0 = * (char __xdata *) 0xfffe;
+  *sif= 's';
+}
diff --git a/sim/ucsim/s51.src/test/stxrw.mk b/sim/ucsim/s51.src/test/stxrw.mk
new file mode 100644
index 0000000..33939bf
--- /dev/null
+++ b/sim/ucsim/s51.src/test/stxrw.mk
@@ -0,0 +1,3 @@
+MAIN		= stxrw
+
+include sdcc.mk
diff --git a/sim/ucsim/s51.src/test/stxw.c b/sim/ucsim/s51.src/test/stxw.c
new file mode 100644
index 0000000..a2232d2
--- /dev/null
+++ b/sim/ucsim/s51.src/test/stxw.c
@@ -0,0 +1,16 @@
+
+unsigned char __xdata * volatile sif;
+
+void
+main(void)
+{
+  volatile unsigned int i, j;
+  __xdata char *p= (__xdata char *)0;
+
+  sif= (unsigned char __xdata *)0xffff;
+  for (j=0; j<10; j++)
+    for (i= 0; i<0xfff0; i++)
+      p[i]= i&0xff;
+  * (char __idata *) 0 = * (char __xdata *) 0xfffe;
+  *sif= 's';
+}
diff --git a/sim/ucsim/s51.src/test/stxw.mk b/sim/ucsim/s51.src/test/stxw.mk
new file mode 100644
index 0000000..36d7ba1
--- /dev/null
+++ b/sim/ucsim/s51.src/test/stxw.mk
@@ -0,0 +1,5 @@
+MAIN		= stxw
+
+include sdcc.mk
+
+MODEL		= small
diff --git a/sim/ucsim/s51.src/test/t0.c b/sim/ucsim/s51.src/test/t0.c
new file mode 100644
index 0000000..bb8c42b
--- /dev/null
+++ b/sim/ucsim/s51.src/test/t0.c
@@ -0,0 +1,89 @@
+/*

+  t0.c

+  Segedlet a T0 idozito/szamlalo kezelesehez

+  (c) Drotos Daniel, 2005

+*/

+

+#include "hw.h"

+#include <stdio.h>

+

+#include "timer.h"

+#include "t0.h"

+

+

+

+/* Adott idoziteshez szukseges szamlalo kezdoerteket szamolja ki.

+   A parametert msec-ben kell megadni (kb 0.02-71 kozott) */

+

+unsigned int T0kezdoertek(float ido /* msec */)

+{

+  return T_kezdoertek(ido);

+}

+

+

+/* Idozito uzemmod */

+

+void T0idozito1(bool kapuzott)

+{

+  TR0= 0;

+  TMOD&= 0xf0;

+  TMOD|= 0x01;

+  if (kapuzott)

+    TMOD|= 0x08;

+}

+

+

+/* Szamlalo uzemmod */

+

+void T0szamlalo(bool kapuzott)

+{

+  TR0= 0;

+  TMOD&= 0xf0;

+  TMOD|= 0x01;

+  TMOD|= 0x04;

+  if (kapuzott)

+    TMOD|= 0x08;

+}

+

+

+/* Szamlalo ertek beallitasa */

+

+void T0beallit(unsigned int kezdoertek)

+{

+  TH0= kezdoertek >> 8;

+  TL0= kezdoertek & 0xff;

+}

+

+

+/* Szamlalo ertek beallitasa */

+

+void T0ujratolt(unsigned int kezdoertek)

+{

+  TH0= kezdoertek >> 8;

+  TL0= kezdoertek & 0xff;

+}

+

+

+/* A szamlalo aktualis allapota usec-ben */

+

+float T0eltelt_us(void)

+{

+  unsigned char h, l;

+  h= TH0;

+  l= TL0;

+  return (12.0/Fosc) * ((unsigned int)(h*256+l));

+}

+

+

+/* A szamlalo tulcsordulasaig hatralevo ido usec-ben */

+

+float T0hatravan_us(void)

+{

+  unsigned char h, l;

+  h= TH0;

+  l= TL0;

+  return (12.0/Fosc) * (0x10000 - (unsigned int)(h*256+l));

+}

+

+

+/* End of t0.c */

diff --git a/sim/ucsim/s51.src/test/t0.h b/sim/ucsim/s51.src/test/t0.h
new file mode 100644
index 0000000..528bd91
--- /dev/null
+++ b/sim/ucsim/s51.src/test/t0.h
@@ -0,0 +1,82 @@
+/*

+  T0.h

+  Segedlet a T0 idozito hasznalatahoz

+  (c) Drotos Daniel, 2005

+*/

+

+#ifndef T0_HEADER

+#define T0_HEADER

+

+#ifndef bool

+#define bool char

+#endif

+

+#ifndef FALSE

+#define FALSE 0

+#endif

+

+#ifndef TRUE

+#define TRUE 1

+#endif

+

+

+/*

+  A megadott ideig tarto idoziteshez szukseges

+  szamlalo kezdoerteket szamolja ki. Az idot

+  msec-ben kell megadni, kb 0.02-71.1 kozott.

+  Felhasznalja az Fosc erteket a szamitashoz.

+*/

+extern unsigned int T0kezdoertek(float ido);

+

+

+/*

+  Beallitja a T0-t idozito 1 uzemmodba (leallitja

+  a szamlalot)

+*/

+extern void T0idozito1(bool kapuzott);

+

+

+/*

+  Beallitja a T0-t szamlalo uzemmodba (leallitja

+  a szamlalot.

+*/

+extern void T0szamlalo(bool kapuzott);

+

+

+/*

+  Ez a ket fuggveny a szamlalo aktualis erteket

+  modositja. Egyforma a ketto, az egyik pl a foprogrambol,

+  mig a masik a megszakitas kezelobol hivhato.

+*/

+extern void T0beallit(unsigned int kezdoertek);

+extern void T0ujratolt(unsigned int kezdoertek);

+

+#define T0set(x) { TH0=(x)>>8;TL0=(x)&0xff; }

+

+

+/*

+  A szamlalo elinditasahoz es leallitasahoz hasznalhato

+  makrok

+*/

+#define T0start() TR0=1

+#define T0stop() TR0=0

+

+

+/*

+  A szamlalo aktualis allapota es a tulcsordulasig hatralevo

+  ido usec-ben

+*/

+extern float T0eltelt_us(void);

+extern float T0hatravan_us(void);

+

+/*

+  A szamlalo aktualis allapota es a tulcsordulasig hatralevo

+  ido msec-ben

+*/

+#define T0eltelt() (T0eltelt_us()/1000.0)

+#define T0hatravan() (T0hatravan_us()/1000.0)

+

+

+#endif

+

+/* End of T0.h */

diff --git a/sim/ucsim/s51.src/test/test_extit.c b/sim/ucsim/s51.src/test/test_extit.c
new file mode 100644
index 0000000..f61fd41
--- /dev/null
+++ b/sim/ucsim/s51.src/test/test_extit.c
@@ -0,0 +1,15 @@
+#include <reg51.h>
+
+sfr at 0xa6 WDTRST;
+
+void jaj() interrupt 0 { P2= P0; P0++; }
+
+void main()
+{
+	IT0=0; /* low level triggered */
+	IT0=1; /* falling edge triggered */
+	EX0=1; /* enable ex #0 */
+	EA=1;
+	P0=0;
+	for(;;);
+}
diff --git a/sim/ucsim/s51.src/test/test_idlepd.c b/sim/ucsim/s51.src/test/test_idlepd.c
new file mode 100644
index 0000000..56b6aaa
--- /dev/null
+++ b/sim/ucsim/s51.src/test/test_idlepd.c
@@ -0,0 +1,35 @@
+#include <reg51.h>
+
+sfr at 0xa6 WDTRST;
+
+void jaj_ex0() interrupt 0 { P2= P0; }
+
+void jaj_t0() interrupt 1 { P2= P0; }
+
+void main()
+{
+  TH0= 0x80;
+  TL0= 0x80;
+  TMOD= 0x02;
+
+  IT0=0; /* low level triggered */
+  IT0=1; /* falling edge triggered */
+  EX0=1; /* enable ex #0 */
+  ET0=1; /* en t0 */
+  
+  TR0= 1;
+
+  EA=1;
+  P0=0;
+  while (1)
+    {
+      P0= 0;
+      PCON|= 1;/*idle*/
+      P0++;
+      P0++;
+      P0++;
+    }
+  WDTRST= 0x1e;
+  WDTRST= 0xe1;
+  PCON|= 2;/*pd*/
+}
diff --git a/sim/ucsim/s51.src/test/test_mdu517.c b/sim/ucsim/s51.src/test/test_mdu517.c
new file mode 100644
index 0000000..494fdc7
--- /dev/null
+++ b/sim/ucsim/s51.src/test/test_mdu517.c
@@ -0,0 +1,284 @@
+#include <stdio.h>
+#include <stdint.h>
+#include <stdlib.h>
+
+#include "hw.h"
+#include "serial.h"
+#include "print.h"
+
+#include "c517.h"
+
+#include "mdu517.h"
+
+__xdata char *simif;
+
+unsigned long lop1, lop2, lres, mdu_lres;
+unsigned int iop1, iop2, ires1, ires2, mdu_ires1, mdu_ires2;
+
+int ok, fail, i;
+uint8_t r, shifts;
+
+void
+test_32div16(char verbose)
+{
+  ok= fail= 0;
+  for (i= 0; i<100; i++)
+    {
+      lop1= labs(rand()) * abs(rand());
+      do {
+	iop2= abs(rand()) * abs(rand()%3);
+      }
+      while (!iop2);
+
+      lres= lop1 / iop2;
+      ires1= lop1 % iop2;
+
+      if (verbose)
+	printf("%8lx/%4x %10lu/%5u=%10lu,%5u ", lop1, iop2, lop1, iop2, lres, ires1);
+      r= mdu_32udiv16(lop1, iop2, &mdu_lres, &mdu_ires1);
+      if (verbose)
+	printf("mdu=%10lu,%5u ", mdu_lres, mdu_ires1);
+      if ((lres != mdu_lres) ||
+	  (ires1 != mdu_ires1))
+	{
+	  if (verbose)
+	    printf("fail ");
+	  fail++;
+	}
+      else
+	{
+	  if (verbose)
+	    printf("ok ");
+	  ok++;
+	}
+      if (r &&
+	  verbose)
+	{
+	  if (r&0x80)
+	    printf("err ");
+	  if (r&0x40)
+	    printf("ovr ");
+	}
+      if (verbose)
+	printf("\n");
+    }
+  printf("32div16 test: succ=%d fails=%d\n\n", ok, fail);
+}
+
+void
+test_16div16(char verbose)
+{
+  ok= fail= 0;
+  for (i= 0; i<100; i++)
+    {
+      iop1= abs(rand()) * 1+abs(rand()%2);
+      do {
+	iop2= abs(rand());
+      }
+      while (!iop2);
+
+      ires1= iop1 / iop2;
+      ires2= iop1 % iop2;
+
+      if (verbose)
+	printf("%4x/%4x %5u/%5u=%5u,%5u ", iop1, iop2, iop1, iop2, ires1, ires2);
+      r= mdu_16udiv16(iop1, iop2, &mdu_ires1, &mdu_ires2);
+      if (verbose)
+	printf("mdu=%5u,%5u ", mdu_ires1, mdu_ires2);
+      if ((ires1 != mdu_ires1) ||
+	  (ires2 != mdu_ires2))
+	{
+	  if (verbose)
+	    printf("fail ");
+	  fail++;
+	}
+      else
+	{
+	  if (verbose)
+	    printf("ok ");
+	  ok++;
+	}
+      if (r &&
+	  verbose)
+	{
+	  if (r&0x80)
+	    printf("err ");
+	  if (r&0x40)
+	    printf("ovr ");
+	}
+      if (verbose)
+	printf("\n");
+    }
+  printf("16div16 test: succ=%d fails=%d\n\n", ok, fail);
+}
+
+void
+test_16mul16(char verbose)
+{
+  ok= fail= 0;
+  for (i= 0; i<100; i++)
+    {
+      iop1= abs(rand()) /*+abs(rand())*/;
+      iop2= abs(rand()) /*+abs(rand())*/;
+
+      lres= (unsigned long)iop1 * (unsigned long)iop2;
+
+      if (verbose)
+	printf("%4x*%4x %5u*%5u=%10lu ", iop1, iop2, iop1, iop2, lres);
+      r= mdu_16umul16(iop1, iop2, &mdu_lres);
+      if (verbose)
+	printf("mdu=%10lu ", mdu_lres);
+      if (lres != mdu_lres)
+	{
+	  if (verbose)
+	    printf("fail ");
+	  fail++;
+	}
+      else
+	{
+	  if (verbose)
+	    printf("ok ");
+	  ok++;
+	}
+      if (r &&
+	  verbose)
+	{
+	  if (r&0x80)
+	    printf("err ");
+	}
+      if (verbose)
+	printf("\n");
+    }
+  printf("16mul16 test: succ=%d fails=%d\n\n", ok, fail);
+}
+
+void
+test_norm(char verbose)
+{
+  uint8_t mdu_shifts;
+  
+  ok= fail= 0;
+  for (i= 0; i<100; i++)
+    {
+      do
+	{
+	  lop1= labs(rand()) * abs(rand());
+	}
+      while (lop1 == 0);
+
+      if (lop1 & 0x80000000)
+	{
+	  lres= lop1;
+	  shifts= 0;
+	}
+      else
+	{
+	  shifts= 0;
+	  lres= lop1;
+	  while ((lres & 0x80000000) == 0)
+	    {
+	      lres<<= 1;
+	      shifts++;
+	    }
+	}
+      
+      if (verbose)
+	printf("%8lx< %10lu=%8lx,%2d ", lop1, lop1, lres, shifts);
+      r= mdu_norm(lop1, &mdu_lres, &mdu_shifts);
+      if (verbose)
+	printf("mdu=%8lx,%2d ", mdu_lres, mdu_shifts);
+      if ((lres != mdu_lres) ||
+	  (shifts != mdu_shifts))
+	{
+	  if (verbose)
+	    printf("fail ");
+	  fail++;
+	}
+      else
+	{
+	  if (verbose)
+	    printf("ok ");
+	  ok++;
+	}
+      if (r &&
+	  verbose)
+	{
+	  if (r&0x80)
+	    printf("err ");
+	  if (r&0x40)
+	    printf("ovr ");
+	}
+      if (verbose)
+	printf("\n");
+    }
+  printf("norm test: succ=%d fails=%d\n\n", ok, fail);
+}
+
+void
+test_shift(char verbose)
+{
+  ok= fail= 0;
+  for (i= 0; i<100; i++)
+    {
+      do
+	{
+	  lop1= labs(rand()) * abs(rand());
+	}
+      while (lop1 == 0);
+      do {
+	shifts= rand() & 0x1f;
+      }
+      while (shifts==0);
+      
+      r= rand() & 1;
+
+      if (r)
+	lres= lop1 << shifts;
+      else
+	lres= lop1 >> shifts;
+      
+      if (verbose)
+	printf("%8lx%c%2d=%8lx ", lop1, r?'<':'>', shifts, lres);
+      r= mdu_lshift(lop1, shifts, r, &mdu_lres);
+      if (verbose)
+	printf("mdu=%8lx ", mdu_lres);
+      if (lres != mdu_lres)
+	{
+	  if (verbose)
+	    printf("fail ");
+	  fail++;
+	}
+      else
+	{
+	  if (verbose)
+	    printf("ok ");
+	  ok++;
+	}
+      if (r &&
+	  verbose)
+	{
+	  if (r&0x80)
+	    printf("err ");
+	}
+      if (verbose)
+	printf("\n");
+    }
+  printf("shift test: succ=%d fails=%d\n\n", ok, fail);
+}
+
+void main(void)
+{
+  simif= (__xdata char *)0xffff;
+  serial_init(9600);
+
+  test_32div16(0);
+  test_16div16(0);
+  test_16mul16(0);
+  test_norm(0);
+  test_shift(0);
+  
+  *simif= 's';
+  while (1)
+    {
+    }
+}
diff --git a/sim/ucsim/s51.src/test/test_mdu517.mk b/sim/ucsim/s51.src/test/test_mdu517.mk
new file mode 100644
index 0000000..ade26b7
--- /dev/null
+++ b/sim/ucsim/s51.src/test/test_mdu517.mk
@@ -0,0 +1,7 @@
+MAIN		= test_mdu517
+
+OTHERS		= serial print mdu517
+
+include sdcc.mk
+
+MODEL		= large
diff --git a/sim/ucsim/s51.src/test/test_mdu517.type b/sim/ucsim/s51.src/test/test_mdu517.type
new file mode 100644
index 0000000..4f95481
--- /dev/null
+++ b/sim/ucsim/s51.src/test/test_mdu517.type
@@ -0,0 +1 @@
+517
\ No newline at end of file
diff --git a/sim/ucsim/s51.src/test/test_mdu88x.c b/sim/ucsim/s51.src/test/test_mdu88x.c
new file mode 100644
index 0000000..b519c76
--- /dev/null
+++ b/sim/ucsim/s51.src/test/test_mdu88x.c
@@ -0,0 +1,488 @@
+#include <stdio.h>
+#include <stdint.h>
+#include <stdlib.h>
+
+#include "hw.h"
+#include "serial.h"
+#include "print.h"
+
+#include "xc88x.h"
+
+#include "mdu88x.h"
+
+__xdata char *simif;
+
+unsigned long lop1, lop2, lres, mdu_lres;
+unsigned int iop1, iop2, ires1, ires2, mdu_ires1, mdu_ires2;
+
+signed long slop1, slop2, slres, mdu_slres;
+signed int siop1, siop2, sires1, sires2, mdu_sires1, mdu_sires2;
+
+int ok, fail, i;
+uint8_t r, shifts;
+
+void
+test_32div16(char verbose)
+{
+  ok= fail= 0;
+  for (i= 0; i<100; i++)
+    {
+      lop1= labs(rand()) * abs(rand());
+      do {
+	iop2= abs(rand()) * abs(rand()%3);
+      }
+      while (!iop2);
+
+      lres= lop1 / iop2;
+      ires1= lop1 % iop2;
+
+      if (verbose)
+	printf("%8lx/%4x %10lu/%5u=%10lu,%5u ", lop1, iop2, lop1, iop2, lres, ires1);
+      r= mdu_32udiv16(lop1, iop2, &mdu_lres, &mdu_ires1);
+      if (verbose)
+	printf("mdu=%10lu,%5u ", mdu_lres, mdu_ires1);
+      if ((lres != mdu_lres) ||
+	  (ires1 != mdu_ires1))
+	{
+	  if (verbose)
+	    printf("fail ");
+	  fail++;
+	}
+      else
+	{
+	  if (verbose)
+	    printf("ok ");
+	  ok++;
+	}
+      if (r &&
+	  verbose)
+	{
+	  if (r&0x20)
+	    printf("err ");
+	}
+      if (verbose)
+	printf("\n");
+    }
+  printf("32udiv16 test: succ=%d fails=%d\n\n", ok, fail);
+}
+
+void
+test_32sdiv16(char verbose)
+{
+  ok= fail= 0;
+  for (i= 0; i<100; i++)
+    {
+      do {
+	slop1= (long)rand() * rand() * (rand()%3-1);
+      }
+      while (!slop1);
+      do {
+	siop2= rand() * (rand()%3-1);
+      }
+      while (!siop2);
+
+      slres= slop1 / siop2;
+      sires1= slop1 % siop2;
+
+      if (verbose)
+	printf("%8lx/%4x %+11ld/%+6d=%+11ld,%+6d ",
+	       slop1, siop2,
+	       slop1, siop2,
+	       slres, sires1);
+      r= mdu_32sdiv16(slop1, siop2, &mdu_slres, &mdu_sires1);
+      if (verbose)
+	printf("mdu=%+11ld,%+6d ",
+	       mdu_slres, mdu_sires1);
+      if ((slres != mdu_slres) ||
+	  (sires1 != mdu_sires1))
+	{
+	  if (verbose)
+	    printf("fail ");
+	  fail++;
+	}
+      else
+	{
+	  if (verbose)
+	    printf("ok ");
+	  ok++;
+	}
+      if (r &&
+	  verbose)
+	{
+	  if (r&0x20)
+	    printf("err ");
+	}
+      if (verbose)
+	printf("\n");
+    }
+  printf("32sdiv16 test: succ=%d fails=%d\n\n", ok, fail);
+}
+
+void
+test_16div16(char verbose)
+{
+  ok= fail= 0;
+  for (i= 0; i<100; i++)
+    {
+      iop1= abs(rand()) * 1+abs(rand()%2);
+      do {
+	iop2= abs(rand());
+      }
+      while (!iop2);
+
+      ires1= iop1 / iop2;
+      ires2= iop1 % iop2;
+
+      if (verbose)
+	printf("%4x/%4x %5u/%5u=%5u,%5u ", iop1, iop2, iop1, iop2, ires1, ires2);
+      r= mdu_16udiv16(iop1, iop2, &mdu_ires1, &mdu_ires2);
+      if (verbose)
+	printf("mdu=%5u,%5u ", mdu_ires1, mdu_ires2);
+      if ((ires1 != mdu_ires1) ||
+	  (ires2 != mdu_ires2))
+	{
+	  if (verbose)
+	    printf("fail ");
+	  fail++;
+	}
+      else
+	{
+	  if (verbose)
+	    printf("ok ");
+	  ok++;
+	}
+      if (r &&
+	  verbose)
+	{
+	  if (r&0x20)
+	    printf("err ");
+	}
+      if (verbose)
+	printf("\n");
+    }
+  printf("16udiv16 test: succ=%d fails=%d\n\n", ok, fail);
+}
+
+void
+test_16sdiv16(char verbose)
+{
+  ok= fail= 0;
+  for (i= 0; i<100; i++)
+    {
+      do {
+	siop1= rand() * (rand()%3-2);
+      }
+      while (!siop1);
+      do {
+	siop2= rand()/8 * (rand()%3-2);
+      }
+      while (!siop2);
+
+      sires1= siop1 / siop2;
+      sires2= siop1 % siop2;
+
+      if (verbose)
+	printf("%4x/%4x %+6d/%+6d=%+6d,%+6d ",
+	       siop1, siop2,
+	       siop1, siop2,
+	       sires1, sires2);
+      r= mdu_16sdiv16(siop1, siop2, &mdu_sires1, &mdu_sires2);
+      if (verbose)
+	printf("mdu=%+6d,%+6d ", mdu_sires1, mdu_sires2);
+      if ((sires1 != mdu_sires1) ||
+	  (sires2 != mdu_sires2))
+	{
+	  if (verbose)
+	    printf("fail ");
+	  fail++;
+	}
+      else
+	{
+	  if (verbose)
+	    printf("ok ");
+	  ok++;
+	}
+      if (r &&
+	  verbose)
+	{
+	  if (r&0x20)
+	    printf("err ");
+	}
+      if (verbose)
+	printf("\n");
+    }
+  printf("16sdiv16 test: succ=%d fails=%d\n\n", ok, fail);
+}
+
+void
+test_16mul16(char verbose)
+{
+  ok= fail= 0;
+  for (i= 0; i<100; i++)
+    {
+      iop1= abs(rand()) /*+abs(rand())*/;
+      iop2= abs(rand()) /*+abs(rand())*/;
+
+      lres= (unsigned long)iop1 * (unsigned long)iop2;
+
+      if (verbose)
+	printf("%4x*%4x %5u*%5u=%10lu ", iop1, iop2, iop1, iop2, lres);
+      r= mdu_16umul16(iop1, iop2, &mdu_lres);
+      if (verbose)
+	printf("mdu=%10lu ", mdu_lres);
+      if (lres != mdu_lres)
+	{
+	  if (verbose)
+	    printf("fail ");
+	  fail++;
+	}
+      else
+	{
+	  if (verbose)
+	    printf("ok ");
+	  ok++;
+	}
+      if (r &&
+	  verbose)
+	{
+	  if (r&0x80)
+	    printf("err ");
+	}
+      if (verbose)
+	printf("\n");
+    }
+  printf("16umul16 test: succ=%d fails=%d\n\n", ok, fail);
+}
+
+void
+test_16smul16(char verbose)
+{
+  ok= fail= 0;
+  for (i= 0; i<100; i++)
+    {
+      siop1= rand() * (rand()%3-2);
+      do {
+	siop2= rand()/8 * (rand()%3-2);
+      }
+      while (!siop2);
+
+      slres= siop1 * (signed long)siop2;
+
+      if (verbose)
+	printf("%4x*%4x %+6d*%+6d=%+11ld ",
+	       siop1, siop2,
+	       siop1, siop2,
+	       slres);
+      r= mdu_16smul16(siop1, siop2, &mdu_slres);
+      if (verbose)
+	printf("mdu=%+11ld ", mdu_slres);
+      if (slres != mdu_slres)
+	{
+	  if (verbose)
+	    printf("fail ");
+	  fail++;
+	}
+      else
+	{
+	  if (verbose)
+	    printf("ok ");
+	  ok++;
+	}
+      if (r &&
+	  verbose)
+	{
+	  if (r&0x20)
+	    printf("err ");
+	}
+      if (verbose)
+	printf("\n");
+    }
+  printf("16sumul16 test: succ=%d fails=%d\n\n", ok, fail);
+}
+
+void
+test_norm(char verbose)
+{
+  uint8_t mdu_shifts;
+  
+  ok= fail= 0;
+  for (i= 0; i<100; i++)
+    {
+      do
+	{
+	  lop1= labs(rand()) * abs(rand());
+	}
+      while (lop1 == 0);
+
+      if (lop1 & 0x80000000)
+	{
+	  lres= lop1;
+	  shifts= 0;
+	}
+      else
+	{
+	  shifts= 0;
+	  lres= lop1;
+	  while ((lres & 0x80000000) == 0)
+	    {
+	      lres<<= 1;
+	      shifts++;
+	    }
+	}
+      
+      if (verbose)
+	printf("%8lx< %10lu=%8lx,%2d ", lop1, lop1, lres, shifts);
+      r= mdu_norm(lop1, &mdu_lres, &mdu_shifts);
+      if (verbose)
+	printf("mdu=%8lx,%2d ", mdu_lres, mdu_shifts);
+      if ((lres != mdu_lres) ||
+	  (shifts != mdu_shifts))
+	{
+	  if (verbose)
+	    printf("fail ");
+	  fail++;
+	}
+      else
+	{
+	  if (verbose)
+	    printf("ok ");
+	  ok++;
+	}
+      if (r &&
+	  verbose)
+	{
+	  if (r&0x80)
+	    printf("err ");
+	  if (r&0x40)
+	    printf("ovr ");
+	}
+      if (verbose)
+	printf("\n");
+    }
+  printf("norm test: succ=%d fails=%d\n\n", ok, fail);
+}
+
+void
+test_lshift(char verbose)
+{
+  ok= fail= 0;
+  for (i= 0; i<100; i++)
+    {
+      do
+	{
+	  lop1= labs(rand()) * abs(rand());
+	}
+      while (lop1 == 0);
+      do {
+	shifts= rand() & 0x1f;
+      }
+      while (shifts==0);
+      
+      r= rand() & 1;
+
+      if (r)
+	lres= lop1 << shifts;
+      else
+	lres= lop1 >> shifts;
+      
+      if (verbose)
+	printf("%8lx%c%2d=%8lx ", lop1, r?'<':'>', shifts, lres);
+      r= mdu_lshift(lop1, shifts, r, &mdu_lres);
+      if (verbose)
+	printf("mdu=%8lx ", mdu_lres);
+      if (lres != mdu_lres)
+	{
+	  if (verbose)
+	    printf("fail ");
+	  fail++;
+	}
+      else
+	{
+	  if (verbose)
+	    printf("ok ");
+	  ok++;
+	}
+      if (r &&
+	  verbose)
+	{
+	  if (r&0x80)
+	    printf("err ");
+	}
+      if (verbose)
+	printf("\n");
+    }
+  printf("lshift test: succ=%d fails=%d\n\n", ok, fail);
+}
+
+void
+test_ashift(char verbose)
+{
+  ok= fail= 0;
+  for (i= 0; i<100; i++)
+    {
+      do
+	{
+	  slop1= (long)rand()/64 * rand()/64 * (rand()%3-2+i%2);
+	}
+      while (slop1 == 0);
+      do {
+	shifts= rand() & 0x1f;
+      }
+      while (shifts==0);
+      
+      r= rand() & 1;
+
+      if (r)
+	slres= slop1 << shifts;
+      else
+	slres= slop1 >> shifts;
+      
+      if (verbose)
+	printf("%8lx%c%2d=%8lx ", slop1, r?'<':'>', shifts, slres);
+      r= mdu_ashift(slop1, shifts, r, &mdu_slres);
+      if (verbose)
+	printf("mdu=%8lx ", mdu_slres);
+      if (slres != mdu_slres)
+	{
+	  if (verbose)
+	    printf("fail ");
+	  fail++;
+	}
+      else
+	{
+	  if (verbose)
+	    printf("ok ");
+	  ok++;
+	}
+      if (r &&
+	  verbose)
+	{
+	  if (r&0x20)
+	    printf("err ");
+	}
+      if (verbose)
+	printf("\n");
+    }
+  printf("ashift test: succ=%d fails=%d\n\n", ok, fail);
+}
+
+void main(void)
+{
+  simif= (__xdata char *)0xffff;
+  serial_init(9600);
+
+  test_32div16(0);
+  test_32sdiv16(0);
+  test_16div16(0);
+  test_16sdiv16(0);
+  test_16mul16(0);
+  test_16smul16(0);
+  test_norm(0);
+  test_lshift(0);
+  test_ashift(0);
+  
+  *simif= 's';
+  while (1)
+    {
+    }
+}
diff --git a/sim/ucsim/s51.src/test/test_mdu88x.cmd b/sim/ucsim/s51.src/test/test_mdu88x.cmd
new file mode 100644
index 0000000..3d3ba38
--- /dev/null
+++ b/sim/ucsim/s51.src/test/test_mdu88x.cmd
@@ -0,0 +1,3 @@
+run
+state
+kill
diff --git a/sim/ucsim/s51.src/test/test_mdu88x.mk b/sim/ucsim/s51.src/test/test_mdu88x.mk
new file mode 100644
index 0000000..b325986
--- /dev/null
+++ b/sim/ucsim/s51.src/test/test_mdu88x.mk
@@ -0,0 +1,7 @@
+MAIN		= test_mdu88x
+
+OTHERS		= serial print mdu88x
+
+include sdcc.mk
+
+MODEL		= large
diff --git a/sim/ucsim/s51.src/test/test_mdu88x.type b/sim/ucsim/s51.src/test/test_mdu88x.type
new file mode 100644
index 0000000..414859f
--- /dev/null
+++ b/sim/ucsim/s51.src/test/test_mdu88x.type
@@ -0,0 +1 @@
+xc88x
\ No newline at end of file
diff --git a/sim/ucsim/s51.src/test/test_ser.c b/sim/ucsim/s51.src/test/test_ser.c
new file mode 100644
index 0000000..43f1f7a
--- /dev/null
+++ b/sim/ucsim/s51.src/test/test_ser.c
@@ -0,0 +1,114 @@
+#include "hw.h"
+
+#define BUFSIZE 16
+#define T0H 0xfc
+#define T0L 0x67
+
+unsigned char buf[BUFSIZE];
+unsigned char first_free= 0, last_occupied= 0;
+bit transmitting, overflow;
+volatile int t0cnt;
+
+void ser_it(void) __interrupt (4)
+{
+  unsigned char temp;
+  if (RI) {
+    buf[first_free]= SBUF;
+    first_free= ((temp= first_free)+1) % BUFSIZE;
+    if (first_free == last_occupied) {
+      first_free= temp;
+      overflow= 1;
+    }
+    RI= 0;
+  }
+  if (TI) {
+    transmitting= 0;
+    TI= 0;
+  }
+}
+
+void t0_it(void) __interrupt (1)
+{
+  TL0= T0L;
+  TH0= T0H;
+  if (t0cnt)
+    t0cnt--;
+}
+
+char empty(void)
+{
+  return(first_free == last_occupied);
+}
+
+unsigned char get_ch(void)
+{
+  unsigned char c;
+  c= buf[last_occupied];
+  last_occupied= (last_occupied+1) % BUFSIZE;
+  overflow= 0;
+  return(c);
+}
+
+void send_ch(unsigned char c)
+{
+  while (transmitting) ;
+  transmitting= 1;
+  SBUF= c;
+}
+
+void send_str(char *str)
+{
+  while (*str) {
+    send_ch(*str);
+    str++;
+  }
+}
+
+void process(void)
+{
+  unsigned char c;
+  c= get_ch();
+  if ((c >= 'a' && c <= 'z') ||
+      (c >= 'A' && c <= 'Z'))
+    c^= 0x20;
+  send_ch(c);
+}
+
+void wait(int delay)
+{
+  t0cnt= delay;
+  while (t0cnt)
+    PCON|= 1;
+}
+
+char test(char c)
+{
+  return(c+1);
+}
+
+void main(void)
+{
+  t0cnt= 0;
+  transmitting= overflow= 0;
+  SCON= 0x7c;
+  TL1= TH1= 250; /* 9600 baud */
+  TH0= T0H;
+  TL0= T0L;
+  TMOD= 0x21;
+  TR0= TR1= 1;
+  ES= ET0= 1;
+  EA= 1;
+  send_str("\nOK\n");
+  test(0);
+  wait(1000);
+  test(1);
+  send_str("delay off\n");
+  for (;;) {
+    if (!empty()) {
+      if (overflow) {
+	send_str("Overflow!\n");
+      }
+      process();
+    }
+  }
+}
diff --git a/sim/ucsim/s51.src/test/test_ser.mk b/sim/ucsim/s51.src/test/test_ser.mk
new file mode 100644
index 0000000..272ce85
--- /dev/null
+++ b/sim/ucsim/s51.src/test/test_ser.mk
@@ -0,0 +1,7 @@
+MAIN		= test_ser
+
+OTHERS		= 
+
+include sdcc.mk
+
+MODEL		= small
diff --git a/sim/ucsim/s51.src/test/test_stack.c b/sim/ucsim/s51.src/test/test_stack.c
new file mode 100644
index 0000000..25ba88d
--- /dev/null
+++ b/sim/ucsim/s51.src/test/test_stack.c
@@ -0,0 +1,9 @@
+void jaj(void)
+{
+	jaj();
+}
+
+void main(void)
+{
+	jaj();
+}
diff --git a/sim/ucsim/s51.src/test/tim_ser.c b/sim/ucsim/s51.src/test/tim_ser.c
new file mode 100644
index 0000000..91d109a
--- /dev/null
+++ b/sim/ucsim/s51.src/test/tim_ser.c
@@ -0,0 +1,73 @@
+#include "hw.h"
+
+#include "serial.h"
+#include "t0.h"
+#include "timer.h"
+#include "print.h"
+
+#define T0H 0xfc
+#define T0L 0x67
+
+unsigned int t0cnt;
+__xdata char *simif;
+
+void t0_it(void) __interrupt (1)
+{
+  TL0= T0L;
+  TH0= T0H;
+  if (t0cnt)
+    t0cnt--;
+}
+
+char min='a', max='z';
+
+void process(void)
+{
+  unsigned char c;
+  c= serial_receive();
+  if ((c >= 'a' && c <= 'z') ||
+      (c >= 'A' && c <= 'Z'))
+    {
+      c^= 0x20;
+      min= 'a';
+      max= 'z';
+      P1= 1;
+    }
+  if ((c >= '0') && (c <= '9'))
+    {
+      min= '0';
+      max= '9';
+      P1= 2;
+    }
+  print_c(c);
+}
+
+void main(void)
+{
+  char c= 'a';
+  beallitas();
+  
+  t0cnt= T_kezdoertek(1);
+  TL0= t0cnt & 0xff;
+  TH0= t0cnt >> 8;
+  T0idozito1(0);
+  T0beallit(t0cnt);
+  ET0= 1;
+  T0start();
+  EA= 1;
+  print("\nStart\n");
+
+  t0cnt= 10;
+  for (;;)
+    {
+      if (serial_received())
+	process();
+      if (!t0cnt)
+	{
+	  print_c(c);
+	  if (++c > max)
+	    c= min;
+	  t0cnt= 10;
+	}
+    }
+}
diff --git a/sim/ucsim/s51.src/test/tim_ser.mk b/sim/ucsim/s51.src/test/tim_ser.mk
new file mode 100644
index 0000000..6a2e4d2
--- /dev/null
+++ b/sim/ucsim/s51.src/test/tim_ser.mk
@@ -0,0 +1,7 @@
+MAIN		= tim_ser
+
+OTHERS		= timer t0 serial print
+
+include sdcc.mk
+
+MODEL		= small
diff --git a/sim/ucsim/s51.src/test/timer.c b/sim/ucsim/s51.src/test/timer.c
new file mode 100644
index 0000000..057644a
--- /dev/null
+++ b/sim/ucsim/s51.src/test/timer.c
@@ -0,0 +1,27 @@
+#include "timer.h"

+

+

+float Fosc= 11.0592; /* MHz, Oszcillator orajel */

+

+

+/* Adott idoziteshez szukseges szamlalo kezdoerteket szamolja ki.

+   A parametert msec-ben kell megadni (kb 0.02-71 kozott) */

+

+unsigned int T_kezdoertek(float ido /* msec */)

+{

+  float tper;	/* szamlalo periodusideje */

+  //float per;	/* szukseges periodusok szama */

+

+  tper= 12.0/Fosc;

+  /* atvaltas usec-be */

+  ido*= 1000.0;

+  /* Max 65529 lepes */

+  if (ido > tper*65529.0)

+    return 0;

+  /* Min 20 lepes */

+  if (ido < tper*20.0)

+    return 0xffff-20;

+  //per= ido/tper;

+  return (unsigned int)(65541.0-ido/tper);

+}

+

diff --git a/sim/ucsim/s51.src/test/timer.h b/sim/ucsim/s51.src/test/timer.h
new file mode 100644
index 0000000..e043fae
--- /dev/null
+++ b/sim/ucsim/s51.src/test/timer.h
@@ -0,0 +1,17 @@
+#ifndef TIMER_HEADER

+#define TIMER_HEADER

+

+/*

+  Oszcillator orajele MHz-ben. Kezdoerteke 11.0592

+*/

+extern float Fosc;

+

+/*

+  A megadott ideig tarto idoziteshez szukseges

+  szamlalo kezdoerteket szamolja ki. Az idot

+  msec-ben kell megadni, kb 0.02-71.1 kozott.

+  Felhasznalja az Fosc erteket a szamitashoz.

+*/

+extern unsigned int T_kezdoertek(float ido);

+

+#endif

diff --git a/sim/ucsim/s51.src/test/xc88x.h b/sim/ucsim/s51.src/test/xc88x.h
new file mode 100644
index 0000000..fe4e110
--- /dev/null
+++ b/sim/ucsim/s51.src/test/xc88x.h
@@ -0,0 +1,14 @@
+#ifndef XC88X_HEADER
+#define XC88X_HEADER
+
+__sfr __at (0xB2) MD0;
+__sfr __at (0xB3) MD1;
+__sfr __at (0xB4) MD2;
+__sfr __at (0xB5) MD3;
+__sfr __at (0xB6) MD4;
+__sfr __at (0xB7) MD5;
+
+__sfr __at (0xB1) MDUCON;
+__sfr __at (0xB0) MDUSTAT;
+
+#endif
diff --git a/sim/ucsim/s51.src/timer0.cc b/sim/ucsim/s51.src/timer0.cc
new file mode 100644
index 0000000..936a795
--- /dev/null
+++ b/sim/ucsim/s51.src/timer0.cc
@@ -0,0 +1,433 @@
+/*
+ * Simulator of microcontrollers (timer0.cc)
+ *
+ * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#include "timer0cl.h"
+#include "regs51.h"
+#include "types51.h"
+#include "uc51cl.h"
+
+
+cl_timer0::cl_timer0(class cl_uc *auc, int aid, const char *aid_string):
+  cl_hw(auc, HW_TIMER, aid, aid_string)
+{
+  cell_tmod= cell_tcon= 0;
+  if (aid == 0)
+    {
+      mask_M0  = bmM00;
+      mask_M1  = bmM10;
+      mask_C_T = bmC_T0;
+      mask_GATE= bmGATE0;
+      mask_TR  = bmTR0;
+      mask_INT = bm_INT0;
+      mask_TF  = bmTF0;
+      mask_T   = bmT0;
+      addr_tl  = TL0;
+      addr_th  = TH0;
+      addr_tcon= TCON;
+    }
+  else if (aid == 1)
+    {
+      mask_M0  = bmM01;
+      mask_M1  = bmM11;
+      mask_C_T = bmC_T1;
+      mask_GATE= bmGATE1;
+      mask_TR  = bmTR1;
+      mask_INT = bm_INT1;
+      mask_TF  = bmTF1;
+      mask_T   = bmT1;
+      addr_tl  = TL1;
+      addr_th  = TH1;
+      addr_tcon= TCON;
+    }
+  else if (aid == 2)
+    {
+      addr_tl  = TL2;
+      addr_th  = TH2;
+      mask_T   = bmT2;
+      mask_C_T = bmC_T2;
+      mask_TR  = bmTR2;
+      mask_TF  = bmTF2;
+      mask_M0= mask_M1= mask_GATE= mask_INT= 0;
+      addr_tcon= T2CON;
+    }
+  else {}
+  make_partner(HW_PCA, 0);
+  make_partner(HW_PCA, 1);
+  make_partner(HW_PCA, 2);
+  make_partner(HW_PCA, 3);
+  make_partner(HW_PCA, 4);
+}
+
+int
+cl_timer0::init(void)
+{
+  class cl_address_space *sfr= uc->address_space(MEM_SFR_ID);
+  int i;
+  
+  cl_hw::init();
+  bas= uc->address_space("bits");
+  if (sfr)
+    {
+      //t_mem d;
+      if (id == 0 || id == 1)
+	{
+	  cell_tmod= register_cell(sfr, TMOD);
+	  cell_tcon= register_cell(sfr, TCON);
+	  INT= sfr->read(P3) & mask_INT;
+	}
+      else if (id == 2)
+	{
+	  cell_tmod= 0;
+	  cell_tcon= register_cell(sfr, T2CON);
+	}
+      cell_tl= sfr->get_cell(addr_tl);//use_cell(sfr, addr_tl);
+      cell_th= sfr->get_cell(addr_th);//use_cell(sfr, addr_th);
+    }
+  for (i= 0; i < 8; i++)
+    {
+      tcon_bits[i]= register_cell(bas, addr_tcon + i);
+    }
+  return(0);
+}
+
+void
+cl_timer0::added_to_uc(void)
+{
+  class cl_address_space *sfr= uc->address_space(MEM_SFR_ID);
+  class cl_it_src *is;
+  
+  if (id == 0)
+    {
+      uc->it_sources->add(is= new cl_it_src(uc, bmET0,
+					    sfr->get_cell(IE), bmET0,
+					    sfr->get_cell(TCON), bmTF0,
+					    0x000b, true, false,
+					    "timer #0", 2));
+      is->init();
+    }
+  else if (id == 1)
+    {
+      uc->it_sources->add(is= new cl_it_src(uc, bmET1,
+					    sfr->get_cell(IE), bmET1,
+					    sfr->get_cell(TCON), bmTF1,
+					    0x001b, true, false,
+					    "timer #1", 4));
+      is->init();
+    }
+}
+
+/*t_mem
+cl_timer0::read(class cl_cell *cell)
+{
+  return(cell->get());
+}*/
+
+void
+cl_timer0::write(class cl_memory_cell *cell, t_mem *val)
+{
+  t_addr ba;
+  bool b= bas->is_owned(cell, &ba);
+  u8_t n= *val;
+  
+  if (b)
+    {
+      u8_t m= 1 << (ba - addr_tcon);
+      n= cell_tcon->get();
+      if (*val)
+	n|= m;
+      else
+	n&= ~m;
+    }
+  if (cell == cell_tmod)
+    {
+      t_mem md= *val & (mask_M0|mask_M1);
+      if (md == mask_M0)
+	mode= 1;
+      else if (md == mask_M1)
+	mode= 2;
+      else if (md == (mask_M0|mask_M1))
+	mode= 3;
+      else
+	mode= 0;
+      GATE= *val & mask_GATE;
+      C_T = *val & mask_C_T;
+      T_edge= 0;
+    }
+  else if ((cell == cell_tcon) ||
+	   b)
+    {
+      TR= n & mask_TR;
+      T_edge= 0;
+    }
+}
+
+/*void
+cl_timer0::mem_cell_changed(class cl_m *mem, t_addr addr)
+{
+  //class cl_m *sfr= uc->mem(MEM_SFR);
+  //t_mem d;
+
+  cl_hw::mem_cell_changed(mem, addr);
+
+  //d= cell_tmod->get();
+  //write(cell_tmod, &d);
+  //d= cell_tcon->get();
+  //write(cell_tcon, &d);
+  //if (addr == addr_tl) cell_tl= sfr->get_cell(addr_tl);
+  //if (addr == addr_th) cell_th= sfr->get_cell(addr_th);
+}*/
+
+int
+cl_timer0::tick(int cycles)
+{
+  switch (mode)
+    {
+    case 0: do_mode0(cycles); break;
+    case 1: do_mode1(cycles); break;
+    case 2: do_mode2(cycles); break;
+    case 3: do_mode3(cycles); break;
+    }
+  return(resGO);
+}
+
+int
+cl_timer0::do_mode0(int cycles)
+{
+  if (!TR)
+    return(0);
+
+  //t_mem p3= uc->mem(MEM_SFR)->get(P3);
+  if (GATE)
+    {
+      if ((/*p3 & mask_*/INT) == 0)
+	return(0);
+    }
+
+  if (C_T)
+    {
+      /*cycles= 0;
+      if ((uc51->prev_p3 & mask_T) &&
+	  !(p3 & uc51->port_pins[3] & mask_T))
+	  cycles= 1;*/
+      cycles= T_edge;
+      T_edge= 0;
+    }
+  while (cycles--)
+    {
+      // mod 0, TH= 8 bit t/c, TL= 5 bit precounter
+      t_mem tl= cell_tl->add(1);
+      if ((tl & 0x1f) == 0)
+	{
+	  cell_tl->set(0);
+	  if (!cell_th->add(1))
+	    {
+	      cell_tcon->set_bit1(mask_TF);
+	      overflow();
+	    }
+	}
+    }
+
+  return(0);
+}
+
+int
+cl_timer0::do_mode1(int cycles)
+{
+  if (!TR)
+    return(0);
+
+  //t_mem p3= uc->mem(MEM_SFR)->get(P3);
+  if (GATE)
+    {
+      if ((/*p3 & mask_*/INT) == 0)
+	return(0);
+    }
+
+  if (C_T)
+    {
+      /*cycles= 0;
+      if ((uc51->prev_p3 & mask_T) &&
+	  !(p3 & uc51->port_pins[3] & mask_T))
+	  cycles= 1;*/
+      cycles= T_edge;
+      T_edge= 0;
+    }
+
+  while (cycles--)
+    {
+      // mod 1 TH+TL= 16 bit t/c
+      if (!cell_tl->add(1))
+	{
+	  if (!cell_th->add(1))
+	    {
+	      cell_tcon->set_bit1(mask_TF);
+	      overflow();
+	    }
+	}
+    }
+
+  return(0);
+}
+
+int
+cl_timer0::do_mode2(int cycles)
+{
+  if (!TR)
+    return(0);
+
+  //t_mem p3= uc->mem(MEM_SFR)->get(P3);
+  if (GATE)
+    {
+      if ((/*p3 & mask_*/INT) == 0)
+	return(0);
+    }
+
+  if (C_T)
+    {
+      /*cycles= 0;
+      if ((uc51->prev_p3 & mask_T) &&
+	  !(p3 & uc51->port_pins[3] & mask_T))
+	  cycles= 1;*/
+      cycles= T_edge;
+      T_edge= 0;
+    }
+
+  //unsigned long startt= uc->ticks->ticks-(cycles*12);int i=0;
+  while (cycles--)
+    {
+      // mod 2 TL= 8 bit t/c auto reload from TH
+      if (!cell_tl->add(1))
+	{
+	  cell_tl->set(cell_th->get());
+	  cell_tcon->set_bit1(mask_TF);
+	  //printf("timer%d overflow %d (%d) %d\n",id,uc->ticks->ticks,i,startt+(i*12));
+	  overflow();
+	}
+      //i++;
+    }
+  return(0);
+}
+
+int
+cl_timer0::do_mode3(int cycles)
+{
+  int cyc= cycles;
+  //t_mem p3= uc->mem(MEM_SFR)->get(P3);
+
+  if (!TR)
+    goto do_th;
+
+  if (GATE)
+    {
+      if ((/*p3 & mask_*/INT) == 0)
+	goto do_th;
+    }
+
+  if (C_T)
+    {
+      /*cycles= 0;
+      if ((uc51->prev_p3 & mask_T) &&
+	  !(p3 & uc51->port_pins[3] & mask_T))
+	  cycles= 1;*/
+      cycles= T_edge;
+      T_edge= 0;
+    }
+
+  while (cycles--)
+    {
+      if (!cell_tl->add(1))
+	{
+	  cell_tcon->set_bit1(mask_TF);
+	  overflow();
+	}
+    }
+
+ do_th:
+  if ((cell_tcon->get() & bmTR1) != 0)
+    while (cyc--)
+      {
+	if (!cell_th->add(1))
+	  cell_tcon->set_bit1(bmTF1);
+      }
+  return(0);
+}
+
+void
+cl_timer0::overflow(void)
+{
+  inform_partners(EV_OVERFLOW, 0);
+}
+
+void
+cl_timer0::happen(class cl_hw *where, enum hw_event he, void *params)
+{
+  struct ev_port_changed *ep= (struct ev_port_changed *)params;
+
+  if (where->cathegory == HW_PORT &&
+      he == EV_PORT_CHANGED &&
+      ep->id == 3)
+    {
+      t_mem p3n= ep->new_pins & ep->new_value;
+      t_mem p3o= ep->pins & ep->prev_value;
+      if ((p3n & mask_T) &&
+	  !(p3o & mask_T))
+	T_edge++;
+      INT= p3n & mask_INT;
+      //printf("timer%d p%dchanged (%02x,%02x->%02x,%02x) INT=%d(%02x) edge=%d(%02x)\n",id,where->id,ep->prev_value,ep->pins,ep->new_value,ep->new_pins,INT,mask_INT,T_edge,mask_T);
+    }
+}
+
+void
+cl_timer0::print_info(class cl_console_base *con)
+{
+  const char *modes[]= { "13 bit", "16 bit", "8 bit autoreload", "2x8 bit" };
+  //t_mem tmod= cell_tmod->get();
+  int on;
+  class cl_address_space *sfr= uc->address_space(MEM_SFR_ID);
+
+  con->dd_printf("%s[%d] 0x%04x", id_string, id,
+		 256*cell_th->get()+cell_tl->get());
+  //int mode= tmod & (bmM00|bmM10);
+  con->dd_printf(" %s", modes[mode]);
+  con->dd_printf(" %s", (/*tmod&bm*/C_T/*0*/)?"counter":"timer");
+  if (/*tmod&bm*/GATE/*0*/)
+    {
+      con->dd_printf(" gated");
+      on= INT;
+    }
+  else
+    on= TR;
+  con->dd_printf(" %s", on?"ON":"OFF");
+  con->dd_printf(" irq=%c", (cell_tcon->get()&mask_TF)?'1':'0');
+  con->dd_printf(" %s", sfr?"?":((sfr->get(IE)&bmET0)?"en":"dis"));
+  con->dd_printf(" prio=%d", uc->priority_of(bmPT0));
+  con->dd_printf("\n");
+  print_cfg_info(con);
+}
+
+
+/* End of s51.src/timer0.cc */
diff --git a/sim/ucsim/s51.src/timer0cl.h b/sim/ucsim/s51.src/timer0cl.h
new file mode 100644
index 0000000..87f7292
--- /dev/null
+++ b/sim/ucsim/s51.src/timer0cl.h
@@ -0,0 +1,76 @@
+/*
+ * Simulator of microcontrollers (timer0cl.h)
+ *
+ * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#ifndef TIMER0CL_HEADER
+#define TIMER0CL_HEADER
+
+#include "stypes.h"
+#include "pobjcl.h"
+#include "uccl.h"
+
+#include "newcmdcl.h"
+
+#include "uc51cl.h"
+
+
+class cl_timer0: public cl_hw
+{
+protected:
+  class cl_memory_cell *cell_tmod, *cell_tcon, *cell_tl, *cell_th;
+  class cl_memory_cell *tcon_bits[8];
+  class cl_address_space *bas;
+  t_mem mask_M0, mask_M1, mask_C_T, mask_GATE, mask_TR, mask_INT,
+    mask_T, mask_TF;
+  t_addr addr_tl, addr_th, addr_tcon;
+  int mode, GATE, C_T, TR, INT, T_edge;
+public:
+  cl_timer0(class cl_uc *auc, int aid, const char *aid_string);
+  virtual int init(void);
+  //virtual char *cfg_help(t_addr addr);
+  
+  virtual void added_to_uc(void);
+
+  //virtual t_mem read(class cl_cell *cell);
+  virtual void write(class cl_memory_cell *cell, t_mem *val);
+  
+  //virtual void mem_cell_changed(class cl_mem *mem, t_addr addr);
+
+  virtual int tick(int cycles);
+  virtual int do_mode0(int cycles);
+  virtual int do_mode1(int cycles);
+  virtual int do_mode2(int cycles);
+  virtual int do_mode3(int cycles);
+  virtual void overflow(void);
+  virtual void happen(class cl_hw *where, enum hw_event he, void *params);
+
+  virtual void print_info(class cl_console_base *con);
+};
+
+
+#endif
+
+/* End of s51.src/timer0cl.h */
diff --git a/sim/ucsim/s51.src/timer1.cc b/sim/ucsim/s51.src/timer1.cc
new file mode 100644
index 0000000..4cd2103
--- /dev/null
+++ b/sim/ucsim/s51.src/timer1.cc
@@ -0,0 +1,93 @@
+/*
+ * Simulator of microcontrollers (s51.src/timer1.cc)
+ *
+ * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#include "timer1cl.h"
+#include "regs51.h"
+
+
+cl_timer1::cl_timer1(class cl_uc *auc, int aid, const char *aid_string):
+  cl_timer0(auc, aid, aid_string)
+{
+  make_partner(HW_UART, 0);
+}
+
+/*int
+cl_timer1::init(void)
+{
+  cl_hw::init();
+  return(0);
+}*/
+
+/*void
+cl_timer1::added(class cl_hw *new_hw)
+{
+  if (new_hw->cathegory == HW_UART)
+    hws_to_inform->add(new_hw);
+}*/
+
+int
+cl_timer1::do_mode3(int cycles)
+{
+  return(0);
+}
+
+/*void
+cl_timer1::overflow(void)
+{
+  inform_partners(EV_OVERFLOW, 0);
+}*/
+
+void
+cl_timer1::print_info(class cl_console_base *con)
+{
+  const char *modes[]= { "13 bit", "16 bit", "8 bit autoreload", "stop" };
+  //int tmod= cell_tmod->get();
+  int on;
+  class cl_address_space *sfr= uc->address_space(MEM_SFR_ID);
+
+  con->dd_printf("%s[%d] 0x%04x", id_string, id,
+		 256*cell_th->get()+cell_tl->get());
+  //int mode= (tmod & (bmM11|bmM01)) >> 4;
+  con->dd_printf(" %s", modes[mode]);
+  con->dd_printf(" %s", (/*tmod&bm*/C_T/*1*/)?"counter":"timer");
+  if (/*tmod&bm*/GATE/*1*/)
+    {
+      con->dd_printf(" gated");
+      on= INT;
+    }
+  else
+    on= cell_tcon->get() & mask_TR;
+  con->dd_printf(" %s", on?"ON":"OFF");
+  con->dd_printf(" irq=%c", (cell_tcon->get()&mask_TF)?'1':'0');
+  con->dd_printf(" %s", sfr?"?":((sfr->get(IE)&bmET1)?"en":"dis"));
+  con->dd_printf(" prio=%d", uc->priority_of(bmPT1));
+  con->dd_printf("\n");
+  print_cfg_info(con);
+}
+
+
+/* End of s51.src/timer1.cc */
diff --git a/sim/ucsim/s51.src/timer1cl.h b/sim/ucsim/s51.src/timer1cl.h
new file mode 100644
index 0000000..75619bc
--- /dev/null
+++ b/sim/ucsim/s51.src/timer1cl.h
@@ -0,0 +1,60 @@
+/*
+ * Simulator of microcontrollers (timer1cl.h)
+ *
+ * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#ifndef TIMER1CL_HEADER
+#define TIMER1CL_HEADER
+
+#include "stypes.h"
+#include "pobjcl.h"
+#include "uccl.h"
+
+#include "newcmdcl.h"
+
+#include "timer0cl.h"
+
+class cl_timer1: public cl_timer0
+{
+public:
+  cl_timer1(class cl_uc *auc, int aid, const char *aid_string);
+  //virtual int init(void);
+  //virtual char *cfg_help(t_addr addr);
+
+  //virtual void new_hw_added(class cl_hw *new_hw);
+  //virtual ulong read(class cl_mem *mem, long addr);
+  //virtual void write(class cl_mem *mem, long addr, ulong *val);
+
+  //virtual int tick(int cycles);
+  virtual int do_mode3(int cycles);
+  //virtual void overflow(void);
+
+  virtual void print_info(class cl_console_base *con);
+};
+
+
+#endif
+
+/* End of s51.src/timer1cl.h */
diff --git a/sim/ucsim/s51.src/timer2.cc b/sim/ucsim/s51.src/timer2.cc
new file mode 100644
index 0000000..0114ffb
--- /dev/null
+++ b/sim/ucsim/s51.src/timer2.cc
@@ -0,0 +1,410 @@
+/*
+ * Simulator of microcontrollers (timer2.cc)
+ *
+ * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#include "timer2cl.h"
+#include "regs51.h"
+#include "types51.h"
+
+
+cl_timer2::cl_timer2(class cl_uc *auc, int aid, const char *aid_string,
+		     int afeatures):
+  cl_timer0(auc, /*2*/aid, /*"timer2"*/aid_string)
+{
+  features= afeatures;
+  exf2it= 0;
+  mask_RCLK= bmRCLK;
+  mask_TCLK= bmTCLK;
+  mask_CP_RL2= bmCP_RL2;
+  make_partner(HW_UART, 0);
+  sfr= uc->address_space(MEM_SFR_ID);
+  if (features & (t2_down|t2_clock_out))
+    {
+      cell_t2mod= register_cell(sfr, T2MOD);
+    }
+}
+
+int
+cl_timer2::init(void)
+{
+  cl_timer0::init();
+  cell_rcap2l= sfr->get_cell(RCAP2L);//use_cell(sfr, RCAP2L);
+  cell_rcap2h= sfr->get_cell(RCAP2H);//use_cell(sfr, RCAP2H);
+  if (sfr)
+    bit_t2ex= sfr->read(P1) & bmT2EX;
+  return(0);
+}
+
+void
+cl_timer2::added_to_uc(void)
+{
+  class cl_address_space *sfr= uc->address_space(MEM_SFR_ID);
+  class cl_it_src *is;
+  
+  uc->it_sources->add(is= new cl_it_src(uc, bmET2,
+					sfr->get_cell(IE), bmET2,
+					sfr->get_cell(T2CON), bmTF2,
+					0x002b, false, false,
+					"timer #2 TF2", 7));
+  is->init();
+  exf2it= new cl_it_src(uc, bmET2,
+			sfr->get_cell(IE), bmET2,
+			sfr->get_cell(T2CON), bmEXF2,
+			0x002b, false, false,
+			"timer #2 EXF2", 7);
+  exf2it->init();
+  uc->it_sources->add(exf2it);
+}
+
+void
+cl_timer2::write(class cl_memory_cell *cell, t_mem *val)
+{
+  int oldmode= mode;
+  bool oldtr= TR;
+  t_addr ba;
+  bool b= bas->is_owned(cell, &ba);
+  t_mem n= *val;
+  
+  if (b)
+    {
+      u8_t m= 1 << (ba - addr_tcon);
+      n= cell_tcon->get();
+      if (*val)
+	n|= m;
+      else
+	n&= ~m;
+    }
+  if (exf2it)
+    exf2it->activate();
+  if ((cell == cell_tcon) ||
+      b)
+    {
+      C_T = n & mask_C_T;
+      TR  = n & mask_TR;
+      RCLK= n & mask_RCLK;
+      TCLK= n & mask_TCLK;
+      CP_RL2= n & mask_CP_RL2;
+      EXEN2 = n & bmEXEN2;
+      if (!(RCLK || TCLK) &&
+	  !CP_RL2)
+	mode= T2MODE_RELOAD;
+      else if (!(RCLK || TCLK) &&
+	       CP_RL2)
+	mode= T2MODE_CAPTURE;
+      else if (RCLK || TCLK)
+	mode= T2MODE_BAUDRATE;
+      else
+	mode= T2MODE_OFF;
+      if (mode != oldmode)
+	inform_partners(EV_T2_MODE_CHANGED, &n);
+    }
+  else if (cell == cell_t2mod)
+    {
+      bit_dcen= (*val & bmDCEN) != 0;
+      bit_t2oe= (*val & bmT2OE) != 0;
+      if ((features & t2_down) &&
+	  bit_dcen &&
+	  mode == T2MODE_RELOAD)
+	{
+	  mode= T2MODE_DOWN;
+	  if (exf2it)
+	    exf2it->deactivate();
+	}
+      if ((features & t2_clock_out) &&
+          bit_t2oe)
+        mode= T2MODE_CLKOUT;
+    }
+  if ((mode != oldmode) ||
+      (TR && !oldtr) ||
+      (!TR && oldtr))
+    T_edge= t2ex_edge= 0;
+}
+
+int
+cl_timer2::tick(int cycles)
+{ 
+  switch (mode)
+    {
+    case T2MODE_BAUDRATE:
+      do_t2_baud(cycles);
+      break;
+    case T2MODE_CAPTURE:
+      do_t2_capture(cycles);
+      break;
+    case T2MODE_RELOAD:
+      do_t2_reload(cycles);
+      break;
+    case T2MODE_DOWN:
+      do_t2_down(cycles);
+      break;
+    case T2MODE_CLKOUT:
+      do_t2_clock_out(cycles);
+      break;
+    default: break;
+    }
+  
+  return(resGO);
+}
+
+/*
+ * Baud rate generator mode of Timer #2
+ */
+
+int
+cl_timer2::do_t2_baud(int cycles)
+{
+  if (EXEN2 && t2ex_edge)
+    {
+      cell_tcon->set_bit1(bmEXF2);
+      t2ex_edge= 0;
+    }
+
+  if (!TR)
+    return(0);
+
+  if (C_T)
+    (cycles= T_edge), T_edge= 0;
+  else
+    cycles*= 6;
+
+  while (cycles--)
+    {
+      if (!cell_tl->add(1))
+	if (!cell_th->add(1))
+	  {
+	    cell_th->set(cell_rcap2h->get());
+	    cell_tl->set(cell_rcap2l->get());
+	    inform_partners(EV_OVERFLOW, 0);
+	  }
+    }
+  return(resGO);
+}
+
+
+/*
+ * Capture function of Timer #2
+ */
+
+void
+cl_timer2::do_t2_capture(int cycles)
+{
+  if (EXEN2 && t2ex_edge)
+    {
+      cell_tcon->set_bit1(bmEXF2);
+      cell_rcap2h->set(cell_th->get());
+      cell_rcap2l->set(cell_tl->get());
+      t2ex_edge= 0;
+    }
+
+  if (!TR)
+    return;
+
+  if (C_T)
+    (cycles= T_edge), T_edge= 0;
+
+  if (!cell_tl->add(1))
+    {
+      if (!cell_th->add(1))
+	cell_tcon->set_bit1(bmTF2);
+    }
+}
+
+
+/*
+ * Auto Reload mode of Timer #2, counting UP
+ */
+
+void
+cl_timer2::do_t2_reload(int cycles)
+{
+  if (EXEN2 && t2ex_edge)
+    {
+      cell_tcon->set_bit1(bmEXF2);
+      cell_th->set(cell_rcap2h->get());
+      cell_tl->set(cell_rcap2l->get());
+      t2ex_edge= 0;
+    }
+
+  if (!TR)
+    return;
+
+  if (C_T)
+    (cycles= T_edge), T_edge= 0;
+
+  if (!cell_tl->add(1))
+    {
+      if (!cell_th->add(1))
+	{
+	  cell_tcon->set_bit1(mask_TF);
+	  cell_th->set(cell_rcap2h->get());
+	  cell_tl->set(cell_rcap2l->get());
+	}
+    }
+}
+
+void
+cl_timer2::do_t2_down(int cycles)
+{
+  bool toggle= false;
+
+  if (!TR)
+    return;
+
+  if (C_T)
+    (cycles= T_edge), T_edge= 0;
+
+  if (bit_t2ex)
+    {
+      // UP
+      while (cycles--)
+	if (!cell_tl->add(1))
+	  {
+	    if (!cell_th->add(1))
+	      {
+		cell_tcon->set_bit1(mask_TF);
+		cell_th->set(cell_rcap2h->get());
+		cell_tl->set(cell_rcap2l->get());
+		toggle= true;
+	      }
+	  }
+    }
+  else
+    {
+       // DOWN
+      while (cycles--)
+	{
+	  t_mem l, h;
+	  if ((l= cell_tl->add(-1)) == 0xff)
+	    h= cell_th->add(-1);
+	  else
+	    h= cell_th->get();
+	  if ((u16_t)(h*256+l) <
+	      (u16_t)(cell_rcap2h->get()*256+cell_rcap2l->get()))
+	    {
+	      cell_tcon->set_bit1(mask_TF);
+	      cell_th->set(0xff);
+	      cell_tl->set(0xff);
+	      toggle= true;
+	    }
+	}
+    }
+  if (toggle &&
+      sfr)
+    {
+      class cl_memory_cell *p1= sfr->get_cell(P1);
+      if (p1)
+	p1->set(p1->get() ^ bmEXF2);
+    }
+}
+
+void
+cl_timer2::do_t2_clock_out(int cycles)
+{
+  if (EXEN2 && t2ex_edge)
+    {
+      cell_tcon->set_bit1(bmEXF2);
+      t2ex_edge= 0;
+    }
+
+  if (!TR)
+    return;
+
+  if (C_T)
+    (cycles= T_edge), T_edge= 0;
+  else
+    cycles*= 6;
+
+  while (cycles--)
+    {
+      if (!cell_tl->add(1))
+	if (!cell_th->add(1))
+	  {
+	    cell_th->set(cell_rcap2h->get());
+	    cell_tl->set(cell_rcap2l->get());
+	    inform_partners(EV_OVERFLOW, 0);
+	    if (!C_T &&
+		sfr)
+	      {
+		// toggle T2 on P1
+		class cl_memory_cell *p1= sfr->get_cell(P1);
+		if (p1)
+		  p1->set(p1->get() ^ bmT2);
+	      }
+	  }
+    }
+}
+
+void
+cl_timer2::happen(class cl_hw *where, enum hw_event he, void *params)
+{
+  struct ev_port_changed *ep= (struct ev_port_changed *)params;
+
+  if (where->cathegory == HW_PORT &&
+      he == EV_PORT_CHANGED &&
+      ep->id == 1)
+    {
+      t_mem p1n= ep->new_pins & ep->new_value;
+      t_mem p1o= ep->pins & ep->prev_value;
+      if (!(p1n & mask_T) &&
+	  (p1o & mask_T))
+	T_edge++;
+      if (!(p1n & bmT2EX) &&
+	  (p1o & bmT2EX))
+	t2ex_edge++;
+      bit_t2ex= p1n & bmT2EX;
+    }
+}
+
+void
+cl_timer2::print_info(class cl_console_base *con)
+{
+  int t2con= cell_tcon->get();
+
+  con->dd_printf("%s[%d] 0x%04x", id_string, id,
+		 256*cell_th->get()+cell_tl->get());
+  if (RCLK || TCLK)
+    {
+      con->dd_printf(" baud");
+      if (RCLK)
+	con->dd_printf(" RCLK");
+      if (TCLK)
+	con->dd_printf(" TCLK");
+    }
+  else
+    con->dd_printf(" %s", (CP_RL2)?"capture":"reload");
+  con->dd_printf(" 0x%04x",
+		 256*MU8(cell_rcap2h->get())+MU8(cell_rcap2l->get()));
+  con->dd_printf(" %s", (C_T)?"counter":"timer");
+  con->dd_printf(" %s", (TR)?"ON":"OFF");
+  con->dd_printf(" irq=%c", (t2con&bmTF2)?'1':'0');
+  con->dd_printf(" %s", sfr?"?":((sfr->get(IE)&bmET2)?"en":"dis"));
+  con->dd_printf(" prio=%d", uc->priority_of(bmPT2));
+  con->dd_printf("\n");
+  print_cfg_info(con);
+}
+
+
+/* End of s51.src/timer2.cc */
diff --git a/sim/ucsim/s51.src/timer2cl.h b/sim/ucsim/s51.src/timer2cl.h
new file mode 100644
index 0000000..dc57239
--- /dev/null
+++ b/sim/ucsim/s51.src/timer2cl.h
@@ -0,0 +1,92 @@
+/*
+ * Simulator of microcontrollers (timer2cl.h)
+ *
+ * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#ifndef TIMER2CL_HEADER
+#define TIMER2CL_HEADER
+
+#include "stypes.h"
+#include "pobjcl.h"
+#include "uccl.h"
+
+#include "newcmdcl.h"
+
+#include "timer0cl.h"
+
+
+#define T2MODE_RELOAD	0
+#define T2MODE_CAPTURE	1
+#define T2MODE_BAUDRATE	2
+#define T2MODE_OFF	3
+#define T2MODE_DOWN	4
+#define T2MODE_CLKOUT	5
+
+enum t2_features {
+  t2_default	= 0x01,
+  t2_down	= 0x02,
+  t2_clock_out	= 0x04
+};
+
+
+class cl_timer2: public cl_timer0
+{
+protected:
+  class cl_address_space *sfr;
+  int features;
+  class cl_it_src *exf2it;
+  t_mem mask_RCLK, mask_TCLK, mask_CP_RL2;
+  t_mem RCLK, TCLK, CP_RL2, EXEN2;
+  long t2ex_edge;
+  class cl_memory_cell *cell_rcap2l, *cell_rcap2h, *cell_t2mod;
+  bool bit_dcen, bit_t2oe, bit_t2ex;
+public:
+  cl_timer2(class cl_uc *auc, int aid, const char *aid_string, int afeautres);
+  virtual int init(void);
+  //virtual char *cfg_help(t_addr addr);
+
+  virtual void added_to_uc(void);
+  //virtual void new_hw_added(class cl_hw *new_hw);
+
+  //virtual ulong read(class cl_mem *mem, long addr);
+  virtual void write(class cl_memory_cell *cell, t_mem *val);
+
+  //virtual void mem_cell_changed(class cl_mem *mem, t_addr addr);
+
+  virtual int  tick(int cycles);
+  virtual int  do_t2_baud(int cycles);
+  virtual void do_t2_capture(int cycles);
+  virtual void do_t2_reload(int cycles);
+  virtual void do_t2_down(int cycles);
+  virtual void do_t2_clock_out(int cycles);
+  virtual void happen(class cl_hw *where, enum hw_event he, void *params);
+  
+  virtual void print_info(class cl_console_base *con);
+};
+
+
+#endif
+
+/* End of s51.src/timer2cl.h */
diff --git a/sim/ucsim/s51.src/types51.h b/sim/ucsim/s51.src/types51.h
new file mode 100644
index 0000000..430116c
--- /dev/null
+++ b/sim/ucsim/s51.src/types51.h
@@ -0,0 +1,59 @@
+/*
+ * Simulator of microcontrollers (types51.h)
+ *
+ * Copyright (C) 2002,02 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#ifndef TYPES51_HEADER
+#define TYPES51_HEADER
+
+#include "ddconfig.h"
+
+
+#define SET_BIT(newbit, reg, bitmask) \
+if (newbit) \
+  (mem(MEM_SFR))->set_bit1((reg), (bitmask)); \
+else \
+  (mem(MEM_SFR))->set_bit0((reg), (bitmask));
+#define SFR_SET_BIT(newbit, reg, bitmask) \
+if (newbit) \
+  sfr->set_bit1((reg), (bitmask)); \
+else \
+  sfr->set_bit0((reg), (bitmask));
+//#define GET_C     (get_mem(MEM_SFR, PSW) & bmCY)
+//#define SFR_GET_C (sfr->get(PSW) & bmCY)
+//#define SET_C(newC) SET_BIT((newC), PSW, bmCY)
+//#define SFR_SET_C(newC) SFR_SET_BIT((newC), PSW, bmCY)
+
+
+/* Event parameters */
+struct ev_port_changed {
+  int id;
+  t_addr addr;
+  t_mem prev_value, new_value, pins, new_pins;
+};
+
+#endif
+
+/* End of s51.src/types51.h */
diff --git a/sim/ucsim/s51.src/uc251.cc b/sim/ucsim/s51.src/uc251.cc
new file mode 100644
index 0000000..6ee3757
--- /dev/null
+++ b/sim/ucsim/s51.src/uc251.cc
@@ -0,0 +1,44 @@
+/*
+ * Simulator of microcontrollers (uc251.cc)
+ *
+ * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#include "ddconfig.h"
+
+#include <stdio.h>
+
+#include "uc251cl.h"
+
+
+/*
+ * Making an 251 CPU object
+ */
+
+cl_uc251::cl_uc251(struct cpu_entry *Itype, class cl_sim *asim):
+  cl_uc89c51r(Itype, asim)
+{
+}
+
+/* End of s51.src/uc251.cc */
diff --git a/sim/ucsim/s51.src/uc251cl.h b/sim/ucsim/s51.src/uc251cl.h
new file mode 100644
index 0000000..b71c249
--- /dev/null
+++ b/sim/ucsim/s51.src/uc251cl.h
@@ -0,0 +1,45 @@
+/*
+ * Simulator of microcontrollers (uc251cl.h)
+ *
+ * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#ifndef UC251CL_HEADER
+#define UC251CL_HEADER
+
+#include "ddconfig.h"
+
+#include "uc89c51rcl.h"
+
+
+class cl_uc251: public cl_uc89c51r
+{
+public:
+  cl_uc251(struct cpu_entry *Itype, class cl_sim *asim);
+};
+
+
+#endif
+
+/* End of s51.src/uc251cl.h */
diff --git a/sim/ucsim/s51.src/uc320.cc b/sim/ucsim/s51.src/uc320.cc
new file mode 100644
index 0000000..3da18eb
--- /dev/null
+++ b/sim/ucsim/s51.src/uc320.cc
@@ -0,0 +1,314 @@
+/*
+ * Simulator of microcontrollers (uc320.cc)
+ *
+ * Copyright (C) 2018,18 whitequark
+ *
+ * To contact author send email to whitequark@whitequark.org
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#include "ddconfig.h"
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <ctype.h>
+#include "i_string.h"
+
+#include "glob.h"
+#include "uc320cl.h"
+#include "regs51.h"
+
+struct timing_desc
+{
+  u8_t  opc_a;
+  u8_t  opc_b;
+  bool  mask;
+  int   cycles;
+};
+
+static struct timing_desc uc320_timing_desc[] = {
+  { 0x00, 0x00, false, 1 }, /*inst_nop*/
+  { 0x1f, 0x01,  true, 3 }, /*inst_ajmp_addr*/
+  { 0x02, 0x02, false, 4 }, /*inst_ljmp*/
+  { 0x03, 0x03, false, 1 }, /*inst_rr*/
+  { 0x04, 0x04, false, 1 }, /*inst_inc_a*/
+  { 0x05, 0x05, false, 2 }, /*inst_inc_addr*/
+  { 0x06, 0x07, false, 1 }, /*inst_inc_Sri*/
+  { 0x08, 0x0f, false, 1 }, /*inst_inc_rn*/
+  { 0x10, 0x10, false, 4 }, /*inst_jbc_bit_addr*/
+  { 0x1f, 0x11,  true, 3 }, /*inst_acall_addr*/
+  { 0x12, 0x12, false, 4 }, /*inst_lcall*/
+  { 0x13, 0x13, false, 1 }, /*inst_rrc*/
+  { 0x14, 0x14, false, 1 }, /*inst_dec_a*/
+  { 0x15, 0x15, false, 2 }, /*inst_dec_addr*/
+  { 0x16, 0x17, false, 1 }, /*inst_dec_Sri*/
+  { 0x18, 0x1f, false, 1 }, /*inst_dec_rn*/
+  { 0x20, 0x20, false, 4 }, /*inst_jb_bit_addr*/
+  { 0x22, 0x22, false, 4 }, /*inst_ret*/
+  { 0x23, 0x23, false, 1 }, /*inst_rl*/
+  { 0x24, 0x24, false, 2 }, /*inst_add_a_Sdata*/
+  { 0x25, 0x25, false, 2 }, /*inst_add_a_addr*/
+  { 0x26, 0x27, false, 1 }, /*inst_add_a_Sri*/
+  { 0x28, 0x2f, false, 1 }, /*inst_add_a_rn*/
+  { 0x30, 0x30, false, 4 }, /*inst_jnb_bit_addr*/
+  { 0x32, 0x32, false, 4 }, /*inst_reti*/
+  { 0x33, 0x33, false, 1 }, /*inst_rlc*/
+  { 0x34, 0x34, false, 2 }, /*inst_addc_a_Sdata*/
+  { 0x35, 0x35, false, 2 }, /*inst_addc_a_addr*/
+  { 0x36, 0x37, false, 1 }, /*inst_addc_a_Sri*/
+  { 0x38, 0x3f, false, 1 }, /*inst_addc_a_rn*/
+  { 0x40, 0x40, false, 3 }, /*inst_jc_addr*/
+  { 0x42, 0x42, false, 2 }, /*inst_orl_addr_a*/
+  { 0x43, 0x43, false, 3 }, /*inst_orl_addr_Sdata*/
+  { 0x44, 0x44, false, 2 }, /*inst_orl_a_Sdata*/
+  { 0x45, 0x45, false, 2 }, /*inst_orl_a_addr*/
+  { 0x46, 0x47, false, 1 }, /*inst_orl_a_Sri*/
+  { 0x48, 0x4f, false, 1 }, /*inst_orl_a_rn*/
+  { 0x50, 0x50, false, 3 }, /*inst_jnc_addr*/
+  { 0x52, 0x52, false, 2 }, /*inst_anl_addr_a*/
+  { 0x53, 0x53, false, 3 }, /*inst_anl_addr_Sdata*/
+  { 0x54, 0x54, false, 2 }, /*inst_anl_a_Sdata*/
+  { 0x55, 0x55, false, 2 }, /*inst_anl_a_addr*/
+  { 0x56, 0x57, false, 1 }, /*inst_anl_a_Sri*/
+  { 0x58, 0x5f, false, 1 }, /*inst_anl_a_rn*/
+  { 0x60, 0x60, false, 3 }, /*inst_jz_addr*/
+  { 0x62, 0x62, false, 2 }, /*inst_xrl_addr_a*/
+  { 0x63, 0x63, false, 3 }, /*inst_xrl_addr_Sdata*/
+  { 0x64, 0x64, false, 2 }, /*inst_xrl_a_Sdata*/
+  { 0x65, 0x65, false, 2 }, /*inst_xrl_a_addr*/
+  { 0x66, 0x67, false, 1 }, /*inst_xrl_a_Sri*/
+  { 0x68, 0x6f, false, 1 }, /*inst_xrl_a_rn*/
+  { 0x70, 0x70, false, 3 }, /*inst_jnz_addr*/
+  { 0x72, 0x72, false, 2 }, /*inst_orl_c_bit*/
+  { 0x73, 0x73, false, 3 }, /*inst_jmp_Sa_dptr*/
+  { 0x74, 0x74, false, 2 }, /*inst_mov_a_Sdata*/
+  { 0x75, 0x75, false, 3 }, /*inst_mov_addr_Sdata*/
+  { 0x76, 0x77, false, 2 }, /*inst_mov_Sri_Sdata*/
+  { 0x78, 0x7f, false, 2 }, /*inst_mov_rn_Sdata*/
+  { 0x80, 0x80, false, 3 }, /*inst_sjmp*/
+  { 0x82, 0x82, false, 2 }, /*inst_anl_c_bit*/
+  { 0x83, 0x83, false, 3 }, /*inst_movc_a_Sa_pc*/
+  { 0x84, 0x84, false, 5 }, /*inst_div_ab*/
+  { 0x85, 0x85, false, 3 }, /*inst_mov_addr_addr*/
+  { 0x86, 0x87, false, 2 }, /*inst_mov_addr_Sri*/
+  { 0x88, 0x8f, false, 2 }, /*inst_mov_addr_rn*/
+  { 0x90, 0x90, false, 3 }, /*inst_mov_dptr_Sdata*/
+  { 0x92, 0x92, false, 2 }, /*inst_mov_bit_c*/
+  { 0x93, 0x93, false, 3 }, /*inst_movc_a_Sa_dptr*/
+  { 0x94, 0x94, false, 2 }, /*inst_subb_a_Sdata*/
+  { 0x95, 0x95, false, 2 }, /*inst_subb_a_addr*/
+  { 0x96, 0x97, false, 1 }, /*inst_subb_a_Sri*/
+  { 0x98, 0x9f, false, 1 }, /*inst_subb_a_rn*/
+  { 0xa0, 0xa0, false, 2 }, /*inst_orl_c_Sbit*/
+  { 0xa2, 0xa2, false, 2 }, /*inst_mov_c_bit*/
+  { 0xa3, 0xa3, false, 3 }, /*inst_inc_dptr*/
+  { 0xa4, 0xa4, false, 5 }, /*inst_mul_ab*/
+  { 0xa6, 0xa7, false, 2 }, /*inst_mov_Sri_addr*/
+  { 0xa8, 0xaf, false, 2 }, /*inst_mov_rn_addr*/
+  { 0xb0, 0xb0, false, 2 }, /*inst_anl_c_Sbit*/
+  { 0xb2, 0xb2, false, 2 }, /*inst_cpl_bit*/
+  { 0xb3, 0xb3, false, 1 }, /*inst_cpl_c*/
+  { 0xb4, 0xb4, false, 4 }, /*inst_cjne_a_Sdata_addr*/
+  { 0xb5, 0xb5, false, 4 }, /*inst_cjne_a_addr_addr*/
+  { 0xb6, 0xb7, false, 4 }, /*inst_cjne_Sri_Sdata_addr*/
+  { 0xb8, 0xbf, false, 4 }, /*inst_cjne_rn_Sdata_addr*/
+  { 0xc0, 0xc0, false, 2 }, /*inst_push*/
+  { 0xc2, 0xc2, false, 2 }, /*inst_clr_bit*/
+  { 0xc3, 0xc3, false, 1 }, /*inst_clr_c*/
+  { 0xc4, 0xc4, false, 1 }, /*inst_swap*/
+  { 0xc5, 0xc5, false, 2 }, /*inst_xch_a_addr*/
+  { 0xc6, 0xc7, false, 1 }, /*inst_xch_a_Sri*/
+  { 0xc8, 0xcf, false, 1 }, /*inst_xch_a_rn*/
+  { 0xd0, 0xd0, false, 2 }, /*inst_pop*/
+  { 0xd2, 0xd2, false, 2 }, /*inst_setb_bit*/
+  { 0xd3, 0xd3, false, 1 }, /*inst_setb_c*/
+  { 0xd4, 0xd4, false, 1 }, /*inst_da_a*/
+  { 0xd5, 0xd5, false, 4 }, /*inst_djnz_addr_addr*/
+  { 0xd6, 0xd7, false, 1 }, /*inst_xchd_a_Sri*/
+  { 0xd8, 0xdf, false, 3 }, /*inst_djnz_rn_addr*/
+  { 0xe0, 0xe0, false, 2 }, /*inst_movx_a_Sdptr*/
+  { 0xe2, 0xe3, false, 2 }, /*inst_movx_a_Sri*/
+  { 0xe4, 0xe4, false, 1 }, /*inst_clr_a*/
+  { 0xe5, 0xe5, false, 2 }, /*inst_mov_a_addr*/
+  { 0xe6, 0xe7, false, 1 }, /*inst_mov_a_Sri*/
+  { 0xe8, 0xef, false, 1 }, /*inst_mov_a_rn*/
+  { 0xf0, 0xf0, false, 2 }, /*inst_movx_Sdptr_a*/
+  { 0xf2, 0xf3, false, 2 }, /*inst_movx_Sri_a*/
+  { 0xf4, 0xf4, false, 1 }, /*inst_cpl_a*/
+  { 0xf5, 0xf5, false, 2 }, /*inst_mov_addr_a*/
+  { 0xf6, 0xf7, false, 1 }, /*inst_mov_Sri_a*/
+  { 0xf8, 0xff, false, 1 }, /*inst_mov_rn_a*/
+};
+
+/*
+ * Unpacking the timing table for fast indexing
+ */
+
+static int uc320_timing[0x100];
+
+static void unpack_timing()
+{
+  static bool unpacked;
+  size_t i;
+
+  if (unpacked)
+    return;
+
+  for (i = 0; i < sizeof(uc320_timing_desc) / sizeof(uc320_timing_desc[0]); i++)
+    {
+      struct timing_desc *td = &uc320_timing_desc[i];
+      int opc;
+
+      for (opc = 0; opc < 0x100; opc++)
+        {
+          if ((td->mask && ((opc & td->opc_a) == td->opc_b)) ||
+              (!td->mask && opc >= td->opc_a && opc <= td->opc_b))
+            uc320_timing[opc] = td->cycles;
+        }
+    }
+
+  unpacked = true;
+}
+
+/*
+ * Making an 320 CPU object
+ */
+
+cl_uc320::cl_uc320 (struct cpu_entry *Itype, class cl_sim *asim):
+  cl_uc521 (Itype, asim)
+{
+  unpack_timing();
+}
+
+/*
+ * Setting up SFR area to reset value
+ */
+
+void
+cl_uc320::clear_sfr(void)
+{
+  cl_uc521::clear_sfr();
+  sfr->write(CKCON, 0x01);
+}
+
+/*
+ * Execution
+ */
+
+int
+cl_uc320::exec_inst(void)
+{
+  int res;
+  t_mem code;
+
+  instPC= PC;
+  pending_ticks= 0;
+  code= rom->read(PC);
+  res= cl_uc521::exec_inst();
+
+  if (res != resNOT_DONE)
+    tick(uc320_timing[code] - pending_ticks);
+
+  return(res);
+}
+
+int
+cl_uc320::tick(int cycles)
+{
+  pending_ticks += 1;
+  return(cl_uc521::tick(cycles));
+}
+
+int
+cl_uc320::tick_hw(int cycles)
+{
+  return(cl_uc521::tick_hw(cycles*3));
+}
+
+/*
+ * 0xe0 1 24 MOVX A,@DPTR
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_uc320::instruction_e0/*inst_movx_a_Sdptr*/(t_mem/*uchar*/ code)
+{
+  int res= cl_uc521::instruction_e0(code);
+
+  u8_t stretch= sfr->read(CKCON) & 0x7;
+  cl_uc521::tick(stretch);
+
+  return(res);
+}
+
+
+/*
+ * 0xe2-0xe3 1 24 MOVX A,@Ri
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_uc320::instruction_e2/*inst_movx_a_Sri*/(t_mem/*uchar*/ code)
+{
+  int res= cl_uc521::instruction_e2(code);
+
+  u8_t stretch= sfr->read(CKCON) & 0x7;
+  cl_uc521::tick(stretch);
+
+  return(res);
+}
+
+
+/*
+ * 0xf0 1 24 MOVX @DPTR,A
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_uc320::instruction_f0/*inst_movx_Sdptr_a*/(t_mem/*uchar*/ code)
+{
+  int res= cl_uc521::instruction_f0(code);
+
+  u8_t stretch= sfr->read(CKCON) & 0x7;
+  cl_uc521::tick(stretch);
+
+  return(res);
+}
+
+
+/*
+ * 0xf2-0xf3 1 24 MOVX @Ri,A
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_uc320::instruction_f2/*inst_movx_Sri_a*/(t_mem/*uchar*/ code)
+{
+  int res= cl_uc521::instruction_f2(code);
+
+  u8_t stretch= sfr->read(CKCON) & 0x7;
+  cl_uc521::tick(stretch);
+
+  return(res);
+}
diff --git a/sim/ucsim/s51.src/uc320cl.h b/sim/ucsim/s51.src/uc320cl.h
new file mode 100644
index 0000000..abff96d
--- /dev/null
+++ b/sim/ucsim/s51.src/uc320cl.h
@@ -0,0 +1,56 @@
+/*
+ * Simulator of microcontrollers (s51.src/uc320cl.h)
+ *
+ * Copyright (C) 2018,18 whitequark
+ *
+ * To contact author send email to whitequark@whitequark.org
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#ifndef UC320CL_HEADER
+#define UC320CL_HEADER
+
+#include "uc521cl.h"
+
+class cl_uc320: public cl_uc521
+{
+ public:
+  cl_uc320(struct cpu_entry *Itype, class cl_sim *asim);
+  void clear_sfr(void);
+
+  virtual int clock_per_cycle(void) { return(4); }
+  virtual int tick(int cycles);
+  virtual int tick_hw(int cycles);
+
+ protected:
+  int pending_ticks;
+
+  virtual int exec_inst(void);
+
+  virtual int instruction_e0/*inst_movx_a_Sdptr*/(t_mem/*uchar*/ code); /* e0 */
+  virtual int instruction_e2/*inst_movx_a_Sri*/(t_mem/*uchar*/ code); /* e2,e3 */
+  virtual int instruction_f0/*inst_movx_Sdptr_a*/(t_mem/*uchar*/ code); /* f0 */
+  virtual int instruction_f2/*inst_movx_Sri_a*/(t_mem/*uchar*/ code); /* f2,f3 */
+};
+
+#endif
+
+/* End of s51.src/uc380cl.h */
diff --git a/sim/ucsim/s51.src/uc380.cc b/sim/ucsim/s51.src/uc380.cc
new file mode 100644
index 0000000..caf0572
--- /dev/null
+++ b/sim/ucsim/s51.src/uc380.cc
@@ -0,0 +1,173 @@
+/*
+ * Simulator of microcontrollers (s51.src/uc380.cc)
+ *
+ * Copyright (C) 2017,17 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#include "portcl.h"
+
+#include "uc380cl.h"
+
+
+cl_uc380::cl_uc380(struct cpu_entry *Itype, class cl_sim *asim):
+  cl_uc52(Itype, asim)
+{
+}
+
+int
+cl_uc380::init(void)
+{
+  int ret;
+  ret= cl_uc52::init();
+
+  return ret;
+}
+
+
+void
+cl_uc380::mk_hw_elements(void)
+{
+  cl_uc52::mk_hw_elements();
+
+  class cl_port *p4= new cl_port(this, 4, 0xc7);
+  add_hw(p4);
+  p4->init();
+
+  class cl_port_ui *d= (class cl_port_ui *)get_hw(cchars("dport"), NULL);
+  if (d)
+    {
+      class cl_port_data pd;
+      pd.init();
+      pd.cell_dir= NULL;
+      
+      pd.set_name("P4");
+      pd.cell_p  = p4->cell_p;
+      pd.cell_in = p4->cell_in;
+      pd.keyset  = chars(keysets[4]);
+      pd.basx    = 1;
+      pd.basy    = 4+7;
+      d->add_port(&pd, 4);
+    }
+}
+
+void
+cl_uc380::make_chips(void)
+{
+  cl_uc52::make_chips();
+  sfr_chip->set_name("sfr_0_chip");
+  sfr_f_chip= new cl_memory_chip("sfr_f_chip", 0x80, 8, 0);
+  sfr_f_chip->init();
+  memchips->add(sfr_f_chip);
+}
+
+void
+cl_uc380::decode_sfr(void)
+{
+  cl_uc52::decode_sfr();
+  t_addr sfrpage= 0xbf;
+  class cl_banker *ad;
+
+  ad= new cl_banker(sfr, sfrpage, 0x0f,
+		    sfr, 0xe4, 0xe4);
+  ad->init();
+  ad->set_name("sfr_banker_0xe4");
+  ad->add_bank(0  , sfr_chip  , 0xe4-0x80);
+  ad->add_bank(0xf, sfr_f_chip, 0xe4-0x80);
+  sfr->decoders->add(ad);
+  sfr->undecode_area(ad, 0xe4, 0xe4, NULL);
+  ad->activate(NULL);
+  
+  ad= new cl_banker(sfr, sfrpage, 0x0f,
+		    sfr, 0xc8, 0xc8);
+  ad->init();
+  ad->set_name("sfr_banker_0xc8");
+  ad->add_bank(0  , sfr_chip  , 0xc8-0x80);
+  ad->add_bank(0xf, sfr_f_chip, 0xc8-0x80);
+  sfr->decoders->add(ad);
+  sfr->undecode_area(ad, 0xc8, 0xc8, NULL);
+  ad->activate(NULL);
+  
+  ad= new cl_banker(sfr, sfrpage, 0x0f,
+		    sfr, 0xca, 0xcf);
+  ad->init();
+  ad->set_name("sfr_banker_0xca-0xcf");
+  ad->add_bank(0  , sfr_chip  , 0xca-0x80);
+  ad->add_bank(0xf, sfr_f_chip, 0xca-0x80);
+  sfr->decoders->add(ad);
+  sfr->undecode_area(ad, 0xca, 0xcf, NULL);
+  ad->activate(NULL);
+  
+  ad= new cl_banker(sfr, sfrpage, 0x0f,
+		    sfr, 0xc0, 0xc2);
+  ad->init();
+  ad->set_name("sfr_banker_0xc0-0xc2");
+  ad->add_bank(0  , sfr_chip  , 0xc0-0x80);
+  ad->add_bank(0xf, sfr_f_chip, 0xc0-0x80);
+  sfr->decoders->add(ad);
+  sfr->undecode_area(ad, 0xc0, 0xc2, NULL);
+  ad->activate(NULL);
+  
+  ad= new cl_banker(sfr, sfrpage, 0x0f,
+		    sfr, 0xb9, 0xb9);
+  ad->init();
+  ad->set_name("sfr_banker_0xb9");
+  ad->add_bank(0  , sfr_chip  , 0xb9-0x80);
+  ad->add_bank(0xf, sfr_f_chip, 0xb9-0x80);
+  sfr->decoders->add(ad);
+  sfr->undecode_area(ad, 0xb9, 0xb9, NULL);
+  ad->activate(NULL);
+  
+  ad= new cl_banker(sfr, sfrpage, 0x0f,
+		    sfr, 0xbc, 0xbc);
+  ad->init();
+  ad->set_name("sfr_banker_0xbc");
+  ad->add_bank(0  , sfr_chip  , 0xbc-0x80);
+  ad->add_bank(0xf, sfr_f_chip, 0xbc-0x80);
+  sfr->decoders->add(ad);
+  sfr->undecode_area(ad, 0xbc, 0xbc, NULL);
+  ad->activate(NULL);
+  
+  ad= new cl_banker(sfr, sfrpage, 0x0f,
+		    sfr, 0x91, 0x95);
+  ad->init();
+  ad->set_name("sfr_banker_0x91-0x95");
+  ad->add_bank(0  , sfr_chip  , 0x91-0x80);
+  ad->add_bank(0xf, sfr_f_chip, 0x91-0x80);
+  sfr->decoders->add(ad);
+  sfr->undecode_area(ad, 0x91, 0x95, NULL);
+  ad->activate(NULL);
+  
+  ad->activate(NULL);
+}
+
+void
+cl_uc380::clear_sfr(void)
+{
+  cl_uc52::clear_sfr();
+
+  sfr->write(/*P4*/0xc7, 0xff);
+}
+
+
+/* End of s51.src/uc380.cc */
diff --git a/sim/ucsim/s51.src/uc380cl.h b/sim/ucsim/s51.src/uc380cl.h
new file mode 100644
index 0000000..1884817
--- /dev/null
+++ b/sim/ucsim/s51.src/uc380cl.h
@@ -0,0 +1,49 @@
+/*
+ * Simulator of microcontrollers (s51.src/uc380cl.h)
+ *
+ * Copyright (C) 2017,17 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#ifndef UC380CL_HEADER
+#define UC380CL_HEADER
+
+#include "uc52cl.h"
+
+class cl_uc380: public cl_uc52
+{
+ protected:
+  class cl_memory_chip *sfr_f_chip;
+ public:
+  cl_uc380(struct cpu_entry *Itype, class cl_sim *asim);
+  virtual int init(void);
+  virtual void mk_hw_elements(void);
+  virtual void make_chips(void);
+  virtual void decode_sfr(void);
+  virtual void clear_sfr(void);
+};
+
+
+#endif
+
+/* End of s51.src/uc380cl.h */
diff --git a/sim/ucsim/s51.src/uc390.cc b/sim/ucsim/s51.src/uc390.cc
new file mode 100644
index 0000000..519720f
--- /dev/null
+++ b/sim/ucsim/s51.src/uc390.cc
@@ -0,0 +1,1318 @@
+/*
+ * Simulator of microcontrollers (uc390.cc)
+ *
+ * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
+ *
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ * uc390.cc - module created by Karl Bongers 2001, karl@turbobit.com
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+// Bernhard's ToDo list:
+
+// - implement math accelerator
+// - consider ACON bits
+// - buy some memory to run s51 with 2*4 Meg ROM/XRAM
+
+// strcpy (mem(MEM_ROM) ->addr_format, "0x%06x");
+// strcpy (mem(MEM_XRAM)->addr_format, "0x%06x");
+
+#include "ddconfig.h"
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <ctype.h>
+#include "i_string.h"
+
+#include "glob.h"
+#include "uc390cl.h"
+#include "regs51.h"
+#include "uc390hwcl.h"
+
+
+#include "uc52cl.h"
+#include "regs51.h"
+#include "timer2cl.h"
+
+/*
+ * Names of instructions
+ */
+
+struct dis_entry disass_390f[] = {
+  { 0x00, 0xff, ' ', 1, "NOP"},
+  { 0x01, 0xff, 'A', 3, "AJMP %A"},
+  { 0x02, 0xff, 'L', 4, "LJMP %l"},
+  { 0x03, 0xff, ' ', 1, "RR A"},
+  { 0x04, 0xff, ' ', 1, "INC A"},
+  { 0x05, 0xff, ' ', 2, "INC %a"},
+  { 0x06, 0xff, ' ', 1, "INC @R0"},
+  { 0x07, 0xff, ' ', 1, "INC @R1"},
+  { 0x08, 0xff, ' ', 1, "INC R0"},
+  { 0x09, 0xff, ' ', 1, "INC R1"},
+  { 0x0a, 0xff, ' ', 1, "INC R2"},
+  { 0x0b, 0xff, ' ', 1, "INC R3"},
+  { 0x0c, 0xff, ' ', 1, "INC R4"},
+  { 0x0d, 0xff, ' ', 1, "INC R5"},
+  { 0x0e, 0xff, ' ', 1, "INC R6"},
+  { 0x0f, 0xff, ' ', 1, "INC R7"},
+  { 0x10, 0xff, 'R', 3, "JBC %b,%R"},
+  { 0x11, 0xff, 'a', 3, "ACALL %A"},
+  { 0x12, 0xff, 'l', 4, "LCALL %l"},
+  { 0x13, 0xff, ' ', 1, "RRC A"},
+  { 0x14, 0xff, ' ', 1, "DEC A"},
+  { 0x15, 0xff, ' ', 2, "DEC %a"},
+  { 0x16, 0xff, ' ', 1, "DEC @R0"},
+  { 0x17, 0xff, ' ', 1, "DEC @R1"},
+  { 0x18, 0xff, ' ', 1, "DEC R0"},
+  { 0x19, 0xff, ' ', 1, "DEC R1"},
+  { 0x1a, 0xff, ' ', 1, "DEC R2"},
+  { 0x1b, 0xff, ' ', 1, "DEC R3"},
+  { 0x1c, 0xff, ' ', 1, "DEC R4"},
+  { 0x1d, 0xff, ' ', 1, "DEC R5"},
+  { 0x1e, 0xff, ' ', 1, "DEC R6"},
+  { 0x1f, 0xff, ' ', 1, "DEC R7"},
+  { 0x20, 0xff, 'R', 3, "JB %b,%R"},
+  { 0x21, 0xff, 'A', 3, "AJMP %A"},
+  { 0x22, 0xff, '_', 1, "RET"},
+  { 0x23, 0xff, ' ', 1, "RL A"},
+  { 0x24, 0xff, ' ', 2, "ADD A,#%d"},
+  { 0x25, 0xff, ' ', 2, "ADD A,%a"},
+  { 0x26, 0xff, ' ', 1, "ADD A,@R0"},
+  { 0x27, 0xff, ' ', 1, "ADD A,@R1"},
+  { 0x28, 0xff, ' ', 1, "ADD A,R0"},
+  { 0x29, 0xff, ' ', 1, "ADD A,R1"},
+  { 0x2a, 0xff, ' ', 1, "ADD A,R2"},
+  { 0x2b, 0xff, ' ', 1, "ADD A,R3"},
+  { 0x2c, 0xff, ' ', 1, "ADD A,R4"},
+  { 0x2d, 0xff, ' ', 1, "ADD A,R5"},
+  { 0x2e, 0xff, ' ', 1, "ADD A,R6"},
+  { 0x2f, 0xff, ' ', 1, "ADD A,R7"},
+  { 0x30, 0xff, 'R', 3, "JNB %b,%R"},
+  { 0x31, 0xff, 'a', 3, "ACALL %A"},
+  { 0x32, 0xff, '_', 1, "RETI"},
+  { 0x33, 0xff, ' ', 1, "RLC A"},
+  { 0x34, 0xff, ' ', 2, "ADDC A,#%d"},
+  { 0x35, 0xff, ' ', 2, "ADDC A,%a"},
+  { 0x36, 0xff, ' ', 1, "ADDC A,@R0"},
+  { 0x37, 0xff, ' ', 1, "ADDC A,@R1"},
+  { 0x38, 0xff, ' ', 1, "ADDC A,R0"},
+  { 0x39, 0xff, ' ', 1, "ADDC A,R1"},
+  { 0x3a, 0xff, ' ', 1, "ADDC A,R2"},
+  { 0x3b, 0xff, ' ', 1, "ADDC A,R3"},
+  { 0x3c, 0xff, ' ', 1, "ADDC A,R4"},
+  { 0x3d, 0xff, ' ', 1, "ADDC A,R5"},
+  { 0x3e, 0xff, ' ', 1, "ADDC A,R6"},
+  { 0x3f, 0xff, ' ', 1, "ADDC A,R7"},
+  { 0x40, 0xff, 'r', 2, "JC %r"},
+  { 0x41, 0xff, 'A', 3, "AJMP %A"},
+  { 0x42, 0xff, ' ', 2, "ORL %a,A"},
+  { 0x43, 0xff, ' ', 3, "ORL %a,#%D"},
+  { 0x44, 0xff, ' ', 2, "ORL A,#%d"},
+  { 0x45, 0xff, ' ', 2, "ORL A,%a"},
+  { 0x46, 0xff, ' ', 1, "ORL A,@R0"},
+  { 0x47, 0xff, ' ', 1, "ORL A,@R1"},
+  { 0x48, 0xff, ' ', 1, "ORL A,R0"},
+  { 0x49, 0xff, ' ', 1, "ORL A,R1"},
+  { 0x4a, 0xff, ' ', 1, "ORL A,R2"},
+  { 0x4b, 0xff, ' ', 1, "ORL A,R3"},
+  { 0x4c, 0xff, ' ', 1, "ORL A,R4"},
+  { 0x4d, 0xff, ' ', 1, "ORL A,R5"},
+  { 0x4e, 0xff, ' ', 1, "ORL A,R6"},
+  { 0x4f, 0xff, ' ', 1, "ORL A,R7"},
+  { 0x50, 0xff, 'r', 2, "JNC %r"},
+  { 0x51, 0xff, 'a', 3, "ACALL %A"},
+  { 0x52, 0xff, ' ', 2, "ANL %a,A"},
+  { 0x53, 0xff, ' ', 3, "ANL %a,#%D"},
+  { 0x54, 0xff, ' ', 2, "ANL A,#%d"},
+  { 0x55, 0xff, ' ', 2, "ANL A,%a"},
+  { 0x56, 0xff, ' ', 1, "ANL A,@R0"},
+  { 0x57, 0xff, ' ', 1, "ANL A,@R1"},
+  { 0x58, 0xff, ' ', 1, "ANL A,R0"},
+  { 0x59, 0xff, ' ', 1, "ANL A,R1"},
+  { 0x5a, 0xff, ' ', 1, "ANL A,R2"},
+  { 0x5b, 0xff, ' ', 1, "ANL A,R3"},
+  { 0x5c, 0xff, ' ', 1, "ANL A,R4"},
+  { 0x5d, 0xff, ' ', 1, "ANL A,R5"},
+  { 0x5e, 0xff, ' ', 1, "ANL A,R6"},
+  { 0x5f, 0xff, ' ', 1, "ANL A,R7"},
+  { 0x60, 0xff, 'r', 2, "JZ %r"},
+  { 0x61, 0xff, 'A', 3, "AJMP %A"},
+  { 0x62, 0xff, ' ', 2, "XRL %a,A"},
+  { 0x63, 0xff, ' ', 3, "XRL %a,#%D"},
+  { 0x64, 0xff, ' ', 2, "XRL A,#%d"},
+  { 0x65, 0xff, ' ', 2, "XRL A,%a"},
+  { 0x66, 0xff, ' ', 1, "XRL A,@R0"},
+  { 0x67, 0xff, ' ', 1, "XRL A,@R1"},
+  { 0x68, 0xff, ' ', 1, "XRL A,R0"},
+  { 0x69, 0xff, ' ', 1, "XRL A,R1"},
+  { 0x6a, 0xff, ' ', 1, "XRL A,R2"},
+  { 0x6b, 0xff, ' ', 1, "XRL A,R3"},
+  { 0x6c, 0xff, ' ', 1, "XRL A,R4"},
+  { 0x6d, 0xff, ' ', 1, "XRL A,R5"},
+  { 0x6e, 0xff, ' ', 1, "XRL A,R6"},
+  { 0x6f, 0xff, ' ', 1, "XRL A,R7"},
+  { 0x70, 0xff, 'r', 2, "JNZ %r"},
+  { 0x71, 0xff, 'a', 3, "ACALL %A"},
+  { 0x72, 0xff, ' ', 2, "ORL C,%b"},
+  { 0x73, 0xff, '_', 1, "JMP @A+DPTR"},
+  { 0x74, 0xff, ' ', 2, "MOV A,#%d"},
+  { 0x75, 0xff, ' ', 3, "MOV %a,#%D"},
+  { 0x76, 0xff, ' ', 2, "MOV @R0,#%d"},
+  { 0x77, 0xff, ' ', 2, "MOV @R1,#%d"},
+  { 0x78, 0xff, ' ', 2, "MOV R0,#%d"},
+  { 0x79, 0xff, ' ', 2, "MOV R1,#%d"},
+  { 0x7a, 0xff, ' ', 2, "MOV R2,#%d"},
+  { 0x7b, 0xff, ' ', 2, "MOV R3,#%d"},
+  { 0x7c, 0xff, ' ', 2, "MOV R4,#%d"},
+  { 0x7d, 0xff, ' ', 2, "MOV R5,#%d"},
+  { 0x7e, 0xff, ' ', 2, "MOV R6,#%d"},
+  { 0x7f, 0xff, ' ', 2, "MOV R7,#%d"},
+  { 0x80, 0xff, 's', 2, "SJMP %r"},
+  { 0x81, 0xff, 'A', 3, "AJMP %A"},
+  { 0x82, 0xff, ' ', 2, "ANL C,%b"},
+  { 0x83, 0xff, ' ', 1, "MOVC A,@A+PC"},
+  { 0x84, 0xff, ' ', 1, "DIV AB"},
+  { 0x85, 0xff, ' ', 3, "MOV %8,%a"},
+  { 0x86, 0xff, ' ', 2, "MOV %a,@R0"},
+  { 0x87, 0xff, ' ', 2, "MOV %a,@R1"},
+  { 0x88, 0xff, ' ', 2, "MOV %a,R0"},
+  { 0x89, 0xff, ' ', 2, "MOV %a,R1"},
+  { 0x8a, 0xff, ' ', 2, "MOV %a,R2"},
+  { 0x8b, 0xff, ' ', 2, "MOV %a,R3"},
+  { 0x8c, 0xff, ' ', 2, "MOV %a,R4"},
+  { 0x8d, 0xff, ' ', 2, "MOV %a,R5"},
+  { 0x8e, 0xff, ' ', 2, "MOV %a,R6"},
+  { 0x8f, 0xff, ' ', 2, "MOV %a,R7"},
+  { 0x90, 0xff, ' ', 4, "MOV DPTR,#%l"},
+  { 0x91, 0xff, 'a', 3, "ACALL %A"},
+  { 0x92, 0xff, ' ', 2, "MOV %b,C"},
+  { 0x93, 0xff, ' ', 1, "MOVC A,@A+DPTR"},
+  { 0x94, 0xff, ' ', 2, "SUBB A,#%d"},
+  { 0x95, 0xff, ' ', 2, "SUBB A,%a"},
+  { 0x96, 0xff, ' ', 1, "SUBB A,@R0"},
+  { 0x97, 0xff, ' ', 1, "SUBB A,@R1"},
+  { 0x98, 0xff, ' ', 1, "SUBB A,R0"},
+  { 0x99, 0xff, ' ', 1, "SUBB A,R1"},
+  { 0x9a, 0xff, ' ', 1, "SUBB A,R2"},
+  { 0x9b, 0xff, ' ', 1, "SUBB A,R3"},
+  { 0x9c, 0xff, ' ', 1, "SUBB A,R4"},
+  { 0x9d, 0xff, ' ', 1, "SUBB A,R5"},
+  { 0x9e, 0xff, ' ', 1, "SUBB A,R6"},
+  { 0x9f, 0xff, ' ', 1, "SUBB A,R7"},
+  { 0xa0, 0xff, ' ', 2, "ORL C,/%b"},
+  { 0xa1, 0xff, 'A', 3, "AJMP %A"},
+  { 0xa2, 0xff, ' ', 2, "MOV C,%b"},
+  { 0xa3, 0xff, ' ', 1, "%i DPTR"},
+  { 0xa4, 0xff, ' ', 1, "MUL AB"},
+  { 0xa5, 0xff, '_', 1, "-"},
+  { 0xa6, 0xff, ' ', 2, "MOV @R0,%a"},
+  { 0xa7, 0xff, ' ', 2, "MOV @R1,%a"},
+  { 0xa8, 0xff, ' ', 2, "MOV R0,%a"},
+  { 0xa9, 0xff, ' ', 2, "MOV R1,%a"},
+  { 0xaa, 0xff, ' ', 2, "MOV R2,%a"},
+  { 0xab, 0xff, ' ', 2, "MOV R3,%a"},
+  { 0xac, 0xff, ' ', 2, "MOV R4,%a"},
+  { 0xad, 0xff, ' ', 2, "MOV R5,%a"},
+  { 0xae, 0xff, ' ', 2, "MOV R6,%a"},
+  { 0xaf, 0xff, ' ', 2, "MOV R7,%a"},
+  { 0xb0, 0xff, ' ', 2, "ANL C,/%b"},
+  { 0xb1, 0xff, 'a', 3, "ACALL %A"},
+  { 0xb2, 0xff, ' ', 2, "CPL %b"},
+  { 0xb3, 0xff, ' ', 1, "CPL C"},
+  { 0xb4, 0xff, 'R', 3, "CJNE A,#%d,%R"},
+  { 0xb5, 0xff, 'R', 3, "CJNE A,%a,%R"},
+  { 0xb6, 0xff, 'R', 3, "CJNE @R0,#%d,%R"},
+  { 0xb7, 0xff, 'R', 3, "CJNE @R1,#%d,%R"},
+  { 0xb8, 0xff, 'R', 3, "CJNE R0,#%d,%R"},
+  { 0xb9, 0xff, 'R', 3, "CJNE R1,#%d,%R"},
+  { 0xba, 0xff, 'R', 3, "CJNE R2,#%d,%R"},
+  { 0xbb, 0xff, 'R', 3, "CJNE R3,#%d,%R"},
+  { 0xbc, 0xff, 'R', 3, "CJNE R4,#%d,%R"},
+  { 0xbd, 0xff, 'R', 3, "CJNE R5,#%d,%R"},
+  { 0xbe, 0xff, 'R', 3, "CJNE R6,#%d,%R"},
+  { 0xbf, 0xff, 'R', 3, "CJNE R7,#%d,%R"},
+  { 0xc0, 0xff, ' ', 2, "PUSH %a"},
+  { 0xc1, 0xff, 'A', 3, "AJMP %A"},
+  { 0xc2, 0xff, ' ', 2, "CLR %b"},
+  { 0xc3, 0xff, ' ', 1, "CLR C"},
+  { 0xc4, 0xff, ' ', 1, "SWAP A"},
+  { 0xc5, 0xff, ' ', 2, "XCH A,%a"},
+  { 0xc6, 0xff, ' ', 1, "XCH A,@R0"},
+  { 0xc7, 0xff, ' ', 1, "XCH A,@R1"},
+  { 0xc8, 0xff, ' ', 1, "XCH A,R0"},
+  { 0xc9, 0xff, ' ', 1, "XCH A,R1"},
+  { 0xca, 0xff, ' ', 1, "XCH A,R2"},
+  { 0xcb, 0xff, ' ', 1, "XCH A,R3"},
+  { 0xcc, 0xff, ' ', 1, "XCH A,R4"},
+  { 0xcd, 0xff, ' ', 1, "XCH A,R5"},
+  { 0xce, 0xff, ' ', 1, "XCH A,R6"},
+  { 0xcf, 0xff, ' ', 1, "XCH A,R7"},
+  { 0xd0, 0xff, ' ', 2, "POP %a"},
+  { 0xd1, 0xff, 'a', 3, "ACALL %A"},
+  { 0xd2, 0xff, ' ', 2, "SETB %b"},
+  { 0xd3, 0xff, ' ', 1, "SETB C"},
+  { 0xd4, 0xff, ' ', 1, "DA A"},
+  { 0xd5, 0xff, 'R', 3, "DJNZ %a,%R"},
+  { 0xd6, 0xff, ' ', 1, "XCHD A,@R0"},
+  { 0xd7, 0xff, ' ', 1, "XCHD A,@R1"},
+  { 0xd8, 0xff, 'r', 2, "DJNZ R0,%r"},
+  { 0xd9, 0xff, 'r', 2, "DJNZ R1,%r"},
+  { 0xda, 0xff, 'r', 2, "DJNZ R2,%r"},
+  { 0xdb, 0xff, 'r', 2, "DJNZ R3,%r"},
+  { 0xdc, 0xff, 'r', 2, "DJNZ R4,%r"},
+  { 0xdd, 0xff, 'r', 2, "DJNZ R5,%r"},
+  { 0xde, 0xff, 'r', 2, "DJNZ R6,%r"},
+  { 0xdf, 0xff, 'r', 2, "DJNZ R7,%r"},
+  { 0xe0, 0xff, ' ', 1, "MOVX A,@DPTR"},
+  { 0xe1, 0xff, 'A', 3, "AJMP %A"},
+  { 0xe2, 0xff, ' ', 1, "MOVX A,@R0"},
+  { 0xe3, 0xff, ' ', 1, "MOVX A,@R1"},
+  { 0xe4, 0xff, ' ', 1, "CLR A"},
+  { 0xe5, 0xff, ' ', 2, "MOV A,%a"},
+  { 0xe6, 0xff, ' ', 1, "MOV A,@R0"},
+  { 0xe7, 0xff, ' ', 1, "MOV A,@R1"},
+  { 0xe8, 0xff, ' ', 1, "MOV A,R0"},
+  { 0xe9, 0xff, ' ', 1, "MOV A,R1"},
+  { 0xea, 0xff, ' ', 1, "MOV A,R2"},
+  { 0xeb, 0xff, ' ', 1, "MOV A,R3"},
+  { 0xec, 0xff, ' ', 1, "MOV A,R4"},
+  { 0xed, 0xff, ' ', 1, "MOV A,R5"},
+  { 0xee, 0xff, ' ', 1, "MOV A,R6"},
+  { 0xef, 0xff, ' ', 1, "MOV A,R7"},
+  { 0xf0, 0xff, ' ', 1, "MOVX @DPTR,A"},
+  { 0xf1, 0xff, 'a', 3, "ACALL %A"},
+  { 0xf2, 0xff, ' ', 1, "MOVX @R0,A"},
+  { 0xf3, 0xff, ' ', 1, "MOVX @R1,A"},
+  { 0xf4, 0xff, ' ', 1, "CPL A"},
+  { 0xf5, 0xff, ' ', 2, "MOV %a,A"},
+  { 0xf6, 0xff, ' ', 1, "MOV @R0,A"},
+  { 0xf7, 0xff, ' ', 1, "MOV @R1,A"},
+  { 0xf8, 0xff, ' ', 1, "MOV R0,A"},
+  { 0xf9, 0xff, ' ', 1, "MOV R1,A"},
+  { 0xfa, 0xff, ' ', 1, "MOV R2,A"},
+  { 0xfb, 0xff, ' ', 1, "MOV R3,A"},
+  { 0xfc, 0xff, ' ', 1, "MOV R4,A"},
+  { 0xfd, 0xff, ' ', 1, "MOV R5,A"},
+  { 0xfe, 0xff, ' ', 1, "MOV R6,A"},
+  { 0xff, 0xff, ' ', 1, "MOV R7,A"},
+  { 0, 0, 0, 0, NULL }
+};
+
+/*
+ * Making an 390 CPU object
+ */
+
+cl_uc390::cl_uc390 (struct cpu_entry *Itype, class cl_sim *asim):
+  cl_uc52 (Itype, asim)
+{
+  //flat24_flag= 0;
+  if (Itype->type == CPU_DS390F)
+    {
+      printf ("24-bit flat mode, warning: lots of sfr-functions not implemented!\n");
+      //flat24_flag = 1;
+    }
+  // todo: add interrupt sources
+}
+
+void
+cl_uc390::mk_hw_elements (void)
+{
+  class cl_hw *h;
+
+  cl_uc52::mk_hw_elements();
+  add_hw(h = new cl_uc390_hw (this));
+  h->init();
+}
+
+void
+cl_uc390::make_memories(void)
+{
+  class cl_address_decoder *ad;
+
+  make_address_spaces();
+  dptr= 0;
+  make_chips();
+
+  acc= sfr->get_cell(ACC);
+  psw= sfr->get_cell(PSW);
+
+  decode_regs();
+  decode_rom();
+  decode_iram();
+  decode_sfr();
+  decode_xram();
+  decode_bits();
+  decode_dptr();
+  
+  ad= new cl_address_decoder(ixram, ixram_chip, 0, 0xfff, 0);
+  ad->init();
+  ixram->decoders->add(ad);
+  ad->activate(0);
+}
+
+void
+cl_uc390::make_address_spaces(void)
+{
+  rom= new cl_address_space("rom", 0, 0x20000, 8);
+  rom->init();
+  address_spaces->add(rom);
+  
+  iram= new cl_address_space("iram", 0, 0x100, 8);
+  iram->init();
+  address_spaces->add(iram);
+
+  sfr= new cl_address_space("sfr", 0x80, 0x80, 8);
+  sfr->init();
+  address_spaces->add(sfr);
+
+  xram= new cl_address_space("xram", 0, 0x100000+128, 8);
+  xram->init();
+  address_spaces->add(xram);
+
+  ixram= new cl_address_space("ixram", 0, 0x1000, 8);
+  ixram->init();
+  address_spaces->add(ixram);
+
+  regs= new cl_address_space("regs", 0, 8, 8);
+  regs->init();
+  address_spaces->add(regs);
+
+  bits= new cl_address_space("bits", 0, 0x100, 1);
+  bits->init();
+  address_spaces->add(bits);
+}
+
+void
+cl_uc390::make_chips(void)
+{
+  rom_chip= new cl_memory_chip("rom_chip", 0x20000, 8, 0xff);
+  rom_chip->init();
+  memchips->add(rom_chip);
+
+  iram_chip= new cl_memory_chip("iram_chip", 0x100, 8, 0);
+  iram_chip->init();
+  memchips->add(iram_chip);
+
+  xram_chip= new cl_memory_chip("xram_chip", 0x100000+128, 8, 0);
+  xram_chip->init();
+  memchips->add(xram_chip);
+
+  ixram_chip= new cl_memory_chip("ixram_chip", 0x1000, 8);
+  ixram_chip->init();
+  memchips->add(ixram_chip);
+
+  sfr_chip= new cl_memory_chip("sfr_chip", 0x80, 8, 0);
+  sfr_chip->init();
+  memchips->add(sfr_chip);
+}
+
+void
+cl_uc390::decode_rom(void)
+{
+  class cl_address_decoder *ad;
+  ad= new cl_address_decoder(rom, rom_chip, 0, 0x1ffff, 0);
+  ad->init();
+  rom->decoders->add(ad);
+  ad->activate(0);
+}
+
+void
+cl_uc390::decode_xram(void)
+{
+  class cl_address_decoder *ad;
+  
+  ad= new cl_address_decoder(xram, xram_chip, 0, 0x10007f, 0);
+  ad->init();
+  xram->decoders->add(ad);
+  ad->activate(0);
+}
+
+void
+cl_uc390::decode_dptr(void)
+{
+  cl_var *v;
+  vars->add(v= new cl_var(chars("dpl"), sfr, 0x82, ""));
+  v->init();
+  vars->add(v= new cl_var(chars("DPL"), sfr, 0x82, ""));
+  v->init();
+  vars->add(v= new cl_var(chars("dph"), sfr, 0x83, ""));
+  v->init();
+  vars->add(v= new cl_var(chars("DPH"), sfr, 0x83, ""));
+  v->init();
+}
+
+
+/*
+ * Setting up SFR area to reset value
+ */
+
+void
+cl_uc390::clear_sfr(void)
+{
+  cl_uc52::clear_sfr();
+	  /* SFR   value */
+  sfr->write(0x80, 0xff); /* P4     */
+  sfr->write(0x81, 0x07); /* SP     */
+  sfr->write(0x86, 0x04); /* DPS    */
+  sfr->write(0x90, 0xff); /* P1     */
+  sfr->write(0x92, 0xbf); /* P4CNT  */
+  sfr->write(0x9b, 0xfc); /* ESP    */
+  if (type->type == CPU_DS390F/*flat24_flag*/)
+    {
+      sfr->/*write*/set(ACON, 0xfa); /* ACON; AM1 set: 24-bit flat */
+      //printf("ACON inited to 0xfa, 24 bit flat mode!\n");
+      //printf("CPU type=%d (%x) flag24=%d\n", type, type, flat24_flag);
+    }
+  else
+    sfr->/*write*/set(ACON, 0xf8); /* ACON   */
+  sfr->write(0xa0, 0xff); /* P2     */
+  sfr->write(0xa1, 0xff); /* P5     */
+  sfr->write(0xa3, 0x09); /* COC    */
+  sfr->write(0xb0, 0xff); /* P3     */
+  sfr->write(0xb8, 0x80); /* IP     */
+  sfr->write(0xc5, 0x10); /* STATUS */
+  sfr->write(0xc6, 0x10); /* MCON   */
+  sfr->write(0xc7, 0xff); /* TA     */
+  sfr->write(0xc9, 0xe4); /* T2MOD  */
+  sfr->write(0xd2, 0x2f); /* MCNT1  */
+  sfr->write(0xe3, 0x09); /* C1C    */
+}
+
+
+t_mem
+cl_uc390::read_mem(char *id/*enum mem_class type*/, t_addr addr)
+{
+
+  if (strcmp(/*type*/id,/* == */MEM_XRAM_ID)==0 &&
+      addr >= 0x400000 &&
+      (sfr->get (ACON) & 0x02)) /* AM1 set: 24-bit flat? */
+    {
+      addr -= 0x400000;
+      id/*type*/ = MEM_IXRAM_ID;
+    }
+  return cl_51core::read_mem(id/*type*/, addr); /* 24 bit */
+}
+
+t_mem
+cl_uc390::get_mem (char *id/*enum mem_class type*/, t_addr addr)
+{
+  if (strcmp(/*type*/id/* == */,MEM_XRAM_ID)==0 &&
+      addr >= 0x400000 &&
+      (sfr->get (ACON) & 0x02)) /* AM1 set: 24-bit flat? */
+    {
+      addr -= 0x400000;
+      /*type*/id = MEM_IXRAM_ID;
+    }
+  return cl_51core::get_mem (/*type*/id, addr);
+}
+
+void
+cl_uc390::write_mem (char *id/*enum mem_class type*/, t_addr addr, t_mem val)
+{
+  if (strcmp(/*type ==*/id, MEM_XRAM_ID)==0 &&
+      addr >= 0x400000 &&
+      (sfr->get (ACON) & 0x02)) /* AM1 set: 24-bit flat? */
+    {
+      addr -= 0x400000;
+      /*type*/id = MEM_IXRAM_ID;
+    }
+  cl_51core::write_mem (/*type*/id, addr, val);
+}
+
+void
+cl_uc390::set_mem (/*enum mem_class type*/char *id, t_addr addr, t_mem val)
+{
+  if (/*type == */strcmp(id,MEM_XRAM_ID)==0 &&
+      addr >= 0x400000 &&
+      (sfr->get (ACON) & 0x02)) /* AM1 set: 24-bit flat? */
+    {
+      addr -= 0x400000;
+      /*type*/id = MEM_IXRAM_ID;
+    }
+  cl_51core::set_mem (id/*type*/, addr, val);
+}
+
+/*
+ *____________________________________________________________________________
+ */
+
+void
+cl_uc390::push_byte (t_mem uc)
+{
+  t_addr sp;
+
+  sp = sfr->wadd (SP, 1);
+  if (sfr->get (ACON) & 0x04) /* SA: 10 bit stack */
+    {
+      if (sp == 0) /* overflow SP */
+        sfr->wadd (R51_ESP, 1);
+      sp += (sfr->read (R51_ESP) & 0x3) * 256;
+      write_mem (MEM_IXRAM_ID, sp, uc); // fixme
+    }
+  else
+    {
+      class cl_memory_cell *stck;
+
+      stck = iram->get_cell (sp);
+      stck->write (uc);
+    }
+}
+
+t_mem
+cl_uc390::pop_byte (void)
+{
+  t_mem temp;
+  t_addr sp;
+
+  if (sfr->get (ACON) & 0x04) /* SA: 10 bit stack */
+    {
+      sp = sfr->read (SP);
+      sp += (sfr->read (R51_ESP) & 0x3) * 256;
+      temp = read_mem (MEM_IXRAM_ID, sp); // fixme
+      sp = sfr->wadd (SP, -1);
+      if (sp == 0xff) /* underflow SP */
+        sfr->wadd (R51_ESP, -1);
+      return temp;
+    }
+  else
+    {
+      class cl_memory_cell *stck;
+
+      stck = iram->get_cell (sfr->get (SP));
+      temp = stck->read();
+      sp = sfr->wadd (SP, -1);
+      return temp;
+    }
+}
+
+/*
+ * 0xa3 1 24 INC DPTR
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_uc390::instruction_a3/*inst_inc_dptr*/ (t_mem/*uchar*/ code)
+{
+  ulong dptr;
+
+  uchar pl, ph, px, dps, dec;
+
+  dps = sfr->get (DPS);
+  if (dps & 0x01)
+    {
+      pl = DPL1;
+      ph = DPH1;
+      px = DPX1;
+      dec = 0x80;
+    }
+  else
+    {
+      pl = DPL;
+      ph = DPH;
+      px = DPX;
+      dec = 0x040;
+    }
+
+  dptr = sfr->read (ph) * 256 + sfr->read (pl);
+  if (sfr->get (ACON) & 0x02) /* AM1 set: 24-bit flat? */
+    dptr += sfr->read (px) *256*256;
+  if (dps & dec) /* decr set */
+    dptr--;
+  else
+    dptr++;
+
+  if (sfr->get (ACON) & 0x02) /* AM1 set: 24-bit flat? */
+    sfr->write (px, (dptr >> 16) & 0xff);
+  sfr->write (ph, (dptr >> 8) & 0xff);
+  sfr->write (pl, dptr & 0xff);
+
+  if (dps & 0x20)                      /* auto-switch dptr */
+    sfr->write (DPS, dps ^ 1);  /* toggle dual-dptr switch */
+  tick (1);
+  return resGO;
+}
+
+/*
+ * 0x73 1 24 JMP @A+DPTR
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_uc390::instruction_73/*inst_jmp_Sa_dptr*/ (t_mem/*uchar*/ code)
+{
+  uchar pl, ph, px, dps;
+
+  dps = sfr->get (DPS);
+  if (dps & 0x01)
+    {
+      pl = DPL1;
+      ph = DPH1;
+      px = DPX1;
+    }
+  else
+    {
+      pl = DPL;
+      ph = DPH;
+      px = DPX;
+    }
+
+  PC = rom->validate_address(sfr->read (ph) * 256 + sfr->read (pl) +
+			     acc->read());
+  if (sfr->get (ACON) & 0x02) /* AM1 set: 24-bit flat? */
+    PC += sfr->read (px) * 256*256;
+
+  tick (1);
+  return resGO;
+}
+
+/*
+ * 0x90 3 24 MOV DPTR,#data
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_uc390::instruction_90/*inst_mov_dptr_Sdata*/ (t_mem/*uchar*/ code)
+{
+  uchar pl, ph, px, dps;
+
+  dps = sfr->get (DPS);
+  if (dps & 0x01)
+    {
+      pl = DPL1;
+      ph = DPH1;
+      px = DPX1;
+    }
+  else
+    {
+      pl = DPL;
+      ph = DPH;
+      px = DPX;
+    }
+
+  if (sfr->get (ACON) & 0x02) /* AM1 set: 24-bit flat? */
+    sfr->write (px, fetch ());
+  sfr->write (ph, fetch ());
+  sfr->write (pl, fetch ());
+
+  if (dps & 0x20)                      /* auto-switch dptr */
+    sfr->write (DPS, dps ^ 1);    /* toggle dual-dptr switch */
+
+  tick (1);
+  return resGO;
+}
+
+
+/*
+ * 0x93 1 24 MOVC A,@A+DPTR
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_uc390::instruction_93/*inst_movc_a_Sa_dptr*/ (t_mem/*uchar*/ code)
+{
+  uchar pl, ph, px, dps;
+
+  dps = sfr->get (DPS);
+  if (dps & 0x01)
+    {
+      pl = DPL1;
+      ph = DPH1;
+      px = DPX1;
+    }
+  else
+    {
+      pl = DPL;
+      ph = DPH;
+      px = DPX;
+    }
+
+  if (sfr->get (ACON) & 0x02) /* AM1 set: 24-bit flat? */
+    acc->write (rom->read ((sfr->read (px) * 256*256 +
+			    sfr->read (ph) * 256 + sfr->read (pl) +
+                acc->read())));
+  else
+    acc->write (rom->read ((sfr->read (ph) * 256 + sfr->read (pl) +
+			    acc->read())));
+
+  if (dps & 0x20)                      /* auto-switch dptr */
+    sfr->write (DPS, dps ^ 1);  /* toggle dual-dptr switch */
+
+  tick (1);
+  return resGO;
+}
+
+/*
+ * 0xc0 2 24 PUSH addr
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_uc390::instruction_c0/*inst_push*/ (t_mem/*uchar*/ code)
+{
+  class cl_memory_cell *cell;
+
+  cell = get_direct(fetch());
+  t_addr sp_before= sfr->get(SP);
+  t_mem data;
+  push_byte (data= cell->read());
+  class cl_stack_op *so=
+    new cl_stack_push(instPC, data, sp_before, sfr->get(SP));
+  so->init();
+  stack_write(so);
+  tick (1);
+  return resGO;
+}
+
+
+/*
+ * 0xd0 2 24 POP addr
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_uc390::instruction_d0/*inst_pop*/ (t_mem/*uchar*/ code)
+{
+  class cl_memory_cell *cell;
+
+  t_addr sp_before= sfr->get(SP);
+  t_mem data;
+  cell = get_direct (fetch());
+  cell->write (data= pop_byte());
+  class cl_stack_op *so=
+    new cl_stack_pop(instPC, data, sp_before, sfr->get(SP));
+  so->init();
+  stack_read(so);
+  tick (1);
+  return resGO;
+}
+
+
+/*
+ * 0xe0 1 24 MOVX A,@DPTR
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_uc390::instruction_e0/*inst_movx_a_Sdptr*/ (t_mem/*uchar*/ code)
+{
+  uchar pl, ph, px, dps;
+
+  dps = sfr->get (DPS);
+  if (dps & 0x01)
+    {
+      pl = DPL1;
+      ph = DPH1;
+      px = DPX1;
+    }
+  else
+    {
+      pl = DPL;
+      ph = DPH;
+      px = DPX;
+    }
+
+  if (sfr->get (ACON) & 0x02) /* AM1 set: 24-bit flat? */
+    acc->write (read_mem (MEM_XRAM_ID,
+                sfr->read (px) * 256*256 + sfr->read (ph) * 256 + sfr->read (pl)));
+  else
+    acc->write (read_mem (MEM_XRAM_ID,
+                sfr->read (ph) * 256 + sfr->read (pl)));
+
+  if (dps & 0x20)                      /* auto-switch dptr */
+    sfr->write (DPS, dps ^ 1);   /* toggle dual-dptr switch */
+
+  tick (1);
+  return resGO;
+}
+
+/*
+ * 0xf0 1 24 MOVX @DPTR,A
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_uc390::instruction_f0/*inst_movx_Sdptr_a*/ (t_mem/*uchar*/ code)
+{
+  uchar pl, ph, px, dps;
+
+  dps = sfr->get (DPS);
+  if (dps & 0x01)
+    {
+      pl = DPL1;
+      ph = DPH1;
+      px = DPX1;
+    }
+  else
+    {
+      pl = DPL;
+      ph = DPH;
+      px = DPX;
+    }
+
+  if (sfr->get (ACON) & 0x02) /* AM1 set: 24-bit flat? */
+    write_mem (MEM_XRAM_ID,
+               sfr->read (px) * 256*256 + sfr->read (ph) * 256 + sfr->read (pl),
+               acc->read());
+  else
+    write_mem (MEM_XRAM_ID,
+               sfr->read (ph) * 256 + sfr->read (pl),
+               acc->read());
+
+  if (dps & 0x20)                      /* auto-switch dptr */
+    sfr->write (DPS, dps ^ 1);   /* toggle dual-dptr switch */
+
+  tick (1);
+  return resGO;
+}
+
+/*
+ * 0x[02468ace]1 2 24 AJMP addr
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_uc390::instruction_01/*inst_ajmp_addr*/ (t_mem/*uchar*/ code)
+{
+  uchar x, h, l;
+
+  if (sfr->get (ACON) & 0x02) /* AM1 set: 24-bit flat? */
+    {
+      x = (code >> 5) & 0x07;
+      h = fetch ();
+      l = fetch ();
+      PC = (PC & 0xf800) | (x * 256*256 + h * 256 + l);
+    }
+  else
+    {
+      h = (code >> 5) & 0x07;
+      l = fetch ();
+      PC = (PC & 0xf800) | (h * 256 + l);
+    }
+  tick (1);
+  return resGO;
+}
+
+/*
+ * 0x02 3 24 LJMP addr
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_uc390::instruction_02/*inst_ljmp*/ (t_mem/*uchar*/ code)
+{
+  uchar x, h, l;
+
+  if (sfr->get (ACON) & 0x02) /* AM1 set: 24-bit flat? */
+    {
+      //printf("LJMP in 24 bit mode! PC=%x\n", PC);
+      x = fetch ();
+      h = fetch ();
+      l = fetch ();
+      PC = x * 256*256 + h * 256 + l;
+    }
+  else
+    {
+      h = fetch ();
+      l = fetch ();
+      PC = h * 256 + l;
+    }
+  tick (1);
+  return resGO;
+}
+
+/*
+ * 0x[13579bdf]1 2 24 ACALL addr
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_uc390::instruction_11/*inst_acall_addr*/ (t_mem/*uchar*/ code)
+{
+  uchar x, h, l;
+
+  if (sfr->get (ACON) & 0x02) /* AM1 set: 24-bit flat? */
+    {
+      x = (code >> 5) & 0x07;
+      h = fetch ();
+      l = fetch ();
+
+      push_byte ( PC        & 0xff); /* push low byte  */
+      push_byte ((PC >>  8) & 0xff); /* push high byte */
+      push_byte ((PC >> 16) & 0xff); /* push x byte    */
+
+      PC = (PC & 0xf800) | (x * 256*256 + h * 256 + l);
+    }
+  else
+    {
+      /* stock mcs51 mode */
+      class cl_memory_cell *stck;
+      t_mem sp;
+
+      h = (code >> 5) & 0x07;
+      l = fetch();
+      sp = sfr->wadd (SP, 1);
+      stck = iram->get_cell (sp);
+      stck->write (PC & 0xff); // push low byte
+
+      sp = sfr->wadd (SP, 1);
+      stck = iram->get_cell (sp);
+      stck->write ((PC >> 8) & 0xff); // push high byte
+      PC = (PC & 0xf800) | (h*256 + l);
+    }
+  tick (1);
+  return resGO;
+}
+
+
+/*
+ * 0x12 3 24 LCALL
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_uc390::inst_lcall (t_mem/*uchar*/ code, uint addr, bool intr)
+{
+  uchar x = 0, h = 0, l = 0;
+
+  if (!intr)
+    { /* this is a normal lcall */
+     if (sfr->get (ACON) & 0x02) /* AM1 set: 24-bit flat? */
+        x = fetch ();
+      h = fetch ();
+      l = fetch ();
+    }
+    /* else, this is interrupt processing */
+
+  t_addr sp_before= sfr->get(SP);
+  push_byte ( PC       & 0xff); /* push low byte  */
+  push_byte ((PC >> 8) & 0xff); /* push high byte */
+
+  t_mem pushed= PC;
+  if (sfr->get (ACON) & 0x02) /* AM1 set: 24-bit flat? */
+    {
+      push_byte ((PC >> 16) & 0xff); /* push x byte */
+      if (addr)
+        PC = addr & 0xfffful; /* if interrupt: x-Byte is 0 */
+      else
+        PC = x * 256*256 + h * 256 + l;
+    }
+  else
+    {
+      class cl_stack_op *so;
+      if (addr)
+        {
+	  PC = addr;
+	  so= new cl_stack_intr(instPC, PC, pushed, sp_before, sfr->get(SP));
+	}
+      else
+        {
+	  PC = h * 256 + l;
+	  so= new cl_stack_call(instPC, PC, pushed, sp_before, sfr->get(SP));
+	}
+      so->init();
+      stack_write(so);
+    }
+  return resGO;
+}
+
+/*
+ * 0x22 1 24 RET
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_uc390::instruction_22/*inst_ret*/ (t_mem/*uchar*/ code)
+{
+  uchar x = 0, h, l;
+
+  t_addr sp_before= sfr->get(SP);
+  if (sfr->get (ACON) & 0x02) /* AM1 set: 24-bit flat? */
+    x = pop_byte ();
+  h = pop_byte ();
+  l = pop_byte ();
+
+  tick (1);
+
+  if (sfr->get (ACON) & 0x02) /* AM1 set: 24-bit flat? */
+    {
+      tick (1);
+      PC = x * 256*256 + h * 256 + l;
+    }
+  else
+    PC = h * 256 + l;
+
+  class cl_stack_op *so= new cl_stack_ret(instPC, PC, sp_before, sfr->get(SP));
+  so->init();
+  stack_read(so);
+  return resGO;
+}
+
+/*
+ * 0x32 1 24 RETI
+ *____________________________________________________________________________
+ *
+ */
+
+int
+cl_uc390::instruction_32/*inst_reti*/ (t_mem/*uchar*/ code)
+{
+  uchar x = 0, h, l;
+
+  t_addr sp_before= sfr->get(SP);
+  if (sfr->get (ACON) & 0x02) /* AM1 set: 24-bit flat? */
+    x = pop_byte ();
+  h = pop_byte ();
+  l = pop_byte ();
+  tick (1);
+
+  if (sfr->get (ACON) & 0x02) /* AM1 set: 24-bit flat? */
+    {
+      tick (1);
+      PC = x * 256*256 + h * 256 + l;
+    }
+  else
+    PC = h * 256 + l;
+
+  interrupt->was_reti = true;
+  class it_level *il = (class it_level *) (it_levels->top ());
+  if (il &&
+      il->level >= 0)
+    {
+      il = (class it_level *) (it_levels->pop ());
+      delete il;
+    }
+
+  class cl_stack_op *so=
+    new cl_stack_iret(instPC, PC, sp_before, sfr->get(SP));
+  so->init();
+  stack_read(so);
+  return resGO;
+}
+
+
+/*
+ * Disassembling an instruction
+ */
+
+struct dis_entry *
+cl_uc390::dis_tbl (void)
+{
+  if (sfr->get (ACON) & 0x02) /* AM1 set: 24-bit flat? */
+    return disass_390f;
+  else
+    return disass_51;
+    //t_uc51::dis_tbl ();
+
+}
+
+char *
+cl_uc390::disass (t_addr addr, const char *sep)
+{
+  char work[256], temp[200]/*, c[2]*/;
+  char *buf, *p, *b, *t, *org_b;
+  t_mem code;
+  uchar dps;
+
+  if (! (sfr->get (ACON) & 0x02)) /* AM1 set: 24-bit flat? */
+    return cl_51core::disass (addr, sep);
+  code = rom->get(addr);
+
+  p = work;
+  b = org_b = strdup(dis_tbl()[code].mnemonic);
+  while (*b)
+    {
+      if (*b == '%')
+        {
+          b++;
+          switch (*(b++))
+            {
+            case 'A': // absolute address
+              // stock:
+              // sprintf (temp, "%04lx",
+              //          (addr & 0xf800)|
+              //          (((code >> 5) & 0x07) * 256 +
+              //          rom->get (addr + 1)));
+
+              sprintf (temp, /*"%06lx"*/rom->addr_format,
+                       (addr & 0xf80000L) |
+                       (((code >> 5) & 0x07) * (256 * 256) +
+                       (rom->get (addr + 1) * 256) +
+                        rom->get (addr + 2)));
+              break;
+            case 'l': // long address
+              sprintf (temp, "%06lx",
+                       rom->get (addr + 1) * (256*256L) +
+                       rom->get (addr + 2) * 256 +
+                       rom->get (addr + 3));
+                       // rom->get (addr + 1) * 256 + rom->get (addr + 2));
+              break;
+            case 'a': // addr8 (direct address) at 2nd byte
+	      daddr_name(rom->get(addr+1), temp);
+              break;
+            case '8': // addr8 (direct address) at 3rd byte
+	      daddr_name(rom->get(addr+2), temp);
+              break;
+            case 'b': // bitaddr at 2nd byte
+	      {
+		t_addr ba = rom->get (addr+1);
+		/*if (get_name (ba, bit_tbl(), temp))
+		  break;
+		if (ba<128)
+		  addr_name((ba/8)+32,iram,temp);
+		else
+		  addr_name(ba&0xf8,sfr,temp);
+		strcat (temp, ".");
+		sprintf (c, "%1d", (int)(ba & 0x07));
+		strcat (temp, c);
+		break;*/
+		baddr_name(ba, temp);
+		break;
+	      }
+            case 'r': // rel8 address at 2nd byte
+              sprintf (temp, "%04x",
+                       /*t_addr*/int (addr + 2 + (signed char) (rom->get (addr + 1))));
+              break;
+            case 'R': // rel8 address at 3rd byte
+              sprintf (temp, "%04x",
+                       /*t_addr*/int (addr + 3 + (signed char) (rom->get (addr + 2))));
+              break;
+            case 'd': // data8 at 2nd byte
+              sprintf (temp, "%02x", (int)rom->get (addr + 1));
+              break;
+            case 'D': // data8 at 3rd byte
+              sprintf (temp, "%02x", (int)rom->get (addr + 2));
+              break;
+            case 'i': // inc/dec dptr
+              dps = sfr->get(DPS);
+              sprintf (temp, ((dps & 0x01) ? (dps & 0x80) : (dps & 0x40)) ? "DEC" : "INC");
+              break;
+            default:
+              strcpy (temp, "?");
+              break;
+            }
+          t = temp;
+          while (*t)
+            *p++ = *t++;
+        }
+      else
+        *p++ = *b++;
+    }
+  *p = '\0';
+
+  p = strchr (work, ' ');
+  if (!p)
+    {
+      buf = strdup (work);
+      return buf;
+    }
+  if (sep == NULL)
+    buf = (char *) malloc (6 + strlen (p) + 1);
+  else
+    buf = (char *) malloc ((p - work) + strlen (sep) + strlen (p) + 1);
+  for (p = work, b = buf; *p != ' '; p++, b++)
+    *b = *p;
+  p++;
+  *b = '\0';
+  if (sep == NULL)
+    while (strlen (buf) < 6)
+      strcat (buf, " ");
+  else
+    strcat (buf, sep);
+  strcat (buf, p);
+  free(org_b);
+  return buf;
+}
+
+void
+cl_uc390::print_regs (class cl_console_base *con)
+{
+  t_addr start;
+  t_mem data;
+  uchar dps;
+
+  if (! (sfr->get (ACON) & 0x02)) /* AM1 set: 24-bit flat? */
+    {
+      cl_51core::print_regs (con);
+      return;
+    }
+  start = sfr->get (PSW) & 0x18;
+  iram->dump (start, start + 7, 8, con/*->get_fout()*/);
+  con->dd_printf("     R0 R1 R2 R3 R4 R5 R6 R7\n");
+  data = iram->get (iram->get (start));
+  con->dd_printf ("@R0 %02x %c", data, isprint (data) ? data : '.');
+  con->dd_printf ("  ACC= 0x%02x %3d %c  B= 0x%02x",
+                  sfr->get (ACC), sfr->get (ACC),
+                  isprint (sfr->get (ACC)) ?
+                  (sfr->get (ACC)) : '.', sfr->get (B));
+  eram2xram ();
+  dps = sfr->get(DPS);
+  data = get_mem (MEM_XRAM_ID,
+                  sfr->get (DPX) * 256*256 + sfr->get (DPH) * 256 + sfr->get (DPL));
+  con->dd_printf ("  %cDPTR0= 0x%02x%02x%02x @DPTR0= 0x%02x %3d %c",
+                  dps & 0x01 ? ' ' : dps & 0x20 ? 't' : '*',
+                  sfr->get (DPX), sfr->get (DPH), sfr->get (DPL),
+                  data, data, isprint (data) ? data : '.');
+  data = get_mem (MEM_XRAM_ID,
+                  sfr->get (DPX1) * 256*256 + sfr->get (DPH1) * 256 + sfr->get (DPL1));
+  con->dd_printf ("  %cDPTR1= 0x%02x%02x%02x @DPTR1= 0x%02x %3d %c\n",
+                  dps & 0x01 ? dps & 0x20 ? 't' : '*' : ' ',
+                  sfr->get (DPX1), sfr->get (DPH1), sfr->get (DPL1),
+                  data, data, isprint (data) ? data : '.');
+  data = iram->get (iram->get (start + 1));
+  con->dd_printf ("@R1 %02x %c", data, isprint (data) ? data : '.');
+  con->dd_printf ("  AP= 0x%02x", sfr->get (AP));
+  data= sfr->get (PSW);
+  con->dd_printf ("  PSW= 0x%02x CY=%c AC=%c OV=%c P=%c    ",
+                  data,
+                  (data & bmCY) ? '1' : '0', (data & bmAC) ? '1' : '0',
+                  (data & bmOV) ? '1' : '0', (data & bmP ) ? '1' : '0');
+  /* show stack pointer */
+  if (sfr->get (ACON) & 0x04)
+    {
+      /* SA: 10 bit stack */
+      start = (sfr->get (R51_ESP) & 3) * 256 + sfr->get (SP);
+      con->dd_printf ("SP10 ", start);
+      ixram->dump (start, start - 7, 8, con/*->get_fout()*/);
+    }
+  else
+    {
+      start = sfr->get (SP);
+      con->dd_printf ("SP ", start);
+      iram->dump (start, start - 7, 8, con/*->get_fout()*/);
+    }
+
+  print_disass (PC, con);
+}
+
+/* End of s51.src/uc390.cc */
diff --git a/sim/ucsim/s51.src/uc390cl.h b/sim/ucsim/s51.src/uc390cl.h
new file mode 100644
index 0000000..4d79514
--- /dev/null
+++ b/sim/ucsim/s51.src/uc390cl.h
@@ -0,0 +1,96 @@
+/*
+ * Simulator of microcontrollers (uc390cl.h)
+ *
+ * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
+ *
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ * uc390cl.h - implemented by Karl Bongers, karl@turbobit.com
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#ifndef UC390CL_HEADER
+#define UC390CL_HEADER
+
+#include "ddconfig.h"
+
+#include "uc52cl.h"
+
+class cl_uc390: public cl_uc52
+{
+public:
+  // memories and cells for faster access
+  class cl_address_space *ixram;
+  class cl_memory_chip *ixram_chip;
+  
+  cl_uc390(struct cpu_entry *Itype, class cl_sim *asim);
+  virtual void mk_hw_elements (void);
+  virtual void make_memories(void);
+  virtual void make_address_spaces();
+  virtual void make_chips(void);
+  virtual void decode_rom(void);
+  virtual void decode_xram(void);
+  virtual void decode_dptr(void);
+  
+  virtual void clear_sfr (void);
+
+  // making objects
+  //virtual t_addr get_mem_size (enum mem_class type);
+
+  // manipulating memories
+  virtual t_mem read_mem (char *id/*enum mem_class type*/, t_addr addr);
+  virtual t_mem get_mem (char *id/*enum mem_class type*/, t_addr addr);
+  virtual void  write_mem (char *id/*enum mem_class type*/, t_addr addr, t_mem val);
+  virtual void  set_mem (char *id/*enum mem_class type*/, t_addr addr, t_mem val);
+
+  /* mods for dual-dptr */
+  virtual int instruction_a3/*inst_inc_dptr*/(t_mem/*uchar*/ code);		// a3
+  virtual int instruction_73/*inst_jmp_Sa_dptr*/(t_mem/*uchar*/ code);		// 73
+  virtual int instruction_90/*inst_mov_dptr_Sdata*/(t_mem/*uchar*/ code);	// 90
+  virtual int instruction_93/*inst_movc_a_Sa_dptr*/(t_mem/*uchar*/ code);	// 93
+  virtual int instruction_e0/*inst_movx_a_Sdptr*/(t_mem/*uchar*/ code);		// e0
+  virtual int instruction_f0/*inst_movx_Sdptr_a*/(t_mem/*uchar*/ code);		// f0
+
+  /* mods for flat24 */
+  virtual int instruction_01/*inst_ajmp_addr*/(t_mem/*uchar*/ code);		// [02468abce]1
+  virtual int instruction_02/*inst_ljmp*/(t_mem/*uchar*/ code);			// 02
+  virtual int instruction_11/*inst_acall_addr*/(t_mem/*uchar*/ code);		// [13579bdf]1
+  virtual int inst_lcall(t_mem/*uchar*/ code, uint addr, bool intr);		// 12
+  virtual int instruction_22/*inst_ret*/(t_mem/*uchar*/ code);			// 22
+  virtual int instruction_32/*inst_reti*/(t_mem/*uchar*/ code);
+
+  /* mods for 10 bit stack */
+  virtual int instruction_c0/*inst_push*/ (t_mem/*uchar*/ code);		// c0
+  virtual int instruction_d0/*inst_pop*/ (t_mem/*uchar*/ code);			// d0
+
+  /* mods for disassembly of flat24 */
+  virtual struct dis_entry *dis_tbl(void);
+  virtual char * disass(t_addr addr, const char *sep);
+  virtual void   print_regs(class cl_console_base *con);
+
+protected:
+  //int flat24_flag; /* true if processor == ds390f */
+  virtual void push_byte (t_mem uc);
+  virtual t_mem pop_byte (void);
+};
+
+/* End of s51.src/uc390cl.h */
+
+#endif
diff --git a/sim/ucsim/s51.src/uc390hw.cc b/sim/ucsim/s51.src/uc390hw.cc
new file mode 100644
index 0000000..72a449b
--- /dev/null
+++ b/sim/ucsim/s51.src/uc390hw.cc
@@ -0,0 +1,268 @@
+/*
+ * Simulator of microcontrollers (serial.cc)
+ *
+ * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
+ *
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#include "ddconfig.h"
+
+#include <stdio.h>
+#include <stdlib.h>
+
+// local
+#include "uc390hwcl.h"
+#include "regs51.h"
+#include "uc51cl.h"
+
+
+cl_uc390_hw::cl_uc390_hw (class cl_uc *auc):
+  cl_hw (auc, HW_CPU/*DUMMY*/, 0, "ds390hw")
+{
+  uc390 = (class cl_uc390 *) uc;
+}
+
+int
+cl_uc390_hw::init(void)
+{
+  cl_hw::init();
+  sfr = uc->address_space(MEM_SFR_ID);
+  if (sfr)
+    {
+      cell_dps= register_cell (sfr, DPS  );
+      cell_p4cnt= register_cell (sfr, P4CNT);
+      cell_exif= register_cell (sfr, EXIF );
+      cell_acon= register_cell (sfr, ACON );
+      cell_p5cnt= register_cell (sfr, P5CNT);
+      cell_c0c= register_cell (sfr, C0C  );
+      cell_pmr= register_cell (sfr, PMR  );
+      cell_mcon= register_cell (sfr, MCON  );
+      cell_ta= register_cell (sfr, TA   );
+      cell_cor= register_cell (sfr, COR  );
+      cell_mcnt0= register_cell (sfr, MCNT0);
+      cell_mcnt1= register_cell (sfr, MCNT1);
+      cell_ma= register_cell (sfr, MA   );
+      cell_mb= register_cell (sfr, MB   );
+      cell_mc= register_cell (sfr, MC   );
+      cell_wdcon= register_cell (sfr, WDCON);
+      cell_c1c= register_cell (sfr, C1C  );
+    }
+  return 0;
+}
+
+t_mem
+cl_uc390_hw::read (class cl_memory_cell *cell)
+{
+  if (cell == cell_exif)
+    {
+      if (ctm_ticks &&
+          uc390->ticks->ticks >= ctm_ticks + 65535)
+	{
+	  ctm_ticks = 0;
+	  cell->set (cell->get() | 0x08); /* set CKRDY */
+	}
+    }
+  return cell->get();
+}
+
+void
+cl_uc390_hw::write (class cl_memory_cell *cell, t_mem *val)
+{
+  if (cell == cell_dps)
+    *val = (*val & 0xe5) | 0x04;
+  else if (cell == cell_exif)
+    {
+      /* Bit 0 (BGS) is TA-protected */
+      if (timed_access_state != 2 ||
+          timed_access_ticks + 2*12 < uc390->ticks->ticks) // fixme: 3 cycles
+	*val = (*val & ~0x01) | (cell_exif->get() & 0x01);
+
+      /* CKRDY and RGMD are read-only */
+      *val = (*val & 0x0c) | (*val & ~0x0c);
+    }
+  else if (cell == cell_p4cnt)
+    {
+      /* P4CNT is TA-protected */
+      if (timed_access_state != 2 ||
+          timed_access_ticks + 2*12 < uc390->ticks->ticks) // fixme: 3 cycles
+        *val = cell_p4cnt->get();
+      *val |= 0x80; /* always 1 */
+    }
+  else if (cell == cell_acon)
+    {
+      /* ACON is TA-protected */
+      if (timed_access_state != 2 ||
+          timed_access_ticks + 2*12 < uc390->ticks->ticks) // fixme: 3 cycles
+        *val = cell_acon->get();
+      else
+        {
+          /* lockout: IDM1:IDM0 and SA can't be set at the same time */
+          if ((cell_mcon->get() & 0xc0) == 0xc0) /* IDM1 and IDM0 set? */
+            *val &= ~0x04; /* lockout SA */
+        }
+      *val |= 0xf8; /* always 1 */
+    }
+  else if (cell == cell_p5cnt)
+    {
+      /* Bits 0...2 are TA-protected */
+      if (timed_access_state != 2 ||
+          timed_access_ticks + 2*12 < uc390->ticks->ticks) // fixme: 3 cycles
+	*val = (*val & ~0x07) | (cell_p5cnt->get() & 0x07);
+    }
+  else if (cell == cell_c0c)
+    {
+      /* Bit 3 (CRST) is TA-protected */
+      if (timed_access_state != 2 ||
+          timed_access_ticks + 2*12 < uc390->ticks->ticks) // fixme: 3 cycles
+	*val = (*val & ~0x08) | (cell_c0c->get() & 0x08);
+    }
+  else if (cell == cell_pmr)
+    {
+      /* fixme: check previous state */
+      if ((*val & 0xd0) == 0x90) /* CD1:CD0 set to 10, CTM set */
+        {
+	  ctm_ticks = uc390->ticks->ticks;
+	  cell_exif->set (cell_exif->get() & ~0x08); /* clear CKRDY */
+        }
+      else
+        ctm_ticks = 0;
+      *val |= 0x03; /* always 1 */
+    }
+  else if (cell == cell_mcon)
+    {
+      /* MCON is TA-protected */
+      if (timed_access_state != 2 ||
+          timed_access_ticks + 2*12 < uc390->ticks->ticks) // fixme: 3 cycles
+        *val = cell_mcon->get();
+      else
+        /* lockout: IDM1:IDM0 and SA can't be set at the same time */
+        if (((*val & 0xc0) == 0xc0) &&
+            ((cell_acon->get() & 0x04) == 0x04)) /* SA set? */
+          *val &= ~0xc0; /* lockout IDM1:IDM0 */
+      *val |= 0x10; /* always 1 */
+    }
+  else if (cell == cell_ta)
+    {
+      if (*val == 0xAA)
+        {
+          timed_access_state = 1;
+          timed_access_ticks = uc390->ticks->ticks;
+        }
+      else if (*val == 0x55 &&
+               timed_access_state == 1 &&
+               timed_access_ticks + 2*12 >= uc390->ticks->ticks) // fixme: 3 cycles
+        {
+          timed_access_state = 2;
+          timed_access_ticks = uc390->ticks->ticks;
+        }
+      else
+        timed_access_state = 0;
+    }
+  else if (cell == cell_cor)
+    {
+      /* COR is TA-protected */
+      if (timed_access_state != 2 ||
+          timed_access_ticks + 2*12 < uc390->ticks->ticks) // fixme: 3 cycles
+	*val = cell_cor->get();
+    }
+  else if (cell == cell_mcnt0)
+    {
+      ;
+    }
+  else if (cell == cell_mcnt1)
+    {
+      *val |= 0x0f; /* always 1 */
+    }
+  else if (cell == cell_ma)
+    {
+      ;
+    }
+  else if (cell == cell_mb)
+    {
+      ;
+    }
+  else if (cell == cell_mc)
+    {
+      ;
+    }
+  else if (cell == cell_wdcon)
+    {
+      /* Bits 0, 1, 3 and 6 are TA-protected */
+      if (timed_access_state != 2 ||
+          timed_access_ticks + 2*12 < uc390->ticks->ticks) // fixme: 3 cycles
+	*val = (*val & ~0x4b) | (cell_wdcon->get() & 0x4b);
+    }
+  else if (cell == cell_c1c)
+    {
+      /* Bit 3 (CRST) is TA-protected */
+      if (timed_access_state != 2 ||
+          timed_access_ticks + 2*12 < uc390->ticks->ticks) // fixme: 3 cycles
+	*val = (*val & ~0x08) | (cell_c1c->get() & 0x08);
+    }
+}
+
+void
+cl_uc390_hw::reset(void)
+{
+  ctm_ticks = 0;
+  timed_access_state = 0;
+}
+
+void
+cl_uc390_hw::print_info(class cl_console_base *con)
+{
+  int i;
+  long l;
+
+  i = sfr->get (EXIF);
+  con->dd_printf ("%s"
+                  " EXIF 0x%02x: IE5 %c IE4 %c IE3 %c IE2 %c CKRDY %c RGMD %c RGSL %c BGS %c\n",
+                  id_string,
+		  i,
+                  (i & 0x80) ? '1' : '0',
+                  (i & 0x40) ? '1' : '0',
+                  (i & 0x20) ? '1' : '0',
+                  (i & 0x10) ? '1' : '0',
+                  (i & 0x08) ? '1' : '0',
+                  (i & 0x04) ? '1' : '0',
+                  (i & 0x02) ? '1' : '0',
+                  (i & 0x01) ? '1' : '0');
+  i = sfr->get (DPS);
+  con->dd_printf ("\tDPS  0x%02x: ID1 %c ID0 %c TSL %c SEL %c\n",
+		  i,
+                  (i & 0x80) ? '1' : '0',
+                  (i & 0x40) ? '1' : '0',
+                  (i & 0x20) ? '1' : '0',
+                  (i & 0x01) ? '1' : '0');
+  l = sfr->get (DPX) * 256*256 +
+      sfr->get (DPH) * 256 +
+      sfr->get (DPL);
+  con->dd_printf ("\tDPTR  0x%06lx\n", l);
+  l = sfr->get (DPX1) * 256*256 +
+      sfr->get (DPH1) * 256 +
+      sfr->get (DPL1);
+  con->dd_printf ("\tDPTR1 0x%06lx\n", l);
+  print_cfg_info(con);
+}
+
+/* End of s51.src/uc390hw.cc */
diff --git a/sim/ucsim/s51.src/uc390hwcl.h b/sim/ucsim/s51.src/uc390hwcl.h
new file mode 100644
index 0000000..ed15b5e
--- /dev/null
+++ b/sim/ucsim/s51.src/uc390hwcl.h
@@ -0,0 +1,65 @@
+/*
+ * Simulator of microcontrollers (serialcl.h)
+ *
+ * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#ifndef UC390HWCL_HEADER
+#define UC390HWCL_HEADER
+
+#include "uccl.h"
+
+#include "uc390cl.h"
+
+
+class cl_uc390_hw: public cl_hw
+{
+protected:
+  class cl_address_space *sfr;
+  class cl_memory_cell *cell_dps, *cell_exif, *cell_p4cnt, *cell_acon,
+    *cell_p5cnt, *cell_c0c, *cell_pmr, *cell_mcon,
+    *cell_ta, *cell_cor, *cell_mcnt0, *cell_mcnt1,
+    *cell_ma, *cell_mb, *cell_mc, *cell_wdcon, *cell_c1c;
+  class cl_uc390 *uc390;
+  unsigned long ctm_ticks; /* mini-state-machine for "crystal multiplier" */
+  unsigned long timed_access_ticks;
+  int timed_access_state; /* 0: idle; 1: $aa written; 2: $55 written */
+public:
+  cl_uc390_hw (class cl_uc *auc);
+  virtual int init (void);
+  //virtual char *cfg_help(t_addr addr);
+
+  virtual t_mem read (class cl_memory_cell *cell);
+  virtual void write (class cl_memory_cell *cell, t_mem *val);
+
+  //virtual void mem_cell_changed (class cl_mem *mem, t_addr addr);
+
+  virtual void reset (void);
+  virtual void print_info (class cl_console_base *con);
+};
+
+
+#endif
+
+/* End of s51.src/serialcl.h */
diff --git a/sim/ucsim/s51.src/uc51.cc b/sim/ucsim/s51.src/uc51.cc
new file mode 100644
index 0000000..d1faf56
--- /dev/null
+++ b/sim/ucsim/s51.src/uc51.cc
@@ -0,0 +1,2072 @@
+/*
+ * Simulator of microcontrollers (uc51.cc)
+ *
+ * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
+ *
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#include "ddconfig.h"
+
+#include <stdio.h>
+#include <stdarg.h>
+#include <stdlib.h>
+#include <ctype.h>
+#include <fcntl.h>
+#include <errno.h>
+#include <sys/types.h>
+#include <sys/time.h>
+//#if FD_HEADER_OK
+//# include HEADER_FD
+//#endif
+#include "i_string.h"
+
+// prj
+#include "utils.h"
+#include "globals.h"
+
+// sim
+#include "optioncl.h"
+#include "iwrap.h"
+
+//cmd.src
+#include "cmd_uccl.h"
+
+// local
+#include "uc51cl.h"
+#include "glob.h"
+#include "regs51.h"
+#include "timer0cl.h"
+#include "timer1cl.h"
+#include "serialcl.h"
+#include "portcl.h"
+#include "interruptcl.h"
+#include "types51.h"
+
+
+
+/*
+ * Names of SFR cells
+ */
+
+static struct name_entry sfr_tab51[]=
+{
+  {CPU_F380,			  0xc7, "P4"},
+  
+  {CPU_251,                       0x84, "DPXL"},
+  {CPU_251|CPU_DS390|CPU_DS390F,  0x93, "DPX"},
+  {CPU_251,                       0xa8, "IE0"},
+  {CPU_251,                       0xb7, "IPH0"},
+  {CPU_251,                       0xb8, "IPL0"},
+  {CPU_251,                       0xbd, "SPH"},
+  {CPU_251,                       0xd1, "PSW1"},
+
+  {CPU_DS390|CPU_DS390F,          0x80, "P4"},
+  {CPU_ALL_DS3X0,                 0x84, "DPL1"},
+  {CPU_ALL_DS3X0,                 0x85, "DPH1"},
+  {CPU_ALL_DS3X0,                 0x86, "DPS"},
+  {CPU_ALL_DS3X0,                 0x8e, "CKCON"},
+  {CPU_DS390|CPU_DS390F,          0x91, "EXIF"},
+  {CPU_DS390|CPU_DS390F,          0x92, "P4CNT"},
+  {CPU_DS390|CPU_DS390F,          0x95, "DPX1"},
+  {CPU_DS390|CPU_DS390F,          0x96, "C0RMS0"},
+  {CPU_DS390|CPU_DS390F,          0x97, "C0RMS1"},
+  {CPU_DS390|CPU_DS390F,          0x98, "SCON0"},
+  {CPU_DS390|CPU_DS390F,          0x99, "SBUF0"},
+  {CPU_DS390|CPU_DS390F,          0x9b, "ESP"},
+  {CPU_DS390|CPU_DS390F,          0x9c, "AP"},
+  {CPU_DS390|CPU_DS390F,          0x9d, "ACON"},
+  {CPU_DS390|CPU_DS390F,          0x9e, "C0TMA0"},
+  {CPU_DS390|CPU_DS390F,          0x9f, "C0TMA1"},
+  {CPU_DS390|CPU_DS390F,          0xa1, "P5"},
+  {CPU_DS390|CPU_DS390F,          0xa2, "P5CNT"},
+  {CPU_DS390|CPU_DS390F,          0xa3, "C0C"},
+  {CPU_DS390|CPU_DS390F,          0xa4, "C0S"},
+  {CPU_DS390|CPU_DS390F,          0xa5, "C0IR"},
+  {CPU_DS390|CPU_DS390F,          0xa6, "C0TE"},
+  {CPU_DS390|CPU_DS390F,          0xa7, "C0RE"},
+  {CPU_DS390|CPU_DS390F,          0xa9, "SADDR0"},
+  {CPU_DS390|CPU_DS390F,          0xaa, "SADDR1"},
+  {CPU_DS390|CPU_DS390F,          0xab, "C0M1C"},
+  {CPU_DS390|CPU_DS390F,          0xac, "C0M2C"},
+  {CPU_DS390|CPU_DS390F,          0xad, "C0M3C"},
+  {CPU_DS390|CPU_DS390F,          0xae, "C0M4C"},
+  {CPU_DS390|CPU_DS390F,          0xaf, "C0M5C"},
+  {CPU_DS390|CPU_DS390F,          0xb3, "C0M6C"},
+  {CPU_DS390|CPU_DS390F,          0xb4, "C0M7C"},
+  {CPU_DS390|CPU_DS390F,          0xb5, "C0M8C"},
+  {CPU_DS390|CPU_DS390F,          0xb6, "C0M9C"},
+  {CPU_DS390|CPU_DS390F,          0xb7, "C0M10C"},
+  {CPU_DS390|CPU_DS390F,          0xb9, "SADEN0"},
+  {CPU_DS390|CPU_DS390F,          0xba, "SADEN1"},
+  {CPU_DS390|CPU_DS390F,          0xbb, "C0M11C"},
+  {CPU_DS390|CPU_DS390F,          0xbc, "C0M12C"},
+  {CPU_DS390|CPU_DS390F,          0xbd, "C0M13C"},
+  {CPU_DS390|CPU_DS390F,          0xbe, "C0M14C"},
+  {CPU_DS390|CPU_DS390F,          0xbf, "C0M15C"},
+  {CPU_DS390|CPU_DS390F,          0xc0, "SCON1"},
+  {CPU_DS390|CPU_DS390F,          0xc1, "SBUF1"},
+  {CPU_DS390|CPU_DS390F,          0xc4, "PMR"},
+  {CPU_DS390|CPU_DS390F,          0xc5, "STATUS"},
+  {CPU_DS390|CPU_DS390F,          0xc6, "MCON"},
+  {CPU_DS390|CPU_DS390F,          0xc7, "TA"},
+  {CPU_DS390|CPU_DS390F,          0xce, "COR"},
+  {CPU_DS390|CPU_DS390F,          0xd1, "MCNT0"},
+  {CPU_DS390|CPU_DS390F,          0xd2, "MCNT1"},
+  {CPU_DS390|CPU_DS390F,          0xd3, "MA"},
+  {CPU_DS390|CPU_DS390F,          0xd4, "MB"},
+  {CPU_DS390|CPU_DS390F,          0xd5, "MC"},
+  {CPU_DS390|CPU_DS390F,          0xd6, "C1RMS0"},
+  {CPU_DS390|CPU_DS390F,          0xd7, "C1RMS1"},
+  {CPU_DS390|CPU_DS390F,          0xd8, "WDCON"},
+  {CPU_DS390|CPU_DS390F,          0xde, "C1TMA0"},
+  {CPU_DS390|CPU_DS390F,          0xdf, "C1TMA1"},
+  {CPU_DS390|CPU_DS390F,          0xe3, "C1C"},
+  {CPU_DS390|CPU_DS390F,          0xe4, "C1S"},
+  {CPU_DS390|CPU_DS390F,          0xe5, "C11R"},
+  {CPU_DS390|CPU_DS390F,          0xe6, "C1TE"},
+  {CPU_DS390|CPU_DS390F,          0xe7, "C1RE"},
+  {CPU_DS390|CPU_DS390F,          0xe8, "EIE"},
+  {CPU_DS390|CPU_DS390F,          0xea, "MXAX"},
+  {CPU_DS390|CPU_DS390F,          0xeb, "C1M1C"},
+  {CPU_DS390|CPU_DS390F,          0xec, "C1M2C"},
+  {CPU_DS390|CPU_DS390F,          0xed, "C1M3C"},
+  {CPU_DS390|CPU_DS390F,          0xee, "C1M4C"},
+  {CPU_DS390|CPU_DS390F,          0xef, "C1M5C"},
+  {CPU_DS390|CPU_DS390F,          0xf3, "C1M6C"},
+  {CPU_DS390|CPU_DS390F,          0xf4, "C1M7C"},
+  {CPU_DS390|CPU_DS390F,          0xf5, "C1M8C"},
+  {CPU_DS390|CPU_DS390F,          0xf6, "C1M9C"},
+  {CPU_DS390|CPU_DS390F,          0xf7, "C1M10C"},
+  {CPU_DS390|CPU_DS390F,          0xfb, "C1M11C"},
+  {CPU_DS390|CPU_DS390F,          0xfc, "C1M12C"},
+  {CPU_DS390|CPU_DS390F,          0xfd, "C1M13C"},
+  {CPU_DS390|CPU_DS390F,          0xfe, "C1M14C"},
+  {CPU_DS390|CPU_DS390F,          0xff, "C1M15C"},
+
+  {CPU_ALL_51|CPU_ALL_52|CPU_251, 0x80, "P0"},
+  {CPU_ALL_51|CPU_ALL_52|CPU_251, 0x81, "SP"},
+  //{CPU_ALL_51|CPU_ALL_52|CPU_251, 0x82, "DPL"},
+  //{CPU_ALL_51|CPU_ALL_52|CPU_251, 0x83, "DPH"},
+  {CPU_ALL_51|CPU_ALL_52|CPU_251, 0x87, "PCON"},
+  {CPU_ALL_51|CPU_ALL_52|CPU_251, 0x88, "TCON"},
+  {CPU_ALL_51|CPU_ALL_52|CPU_251, 0x89, "TMOD"},
+  {CPU_ALL_51|CPU_ALL_52|CPU_251, 0x8a, "TL0"},
+  {CPU_ALL_51|CPU_ALL_52|CPU_251, 0x8b, "TL1"},
+  {CPU_ALL_51|CPU_ALL_52|CPU_251, 0x8c, "TH0"},
+  {CPU_ALL_51|CPU_ALL_52|CPU_251, 0x8d, "TH1"},
+  {CPU_ALL_51|CPU_ALL_52|CPU_251, 0x90, "P1"},
+  {CPU_ALL_51|CPU_ALL_52|CPU_251, 0x98, "SCON"},
+  {CPU_ALL_51|CPU_ALL_52|CPU_251, 0x99, "SBUF"},
+  {CPU_ALL_51|CPU_ALL_52|CPU_251, 0xa0, "P2"},
+  {CPU_ALL_51|CPU_ALL_52,         0xa8, "IE"},
+  {CPU_ALL_51|CPU_ALL_52|CPU_251, 0xb0, "P3"},
+  {CPU_ALL_51|CPU_ALL_52,         0xb8, "IP"},
+  {CPU_ALL_51|CPU_ALL_52|CPU_251, 0xd0, "PSW"},
+  {CPU_ALL_51|CPU_ALL_52|CPU_251, 0xe0, "ACC"},
+  {CPU_ALL_51|CPU_ALL_52|CPU_251, 0xf0, "B"},
+
+  {CPU_ALL_52|CPU_251,            0xc8, "T2CON"},
+  {CPU_ALL_52|CPU_251,            0xca, "RCAP2L"},
+  {CPU_ALL_52|CPU_251,            0xcb, "RCAP2H"},
+  {CPU_ALL_52|CPU_251,            0xcc, "TL2"},
+  {CPU_ALL_52|CPU_251,            0xcd, "TH2"},
+
+  {CPU_51R|CPU_89C51R,            0x8e, "AUXR"},
+  {CPU_51R|CPU_89C51R|CPU_251,    0xa6, "WDTRST"},
+  {CPU_51R|CPU_89C51R|CPU_251,    0xa9, "SADDR"},
+  {CPU_51R|CPU_89C51R,            0xb7, "IPH"},
+  {CPU_51R|CPU_89C51R|CPU_251,    0xb9, "SADEN"},
+  {CPU_51R|CPU_89C51R|CPU_251|\
+            CPU_DS390|CPU_DS390F, 0xc9, "T2MOD"}, /* fixme: isn't that CPU_ALL_52? */
+
+  {CPU_89C51R,                    0xa2, "AUXR1"},
+  {CPU_89C51R|CPU_251,            0xd8, "CCON"},
+  {CPU_89C51R|CPU_251,            0xd9, "CMOD"},
+  {CPU_89C51R|CPU_251,            0xda, "CCAPM0"},
+  {CPU_89C51R|CPU_251,            0xdb, "CCAPM1"},
+  {CPU_89C51R|CPU_251,            0xdc, "CCAPM2"},
+  {CPU_89C51R|CPU_251,            0xdd, "CCAPM3"},
+  {CPU_89C51R|CPU_251,            0xde, "CCAPM4"},
+  {CPU_89C51R|CPU_251,            0xe9, "CL"},
+  {CPU_89C51R|CPU_251,            0xea, "CCAP0L"},
+  {CPU_89C51R|CPU_251,            0xeb, "CCAP1L"},
+  {CPU_89C51R|CPU_251,            0xec, "CCAP2L"},
+  {CPU_89C51R|CPU_251,            0xed, "CCAP3L"},
+  {CPU_89C51R|CPU_251,            0xee, "CCAP4L"},
+  {CPU_89C51R|CPU_251,            0xf9, "CH"},
+  {CPU_89C51R|CPU_251,            0xfa, "CCAP0H"},
+  {CPU_89C51R|CPU_251,            0xfb, "CCAP1H"},
+  {CPU_89C51R|CPU_251,            0xfc, "CCAP2H"},
+  {CPU_89C51R|CPU_251,            0xfd, "CCAP3H"},
+  {CPU_89C51R|CPU_251,            0xfe, "CCAP4H"},
+
+  {CPU_F380, 0x8e, "CKCON"},
+  {CPU_F380, 0x8f, "PSCTL"},
+  {CPU_F380, 0x91, "TMR3CN"},
+  {CPU_F380, 0x91, "TMR4CN"},
+  {CPU_F380, 0x92, "TMR3RLL"},
+  {CPU_F380, 0x92, "TMR4RLL"},
+  {CPU_F380, 0x93, "TMR3RLH"},
+  {CPU_F380, 0x93, "TMR4RLH"},
+  {CPU_F380, 0x94, "TMR3L"},
+  {CPU_F380, 0x94, "TMR4L"},
+  {CPU_F380, 0x95, "TMR3H"},
+  {CPU_F380, 0x95, "TMR4H"},
+  {CPU_F380, 0x96, "USB0ADR"},
+  {CPU_F380, 0x97, "USB0DAT"},
+  {CPU_F380, 0x9a, "CPT1CN"},
+  {CPU_F380, 0x9b, "CPT0CN"},
+  {CPU_F380, 0x9c, "CPT1MD"},
+  {CPU_F380, 0x9d, "CPT0MD"},
+  {CPU_F380, 0x9e, "CPT1MX"},
+  {CPU_F380, 0x9f, "CPT0MX"},
+  {CPU_F380, 0xa1, "SPI0CFG"},
+  {CPU_F380, 0xa2, "SPI0CKR"},
+  {CPU_F380, 0xa3, "SPI0DAT"},
+  {CPU_F380, 0xa4, "P0MDOUT"},
+  {CPU_F380, 0xa5, "P1MDOUT"},
+  {CPU_F380, 0xa6, "P2MDOUT"},
+  {CPU_F380, 0xa7, "P3MDOUT"},
+  {CPU_F380, 0xa9, "CLKSEL"},
+  {CPU_F380, 0xaa, "EMI0CN"},
+  {CPU_F380, 0xac, "SBCON1"},
+  {CPU_F380, 0xae, "P4MDOUT"},
+  {CPU_F380, 0xaf, "PFE0CN"},
+  {CPU_F380, 0xb1, "OSCXCN"},
+  {CPU_F380, 0xb2, "OSCICN"},
+  {CPU_F380, 0xb3, "OSCICL"},
+  {CPU_F380, 0xb4, "SBRLL1"},
+  {CPU_F380, 0xb5, "SBRLH1"},
+  {CPU_F380, 0xb6, "FLSCL"},
+  {CPU_F380, 0xb7, "FLKEY"},
+  {CPU_F380, 0xb9, "CLKMUL"},
+  {CPU_F380, 0xb9, "SMBTC"},
+  {CPU_F380, 0xba, "AMX0N"},
+  {CPU_F380, 0xbb, "AMX0P"},
+  {CPU_F380, 0xbc, "ADC0CF"},
+  {CPU_F380, 0xbd, "ADC0L"},
+  {CPU_F380, 0xbe, "ADC0H"},
+  {CPU_F380, 0xbf, "SFRPAGE"},
+  {CPU_F380, 0xc0, "SMB0CN"},
+  {CPU_F380, 0xc0, "SMB1CN"},
+  {CPU_F380, 0xc1, "SMB0CF"},
+  {CPU_F380, 0xc1, "SMB1CF"},
+  {CPU_F380, 0xc2, "SMB0DAT"},
+  {CPU_F380, 0xc2, "SMB1DAT"},
+  {CPU_F380, 0xc3, "ADC0GTL"},
+  {CPU_F380, 0xc4, "ADC0GTH"},
+  {CPU_F380, 0xc5, "ADC0LTL"},
+  {CPU_F380, 0xc6, "ADC0LTH"},
+  {CPU_F380, 0xc7, "P4"},
+  {CPU_F380, 0xd1, "REF0CN"},
+  {CPU_F380, 0xd2, "SCON1"},
+  {CPU_F380, 0xd3, "SBUF1"},
+  {CPU_F380, 0xd4, "P0SKIP"},
+  {CPU_F380, 0xd5, "P1SKIP"},
+  {CPU_F380, 0xd6, "P2SKIP"},
+  {CPU_F380, 0xd7, "USB0XCN"},
+  {CPU_F380, 0xd8, "PCA0CN"},
+  {CPU_F380, 0xd9, "PCA0MD"},
+  {CPU_F380, 0xda, "PCA0CPM0"},
+  {CPU_F380, 0xdb, "PCA0CPM1"},
+  {CPU_F380, 0xdc, "PCA0CPM2"},
+  {CPU_F380, 0xdd, "PCA0CPM3"},
+  {CPU_F380, 0xde, "PCA0CPM4"},
+  {CPU_F380, 0xdf, "P3SKIP"},
+  {CPU_F380, 0xe1, "XBR0"},
+  {CPU_F380, 0xe2, "XBR1"},
+  {CPU_F380, 0xe3, "XBR2"},
+  {CPU_F380, 0xe4, "IT01CF"},
+  {CPU_F380, 0xe4, "CKCON1"},
+  {CPU_F380, 0xe5, "SMOD1"},
+  {CPU_F380, 0xe6, "EIE1"},
+  {CPU_F380, 0xe7, "EIE2"},
+  {CPU_F380, 0xe8, "ADC0CN"},
+  {CPU_F380, 0xe9, "PCA0CPL1"},
+  {CPU_F380, 0xea, "PCA0CPH1"},
+  {CPU_F380, 0xeb, "PCA0CPL2"},
+  {CPU_F380, 0xec, "PCA0CPH2"},
+  {CPU_F380, 0xed, "PCA0CPL3"},
+  {CPU_F380, 0xee, "PCA0CPH3"},
+  {CPU_F380, 0xef, "RSTSRC"},
+  {CPU_F380, 0xf1, "P0MDIN"},
+  {CPU_F380, 0xf2, "P1MDIN"},
+  {CPU_F380, 0xf3, "P2MDIN"},
+  {CPU_F380, 0xf4, "P3MDIN"},
+  {CPU_F380, 0xf5, "P4MDIN"},
+  {CPU_F380, 0xf6, "EIP1"},
+  {CPU_F380, 0xf7, "EIP2"},
+  {CPU_F380, 0xf8, "SPI0CN"},
+  {CPU_F380, 0xf9, "PCA0L"},
+  {CPU_F380, 0xfa, "PCA0H"},
+  {CPU_F380, 0xfb, "PCA0CPL0"},
+  {CPU_F380, 0xfc, "PCA0CPH0"},
+  {CPU_F380, 0xfd, "PCA0CPL4"},
+  {CPU_F380, 0xfe, "PCA0CPH4"},
+  {CPU_F380, 0xff, "VDM0CN"},
+  
+  {0, 0, NULL}
+};
+
+/*
+ * Names of bits
+ */
+
+static struct name_entry bit_tab51[]=
+{
+  /* PSW */
+  {CPU_ALL_51|CPU_ALL_52|CPU_251, 0xd7, "CY"},
+  {CPU_ALL_51|CPU_ALL_52|CPU_251, 0xd6, "AC"},
+  {CPU_ALL_51|CPU_ALL_52|CPU_251, 0xd5, "F0"},
+  {CPU_ALL_51|CPU_ALL_52|CPU_251, 0xd4, "RS1"},
+  {CPU_ALL_51|CPU_ALL_52|CPU_251, 0xd3, "RS0"},
+  {CPU_ALL_51|CPU_ALL_52|CPU_251, 0xd2, "OV"},
+  {CPU_ALL_51|CPU_ALL_52|CPU_251, 0xd1, "F1"},
+  {CPU_ALL_51|CPU_ALL_52|CPU_251, 0xd0, "P"},
+  /* TCON */
+  {CPU_ALL_51|CPU_ALL_52|CPU_251, 0x8f, "TF1"},
+  {CPU_ALL_51|CPU_ALL_52|CPU_251, 0x8e, "TR1"},
+  {CPU_ALL_51|CPU_ALL_52|CPU_251, 0x8d, "TF0"},
+  {CPU_ALL_51|CPU_ALL_52|CPU_251, 0x8c, "TR0"},
+  {CPU_ALL_51|CPU_ALL_52|CPU_251, 0x8b, "IE1"},
+  {CPU_ALL_51|CPU_ALL_52|CPU_251, 0x8a, "IT1"},
+  {CPU_ALL_51|CPU_ALL_52|CPU_251, 0x89, "IE0"},
+  {CPU_ALL_51|CPU_ALL_52|CPU_251, 0x88, "IT0"},
+  /* IE */
+  {CPU_ALL_51|CPU_ALL_52|CPU_251, 0xaf, "EA"},
+  {CPU_DS390|CPU_DS390F,          0xae, "ES1"},
+  {CPU_89C51R|CPU_251,            0xae, "EC"},
+  {CPU_ALL_52|CPU_251,            0xad, "ET2"},
+  {CPU_DS390|CPU_DS390F,          0xac, "ES0"},
+  {CPU_ALL_51|CPU_ALL_52|CPU_251, 0xac, "ES"},
+  {CPU_ALL_51|CPU_ALL_52|CPU_251, 0xab, "ET1"},
+  {CPU_ALL_51|CPU_ALL_52|CPU_251, 0xaa, "EX1"},
+  {CPU_ALL_51|CPU_ALL_52|CPU_251, 0xa9, "ET0"},
+  {CPU_ALL_51|CPU_ALL_52|CPU_251, 0xa8, "EX0"},
+  /* IP */
+  {CPU_89C51R|CPU_251,    0xbe, "PPC"},
+  {CPU_DS390|CPU_DS390F,  0xbe, "PS1"},
+  {CPU_ALL_52,            0xbd, "PT2"},
+  {CPU_DS390|CPU_DS390F,  0xbc, "PS0"},
+  {CPU_ALL_51|CPU_ALL_52, 0xbc, "PS"},
+  {CPU_ALL_51|CPU_ALL_52, 0xbb, "PT1"},
+  {CPU_ALL_51|CPU_ALL_52, 0xba, "PX1"},
+  {CPU_ALL_51|CPU_ALL_52, 0xb9, "PT0"},
+  {CPU_ALL_51|CPU_ALL_52, 0xb8, "PX0"},
+  /* IPL0 */
+  {CPU_251, 0xbe, "IPL0.6"},
+  {CPU_251, 0xbd, "IPL0.5"},
+  {CPU_251, 0xbc, "IPL0.4"},
+  {CPU_251, 0xbb, "IPL0.3"},
+  {CPU_251, 0xba, "IPL0.2"},
+  {CPU_251, 0xb9, "IPL0.1"},
+  {CPU_251, 0xb8, "IPL0.0"},
+  /* SCON */
+  {CPU_DS390|CPU_DS390F,          0x9f, "SM0/FE_0"},
+  {CPU_DS390|CPU_DS390F,          0x9e, "SM1_0"},
+  {CPU_DS390|CPU_DS390F,          0x9d, "SM2_0"},
+  {CPU_DS390|CPU_DS390F,          0x9c, "REN_0"},
+  {CPU_DS390|CPU_DS390F,          0x9b, "TB8_0"},
+  {CPU_DS390|CPU_DS390F,          0x9a, "RB8_0"},
+  {CPU_DS390|CPU_DS390F,          0x99, "TI_0"},
+  {CPU_DS390|CPU_DS390F,          0x98, "RI_0"},
+
+  {CPU_51R|CPU_89C51R|CPU_251,    0x9f, "FE/SM0"},
+  {CPU_ALL_51|CPU_ALL_52,         0x9f, "SM0"},
+  {CPU_ALL_51|CPU_ALL_52|CPU_251, 0x9e, "SM1"},
+  {CPU_ALL_51|CPU_ALL_52|CPU_251, 0x9d, "SM2"},
+  {CPU_ALL_51|CPU_ALL_52|CPU_251, 0x9c, "REN"},
+  {CPU_ALL_51|CPU_ALL_52|CPU_251, 0x9b, "TB8"},
+  {CPU_ALL_51|CPU_ALL_52|CPU_251, 0x9a, "RB8"},
+  {CPU_ALL_51|CPU_ALL_52|CPU_251, 0x99, "TI"},
+  {CPU_ALL_51|CPU_ALL_52|CPU_251, 0x98, "RI"},
+  /* SCON 1 */
+  {CPU_DS390|CPU_DS390F,          0xc7, "SM0/FE_1"},
+  {CPU_DS390|CPU_DS390F,          0xc6, "SM1_1"},
+  {CPU_DS390|CPU_DS390F,          0xc5, "SM2_1"},
+  {CPU_DS390|CPU_DS390F,          0xc4, "REN_1"},
+  {CPU_DS390|CPU_DS390F,          0xc3, "TB8_1"},
+  {CPU_DS390|CPU_DS390F,          0xc2, "RB8_1"},
+  {CPU_DS390|CPU_DS390F,          0xc1, "TI_1"},
+  {CPU_DS390|CPU_DS390F,          0xc0, "RI_1"},
+  /* T2CON */
+  {CPU_ALL_52|CPU_251, 0xcf, "TF2"},
+  {CPU_ALL_52|CPU_251, 0xce, "EXF2"},
+  {CPU_ALL_52|CPU_251, 0xcd, "RCLK"},
+  {CPU_ALL_52|CPU_251, 0xcc, "TCLK"},
+  {CPU_ALL_52|CPU_251, 0xcb, "EXEN2"},
+  {CPU_ALL_52|CPU_251, 0xca, "TR2"},
+  {CPU_ALL_52|CPU_251, 0xc9, "C/T2"},
+  {CPU_ALL_52|CPU_251, 0xc8, "CP/RL2"},
+  /* CCON */
+  {CPU_89C51R|CPU_251, 0xdf, "CF"},
+  {CPU_89C51R|CPU_251, 0xde, "CR"},
+  {CPU_89C51R|CPU_251, 0xdc, "CCF4"},
+  {CPU_89C51R|CPU_251, 0xdb, "CCF3"},
+  {CPU_89C51R|CPU_251, 0xda, "CCF2"},
+  {CPU_89C51R|CPU_251, 0xd9, "CCF1"},
+  {CPU_89C51R|CPU_251, 0xd8, "CCF0"},
+  /* P1 */
+  {CPU_89C51R|CPU_251, 0x97, "CEX4"},
+  {CPU_89C51R|CPU_251, 0x96, "CEX3"},
+  {CPU_89C51R|CPU_251, 0x95, "CEX2"},
+  {CPU_89C51R|CPU_251, 0x94, "CEX1"},
+  {CPU_89C51R|CPU_251, 0x93, "CEX0"},
+  {CPU_89C51R|CPU_251, 0x92, "EXI"},
+  {CPU_89C51R|CPU_251, 0x91, "T2EX"},
+  {CPU_89C51R|CPU_251, 0x90, "T2"},
+  /* WDCON */
+  {CPU_DS390|CPU_DS390F, 0xdf, "SMOD_1"},
+  {CPU_DS390|CPU_DS390F, 0xde, "POR,"},
+  {CPU_DS390|CPU_DS390F, 0xdd, "EPF1"},
+  {CPU_DS390|CPU_DS390F, 0xdc, "PF1"},
+  {CPU_DS390|CPU_DS390F, 0xdb, "WDIF"},
+  {CPU_DS390|CPU_DS390F, 0xda, "WTRF"},
+  {CPU_DS390|CPU_DS390F, 0xd9, "EWT"},
+  {CPU_DS390|CPU_DS390F, 0xd8, "RWT"},
+  /* EIE */
+  {CPU_DS390|CPU_DS390F, 0xef, "CANBIE"},
+  {CPU_DS390|CPU_DS390F, 0xee, "C0IE"},
+  {CPU_DS390|CPU_DS390F, 0xed, "C1IE"},
+  {CPU_DS390|CPU_DS390F, 0xec, "EWDI"},
+  {CPU_DS390|CPU_DS390F, 0xeb, "EX5"},
+  {CPU_DS390|CPU_DS390F, 0xea, "EX4"},
+  {CPU_DS390|CPU_DS390F, 0xe9, "EX3"},
+  {CPU_DS390|CPU_DS390F, 0xe8, "EX2"},
+  /* EIP */
+  {CPU_DS390|CPU_DS390F, 0xef, "CANBIP"},
+  {CPU_DS390|CPU_DS390F, 0xee, "C0IP"},
+  {CPU_DS390|CPU_DS390F, 0xed, "C1IP"},
+  {CPU_DS390|CPU_DS390F, 0xec, "PWDI"},
+  {CPU_DS390|CPU_DS390F, 0xeb, "PX5"},
+  {CPU_DS390|CPU_DS390F, 0xea, "PX4"},
+  {CPU_DS390|CPU_DS390F, 0xe9, "PX3"},
+  {CPU_DS390|CPU_DS390F, 0xe8, "PX2"},
+
+  {0, 0, NULL}
+};
+
+
+/*
+ * Options of uc51
+ */
+
+cl_irq_stop_option::cl_irq_stop_option(class cl_51core *the_uc51):
+  cl_optref(the_uc51)
+{
+  uc51= the_uc51;
+}
+
+int
+cl_irq_stop_option::init(void)
+{
+  cl_optref::init();
+  create(uc51, bool_opt, "irq_stop", "Stop when IRQ accepted");
+  return(0);
+}
+
+void
+cl_irq_stop_option::option_changed(void)
+{
+  if (!uc51)
+    return;
+  bool b;
+  option->get_value(&b);
+  uc51->stop_at_it= b;
+}
+
+instruction_wrapper_fn itab51[256];
+
+/*
+ * Making a new micro-controller and reset it
+ */
+
+cl_51core::cl_51core(struct cpu_entry *Itype, class cl_sim *asim):
+  cl_uc(asim)
+{
+  type= Itype;
+
+  irq_stop_option= new cl_irq_stop_option(this);
+  stop_at_it= false;
+}
+
+
+/*
+ * Initializing. Virtual calls go here
+ * This method must be called first after object creation.
+ */
+
+int
+cl_51core::init(void)
+{
+  fill_def_wrappers(itab51);
+  itab51[0x89]= itab51[0x88];
+  itab51[0x8a]= itab51[0x88];
+  itab51[0x8b]= itab51[0x88];
+  itab51[0x8c]= itab51[0x88];
+  itab51[0x8d]= itab51[0x88];
+  itab51[0x8e]= itab51[0x88];
+  itab51[0x8f]= itab51[0x88];
+
+  itab51[0xf9]= itab51[0xf8];
+  itab51[0xfa]= itab51[0xf8];
+  itab51[0xfb]= itab51[0xf8];
+  itab51[0xfc]= itab51[0xf8];
+  itab51[0xfd]= itab51[0xf8];
+  itab51[0xfe]= itab51[0xf8];
+  itab51[0xff]= itab51[0xf8];
+
+  itab51[0x21]= itab51[0x01];
+  itab51[0x41]= itab51[0x01];
+  itab51[0x61]= itab51[0x01];
+  itab51[0x81]= itab51[0x01];
+  itab51[0xa1]= itab51[0x01];
+  itab51[0xc1]= itab51[0x01];
+  itab51[0xe1]= itab51[0x01];
+
+  itab51[0x07]= itab51[0x06];
+
+  itab51[0x09]= itab51[0x08];
+  itab51[0x0a]= itab51[0x08];
+  itab51[0x0b]= itab51[0x08];
+  itab51[0x0c]= itab51[0x08];
+  itab51[0x0d]= itab51[0x08];
+  itab51[0x0e]= itab51[0x08];
+  itab51[0x0f]= itab51[0x08];
+
+  itab51[0x31]= itab51[0x11];
+  itab51[0x51]= itab51[0x11];
+  itab51[0x71]= itab51[0x11];
+  itab51[0x91]= itab51[0x11];
+  itab51[0xb1]= itab51[0x11];
+  itab51[0xd1]= itab51[0x11];
+  itab51[0xf1]= itab51[0x11];
+
+  itab51[0x17]= itab51[0x16];
+
+  itab51[0x19]= itab51[0x18];
+  itab51[0x1a]= itab51[0x18];
+  itab51[0x1b]= itab51[0x18];
+  itab51[0x1c]= itab51[0x18];
+  itab51[0x1d]= itab51[0x18];
+  itab51[0x1e]= itab51[0x18];
+  itab51[0x1f]= itab51[0x18];
+
+  itab51[0x29]= itab51[0x28];
+  itab51[0x2a]= itab51[0x28];
+  itab51[0x2b]= itab51[0x28];
+  itab51[0x2c]= itab51[0x28];
+  itab51[0x2d]= itab51[0x28];
+  itab51[0x2e]= itab51[0x28];
+  itab51[0x2f]= itab51[0x28];
+
+  itab51[0x27]= itab51[0x26];
+
+  itab51[0x37]= itab51[0x36];
+  
+  itab51[0x39]= itab51[0x38];
+  itab51[0x3a]= itab51[0x38];
+  itab51[0x3b]= itab51[0x38];
+  itab51[0x3c]= itab51[0x38];
+  itab51[0x3d]= itab51[0x38];
+  itab51[0x3e]= itab51[0x38];
+  itab51[0x3f]= itab51[0x38];
+
+  itab51[0x47]= itab51[0x46];
+
+  itab51[0x49]= itab51[0x48];
+  itab51[0x4a]= itab51[0x48];
+  itab51[0x4b]= itab51[0x48];
+  itab51[0x4c]= itab51[0x48];
+  itab51[0x4d]= itab51[0x48];
+  itab51[0x4e]= itab51[0x48];
+  itab51[0x4f]= itab51[0x48];
+
+  itab51[0x97]= itab51[0x96];
+
+  itab51[0x99]= itab51[0x98];
+  itab51[0x9a]= itab51[0x98];
+  itab51[0x9b]= itab51[0x98];
+  itab51[0x9c]= itab51[0x98];
+  itab51[0x9d]= itab51[0x98];
+  itab51[0x9e]= itab51[0x98];
+  itab51[0x9f]= itab51[0x98];
+
+  itab51[0xb7]= itab51[0xb6];
+
+  itab51[0xb9]= itab51[0xb8];
+  itab51[0xba]= itab51[0xb8];
+  itab51[0xbb]= itab51[0xb8];
+  itab51[0xbc]= itab51[0xb8];
+  itab51[0xbd]= itab51[0xb8];
+  itab51[0xbe]= itab51[0xb8];
+  itab51[0xbf]= itab51[0xb8];
+
+  itab51[0xd9]= itab51[0xd8];
+  itab51[0xda]= itab51[0xd8];
+  itab51[0xdb]= itab51[0xd8];
+  itab51[0xdc]= itab51[0xd8];
+  itab51[0xdd]= itab51[0xd8];
+  itab51[0xde]= itab51[0xd8];
+  itab51[0xdf]= itab51[0xd8];
+
+  itab51[0x57]= itab51[0x56];
+
+  itab51[0x59]= itab51[0x58];
+  itab51[0x5a]= itab51[0x58];
+  itab51[0x5b]= itab51[0x58];
+  itab51[0x5c]= itab51[0x58];
+  itab51[0x5d]= itab51[0x58];
+  itab51[0x5e]= itab51[0x58];
+  itab51[0x5f]= itab51[0x58];
+
+  itab51[0x67]= itab51[0x66];
+
+  itab51[0x69]= itab51[0x68];
+  itab51[0x6a]= itab51[0x68];
+  itab51[0x6b]= itab51[0x68];
+  itab51[0x6c]= itab51[0x68];
+  itab51[0x6d]= itab51[0x68];
+  itab51[0x6e]= itab51[0x68];
+  itab51[0x6f]= itab51[0x68];
+
+  itab51[0x77]= itab51[0x76];
+
+  itab51[0x79]= itab51[0x78];
+  itab51[0x7a]= itab51[0x78];
+  itab51[0x7b]= itab51[0x78];
+  itab51[0x7c]= itab51[0x78];
+  itab51[0x7d]= itab51[0x78];
+  itab51[0x7e]= itab51[0x78];
+  itab51[0x7f]= itab51[0x78];
+
+  itab51[0x87]= itab51[0x86];
+
+  itab51[0xa7]= itab51[0xa6];
+
+  itab51[0xa9]= itab51[0xa8];
+  itab51[0xaa]= itab51[0xa8];
+  itab51[0xab]= itab51[0xa8];
+  itab51[0xac]= itab51[0xa8];
+  itab51[0xad]= itab51[0xa8];
+  itab51[0xae]= itab51[0xa8];
+  itab51[0xaf]= itab51[0xa8];
+
+  itab51[0xc7]= itab51[0xc6];
+
+  itab51[0xc9]= itab51[0xc8];
+  itab51[0xca]= itab51[0xc8];
+  itab51[0xcb]= itab51[0xc8];
+  itab51[0xcc]= itab51[0xc8];
+  itab51[0xcd]= itab51[0xc8];
+  itab51[0xce]= itab51[0xc8];
+  itab51[0xcf]= itab51[0xc8];
+
+  itab51[0xd7]= itab51[0xd6];
+
+  itab51[0xe3]= itab51[0xe2];
+
+  itab51[0xe7]= itab51[0xe6];
+
+  itab51[0xe9]= itab51[0xe8];
+  itab51[0xea]= itab51[0xe8];
+  itab51[0xeb]= itab51[0xe8];
+  itab51[0xec]= itab51[0xe8];
+  itab51[0xed]= itab51[0xe8];
+  itab51[0xee]= itab51[0xe8];
+  itab51[0xef]= itab51[0xe8];
+
+  itab51[0xf3]= itab51[0xf2];
+
+  itab51[0xf7]= itab51[0xf6];
+
+  irq_stop_option->init();
+  dptr= 0;
+  cl_uc::init();
+  decode_dptr();
+  set_name("mcs51_controller");
+  reset();
+
+  make_vars();
+
+  return(0);
+}
+
+static char id_string_51[100];
+
+char *
+cl_51core::id_string(void)
+{
+  int i;
+
+  for (i= 0;
+       (cpus_51[i].type_str != NULL) &&
+	 (cpus_51[i].type != type->type);
+       i++) ;
+  sprintf(id_string_51, "%s %s",
+	  cpus_51[i].type_str?cpus_51[i].type_str:"51",
+	  (type->subtype & CPU_HMOS)?"HMOS":"CMOS");
+  return(id_string_51);
+}
+
+void
+cl_51core::make_cpu_hw(void)
+{
+  cpu= new cl_uc51_cpu(this);
+  cpu->init();
+}
+
+void
+cl_51core::mk_hw_elements(void)
+{
+  cl_uc::mk_hw_elements();
+
+  class cl_hw *h;
+
+  acc= sfr->get_cell(ACC);
+  psw= sfr->get_cell(PSW);
+
+  add_hw(h= new cl_timer0(this, 0, "timer0"));
+  h->init();
+  add_hw(h= new cl_timer1(this, 1, "timer1"));
+  h->init();
+  add_hw(h= new cl_serial(this));
+  h->init();
+
+  class cl_port_ui *d;
+  add_hw(d= new cl_port_ui(this, 0, "dport"));
+  d->init();
+
+  class cl_port *p0, *p1, *p2, *p3;
+  add_hw(p0= new cl_port(this, 0));
+  p0->init();
+  add_hw(p1= new cl_port(this, 1));
+  p1->init();
+  add_hw(p2= new cl_port(this, 2));
+  p2->init();
+  add_hw(p3= new cl_port(this, 3));
+  p3->init();
+
+  class cl_port_data pd;
+  pd.init();
+  pd.cell_dir= NULL;
+
+  pd.set_name("P0");
+  pd.cell_p  = p0->cell_p;
+  pd.cell_in = p0->cell_in;
+  pd.keyset  = chars(keysets[0]);
+  pd.basx    = 1;
+  pd.basy    = 4;
+  d->add_port(&pd, 0);
+  
+  pd.set_name("P1");
+  pd.cell_p  = p1->cell_p;
+  pd.cell_in = p1->cell_in;
+  pd.keyset  = chars(keysets[1]);
+  pd.basx    = 20;
+  pd.basy    = 4;
+  d->add_port(&pd, 1);
+  
+  pd.set_name("P2");
+  pd.cell_p  = p2->cell_p;
+  pd.cell_in = p2->cell_in;
+  pd.keyset  = chars(keysets[2]);
+  pd.basx    = 40;
+  pd.basy    = 4;
+  d->add_port(&pd, 2);
+  
+  pd.set_name("P3");
+  pd.cell_p  = p3->cell_p;
+  pd.cell_in = p3->cell_in;
+  pd.keyset  = chars(keysets[3]);
+  pd.basx    = 60;
+  pd.basy    = 4;
+  d->add_port(&pd, 3);
+  
+  add_hw(interrupt= new cl_interrupt(this));
+  interrupt->init();
+}
+
+void
+cl_51core::build_cmdset(class cl_cmdset *cmdset)
+{
+  class cl_cmd *cmd;
+  //class cl_super_cmd *super_cmd;
+  //class cl_cmdset *cset;
+
+  cl_uc::build_cmdset(cmdset);
+
+  cmdset->add(cmd= new cl_di_cmd("di", true));
+  cmd->init();
+
+  cmdset->add(cmd= new cl_dx_cmd("dx", true));
+  cmd->init();
+
+  cmdset->add(cmd= new cl_ds_cmd("ds", true));
+  cmd->init();
+}
+
+
+void
+cl_51core::make_memories(void)
+{
+  make_address_spaces();
+  make_chips();
+  
+  acc= sfr->get_cell(ACC);
+  psw= sfr->get_cell(PSW);
+
+  decode_regs();
+  decode_rom();
+  decode_iram();
+  decode_sfr();
+  decode_xram();
+  decode_bits();
+}
+
+void
+cl_51core::make_address_spaces(void)
+{
+  rom= new cl_address_space("rom", 0, 0x10000, 8);
+  rom->init();
+  address_spaces->add(rom);
+  
+  iram= new cl_address_space("iram", 0, 0x80, 8);
+  iram->init();
+  address_spaces->add(iram);
+
+  sfr= new cl_address_space("sfr", 0x80, 0x80, 8);
+  sfr->init();
+  address_spaces->add(sfr);
+
+  xram= new cl_address_space("xram", 0, 0x10000, 8);
+  xram->init();
+  address_spaces->add(xram);
+
+  regs= new cl_address_space("regs", 0, 8, 8);
+  regs->init();
+  address_spaces->add(regs);
+
+  bits= new cl_address_space("bits", 0, 0x100, 1);
+  bits->init();
+  address_spaces->add(bits);
+
+  dptr= new cl_address_space("dptr", 0, 2, 8);
+  dptr->init();
+  address_spaces->add(dptr);
+}
+
+void
+cl_51core::make_chips(void)
+{
+  rom_chip= new cl_memory_chip("rom_chip", 0x10000, 8, 0/*, 0xff*/);
+  rom_chip->init();
+  memchips->add(rom_chip);
+  
+  iram_chip= new cl_memory_chip("iram_chip", 0x100, 8);
+  iram_chip->init();
+  memchips->add(iram_chip);
+
+  xram_chip= new cl_memory_chip("xram_chip", 0x10000, 8);
+  xram_chip->init();
+  memchips->add(xram_chip);
+
+  sfr_chip= new cl_memory_chip("sfr_chip", 0x80, 8);
+  sfr_chip->init();
+  memchips->add(sfr_chip);
+}
+
+void
+cl_51core::decode_rom(void)
+{
+  class cl_address_decoder *ad;
+  ad= new cl_address_decoder(rom, rom_chip, 0, 0xffff, 0);
+  ad->init();
+  ad->set_name("def_rom_decoder");
+  rom->decoders->add(ad);
+  ad->activate(0);
+}
+
+void
+cl_51core::decode_regs(void)
+{
+  int i;
+  cl_banker *b= new cl_banker(sfr, 0xd0, 0x18, //0,
+			      regs, 0, 7);
+  b->init();
+  b->set_name("def_regs_banker");
+  regs->decoders->add(b);
+  b->add_bank(0, memory("iram_chip"), 0);
+  b->add_bank(1, memory("iram_chip"), 8);
+  b->add_bank(2, memory("iram_chip"), 16);
+  b->add_bank(3, memory("iram_chip"), 24);
+  psw->write(0);
+  for (i= 0; i < 8; i++)
+    R[i]= regs->get_cell(i);
+}
+
+void
+cl_51core::decode_bits(void)
+{
+  class cl_address_decoder *ad;
+  
+  ad= new cl_bander(bits, 0, 127,
+		    iram_chip, 32,
+		    8, 1);
+  ad->init();
+  ad->set_name("def_bits_bander_0-7f");
+  bits->decoders->add(ad);
+  ad->activate(0);
+
+  ad= new cl_bander(bits, 128, 255,
+		    sfr_chip, 0,
+		    8, 8);
+  ad->init();
+  ad->set_name("def_bits_bander_80-ff");
+  bits->decoders->add(ad);
+  ad->activate(0);
+}
+
+void
+cl_51core::decode_iram(void)
+{
+  class cl_address_decoder *ad;
+  
+  ad= new cl_address_decoder(iram, iram_chip, 0, 0x7f, 0);
+  ad->init();
+  ad->set_name("def_iram_decoder");
+  iram->decoders->add(ad);
+  ad->activate(0);
+}
+
+void
+cl_51core::decode_sfr(void)
+{
+  class cl_address_decoder *ad;
+  
+  ad= new cl_address_decoder(sfr, sfr_chip, 0x80, 0xff, 0);
+  ad->init();
+  ad->set_name("def_sfr_decoder");
+  sfr->decoders->add(ad);
+  ad->activate(0);
+}
+
+void
+cl_51core::decode_xram(void)
+{
+  class cl_address_decoder *ad;
+  
+  ad= new cl_address_decoder(xram, xram_chip, 0, 0xffff, 0);
+  ad->init();
+  ad->set_name("def_xram_decoder");
+  xram->decoders->add(ad);
+  ad->activate(0);
+}
+
+void
+cl_51core::decode_dptr(void)
+{
+  class cl_address_decoder *ad;
+  t_mem adps= 0, mdps, dpl1, dph1, mdpc, adpc;
+  class cl_banker *banker;
+
+  dptr->undecode_area(NULL, 0, 1, NULL);
+  
+  if (cpu)
+    {
+      adps= cpu->cfg_get(uc51cpu_aof_mdps);
+      mdps= cpu->cfg_get(uc51cpu_mask_mdps);
+      dpl1= cpu->cfg_get(uc51cpu_aof_mdps1l);
+      dph1= cpu->cfg_get(uc51cpu_aof_mdps1h);
+
+      adpc= cpu->cfg_get(uc51cpu_aof_mdpc);
+      mdpc= cpu->cfg_get(uc51cpu_mask_mdpc);
+      
+      if ((adps > 0x7f) &&
+	  (dpl1 > 0x7f) &&
+	  (dph1 > 0x7f))
+	{
+	  // multi DPTR sfr style
+	  //printf("MDPS %x %x %x %x\n", adps, mdps, dpl1, dph1);
+	  banker= new cl_banker(sfr, adps, mdps, //0,
+				dptr, 0, 0);
+	  banker->init();
+	  dptr->decoders->add(banker);
+	  banker->add_bank(0, memory("sfr_chip"), DPL-0x80);
+	  banker->add_bank(1, memory("sfr_chip"), dpl1-0x80);
+	  banker->activate(0);
+
+	  banker= new cl_banker(sfr, adps, mdps, //0,
+				dptr, 1, 1);
+	  banker->init();
+	  dptr->decoders->add(banker);
+	  banker->add_bank(0, memory("sfr_chip"), DPH-0x80);
+	  banker->add_bank(1, memory("sfr_chip"), dph1-0x80);
+	  banker->activate(0);
+
+	  sfr->write(adps, sfr->get(adps));
+	}
+      else if (adpc > 0x7f)
+	{
+	  // multi DPTR chip style
+	  adps=0x80;
+	  class cl_memory_chip *dptr_chip= (cl_memory_chip*)memory("dptr_chip");
+	  if (dptr_chip == 0)
+	    {
+	      dptr_chip= new cl_memory_chip("dptr_chip", 3*8, 8);
+	      dptr_chip->init();
+	      memchips->add(dptr_chip);
+	    }
+	  if (dptr_chip &&
+	      (mdpc != 0))
+	    {
+	      int a, m= mdpc;
+	      //printf("MDPC %x %x\n", adpc, mdpc);
+	      while ((m&1) == 0)
+		m>>= 1;
+	      
+	      banker= new cl_banker(sfr, adpc, mdpc, //0,
+			    dptr, 0, 1);
+	      banker->init();
+	      dptr->decoders->add(banker);
+	      for (a= 0; a <= m; a++)
+		banker->add_bank(a, dptr_chip, a*2);
+	      banker->activate(0);
+
+	      banker= new cl_banker(sfr, adpc, mdpc, //0,
+			    sfr, DPL, DPH);
+	      banker->init();
+	      sfr->decoders->add(banker);
+	      for (a= 0; a <= m; a++)
+		banker->add_bank(a, dptr_chip, a*2);
+	      banker->activate(0);
+	      
+	      sfr->write(adpc, sfr->get(adpc));
+	    }
+	}
+      else
+	adps= 0;
+    }
+  if (adps == 0)
+    {
+      //printf("DPTR\n");
+      ad= new cl_address_decoder(dptr, sfr_chip, 0, 1, DPL-0x80);
+      ad->init();
+      dptr->decoders->add(ad);
+      ad->activate(0);
+    }
+  
+  cl_var *v;
+  vars->add(v= new cl_var(chars("dpl"), dptr, 0, ""));
+  v->init();
+  vars->add(v= new cl_var(chars("DPL"), dptr, 0, ""));
+  v->init();
+  vars->add(v= new cl_var(chars("dph"), dptr, 1, ""));
+  v->init();
+  vars->add(v= new cl_var(chars("DPH"), dptr, 1, ""));
+  v->init();
+}
+
+void
+cl_51core::make_vars(void)
+{
+  cl_var *v;
+
+  vars->add(v= new cl_var(cchars("R0"), regs, 0, ""));
+  v->init();
+  vars->add(v= new cl_var(cchars("R1"), regs, 1, ""));
+  v->init();
+  vars->add(v= new cl_var(cchars("R2"), regs, 2, ""));
+  v->init();
+  vars->add(v= new cl_var(cchars("R3"), regs, 3, ""));
+  v->init();
+  vars->add(v= new cl_var(cchars("R4"), regs, 4, ""));
+  v->init();
+  vars->add(v= new cl_var(cchars("R5"), regs, 5, ""));
+  v->init();
+  vars->add(v= new cl_var(cchars("R6"), regs, 6, ""));
+  v->init();
+  vars->add(v= new cl_var(cchars("R7"), regs, 7, ""));
+  v->init();
+
+  int i;
+  for (i= 0; sfr_tab51[i].name != NULL; i++)
+    {
+      if (type->type & sfr_tab51[i].cpu_type)
+	{
+	  vars->add(v= new cl_var(chars(sfr_tab51[i].name),
+				  sfr,
+				  sfr_tab51[i].addr, ""));
+	  v->init();
+	}
+    }
+  for (i= 0; bit_tab51[i].name != NULL; i++)
+    {
+      if (type->type & bit_tab51[i].cpu_type)
+	{
+	  vars->add(v= new cl_var(chars(bit_tab51[i].name),
+				  bits,
+				  bit_tab51[i].addr, ""));
+	  v->init();
+	}
+    }
+}
+
+/*
+ * Destroying the micro-controller object
+ */
+
+cl_51core::~cl_51core(void)
+{
+  delete irq_stop_option;
+}
+
+
+/*
+ * Disassembling an instruction
+ */
+
+struct dis_entry *
+cl_51core::dis_tbl(void)
+{
+  return(disass_51);
+}
+
+struct name_entry *
+cl_51core::bit_tbl(void)
+{
+  return(bit_tab51);
+}
+
+char *
+cl_51core::disass(t_addr addr, const char *sep)
+{
+  char work[256], temp[200]/*, c[2]*/;
+  char *buf, *p, *t, *s;
+  const char *b;
+  t_mem code= rom->get(addr);
+
+  p= work;
+  b= dis_tbl()[code].mnemonic;
+  while (*b)
+    {
+      if (*b == '%')
+	{
+	  b++;
+	  switch (*(b++))
+	    {
+	    case 'A': // absolute address
+	      sprintf(temp, "%04x",
+		      /*t_addr*/int((addr&0xf800)|
+				    (((code>>5)&0x07)*256 +
+				     rom->get(addr+1))));
+	      break;
+	    case 'l': // long address
+	      sprintf(temp, "%04x",
+		      /*t_addr*/int(rom->get(addr+1)*256 +
+				    rom->get(addr+2)));
+	      break;
+	    case 'a': // addr8 (direct address) at 2nd byte
+	      daddr_name(rom->get(addr+1), temp);
+	      break;
+	    case '8': // addr8 (direct address) at 3rd byte
+	      daddr_name(rom->get(addr+2), temp);
+	      break;
+	    case 'b': // bitaddr at 2nd byte
+	      {
+		t_addr ba= rom->get(addr+1);
+		/*if (get_name(ba, bit_tbl(), temp))
+		  break;
+		if (ba<128)
+		  addr_name((ba/8)+32,iram,temp);
+		else
+		  addr_name(ba&0xf8,sfr,temp);
+		strcat(temp, ".");
+		sprintf(c, "%1d", (int)(ba & 0x07));
+		strcat(temp, c);*/
+		baddr_name(ba, temp);
+		break;
+	      }
+	    case 'r': // rel8 address at 2nd byte
+	      sprintf(temp, "%04x",
+		      /*t_addr*/int(addr+2+(signed char)(rom->get(addr+1))));
+	      break;
+	    case 'R': // rel8 address at 3rd byte
+	      sprintf(temp, "%04x",
+		      /*t_addr*/int(addr+3+(signed char)(rom->get(addr+2))));
+	      break;
+	    case 'd': // data8 at 2nd byte
+	      sprintf(temp, "%02x", (int)rom->get(addr+1));
+	      break;
+	    case 'D': // data8 at 3rd byte
+	      sprintf(temp, "%02x", (int)rom->get(addr+2));
+	      break;
+	    case '6': // data16 at 2nd(H)-3rd(L) byte
+	      sprintf(temp, "%04x",
+		      /*t_addr*/int(rom->get(addr+1)*256 +
+				    rom->get(addr+2)));
+	      break;
+	    default:
+	      strcpy(temp, "?");
+	      break;
+	    }
+	  t= temp;
+	  while (*t)
+	    *(p++)= *(t++);
+	}
+      else
+	*(p++)= *(b++);
+    }
+  *p= '\0';
+
+  p= strchr(work, ' ');
+  if (!p)
+    {
+      buf= strdup(work);
+      return(buf);
+    }
+  if (sep == NULL)
+    buf= (char *)malloc(6+strlen(p)+1);
+  else
+    buf= (char *)malloc((p-work)+strlen(sep)+strlen(p)+1);
+  for (p= work, s= buf; *p != ' '; p++, s++)
+    *s= *p;
+  p++;
+  *s= '\0';
+  if (sep == NULL)
+    {
+      while (strlen(buf) < 6)
+	strcat(buf, " ");
+    }
+  else
+    strcat(buf, sep);
+  strcat(buf, p);
+  return(buf);
+}
+
+
+void
+cl_51core::print_regs(class cl_console_base *con)
+{
+  t_addr start;
+  t_mem data;
+  t_mem dp;
+  
+  // show regs
+  start= psw->get() & 0x18;
+  con->dd_printf("     R0 R1 R2 R3 R4 R5 R6 R7\n");
+  iram->dump(start, start+7, 8, con/*->get_fout()*/);
+  con->dd_color("answer");
+  // show indirectly addressed IRAM and some basic regs
+  data= iram->get(iram->get(start));
+  con->dd_printf("@R0 %02x %c", data, isprint(data) ? data : '.');
+
+  con->dd_printf("  ACC= 0x%02x %3d %c  B= 0x%02x\n", sfr->get(ACC), sfr->get(ACC),
+              isprint(sfr->get(ACC))?(sfr->get(ACC)):'.', sfr->get(B));
+  data= iram->get(iram->get(start+1));
+  con->dd_printf("@R1 %02x %c", data, isprint(data) ? data : '.');
+  data= psw->get();
+  con->dd_printf("  PSW= 0x%02x CY=%c AC=%c OV=%c P=%c\n", data,
+              (data&bmCY)?'1':'0', (data&bmAC)?'1':'0',
+              (data&bmOV)?'1':'0', (data&bmP)?'1':'0');
+  /* show stack pointer */
+  start = sfr->get (SP);
+  con->dd_printf ("SP ", start);
+  iram->dump (start, start - 7, 8, con/*->get_fout()*/);
+  con->dd_color("answer");
+  // show DPTR(s)
+  if (dptr)
+    {
+      int act;
+      int mask;
+	      int i;
+      if (cpu &&
+	  (cpu->cfg_get(uc51cpu_aof_mdpc) > 0x7f))
+	{
+	  // multi DPTR chip style
+	  act= sfr->get(cpu->cfg_get(uc51cpu_aof_mdpc));
+	  mask= cpu->cfg_get(uc51cpu_mask_mdpc);
+	  while ((mask&1) == 0)
+	    {
+	      act>>= 1;
+	      mask>>= 1;
+	    }
+	  act&= mask;
+	  class cl_memory *dptr_chip= memory("dptr_chip");
+	  if (dptr_chip)
+	    {
+	      for (i= 0; i <= mask; i++)
+		{
+		  int a= i*dptr->get_size();
+		  dp= 0;
+		  int di;
+		  for (di= dptr->get_size()-1; di >= 0; di--)
+		    dp= (dp*256) + dptr_chip->get(a+di);
+		  con->dd_printf("  %cDPTR%d= ", (i==act)?'*':' ', i);
+		  con->dd_printf(xram->addr_format, dp);
+		  data= xram->read(dp);
+		  con->dd_printf(" @DPTR%d= ", i);
+		  con->dd_printf("0x%02x %3d %c\n", data, data,
+				 isprint(data)?data:'.');
+		}
+	    }
+	}
+      else if (cpu &&
+	  (cpu->cfg_get(uc51cpu_aof_mdps) > 0x7f))
+	{
+	  // multi DPTR sfr style
+	  act= sfr->get(cpu->cfg_get(uc51cpu_aof_mdps));
+	  mask= cpu->cfg_get(uc51cpu_mask_mdps);
+	  while ((mask&1) == 0)
+	    {
+	      act>>= 1;
+	      mask>>= 1;
+	    }
+	  act&= mask;
+	  i= 0;
+	  dp= (sfr_chip->get(DPL-0x80) +
+	       sfr_chip->get(DPH-0x80) * 256) & 0xffff;
+	  con->dd_printf("  %cDPTR%d= ", (i==act)?'*':' ', i);
+	  con->dd_printf(xram->addr_format, dp);
+	  data= xram->read(dp);
+	  con->dd_printf(" @DPTR%d= ", i);
+	  con->dd_printf("0x%02x %3d %c\n", data, data,
+			 isprint(data)?data:'.');
+	  i= 1;
+	  dp= sfr_chip->get(cpu->cfg_get(uc51cpu_aof_mdps1l) - 0x80) +
+	    sfr_chip->get(cpu->cfg_get(uc51cpu_aof_mdps1h) - 0x80) * 256;
+	  con->dd_printf("  %cDPTR%d= ", (i==act)?'*':' ', i);
+	  con->dd_printf(xram->addr_format, dp);
+	  data= xram->read(dp);
+	  con->dd_printf(" @DPTR%d= ", i);
+	  con->dd_printf("0x%02x %3d %c\n", data, data,
+			 isprint(data)?data:'.');
+	}
+      else
+	{
+	  // non-multi DPTR
+	  int a= dptr->get_size();
+	  dp= 0;
+	  int di;
+	  chars f="";
+	  for (di= a-1; di >= 0; di--)
+	    {
+	      dp= (dp*256) + dptr->get(di);
+	    }
+	  f.format("0x%%0%dx",a*2);
+	  data= xram->get(dp);
+	  con->dd_printf("   DPTR= ");
+	  con->dd_printf(/*xram->addr_format*/(char*)f, dp);
+	  con->dd_printf(" @DPTR= 0x%02x %3d %c\n",
+			 data, data, isprint(data)?data:'.');
+	}
+    }
+  else
+    {
+      // no dptr address space, read SFR directly
+      data= xram->get(sfr->read(DPH)*256+sfr->read(DPL));
+      con->dd_printf("   DPTR= 0x%02x%02x @DPTR= 0x%02x %3d %c\n",
+		     sfr->get(DPH),
+		     sfr->get(DPL),
+		     data, data, isprint(data)?data:'.');
+    }
+  
+  print_disass(PC, con);
+}
+
+
+/*
+ * Converting bit address into real memory
+ */
+
+class cl_address_space *
+cl_51core::bit2mem(t_addr bitaddr, t_addr *memaddr, t_mem *bitmask)
+{
+  class cl_address_space *m;
+  t_addr ma;
+
+  bitaddr&= 0xff;
+  if (bitaddr < 128)
+    {
+      m= iram;
+      ma= bitaddr/8 + 0x20;
+    }
+  else
+    {
+      m= sfr;
+      ma= bitaddr & 0xf8;
+    }
+  if (memaddr)
+    *memaddr= ma;
+  if (bitmask)
+    *bitmask= 1 << (bitaddr & 0x7);
+  return(m);
+}
+
+t_addr
+cl_51core::bit_address(class cl_memory *mem,
+		       t_addr mem_address, int bit_number)
+{
+  if (bit_number < 0 ||
+      bit_number > 7 ||
+      mem_address < 0)
+    return(-1);
+  class cl_memory *sfrchip= memory("sfr_chip");
+  if (mem == sfrchip)
+    {
+      mem= sfr;
+      mem_address+= sfr->start_address;
+    }
+  if (mem == sfr)
+    {
+      if (mem_address < 128 ||
+	  mem_address % 8 != 0 ||
+	  mem_address > 255)
+	return(-1);
+      return(128 + (mem_address-128) + bit_number);
+    }
+  if (mem == iram)
+    {
+      if (mem_address < 0x20 ||
+	  mem_address >= 0x20+32)
+	return(-1);
+      return((mem_address-0x20)*8 + bit_number);
+    }
+  return(-1);
+}
+
+/* Get name of directly addressed iram/sfr cell */
+
+void
+cl_51core::daddr_name(t_addr addr, char *buf)
+{
+  if (!buf)
+    return;
+  if (addr < 128)
+    {
+      // register?
+      if (addr_name(addr, regs, buf))
+	return;
+      // variale?
+      if (addr_name(addr, iram, buf))
+	return;
+    }
+  else
+    {
+      // dptr?
+      if (addr_name(addr-0x82, dptr, buf))
+	return;
+      // sfr?
+      if (addr_name(addr, sfr, buf))
+	return;
+    }
+  unsigned int a= addr;
+  sprintf(buf, "%02x", a);
+}
+
+/* Get name of a bit cell */
+
+void
+cl_51core::baddr_name(t_addr addr, char *buf)
+{
+  t_addr ma;
+  
+  if (!buf)
+    return;
+  if (addr_name(addr, bits, buf))
+    return;
+  if (addr < 128)
+    ma= 32+(addr/8);
+  else
+    ma= addr&0xf8;
+  daddr_name(ma, buf);
+  chars c= chars("", "%s.%d", buf, (int)(addr & 7));
+  strcpy(buf, (char*)c);
+}
+
+
+/*
+ * Resetting the micro-controller
+ */
+
+void
+cl_51core::reset(void)
+{
+  cl_uc::reset();
+
+  clear_sfr();
+
+  result= resGO;
+
+  //was_reti= false;
+}
+
+
+/*
+ * Setting up SFR area to reset value
+ */
+
+void
+cl_51core::clear_sfr(void)
+{
+  int i;
+
+  for (i= 0x80; i <= 0xff; i++)
+    sfr->set(i, 0);
+  sfr->/*set*/write(P0, 0xff);
+  sfr->/*set*/write(P1, 0xff);
+  sfr->/*set*/write(P2, 0xff);
+  sfr->/*set*/write(P3, 0xff);
+  prev_p1= /*port_pins[1] &*/ sfr->/*get*/read(P1);
+  prev_p3= /*port_pins[3] &*/ sfr->/*get*/read(P3);
+  sfr->write(ACC, 0);
+  sfr->write(B, 0);
+  sfr->write(PSW, 0);
+  sfr->write(SP, 7);
+  sfr->write(DPL, 0);
+  sfr->write(DPH, 0);
+  sfr->write(IP, 0);
+  sfr->write(IE, 0);
+  sfr->write(TMOD, 0);
+  sfr->write(TCON, 0);
+  sfr->write(TH0, 0);
+  sfr->write(TL0, 0);
+  sfr->write(TH1, 0);
+  sfr->write(TL1, 0);
+  sfr->write(SCON, 0);
+  sfr->write(PCON, 0);
+
+  sfr->set_nuof_writes(0);
+  sfr->set_nuof_reads(0);
+}
+
+
+/*
+ * Analyzing code and settig up instruction map
+ */
+
+void
+cl_51core::analyze(t_addr addr)
+{
+  uint code;
+  struct dis_entry *tabl;
+
+  code= rom->get(addr);
+  tabl= &(dis_tbl()[code]);
+  while (!inst_at(addr) &&
+	 code != 0xa5 /* break point */)
+    {
+      set_inst_at(addr);
+      switch (tabl->branch)
+	{
+	case 'a': // acall
+	  analyze((addr & 0xf800)|
+		  ((rom->get(addr+1)&0x07)*256+
+		   rom->get(addr+2)));
+	  analyze(addr+tabl->length);
+	  break;
+	case 'A': // ajmp
+	  addr= (addr & 0xf800)|
+	    ((rom->get(addr+1) & 0x07)*256 + rom->get(addr+2));
+	  break;
+	case 'l': // lcall
+	  analyze(rom->get(addr+1)*256 + rom->get(addr+2));
+	  analyze(addr+tabl->length);
+	  break;
+	case 'L': // ljmp
+	  addr= rom->get(addr+1)*256 + rom->get(addr+2);
+	  break;
+	case 'r': // reljmp (2nd byte)
+	  analyze(rom->validate_address(addr+(signed char)(rom->get(addr+1))));
+	  analyze(addr+tabl->length);
+	  break;
+	case 'R': // reljmp (3rd byte)
+	  analyze(rom->validate_address(addr+(signed char)(rom->get(addr+2))));
+	  analyze(addr+tabl->length);
+	  break;
+	case 's': // sjmp
+	  {
+	    signed char target;
+	    target= rom->get(addr+1);
+	    addr+= 2;
+	    addr= rom->validate_address(addr+target);
+	    break;
+	  }
+	case '_':
+	  return;
+	default:
+	  addr= rom->validate_address(addr+tabl->length);
+	  break;
+	}
+      code= rom->get(addr);
+      tabl= &(dis_tbl()[code]);
+    }
+}
+
+
+/*
+ * Inform hardware elements that `cycles' machine cycles have elapsed
+ */
+
+/*int
+cl_51core::tick_hw(int cycles)
+{
+  cl_uc::tick_hw(cycles);
+  //do_hardware(cycles);
+  return(0);
+}*/
+
+/*int
+cl_51core::tick(int cycles)
+{
+  cl_uc::tick(cycles);
+  //do_hardware(cycles);
+  return(0);
+}*/
+
+
+/*
+ * Correcting direct address
+ *
+ * This function returns address of addressed element which can be an IRAM
+ * or an SFR.
+ */
+
+class cl_memory_cell *
+cl_51core::get_direct(t_mem addr)
+{
+  if (addr < sfr->start_address)
+    return(iram->get_cell(addr));
+  else
+    return(sfr->get_cell(addr));
+}
+
+
+/*
+ * Fetching one instruction and executing it
+ */
+
+
+int
+cl_51core::exec_inst(void)
+{
+  t_mem code;
+  int res= resGO;
+
+  if ((res= exec_inst_tab(itab51)) != resNOT_DONE)
+    return res;
+
+  instPC= PC;
+  if (fetch(&code))
+    return(resBREAKPOINT);
+  tick(1);
+  res= inst_unknown();
+  return(res);
+}
+
+
+/*
+ * Simulating execution of next instruction
+ *
+ * This is an endless loop if requested number of steps is negative.
+ * In this case execution is stopped if an instruction results other
+ * status than GO. Execution can be stopped if `cmd_in' is not NULL
+ * and there is input available on that file. It is usefull if the
+ * command console is on a terminal. If input is available then a
+ * complete line is read and dropped out because input is buffered
+ * (inp_avail will be TRUE if ENTER is pressed) and it can confuse
+ * command interepter.
+ */
+//static class cl_console *c= NULL;
+int
+cl_51core::do_inst(int step)
+{
+  result= resGO;
+  while ((result == resGO) &&
+	 (state != stPD) &&
+	 (step != 0))
+    {
+      if (step > 0)
+	step--;
+      if (state == stGO)
+	{
+	  interrupt->was_reti= false;
+	  pre_inst();
+	  result= exec_inst();
+	  post_inst();
+	}
+      else
+	{
+	  // tick hw in idle state
+	  inst_ticks= 1;
+	  post_inst();
+	  tick(1);
+	}
+      if (result == resGO)
+	{
+	  int res;
+	  if ((res= do_interrupt()) != resGO)
+	    result= res;
+	  else
+	    result= idle_pd();
+	}
+      if (((result == resINTERRUPT) &&
+	   stop_at_it) ||
+	  result >= resSTOP)
+	{
+	  sim->stop(result);
+	  break;
+	}
+    }
+  if (state == stPD)
+    {
+      //FIXME: tick outsiders eg. watchdog
+    }
+  return(result);
+}
+
+/*
+ * Abstract method to handle WDT
+ */
+
+/*int
+cl_51core::do_wdt(int cycles)
+{
+  return(resGO);
+}*/
+
+
+/*
+ * Checking for interrupt requests and accept one if needed
+ */
+
+int
+cl_51core::do_interrupt(void)
+{
+  int i, ie= 0;
+
+  if (interrupt->was_reti)
+    {
+      interrupt->was_reti= false;
+      return(resGO);
+    }
+  if (!((ie= sfr->get(IE)) & bmEA))
+    return(resGO);
+  class it_level *il= (class it_level *)(it_levels->top()), *IL= 0;
+  for (i= 0; i < it_sources->count; i++)
+    {
+      class cl_it_src *is= (class cl_it_src *)(it_sources->at(i));
+      if (is->is_active() &&
+	  is->enabled() &&
+	  is->pending())
+	{
+	  int pr= priority_of(is->ie_mask);
+	  if (il->level >= 0 &&
+	      pr <= il->level)
+	    continue;
+	  if (state == stIDLE)
+	    {
+	      state= stGO;
+	      sfr->set_bit0(PCON, bmIDL);
+	      interrupt->was_reti= true;
+	      return(resGO);
+	    }
+	  is->clear();
+	  sim->app->get_commander()->
+	    debug("%g sec (%d clks): Accepting interrupt `%s' PC= 0x%06x\n",
+			  get_rtime(), ticks->ticks, object_name(is), PC);
+	  IL= new it_level(pr, is->addr, PC, is);
+	  return(accept_it(IL));
+	}
+    }
+  return(resGO);
+}
+
+int
+cl_51core::priority_of(uchar nuof_it)
+{
+  if (sfr->get(IP) & /*ie_mask*/nuof_it)
+    return(1);
+  return(0);
+}
+
+
+/*
+ * Accept an interrupt
+ */
+
+int
+cl_51core::accept_it(class it_level *il)
+{
+  state= stGO;
+  sfr->set_bit0(PCON, bmIDL);
+  it_levels->push(il);
+  tick(1);
+  int res= inst_lcall(0, il->addr, true);
+  if (res != resGO)
+    return(res);
+  else
+    return(resINTERRUPT);
+}
+
+
+/* check if interrupts are enabled (globally)
+ */
+
+bool
+cl_51core::it_enabled(void)
+{
+  return sfr->get(IE) & bmEA;
+}
+
+
+/*
+ * Checking if Idle or PowerDown mode should be activated
+ */
+
+int
+cl_51core::idle_pd(void)
+{
+  uint pcon= sfr->get(PCON);
+
+  if (!(type->subtype & CPU_CMOS))
+    return(resGO);
+  if (pcon & bmIDL)
+    {
+      if (state != stIDLE)
+	sim->app->get_commander()->
+	  debug("%g sec (%d clks): CPU in Idle mode (PC=0x%x, PCON=0x%x)\n",
+		get_rtime(), ticks->ticks, PC, pcon);
+      state= stIDLE;
+      //was_reti= 1;
+    }
+  if (pcon & bmPD)
+    {
+      if (state != stPD)
+	sim->app->get_commander()->
+	  debug("%g sec (%d clks): CPU in PowerDown mode\n",
+			get_rtime(), ticks->ticks);
+      state= stPD;
+    }
+  return(resGO);
+}
+
+
+/*
+ * Simulating an unknown instruction
+ *
+ * Normally this function is called for unimplemented instructions, because
+ * every instruction must be known!
+ */
+
+int
+cl_51core::inst_unknown(void)
+{
+  //PC--;
+  class cl_error_unknown_code *e= new cl_error_unknown_code(this);
+  error(e);
+  return(resGO);
+}
+
+
+/*
+ * 0x00 1 12 NOP
+ */
+
+int
+cl_51core::instruction_00/*inst_nop*/(t_mem/*uchar*/ code)
+{
+  return(resGO);
+}
+
+
+/*
+ * 0xe4 1 12 CLR A
+ */
+
+int
+cl_51core::instruction_e4/*inst_clr_a*/(t_mem/*uchar*/ code)
+{
+  acc->write(0);
+  return(resGO);
+}
+
+
+/*
+ * 0xc4 1 1 SWAP A
+ */
+
+int
+cl_51core::instruction_c4/*inst_swap*/(t_mem/*uchar*/ code)
+{
+  uchar temp;
+
+  temp= (acc->read() >> 4) & 0x0f;
+  sfr->write(ACC, (acc->get() << 4) | temp);
+  return(resGO);
+}
+
+
+/*
+ */
+
+cl_uc51_cpu::cl_uc51_cpu(class cl_uc *auc):
+  cl_hw(auc, HW_CPU/*DUMMY*/, 0, "cpu")
+{
+}
+
+int
+cl_uc51_cpu::init(void)
+{
+  class cl_address_space *sfr= uc->address_space(MEM_SFR_ID),
+    *bas= uc->address_space("bits");
+  int i;
+  cl_hw::init();
+  if (!sfr)
+    {
+      fprintf(stderr, "No SFR to register %s[%d] into\n", id_string, id);
+    }
+  cell_psw= sfr->get_cell(PSW);//use_cell(sfr, PSW);
+  cell_acc= register_cell(sfr, ACC);
+  cell_sp= register_cell(sfr, SP);
+  for (i= 0; i < 8; i++)
+    acc_bits[i]= register_cell(bas, ACC+i);
+
+  cl_var *v;
+  uc->vars->add(v= new cl_var(cchars("cpu_aof_mdps"), cfg, uc51cpu_aof_mdps,
+			      cfg_help(uc51cpu_aof_mdps)));
+  v->init();
+  uc->vars->add(v= new cl_var(cchars("cpu_mask_mdps"), cfg, uc51cpu_mask_mdps,
+			      cfg_help(uc51cpu_mask_mdps)));
+  v->init();
+  uc->vars->add(v= new cl_var(cchars("cpu_aof_mdps1l"), cfg, uc51cpu_aof_mdps1l,
+			      cfg_help(uc51cpu_aof_mdps1l)));
+  v->init();
+  uc->vars->add(v= new cl_var(cchars("cpu_aof_mdps1h"), cfg, uc51cpu_aof_mdps1h,
+			      cfg_help(uc51cpu_aof_mdps1h)));
+  v->init();
+  uc->vars->add(v= new cl_var(cchars("cpu_aof_mdpc"), cfg, uc51cpu_aof_mdpc,
+			      cfg_help(uc51cpu_aof_mdpc)));
+  v->init();
+  uc->vars->add(v= new cl_var(cchars("cpu_mask_mdpc"), cfg, uc51cpu_mask_mdpc,
+			      cfg_help(uc51cpu_mask_mdpc)));
+  v->init();
+  
+  return(0);
+}
+
+char *
+cl_uc51_cpu::cfg_help(t_addr addr)
+{
+  switch (addr)
+    {
+    case uc51cpu_aof_mdps:
+      return (char*)"Address of multi_DPTR_sfr selector, WR selects this style of multi_DPTR (int, RW)";
+    case uc51cpu_mask_mdps:
+      return (char*)"Mask in multi_DPTR_srf selector (int, RW)";
+    case uc51cpu_aof_mdps1l:
+      return (char*)"Address of multi_DPTR_sfr DPL1 (int, RW)";
+    case uc51cpu_aof_mdps1h:
+      return (char*)"Address of multi_DPTR_sfr DPH1 (int, RW)";
+    case uc51cpu_aof_mdpc:
+      return (char*)"Address of multi_DPTR_chip selector, WR selects this stlye of multi_DPTR (int, RW)";
+    case uc51cpu_mask_mdpc:
+      return (char*)"Mask in multi_DPTR_chip selector (int, RW)";
+    }
+  return (char*)"Not used";
+}
+
+void
+cl_uc51_cpu::write(class cl_memory_cell *cell, t_mem *val)
+{
+  if (conf(cell, val))
+    return;
+  if (cell == cell_sp)
+    {
+      if (*val > uc->sp_max)
+	uc->sp_max= *val;
+      uc->sp_avg= (uc->sp_avg+(*val))/2;
+    }
+  else 
+    {
+      bool p;
+      int i;
+      uchar uc, n= *val;
+
+      if (cell != cell_acc)
+	{
+	  cell->set(*val);
+	  n= cell_acc->get();
+	}
+      p = false;
+      uc= n;
+      for (i= 0; i < 8; i++)
+	{
+	  if (uc & 1)
+	    p= !p;
+	  uc>>= 1;
+	}
+      if (p)
+	cell_psw->set_bit1(bmP);
+      else
+	cell_psw->set_bit0(bmP);
+    }
+  /*else if (cell == cell_pcon)
+    {
+      printf("PCON write 0x%x (PC=0x%x)\n", *val, uc->PC);
+      uc->sim->stop(0);
+      }*/
+}
+
+t_mem
+cl_uc51_cpu::conf_op(cl_memory_cell *cell, t_addr addr, t_mem *val)
+{
+  if (val)
+    cell->set(*val);
+  switch ((enum uc51cpu_cfg)addr)
+    {
+    case uc51cpu_aof_mdps: // addr of multi_DPTR_sfr selector
+      if (val)
+	((cl_51core *)uc)->decode_dptr();
+      break;
+    case uc51cpu_mask_mdps: // mask in mutli_DPTR_sfr selector
+      break;
+    case uc51cpu_aof_mdps1l: // addr of multi_DPTR_sfr DPL1
+      break;
+    case uc51cpu_aof_mdps1h: // addr of multi_DPTR_sfr DPH1
+      break;
+
+    case uc51cpu_aof_mdpc: // addr of multi_DPTR_chip selector
+      if (val)
+	((cl_51core *)uc)->decode_dptr();
+      break;
+    case uc51cpu_mask_mdpc: // mask in multi_DPTR_chip selector
+      break;
+  
+    case uc51cpu_nuof:
+      break;
+    }
+  return cell->get();
+}
+
+/* End of s51.src/uc51.cc */
diff --git a/sim/ucsim/s51.src/uc517.cc b/sim/ucsim/s51.src/uc517.cc
new file mode 100644
index 0000000..97221b8
--- /dev/null
+++ b/sim/ucsim/s51.src/uc517.cc
@@ -0,0 +1,65 @@
+/*
+ * Simulator of microcontrollers (s51.src/uc517.cc)
+ *
+ * Copyright (C) 2017,17 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#include "mducl.h"
+
+#include "uc517cl.h"
+
+
+cl_uc517::cl_uc517(struct cpu_entry *Itype, class cl_sim *asim):
+  cl_uc52(Itype, asim)
+{
+}
+
+int
+cl_uc517::init(void)
+{
+  int ret;
+  ret= cl_uc52::init();
+
+  cpu->cfg_set(uc51cpu_aof_mdpc, 0x92);
+  cpu->cfg_set(uc51cpu_mask_mdpc, 7);
+  class cl_memory_chip *dptr_chip=
+    new cl_memory_chip("dptr_chip", 3*8, 8);
+  dptr_chip->init();
+  memchips->add(dptr_chip);
+  decode_dptr();
+
+  return ret;
+}
+
+void
+cl_uc517::mk_hw_elements(void)
+{
+  cl_uc52::mk_hw_elements();
+
+  class cl_mdu517 *mdu= new cl_mdu517(this, 0);
+  add_hw(mdu);
+  mdu->init();
+}
+
+/* End of s51.src/uc517.cc */
diff --git a/sim/ucsim/s51.src/uc517cl.h b/sim/ucsim/s51.src/uc517cl.h
new file mode 100644
index 0000000..b39ff1b
--- /dev/null
+++ b/sim/ucsim/s51.src/uc517cl.h
@@ -0,0 +1,44 @@
+/*
+ * Simulator of microcontrollers (s51.src/uc517cl.h)
+ *
+ * Copyright (C) 2017,17 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#ifndef UC517CL_HEADER
+#define UC517CL_HEADER
+
+#include "uc52cl.h"
+
+class cl_uc517: public cl_uc52
+{
+ public:
+  cl_uc517(struct cpu_entry *Itype, class cl_sim *asim);
+  virtual int init(void);
+  virtual void mk_hw_elements(void);
+};
+
+
+#endif
+
+/* End of s51.src/uc517cl.h */
diff --git a/sim/ucsim/s51.src/uc51cl.h b/sim/ucsim/s51.src/uc51cl.h
new file mode 100644
index 0000000..4cc38af
--- /dev/null
+++ b/sim/ucsim/s51.src/uc51cl.h
@@ -0,0 +1,290 @@
+/*
+ * Simulator of microcontrollers (uc51cl.h)
+ *
+ * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
+ *
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/*
+  This file is part of microcontroller simulator: ucsim.
+
+  UCSIM is free software; you can redistribute it and/or modify
+  it under the terms of the GNU General Public License as published by
+  the Free Software Foundation; either version 2 of the License, or
+  (at your option) any later version.
+
+  UCSIM is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+  GNU General Public License for more details.
+
+  You should have received a copy of the GNU General Public License
+  along with UCSIM; see the file COPYING.  If not, write to the Free
+  Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+  02111-1307, USA.
+*/
+/*@1@*/
+
+#ifndef UC51CL_HEADER
+#define UC51CL_HEADER
+
+#include <stdio.h>
+#ifdef HAVE_TERMIOS_H
+#include <termios.h>
+#endif
+
+#include "pobjcl.h"
+
+#include "simcl.h"
+#include "memcl.h"
+#include "uccl.h"
+#include "itsrccl.h"
+#include "brkcl.h"
+#include "stypes.h"
+
+#include "interruptcl.h"
+
+
+class t_uc51;
+
+class cl_irq_stop_option: public cl_optref
+{
+protected:
+  class cl_51core *uc51;
+public:
+  cl_irq_stop_option(class cl_51core *the_uc51);
+  virtual int init(void);
+  virtual void option_changed(void);
+};
+
+class cl_51core: public cl_uc
+{
+public:
+  // Options
+  //bool debug;
+  class cl_irq_stop_option *irq_stop_option;
+  bool stop_at_it;
+
+  // memories and cells for faster access
+  class cl_address_space *sfr, *iram, *xram, *regs, *bits;
+  class cl_address_space *dptr;
+  class cl_memory_cell *acc, *psw, *R[8];
+  class cl_memory_chip *rom_chip, *sfr_chip, *iram_chip, *xram_chip;
+  
+public:
+  // Help to detect external it requests (falling edge)
+  uchar prev_p1;	// Prev state of P1
+  uchar prev_p3;	// Prev state of P3
+  int p3_int0_edge, p3_int1_edge;
+
+public:
+  // Simulation of interrupt system
+  class cl_interrupt *interrupt;
+  //bool  was_reti;	// Instruction had an effect on IE
+
+public:
+  int result;		// result of instruction execution
+
+  cl_51core(struct cpu_entry *Itype, class cl_sim *asim);
+  virtual ~cl_51core(void);
+  virtual int    init(void);
+  virtual char  *id_string(void);
+  virtual void make_cpu_hw(void);
+  virtual void mk_hw_elements(void);
+  virtual void build_cmdset(class cl_cmdset *cmdset);
+  //virtual class cl_m *mk_mem(enum mem_class type, char *class_name);
+  virtual void make_memories(void);
+  virtual void make_address_spaces(void);
+  virtual void make_chips(void);
+  virtual void decode_regs(void);
+  virtual void decode_bits(void);
+  virtual void decode_rom(void);
+  virtual void decode_iram(void);
+  virtual void decode_sfr(void);
+  virtual void decode_xram(void);
+  virtual void decode_dptr(void);
+  virtual void make_vars(void);
+  
+  virtual int clock_per_cycle(void) { return(12); }
+  virtual struct dis_entry *dis_tbl(void);
+  virtual struct name_entry *bit_tbl(void);
+  virtual char *disass(t_addr addr, const char *sep);
+  virtual void   print_regs(class cl_console_base *con);
+  virtual class cl_address_space *bit2mem(t_addr bitaddr,
+					  t_addr *memaddr, t_mem *bitmask);
+  virtual t_addr bit_address(class cl_memory *mem,
+			     t_addr mem_address,
+			     int bit_number);
+  virtual void   daddr_name(t_addr addr, char *buf);
+  virtual void   baddr_name(t_addr addr, char *buf);
+  
+  virtual void   reset(void);
+  virtual void   clear_sfr(void);
+  virtual void   analyze(t_addr addr);
+
+  virtual int    do_inst(int step);
+
+  //virtual void mem_cell_changed(class cl_m *mem, t_addr addr);
+
+  virtual int  priority_of(uchar nuof_it);
+  virtual int  do_interrupt(void);
+  virtual int  accept_it(class it_level *il);
+  virtual bool it_enabled(void);
+  
+protected:
+  virtual int  idle_pd(void);
+
+  virtual class cl_memory_cell *get_direct(t_mem addr);
+
+  virtual int   exec_inst(void);
+  //virtual void  post_inst(void);
+
+  virtual int inst_unknown(void);
+  virtual int instruction_00/*inst_nop*/(t_mem/*uchar*/ code);		/* 00 */
+  virtual int instruction_01/*inst_ajmp_addr*/(t_mem/*uchar*/ code);	/* [02468ace]1 */
+  virtual int instruction_02/*inst_ljmp*/(t_mem/*uchar*/ code);		/* 02 */
+  virtual int instruction_03/*inst_rr*/(t_mem/*uchar*/ code);		/* 03 */
+  virtual int instruction_04/*inst_inc_a*/(t_mem/*uchar*/ code);	/* 04 */
+  virtual int instruction_05/*inst_inc_addr*/(t_mem/*uchar*/ code);	/* 05 */
+  virtual int instruction_06/*inst_inc_Sri*/(t_mem/*uchar*/ code);	/* 06,07 */
+  virtual int instruction_08/*inst_inc_rn*/(t_mem/*uchar*/ code);	/* 08-0f */
+  virtual int instruction_10/*inst_jbc_bit_addr*/(t_mem/*uchar*/ code);	/* 10 */
+  virtual int instruction_11/*inst_acall_addr*/(t_mem/*uchar*/ code);	/* [13579bdf]1 */
+  virtual int inst_lcall(t_mem code, uint addr, bool intr);		/* 12 */
+  virtual int instruction_12(t_mem code) { return inst_lcall(code, 0, false); }
+  virtual int instruction_13/*inst_rrc*/(t_mem/*uchar*/ code);		/* 13 */
+  virtual int instruction_14/*inst_dec_a*/(t_mem/*uchar*/ code);	/* 14 */
+  virtual int instruction_15/*inst_dec_addr*/(t_mem/*uchar*/ code);	/* 15 */
+  virtual int instruction_16/*inst_dec_Sri*/(t_mem/*uchar*/ code);	/* 16,17 */
+  virtual int instruction_18/*inst_dec_rn*/(t_mem/*uchar*/ code);	/* 18-1f */
+  virtual int instruction_20/*inst_jb_bit_addr*/(t_mem/*uchar*/ code);	/* 20 */
+  virtual int instruction_22/*inst_ret*/(t_mem/*uchar*/ code);		/* 22 */
+  virtual int instruction_23/*inst_rl*/(t_mem/*uchar*/ code);		/* 23 */
+  virtual int instruction_24/*inst_add_a_Sdata*/(t_mem/*uchar*/ code);	/* 24 */
+  virtual int instruction_25/*inst_add_a_addr*/(t_mem/*uchar*/ code);	/* 25 */
+  virtual int instruction_26/*inst_add_a_Sri*/(t_mem/*uchar*/ code);	/* 26,27 */
+  virtual int instruction_28/*inst_add_a_rn*/(t_mem/*uchar*/ code);	/* 28-2f */
+  virtual int instruction_30/*inst_jnb_bit_addr*/(t_mem/*uchar*/ code);	/* 30 */
+  virtual int instruction_32/*inst_reti*/(t_mem/*uchar*/ code);		/* 32 */
+  virtual int instruction_33/*inst_rlc*/(t_mem/*uchar*/ code);		/* 33 */
+  virtual int instruction_34/*inst_addc_a_Sdata*/(t_mem/*uchar*/ code);	/* 34 */
+  virtual int instruction_35/*inst_addc_a_addr*/(t_mem/*uchar*/ code);	/* 35 */
+  virtual int instruction_36/*inst_addc_a_Sri*/(t_mem/*uchar*/ code);	/* 36,37 */
+  virtual int instruction_38/*inst_addc_a_rn*/(t_mem/*uchar*/ code);	/* 38-3f */
+  virtual int instruction_40/*inst_jc_addr*/(t_mem/*uchar*/ code);	/* 40 */
+  virtual int instruction_42/*inst_orl_addr_a*/(t_mem/*uchar*/ code);	/* 42 */
+  virtual int instruction_43/*inst_orl_addr_Sdata*/(t_mem/*uchar*/ code);/* 43 */
+  virtual int instruction_44/*inst_orl_a_Sdata*/(t_mem/*uchar*/ code);	/* 44 */
+  virtual int instruction_45/*inst_orl_a_addr*/(t_mem/*uchar*/ code);	/* 45 */
+  virtual int instruction_46/*inst_orl_a_Sri*/(t_mem/*uchar*/ code);	/* 46,47 */
+  virtual int instruction_48/*inst_orl_a_rn*/(t_mem/*uchar*/ code);	/* 48-4f */
+  virtual int instruction_50/*inst_jnc_addr*/(t_mem/*uchar*/ code);	/* 50 */
+  virtual int instruction_52/*inst_anl_addr_a*/(t_mem/*uchar*/ code);	/* 52 */
+  virtual int instruction_53/*inst_anl_addr_Sdata*/(t_mem/*uchar*/ code);/* 53 */
+  virtual int instruction_54/*inst_anl_a_Sdata*/(t_mem/*uchar*/ code);	/* 54 */
+  virtual int instruction_55/*inst_anl_a_addr*/(t_mem/*uchar*/ code);	/* 55 */
+  virtual int instruction_56/*inst_anl_a_Sri*/(t_mem/*uchar*/ code);	/* 56,57 */
+  virtual int instruction_58/*inst_anl_a_rn*/(t_mem/*uchar*/ code);	/* 58-5f */
+  virtual int instruction_60/*inst_jz_addr*/(t_mem/*uchar*/ code);	/* 60 */
+  virtual int instruction_62/*inst_xrl_addr_a*/(t_mem/*uchar*/ code);	/* 62 */
+  virtual int instruction_63/*inst_xrl_addr_Sdata*/(t_mem/*uchar*/ code);/* 63 */
+  virtual int instruction_64/*inst_xrl_a_Sdata*/(t_mem/*uchar*/ code);	/* 64 */
+  virtual int instruction_65/*inst_xrl_a_addr*/(t_mem/*uchar*/ code);	/* 65 */
+  virtual int instruction_66/*inst_xrl_a_Sri*/(t_mem/*uchar*/ code);	/* 66,67 */
+  virtual int instruction_68/*inst_xrl_a_rn*/(t_mem/*uchar*/ code);	/* 68-6f */
+  virtual int instruction_70/*inst_jnz_addr*/(t_mem/*uchar*/ code);	/* 70 */
+  virtual int instruction_72/*inst_orl_c_bit*/(t_mem/*uchar*/ code);	/* 72 */
+  virtual int instruction_73/*inst_jmp_Sa_dptr*/(t_mem/*uchar*/ code);	/* 73 */
+  virtual int instruction_74/*inst_mov_a_Sdata*/(t_mem/*uchar*/ code);	/* 74 */
+  virtual int instruction_75/*inst_mov_addr_Sdata*/(t_mem/*uchar*/ code);/* 75 */
+  virtual int instruction_76/*inst_mov_Sri_Sdata*/(t_mem/*uchar*/ code);/* 76,77 */
+  virtual int instruction_78/*inst_mov_rn_Sdata*/(t_mem/*uchar*/ code);	/* 78-7f */
+  virtual int instruction_80/*inst_sjmp*/(t_mem/*uchar*/ code);		/* 80 */
+  virtual int instruction_82/*inst_anl_c_bit*/(t_mem/*uchar*/ code);	/* 82 */
+  virtual int instruction_83/*inst_movc_a_Sa_pc*/(t_mem/*uchar*/ code);	/* 83 */
+  virtual int instruction_84/*inst_div_ab*/(t_mem/*uchar*/ code);	/* 84 */
+  virtual int instruction_85/*inst_mov_addr_addr*/(t_mem/*uchar*/ code);/* 85 */
+  virtual int instruction_86/*inst_mov_addr_Sri*/(t_mem/*uchar*/ code);	/* 86,87 */
+  virtual int instruction_88/*inst_mov_addr_rn*/(t_mem/*uchar*/ code);	/* 88-8f */
+  virtual int instruction_90/*inst_mov_dptr_Sdata*/(t_mem/*uchar*/ code);/* 90 */
+  virtual int instruction_92/*inst_mov_bit_c*/(t_mem/*uchar*/ code);	/* 92 */
+  virtual int instruction_93/*inst_movc_a_Sa_dptr*/(t_mem/*uchar*/ code);/* 93 */
+  virtual int instruction_94/*inst_subb_a_Sdata*/(t_mem/*uchar*/ code);	/* 94 */
+  virtual int instruction_95/*inst_subb_a_addr*/(t_mem/*uchar*/ code);	/* 95 */
+  virtual int instruction_96/*inst_subb_a_Sri*/(t_mem/*uchar*/ code);	/* 96,97 */
+  virtual int instruction_98/*inst_subb_a_rn*/(t_mem/*uchar*/ code);	/* 98-9f */
+  virtual int instruction_a0/*inst_orl_c_Sbit*/(t_mem/*uchar*/ code);	/* a0 */
+  virtual int instruction_a2/*inst_mov_c_bit*/(t_mem/*uchar*/ code);	/* a2 */
+  virtual int instruction_a3/*inst_inc_dptr*/(t_mem/*uchar*/ code);	/* a3 */
+  virtual int instruction_a4/*inst_mul_ab*/(t_mem/*uchar*/ code);	/* a4 */
+  virtual int instruction_a6/*inst_mov_Sri_addr*/(t_mem/*uchar*/ code);	/* a6,a7 */
+  virtual int instruction_a8/*inst_mov_rn_addr*/(t_mem/*uchar*/ code);	/* a8-af */
+  virtual int instruction_b0/*inst_anl_c_Sbit*/(t_mem/*uchar*/ code);	/* b0 */
+  virtual int instruction_b2/*inst_cpl_bit*/(t_mem/*uchar*/ code);	/* b2 */
+  virtual int instruction_b3/*inst_cpl_c*/(t_mem/*uchar*/ code);	/* b3 */
+  virtual int instruction_b4/*inst_cjne_a_Sdata_addr*/(t_mem/*uchar*/ code);/* b4 */
+  virtual int instruction_b5/*inst_cjne_a_addr_addr*/(t_mem/*uchar*/ code);/* b5 */
+  virtual int instruction_b6/*inst_cjne_Sri_Sdata_addr*/(t_mem/*uchar*/ code);/* b6,b7 */
+  virtual int instruction_b8/*inst_cjne_rn_Sdata_addr*/(t_mem/*uchar*/ code);/* b8-bf */
+  virtual int instruction_c0/*inst_push*/(t_mem/*uchar*/ code);		/* c0 */
+  virtual int instruction_c2/*inst_clr_bit*/(t_mem/*uchar*/ code);	/* c2 */
+  virtual int instruction_c3/*inst_clr_c*/(t_mem/*uchar*/ code);	/* c3*/
+  virtual int instruction_c4/*inst_swap*/(t_mem/*uchar*/ code);		/* c4 */
+  virtual int instruction_c5/*inst_xch_a_addr*/(t_mem/*uchar*/ code);	/* c5 */
+  virtual int instruction_c6/*inst_xch_a_Sri*/(t_mem/*uchar*/ code);	/* c6,c7 */
+  virtual int instruction_c8/*inst_xch_a_rn*/(t_mem/*uchar*/ code);	/* c8-cf */
+  virtual int instruction_d0/*inst_pop*/(t_mem/*uchar*/ code);		/* d0 */
+  virtual int instruction_d2/*inst_setb_bit*/(t_mem/*uchar*/ code);	/* d2 */
+  virtual int instruction_d3/*inst_setb_c*/(t_mem/*uchar*/ code);	/* d3 */
+  virtual int instruction_d4/*inst_da_a*/(t_mem/*uchar*/ code);		/* d4 */
+  virtual int instruction_d5/*inst_djnz_addr_addr*/(t_mem/*uchar*/ code);/* d5 */
+  virtual int instruction_d6/*inst_xchd_a_Sri*/(t_mem/*uchar*/ code);	/* d6,d7 */
+  virtual int instruction_d8/*inst_djnz_rn_addr*/(t_mem/*uchar*/ code);	/* d8-df */
+  virtual int instruction_e0/*inst_movx_a_Sdptr*/(t_mem/*uchar*/ code);	/* e0 */
+  virtual int instruction_e2/*inst_movx_a_Sri*/(t_mem/*uchar*/ code);	/* e2,e3 */
+  virtual int instruction_e4/*inst_clr_a*/(t_mem/*uchar*/ code);	/* e4 */
+  virtual int instruction_e5/*inst_mov_a_addr*/(t_mem/*uchar*/ code);	/* e5 */
+  virtual int instruction_e6/*inst_mov_a_Sri*/(t_mem/*uchar*/ code);	/* e6,e7 */
+  virtual int instruction_e8/*inst_mov_a_rn*/(t_mem/*uchar*/ code);	/* e8-ef */
+  virtual int instruction_f0/*inst_movx_Sdptr_a*/(t_mem/*uchar*/ code);	/* f0 */
+  virtual int instruction_f2/*inst_movx_Sri_a*/(t_mem/*uchar*/ code);	/* f2,f3 */
+  virtual int instruction_f4/*inst_cpl_a*/(t_mem/*uchar*/ code);	/* f4 */
+  virtual int instruction_f5/*inst_mov_addr_a*/(t_mem/*uchar*/ code);	/* f5 */
+  virtual int instruction_f6/*inst_mov_Sri_a*/(t_mem/*uchar*/ code);	/* f6,f7 */
+  virtual int instruction_f8/*inst_mov_rn_a*/(t_mem/*uchar*/ code);	/* f8-ff */
+};
+
+
+enum uc51cpu_cfg {
+  uc51cpu_aof_mdps	= 0, // addr of multi_DPTR_sfr selector
+  uc51cpu_mask_mdps	= 1, // mask in mutli_DPTR_sfr selector
+  uc51cpu_aof_mdps1l	= 2, // addr of multi_DPTR_sfr DPL1
+  uc51cpu_aof_mdps1h	= 3, // addr of multi_DPTR_sfr DPH1
+
+  uc51cpu_aof_mdpc	= 4, // addr of multi_DPTR_chip selector
+  uc51cpu_mask_mdpc	= 5, // mask in multi_DPTR_chip selector
+  
+  uc51cpu_nuof		= 16
+};
+
+class cl_uc51_cpu: public cl_hw
+{
+ protected:
+  class cl_memory_cell *cell_acc, *cell_sp, *cell_psw;
+  class cl_memory_cell *acc_bits[8];
+ public:
+  cl_uc51_cpu(class cl_uc *auc);
+  virtual int init(void);
+  virtual int cfg_size(void) { return uc51cpu_nuof; }
+  virtual char *cfg_help(t_addr addr);
+  
+  virtual void write(class cl_memory_cell *cell, t_mem *val);
+  virtual t_mem conf_op(cl_memory_cell *cell, t_addr addr, t_mem *val);
+};
+
+
+#endif
+
+/* End of s51.src/uc51cl.h */
diff --git a/sim/ucsim/s51.src/uc51r.cc b/sim/ucsim/s51.src/uc51r.cc
new file mode 100644
index 0000000..9a763b2
--- /dev/null
+++ b/sim/ucsim/s51.src/uc51r.cc
@@ -0,0 +1,146 @@
+/*
+ * Simulator of microcontrollers (uc51r.cc)
+ *
+ * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#include "ddconfig.h"
+
+#include <stdio.h>
+
+// local
+#include "uc51rcl.h"
+#include "regs51.h"
+#include "types51.h"
+#include "wdtcl.h"
+
+
+/*
+ * Making an 8051r CPU object
+ */
+
+cl_uc51r::cl_uc51r(struct cpu_entry *Itype, class cl_sim *asim):
+  cl_uc52(Itype, asim)
+{
+  /*  int i;
+  for (i= 0; i < ERAM_SIZE; i++)
+  ERAM[i]= 0;*/
+  clock_out= 0;
+}
+
+
+void
+cl_uc51r::mk_hw_elements(void)
+{
+  class cl_hw *h;
+
+  cl_uc52::mk_hw_elements();
+  add_hw(h= new cl_wdt(this, 0x3fff));
+  h->init();
+}
+
+
+void
+cl_uc51r::make_memories(void)
+{
+  cl_uc52::make_memories();
+}
+
+void
+cl_uc51r::make_chips(void)
+{
+  cl_uc52::make_chips();
+  
+  eram_chip= new cl_memory_chip("eram_chip", 0x100, 8);
+  eram_chip->init();
+  memchips->add(eram_chip);
+}
+
+void
+cl_uc51r::decode_xram(void)
+{
+  class cl_address_decoder *ad;
+  class cl_banker *b;
+
+  ad= new cl_address_decoder(xram, xram_chip, 0x100, 0xffff, 0x100);
+  ad->init();
+  xram->decoders->add(ad);
+  ad->activate(0);
+  
+  b= new cl_banker(sfr, AUXR, 0x02, //0,
+		   xram, 0, 0xff);
+  b->init();
+  xram->decoders->add(b);
+  b->add_bank(0, eram_chip, 0);
+  b->add_bank(1, xram_chip, 0);
+}
+
+/*
+ * Resetting of the microcontroller
+ *
+ * Original method is extended with handling of WDT.
+ */
+
+void
+cl_uc51r::reset(void)
+{
+  cl_uc52::reset();
+  sfr->write(SADDR, 0);
+  sfr->write(SADEN, 0);
+  sfr->write(AUXR, 0);
+}
+
+void
+cl_uc51r::clear_sfr(void)
+{
+  cl_uc52::clear_sfr();
+  sfr->write(SADDR, 0);
+  sfr->write(SADEN, 0);
+  sfr->write(AUXR, 0);
+  sfr->write(IPH, 0);
+}
+
+
+void
+cl_uc51r::received(int c)
+{
+  t_mem br= sfr->get(SADDR) | sfr->get(SADEN);
+  int scon= sfr->get(SCON);
+
+  if ((0 < scon >> 6) &&
+      (scon & bmSM2))
+    {
+      if (/* Check for individual address */
+	  ((sfr->get(SADDR) & sfr->get(SADEN)) == (c & sfr->get(SADEN)))
+	  ||
+	  /* Check for broadcast address */
+	  (br == (br & c)))
+	sfr->set_bit1(SCON, bmRI);
+      return;
+    }
+  sfr->set_bit1(SCON, bmRI);
+}
+
+
+/* End of s51.src/uc51r.cc */
diff --git a/sim/ucsim/s51.src/uc51rcl.h b/sim/ucsim/s51.src/uc51rcl.h
new file mode 100644
index 0000000..f7e4fcd
--- /dev/null
+++ b/sim/ucsim/s51.src/uc51rcl.h
@@ -0,0 +1,59 @@
+/*
+ * Simulator of microcontrollers (uc51rcl.h)
+ *
+ * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#ifndef UC51RCL_HEADER
+#define UC51RCL_HEADER
+
+#include "ddconfig.h"
+
+#include "uc52cl.h"
+#include "itsrccl.h"
+
+
+class cl_uc51r: public cl_uc52
+{
+public:
+  int   clock_out;
+  class cl_memory_chip *eram_chip;
+  
+public:
+  cl_uc51r(struct cpu_entry *Itype, class cl_sim *asim);
+  virtual void mk_hw_elements(void);
+  virtual void make_memories(void);
+  virtual void make_chips(void);
+  virtual void decode_xram(void);
+  
+  virtual void reset(void);
+  virtual void clear_sfr(void);
+
+  virtual void received(int c);
+};
+
+
+#endif
+
+/* End of s51.src/uc52cl.h */
diff --git a/sim/ucsim/s51.src/uc52.cc b/sim/ucsim/s51.src/uc52.cc
new file mode 100644
index 0000000..c81524b
--- /dev/null
+++ b/sim/ucsim/s51.src/uc52.cc
@@ -0,0 +1,137 @@
+/*
+ * Simulator of microcontrollers (uc52.cc)
+ *
+ * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#include "ddconfig.h"
+
+#include <stdio.h>
+
+// local
+#include "uc52cl.h"
+#include "regs51.h"
+#include "timer2cl.h"
+#include "portcl.h"
+#include "mducl.h"
+
+
+/*
+ * Making an 8052 CPU object
+ */
+
+cl_uc52::cl_uc52(struct cpu_entry *Itype, class cl_sim *asim):
+  cl_51core(Itype, asim)
+{
+}
+
+int
+cl_uc52::init(void)
+{
+  int ret;
+  ret= cl_51core::init();
+
+  return ret;
+}
+
+void
+cl_uc52::mk_hw_elements(void)
+{
+  class cl_hw *h;
+
+  cl_51core::mk_hw_elements();
+  add_hw(h= new cl_timer2(this, 2, "timer2", t2_default|t2_down));
+  h->init();
+}
+
+void
+cl_uc52::make_memories(void)
+{
+  cl_51core::make_memories();
+}
+
+void
+cl_uc52::make_address_spaces(void)
+{
+  rom= new cl_address_space("rom", 0, 0x10000, 8);
+  rom->init();
+  address_spaces->add(rom);
+  
+  iram= new cl_address_space("iram", 0, 0x100, 8);
+  iram->init();
+  address_spaces->add(iram);
+
+  sfr= new cl_address_space("sfr", 0x80, 0x80, 8);
+  sfr->init();
+  address_spaces->add(sfr);
+
+  xram= new cl_address_space("xram", 0, 0x10000, 8);
+  xram->init();
+  address_spaces->add(xram);
+
+  regs= new cl_address_space("regs", 0, 8, 8);
+  regs->init();
+  address_spaces->add(regs);
+
+  bits= new cl_address_space("bits", 0, 0x100, 1);
+  bits->init();
+  address_spaces->add(bits);
+
+  dptr= new cl_address_space("dptr", 0, 2, 8);
+  dptr->init();
+  address_spaces->add(dptr);
+}
+
+
+void
+cl_uc52::decode_iram(void)
+{
+  class cl_address_decoder *ad;
+  
+  ad= new cl_address_decoder(iram, iram_chip, 0, 0xff, 0);
+  ad->init();
+  iram->decoders->add(ad);
+  ad->activate(0);
+
+}
+
+void
+cl_uc52::decode_dptr(void)
+{
+  cl_51core::decode_dptr();
+}
+
+void
+cl_uc52::clear_sfr(void)
+{
+  cl_51core::clear_sfr();
+  sfr->write(T2CON, 0);
+  sfr->write(TH2, 0);
+  sfr->write(TL2, 0);
+  sfr->write(RCAP2L, 0);
+  sfr->write(RCAP2H, 0);
+}
+
+
+/* End of s51.src/uc52.cc */
diff --git a/sim/ucsim/s51.src/uc521.cc b/sim/ucsim/s51.src/uc521.cc
new file mode 100644
index 0000000..85e9770
--- /dev/null
+++ b/sim/ucsim/s51.src/uc521.cc
@@ -0,0 +1,52 @@
+/*
+ * Simulator of microcontrollers (s51.src/uc521.cc)
+ *
+ * Copyright (C) 2017,17 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#include "uc521cl.h"
+
+
+cl_uc521::cl_uc521(struct cpu_entry *Itype, class cl_sim *asim):
+  cl_uc52(Itype, asim)
+{
+}
+
+int
+cl_uc521::init(void)
+{
+  int ret;
+  ret= cl_uc52::init();
+
+  cpu->cfg_set(uc51cpu_aof_mdps, 0x86);
+  cpu->cfg_set(uc51cpu_mask_mdps, 1);
+  cpu->cfg_set(uc51cpu_aof_mdps1l, 0x84);
+  cpu->cfg_set(uc51cpu_aof_mdps1h, 0x85);
+  decode_dptr();
+
+  return ret;
+}
+
+
+/* End of s51.src/uc521.cc */
diff --git a/sim/ucsim/s51.src/uc521cl.h b/sim/ucsim/s51.src/uc521cl.h
new file mode 100644
index 0000000..8e5ac3e
--- /dev/null
+++ b/sim/ucsim/s51.src/uc521cl.h
@@ -0,0 +1,43 @@
+/*
+ * Simulator of microcontrollers (s51.src/uc521cl.h)
+ *
+ * Copyright (C) 2017,17 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#ifndef UC521CL_HEADER
+#define UC521CL_HEADER
+
+#include "uc52cl.h"
+
+class cl_uc521: public cl_uc52
+{
+ public:
+  cl_uc521(struct cpu_entry *Itype, class cl_sim *asim);
+  virtual int init(void);
+};
+
+
+#endif
+
+/* End of s51.src/uc521cl.h */
diff --git a/sim/ucsim/s51.src/uc52cl.h b/sim/ucsim/s51.src/uc52cl.h
new file mode 100644
index 0000000..e69bf2d
--- /dev/null
+++ b/sim/ucsim/s51.src/uc52cl.h
@@ -0,0 +1,54 @@
+/*
+ * Simulator of microcontrollers (uc52cl.h)
+ *
+ * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#ifndef UC52CL_HEADER
+#define UC52CL_HEADER
+
+#include "ddconfig.h"
+
+#include "uc51cl.h"
+#include "itsrccl.h"
+
+
+class cl_uc52: public cl_51core
+{
+public:
+  cl_uc52(struct cpu_entry *Itype, class cl_sim *asim);
+  virtual int init(void);
+  virtual void mk_hw_elements(void);
+  virtual void make_memories(void);
+  virtual void make_address_spaces(void);
+  virtual void decode_iram(void);
+  virtual void decode_dptr(void);
+  
+  virtual void clear_sfr(void);
+};
+
+
+#endif
+
+/* End of s51.src/uc52cl.h */
diff --git a/sim/ucsim/s51.src/uc88x.cc b/sim/ucsim/s51.src/uc88x.cc
new file mode 100644
index 0000000..3f79e08
--- /dev/null
+++ b/sim/ucsim/s51.src/uc88x.cc
@@ -0,0 +1,66 @@
+/*
+ * Simulator of microcontrollers (s51.src/uc88x.cc)
+ *
+ * Copyright (C) 2017,17 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#include "mducl.h"
+
+#include "uc88xcl.h"
+
+
+cl_uc88x::cl_uc88x(struct cpu_entry *Itype, class cl_sim *asim):
+  cl_uc52(Itype, asim)
+{
+}
+
+int
+cl_uc88x::init(void)
+{
+  int ret;
+  ret= cl_uc52::init();
+
+  cpu->cfg_set(uc51cpu_aof_mdpc, 0xA2);
+  cpu->cfg_set(uc51cpu_mask_mdpc, 1);
+  class cl_memory_chip *dptr_chip=
+    new cl_memory_chip("dptr_chip", 3*8, 8);
+  dptr_chip->init();
+  memchips->add(dptr_chip);
+  decode_dptr();
+  
+  return ret;
+}
+
+
+void
+cl_uc88x::mk_hw_elements(void)
+{
+  cl_uc52::mk_hw_elements();
+
+  class cl_mdu88x *mdu= new cl_mdu88x(this, 0);
+  add_hw(mdu);
+  mdu->init();
+}
+
+/* End of s51.src/uc88x.cc */
diff --git a/sim/ucsim/s51.src/uc88xcl.h b/sim/ucsim/s51.src/uc88xcl.h
new file mode 100644
index 0000000..0cfcf50
--- /dev/null
+++ b/sim/ucsim/s51.src/uc88xcl.h
@@ -0,0 +1,44 @@
+/*
+ * Simulator of microcontrollers (s51.src/uc88xcl.h)
+ *
+ * Copyright (C) 2017,17 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#ifndef UC88XCL_HEADER
+#define UC88XCL_HEADER
+
+#include "uc52cl.h"
+
+class cl_uc88x: public cl_uc52
+{
+ public:
+  cl_uc88x(struct cpu_entry *Itype, class cl_sim *asim);
+  virtual int init(void);
+  virtual void mk_hw_elements(void);
+};
+
+
+#endif
+
+/* End of s51.src/uc88xcl.h */
diff --git a/sim/ucsim/s51.src/uc89c51r.cc b/sim/ucsim/s51.src/uc89c51r.cc
new file mode 100644
index 0000000..9a658f1
--- /dev/null
+++ b/sim/ucsim/s51.src/uc89c51r.cc
@@ -0,0 +1,110 @@
+/*
+ * Simulator of microcontrollers (uc89c51r.cc)
+ *
+ * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
+ *
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#include "ddconfig.h"
+
+#include <stdio.h>
+#include <ctype.h>
+
+// local
+#include "uc89c51rcl.h"
+#include "regs51.h"
+#include "pcacl.h"
+#include "wdtcl.h"
+
+
+cl_uc89c51r::cl_uc89c51r(struct cpu_entry *Itype, class cl_sim *asim):
+  cl_uc51r(Itype, asim)
+{
+}
+
+int
+cl_uc89c51r::init(void)
+{
+  int r= cl_uc51r::init();
+
+  cpu->cfg_set(uc51cpu_aof_mdpc, 0xA2);
+  cpu->cfg_set(uc51cpu_mask_mdpc, 1);
+  class cl_memory_chip *dptr_chip=
+    new cl_memory_chip("dptr_chip", 3*8, 8);
+  dptr_chip->init();
+  memchips->add(dptr_chip);
+  decode_dptr();
+  
+  return r;
+}
+
+void
+cl_uc89c51r::mk_hw_elements(void)
+{
+  class cl_hw *h;
+
+  cl_uc52::mk_hw_elements();
+  add_hw(h= new cl_wdt(this, 0x3fff));
+  h->init();
+  add_hw(h= new cl_pca(this, 0));
+  h->init();
+}
+
+void
+cl_uc89c51r::make_memories(void)
+{
+  cl_uc52::make_memories();
+}
+
+void
+cl_uc89c51r::reset(void)
+{
+  cl_uc51r::reset();
+  sfr->set_bit1(CCAPM0, bmECOM);
+  sfr->set_bit1(CCAPM1, bmECOM);
+  sfr->set_bit1(CCAPM2, bmECOM);
+  sfr->set_bit1(CCAPM3, bmECOM);
+  sfr->set_bit1(CCAPM4, bmECOM);
+  sfr->write(IPH, 0);
+}
+
+int
+cl_uc89c51r::it_priority(uchar ie_mask)
+{
+  uchar l, h;
+
+  l= sfr->get(IP) & ie_mask;
+  h= sfr->get(IPH) & ie_mask;
+  if (!h && !l)
+    return(0);
+  if (!h && l)
+    return(1);
+  if (h && !l)
+    return(2);
+  if (h && l)
+    return(3);
+  return(0);
+}
+
+
+/* End of s51.src/uc89c51r.cc */
diff --git a/sim/ucsim/s51.src/uc89c51rcl.h b/sim/ucsim/s51.src/uc89c51rcl.h
new file mode 100644
index 0000000..b90ca63
--- /dev/null
+++ b/sim/ucsim/s51.src/uc89c51rcl.h
@@ -0,0 +1,53 @@
+/*
+ * Simulator of microcontrollers (uc89c51rcl.h)
+ *
+ * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#ifndef UC89C51RCL_HEADER
+#define UC89C51RCL_HEADER
+
+#include "ddconfig.h"
+
+#include "uc51rcl.h"
+
+#include "newcmdcl.h"
+
+
+class cl_uc89c51r: public cl_uc51r
+{
+public:
+  cl_uc89c51r(struct cpu_entry *Itype, class cl_sim *asim);
+  virtual int init(void);
+  virtual void mk_hw_elements(void);
+  virtual void make_memories(void);
+  
+  virtual void  reset(void);
+  virtual int   it_priority(uchar ie_mask);
+};
+
+
+#endif
+
+/* End of s51.src/uc89c51rcl.h */
diff --git a/sim/ucsim/s51.src/wdt.cc b/sim/ucsim/s51.src/wdt.cc
new file mode 100644
index 0000000..cf4795f
--- /dev/null
+++ b/sim/ucsim/s51.src/wdt.cc
@@ -0,0 +1,101 @@
+/*
+ * Simulator of microcontrollers (wdt.cc)
+ *
+ * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#include <ctype.h>
+
+// local
+#include "wdtcl.h"
+#include "regs51.h"
+
+
+cl_wdt::cl_wdt(class cl_uc *auc, long resetvalue):
+  cl_hw(auc, HW_WDT, 0, "wdt")
+{
+  reset_value= resetvalue;
+  wdt= -1;
+  written_since_reset= false;
+}
+
+int
+cl_wdt::init(void)
+{
+  class cl_address_space *sfr= uc->address_space(MEM_SFR_ID);
+
+  cl_hw::init();
+  if (!sfr)
+    {
+      fprintf(stderr, "No SFR to register WDT into\n");
+    }
+  wdtrst= register_cell(sfr, WDTRST);
+  return(0);
+}
+
+void
+cl_wdt::write(class cl_memory_cell *cell, t_mem *val)
+{
+  if (cell == wdtrst &&
+      (((*val)&0xff) == 0xe1) &&
+      (wdtrst->get() == 0x1e) &&
+      written_since_reset)
+    {
+      wdt= 0;
+    }
+  written_since_reset= true;
+}
+
+int
+cl_wdt::tick(int cycles)
+{
+  if (wdt >= 0)
+    {
+      wdt+= cycles;
+      if (wdt > reset_value)
+	{
+	  uc->reset();
+	  //return(resWDTRESET);
+	}
+    }
+  return(0);
+}
+
+void
+cl_wdt::reset(void)
+{
+  written_since_reset= false;
+  wdt= -1;
+}
+
+void
+cl_wdt::print_info(class cl_console_base *con)
+{
+  con->dd_printf("%s[%d] %s counter=%d (remains=%d)\n", id_string, id,
+		 (wdt>=0)?"ON":"OFF", wdt, (wdt>=0)?(reset_value-wdt):0);
+  print_cfg_info(con);
+}
+
+
+/* End of s51.src/wdt.cc */
diff --git a/sim/ucsim/s51.src/wdtcl.h b/sim/ucsim/s51.src/wdtcl.h
new file mode 100644
index 0000000..68d5252
--- /dev/null
+++ b/sim/ucsim/s51.src/wdtcl.h
@@ -0,0 +1,66 @@
+/*
+ * Simulator of microcontrollers (wdtcl.h)
+ *
+ * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#ifndef S51_WDTCL_HEADER
+#define S51_WDTCL_HEADER
+
+// sim.src
+//#include "stypes.h"
+//#include "pobjcl.h"
+#include "uccl.h"
+
+// local
+//#include "newcmdcl.h"
+#include "uc51rcl.h"
+
+
+class cl_wdt: public cl_hw
+{
+protected:
+  long wdt, reset_value;
+  class cl_memory_cell *wdtrst;
+  bool written_since_reset;
+public:
+  cl_wdt(class cl_uc *auc, long resetvalue);
+  virtual int init(void);
+  //virtual char *cfg_help(t_addr addr);
+
+  //virtual t_mem read(class cl_memory_cell *cell);
+  virtual void write(class cl_memory_cell *cell, t_mem *val);
+
+  //virtual t_mem set_cmd(t_mem value);
+
+  virtual int tick(int cycles);
+  virtual void reset(void);
+  
+  virtual void print_info(class cl_console_base *con);
+};
+
+
+#endif
+
+/* End of s51.src/wdtcl.h */