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| author | Xavier ASUS <xavi92psx@gmail.com> | 2019-10-18 00:31:54 +0200 |
|---|---|---|
| committer | Xavier ASUS <xavi92psx@gmail.com> | 2019-10-18 00:31:54 +0200 |
| commit | 268a53de823a6750d6256ee1fb1e7707b4b45740 (patch) | |
| tree | 42c1799a9a82b2f7d9790ee9fe181d72a7274751 /sim/ucsim/doc/decoded.fig | |
| download | sdcc-gas-268a53de823a6750d6256ee1fb1e7707b4b45740.tar.gz | |
sdcc-3.9.0 fork implementing GNU assembler syntax
This fork aims to provide better support for stm8-binutils
Diffstat (limited to 'sim/ucsim/doc/decoded.fig')
| -rw-r--r-- | sim/ucsim/doc/decoded.fig | 116 |
1 files changed, 116 insertions, 0 deletions
diff --git a/sim/ucsim/doc/decoded.fig b/sim/ucsim/doc/decoded.fig new file mode 100644 index 0000000..77d98bf --- /dev/null +++ b/sim/ucsim/doc/decoded.fig @@ -0,0 +1,116 @@ +#FIG 3.2 Produced by xfig version 3.2.5-alpha4 +Landscape +Center +Metric +A4 +100.00 +Single +-2 +1200 2 +2 1 0 3 0 15 46 -1 20 0.000 0 0 -1 0 0 2 + 3285 1080 3465 1080 +2 1 0 3 0 15 46 -1 20 0.000 0 0 -1 0 0 2 + 3285 4140 3465 4140 +2 1 0 1 0 7 46 -1 -1 0.000 0 0 -1 0 0 7 + 3375 3870 3465 3780 3465 3465 3555 3375 3465 3285 3465 2970 + 3375 2880 +2 2 0 1 0 17 50 -1 20 0.000 0 0 -1 0 0 5 + 3870 1350 4410 1350 4410 2520 3870 2520 3870 1350 +2 1 0 1 0 7 46 -1 -1 0.000 0 0 -1 0 0 7 + 3375 2520 3465 2430 3465 1980 3555 1890 3465 1800 3465 1440 + 3375 1350 +2 1 2 1 0 15 46 -1 20 2.000 0 0 -1 0 0 2 + 3375 3870 3870 3870 +2 1 2 1 0 15 46 -1 20 2.000 0 0 -1 0 0 2 + 3375 2520 3870 2520 +2 1 2 1 0 15 46 -1 20 2.000 0 0 -1 1 0 2 + 0 0 1.00 60.00 120.00 + 3690 2520 3690 1350 +2 1 2 1 0 15 46 -1 20 2.000 0 0 -1 1 0 2 + 0 0 1.00 60.00 120.00 + 3690 3870 3690 2880 +2 1 0 3 0 15 46 -1 20 0.000 0 0 -1 0 0 2 + 3375 2925 3375 3870 +2 2 0 1 0 17 50 -1 20 0.000 0 0 -1 0 0 5 + 3870 2880 4410 2880 4410 3870 3870 3870 3870 2880 +2 1 0 3 0 15 46 -1 20 0.000 0 0 -1 0 0 2 + 3375 1350 3375 2520 +2 1 0 1 0 7 50 -1 -1 0.000 0 0 -1 0 0 2 + 3375 1080 3375 4140 +2 1 0 3 8 15 46 -1 20 0.000 0 0 -1 0 0 2 + 5715 1350 5895 1350 +2 1 0 3 8 15 46 -1 20 0.000 0 0 -1 0 0 2 + 5715 3375 5895 3375 +2 1 0 1 0 7 46 -1 -1 0.000 0 0 -1 0 0 7 + 5805 2970 5895 2880 5895 2565 5985 2475 5895 2385 5895 2070 + 5805 1980 +2 1 2 1 0 15 46 -1 20 2.000 0 0 -1 0 0 2 + 5805 2970 6300 2970 +2 1 2 1 0 15 46 -1 20 2.000 0 0 -1 1 0 2 + 0 0 1.00 60.00 120.00 + 6075 2970 6075 1980 +2 2 0 1 0 15 50 -1 20 0.000 0 0 -1 0 0 5 + 6300 1980 6840 1980 6840 2970 6300 2970 6300 1980 +2 1 0 3 8 15 46 -1 20 0.000 0 0 -1 0 0 2 + 5805 1980 5805 2970 +2 1 0 1 8 7 50 -1 -1 0.000 0 0 -1 0 0 2 + 5805 1350 5805 3375 +2 1 0 3 8 15 46 -1 20 0.000 0 0 -1 0 0 2 + 8280 1350 8460 1350 +2 1 0 3 8 15 46 -1 20 0.000 0 0 -1 0 0 2 + 8280 3375 8460 3375 +2 1 0 1 0 7 46 -1 -1 0.000 0 0 -1 0 0 7 + 8370 2970 8460 2880 8460 2745 8550 2655 8460 2565 8460 2385 + 8370 2295 +2 1 2 1 0 15 46 -1 20 2.000 0 0 -1 0 0 2 + 8370 2970 8865 2970 +2 1 2 1 0 15 46 -1 20 2.000 0 0 -1 1 0 2 + 0 0 1.00 60.00 120.00 + 8640 2970 8640 2295 +2 1 0 3 8 15 46 -1 20 0.000 0 0 -1 0 0 2 + 8370 2295 8370 2970 +2 1 0 1 8 7 50 -1 -1 0.000 0 0 -1 0 0 2 + 8370 1350 8370 3375 +2 2 0 1 0 15 50 -1 20 0.000 0 0 -1 0 0 5 + 8865 2295 9405 2295 9405 2970 8865 2970 8865 2295 +2 2 0 1 -1 7 60 -1 20 0.000 0 0 -1 0 0 5 + 8865 2295 9405 2295 9405 1980 8865 1980 8865 2295 +2 1 0 1 0 7 58 -1 -1 0.000 0 0 -1 0 0 2 + 9000 1710 9180 2025 +2 1 0 1 0 7 60 -1 -1 0.000 0 0 -1 0 0 2 + 5805 3105 6525 3555 +2 1 0 1 0 7 60 -1 -1 0.000 0 0 -1 0 0 2 + 6390 1530 5805 2250 +2 1 0 1 0 7 60 -1 -1 0.000 0 0 -1 0 0 2 + 6930 1530 8370 2475 +4 1 0 46 -1 16 12 0.0000 4 135 465 4140 1530 size2\001 +4 1 0 46 -1 16 12 0.0000 4 135 540 4140 2025 Mem2\001 +4 2 0 46 -1 16 12 0.0000 4 165 1035 3285 2520 mem2_start\001 +4 2 0 46 -1 16 12 0.0000 4 180 1035 3285 3870 mem1_start\001 +4 1 0 46 -1 16 12 0.0000 4 195 885 2835 4185 begin_as1\001 +4 1 0 46 -1 16 12 0.0000 4 180 735 2880 1125 end_as1\001 +4 1 0 46 -1 16 12 0.0000 4 180 1515 2790 810 Address Space I.\001 +4 1 0 46 -1 16 12 0.0000 4 180 1575 5220 1080 Address Space II.\001 +4 1 0 46 -1 16 12 0.0000 4 150 465 4140 3060 size1\001 +4 1 0 46 -1 16 12 0.0000 4 150 540 4140 3465 Mem1\001 +4 1 0 46 -1 16 12 0.0000 4 135 105 4140 2430 0\001 +4 1 0 46 -1 16 12 0.0000 4 135 105 4140 3780 0\001 +4 1 0 46 -1 16 12 0.0000 4 135 105 6570 2925 0\001 +4 1 0 46 -1 16 12 0.0000 4 135 465 6570 2160 size3\001 +4 1 0 46 -1 16 12 0.0000 4 135 540 6570 2520 Mem3\001 +4 1 0 46 -1 16 12 0.0000 4 165 735 5310 1395 end_as2\001 +4 1 0 46 -1 16 12 0.0000 4 180 885 5220 3420 begin_as2\001 +4 2 0 46 -1 16 12 0.0000 4 165 1035 5715 2970 mem3_start\001 +4 1 0 46 -1 16 12 0.0000 4 135 105 9135 2925 0\001 +4 1 0 46 -1 16 12 0.0000 4 135 360 9135 2160 size\001 +4 1 0 46 -1 16 12 0.0000 4 135 435 9135 2520 Mem\001 +4 1 0 46 -1 16 12 0.0000 4 165 630 7875 1395 end_as\001 +4 1 0 46 -1 16 12 0.0000 4 180 780 7785 3420 begin_as\001 +4 2 0 46 -1 16 12 0.0000 4 165 930 8280 2970 mem_start\001 +4 0 0 60 -1 16 12 0.0000 4 135 1140 8865 1170 Non-decoded\001 +4 0 0 60 -1 16 12 0.0000 4 150 705 8865 1395 memory\001 +4 0 0 60 -1 16 12 0.0000 4 135 405 8865 1620 cells\001 +4 0 0 60 -1 16 12 0.0000 4 135 1140 6165 3735 Non-decoded\001 +4 0 0 60 -1 16 12 0.0000 4 135 900 6165 3960 addresses\001 +4 0 0 60 -1 16 12 0.0000 4 135 765 6255 1260 Decoded\001 +4 0 0 60 -1 16 12 0.0000 4 135 900 6255 1485 addresses\001 |
