sdcc-3.9.0 fork implementing GNU assembler syntax

This fork aims to provide better support for stm8-binutils

36 files changed, 5322 insertions, 0 deletions

diff --git a/sim/ucsim/avr.src/(c).1 b/sim/ucsim/avr.src/(c).1
new file mode 100644
index 0000000..d673f9f
--- /dev/null
+++ b/sim/ucsim/avr.src/(c).1
@@ -0,0 +1,25 @@
+/*
+ * Simulator of microcontrollers (@@F@@)
+ *
+ * Copyright (C) @@S@@,@@Y@@ Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
diff --git a/sim/ucsim/avr.src/Makefile b/sim/ucsim/avr.src/Makefile
new file mode 100644
index 0000000..6d3859a
--- /dev/null
+++ b/sim/ucsim/avr.src/Makefile
@@ -0,0 +1,162 @@
+#
+# uCsim avr.src/Makefile
+#
+# (c) Drotos Daniel, Talker Bt. 1997
+#
+
+STARTYEAR	= 1997
+
+SHELL		= /bin/sh
+CXX		= g++
+CPP		= gcc -E
+CXXCPP		= g++ -E
+RANLIB		= ranlib
+INSTALL		= /usr/bin/install -c
+STRIP		= strip
+MAKEDEP         = g++ -MM
+
+top_builddir	= ..
+top_srcdir	= ..
+
+transform	= s,x,x,
+
+DEFS            = $(subs -DHAVE_CONFIG_H,,-DHAVE_CONFIG_H)
+CPPFLAGS        =  -I$(srcdir) -I$(top_srcdir) -I$(top_builddir) \
+		  -I$(top_srcdir)/cmd.src -I$(top_srcdir)/sim.src \
+		  -I$(top_srcdir)/gui.src
+CFLAGS          = -g -O2 -Wall
+CXXFLAGS        = -g -O2 -g -Wall
+LDFLAGS         = 
+PICOPT		=  -fPIC -DPIC
+SHAREDLIB	= yes
+EXEEXT		= 
+
+LIBS		= -L$(top_builddir) -lsim -lucsimutil -lguiucsim -lcmd -lsim -lrt -lnsl 
+DL		= -ldl
+dl_ok		= yes
+
+prefix          = /usr/local
+exec_prefix     = ${prefix}
+bindir          = ${exec_prefix}/bin
+libdir          = ${exec_prefix}/lib
+datadir         = ${datarootdir}
+datarootdir     = ${prefix}/share
+includedir      = ${prefix}/include
+mandir          = ${datarootdir}/man
+man1dir         = $(mandir)/man1
+man2dir         = $(mandir)/man2
+infodir         = ${datarootdir}/info
+srcdir          = .
+
+
+OBJECTS_SHARED	= glob.o \
+		  simavr.o avr.o port.o \
+		  inst.o bit_inst.o jump_inst.o move_inst.o logic_inst.o \
+		  arith_inst.o
+OBJECTS_EXE	= savr.o
+OBJECTS		= $(OBJECTS_SHARED) $(OBJECTS_EXE)
+
+enable_dlso	= no
+dlso_ok		= no
+
+AVRASM		= tavrasm
+TEST_OBJ	= test_bit.hex test_dis.hex test_mov.hex test_jmp.hex \
+		  test_arith.hex test_call.hex
+
+
+# Compiling entire program or any subproject
+# ------------------------------------------
+all: checkconf otherlibs avr.src
+
+
+# Compiling and installing everything and runing test
+# ---------------------------------------------------
+install: all installdirs
+	$(INSTALL) savr$(EXEEXT) $(DESTDIR)$(bindir)/`echo savr|sed '$(transform)'`$(EXEEXT)
+	$(STRIP) $(DESTDIR)$(bindir)/`echo savr|sed '$(transform)'`$(EXEEXT)
+
+
+# Deleting all the installed files
+# --------------------------------
+uninstall:
+	rm -f $(DESTDIR)$(bindir)/savr
+	rm -f $(DESTDIR)$(bindir)/`echo savr|sed '$(transform)'`$(EXEEXT)
+
+
+# Performing self-test
+# --------------------
+check: $(TEST_OBJ)
+
+test:
+
+
+# Performing installation test
+# ----------------------------
+installcheck:
+
+
+# Creating installation directories
+# ---------------------------------
+installdirs:
+	test -d $(DESTDIR)$(bindir) || $(INSTALL) -d $(DESTDIR)$(bindir)
+
+
+# Creating dependencies
+# ---------------------
+dep: Makefile.dep
+
+Makefile.dep: $(srcdir)/*.cc $(srcdir)/*.h
+	$(MAKEDEP) $(CPPFLAGS) $(filter %.cc,$^) >Makefile.dep
+
+-include Makefile.dep
+include $(srcdir)/clean.mk
+
+# My rules
+# --------
+.SUFFIXES: .asm .hex
+
+avr.src: savr$(EXEEXT) shared_lib
+
+savr$(EXEEXT): $(OBJECTS) $(top_builddir)/libcmd.a $(top_builddir)/libguiucsim.a $(top_builddir)/libsim.a $(top_builddir)/libucsimutil.a
+	$(CXX) $(CXXFLAGS) $(LDFLAGS) $(OBJECTS) $(LIBS) -o $@
+
+ifeq ($(dlso_ok),yes)
+shared_lib: $(top_builddir)/savr.so
+else
+shared_lib:
+	@$(top_srcdir)/mkecho $(top_builddir) "No AVR shared lib made."
+	@$(top_srcdir)/mkecho $(top_builddir) "(SHAREDLIB="$(SHAREDLIB)",dl_ok="$(dl_ok)",enable_dlso="$(enable_dlso)")"
+endif
+
+$(top_builddir)/savr.so: $(OBJECTS_SHARED)
+	$(CXX) -shared $(LDFLAGS) $(OBJECTS_SHARED) -o $@
+
+otherlibs: $(top_builddir)/libcmd.a $(top_builddir)/libguiucsim.a $(top_builddir)/libsim.a $(top_builddir)/libucsimutil.a
+
+$(top_builddir)/libcmd.a:
+	$(MAKE) -C $(top_builddir)/cmd.src all
+
+$(top_builddir)/libguiucsim.a:
+	$(MAKE) -C $(top_builddir)/gui.src checkconf ucsim_lib
+
+$(top_builddir)/libsim.a:
+	$(MAKE) -C $(top_builddir)/sim.src all
+
+$(top_builddir)/libucsimutil.a:
+	$(MAKE) -C $(top_builddir) -f main.mk
+
+.cc.o:
+	$(CXX) $(CXXFLAGS) $(PICOPT) $(CPPFLAGS) $(TARGET_ARCH) -c $< -o $@
+
+.asm.hex:
+	$(AVRASM) -l $< -o $@ -e $<.lst
+
+
+# Remaking configuration
+# ----------------------
+checkconf:
+	@if [ -f $(top_builddir)/devel ]; then\
+	  $(MAKE) -C $(top_builddir) -f conf.mk srcdir="$(srcdir)" top_builddir="$(top_builddir)" freshconf;\
+	fi
+
+# End of avr.src/Makefile.in
diff --git a/sim/ucsim/avr.src/Makefile.in b/sim/ucsim/avr.src/Makefile.in
new file mode 100644
index 0000000..f5b9760
--- /dev/null
+++ b/sim/ucsim/avr.src/Makefile.in
@@ -0,0 +1,162 @@
+#
+# uCsim avr.src/Makefile
+#
+# (c) Drotos Daniel, Talker Bt. 1997
+#
+
+STARTYEAR	= 1997
+
+SHELL		= /bin/sh
+CXX		= @CXX@
+CPP		= @CPP@
+CXXCPP		= @CXXCPP@
+RANLIB		= @RANLIB@
+INSTALL		= @INSTALL@
+STRIP		= @STRIP@
+MAKEDEP         = @MAKEDEP@
+
+top_builddir	= @top_builddir@
+top_srcdir	= @top_srcdir@
+
+transform	= @program_transform_name@
+
+DEFS            = $(subs -DHAVE_CONFIG_H,,@DEFS@)
+CPPFLAGS        = @CPPFLAGS@ -I$(srcdir) -I$(top_srcdir) -I$(top_builddir) \
+		  -I$(top_srcdir)/cmd.src -I$(top_srcdir)/sim.src \
+		  -I$(top_srcdir)/gui.src
+CFLAGS          = @CFLAGS@ @WALL_FLAG@
+CXXFLAGS        = @CXXFLAGS@ @WALL_FLAG@
+LDFLAGS         = @LDFLAGS@
+PICOPT		= @PICOPT@
+SHAREDLIB	= @SHAREDLIB@
+EXEEXT		= @EXEEXT@
+
+LIBS		= -L$(top_builddir) -lsim -lucsimutil -lguiucsim -lcmd -lsim @LIBS@
+DL		= @DL@
+dl_ok		= @dl_ok@
+
+prefix          = @prefix@
+exec_prefix     = @exec_prefix@
+bindir          = @bindir@
+libdir          = @libdir@
+datadir         = @datadir@
+datarootdir     = @datarootdir@
+includedir      = @includedir@
+mandir          = @mandir@
+man1dir         = $(mandir)/man1
+man2dir         = $(mandir)/man2
+infodir         = @infodir@
+srcdir          = @srcdir@
+VPATH           = @srcdir@
+
+OBJECTS_SHARED	= glob.o \
+		  simavr.o avr.o port.o \
+		  inst.o bit_inst.o jump_inst.o move_inst.o logic_inst.o \
+		  arith_inst.o
+OBJECTS_EXE	= savr.o
+OBJECTS		= $(OBJECTS_SHARED) $(OBJECTS_EXE)
+
+enable_dlso	= @enable_dlso@
+dlso_ok		= @dlso_ok@
+
+AVRASM		= tavrasm
+TEST_OBJ	= test_bit.hex test_dis.hex test_mov.hex test_jmp.hex \
+		  test_arith.hex test_call.hex
+
+
+# Compiling entire program or any subproject
+# ------------------------------------------
+all: checkconf otherlibs avr.src
+
+
+# Compiling and installing everything and runing test
+# ---------------------------------------------------
+install: all installdirs
+	$(INSTALL) savr$(EXEEXT) $(DESTDIR)$(bindir)/`echo savr|sed '$(transform)'`$(EXEEXT)
+	$(STRIP) $(DESTDIR)$(bindir)/`echo savr|sed '$(transform)'`$(EXEEXT)
+
+
+# Deleting all the installed files
+# --------------------------------
+uninstall:
+	rm -f $(DESTDIR)$(bindir)/savr
+	rm -f $(DESTDIR)$(bindir)/`echo savr|sed '$(transform)'`$(EXEEXT)
+
+
+# Performing self-test
+# --------------------
+check: $(TEST_OBJ)
+
+test:
+
+
+# Performing installation test
+# ----------------------------
+installcheck:
+
+
+# Creating installation directories
+# ---------------------------------
+installdirs:
+	test -d $(DESTDIR)$(bindir) || $(INSTALL) -d $(DESTDIR)$(bindir)
+
+
+# Creating dependencies
+# ---------------------
+dep: Makefile.dep
+
+Makefile.dep: $(srcdir)/*.cc $(srcdir)/*.h
+	$(MAKEDEP) $(CPPFLAGS) $(filter %.cc,$^) >Makefile.dep
+
+-include Makefile.dep
+include $(srcdir)/clean.mk
+
+# My rules
+# --------
+.SUFFIXES: .asm .hex
+
+avr.src: savr$(EXEEXT) shared_lib
+
+savr$(EXEEXT): $(OBJECTS) $(top_builddir)/libcmd.a $(top_builddir)/libguiucsim.a $(top_builddir)/libsim.a $(top_builddir)/libucsimutil.a
+	$(CXX) $(CXXFLAGS) $(LDFLAGS) $(OBJECTS) $(LIBS) -o $@
+
+ifeq ($(dlso_ok),yes)
+shared_lib: $(top_builddir)/savr.so
+else
+shared_lib:
+	@$(top_srcdir)/mkecho $(top_builddir) "No AVR shared lib made."
+	@$(top_srcdir)/mkecho $(top_builddir) "(SHAREDLIB="$(SHAREDLIB)",dl_ok="$(dl_ok)",enable_dlso="$(enable_dlso)")"
+endif
+
+$(top_builddir)/savr.so: $(OBJECTS_SHARED)
+	$(CXX) -shared $(LDFLAGS) $(OBJECTS_SHARED) -o $@
+
+otherlibs: $(top_builddir)/libcmd.a $(top_builddir)/libguiucsim.a $(top_builddir)/libsim.a $(top_builddir)/libucsimutil.a
+
+$(top_builddir)/libcmd.a:
+	$(MAKE) -C $(top_builddir)/cmd.src all
+
+$(top_builddir)/libguiucsim.a:
+	$(MAKE) -C $(top_builddir)/gui.src checkconf ucsim_lib
+
+$(top_builddir)/libsim.a:
+	$(MAKE) -C $(top_builddir)/sim.src all
+
+$(top_builddir)/libucsimutil.a:
+	$(MAKE) -C $(top_builddir) -f main.mk
+
+.cc.o:
+	$(CXX) $(CXXFLAGS) $(PICOPT) $(CPPFLAGS) $(TARGET_ARCH) -c $< -o $@
+
+.asm.hex:
+	$(AVRASM) -l $< -o $@ -e $<.lst
+
+
+# Remaking configuration
+# ----------------------
+checkconf:
+	@if [ -f $(top_builddir)/devel ]; then\
+	  $(MAKE) -C $(top_builddir) -f conf.mk srcdir="$(srcdir)" top_builddir="$(top_builddir)" freshconf;\
+	fi
+
+# End of avr.src/Makefile.in
diff --git a/sim/ucsim/avr.src/arith_cl.h b/sim/ucsim/avr.src/arith_cl.h
new file mode 100644
index 0000000..8d43b88
--- /dev/null
+++ b/sim/ucsim/avr.src/arith_cl.h
@@ -0,0 +1,27 @@
+/* avr.src/arith_cl.h */
+
+  virtual int cpi_Rd_K(t_mem code);
+  virtual int sbci_Rd_K(t_mem code);
+  virtual int subi_Rd_K(t_mem code);
+  virtual int muls_Rd_Rr(t_mem code);
+  virtual int mulsu_Rd_Rr(t_mem code);
+  virtual int fmul_Rd_Rr(t_mem code);
+  virtual int fmuls_Rd_Rr(t_mem code);
+  virtual int fmulsu_Rd_Rr(t_mem code);
+  virtual int cpc_Rd_Rr(t_mem code);
+  virtual int sbc_Rd_Rr(t_mem code);
+  virtual int add_Rd_Rr(t_mem code);
+  virtual int cp_Rd_Rr(t_mem code);
+  virtual int sub_Rd_Rr(t_mem code);
+  virtual int adc_Rd_Rr(t_mem code);
+  virtual int com_Rd(t_mem code);
+  virtual int neg_Rd(t_mem code);
+  virtual int inc_Rd(t_mem code);
+  virtual int asr_Rd(t_mem code);
+  virtual int lsr_Rd(t_mem code);
+  virtual int ror_Rd(t_mem code);
+  virtual int dec_Rd(t_mem code);
+  virtual int mul_Rd_Rr(t_mem code);
+  virtual int adiw_Rdl_K(t_mem code);
+  virtual int sbiw_Rdl_K(t_mem code);
+/* End of avr.src/arith_cl.h */
diff --git a/sim/ucsim/avr.src/arith_inst.cc b/sim/ucsim/avr.src/arith_inst.cc
new file mode 100644
index 0000000..53f6626
--- /dev/null
+++ b/sim/ucsim/avr.src/arith_inst.cc
@@ -0,0 +1,956 @@
+/*
+ * Simulator of microcontrollers (arith_inst.cc)
+ *
+ * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#include "avrcl.h"
+#include "regsavr.h"
+
+
+/*
+ * Compare with Immediate
+ * CPI Rd,K 16<=d<=31, 0<=K<=255
+ * 0011 KKKK dddd KKKK
+ *____________________________________________________________________________
+ */
+
+int
+cl_avr::cpi_Rd_K(t_mem code)
+{
+  t_addr d;
+  t_mem D, K, result, res;
+
+  d= 16+((code&0xf0)>>4);
+  K= (code&0xf) | ((code&0xf00)>>8);
+  D= ram->read(d);
+
+  if (K & 0x80)
+    K|= ~0xff;
+  if (D & 0x80)
+    D|= ~0xff;
+  t_mem sreg= ram->get(SREG);
+  result= (signed)D-(signed)K;
+  res= result & 0xff;
+  
+  sreg= sreg & ~(BIT_H|BIT_S|BIT_V|BIT_N|BIT_C|BIT_Z);
+  if (0x08 & (((~D)&K) | (K&res) | (res&(~D))))
+    sreg|= BIT_H;
+  int n= 0, v= 0;
+  if (0x80 & ((D&(~K)&(~res)) | ((~D)&K&res)))
+    {
+      sreg|= BIT_V;
+      v= 1;
+    }
+  if (res & 0x80)
+    {
+      sreg|= BIT_N;
+      n= 1;
+    }
+  if ((n ^ v) & 1)
+    sreg|= BIT_S;
+  if (!res)
+    sreg|= BIT_Z;
+  if (0x80 & (((~D)&K) | (K&res) | (res&(~D))))
+    sreg|= BIT_C;
+  ram->set(SREG, sreg);
+  return(resGO);
+}
+
+
+/*
+ * Substract Immediate with Carry
+ * SBCI Rd,K 16<=d<=31, 0<=K<=255
+ * 0100 KKKK dddd KKKK
+ *____________________________________________________________________________
+ */
+
+int
+cl_avr::sbci_Rd_K(t_mem code)
+{
+  t_addr d;
+  t_mem D, K, result, res;
+
+  d= 16+((code&0xf0)>>4);
+  K= (code&0xf) | ((code&0xf00)>>8);
+  D= ram->read(d);
+
+  if (K & 0x80)
+    K|= ~0xff;
+  if (D & 0x80)
+    D|= ~0xff;
+  t_mem sreg= ram->get(SREG);
+  result= (signed)D-(signed)K-(sreg&BIT_C)?1:0;
+  res= result & 0xff;
+  ram->write(d, res);
+  
+  sreg= sreg & ~(BIT_H|BIT_S|BIT_V|BIT_N|BIT_C);
+  if (0x08 & (((~D)&K) | (K&res) | (res&(~D))))
+    sreg|= BIT_H;
+  int n= 0, v= 0;
+  if (0x80 & ((D&(~K)&(~res)) | ((~D)&K&res)))
+    {
+      sreg|= BIT_V;
+      v= 1;
+    }
+  if (res & 0x80)
+    {
+      sreg|= BIT_N;
+      n= 1;
+    }
+  if ((n ^ v) & 1)
+    sreg|= BIT_S;
+  if (res)
+    sreg&= ~BIT_Z;
+  if (0x80 & (((~D)&K) | (K&res) | (res&(~D))))
+    sreg|= BIT_C;
+  ram->set(SREG, sreg);
+  return(resGO);
+}
+
+
+/*
+ * Substract Immediate
+ * SUBI Rd,K 16<=d<=31, 0<=K<=255
+ * 0101 KKKK dddd KKKK
+ *____________________________________________________________________________
+ */
+
+int
+cl_avr::subi_Rd_K(t_mem code)
+{
+  t_addr d;
+  t_mem D, K, result, res;
+
+  d= 16+((code&0xf0)>>4);
+  K= (code&0xf) | ((code&0xf00)>>8);
+  D= ram->read(d);
+
+  if (K & 0x80)
+    K|= ~0xff;
+  if (D & 0x80)
+    D|= ~0xff;
+  result= (signed)D-(signed)K;
+  res= result & 0xff;
+  ram->write(d, res);
+  
+  t_mem sreg= ram->get(SREG) & ~(BIT_H|BIT_S|BIT_V|BIT_N|BIT_Z|BIT_C);
+  if (0x08 & (((~D)&K) | (K&res) | (res&(~D))))
+    sreg|= BIT_H;
+  int n= 0, v= 0;
+  if (0x80 & ((D&(~K)&(~res)) | ((~D)&K&res)))
+    {
+      sreg|= BIT_V;
+      v= 1;
+    }
+  if (res & 0x80)
+    {
+      sreg|= BIT_N;
+      n= 1;
+    }
+  if ((n ^ v) & 1)
+    sreg|= BIT_S;
+  if (!res)
+    sreg|= BIT_Z;
+  if (0x80 & (((~D)&K) | (K&res) | (res&(~D))))
+    sreg|= BIT_C;
+  ram->set(SREG, sreg);
+  return(resGO);
+}
+
+
+int
+cl_avr::muls_Rd_Rr(t_mem code)
+{
+  return(resGO);
+}
+
+
+int
+cl_avr::mulsu_Rd_Rr(t_mem code)
+{
+  return(resGO);
+}
+
+
+int
+cl_avr::fmul_Rd_Rr(t_mem code)
+{
+  return(resGO);
+}
+
+
+int
+cl_avr::fmuls_Rd_Rr(t_mem code)
+{
+  return(resGO);
+}
+
+
+int
+cl_avr::fmulsu_Rd_Rr(t_mem code)
+{
+  return(resGO);
+}
+
+
+/*
+ * Compare with Carry
+ * CPC Rd,Rr 0<=d<=31, 0<=r<=31
+ * 0000 01rd dddd rrrr
+ *____________________________________________________________________________
+ */
+
+int
+cl_avr::cpc_Rd_Rr(t_mem code)
+{
+  t_addr r, d;
+  t_mem R, D, result, res;
+
+  d= (code&0x1f0)>>4;
+  r= ((code&0x200)>>5)|(code&0xf);
+  R= ram->read(r);
+  D= ram->read(d);
+  if (R & 0x80)
+    R|= ~0xff;
+  if (D & 0x80)
+    D|= ~0xff;
+  t_mem sreg= ram->get(SREG);
+  result= (signed)D-(signed)R-(sreg&BIT_C)?1:0;
+  res= result & 0xff;
+  
+  sreg= sreg & ~(BIT_H|BIT_S|BIT_V|BIT_N|BIT_C);
+  if (0x08 & (((~D)&R) | (R&res) | (res&(~D))))
+    sreg|= BIT_H;
+  int n= 0, v= 0;
+  if (0x80 & ((D&(~R)&(~res)) | ((~D)&R&res)))
+    {
+      sreg|= BIT_V;
+      v= 1;
+    }
+  if (res & 0x80)
+    {
+      sreg|= BIT_N;
+      n= 1;
+    }
+  if ((n ^ v) & 1)
+    sreg|= BIT_S;
+  if (res)
+    sreg&= ~BIT_Z;
+  if (0x80 & (((~D)&R) | (R&res) | (res&(~D))))
+    sreg|= BIT_C;
+  ram->set(SREG, sreg);
+  return(resGO);
+}
+
+
+/*
+ * Substract with Carry
+ * SBC Rd,Rr 0<=d<=31, 0<=r<=31
+ * 0000 10rd dddd rrrr
+ *____________________________________________________________________________
+ */
+
+int
+cl_avr::sbc_Rd_Rr(t_mem code)
+{
+  t_addr r, d;
+  t_mem R, D, result, res;
+
+  d= (code&0x1f0)>>4;
+  r= ((code&0x200)>>5)|(code&0xf);
+  R= ram->read(r);
+  D= ram->read(d);
+  if (R & 0x80)
+    R|= ~0xff;
+  if (D & 0x80)
+    D|= ~0xff;
+  t_mem sreg= ram->get(SREG);
+  result= (signed)D-(signed)R-(sreg&BIT_C)?1:0;
+  res= result & 0xff;
+  ram->write(d, res);
+  
+  sreg= sreg & ~(BIT_H|BIT_S|BIT_V|BIT_N|BIT_C);
+  if (0x08 & (((~D)&R) | (R&res) | (res&(~D))))
+    sreg|= BIT_H;
+  int n= 0, v= 0;
+  if (0x80 & ((D&(~R)&(~res)) | ((~D)&R&res)))
+    {
+      sreg|= BIT_V;
+      v= 1;
+    }
+  if (res & 0x80)
+    {
+      sreg|= BIT_N;
+      n= 1;
+    }
+  if ((n ^ v) & 1)
+    sreg|= BIT_S;
+  if (res)
+    sreg&= ~BIT_Z;
+  if (0x80 & (((~D)&R) | (R&res) | (res&(~D))))
+    sreg|= BIT_C;
+  ram->set(SREG, sreg);
+  return(resGO);
+}
+
+
+/*
+ * Add without Carry
+ * ADD Rd,Rr 0<=d<=31, 0<=r<=31
+ * 0000 11rd dddd rrrr
+ *____________________________________________________________________________
+ */
+
+int
+cl_avr::add_Rd_Rr(t_mem code)
+{
+  t_addr r, d;
+  t_mem R, D, result, res;
+
+  d= (code&0x1f0)>>4;
+  r= ((code&0x200)>>5)|(code&0xf);
+  R= ram->read(r);
+  D= ram->read(d);
+  result= D+R;
+  res= result & 0xff;
+  ram->write(d, res);
+  
+  t_mem sreg= ram->get(SREG);
+  if (!res)
+    sreg|= BIT_Z;
+  else
+    sreg&= ~BIT_Z;
+  if (((D&R&~res)&0x80) ||
+      ((~D&~R&res)&0x80))
+    sreg|= (BIT_V|BIT_S);
+  else
+    sreg&= ~(BIT_V|BIT_S);
+  if (res & 0x80)
+    {
+      sreg|= BIT_N;
+      sreg^= BIT_S;
+    }
+  else
+    sreg&= ~BIT_N;
+  if (result & ~0xff)
+    sreg|= BIT_C;
+  else
+    sreg&= ~BIT_C;
+  if ((R&0xf) + (D&0xf) > 15)
+    sreg|= BIT_H;
+  else
+    sreg&= ~BIT_H;
+  ram->set(SREG, sreg);
+
+  return(resGO);
+}
+
+
+/*
+ * Compare
+ * CP Rd,Rr 0<=d<=31, 0<=r<=31
+ * 0001 01rd dddd rrrr
+ *____________________________________________________________________________
+ */
+
+int
+cl_avr::cp_Rd_Rr(t_mem code)
+{
+  t_addr r, d;
+  t_mem R, D, result, res;
+
+  d= (code&0x1f0)>>4;
+  r= ((code&0x200)>>5)|(code&0xf);
+  R= ram->read(r);
+  D= ram->read(d);
+  if (R & 0x80)
+    R|= ~0xff;
+  if (D & 0x80)
+    D|= ~0xff;
+  result= (signed)D-(signed)R;
+  res= result & 0xff;
+  
+  t_mem sreg= ram->get(SREG) & ~(BIT_H|BIT_S|BIT_V|BIT_N|BIT_Z|BIT_C);
+  if (0x08 & (((~D)&R) | (R&res) | (res&(~D))))
+    sreg|= BIT_H;
+  int n= 0, v= 0;
+  if (0x80 & ((D&(~R)&(~res)) | ((~D)&R&res)))
+    {
+      sreg|= BIT_V;
+      v= 1;
+    }
+  if (res & 0x80)
+    {
+      sreg|= BIT_N;
+      n= 1;
+    }
+  if ((n ^ v) & 1)
+    sreg|= BIT_S;
+  if (!res)
+    sreg|= BIT_Z;
+  if (0x80 & (((~D)&R) | (R&res) | (res&(~D))))
+    sreg|= BIT_C;
+  ram->set(SREG, sreg);
+  return(resGO);
+}
+
+
+/*
+ * Substract without Carry
+ * SUB Rd,Rr 0<=d<=31, 0<=r<=31
+ * 0001 10rd dddd rrrr
+ *____________________________________________________________________________
+ */
+
+int
+cl_avr::sub_Rd_Rr(t_mem code)
+{
+  t_addr r, d;
+  t_mem R, D, result, res;
+
+  d= (code&0x1f0)>>4;
+  r= ((code&0x200)>>5)|(code&0xf);
+  R= ram->read(r);
+  D= ram->read(d);
+  if (R & 0x80)
+    R|= ~0xff;
+  if (D & 0x80)
+    D|= ~0xff;
+  result= (signed)D-(signed)R;
+  res= result & 0xff;
+  ram->write(d, res);
+  
+  t_mem sreg= ram->get(SREG) & ~(BIT_H|BIT_S|BIT_V|BIT_N|BIT_Z|BIT_C);
+  if (0x08 & (((~D)&R) | (R&res) | (res&(~D))))
+    sreg|= BIT_H;
+  int n= 0, v= 0;
+  if (0x80 & ((D&(~R)&(~res)) | ((~D)&R&res)))
+    {
+      sreg|= BIT_V;
+      v= 1;
+    }
+  if (res & 0x80)
+    {
+      sreg|= BIT_N;
+      n= 1;
+    }
+  if ((n ^ v) & 1)
+    sreg|= BIT_S;
+  if (!res)
+    sreg|= BIT_Z;
+  if (0x80 & (((~D)&R) | (R&res) | (res&(~D))))
+    sreg|= BIT_C;
+  ram->set(SREG, sreg);
+  return(resGO);
+}
+
+
+/*
+ * Add with Carry
+ * ADC Rd,Rr 0<=d<=31, 0<=r<=31
+ * 0001 11rd dddd rrrr
+ *____________________________________________________________________________
+ */
+
+int
+cl_avr::adc_Rd_Rr(t_mem code)
+{
+  t_addr r, d;
+  t_mem R, D, result, res;
+
+  d= (code&0x1f0)>>4;
+  r= ((code&0x200)>>5)|(code&0xf);
+  R= ram->read(r);
+  D= ram->read(d);
+  t_mem sreg= ram->get(SREG);
+  result= D+R+((sreg&BIT_C)?1:0);
+  res= result & 0xff;
+  ram->write(d, res);
+  
+  if (!res)
+    sreg|= BIT_Z;
+  else
+    sreg&= ~BIT_Z;
+  if (((D&R&~res)&0x80) ||
+      ((~D&~R&res)&0x80))
+    sreg|= (BIT_V|BIT_S);
+  else
+    sreg&= ~(BIT_V|BIT_S);
+  if (res & 0x80)
+    {
+      sreg|= BIT_N;
+      sreg^= BIT_S;
+    }
+  else
+    sreg&= ~BIT_N;
+  if (result & ~0xff)
+    sreg|= BIT_C;
+  else
+    sreg&= ~BIT_C;
+  if ((R&0xf) + (D&0xf) > 15)
+    sreg|= BIT_H;
+  else
+    sreg&= ~BIT_H;
+  ram->set(SREG, sreg);
+
+  return(resGO);
+}
+
+
+/*
+ * One's Complement
+ * COM Rd 0<=d<=31
+ * 1001 010d dddd 0000
+ *____________________________________________________________________________
+ */
+
+int
+cl_avr::com_Rd(t_mem code)
+{
+  t_addr d;
+  t_mem D, result, res;
+
+  d= (code&0x1f0)>>4;
+  D= ram->read(d);
+  result= ~D;
+  res= result & 0xff;
+  ram->write(d, res);
+  
+  t_mem sreg= ram->get(SREG);
+  if (!res)
+    sreg|= BIT_Z;
+  else
+    sreg&= ~BIT_Z;
+  sreg&= ~BIT_V;
+  if (res & 0x80)
+    sreg|= (BIT_N|BIT_S);
+  else
+    sreg&= ~(BIT_N|BIT_S);
+  sreg|= BIT_C;
+  ram->set(SREG, sreg);
+
+  return(resGO);
+}
+
+
+/*
+ * Two's Complement
+ * NEG Rd 0<=d<=31
+ * 1001 010d dddd 0001
+ *____________________________________________________________________________
+ */
+
+int
+cl_avr::neg_Rd(t_mem code)
+{
+  t_addr d;
+  t_mem D, result, res;
+
+  d= (code&0x1f0)>>4;
+  D= ram->read(d);
+  result= (~D)+1;
+  res= result & 0xff;
+  ram->write(d, res);
+  
+  t_mem sreg= ram->get(SREG);
+  if (res & (~d) & 0x08)
+    sreg|= BIT_H;
+  else
+    sreg&= ~BIT_H;
+  if (res > 0x80)
+    sreg|= BIT_S;
+  else
+    sreg&= ~BIT_S;
+  if (!res)
+    {
+      sreg|= BIT_Z;
+      sreg&= ~BIT_C;
+    }
+  else
+    {
+      sreg&= ~BIT_Z;
+      sreg|= BIT_C;
+    }
+  if (res == 0x80)
+    sreg|= BIT_V;
+  else
+    sreg&= ~BIT_V;
+  if (res & 0x80)
+    sreg|= (BIT_N);
+  else
+    sreg&= ~BIT_N;
+  ram->set(SREG, sreg);
+
+  return(resGO);
+}
+
+
+/*
+ * Increment
+ * INC Rd 0<=d<=31
+ * 1001 010d dddd 0011
+ *____________________________________________________________________________
+ */
+
+int
+cl_avr::inc_Rd(t_mem code)
+{
+  t_addr d;
+
+  d= (code&0x1f0)>>4;
+  t_mem data= ram->read(d)+1;
+  ram->write(d, data);
+
+  t_mem sreg= ram->get(SREG);
+  data= data&0xff;
+  if (data & 0x80)
+    {
+      sreg|= (BIT_N);
+      if (data == 0x80)
+	{
+	  sreg|= BIT_V;
+	  sreg&= ~BIT_S;
+	}
+      else
+	{
+	  sreg&= ~BIT_V;
+	  sreg|= BIT_S;
+	}
+      sreg&= ~BIT_Z;
+    }
+  else
+    {
+      sreg&= ~(BIT_N|BIT_V|BIT_S);
+      if (!data)
+	sreg|= BIT_Z;
+      else
+	sreg&= ~BIT_Z;
+    }
+  ram->set(SREG, sreg);
+  return(resGO);
+}
+
+
+/*
+ * Arithmetic Shift Right
+ * ASR Rd 0<=d<=31
+ * 1001 010d dddd 0101
+ *____________________________________________________________________________
+ */
+
+int
+cl_avr::asr_Rd(t_mem code)
+{
+  t_addr d;
+  t_mem D, result, res;
+
+  d= (code&0x1f0)>>4;
+  D= ram->read(d);
+  t_mem sreg= ram->read(SREG) & ~(BIT_S|BIT_V|BIT_N|BIT_Z|BIT_C);
+  int n=0, v= 0, c= 0;
+  if (D & 1)
+    {
+      sreg|= BIT_C;
+      c= 1;
+    }
+  result= D>>1;
+  if (result & 0x40)
+    result|= 0x80;
+  res= result & 0xff;
+  ram->write(d, res);
+  if (res & 0x80)
+    {
+      sreg|= BIT_N;
+      n= 1;
+    }
+  if ((n ^ c) & 1)
+    {
+      sreg|= BIT_V;
+      v= 1;
+    }
+  if ((n ^ v) & 1)
+    sreg|= BIT_S;
+  if (!res)
+    sreg|= BIT_Z;
+  ram->write(SREG, sreg);
+  return(resGO);
+}
+
+
+/*
+ * Logical Shift Right
+ * LSR Rd 0<=d<=31
+ * 1001 010d dddd 0110
+ *____________________________________________________________________________
+ */
+
+int
+cl_avr::lsr_Rd(t_mem code)
+{
+  t_addr d;
+  t_mem D, result, res;
+
+  d= (code &0x1f0)>>4;
+  D= ram->read(d);
+  t_mem sreg= ram->read(SREG) & ~(BIT_S|BIT_V|BIT_N|BIT_Z|BIT_C);
+  if (D & 1)
+    sreg|= (BIT_C|BIT_V|BIT_S);
+  result= D >> 1;
+  res= result & 0xff;
+  ram->write(d, res);
+  if (!res)
+    sreg|= BIT_Z;
+  ram->write(SREG, sreg);
+  return(resGO);
+}
+
+
+/*
+ * Rotate Right trough Carry
+ * ROR Rd 0<=d<=31
+ * 1001 010d dddd 0111
+ *____________________________________________________________________________
+ */
+
+int
+cl_avr::ror_Rd(t_mem code)
+{
+  t_addr d;
+  t_mem D, result, res;
+
+  d= (code&0x1f0)>>4;
+  D= ram->read(d);
+  t_mem sreg= ram->read(SREG);
+  int oldc= sreg & BIT_C;
+  sreg= sreg & ~(BIT_S|BIT_V|BIT_N|BIT_Z|BIT_C);
+  int n= 0, v= 0, c= 0;
+  if (D & 1)
+    {
+      sreg|= BIT_C;
+      c= 1;
+    }
+  result= (D >> 1) | oldc?0x80:0;
+  res= result & 0xff;
+  ram->write(d, res);
+  if (res & 0x80)
+    {
+      sreg|= BIT_N;
+      n= 1;
+    }
+  if ((n ^ c) & 1)
+    {
+      sreg|= BIT_V;
+      v= 1;
+    }
+  if ((n ^ v) & 1)
+    sreg|= BIT_S;
+  if (!res)
+    sreg|= BIT_Z;
+  ram->write(SREG, sreg);
+  return(resGO);
+}
+
+
+/*
+ * Decrement
+ * DEC Rd 0<=d<=31
+ * 1001 010d dddd 1010
+ *____________________________________________________________________________
+ */
+
+int
+cl_avr::dec_Rd(t_mem code)
+{
+  t_addr d;
+  t_mem D, result, res;
+
+  d= (code&0x1f0)>>4;
+  D= ram->read(d);
+  result= D-1;
+  res= result & 0xff;
+  ram->write(d, res);
+
+  t_mem sreg= ram->get(SREG);
+  if (!res)
+    sreg|= BIT_Z;
+  else
+    sreg&= ~BIT_Z;
+  int n= 0, v= 0;
+  if (res & 0x80)
+    {
+      sreg|= BIT_N;
+      n= 1;
+    }
+  else
+    sreg&= ~BIT_N;
+  if (D == 0x80)
+    {
+      sreg|= BIT_V;
+      v= 1;
+    }
+  else
+    sreg&= ~BIT_V;
+  if ((n ^ v) & 1)
+    sreg|= BIT_S;
+  else
+    sreg&= ~BIT_S;
+  ram->set(SREG, sreg);
+
+  return(resGO);
+}
+
+
+/*
+ * Multiply
+ * MUL Rd,Rr 0<=d<=31, 0<=r<=31
+ * 1001 11rd dddd rrrr
+ *____________________________________________________________________________
+ */
+
+int
+cl_avr::mul_Rd_Rr(t_mem code)
+{
+  t_addr d, r;
+  t_mem D, R, result, resl, resh;
+
+  d= (code>>4) & 0x1f;
+  r= ((code&0x200)>>5) | (code&0xf);
+  D= ram->read(d);
+  R= ram->read(r);
+  result= R*D;
+  resl= result & 0xff;
+  resh= (result>>8) & 0xff;
+  ram->write(0, resl);
+  ram->write(1, resh);
+  t_mem sreg= ram->read(SREG) & ~BIT_C;
+  if (resh & 0x80)
+    sreg|= BIT_C;
+  ram->write(SREG, sreg);
+  tick(1);
+  return(resGO);
+}
+
+
+/*
+ * Add Immediate to Word
+ * ADIW Rdl,K dl={24,26,28,30}, 0<=K<=63
+ * 1001 0110 KK dd KKKK
+ *____________________________________________________________________________
+ */
+
+int
+cl_avr::adiw_Rdl_K(t_mem code)
+{
+  t_addr dl;
+  t_mem D, K, result, res;
+
+  dl= 24+(2*((code&0x30)>>4));
+  K= ((code&0xc0)>>2)|(code&0xf);
+  D= ram->read(dl+1)*256 + ram->read(dl);
+  result= D+K;
+  res= result & 0xffff;
+  t_mem resl= result&0xff, resh= (result>>8)&0xff;
+  ram->write(dl+1, resh);
+  ram->write(dl, resl);
+  
+  t_mem sreg= ram->get(SREG);
+  if (!res)
+    sreg|= BIT_Z;
+  else
+    sreg&= ~BIT_Z;
+  if (D&res&0x8000)
+    sreg|= (BIT_V|BIT_S);
+  else
+    sreg&= ~(BIT_V|BIT_S);
+  if (res & 0x8000)
+    {
+      sreg|= BIT_N;
+      sreg^= BIT_S;
+    }
+  else
+    sreg&= ~BIT_N;
+  if ((~res)&D&0x8000)
+    sreg|= BIT_C;
+  else
+    sreg&= ~BIT_C;
+  ram->set(SREG, sreg);
+  tick(1);
+
+  return(resGO);
+}
+
+
+/*
+ * Substract Immediate from Word
+ * SBIW Rdl,K dl={24,26,28,30}, 0<=K<=63
+ * 1001 0111 KK dd KKKK
+ *____________________________________________________________________________
+ */
+
+int
+cl_avr::sbiw_Rdl_K(t_mem code)
+{
+  t_addr dl;
+  t_mem D, K, result, res;
+
+  dl= 24+(2*((code&0x30)>>4));
+  K= ((code&0xc0)>>2)|(code&0xf);
+  D= ram->read(dl+1)*256 + ram->read(dl);
+  if (K & 0x20)
+    K|= ~0x3f;
+  if (D & 0x8000)
+    D|= ~0xffff;
+  result= (signed)D-(signed)K;
+  res= result & 0xffff;
+  t_mem resl= res&0xff, resh= (res>>8)&0xff;
+  ram->write(dl+1, resh);
+  ram->write(dl, resl);
+
+  t_mem sreg= ram->get(SREG) & ~(BIT_S|BIT_V|BIT_N|BIT_Z|BIT_C);
+  int n= 0, v= 0;
+  if (0x8000 & D & (~res))
+    {
+      sreg|= BIT_V;
+      v= 1;
+    }
+  if (res & 0x8000)
+    {
+      sreg|= BIT_N;
+      n= 1;
+    }
+  if ((n ^ v) & 1)
+    sreg|= BIT_S;
+  if (!res)
+    sreg|= BIT_Z;
+  if (0x8000 & res & (~D))
+    sreg|= BIT_C;
+  ram->set(SREG, sreg);
+  tick(1);
+
+  return(resGO);
+}
+
+
+/* End of avr.src/arith_inst.cc */
diff --git a/sim/ucsim/avr.src/avr.cc b/sim/ucsim/avr.src/avr.cc
new file mode 100644
index 0000000..44912a7
--- /dev/null
+++ b/sim/ucsim/avr.src/avr.cc
@@ -0,0 +1,793 @@
+/*
+ * Simulator of microcontrollers (avr.cc)
+ *
+ * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
+ *
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#include "ddconfig.h"
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <ctype.h>
+#include "i_string.h"
+
+// prj
+#include "pobjcl.h"
+
+// sim
+#include "simcl.h"
+#include "memcl.h"
+
+// local
+#include "portcl.h"
+#include "avrcl.h"
+#include "glob.h"
+#include "regsavr.h"
+
+
+// Addresses are IRAM addresses!
+static struct name_entry sfr_tabl[]= {
+  { CPU_ALL_AVR, 0x001a, "XL"},
+  { CPU_ALL_AVR, 0x001a, "XL" },
+  { CPU_ALL_AVR, 0x001b, "XH" },
+  { CPU_ALL_AVR, 0x001c, "YL" },
+  { CPU_ALL_AVR, 0x001d, "YH" },
+  { CPU_ALL_AVR, 0x001e, "ZL" },
+  { CPU_ALL_AVR, 0x001f, "ZH" },
+  { CPU_ALL_AVR, 0x0024, "ADCL" },
+  { CPU_ALL_AVR, 0x0025, "ADCH" },
+  { CPU_ALL_AVR, 0x0026, "ADCSR" },
+  { CPU_ALL_AVR, 0x0027, "ADMUX" },
+  { CPU_ALL_AVR, 0x0028, "ACSR" },
+  { CPU_ALL_AVR, 0x0029, "UBRR" },
+  { CPU_ALL_AVR, 0x002A, "UCR" },
+  { CPU_ALL_AVR, 0x002B, "USR" },
+  { CPU_ALL_AVR, 0x002C, "UDR" },
+  { CPU_ALL_AVR, 0x002D, "SPCR" },
+  { CPU_ALL_AVR, 0x002E, "SPSR" },
+  { CPU_ALL_AVR, 0x002F, "SPDR" },
+  { CPU_ALL_AVR, 0x0030, "PIND" },
+  { CPU_ALL_AVR, 0x0031, "DDRD" },
+  { CPU_ALL_AVR, 0x0032, "PORTD" },
+  { CPU_ALL_AVR, 0x0033, "PINC" },
+  { CPU_ALL_AVR, 0x0034, "DDRC" },
+  { CPU_ALL_AVR, 0x0035, "PORTC" },
+  { CPU_ALL_AVR, 0x0036, "PINB" },
+  { CPU_ALL_AVR, 0x0037, "DDRB" },
+  { CPU_ALL_AVR, 0x0038, "PORTB" },
+  { CPU_ALL_AVR, 0x0039, "PINA" },
+  { CPU_ALL_AVR, 0x003A, "DDRA" },
+  { CPU_ALL_AVR, 0x003B, "PORTA" },
+  { CPU_ALL_AVR, 0x003C, "EECR" },
+  { CPU_ALL_AVR, 0x003D, "EEDR" },
+  { CPU_ALL_AVR, 0x003E, "EEARL" },
+  { CPU_ALL_AVR, 0x003E, "EEARH" },
+  { CPU_ALL_AVR, 0x0041, "WDTCR" },
+  { CPU_ALL_AVR, 0x0042, "ASSR" },
+  { CPU_ALL_AVR, 0x0043, "OCR2" },
+  { CPU_ALL_AVR, 0x0044, "TCNT2" },
+  { CPU_ALL_AVR, 0x0045, "TCCR2" },
+  { CPU_ALL_AVR, 0x0046, "ICR1L" },
+  { CPU_ALL_AVR, 0x0047, "ICR1H" },
+  { CPU_ALL_AVR, 0x0048, "OCR1BL" },
+  { CPU_ALL_AVR, 0x0049, "OCR1BH" },
+  { CPU_ALL_AVR, 0x004A, "OCR1AL" },
+  { CPU_ALL_AVR, 0x004B, "OCR1AH" },
+  { CPU_ALL_AVR, 0x004C, "TCNT1L" },
+  { CPU_ALL_AVR, 0x004D, "TCNT1H" },
+  { CPU_ALL_AVR, 0x004E, "TCCR1B" },
+  { CPU_ALL_AVR, 0x004F, "TCCR1A" },
+  { CPU_ALL_AVR, 0x0052, "TCNT0" },
+  { CPU_ALL_AVR, 0x0053, "TCCR0" },
+  { CPU_ALL_AVR, 0x0054, "MCUSR" },
+  { CPU_ALL_AVR, 0x0055, "MCUCR" },
+  { CPU_ALL_AVR, 0x0058, "TIFR" },
+  { CPU_ALL_AVR, 0x0059, "TIMSK" },
+  { CPU_ALL_AVR, 0x005A, "GIFR" },
+  { CPU_ALL_AVR, 0x005B, "GIMSK" },
+  { CPU_ALL_AVR, 0x005D, "SPL" },
+  { CPU_ALL_AVR, 0x005E, "SPH" },
+  { CPU_ALL_AVR, 0x005F, "SREG" },
+  {0, 0, NULL}
+};
+
+/*
+ * Base type of AVR microcontrollers
+ */
+
+cl_avr::cl_avr(class cl_sim *asim):
+  cl_uc(asim)
+{
+  type= (struct cpu_entry *)malloc(sizeof(struct cpu_entry));
+  type->type= CPU_AVR;
+  sleep_executed= 0;
+}
+
+int
+cl_avr::init(void)
+{
+  cl_uc::init(); /* Memories now exist */
+  int i;
+  for (i= 0; sfr_tabl[i].name != NULL; i++)
+    {
+      if (type->type & sfr_tabl[i].cpu_type)
+	{
+	  class cl_var *v;
+	  vars->add(v= new cl_var(chars(sfr_tabl[i].name),
+				  ram,
+				  sfr_tabl[i].addr, ""));
+	  v->init();
+	}
+    }
+  return(0);
+}
+
+char *
+cl_avr::id_string(void)
+{
+  return((char*)"unspecified AVR");
+}
+
+
+/*
+ * Making elements of the controller
+ */
+
+void
+cl_avr::mk_hw_elements(void)
+{
+  class cl_hw *h;
+  cl_uc::mk_hw_elements();
+  add_hw(h= new cl_port(this));
+  h->init();
+}
+
+
+void
+cl_avr::make_memories(void)
+{
+  class cl_address_space *as;
+
+  rom= as= new cl_address_space("rom"/*MEM_ROM_ID*/, 0, 0x10000, 16);
+  as->init();
+  address_spaces->add(as);
+  ram= as= new cl_address_space(MEM_IRAM_ID, 0, 0x10000, 8);
+  as->init();
+  address_spaces->add(as);
+
+  class cl_address_decoder *ad;
+  class cl_memory_chip *chip;
+
+  chip= new cl_memory_chip("rom_chip", 0x10000, 16);
+  chip->init();
+  memchips->add(chip);
+  ad= new cl_address_decoder(as= rom/*address_space(MEM_ROM_ID)*/,
+			     chip, 0, 0xffff, 0);
+  ad->init();
+  as->decoders->add(ad);
+  ad->activate(0);
+
+  chip= new cl_memory_chip("iram_chip", 0x80, 8);
+  chip->init();
+  memchips->add(chip);
+  ad= new cl_address_decoder(as= ram/*address_space(MEM_IRAM_ID)*/,
+			     chip, 0, 0x7f, 0);
+  ad->init();
+  as->decoders->add(ad);
+  ad->activate(0);
+}
+
+
+/*
+ * Help command interpreter
+ */
+
+struct dis_entry *
+cl_avr::dis_tbl(void)
+{
+  return(disass_avr);
+}
+
+char *
+cl_avr::disass(t_addr addr, const char *sep)
+{
+  char work[256], temp[20];
+  char *buf, *p, *t, *s;
+  const char *b;
+  uint code, data= 0;
+  int i;
+
+  p= work;
+
+  code= rom/*get_mem*/->get(/*MEM_ROM_ID,*/ addr);
+  i= 0;
+  while ((code & dis_tbl()[i].mask) != dis_tbl()[i].code &&
+	 dis_tbl()[i].mnemonic)
+    i++;
+  if (dis_tbl()[i].mnemonic == NULL)
+    {
+      buf= (char*)malloc(30);
+      strcpy(buf, "UNKNOWN/INVALID");
+      return(buf);
+    }
+  b= dis_tbl()[i].mnemonic;
+
+  while (*b)
+    {
+      if (*b == '%')
+	{
+	  b++;
+	  switch (*(b++))
+	    {
+	    case 'd': // Rd   .... ...d dddd ....  0<=d<=31
+	      if (!/*get*/addr_name(data= (code&0x01f0)>>4, /*sfr_tbl()*/ram, temp))
+		sprintf(temp, "r%d", data);
+	      break;
+	    case 'D': // Rd   .... .... dddd ....  16<=d<=31
+	      if (!/*get*/addr_name(data= 16+((code&0xf0)>>4), /*sfr_tbl()*/ram, temp))
+		sprintf(temp, "r%d", data);
+	      break;
+	    case 'K': // K    .... KKKK .... KKKK  0<=K<=255
+	      sprintf(temp, "%d", ((code&0xf00)>>4)|(code&0xf));
+	      break;
+	    case 'r': // Rr   .... ..r. .... rrrr  0<=r<=31
+	      if (!/*get*/addr_name(data= ((code&0x0200)>>5)|(code&0x000f),
+				    /*sfr_tbl()*/ram, temp))
+		sprintf(temp, "r%d", data);
+	      break;
+	    case '2': // Rdl  .... .... ..dd ....  dl= {24,26,28,30}
+	      if (!/*get*/addr_name(data= 24+(2*((code&0x0030)>>4)),
+				    /*sfr_tbl()*/ram, temp))
+		sprintf(temp, "r%d", data);
+	      break;
+	    case '6': // K    .... .... KK.. KKKK  0<=K<=63
+	      sprintf(temp, "%d", ((code&0xc0)>>2)|(code&0xf));
+	      break;
+	    case 's': // s    .... .... .sss ....  0<=s<=7
+	      sprintf(temp, "%d", (code&0x70)>>4);
+	      break;
+	    case 'b': // b    .... .... .... .bbb  0<=b<=7
+	      sprintf(temp, "%d", code&0x7);
+	      break;
+	    case 'k': // k    .... ..kk kkkk k...  -64<=k<=+63
+	      {
+		int k= (code&0x3f8)>>3;
+		if (code&0x200)
+		  k|= -128;
+		sprintf(temp, "0x%06x", k+1+(signed int)addr);
+		break;
+	      }
+	    case 'A': // k    .... ...k kkkk ...k  0<=k<=64K
+	              //      kkkk kkkk kkkk kkkk  0<=k<=4M
+	      sprintf(temp, "0x%06x",
+		      (((code&0x1f0)>>3)|(code&1))*0x10000+
+		      (uint)rom->get/*_mem*/(/*MEM_ROM_ID,*/ addr+1));
+	      break;
+	    case 'P': // P    .... .... pppp p...  0<=P<=31
+	      data= (code&0xf8)>>3;
+	      if (!/*get*/addr_name(data+0x20, /*sfr_tbl()*/ram, temp))
+		sprintf(temp, "%d", data);
+	      break;
+	    case 'p': // P    .... .PP. .... PPPP  0<=P<=63
+	      data= ((code&0x600)>>5)|(code&0xf);
+	      if (!/*get*/addr_name(data+0x20, /*sfr_tbl()*/ram, temp))
+		sprintf(temp, "%d", data);
+	      break;
+	    case 'q': // q    ..q. qq.. .... .qqq  0<=q<=63
+	      sprintf(temp, "%d",
+		      ((code&0x2000)>>8)|((code&0xc00)>>7)|(code&7));
+	      break;
+	    case 'R': // k    SRAM address on second word 0<=k<=65535
+	      sprintf(temp, "0x%06x", (uint)rom->get/*_mem*/(/*MEM_ROM_ID,*/ addr+1));
+	      break;
+	    case 'a': // k    .... kkkk kkkk kkkk  -2k<=k<=2k
+	      {
+		int k= code&0xfff;
+		if (code&0x800)
+		  k|= -4096;
+		sprintf(temp, "0x%06x",
+			(int)rom->validate_address(k+1+(signed int)addr));
+		break;
+	      }
+	    default:
+	      strcpy(temp, "?");
+	      break;
+	    }
+	  t= temp;
+	  while (*t)
+	    *(p++)= *(t++);
+	}
+      else
+	*(p++)= *(b++);
+    }
+  *p= '\0';
+
+  p= strchr(work, ' ');
+  if (!p)
+    {
+      buf= strdup(work);
+      return(buf);
+    }
+  if (sep == NULL)
+    buf= (char *)malloc(6+strlen(p)+1);
+  else
+    buf= (char *)malloc((p-work)+strlen(sep)+strlen(p)+1);
+  for (p= work, s= buf; *p != ' '; p++, s++)
+    *s= *p;
+  p++;
+  *s= '\0';
+  if (sep == NULL)
+    {
+      while (strlen(buf) < 6)
+	strcat(buf, " ");
+    }
+  else
+    strcat(buf, sep);
+  strcat(buf, p);
+  return(buf);
+}
+
+
+void
+cl_avr::print_regs(class cl_console_base *con)
+{
+  uchar data, sreg= ram->get(SREG);
+  uint x, y, z;
+
+  ram->dump(0, 31, 16, con/*->get_fout()*/);
+
+  con->dd_color("answer");
+  con->dd_printf("ITHSVNZC  SREG= 0x%02x %3d %c\n",
+		 sreg, sreg, isprint(sreg)?sreg:'.');
+  con->dd_printf("%c%c%c%c%c%c%c%c  ",
+		 (sreg&BIT_I)?'1':'0',
+		 (sreg&BIT_T)?'1':'0',
+		 (sreg&BIT_H)?'1':'0',
+		 (sreg&BIT_S)?'1':'0',
+		 (sreg&BIT_V)?'1':'0',
+		 (sreg&BIT_N)?'1':'0',
+		 (sreg&BIT_Z)?'1':'0',
+		 (sreg&BIT_C)?'1':'0');
+  con->dd_printf("SP  = 0x%06x\n", ram->get(SPH)*256+ram->get(SPL));
+
+  x= ram->get(XH)*256 + ram->get(XL);
+  data= ram->get(x);
+  con->dd_printf("X= 0x%04x [X]= 0x%02x %3d %c  ", x,
+		 data, data, isprint(data)?data:'.');
+  y= ram->get(YH)*256 + ram->get(YL);
+  data= ram->get(y);
+  con->dd_printf("Y= 0x%04x [Y]= 0x%02x %3d %c  ", y,
+		 data, data, isprint(data)?data:'.');
+  z= ram->get(ZH)*256 + ram->get(ZL);
+  data= ram->get(z);
+  con->dd_printf("Z= 0x%04x [Z]= 0x%02x %3d %c\n", z,
+		 data, data, isprint(data)?data:'.');
+
+  print_disass(PC, con);
+}
+
+
+/*
+ * Execution
+ */
+
+int
+cl_avr::exec_inst(void)
+{
+  t_mem code;
+
+  instPC= PC;
+  if (fetch(&code))
+    return(resBREAKPOINT);
+  tick(1);
+  switch (code)
+    {
+    case 0x9419:
+      return(eijmp(code));
+    case 0x9519:
+      return(eicall(code));
+    case 0x9508: case 0x9528: case 0x9548: case 0x9568:
+      return(ret(code));
+    case 0x9518: case 0x9538: case 0x9558: case 0x9578:
+      return(reti(code));
+    case 0x95c8:
+      return(lpm(code));
+    case 0x95d8:
+      return(elpm(code)); // in some devices equal to lpm
+    case 0x95e8:
+      return(spm(code));
+    case 0x95f8:
+      return(espm(code));
+    case 0x9408:
+      return(sec(code));
+    case 0x9488:
+      return(clc(code));
+    case 0x9428:
+      return(sen(code));
+    case 0x94a8:
+      return(cln(code));
+    case 0x9418:
+      return(sez(code));
+    case 0x9498:
+      return(clz(code));
+    case 0x9478:
+     return(sei(code));
+    case 0x94f8:
+      return(cli(code));
+    case 0x9448:
+      return(ses(code));
+    case 0x94c8:
+      return(cls(code));
+    case 0x9438:
+      return(sev(code));
+    case 0x94b8:
+      return(clv(code));
+    case 0x9468:
+      return(set(code));
+    case 0x94e8:
+      return(clt(code));
+    case 0x9458:
+      return(seh(code));
+    case 0x94d8:
+      return(clh(code));
+    case 0x0000:
+      return(nop(code));
+    case 0x9588: case 0x9598:
+      return(sleep(code));
+    case 0x95a8: case 0x95b8:
+      return(wdr(code));
+    }
+  switch (code & 0xf000)
+    {
+    case 0x3000: return(cpi_Rd_K(code));
+    case 0x4000: return(sbci_Rd_K(code));
+    case 0x5000: return(subi_Rd_K(code));
+    case 0x6000: return(ori_Rd_K(code));
+    case 0x7000: return(andi_Rd_K(code));
+    case 0xc000: return(rjmp_k(code));
+    case 0xd000: return(rcall_k(code));
+    case 0xe000: return(ldi_Rd_K(code));
+    }
+  switch (code & 0xf000)
+    {
+    case 0x0000:
+      {
+	// 0x0...
+	switch (code & 0xfc00)
+	  {
+	  case 0x0000:
+	    {
+	      switch (code & 0xff00)
+		{
+		case 0x0100: return(movw_Rd_Rr(code));
+		case 0x0200: return(muls_Rd_Rr(code));
+		case 0x0300:
+		  {
+		    switch (code & 0xff88)
+		      {
+		      case 0x0300: return(mulsu_Rd_Rr(code));
+		      case 0x0308: return(fmul_Rd_Rr(code));
+		      case 0x0380: return(fmuls_Rd_Rr(code));
+		      case 0x0388: return(fmulsu_Rd_Rr(code));
+		      }
+		    break;
+		  }
+		  break;
+		}
+	      break;
+	    }
+	  case 0x0400: return(cpc_Rd_Rr(code));
+	  case 0x0800: return(sbc_Rd_Rr(code));
+	  case 0x0c00: return(add_Rd_Rr(code));
+	  }
+	break;
+      }
+    case 0x1000:
+      {
+	// 0x1...
+	switch (code & 0xfc00)
+	  {
+	  case 0x1000: return(cpse_Rd_Rr(code));
+	  case 0x1400: return(cp_Rd_Rr(code));
+	  case 0x1800: return(sub_Rd_Rr(code));
+	  case 0x1c00: return(adc_Rd_Rr(code));
+	  }
+	break;
+      }
+    case 0x2000:
+      {
+	// 0x2...
+	switch (code & 0xfc00)
+	  {
+	  case 0x2000: return(and_Rd_Rr(code));
+	  case 0x2400: return(eor_Rd_Rr(code));
+	  case 0x2800: return(or_Rd_Rr(code));
+	  case 0x2c00: return(mov_Rd_Rr(code));
+	}
+	break;
+      }
+    case 0x8000:
+      {
+	// 0x8...
+	switch (code &0xf208)
+	  {
+	  case 0x8000: return(ldd_Rd_Z_q(code));
+	  case 0x8008: return(ldd_Rd_Y_q(code));
+	  case 0x8200: return(std_Z_q_Rr(code));
+	  case 0x8208: return(std_Y_q_Rr(code));
+	  }
+	break;
+      }
+    case 0x9000:
+      {
+	// 0x9...
+	if ((code & 0xff0f) == 0x9509)
+	  return(icall(code));
+	if ((code & 0xff0f) == 0x9409)
+	  return(ijmp(code));
+	if ((code & 0xff00) == 0x9600)
+	  return(adiw_Rdl_K(code));
+	if ((code & 0xff00) == 0x9700)
+	  return(sbiw_Rdl_K(code));
+	switch (code & 0xfc00)
+	  {
+	  case 0x9000:
+	    {
+	      switch (code & 0xfe0f)
+		{
+		case 0x9000: return(lds_Rd_k(code));
+		case 0x9001: return(ld_Rd_ZS(code));
+		case 0x9002: return(ld_Rd_SZ(code));
+		case 0x9004: return(lpm_Rd_Z(code));
+		case 0x9005: return(lpm_Rd_ZS(code));
+		case 0x9006: return(elpm_Rd_Z(code));
+		case 0x9007: return(elpm_Rd_ZS(code));
+		case 0x9009: return(ld_Rd_YS(code));
+		case 0x900a: return(ld_Rd_SY(code));
+		case 0x900c: return(ld_Rd_X(code));
+		case 0x900d: return(ld_Rd_XS(code));
+		case 0x900e: return(ld_Rd_SX(code));
+		case 0x900f: return(pop_Rd(code));
+		case 0x9200: return(sts_k_Rr(code));
+		case 0x9201: return(st_ZS_Rr(code));
+		case 0x9202: return(st_SZ_Rr(code));
+		case 0x9209: return(st_YS_Rr(code));
+		case 0x920a: return(st_SY_Rr(code));
+		case 0x920c: return(st_X_Rr(code));
+		case 0x920d: return(st_XS_Rr(code));
+		case 0x920e: return(st_SX_Rr(code));
+		case 0x920f: return(push_Rr(code));
+		}
+	      break;
+	    }
+	  case 0x9400:
+	    {
+	      switch (code & 0xfe0f)
+		{
+		case 0x9400: return(com_Rd(code));
+		case 0x9401: return(neg_Rd(code));
+		case 0x9402: return(swap_Rd(code));
+		case 0x9403: return(inc_Rd(code));
+		case 0x9405: return(asr_Rd(code));
+		case 0x9406: return(lsr_Rd(code));
+		case 0x9407: return(ror_Rd(code));
+		case 0x940a: return(dec_Rd(code));
+		case 0x940c: case 0x940d: return(jmp_k(code));
+		case 0x940e: case 0x940f: return(call_k(code));
+		}
+	      break;
+	    }
+	  case 0x9800:
+	    {
+	      switch (code & 0xff00)
+		{
+		case 0x9800: return(cbi_A_b(code));
+		case 0x9900: return(sbic_P_b(code));
+		case 0x9a00: return(sbi_A_b(code));
+		case 0x9b00: return(sbis_P_b(code));
+		}
+	      break;
+	    }
+	  case 0x9c00: return(mul_Rd_Rr(code));
+	  }
+	break;
+      }
+    case 0xa000:
+      {
+	// 0xa...
+	switch (code &0xf208)
+	  {
+	  case 0xa000: return(ldd_Rd_Z_q(code));
+	  case 0xa008: return(ldd_Rd_Y_q(code));
+	  case 0xa200: return(std_Z_q_Rr(code));
+	  case 0xa208: return(std_Y_q_Rr(code));
+	  }
+	break;
+      }
+    case 0xb000:
+      {
+	// 0xb...
+	switch (code & 0xf800)
+	  {
+	  case 0xb000: return(in_Rd_A(code));
+	  case 0xb800: return(out_A_Rr(code));
+	  }
+	break;
+      }
+    case 0xe000:
+      {
+	// 0xe...
+	switch (code & 0xff0f)
+	  {
+	  case 0xef0f: return(ser_Rd(code));
+	  }
+	break;
+      }
+    case 0xf000:
+      {
+	// 0xf...
+	switch (code & 0xfc00)
+	  {
+	  case 0xf000: return(brbs_s_k(code));
+	  case 0xf400: return(brbc_s_k(code));
+	  case 0xf800: case 0xfc00:
+	    {
+	      switch (code & 0xfe08)
+		{
+		case 0xf800: return(bld_Rd_b(code));
+		case 0xfa00: return(bst_Rd_b(code));
+		case 0xfc00: case 0xfc08: return(sbrc_Rr_b(code));
+		case 0xfe00: case 0xfe08: return(sbrs_Rr_b(code));
+		}
+	      break;
+	    }
+	  }
+	break;
+      }
+    }
+  /*if (PC)
+    PC--;
+  else
+  PC= get_mem_size(MEM_ROM_ID)-1;*/
+  class cl_error_unknown_code *e= new cl_error_unknown_code(this);
+  error(e);
+  return(resGO);
+  PC= rom->inc_address(PC, -1);
+  //tick(-clock_per_cycle());
+  sim->stop(resINV_INST);
+  return(resINV_INST);
+}
+
+
+/*
+ */
+
+int
+cl_avr::push_data(t_mem data)
+{
+  t_addr sp;
+  t_mem spl, sph;
+
+  spl= ram->read(SPL);
+  sph= ram->read(SPH);
+  sp= 0xffff & (256*sph + spl);
+  data= ram->write(sp, data);
+  vc.wr++;
+  sp= 0xffff & (sp-1);
+  spl= sp & 0xff;
+  sph= (sp>>8) & 0xff;
+  ram->write(SPL, spl);
+  ram->write(SPH, sph);
+  return(resGO);
+}
+
+int
+cl_avr::push_addr(t_addr addr)
+{
+  t_addr sp;
+  t_mem spl, sph, al, ah;
+
+  spl= ram->read(SPL);
+  sph= ram->read(SPH);
+  sp= 0xffff & (256*sph + spl);
+  al= addr & 0xff;
+  ah= (addr>>8) & 0xff;
+  ram->write(sp, ah);
+  sp= 0xffff & (sp-1);
+  ram->write(sp, al);
+  vc.wr+= 2;
+  sp= 0xffff & (sp-1);
+  spl= sp & 0xff;
+  sph= (sp>>8) & 0xff;
+  ram->write(SPL, spl);
+  ram->write(SPH, sph);
+  return(resGO);
+}
+
+int
+cl_avr::pop_data(t_mem *data)
+{
+  t_addr sp;
+  t_mem spl, sph;
+
+  spl= ram->read(SPL);
+  sph= ram->read(SPH);
+  sp= 256*sph + spl;
+  sp= 0xffff & (sp+1);
+  *data= ram->read(sp);
+  vc.rd++;
+  spl= sp & 0xff;
+  sph= (sp>>8) & 0xff;
+  ram->write(SPL, spl);
+  ram->write(SPH, sph);
+
+  return(resGO);
+}
+
+int
+cl_avr::pop_addr(t_addr *addr)
+{
+  t_addr sp;
+  t_mem spl, sph, al, ah;
+
+  spl= ram->read(SPL);
+  sph= ram->read(SPH);
+  sp= 256*sph + spl;
+  sp= 0xffff & (sp+1);
+  al= ram->read(sp);
+  sp= 0xffff & (sp+1);
+  ah= ram->read(sp);
+  vc.rd+= 2;
+  *addr= ah*256 + al;
+  spl= sp & 0xff;
+  sph= (sp>>8) & 0xff;
+  ram->write(SPL, spl);
+  ram->write(SPH, sph);
+
+  return(resGO);
+}
+
+
+/*
+ * Set Z, N, V, S bits of SREG after logic instructions and some others
+ */
+
+void
+cl_avr::set_zn0s(t_mem data)
+{
+  t_mem sreg= ram->get(SREG) & ~BIT_V;
+  data= data&0xff;
+  if (!data)
+    sreg|= BIT_Z;
+  else
+    sreg&= ~BIT_Z;
+  if (data & 0x80)
+    sreg|= (BIT_N|BIT_S);
+  else
+    sreg&= ~(BIT_N|BIT_S);
+  ram->set(SREG, sreg);
+}
+
+
+/* End of avr.src/avr.cc */
diff --git a/sim/ucsim/avr.src/avrcl.h b/sim/ucsim/avr.src/avrcl.h
new file mode 100644
index 0000000..8ddecc0
--- /dev/null
+++ b/sim/ucsim/avr.src/avrcl.h
@@ -0,0 +1,81 @@
+/*
+ * Simulator of microcontrollers (avrcl.h)
+ *
+ * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
+ *
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#ifndef AVRCL_HEADER
+#define AVRCL_HEADER
+
+// sim.src
+#include "uccl.h"
+#include "memcl.h"
+
+
+/*
+ * Base type of AVR microcontrollers
+ */
+
+class cl_avr: public cl_uc
+{
+public:
+  class cl_address_space *ram;
+  class cl_address_space *rom;
+  int sleep_executed;
+public:
+  cl_avr(class cl_sim *asim);
+  virtual int init(void);
+  virtual char *id_string(void);
+
+  //virtual t_addr get_mem_size(enum mem_class type);
+  //virtual int get_mem_width(enum mem_class type);
+  virtual void mk_hw_elements(void);
+  virtual void make_memories(void);
+
+  virtual struct dis_entry *dis_tbl(void);
+  //virtual struct name_entry *sfr_tbl(void);
+  //virtual struct name_entry *bit_tbl(void);
+  virtual char *disass(t_addr addr, const char *sep);
+  virtual void print_regs(class cl_console_base *con);
+
+  virtual int exec_inst(void);
+
+  virtual int push_data(t_mem data);
+  virtual int push_addr(t_addr addr);
+  virtual int pop_data(t_mem *data);
+  virtual int pop_addr(t_addr *addr);
+
+  void set_zn0s(t_mem data);
+#include "arith_cl.h"
+#include "logic_cl.h"
+#include "move_cl.h"
+#include "bit_cl.h"
+#include "jump_cl.h"
+#include "instcl.h"
+};
+
+
+#endif
+
+/* End of avr.src/avrcl.h */
diff --git a/sim/ucsim/avr.src/bit_cl.h b/sim/ucsim/avr.src/bit_cl.h
new file mode 100644
index 0000000..65ab343
--- /dev/null
+++ b/sim/ucsim/avr.src/bit_cl.h
@@ -0,0 +1,24 @@
+/* avr.src/bit_cl.h */
+
+  virtual int sec(t_mem code);
+  virtual int clc(t_mem code);
+  virtual int sen(t_mem code);
+  virtual int cln(t_mem code);
+  virtual int sez(t_mem code);
+  virtual int clz(t_mem code);
+  virtual int sei(t_mem code);
+  virtual int cli(t_mem code);
+  virtual int ses(t_mem code);
+  virtual int cls(t_mem code);
+  virtual int sev(t_mem code);
+  virtual int clv(t_mem code);
+  virtual int set(t_mem code);
+  virtual int clt(t_mem code);
+  virtual int seh(t_mem code);
+  virtual int clh(t_mem code);
+  virtual int cbi_A_b(t_mem code);
+  virtual int sbi_A_b(t_mem code);
+  virtual int bld_Rd_b(t_mem code);
+  virtual int bst_Rd_b(t_mem code);
+
+/* End of avr.src/bit_cl.h */
diff --git a/sim/ucsim/avr.src/bit_inst.cc b/sim/ucsim/avr.src/bit_inst.cc
new file mode 100644
index 0000000..e0f27cc
--- /dev/null
+++ b/sim/ucsim/avr.src/bit_inst.cc
@@ -0,0 +1,389 @@
+/*
+ * Simulator of microcontrollers (bit_inst.cc)
+ *
+ * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+// local
+#include "avrcl.h"
+#include "regsavr.h"
+
+
+/*
+ * Set Carry Flag
+ * SEC
+ * 1001 0100 0000 1000
+ *----------------------------------------------------------------------------
+ */
+
+int
+cl_avr::sec(t_mem code)
+{
+  t_mem d= BIT_C | ram->read(SREG);
+  ram->write(SREG, d);
+  return(resGO);
+}
+
+
+/*
+ * Set Negative Flag
+ * SEN
+ * 1001 0100 0010 1000
+ *----------------------------------------------------------------------------
+ */
+
+int
+cl_avr::sen(t_mem code)
+{
+  t_mem d= BIT_N | ram->read(SREG);
+  ram->write(SREG, d);
+  return(resGO);
+}
+
+
+/*
+ * Set Zero Flag
+ * SEZ
+ * 1001 0100 0001 1000
+ *----------------------------------------------------------------------------
+ */
+
+int
+cl_avr::sez(t_mem code)
+{
+  t_mem d= BIT_Z | ram->read(SREG);
+  ram->write(SREG, d);
+  return(resGO);
+}
+
+
+/*
+ * Set Global Interrupt Flag
+ * SEI
+ * 1001 0100 0111 1000
+ *----------------------------------------------------------------------------
+ */
+
+int
+cl_avr::sei(t_mem code)
+{
+  t_mem d= BIT_I | ram->read(SREG);
+  ram->write(SREG, d);
+  return(resGO);
+}
+
+
+/*
+ * Set Signed Flag
+ * SES
+ * 1001 0100 0100 1000
+ *----------------------------------------------------------------------------
+ */
+
+int
+cl_avr::ses(t_mem code)
+{
+  t_mem d= BIT_S | ram->read(SREG);
+  ram->write(SREG, d);
+  return(resGO);
+}
+
+
+/*
+ * Set Overflow Flag
+ * SEV
+ * 1001 0100 0011 1000
+ *----------------------------------------------------------------------------
+ */
+
+int
+cl_avr::sev(t_mem code)
+{
+  t_mem d= BIT_V | ram->read(SREG);
+  ram->write(SREG, d);
+  return(resGO);
+}
+
+
+/*
+ * Set T Flag
+ * SET
+ * 1001 0100 0110 1000
+ *----------------------------------------------------------------------------
+ */
+
+int
+cl_avr::set(t_mem code)
+{
+  t_mem d= BIT_T | ram->read(SREG);
+  ram->write(SREG, d);
+  return(resGO);
+}
+
+
+/*
+ * Set Half Carry Flag
+ * SEH
+ * 1001 0100 0101 1000
+ *----------------------------------------------------------------------------
+ */
+
+int
+cl_avr::seh(t_mem code)
+{
+  t_mem d= BIT_H | ram->read(SREG);
+  ram->write(SREG, d);
+  return(resGO);
+}
+
+
+/*
+ * Clear Carry Flag
+ * CLC
+ * 1001 0100 1000 1000
+ *----------------------------------------------------------------------------
+ */
+
+int
+cl_avr::clc(t_mem code)
+{
+  t_mem d= ~BIT_C & ram->read(SREG);
+  ram->write(SREG, d);
+  return(resGO);
+}
+
+
+/*
+ * Clear Negative Flag
+ * CLN
+ * 1001 0100 1010 1000
+ *----------------------------------------------------------------------------
+ */
+
+int
+cl_avr::cln(t_mem code)
+{
+  t_mem d= ~BIT_N & ram->read(SREG);
+  ram->write(SREG, d);
+  return(resGO);
+}
+
+
+/*
+ * Clear Zero Flag
+ * CLZ
+ * 1001 0100 1001 1000
+ *----------------------------------------------------------------------------
+ */
+
+int
+cl_avr::clz(t_mem code)
+{
+  t_mem d= ~BIT_Z & ram->read(SREG);
+  ram->write(SREG, d);
+  return(resGO);
+}
+
+
+/*
+ * Global Interrupt Flag
+ * CLI
+ * 1001 0100 1111 1000
+ *----------------------------------------------------------------------------
+ */
+
+int
+cl_avr::cli(t_mem code)
+{
+  t_mem d= ~BIT_I & ram->read(SREG);
+  ram->write(SREG, d);
+  return(resGO);
+}
+
+
+/*
+ * Clear Signed Flag
+ * CLS
+ * 1001 0100 1100 1000
+ *----------------------------------------------------------------------------
+ */
+
+int
+cl_avr::cls(t_mem code)
+{
+  t_mem d= ~BIT_S & ram->read(SREG);
+  ram->write(SREG, d);
+  return(resGO);
+}
+
+
+/*
+ * Clear Overflow Flag
+ * CLV
+ * 1001 0100 1011 1000
+ *----------------------------------------------------------------------------
+ */
+
+int
+cl_avr::clv(t_mem code)
+{
+  t_mem d= ~BIT_V & ram->read(SREG);
+  ram->write(SREG, d);
+  return(resGO);
+}
+
+
+/*
+ * Clear T Flag
+ * CLT
+ * 1001 0100 1110 1000
+ *----------------------------------------------------------------------------
+ */
+
+int
+cl_avr::clt(t_mem code)
+{
+  t_mem d= ~BIT_T & ram->read(SREG);
+  ram->write(SREG, d);
+  return(resGO);
+}
+
+
+/*
+ * Clear Half Carry Flag
+ * CLH
+ * 1001 0100 1101 1000
+ *----------------------------------------------------------------------------
+ */
+
+int
+cl_avr::clh(t_mem code)
+{
+  t_mem d= ~BIT_H & ram->read(SREG);
+  ram->write(SREG, d);
+  return(resGO);
+}
+
+
+/*
+ * Clear Bit in I/O Register
+ * CBI P,b 0<=P<=31 0<=b<=7
+ * 1001 1000 pppp pbbb
+ *____________________________________________________________________________
+ */
+
+int
+cl_avr::cbi_A_b(t_mem code)
+{
+  uint addr, mask;
+  t_mem d;
+
+  addr= ((code&0xf8)>>3)+0x20;
+  mask= 1 << (code&7);
+  d= ~mask & ram->read(addr);
+  ram->write(addr, d);
+  vc.rd++;
+  vc.wr++;
+  tick(1);
+  return(resGO);
+}
+
+
+/*
+ * Set Bit in I/O Register
+ * SBI P,b 0<=P<=31 0<=b<=7
+ * 1001 1010 pppp pbbb
+ *____________________________________________________________________________
+ */
+
+int
+cl_avr::sbi_A_b(t_mem code)
+{
+  uint addr, mask;
+  
+  addr= ((code&0xf8)>>3)+0x20;
+  mask= 1 << (code&7);
+  t_mem d= mask | ram->read(addr);
+  ram->write(addr, d);
+  vc.rd++;
+  vc.wr++;
+  tick(1);
+  return(resGO);
+}
+
+
+/*
+ * Bit Load from the T Flag in SREG to a Bit in Register
+ * BLD Rd,b 0<=d<=31, 0<=b<=7
+ * 1111 100d dddd 0bbb
+ *____________________________________________________________________________
+ */
+
+int
+cl_avr::bld_Rd_b(t_mem code)
+{
+  t_addr d;
+  int b, mask;
+  t_mem data;
+
+  d= (code&0x1f0)>>4;
+  b= code&7;
+  mask= 1<<b;
+  if (ram->read(SREG) & BIT_T)
+    data= ram->read(d) | mask;
+  else
+    data= ram->read(d) & ~mask;
+  ram->write(d, data);
+  vc.wr++;
+  return(resGO);
+}
+
+
+/*
+ * Bit Store from Bit in Register to T Flag in SREG
+ * BST Rd,b 0<=d<=31, 0<=b<=7
+ * 1111 101d dddd Xbbb
+ *____________________________________________________________________________
+ */
+
+int
+cl_avr::bst_Rd_b(t_mem code)
+{
+  t_addr d;
+  int b, mask;
+
+  d= (code&0x1f0)>>4;
+  b= code&7;
+  mask= 1<<b;
+  t_mem data= ram->read(d);
+  if (data & mask)
+    ram->set_bit1(SREG, BIT_T);
+  else
+    ram->set_bit0(SREG, BIT_T);
+  vc.rd++;
+  return(resGO);
+}
+
+
+/* End of avr.src/bit_inst.cc */
diff --git a/sim/ucsim/avr.src/clean.mk b/sim/ucsim/avr.src/clean.mk
new file mode 100644
index 0000000..e81b3cc
--- /dev/null
+++ b/sim/ucsim/avr.src/clean.mk
@@ -0,0 +1,29 @@
+# avr.src/clean.mk
+
+# Deleting all files created by building the program
+# --------------------------------------------------
+clean:
+	rm -f *core *[%~] *.[oa] *.map
+	rm -f .[a-z]*~
+	rm -f savr$(EXEEXT)
+
+
+# Deleting all files created by configuring or building the program
+# -----------------------------------------------------------------
+distclean: clean
+	rm -f config.cache config.log config.status
+	rm -f Makefile *.dep
+	rm -f *.obj *.list *.lst *.hex
+
+
+# Like clean but some files may still exist
+# -----------------------------------------
+mostlyclean: clean
+
+
+# Deleting everything that can reconstructed by this Makefile. It deletes
+# everything deleted by distclean plus files created by bison, etc.
+# -----------------------------------------------------------------------
+realclean: distclean
+
+# End of avr.src/clean.mk
diff --git a/sim/ucsim/avr.src/conf.mk b/sim/ucsim/avr.src/conf.mk
new file mode 100644
index 0000000..3e77898
--- /dev/null
+++ b/sim/ucsim/avr.src/conf.mk
@@ -0,0 +1,11 @@
+# avr.src/conf.mk
+#
+# Makefile targets to remake configuration
+#
+
+freshconf: Makefile
+
+Makefile: $(srcdir)/Makefile.in $(top_srcdir)/configure.ac
+	cd $(top_builddir) && $(SHELL) ./config.status
+
+# End of avr.src/conf.mk
diff --git a/sim/ucsim/avr.src/glob.cc b/sim/ucsim/avr.src/glob.cc
new file mode 100644
index 0000000..d79dc26
--- /dev/null
+++ b/sim/ucsim/avr.src/glob.cc
@@ -0,0 +1,155 @@
+/*
+ * Simulator of microcontrollers (glob.cc)
+ *
+ * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#include <stdio.h>
+
+#include "stypes.h"
+
+
+struct dis_entry disass_avr[]= {
+  { 0x0000, 0xffff, ' ', 1, "nop" },
+  { 0x9488, 0xffff, ' ', 1, "clc" },
+  { 0x94d8, 0xffff, ' ', 1, "clh" },
+  { 0x94f8, 0xffff, ' ', 1, "cli" },
+  { 0x94a8, 0xffff, ' ', 1, "cln" },
+  { 0x94c8, 0xffff, ' ', 1, "cls" },
+  { 0x94e8, 0xffff, ' ', 1, "clt" },
+  { 0x94b8, 0xffff, ' ', 1, "clv" },
+  { 0x9498, 0xffff, ' ', 1, "clz" },
+  { 0x9408, 0xffff, ' ', 1, "sec" },
+  { 0x9458, 0xffff, ' ', 1, "seh" },
+  { 0x9478, 0xffff, ' ', 1, "sei" },
+  { 0x9428, 0xffff, ' ', 1, "sen" },
+  { 0x9448, 0xffff, ' ', 1, "ses" },
+  { 0x9468, 0xffff, ' ', 1, "set" },
+  { 0x9438, 0xffff, ' ', 1, "sev" },
+  { 0x9418, 0xffff, ' ', 1, "sez" },
+  { 0x1c00, 0xfc00, ' ', 1, "adc %d,%r" },
+  { 0x0c00, 0xfc00, ' ', 1, "add %d,%r" },
+  { 0x9600, 0xff00, ' ', 1, "adiw %2,%6" },
+  { 0x2000, 0xfc00, ' ', 1, "and %d,%r" },
+  { 0x7000, 0xf000, ' ', 1, "andi %D,%K" },
+  { 0x9405, 0xfe0f, ' ', 1, "asr %d" },
+  { 0x9488, 0xff8f, ' ', 1, "bclr %s" },
+  { 0xf800, 0xfe08, ' ', 1, "bld %d,%b" },
+  { 0xf400, 0xfc07, ' ', 1, "brcc %k" },
+  { 0xf000, 0xfc07, ' ', 1, "brcs %k" },
+  { 0xf001, 0xfc07, ' ', 1, "breq %k" },
+  { 0xf404, 0xfc07, ' ', 1, "brge %k" },
+  { 0xf405, 0xfc07, ' ', 1, "brhc %k" },
+  { 0xf005, 0xfc07, ' ', 1, "brhs %k" },
+  { 0xf407, 0xfc07, ' ', 1, "brid %k" },
+  { 0xf007, 0xfc07, ' ', 1, "brie %k" },
+  { 0xf000, 0xfc07, ' ', 1, "brlo %k" },
+  { 0xf004, 0xfc07, ' ', 1, "brlt %k" },
+  { 0xf002, 0xfc07, ' ', 1, "brmi %k" },
+  { 0xf401, 0xfc07, ' ', 1, "brne %k" },
+  { 0xf402, 0xfc07, ' ', 1, "brpl %k" },
+  { 0xf400, 0xfc07, ' ', 1, "brsh %k" },
+  { 0xf406, 0xfc07, ' ', 1, "brtc %k" },
+  { 0xf006, 0xfc07, ' ', 1, "brts %k" },
+  { 0xf403, 0xfc07, ' ', 1, "brvc %k" },
+  { 0xf003, 0xfc07, ' ', 1, "brvs %k" },
+  { 0xf400, 0xfc00, ' ', 1, "brbc %b,%k" },
+  { 0xf000, 0xfc00, ' ', 1, "brbs %b,%k" },
+  { 0x9408, 0xff8f, ' ', 1, "bset %s" },
+  { 0xfa00, 0xfe00, ' ', 1, "bst %d,%b" },
+  { 0x940e, 0xfe0e, 'l', 2, "call %A", true },
+  { 0x9800, 0xff00, ' ', 1, "cbi %P,%b" },
+  { 0x9400, 0xfe0f, ' ', 1, "com %d" },
+  { 0x1400, 0xfc00, ' ', 1, "cp %d,%r" },
+  { 0x0400, 0xfc00, ' ', 1, "cpc %d,%r" },
+  { 0x3000, 0xf000, ' ', 1, "cpi %D,%K" },
+  { 0x1000, 0xfc00, ' ', 1, "cpse %d,%r" },
+  { 0x940a, 0xfe0f, ' ', 1, "dec %d" },
+  { 0x2400, 0xfc00, ' ', 1, "eor %d,%r" },
+  { 0x9509, 0xff0f, ' ', 1, "icall" },
+  { 0x9409, 0xff0f, ' ', 1, "ijmp" },
+  { 0xb000, 0xf800, ' ', 1, "in %d,%p" },
+  { 0x9403, 0xfe0f, ' ', 1, "inc %d" },
+  { 0x940c, 0xfe0e, ' ', 2, "jmp %A" },
+  { 0x900c, 0xfe0f, ' ', 1, "ld %d,X" },
+  { 0x900d, 0xfe0f, ' ', 1, "ld %d,X+" },
+  { 0x900e, 0xfe0f, ' ', 1, "ld %d,-X" },
+  { 0x8008, 0xfe0f, ' ', 1, "ld %d,Y" },
+  { 0x9009, 0xfe0f, ' ', 1, "ld %d,Y+" },
+  { 0x900a, 0xfe0f, ' ', 1, "ld %d,-Y" },
+  { 0x8008, 0xd208, ' ', 1, "ldd %d,Y+%q" },
+  { 0x8000, 0xfe0f, ' ', 1, "ld %d,Z" },
+  { 0x9001, 0xfe0f, ' ', 1, "ld %d,Z+" },
+  { 0x9002, 0xfe0f, ' ', 1, "ld %d,-Z" },
+  { 0x8000, 0xd208, ' ', 1, "ldd %d,Z+%q" },
+  { 0xe000, 0xf000, ' ', 1, "ldi %D,%K" },
+  { 0x9000, 0xfe0f, ' ', 2, "lds %d,%R" },
+  { 0x95c8, 0xffff, ' ', 1, "lpm" },
+  { 0x95d8, 0xffff, ' ', 1, "elpm" }, // in some devices equal to lpm
+  { 0x9406, 0xfe0f, ' ', 1, "lsr %d" },
+  { 0x2c00, 0xfc00, ' ', 1, "mov %d,%r" },
+  { 0x9c00, 0xfc00, ' ', 1, "mul %d,%r" },
+  { 0x9401, 0xfe0f, ' ', 1, "neg %d" },
+  { 0x2800, 0xfc00, ' ', 1, "or %d,%r" },
+  { 0x6000, 0xf000, ' ', 1, "ori %d,%K" },
+  { 0xb800, 0xf800, ' ', 1, "out %p,%d" },
+  { 0x900f, 0xfe0f, ' ', 1, "pop %d" },
+  { 0x920f, 0xfe0f, ' ', 1, "push %d" },
+  { 0xd000, 0xf000, ' ', 1, "rcall %a" },
+  { 0x9508, 0xff9f, ' ', 1, "ret" },
+  { 0x9518, 0xff9f, ' ', 1, "reti" },
+  { 0xc000, 0xf000, ' ', 1, "rjmp %a" },
+  { 0x9407, 0xfe0f, ' ', 1, "ror %d" },
+  { 0x0800, 0xfc00, ' ', 1, "sbc %d,%r" },
+  { 0x4000, 0xf000, ' ', 1, "sbci %D,%K" },
+  { 0x9a00, 0xff00, ' ', 1, "sbi %P,%b" },
+  { 0x9900, 0xff00, ' ', 1, "sbic %P,%b" },
+  { 0x9b00, 0xff00, ' ', 1, "sbis %P,%b" },
+  { 0x9700, 0xff00, ' ', 1, "sbiw %2,%6" },
+  { 0x6000, 0xf000, ' ', 1, "sbr %D,%K" },
+  { 0xfc00, 0xfe00, ' ', 1, "sbrc %d,%b" },
+  { 0xfe00, 0xfe00, ' ', 1, "sbrs %d,%b" },
+  { 0xef0f, 0xff0f, ' ', 1, "ser %D" },
+  { 0x9588, 0xffef, ' ', 1, "sleep" },
+  { 0x920c, 0xfe0f, ' ', 1, "st X,%d" },
+  { 0x920d, 0xfe0f, ' ', 1, "st X+,%d" },
+  { 0x920e, 0xfe0f, ' ', 1, "st -X,%d" },
+  { 0x8208, 0xfe0f, ' ', 1, "st Y,%d" },
+  { 0x9209, 0xfe0f, ' ', 1, "st Y+,%d" },
+  { 0x920a, 0xfe0f, ' ', 1, "st -Y,%d" },
+  { 0x8208, 0xd208, ' ', 1, "std Y+%q,%d" },
+  { 0x8200, 0xfe0f, ' ', 1, "st Z,%d" },
+  { 0x9201, 0xfe0f, ' ', 1, "st Z+,%d" },
+  { 0x9202, 0xfe0f, ' ', 1, "st -Z,%d" },
+  { 0x8200, 0xd208, ' ', 1, "std Z+%q,%d" },
+  { 0x9200, 0xfe0f, ' ', 2, "sts %R,%d" },
+  { 0x1800, 0xfc00, ' ', 1, "sub %d,%r" },
+  { 0x5000, 0xf000, ' ', 1, "subi %D,%K" },
+  { 0x9402, 0xfe0f, ' ', 1, "swap %d" },
+  { 0x95a8, 0xffef, ' ', 1, "wdr" },
+  { 0, 0, 0, 0, NULL }
+};
+
+
+/* End of avr.src/glob.cc */
diff --git a/sim/ucsim/avr.src/glob.h b/sim/ucsim/avr.src/glob.h
new file mode 100644
index 0000000..308c74f
--- /dev/null
+++ b/sim/ucsim/avr.src/glob.h
@@ -0,0 +1,39 @@
+/*
+ * Simulator of microcontrollers (glob.h)
+ *
+ * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#ifndef GLOB_HEADER
+#define GLOB_HEADER
+
+#include "stypes.h"
+
+
+extern struct dis_entry disass_avr[];
+
+
+#endif
+
+/* End of avr.src/glob.h */
diff --git a/sim/ucsim/avr.src/info_1001.txt b/sim/ucsim/avr.src/info_1001.txt
new file mode 100644
index 0000000..c9650c1
--- /dev/null
+++ b/sim/ucsim/avr.src/info_1001.txt
@@ -0,0 +1,47 @@
+LDS Rd,k	1001 000d dddd 0000
+LD Rd,Z+	1001 000d dddd 0001
+LD Rd,-Z	1001 000d dddd 0010
+LPM Rd,Z	1001 000d dddd 0100
+LPM Rd,Z+	1001 000d dddd 0101
+ELMP Rd,Z	1001 000d dddd 0110
+ELMP Rd,Z+	1001 000d dddd 0111
+LD Rd,Y+	1001 000d dddd 1001
+LD Rd,-Y	1001 000d dddd 1010
+LD Rd,X		1001 000d dddd 1100
+LD Rd,X+	1001 000d dddd 1101
+LD Rd,-X	1001 000d dddd 1110
+POP Rd		1001 000d dddd 1111
+
+STS k,Rr	1001 001d dddd 0000
+ST Z+,Rr	1001 001r rrrr 0001
+ST -Z,Rr	1001 001r rrrr 0010
+ST Y+,Rr	1001 001r rrrr 1001
+ST -Y,Rr	1001 001r rrrr 1010
+ST X,Rr		1001 001r rrrr 1100
+ST X+,Rr	1001 001r rrrr 1101
+ST -X,Rr	1001 001r rrrr 1110
+PUSH Rr		1001 001d dddd 1111
+
+COM Rd		1001 010d dddd 0000
+NEG Rd		1001 010d dddd 0001
+SWAP Rd		1001 010d dddd 0010
+INC Rd		1001 010d dddd 0011
+ASR Rd		1001 010d dddd 0101
+LSR Rd		1001 010d dddd 0110
+ROR Rd		1001 010d dddd 0111
+DEC Rd		1001 010d dddd 1010
+JMP k		1001 010k kkkk 110k
+CALL k		1001 010k kkkk 111k
+
+BSET s		1001 0100 0sss 1000
+BCLR s		1001 0100 1sss 1000
+
+ADIW Rd,K	1001 0110 KKdd KKKK
+SBIW Rd,K	1001 0111 KKdd KKKK
+
+CBI A,b		1001 1000 AAAA Abbb
+SBIC A,b	1001 1001 AAAA Abbb
+SBI A,b		1001 1010 AAAA Abbb
+SBIS A,b	1001 1011 AAAA Abbb
+
+MUL Rd,Rr	1001 11rd dddd rrrr
diff --git a/sim/ucsim/avr.src/info_1111.txt b/sim/ucsim/avr.src/info_1111.txt
new file mode 100644
index 0000000..0faf0a1
--- /dev/null
+++ b/sim/ucsim/avr.src/info_1111.txt
@@ -0,0 +1,27 @@
+BRCS k		1111 00kk kkkk k000 =BRBS 0,k =BRLO k
+BRLO k		1111 00kk kkkk k000 =BRBS 0,k =BRCS k
+BREQ k		1111 00kk kkkk k001 =BRBS 1,k
+BRMI k		1111 00kk kkkk k010 =BRBS 2,k
+BRVS k		1111 00kk kkkk k011 =BRBS 3,k
+BRLT k		1111 00kk kkkk k100 =BRBS 4,k
+BRHS k		1111 00kk kkkk k101 =BRBS 5,k
+BRTS k		1111 00kk kkkk k110 =BRBS 6,k
+BRIE k		1111 00kk kkkk k111 =BRBS 7,k
+BRBS s,k	1111 00kk kkkk ksss
+
+BRCC k		1111 01kk kkkk k000 =BRBC 0,k
+BRHS k		1111 01kk kkkk k000 =BRBC 0,k
+BRNE k		1111 01kk kkkk k001 =BRBC 1,k
+BRPL k		1111 01kk kkkk k010 =BRBC 2,k
+BRVC k		1111 01kk kkkk k011 =BRBC 3,k
+BRGE k		1111 01kk kkkk k100 =BRBC 4,k
+BRHC k		1111 01kk kkkk k101 =BRBC 5,k
+BRTC k		1111 01kk kkkk k110 =BRBC 6,k
+BRID k		1111 01kk kkkk k111 =BRBC 7,k
+BRBC s,k	1111 01kk kkkk ksss
+
+BLD Rd,b	1111 100d dddd 0bbb
+BST Rd,b	1111 101d dddd 0bbb
+
+SBRC Rr,b	1111 110r rrrr 0bbb
+SBRS Rr,b	1111 111r rrrr 0bbb
diff --git a/sim/ucsim/avr.src/info_types.txt b/sim/ucsim/avr.src/info_types.txt
new file mode 100644
index 0000000..21f4115
--- /dev/null
+++ b/sim/ucsim/avr.src/info_types.txt
@@ -0,0 +1,23 @@
+		inst Flash EE  SRAM I/O Vcc     Speed
+AT90S1200	89   1K	   64  0    15  2.7-6.0 0-12
+AT90S2313	118  2K    128 128  15  2.7-6.0 0-10
+AT90S2323	118  2K    128 128  3   4.0-6.0 0-10
+AT90LS2323	118  2K    128 128  3   2.7-6.0 0-4
+AT90S2343	118  2K    128 128  5   4.0-6.0 0-10
+AT90LS2343	118  2K    128 128  5   2.7-6.0 0-4
+AT90S2333	118  2K    128 128  20  4.0-6.0 0-8
+AT90LS2333	118  2K    128 128  20  2.7-6.0 0-4
+AT90S4433	118  4K    256 128  20  4.0-6.0 0-8
+AT90LS4433	118  4K    256 128  20  2.7-6.0 0-4
+AT90S4414	118  4K    256 256  32  2.7-6.0 0-8
+AT90S4434	118  4K    256 256  32  4.0-6.0 0-8
+AT90LS4434	118  4K    256 256  32  2.7-6.0 0-4
+AT90S8535	118  8K    512 512  32  4.0-6.0 0-8
+AT90LS8535	118  8K    512 512  32  2.7-6.0 0-4
+AT90S8515	118  8K    512 512  32  2.7-6.0 0-8
+ATmega603	121  64K   2K  4K   32  4.0-5.5 0-6
+ATmega603L	121  64K   2K  4K   32  2.7-3.6 0-4
+ATmega103	121  128K  4K  4K   32  4.0-5.5 0-6
+ATmega103L	121  128K  4K  4K   32  2.7-3.6 0-4
+
+1200 2313 2323 2343 2333 4333 4414/34 8535/15 603 103
\ No newline at end of file
diff --git a/sim/ucsim/avr.src/inst.cc b/sim/ucsim/avr.src/inst.cc
new file mode 100644
index 0000000..5818294
--- /dev/null
+++ b/sim/ucsim/avr.src/inst.cc
@@ -0,0 +1,96 @@
+/*
+ * Simulator of microcontrollers (inst.cc)
+ *
+ * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#include "ddconfig.h"
+
+// local
+#include "avrcl.h"
+#include "regsavr.h"
+
+
+/*
+ * No Instruction
+ * NOP
+ * 0000 0000 0000 0000
+ *----------------------------------------------------------------------------
+ */
+
+int
+cl_avr::nop(t_mem code)
+{
+  return(resGO);
+}
+
+
+/*
+ * Sleep
+ * SLEEP
+ * 1001 0101 100X 1000
+ *____________________________________________________________________________
+ */
+
+int
+cl_avr::sleep(t_mem code)
+{
+  sleep_executed= 1;
+  return(resGO);
+}
+
+
+/*
+ * Watchdog Reset
+ * WDR
+ * 1001 0101 101X 1000
+ *____________________________________________________________________________
+ */
+
+int
+cl_avr::wdr(t_mem code)
+{
+  //FIXME
+  return(resGO);
+}
+
+
+/*
+ * Set all bits in Register
+ * SER Rd  16<=d<=31
+ * 1110 1111 dddd 1111
+ *____________________________________________________________________________
+ */
+
+int
+cl_avr::ser_Rd(t_mem code)
+{
+  t_addr d= (code&0xf0)>>4;
+  t_mem data= 0xff;
+  ram->write(d, data);
+  return(resGO);
+}
+
+
+/* End of avr.src/inst.cc */
diff --git a/sim/ucsim/avr.src/instcl.h b/sim/ucsim/avr.src/instcl.h
new file mode 100644
index 0000000..62b2398
--- /dev/null
+++ b/sim/ucsim/avr.src/instcl.h
@@ -0,0 +1,8 @@
+/* avr.src/instcl.h */
+
+  virtual int nop(t_mem code);
+  virtual int sleep(t_mem code);
+  virtual int wdr(t_mem code);
+  virtual int ser_Rd(t_mem code);
+
+/* End of avr.src/instcl.h */
diff --git a/sim/ucsim/avr.src/jump_cl.h b/sim/ucsim/avr.src/jump_cl.h
new file mode 100644
index 0000000..92dedc7
--- /dev/null
+++ b/sim/ucsim/avr.src/jump_cl.h
@@ -0,0 +1,21 @@
+/* avr.src/jump_cl.h */
+
+  virtual int ijmp(t_mem code);
+  virtual int eijmp(t_mem code);
+  virtual int icall(t_mem code);
+  virtual int eicall(t_mem code);
+  virtual int ret(t_mem code);
+  virtual int reti(t_mem code);
+  virtual int rjmp_k(t_mem code);
+  virtual int rcall_k(t_mem code);
+  virtual int cpse_Rd_Rr(t_mem code);
+  virtual int jmp_k(t_mem code);
+  virtual int call_k(t_mem code);
+  virtual int brbs_s_k(t_mem code);
+  virtual int brbc_s_k(t_mem code);
+  virtual int sbrc_Rr_b(t_mem code);
+  virtual int sbrs_Rr_b(t_mem code);
+  virtual int sbic_P_b(t_mem code);
+  virtual int sbis_P_b(t_mem code);
+
+/* End of avr.src/jump_cl.h */
diff --git a/sim/ucsim/avr.src/jump_inst.cc b/sim/ucsim/avr.src/jump_inst.cc
new file mode 100644
index 0000000..0d80dce
--- /dev/null
+++ b/sim/ucsim/avr.src/jump_inst.cc
@@ -0,0 +1,430 @@
+/*
+ * Simulator of microcontrollers (jmp_inst.cc)
+ *
+ * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#include "avrcl.h"
+#include "regsavr.h"
+
+
+/*
+ * Indirect Jump
+ * IJMP
+ * 1001 0100 XXXX 1001
+ *____________________________________________________________________________
+ */
+
+int
+cl_avr::ijmp(t_mem code)
+{
+  t_addr z;
+
+  z= ram->get(ZH)*256 + ram->get(ZL);
+  PC= rom->validate_address((PC & ~0xffff) | z);
+  //FIXME: analyze
+  return(resGO);
+}
+
+
+int
+cl_avr::eijmp(t_mem code)
+{
+  return(resGO);
+}
+
+
+/*
+ * Indirect Call to Subroutine
+ * ICALL
+ * 1001 0101 XXXX 1001
+ *____________________________________________________________________________
+ */
+
+int
+cl_avr::icall(t_mem code)
+{
+  t_mem zl, zh;
+  t_addr z;
+  
+  push_addr(PC);
+  zl= ram->read(ZL);
+  zh= ram->read(ZH);
+  z= zh*256 + zl;
+  PC= (PC & ~0xffff) | (z & 0xffff);
+  //FIXME: analyze
+  tick(2);
+  return(resGO);
+}
+
+
+int
+cl_avr::eicall(t_mem code)
+{
+  return(resGO);
+}
+
+
+/*
+ * Return from Subroutine
+ * RET
+ * 1001 0101 0XX0 1000
+ *____________________________________________________________________________
+ */
+
+int
+cl_avr::ret(t_mem code)
+{
+  t_addr a;
+
+  pop_addr(&a);
+  PC= rom->validate_address(a);
+  tick(3);
+  return(resGO);
+}
+
+
+/*
+ * Return from Interrupt
+ * RETI
+ * 1001 0101 0XX1 1000
+ *____________________________________________________________________________
+ */
+
+int
+cl_avr::reti(t_mem code)
+{
+  t_addr a;
+
+  pop_addr(&a);
+  PC= rom->validate_address(a);
+  t_mem sreg= ram->read(SREG);
+  sreg|= BIT_I;
+  ram->write(SREG, sreg);
+  tick(3);
+  return(resGO);
+}
+
+
+/*
+ * Relative Jump
+ * RJMP k -2K<=k<=2K
+ * 1100 kkkk kkkk kkkk
+ *____________________________________________________________________________
+ */
+
+int
+cl_avr::rjmp_k(t_mem code)
+{
+  long k= code & 0xfff;
+
+  if (k & 0x800)
+    k|= -4096;
+  PC= rom->validate_address((signed)PC + (signed)k);
+  tick(1);
+  return(resGO);
+}
+
+
+/*
+ * Relative Call to Subroutine
+ * RCALL k
+ * 1101 kkkk kkkk kkkk -1K<=k<=+1k
+ *____________________________________________________________________________
+ */
+
+int
+cl_avr::rcall_k(t_mem code)
+{
+  t_addr k;
+
+  push_addr(PC);
+  k= code & 0xfff;
+  if (k & 0x800)
+    k|= ~0xfff;
+  PC= rom->validate_address((signed)PC + (signed)k);
+  tick(2);
+
+  return(resGO);
+}
+
+
+/*
+ * Compare Skip if Equal
+ * CPSE Rd,Rr 0<=d<=31, 0<=r<=31
+ * 0001 00rd dddd rrrr
+ *____________________________________________________________________________
+ */
+
+int
+cl_avr::cpse_Rd_Rr(t_mem code)
+{
+  t_addr d, r;
+
+  d= (code&0x1f0)>>4;
+  r= ((code&0x200)>>5)|(code&0xf);
+  if (ram->read(r) == ram->read(d))
+    {
+      t_mem next_code= rom->get(PC);
+      int i= 0;
+      struct dis_entry *dt= dis_tbl();
+      while ((next_code & dt[i].mask) != dt[i].code &&
+	     dt[i].mnemonic)
+	i++;
+      if (dt[i].mnemonic != NULL)
+	{
+	  PC= rom->validate_address(PC + dt[i].length);
+	  tick(1);
+	}
+      else
+	return(resINV_INST);
+    }
+  return(resGO);
+}
+
+
+/*
+ * Jump
+ * JMP k 0<=k<=4M
+ * 1001 010k kkkk 110k
+ * kkkk kkkk kkkk kkkk
+ *____________________________________________________________________________
+ */
+
+int
+cl_avr::jmp_k(t_mem code)
+{
+  t_addr k;
+
+  k= ((code&0x1f0)>>3)|(code&1);
+  k= (k<<16)|fetch();
+  PC= rom->validate_address(k);
+  tick(2);
+  return(resGO);
+}
+
+
+/*
+ * Long Call to a Subroutine
+ * CALL k 0<=k<=64k/4M
+ * 1001 010k kkkk 111k
+ * kkkk kkkk kkkk kkkk
+ *____________________________________________________________________________
+ */
+
+int
+cl_avr::call_k(t_mem code)
+{
+  t_addr k;
+
+  k= (((code&0x1f0)>>3)|(code&1))*0x10000;
+  k= k + fetch();
+  push_addr(PC);
+  PC= rom->validate_address(k);
+  tick(3);
+  return(resGO);
+}
+
+
+/*
+ * Branch if Bit in SREG is Set
+ * BRBS s,k 0<=s<=7, -64<=k<=+63
+ * 1111 00kk kkkk ksss
+ *____________________________________________________________________________
+ */
+
+int
+cl_avr::brbs_s_k(t_mem code)
+{
+  int s, k;
+
+  k= (code&0x3f8)>>3;
+  s= code&7;
+  t_mem sreg= ram->get(SREG);
+  t_mem mask= 1<<s;
+  if (sreg & mask)
+    {
+      if (code&0x200)
+	k|= -128;
+      PC= rom->validate_address((signed)PC+k);
+      tick(1);
+    }
+  return(resGO);
+}
+
+
+/*
+ * Branch if Bit in SREG is Cleared
+ * BRBC s,k 0<=s<=7, -64<=k<=+63
+ * 1111 01kk kkkk ksss
+ *____________________________________________________________________________
+ */
+
+int
+cl_avr::brbc_s_k(t_mem code)
+{
+  int s, k;
+
+  k= (code&0x3f8)>>3;
+  s= code&7;
+  t_mem sreg= ram->get(SREG);
+  t_mem mask= 1<<s;
+  if (!(sreg & mask))
+    {
+      if (code&0x200)
+	k|= -128;
+      PC= rom->validate_address((signed)PC+k);
+      tick(1);
+    }
+  return(resGO);
+}
+
+
+/*
+ * Skip if Bit in Register is Cleared
+ * SBRC Rr,b  0<=r<=31, 0<=b<=7
+ * 1111 110r rrrr Xbbb
+ *____________________________________________________________________________
+ */
+
+int
+cl_avr::sbrc_Rr_b(t_mem code)
+{
+  t_addr r= (code&0x1f0)>>4;
+  int b= code&7;
+  t_mem mask= 1<<b;
+  if (!(ram->read(r) & mask))
+    {
+      t_mem next_code= rom->get(PC);
+      int i= 0;
+      struct dis_entry *dt= dis_tbl();
+      while ((next_code & dt[i].mask) != dt[i].code &&
+	     dt[i].mnemonic)
+	i++;
+      if (dt[i].mnemonic != NULL)
+	{
+	  PC= rom->validate_address(PC + dt[i].length);
+	  tick(1);
+	}
+      else
+	return(resINV_INST);
+    }
+  return(resGO);
+}
+
+
+/*
+ * Skip if Bit in Register is Set
+ * SBRS Rr,b  0<=r<=31, 0<=b<=7
+ * 1111 111r rrrr Xbbb
+ *____________________________________________________________________________
+ */
+
+int
+cl_avr::sbrs_Rr_b(t_mem code)
+{
+  t_addr r= (code&0x1f0)>>4;
+  int b= code&7;
+  t_mem mask= 1<<b;
+  if (ram->read(r) & mask)
+    {
+      t_mem next_code= rom->get(PC);
+      int i= 0;
+      struct dis_entry *dt= dis_tbl();
+      while ((next_code & dt[i].mask) != dt[i].code &&
+	     dt[i].mnemonic)
+	i++;
+      if (dt[i].mnemonic != NULL)
+	{
+	  PC= rom->validate_address(PC + dt[i].length);
+	  tick(1);
+	}
+      else
+	return(resINV_INST);
+    }
+  return(resGO);
+}
+
+
+/*
+ * Skip if Bit in I/O Register is Clear
+ * SBIC P,b 0<=P<=31 0<=b<=7
+ * 1001 1001 pppp pbbb
+ *____________________________________________________________________________
+ */
+
+int
+cl_avr::sbic_P_b(t_mem code)
+{
+  uint addr, mask;
+  
+  addr= ((code&0xf8)>>3)+0x20;
+  mask= 1 << (code&7);
+  vc.rd++;
+  if (0 == (mask & ram->read(addr)))
+    {
+      code= fetch();
+      int size= inst_length(code);
+      while (size > 1)
+	{
+	  fetch();
+	  size--;
+	}
+      tick(1);
+    }
+  return(resGO);
+}
+
+
+/*
+ * Skip if Bit in I/O Register is Set
+ * SBIS P,b 0<=P<=31 0<=b<=7
+ * 1001 1011 pppp pbbb
+ *____________________________________________________________________________
+ */
+
+int
+cl_avr::sbis_P_b(t_mem code)
+{
+  uint addr, mask;
+  
+  addr= ((code&0xf8)>>3)+0x20;
+  mask= 1 << (code&7);
+  vc.rd++;
+  if (mask & ram->read(addr))
+    {
+      code= fetch();
+      int size= inst_length(code);
+      while (size > 1)
+	{
+	  fetch();
+	  size--;
+	}
+      tick(1);
+    }
+  return(resGO);
+}
+
+
+/* End of avr.src/jump_inst.cc */
diff --git a/sim/ucsim/avr.src/logic_cl.h b/sim/ucsim/avr.src/logic_cl.h
new file mode 100644
index 0000000..636eba4
--- /dev/null
+++ b/sim/ucsim/avr.src/logic_cl.h
@@ -0,0 +1,9 @@
+/* avr.src/logic_cl.h */
+
+  virtual int ori_Rd_K(t_mem code);
+  virtual int andi_Rd_K(t_mem code);
+  virtual int and_Rd_Rr(t_mem code);
+  virtual int eor_Rd_Rr(t_mem code);
+  virtual int or_Rd_Rr(t_mem code);
+
+/* End of avr.src/logic_cl.h */
diff --git a/sim/ucsim/avr.src/logic_inst.cc b/sim/ucsim/avr.src/logic_inst.cc
new file mode 100644
index 0000000..3a2c935
--- /dev/null
+++ b/sim/ucsim/avr.src/logic_inst.cc
@@ -0,0 +1,142 @@
+/*
+ * Simulator of microcontrollers (logic_inst.cc)
+ *
+ * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#include "avrcl.h"
+#include "regsavr.h"
+
+
+/*
+ * Logical OR with Immediate
+ * ORI Rd,K 16<=d<=31 0<=K<=255
+ * 0110 KKKK dddd KKKK
+ *____________________________________________________________________________
+ */
+
+int
+cl_avr::ori_Rd_K(t_mem code)
+{
+  t_addr d;
+  t_mem K, data;
+
+  d= (code&0xf0)>>4;
+  K= ((code&0xf00)>>4)|(code&0xf);
+  data= K | ram->read(d);
+  ram->write(d+16, data);
+  set_zn0s(data);
+  return(resGO);
+}
+
+
+/*
+ * Logical AND with Immediate
+ * ANDI Rd,K 16<=d<=31 0<=K<=255
+ * 0111 KKKK dddd KKKK
+ *____________________________________________________________________________
+ */
+
+int
+cl_avr::andi_Rd_K(t_mem code)
+{
+  t_addr d;
+  t_mem K, data;
+
+  d= (code&0xf0)>>4;
+  K= ((code&0xf00)>>4)|(code&0xf);
+  data= K & ram->read(d);
+  ram->write(d+16, data);
+  set_zn0s(data);
+  return(resGO);
+}
+
+
+/*
+ * Logical AND
+ * AND Rd,Rr 0<=d<=31 0<=r<=31
+ * 0010 00rd dddd rrrr
+ *____________________________________________________________________________
+ */
+
+int
+cl_avr::and_Rd_Rr(t_mem code)
+{
+  t_addr d, r;
+  t_mem data;
+
+  d= (code&0x1f0)>>4;
+  r= ((code&0x200)>>5)|(code&0xf);
+  data= ram->read(d) & ram->read(r);
+  ram->write(d, data);
+  set_zn0s(data);
+  return(resGO);
+}
+
+
+/*
+ * Exclusive OR
+ * EOR Rd,Rr 0<=d<=31 0<=r<=31
+ * 0010 01rd dddd rrrr
+ *____________________________________________________________________________
+ */
+
+int
+cl_avr::eor_Rd_Rr(t_mem code)
+{
+  t_addr d, r;
+  t_mem data;
+
+  d= (code&0x1f0)>>4;
+  r= ((code&0x200)>>5)|(code&0xf);
+  data= ram->read(d) ^ ram->read(r);
+  ram->write(d, data);
+  set_zn0s(data);
+  return(resGO);
+}
+
+
+/*
+ * Logical OR
+ * OR Rd,Rr 0<=d<=31 0<=r<=31
+ * 0010 10rd dddd rrrr
+ *____________________________________________________________________________
+ */
+
+int
+cl_avr::or_Rd_Rr(t_mem code)
+{
+  t_addr d, r;
+  t_mem data;
+
+  d= (code&0x1f0)>>4;
+  r= ((code&0x200)>>5)|(code&0xf);
+  data= ram->read(d) | ram->read(r);
+  ram->write(d, data);
+  set_zn0s(data);
+  return(resGO);
+}
+
+
+/* End of avr.src/logic_inst.cc */
diff --git a/sim/ucsim/avr.src/move_cl.h b/sim/ucsim/avr.src/move_cl.h
new file mode 100644
index 0000000..46e11d2
--- /dev/null
+++ b/sim/ucsim/avr.src/move_cl.h
@@ -0,0 +1,40 @@
+/* avr.src/move_cl.h */
+
+  virtual int lpm(t_mem code);
+  virtual int elpm(t_mem code);
+  virtual int spm(t_mem code);
+  virtual int espm(t_mem code);
+  virtual int ldi_Rd_K(t_mem code);
+  virtual int movw_Rd_Rr(t_mem code);
+  virtual int lds_Rd_k(t_mem code);
+  virtual int ld_Rd_ZS(t_mem code);
+  virtual int ld_Rd_SZ(t_mem code);
+  virtual int lpm_Rd_Z(t_mem code);
+  virtual int lpm_Rd_ZS(t_mem code);
+  virtual int elpm_Rd_Z(t_mem code);
+  virtual int elpm_Rd_ZS(t_mem code);
+  virtual int ld_Rd_YS(t_mem code);
+  virtual int ld_Rd_SY(t_mem code);
+  virtual int ld_Rd_X(t_mem code);
+  virtual int ld_Rd_XS(t_mem code);
+  virtual int ld_Rd_SX(t_mem code);
+  virtual int pop_Rd(t_mem code);
+  virtual int sts_k_Rr(t_mem code);
+  virtual int st_ZS_Rr(t_mem code);
+  virtual int st_SZ_Rr(t_mem code);
+  virtual int st_YS_Rr(t_mem code);
+  virtual int st_SY_Rr(t_mem code);
+  virtual int st_X_Rr(t_mem code);
+  virtual int st_XS_Rr(t_mem code);
+  virtual int st_SX_Rr(t_mem code);
+  virtual int push_Rr(t_mem code);
+  virtual int swap_Rd(t_mem code);
+  virtual int ldd_Rd_Z_q(t_mem code);
+  virtual int ldd_Rd_Y_q(t_mem code);
+  virtual int std_Z_q_Rr(t_mem code);
+  virtual int std_Y_q_Rr(t_mem code);
+  virtual int in_Rd_A(t_mem code);
+  virtual int out_A_Rr(t_mem code);
+  virtual int mov_Rd_Rr(t_mem code);
+
+/* End of avr.src/move_cl.h */
diff --git a/sim/ucsim/avr.src/move_inst.cc b/sim/ucsim/avr.src/move_inst.cc
new file mode 100644
index 0000000..2c738d0
--- /dev/null
+++ b/sim/ucsim/avr.src/move_inst.cc
@@ -0,0 +1,755 @@
+/*
+ * Simulator of microcontrollers (move_inst.cc)
+ *
+ * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#include "avrcl.h"
+#include "regsavr.h"
+
+
+/*
+ * Load Program Memory
+ * LPM
+ * 1001 0101 110X 1000
+ *____________________________________________________________________________
+ */
+
+int
+cl_avr::lpm(t_mem code)
+{
+  t_addr addr;
+  t_mem data;
+
+  addr= ram->get(ZH)*256 + ram->get(ZL);
+  data= rom->read(addr);
+  vc.rd++;
+  if (addr & 1)
+    ram->/*write*/set(0, (data>>8)&0xff);
+  else
+    ram->/*write*/set(0, data&0xff);
+  tick(2);
+  return(resGO);
+}
+
+
+int
+cl_avr::elpm(t_mem code)
+{
+  return(resGO);
+}
+
+
+int
+cl_avr::spm(t_mem code)
+{
+  return(resGO);
+}
+
+
+int
+cl_avr::espm(t_mem code)
+{
+  return(resGO);
+}
+
+
+/*
+ * Load Immediate
+ * LDI Rd,K 16<=d<=31 0<=K<=255
+ * 1110 KKKK dddd KKKK
+ *____________________________________________________________________________
+ */
+
+int
+cl_avr::ldi_Rd_K(t_mem code)
+{
+  t_addr d;
+  t_mem K;
+
+  d= (code&0xf0)>>4;
+  K= ((code&0xf00)>>4)|(code&0xf);
+  ram->write(d+16, K);
+  return(resGO);
+}
+
+
+int
+cl_avr::movw_Rd_Rr(t_mem code)
+{
+  return(resGO);
+}
+
+
+/*
+ * Load Indirect From SRAM to Register using Index Z
+ * LDD Rd,Z+q 0<=d<=31, 0<=q<=63
+ * 10q0 qq0d dddd 0qqq
+ *____________________________________________________________________________
+ */
+
+int
+cl_avr::ldd_Rd_Z_q(t_mem code)
+{
+  int d, q;
+  t_addr z;
+
+  d= (code&0x1f0)>>4;
+  q= ((code&0x2000)>>8)|((code&0xc00)>>7)|(code&0x7);
+  z= ram->get(ZH)*256 + ram->get(ZL);
+  t_mem data= ram->read(z+q);
+  vc.rd++;
+  ram->write(d, data);
+  tick(1);
+  return(resGO);
+}
+
+
+/*
+ * Load Indirect From SRAM to Register using Index Y
+ * LDD Rd,Y+q 0<=d<=31, 0<=q<=63
+ * 10q0 qq0d dddd 1qqq
+ *____________________________________________________________________________
+ */
+
+int
+cl_avr::ldd_Rd_Y_q(t_mem code)
+{
+  int d, q;
+  t_addr y;
+
+  d= (code&0x1f0)>>4;
+  q= ((code&0x2000)>>8)|((code&0xc00)>>7)|(code&0x7);
+  y= ram->get(YH)*256 + ram->get(YL);
+  t_mem data= ram->read(y+q);
+  vc.rd++;
+  ram->write(d, data);
+  tick(1);
+  return(resGO);
+}
+
+
+/*
+ * Store Indirect From Register to SRAM using Index Z
+ * ST Z+q,Rr 0<=r<=31, 0<=q<=63
+ * 10q0 qq1r rrrr 0qqq
+ *____________________________________________________________________________
+ */
+
+int
+cl_avr::std_Z_q_Rr(t_mem code)
+{
+  int r, q;
+  t_addr z;
+
+  r= (code&0x1f0)>>4;
+  q= ((code&0x2000)>>8)|((code&0xc00)>>7)|(code&0x7);
+  z= ram->get(ZH)*256 + ram->get(ZL);
+  t_mem data= ram->read(r);
+  ram->write(z+q, data);
+  vc.wr++;
+  tick(1);
+  return(resGO);
+}
+
+
+/*
+ * Store Indirect From Register to SRAM using Index Y
+ * ST Y+q,Rr 0<=r<=31, 0<=q<=63
+ * 10q0 qq1r rrrr 1qqq
+ *____________________________________________________________________________
+ */
+
+int
+cl_avr::std_Y_q_Rr(t_mem code)
+{
+  int r, q;
+  t_addr y;
+
+  r= (code&0x1f0)>>4;
+  q= ((code&0x2000)>>8)|((code&0xc00)>>7)|(code&0x7);
+  y= ram->get(YH)*256 + ram->get(YL);
+  t_mem data= ram->read(r);
+  ram->write(y+q, data);
+  vc.wr++;
+  tick(1);
+  return(resGO);
+}
+
+
+/*
+ * Load Direct from SRAM
+ * LDS Rd,k 0<=d<=31, 0<=k<=65535
+ * 1001 000d dddd 0000
+ * kkkk kkkk kkkk kkkk
+ *____________________________________________________________________________
+ */
+
+int
+cl_avr::lds_Rd_k(t_mem code)
+{
+  t_addr d, k;
+
+  d= (code&0x1f0)>>4;
+  k= fetch();
+  t_mem data= ram->read(k);
+  ram->write(d, data);
+  tick(2);
+  return(resGO);
+}
+
+
+/*
+ * Load Indirect From SRAM to register using Index Z
+ * LD Rd,Z+ 0<=d<=31
+ * 1001 000d dddd 0001
+ *____________________________________________________________________________
+ */
+
+int
+cl_avr::ld_Rd_ZS(t_mem code)
+{
+  t_addr z, d;
+
+  d= (code&0x1f0)>>4;
+  z= ram->get(ZH)*256 + ram->get(ZL);
+  t_mem data= ram->read(z);
+  vc.rd++;
+  ram->write(d, data);
+  ram->set(ZL, data= (ram->get(ZL)+1)&0xff);
+  if (!data)
+    ram->set(ZH, (ram->get(ZH)+1)&0xff);
+  tick(1);
+  return(resGO);
+}
+
+
+/*
+ * Load Indirect From SRAM to register using Index Z
+ * LD Rd,-Z 0<=d<=31
+ * 1001 000d dddd 0010
+ *____________________________________________________________________________
+ */
+
+int
+cl_avr::ld_Rd_SZ(t_mem code)
+{
+  t_addr z, d;
+  t_mem data;
+
+  d= (code&0x1f0)>>4;
+  ram->set(ZL, z= (ram->get(ZL)-1)&0xff);
+  if (z == 0xff)
+    ram->set(ZH, (ram->get(ZH)-1)&0xff);
+  z= ram->get(ZH)*256 + z;
+  data= ram->read(z);
+  vc.rd++;
+  ram->write(d, data);
+  tick(1);
+  return(resGO);
+}
+
+
+int
+cl_avr::lpm_Rd_Z(t_mem code)
+{
+  return(resGO);
+}
+
+
+int
+cl_avr::lpm_Rd_ZS(t_mem code)
+{
+  return(resGO);
+}
+
+
+int
+cl_avr::elpm_Rd_Z(t_mem code)
+{
+  return(resGO);
+}
+
+
+int
+cl_avr::elpm_Rd_ZS(t_mem code)
+{
+  return(resGO);
+}
+
+
+/*
+ * Load Indirect From SRAM to register using Index Y
+ * LD Rd,Y+ 0<=d<=31
+ * 1001 000d dddd 1001
+ *____________________________________________________________________________
+ */
+
+int
+cl_avr::ld_Rd_YS(t_mem code)
+{
+  t_addr y, d;
+
+  d= (code&0x1f0)>>4;
+  y= ram->get(YH)*256 + ram->get(YL);
+  t_mem data= ram->read(y);
+  vc.rd++;
+  ram->write(d, data);
+  ram->set(YL, data= (ram->get(YL)+1)&0xff);
+  if (!data)
+    ram->set(YH, (ram->get(YH)+1)&0xff);
+  tick(1);
+  return(resGO);
+}
+
+
+/*
+ * Load Indirect From SRAM to register using Index Y
+ * LD Rd,-Y 0<=d<=31
+ * 1001 000d dddd 1010
+ *____________________________________________________________________________
+ */
+
+int
+cl_avr::ld_Rd_SY(t_mem code)
+{
+  t_addr y, d;
+  t_mem data;
+
+  d= (code&0x1f0)>>4;
+  ram->set(YL, y= (ram->get(YL)-1)&0xff);
+  if (y == 0xff)
+    ram->set(YH, (ram->get(YH)-1)&0xff);
+  y= ram->get(YH)*256 + y;
+  data= ram->read(y);
+  vc.rd++;
+  ram->write(d, data);
+  tick(1);
+  return(resGO);
+}
+
+
+/*
+ * Load Indirect From SRAM to register using Index X
+ * LD Rd,X 0<=d<=31
+ * 1001 000d dddd 1100
+ *____________________________________________________________________________
+ */
+
+int
+cl_avr::ld_Rd_X(t_mem code)
+{
+  t_addr x, d;
+
+  d= (code&0x1f0)>>4;
+  x= ram->get(XH)*256 + ram->get(XL);
+  t_mem data= ram->read(x);
+  vc.rd++;
+  ram->write(d, data);
+  tick(1);
+  return(resGO);
+}
+
+
+/*
+ * Load Indirect From SRAM to register using Index X
+ * LD Rd,X+ 0<=d<=31
+ * 1001 000d dddd 1101
+ *____________________________________________________________________________
+ */
+
+int
+cl_avr::ld_Rd_XS(t_mem code)
+{
+  t_addr x, d;
+
+  d= (code&0x1f0)>>4;
+  x= ram->get(XH)*256 + ram->get(XL);
+  t_mem data= ram->read(x);
+  vc.rd++;
+  ram->write(d, data);
+  ram->set(XL, data= (ram->get(XL)+1)&0xff);
+  if (!data)
+    ram->set(XH, (ram->get(XH)+1)&0xff);
+  tick(1);
+  return(resGO);
+}
+
+
+/*
+ * Load Indirect From SRAM to register using Index X
+ * LD Rd,-X 0<=d<=31
+ * 1001 000d dddd 1110
+ *____________________________________________________________________________
+ */
+
+int
+cl_avr::ld_Rd_SX(t_mem code)
+{
+  t_addr x, d;
+  t_mem data;
+
+  d= (code&0x1f0)>>4;
+  ram->set(XL, x= (ram->get(XL)-1)&0xff);
+  if (x == 0xff)
+    ram->set(XH, (ram->get(XH)-1)&0xff);
+  x= ram->get(XH)*256 + x;
+  data= ram->read(x);
+  vc.rd++;
+  ram->write(d, data);
+  tick(1);
+  return(resGO);
+}
+
+
+/*
+ * Pop Register from Stack
+ * POP Rd 0<=d<=31
+ * 1001 000d dddd 1111
+ *____________________________________________________________________________
+ */
+
+int
+cl_avr::pop_Rd(t_mem code)
+{
+  t_addr d;
+  t_mem D;
+
+  d= (code&0x1f0)>>4;
+  pop_data(&D);
+  ram->write(d, D);
+  tick(1);
+  
+  return(resGO);
+}
+
+
+/*
+ * Store Direct to SRAM
+ * STS k,Rr 0<=r<=31, 0<=k<=65535
+ * 1001 001r rrrr 0000
+ * kkkk kkkk kkkk kkkk
+ *____________________________________________________________________________
+ */
+
+int
+cl_avr::sts_k_Rr(t_mem code)
+{
+  t_addr r, k;
+
+  r= (code&0x1f0)>>4;
+  k= fetch();
+  t_mem data= ram->read(r);
+  ram->write(k, data);
+  vc.wr++;
+  tick(2);
+  return(resGO);
+}
+
+
+/*
+ * Store Indirect From Register to SRAM using Index Z
+ * ST Z+,Rr 0<=r<=63
+ * 1001 001r rrrr 0001
+ *____________________________________________________________________________
+ */
+
+int
+cl_avr::st_ZS_Rr(t_mem code)
+{ 
+  t_addr z, r;
+
+  r= (code&0x1f0)>>4;
+  z= ram->get(ZH)*256 + ram->get(ZL);
+  t_mem data= ram->read(r);
+  ram->write(z, data);
+  vc.wr++;
+  ram->set(ZL, data= (ram->get(ZL)+1)&0xff);
+  if (!data)
+    ram->set(ZH, (ram->get(ZH)+1)&0xff);
+  tick(1);
+  return(resGO);
+}
+
+
+/*
+ * Store Indirect From Register to SRAM using Index Z
+ * ST -Z,Rr 0<=r<=63
+ * 1001 001r rrrr 0010
+ *____________________________________________________________________________
+ */
+
+int
+cl_avr::st_SZ_Rr(t_mem code)
+{
+  t_addr z, r;
+  t_mem data;
+
+  r= (code&0x1f0)>>4;
+  ram->set(ZL, z= (ram->get(ZL)-1)&0xff);
+  if (z == 0xff)
+    ram->set(ZH, (ram->get(ZH)-1)&0xff);
+  z= ram->get(ZH)*256 + z;
+  data= ram->read(r);
+  vc.wr++;
+  ram->write(z, data);
+  tick(1);
+  return(resGO);
+}
+
+
+/*
+ * Store Indirect From Register to SRAM using Index Y
+ * ST Y+,Rr 0<=r<=63
+ * 1001 001r rrrr 1001
+ *____________________________________________________________________________
+ */
+
+int
+cl_avr::st_YS_Rr(t_mem code)
+{
+  t_addr y, r;
+
+  r= (code&0x1f0)>>4;
+  y= ram->get(YH)*256 + ram->get(YL);
+  t_mem data= ram->read(r);
+  ram->write(y, data);
+  vc.wr++;
+  ram->set(YL, data= (ram->get(YL)+1)&0xff);
+  if (!data)
+    ram->set(YH, (ram->get(YH)+1)&0xff);
+  tick(1);
+  return(resGO);
+}
+
+
+/*
+ * Store Indirect From Register to SRAM using Index Y
+ * ST -Y,Rr 0<=r<=63
+ * 1001 001r rrrr 1010
+ *____________________________________________________________________________
+ */
+
+int
+cl_avr::st_SY_Rr(t_mem code)
+{
+  t_addr y, r;
+  t_mem data;
+
+  r= (code&0x1f0)>>4;
+  ram->set(YL, y= (ram->get(YL)-1)&0xff);
+  if (y == 0xff)
+    ram->set(YH, (ram->get(YH)-1)&0xff);
+  y= ram->get(YH)*256 + y;
+  data= ram->read(r);
+  ram->write(y, data);
+  vc.wr++;
+  tick(1);
+  return(resGO);
+}
+
+
+/*
+ * Store Indirect From Register to SRAM using Index X
+ * ST X,Rr 0<=r<=31
+ * 1001 001r rrrr 1100
+ *____________________________________________________________________________
+ */
+
+int
+cl_avr::st_X_Rr(t_mem code)
+{
+  int r;
+  t_addr x;
+
+  r= (code&0x1f0)>>4;
+  x= ram->get(XH)*256 + ram->get(XL);
+  t_mem data= ram->read(r);
+  ram->write(x, data);
+  vc.wr++;
+  tick(1);
+  return(resGO);
+}
+
+
+/*
+ * Store Indirect From Register to SRAM using Index X
+ * ST X+,Rr 0<=r<=63
+ * 1001 001r rrrr 1101
+ *____________________________________________________________________________
+ */
+
+int
+cl_avr::st_XS_Rr(t_mem code)
+{
+  t_addr x, r;
+
+  r= (code&0x1f0)>>4;
+  x= ram->get(XH)*256 + ram->get(XL);
+  t_mem data= ram->read(r);
+  ram->write(x, data);
+  vc.wr++;
+  ram->set(XL, data= (ram->get(XL)+1)&0xff);
+  if (!data)
+    ram->set(XH, (ram->get(XH)+1)&0xff);
+  tick(1);
+  return(resGO);
+}
+
+
+/*
+ * Store Indirect From Register to SRAM using Index X
+ * ST -X,Rr 0<=r<=63
+ * 1001 001r rrrr 1110
+ *____________________________________________________________________________
+ */
+
+int
+cl_avr::st_SX_Rr(t_mem code)
+{
+  t_addr x, r;
+  t_mem data;
+
+  r= (code&0x1f0)>>4;
+  ram->set(XL, x= (ram->get(XL)-1)&0xff);
+  if (x == 0xff)
+    ram->set(XH, (ram->get(XH)-1)&0xff);
+  x= ram->get(XH)*256 + x;
+  data= ram->read(r);
+  ram->write(x, data);
+  vc.wr++;
+  tick(1);
+  return(resGO);
+}
+
+
+/*
+ * Push register on Stack
+ * PUSH Rr 0<=r<=31
+ * 1001 001d dddd 1111
+ *____________________________________________________________________________
+ */
+
+int
+cl_avr::push_Rr(t_mem code)
+{
+  t_addr d;
+  t_mem D;
+
+  d= (code&0x1f0)>>4;
+  D= ram->read(d);
+  push_data(D);
+  tick(1);
+
+  return(resGO);
+}
+
+
+/*
+ * Swap Nibbles
+ * SWAP Rd 0<=d<=31
+ * 1001 010d dddd 0010
+ *____________________________________________________________________________
+ */
+
+int
+cl_avr::swap_Rd(t_mem code)
+{
+  t_addr d;
+  t_mem data, temp;
+
+  d= (code&0x1f0)>>4;
+  data= ram->read(d);
+  temp= (data>>4)&0xf;
+  data= (data<<4)|temp;
+  ram->write(d, data);
+  return(resGO);
+}
+
+
+/*
+ * Load an I/O Port to Register
+ * IN Rd,P 0<=d<=31 0<=P<=63
+ * 1011 0PPd dddd PPPP
+ *____________________________________________________________________________
+ */
+
+int
+cl_avr::in_Rd_A(t_mem code)
+{
+  t_mem P, data;
+  t_addr d;
+  
+  P= ((code&0x600)>>5)|(code&0xf);
+  d= (code&0x1f0)>>4;
+  data= ram->read(P+0x20);
+  vc.rd++;
+  ram->write(d, data);
+  return(resGO);
+}
+
+
+/*
+ * Store Register to I/O Port
+ * OUT P,Rr 0<=r<=31 0<=P<=63
+ * 1011 1PPr rrrr PPPP
+ *____________________________________________________________________________
+ */
+
+int
+cl_avr::out_A_Rr(t_mem code)
+{
+  t_mem P, data;
+  t_addr r;
+  
+  P= ((code&0x600)>>5)|(code&0xf);
+  r= (code&0x1f0)>>4;
+  data= ram->read(r);
+  ram->write(P+0x20, data);
+  vc.wr++;
+  return(resGO);
+}
+
+
+/*
+ * Copy Register
+ * MOV Rd,Rr 0<=d<=31 0<=r<=31
+ * 0010 11rd dddd rrrr
+ *____________________________________________________________________________
+ */
+
+int
+cl_avr::mov_Rd_Rr(t_mem code)
+{
+  t_addr d, r;
+  
+  d= (code&0x1f0)>>4;
+  r= ((code&0x200)>>5)|(code&0xf);
+  t_mem data= ram->read(r);
+  ram->write(d, data);
+  return(resGO);
+}
+
+
+/* End of avr.src/move_inst.cc */
diff --git a/sim/ucsim/avr.src/port.cc b/sim/ucsim/avr.src/port.cc
new file mode 100644
index 0000000..0cb2638
--- /dev/null
+++ b/sim/ucsim/avr.src/port.cc
@@ -0,0 +1,55 @@
+/*
+ * Simulator of microcontrollers (port.cc)
+ *
+ * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+
+#include <stdio.h>
+
+#include "portcl.h"
+
+
+cl_port::cl_port(class cl_uc *auc):
+  cl_hw(auc, HW_PORT, 0, "port")
+{
+  //uc->register_hw_read(MEM_SFR, 2, this);
+  //uc->register_hw_read(MEM_SFR, 4, this);
+}
+
+/*ulong
+cl_port::read(class cl_mem *mem, long addr)
+{
+  switch (addr)
+    {
+    case 2:
+      return(22);
+    case 4:
+      return(44);
+    }
+  return(cl_hw::read(mem, addr));
+}*/
+
+
+/* End of avr.src/port.cc */
diff --git a/sim/ucsim/avr.src/portcl.h b/sim/ucsim/avr.src/portcl.h
new file mode 100644
index 0000000..37e4369
--- /dev/null
+++ b/sim/ucsim/avr.src/portcl.h
@@ -0,0 +1,45 @@
+/*
+ * Simulator of microcontrollers (portcl.h)
+ *
+ * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#ifndef PORTCL_HEADER
+#define PORTCL_HEADER
+
+#include "port_hwcl.h"
+
+
+class cl_port: public cl_hw
+{
+public:
+  cl_port(class cl_uc *auc);
+
+  //virtual ulong read(class cl_mem *mem, long addr);
+};
+
+
+#endif
+
+/* End of avr.src/portcl.h */
diff --git a/sim/ucsim/avr.src/regsavr.h b/sim/ucsim/avr.src/regsavr.h
new file mode 100644
index 0000000..a0d72b1
--- /dev/null
+++ b/sim/ucsim/avr.src/regsavr.h
@@ -0,0 +1,113 @@
+/*
+ * Simulator of microcontrollers (regsavr.h)
+ *
+ * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#ifndef REGSAVR_HEADER
+#define REGSAVR_HEADER
+
+/*
+ * Registers, absolute data space addresses
+ */
+
+#define X	0x001a
+#define XL	0x001a
+#define XH	0x001b
+#define Y	0x001c
+#define YL	0x001c
+#define YH	0x001d
+#define Z	0x001e
+#define ZL	0x001e
+#define ZH	0x001f
+
+#define ADCL	0x0024
+#define ADCH	0x0025
+#define ADCSR	0x0026
+#define ADMUX	0x0027
+#define ACSR	0x0028
+#define UBRR	0x0029
+#define UCR	0x002A
+#define USR	0x002B
+#define UDR	0x002C
+#define SPCR	0x002D
+#define SPSR	0x002E
+#define SPDR	0x002F
+#define PIND	0x0030
+#define DDRD	0x0031
+#define PORTD	0x0032
+#define PINC	0x0033
+#define DDRC	0x0034
+#define PORTC	0x0035
+#define PINB	0x0036
+#define DDRB	0x0037
+#define PORTB	0x0038
+#define PINA	0x0039
+#define DDRA	0x003A
+#define PORTA	0x003B
+#define EECR	0x003C
+#define EEDR	0x003D
+#define EEARL	0x003E
+#define EEARH	0x003E
+#define WDTCR	0x0041
+#define ASSR	0x0042
+#define OCR2	0x0043
+#define TCNT2	0x0044
+#define TCCR2	0x0045
+#define ICR1L	0x0046
+#define ICR1H	0x0047
+#define OCR1BL	0x0048
+#define OCR1BH	0x0049
+#define OCR1AL	0x004A
+#define OCR1AH	0x004B
+#define TCNT1L	0x004C
+#define TCNT1H	0x004D
+#define TCCR1B	0x004E
+#define TCCR1A	0x004F
+#define TCNT0	0x0052
+#define TCCR0	0x0053
+#define MCUSR	0x0054
+#define MCUCR	0x0055
+#define TIFR	0x0058
+#define TIMSK	0x0059
+#define GIFR	0x005A
+#define GIMSK	0x005B
+#define SPL	0x005D
+#define SPH	0x005E
+#define SREG	0x005F
+
+/* Bits of SREG */
+#define BIT_I	0x80
+#define BIT_T	0x40
+#define BIT_H	0x20
+#define BIT_S	0x10
+#define BIT_V	0x08
+#define BIT_N	0x04
+#define BIT_Z	0x02
+#define BIT_C	0x01
+
+
+#endif
+
+/* End of avr.src/regsavr.h */
diff --git a/sim/ucsim/avr.src/savr.cc b/sim/ucsim/avr.src/savr.cc
new file mode 100644
index 0000000..b756eae
--- /dev/null
+++ b/sim/ucsim/avr.src/savr.cc
@@ -0,0 +1,59 @@
+/*
+ * Simulator of microcontrollers (savr.cc)
+ *
+ * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#include <stdio.h>
+
+  // prj
+#include "globals.h"
+
+// sim.src
+#include "appcl.h"
+
+// local
+#include "simavrcl.h"
+
+
+int
+main(int argc, char *argv[])
+{
+  class cl_sim *sim;
+  
+  application= new cl_app();
+  application->init(argc, argv);
+  sim= new cl_simavr(application);
+  if (sim->init())
+    sim->state|= SIM_QUIT;
+  application->set_simulator(sim);
+  //sim->main();
+  application->run();
+  application->done();
+  delete application;
+  return(0);
+}
+
+
+/* End of avr.src/savr.cc */
diff --git a/sim/ucsim/avr.src/simavr.cc b/sim/ucsim/avr.src/simavr.cc
new file mode 100644
index 0000000..58b8d8d
--- /dev/null
+++ b/sim/ucsim/avr.src/simavr.cc
@@ -0,0 +1,50 @@
+/*
+ * Simulator of microcontrollers (simavr.cc)
+ *
+ * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+
+//#include <ctype.h>
+
+// sim.src
+#include "appcl.h"
+
+// local
+#include "simavrcl.h"
+#include "avrcl.h"
+
+
+cl_simavr::cl_simavr(class cl_app *the_app):
+  cl_sim(the_app)
+{}
+
+class cl_uc *
+cl_simavr::mk_controller(void)
+{
+  return(new cl_avr(this));
+}
+
+
+/* End of avr.src/simavr.cc */
diff --git a/sim/ucsim/avr.src/simavrcl.h b/sim/ucsim/avr.src/simavrcl.h
new file mode 100644
index 0000000..70347ed
--- /dev/null
+++ b/sim/ucsim/avr.src/simavrcl.h
@@ -0,0 +1,45 @@
+/*
+ * Simulator of microcontrollers (simavrcl.h)
+ *
+ * Copyright (C) 1999,99 Drotos Daniel, Talker Bt.
+ * 
+ * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
+ *
+ */
+
+/* This file is part of microcontroller simulator: ucsim.
+
+UCSIM is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+UCSIM is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with UCSIM; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+/*@1@*/
+
+#ifndef SIMAVRCL_HEADER
+#define SIMAVRCL_HEADER
+
+#include "simcl.h"
+
+
+class cl_simavr: public cl_sim
+{
+public:
+  cl_simavr(class cl_app *the_app);
+
+  virtual class cl_uc *mk_controller(void);
+};
+
+
+#endif
+
+/* End of avr.src/simavrcl.h */
diff --git a/sim/ucsim/avr.src/test_arith.asm b/sim/ucsim/avr.src/test_arith.asm
new file mode 100644
index 0000000..cb097af
--- /dev/null
+++ b/sim/ucsim/avr.src/test_arith.asm
@@ -0,0 +1,81 @@
+	nop
+	clr	r0
+	out	$3f,r0
+	
+;	jmp	t2
+
+	ldi	r16,$12
+	mov	r2,r16
+	inc	r16
+	inc	r2
+	ldi	r17,$ff
+	inc	r17
+	ldi	r18,$7f
+	inc	r18
+	nop
+t1:
+	ldi	r16,10		; 10+20
+	ldi	r17,20
+	add	r16,r17
+	in	r0,$3f
+	mov	r18,r16
+	ldi	r16,127		; 127+10
+	ldi	r17,10
+	add	r16,r17
+	in	r1,$3f
+	mov	r19,r16
+	ldi	r16,255		; 255+2
+	ldi	r17,2
+	add	r16,r17
+	in	r2,$3f
+	mov	r20,r16
+	ldi	r16,255		; 255+1
+	ldi	r17,1
+	add	r16,r17
+	in	r3,$3f
+	mov	r21,r16
+	ldi	r16,10		; 10+6
+	ldi	r17,6
+	add	r16,r17
+	in	r4,$3f
+	mov	r22,r16
+	nop
+	ldi	r16,-10		; -10-20
+	ldi	r17,-20
+	add	r16,r17
+	in	r5,$3f
+	mov	r23,r16
+	ldi	r16,-120	; -120-30
+	ldi	r17,-30
+	add	r16,r17
+	in	r6,$3f
+	mov	r24,r16
+	nop
+	ldi	r16,254		; 254+1 +0
+	ldi	r17,1
+	clc
+	adc	r16,r17
+	in	r7,$3f
+	mov	r25,r16
+	ldi	r16,254		; 254+1 +1
+	sec
+	adc	r16,r17
+	in	r8,$3f
+	mov	r26,r16
+	nop
+t2:
+	ldi	r24,0
+	ldi	r25,0
+	adiw	r24,20
+	ldi	r26,low($0fff)
+	ldi	r27,high($0fff)
+	adiw	r26,2
+	ldi	r28,low($fff0)
+	ldi	r29,high($fff0)
+	adiw	r28,$f
+	adiw	r28,1
+done:
+	jmp	done
+		
+copyright:
+	.db	"(c) 2000 Talker Bt."
diff --git a/sim/ucsim/avr.src/test_bit.asm b/sim/ucsim/avr.src/test_bit.asm
new file mode 100644
index 0000000..687e539
--- /dev/null
+++ b/sim/ucsim/avr.src/test_bit.asm
@@ -0,0 +1,87 @@
+	jmp	t11
+	
+	ldi	r17,0
+	sbi	0,0
+	sbis	0,0
+	ldi	r17,1
+	cbi	0,0
+	sbis	0,0
+	ldi	r17,2
+	nop
+	
+	ldi	r17,0
+	cbi	0,0
+	sbic	0,0
+	ldi	r17,1
+	sbi	0,0
+	sbic	0,0
+	ldi	r17,2
+	nop
+	
+	clr	r0
+	out	$3f,r0
+	
+	sec
+	sen
+	sez
+	sei
+	ses
+	sev
+	set
+	seh
+
+	;ld	sreg,$ff
+
+	clc
+	cln
+	clz
+	cli
+	cls
+	clv
+	clt
+	clh
+
+	nop
+
+	sbi	0,0
+	sbi	0,1
+	sbi	0,2
+	sbi	0,3
+	sbi	0,4
+	sbi	0,5
+	sbi	0,6
+	sbi	0,7
+	nop
+	sbi	$10,4
+	sbi	$1f,7
+	nop
+	cbi	0,0
+	cbi	0,1
+	cbi	0,2
+	cbi	0,3
+	cbi	0,4
+	cbi	0,5
+	cbi	0,6
+	cbi	0,7
+t1:
+	ldi	r16,$55
+	bst	r16,0
+	bst	r16,1
+	bst	r16,2
+	bst	r16,3
+	bst	r16,4
+	bst	r16,5
+	bst	r16,6
+	bst	r16,7
+t11:
+	ldi	r16,0
+	set
+	bld	r16,0
+	ldi	r16,1
+	clt
+	bld	r16,0
+	
+	nop
+
+copyright:
+	.db	"(c) 1999,2000 Talker Bt."
diff --git a/sim/ucsim/avr.src/test_call.asm b/sim/ucsim/avr.src/test_call.asm
new file mode 100644
index 0000000..753a686
--- /dev/null
+++ b/sim/ucsim/avr.src/test_call.asm
@@ -0,0 +1,14 @@
+	nop
+	ldi	r16,$ff
+	out	$3d,r16
+	ldi	r16,$01
+	out	$3e,r16
+	nop
+	call	sub1
+	nop
+
+sub1:	nop
+	ret
+	
+copyright:
+	.db	"(c) 2000 talker Bt."
diff --git a/sim/ucsim/avr.src/test_dis.asm b/sim/ucsim/avr.src/test_dis.asm
new file mode 100644
index 0000000..71fd621
--- /dev/null
+++ b/sim/ucsim/avr.src/test_dis.asm
@@ -0,0 +1,167 @@
+	nop
+
+	adc	r1,r31
+	add	r2,r30
+	adiw	r24,54
+	and	r4,r29
+	andi	r16,253
+	asr	r5
+	bclr	7
+	bld	r6,6
+lab1:	nop
+	brbc	0,lab1
+	brbc	1,lab1
+	brbc	2,lab1
+	brbc	3,lab1
+	brbc	4,lab1
+	brbc	5,lab1
+	brbc	6,lab1
+	brbc	7,lab1
+lab2:	brbs	0,lab3
+	brbs	1,lab3
+	brbs	2,lab3
+	brbs	3,lab3
+	brbs	4,lab3
+	brbs	5,lab3
+	brbs	6,lab3
+	brbs	7,lab3
+lab3:	brcc	lab4
+	brcc	lab3
+lab4:	brcs	lab5
+	brcs	lab4
+lab5:	breq	lab6
+	breq	lab5
+lab6:	brge	lab7
+	brge	lab6
+lab7:	brhc	lab8
+	brhc	lab7
+lab8:	brhs	lab9
+	brhs	lab8
+lab9:	brid	lab10
+	brid	lab9
+lab10:	brie	lab11
+	brie	lab10
+lab11:	brlo	lab12
+	brlo	lab11
+lab12:	brlt	lab13
+	brlt	lab12
+lab13:	brmi	lab14
+	brmi	lab13
+lab14:	brne	lab15
+	brne	lab14
+lab15:	brpl	lab16
+	brpl	lab15
+lab16:	brsh	lab17
+	brsh	lab16
+lab17:	brtc	lab18
+	brtc	lab17
+lab18:	brts	lab19
+	brts	lab18
+lab19:	brvc	lab20
+	brvc	lab19
+lab20:	brvs	lab21
+	brvs	lab20
+lab21:	bset	6
+	bst	r7,5
+	call	0
+	call	lab1
+	call	lab22
+	nop
+lab22:	cbi	$8,4
+	
+	clc
+	clh
+	cli
+	cln
+	cls
+	clt
+	clv
+	clz
+
+	com	r9
+	cp	r10,r11
+	cpc	r12,r13
+	cpi	r16,95
+	cpse	r14,r15
+	dec	r17
+	eor	r18,r19
+	icall
+	ijmp
+	in	r20,9
+	inc	r21
+	jmp	lab1
+	jmp	lab23
+	ld	r22,x
+	ld	r23,x+
+	ld	r24,-x
+	ld	r25,y
+	ld	r26,y+
+	ld	r27,-y
+	ldd	r28,y+63
+	ld	r29,z
+	ld	r30,z+
+	ld	r31,-z
+	ldd	r0,z+1
+	ldi	r17,170
+	lds	r1,12345
+	lpm
+	;elpm
+	lsr	r2
+	mov	r3,r4
+	mul	r5,r6
+	neg	r7
+	or	r8,r9
+	ori	r18,85
+	out	9,r10
+	pop	r11
+	push	r12
+	rcall	lab1
+	rcall	lab23
+	nop
+lab23:	ret
+	reti
+	rjmp	lab23
+	rjmp	lab24
+	nop
+lab24:	ror	r13
+	sbc	r14,r15
+	sbci	r19,83
+	sbi	10,2
+	sbic	11,3
+	sbis	12,4
+	sbiw	r26,60
+	sbr	r19,254
+	sbrc	r20,5
+	sbrs	r21,6
+	sec
+	seh
+	sei
+	sen
+	ses
+	set
+	sev
+	sez
+
+	ser	r22	
+	sleep
+	st	x,r23
+	st	x+,r24
+	st	-x,r25
+	st	y,r26
+	st	y+,r27
+	st	-y,r28
+	std	y+34,r29
+	st	z,r30
+	st	z+,r31
+	st	-z,r0
+	st	z+35,r1
+	sts	$ff00,r2
+	sub	r3,r4
+	subi	r31,123
+	swap	r4
+	wdr
+	
+	nop
+a:	jmp	a
+
+	.db	"(c) 1999 Talker Bt."
diff --git a/sim/ucsim/avr.src/test_jmp.asm b/sim/ucsim/avr.src/test_jmp.asm
new file mode 100644
index 0000000..3b6a1d4
--- /dev/null
+++ b/sim/ucsim/avr.src/test_jmp.asm
@@ -0,0 +1,62 @@
+	nop
+	jmp	skip
+	nop
+skip:
+	ldi	r16,12
+	ldi	r17,13
+	cpse	r16,r17
+	inc	r16
+	cpse	r16,r17
+	inc	r16
+	inc	r16
+	nop
+	nop
+	ldi	r16,0
+	sbrc	r16,0
+	nop
+	sbrc	r16,1
+	jmp	0
+	sbrs	r16,2
+	ldi	r16,$ff
+	sbrs	r16,7
+	nop
+	sbrs	r16,6
+	jmp	0
+	nop	
+t0:
+;	rjmp	-$100
+	bclr	0
+	brbs	0,b0_1
+	brbc	0,b0_1
+	nop
+b2_0:
+	nop
+b1_0:
+	bclr	1
+	brbs	1,b1_1
+	brbc	1,b1_1
+	nop
+b0_1:
+	bset	0
+	brbc	0,b1_0
+	brbs	0,b1_0
+	nop
+b1_1:
+	bset	1
+	brbc	1,b2_0
+	brbs	1,b2_0
+	nop
+t1:
+	ldi	r30,low(t11)
+	ldi	r31,high(t11)
+	ijmp
+	nop
+t11:
+	rjmp	t2
+	nop
+t2:
+	rjmp	t0
+	nop
+
+copyright:
+	.db	"(c) 2000 talker Bt."
diff --git a/sim/ucsim/avr.src/test_mov.asm b/sim/ucsim/avr.src/test_mov.asm
new file mode 100644
index 0000000..315681c
--- /dev/null
+++ b/sim/ucsim/avr.src/test_mov.asm
@@ -0,0 +1,93 @@
+;X	=	0x001a
+;XL	=	0x001a
+;XH	=	0x001b
+;Y	=	0x001c
+;YL	=	0x001c
+;YH	=	0x001d
+;Z	=	0x001e
+;ZL	=	0x001e
+.equ	ZH	=$1f
+
+	jmp	t42
+	
+	ldi	r16,0
+	ldi	r16,16
+	ldi	r17,0
+	ldi	r17,17
+	ldi	r30,0
+	ldi	r30,30
+	ldi	r30,255
+t1:
+	ldi	r30,low(copyright)
+	ldi	r31,high(copyright)
+	lpm
+	ldi	r30,low(copyright+1)
+	ldi	r31,high(copyright+1)
+	lpm
+t2:
+	ldi	r31,0
+	ldi	r30,100
+	ldi	r16,$65
+	std	z+1,r16
+	std	z+63,r16
+	ldd	r1,z+1
+	ldd	r2,z+63
+t21:
+	ldi	r31,0
+	ldi	r30,255
+	ldi	r18,88
+	std	z,r18
+	ld	r6,z+
+	ld	r7,-z
+t3:
+	ldi	r29,0
+	ldi	r28,100
+	ldi	r17,$45
+	std	y+2,r17
+	std	y+62,r17
+	ldd	r3,y+2
+	ldd	r4,y+62
+t31:
+	ldi	r29,0
+	ldi	r28,255
+	ldi	r19,$55
+	std	y,r19
+	ld	r8,y+
+	ld	r9,-y
+t32:
+	ldi	r27,0
+	ldi	r26,255
+	ldi	r19,$70
+	st	x,r19
+	ld	r20,x
+	ld	r10,x+
+	ld	r11,-x
+t4:
+	ldi	r31,0
+	ldi	r30,255
+	ldi	r16,66
+	ldi	r17,77
+	st	z+,r16
+	st	-z,r17
+t41:
+	ldi	r29,0
+	ldi	r28,255
+	ldi	r18,88
+	ldi	r19,99
+	st	y+,r18
+	st	-y,r19
+t42:
+	ldi	r27,0
+	ldi	r26,255
+	ldi	r20,22
+	ldi	r21,11
+	st	x+,r20
+	st	-x,r21
+
+	lds	r5,162
+	sts	161,r5
+
+	nop
+	
+copyright:
+	.db	"(c) 2000 Talker Bt."