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| author | Xavier ASUS <xavi92psx@gmail.com> | 2019-10-18 00:31:54 +0200 |
|---|---|---|
| committer | Xavier ASUS <xavi92psx@gmail.com> | 2019-10-18 00:31:54 +0200 |
| commit | 268a53de823a6750d6256ee1fb1e7707b4b45740 (patch) | |
| tree | 42c1799a9a82b2f7d9790ee9fe181d72a7274751 /device/lib/stm8/_fseq.lst | |
| download | sdcc-gas-268a53de823a6750d6256ee1fb1e7707b4b45740.tar.gz | |
sdcc-3.9.0 fork implementing GNU assembler syntax
This fork aims to provide better support for stm8-binutils
Diffstat (limited to 'device/lib/stm8/_fseq.lst')
| -rw-r--r-- | device/lib/stm8/_fseq.lst | 118 |
1 files changed, 118 insertions, 0 deletions
diff --git a/device/lib/stm8/_fseq.lst b/device/lib/stm8/_fseq.lst new file mode 100644 index 0000000..32c04fb --- /dev/null +++ b/device/lib/stm8/_fseq.lst @@ -0,0 +1,118 @@ + 1 ;-------------------------------------------------------- + 2 ; File Created by SDCC : free open source ANSI-C Compiler + 3 ; Version 3.9.3 #11345 (Linux) + 4 ;-------------------------------------------------------- + 5 .module _fseq + 6 .optsdcc -mstm8 + 7 + 8 ;-------------------------------------------------------- + 9 ; Public variables in this module + 10 ;-------------------------------------------------------- + 11 .globl ___fseq + 12 ;-------------------------------------------------------- + 13 ; ram data + 14 ;-------------------------------------------------------- + 15 .area DATA + 16 ;-------------------------------------------------------- + 17 ; ram data + 18 ;-------------------------------------------------------- + 19 .area INITIALIZED + 20 ;-------------------------------------------------------- + 21 ; absolute external ram data + 22 ;-------------------------------------------------------- + 23 .area DABS (ABS) + 24 + 25 ; default segment ordering for linker + 26 .area HOME + 27 .area GSINIT + 28 .area GSFINAL + 29 .area CONST + 30 .area INITIALIZER + 31 .area CODE + 32 + 33 ;-------------------------------------------------------- + 34 ; global & static initialisations + 35 ;-------------------------------------------------------- + 36 .area HOME + 37 .area GSINIT + 38 .area GSFINAL + 39 .area GSINIT + 40 ;-------------------------------------------------------- + 41 ; Home + 42 ;-------------------------------------------------------- + 43 .area HOME + 44 .area HOME + 45 ;-------------------------------------------------------- + 46 ; code + 47 ;-------------------------------------------------------- + 48 .area CODE + 49 ; ../_fseq.c: 83: __fseq (float a1, float a2) + 50 ; ----------------------------------------- + 51 ; function __fseq + 52 ; ----------------------------------------- + 000000 53 ___fseq: + 000000 52 10 [ 2] 54 sub sp, #16 + 55 ; ../_fseq.c: 87: fl1.f = a1; + 000002 16 15 [ 2] 56 ldw y, (0x15, sp) + 000004 17 03 [ 2] 57 ldw (0x03, sp), y + 000006 16 13 [ 2] 58 ldw y, (0x13, sp) + 000008 17 01 [ 2] 59 ldw (0x01, sp), y + 60 ; ../_fseq.c: 88: fl2.f = a2; + 00000A 16 19 [ 2] 61 ldw y, (0x19, sp) + 00000C 17 07 [ 2] 62 ldw (0x07, sp), y + 00000E 16 17 [ 2] 63 ldw y, (0x17, sp) + 000010 17 05 [ 2] 64 ldw (0x05, sp), y + 65 ; ../_fseq.c: 90: if (fl1.l == fl2.l) + 000012 16 03 [ 2] 66 ldw y, (0x03, sp) + 000014 17 0B [ 2] 67 ldw (0x0b, sp), y + 000016 16 01 [ 2] 68 ldw y, (0x01, sp) + 000018 17 09 [ 2] 69 ldw (0x09, sp), y + 00001A 16 07 [ 2] 70 ldw y, (0x07, sp) + 00001C 17 0F [ 2] 71 ldw (0x0f, sp), y + 00001E 16 05 [ 2] 72 ldw y, (0x05, sp) + 000020 1E 0B [ 2] 73 ldw x, (0x0b, sp) + 000022 13 0F [ 2] 74 cpw x, (0x0f, sp) + 000024 26 09 [ 1] 75 jrne 00102$ + 000026 93 [ 1] 76 ldw x, y + 000027 13 09 [ 2] 77 cpw x, (0x09, sp) + 000029 26 04 [ 1] 78 jrne 00102$ + 79 ; ../_fseq.c: 91: return (1); + 00002B A6 01 [ 1] 80 ld a, #0x01 + 00002D 20 2A [ 2] 81 jra 00105$ + 00002F 82 00102$: + 83 ; ../_fseq.c: 92: if (((fl1.l | fl2.l) & 0x7FFFFFFF) == 0) + 00002F 16 03 [ 2] 84 ldw y, (0x03, sp) + 000031 17 0F [ 2] 85 ldw (0x0f, sp), y + 000033 16 01 [ 2] 86 ldw y, (0x01, sp) + 000035 17 0D [ 2] 87 ldw (0x0d, sp), y + 000037 1E 07 [ 2] 88 ldw x, (0x07, sp) + 000039 16 05 [ 2] 89 ldw y, (0x05, sp) + 00003B 9F [ 1] 90 ld a, xl + 00003C 1A 10 [ 1] 91 or a, (0x10, sp) + 00003E 02 [ 1] 92 rlwa x + 00003F 1A 0F [ 1] 93 or a, (0x0f, sp) + 000041 95 [ 1] 94 ld xh, a + 000042 90 9F [ 1] 95 ld a, yl + 000044 1A 0E [ 1] 96 or a, (0x0e, sp) + 000046 90 02 [ 1] 97 rlwa y + 000048 1A 0D [ 1] 98 or a, (0x0d, sp) + 00004A A4 7F [ 1] 99 and a, #0x7f + 00004C 90 95 [ 1] 100 ld yh, a + 00004E 5D [ 2] 101 tnzw x + 00004F 26 07 [ 1] 102 jrne 00104$ + 000051 90 5D [ 2] 103 tnzw y + 000053 26 03 [ 1] 104 jrne 00104$ + 105 ; ../_fseq.c: 93: return (1); + 000055 A6 01 [ 1] 106 ld a, #0x01 + 107 ; ../_fseq.c: 94: return (0); + 000057 21 108 .byte 0x21 + 000058 109 00104$: + 000058 4F [ 1] 110 clr a + 000059 111 00105$: + 112 ; ../_fseq.c: 95: } + 000059 5B 10 [ 2] 113 addw sp, #16 + 00005B 81 [ 4] 114 ret + 115 .area CODE + 116 .area CONST + 117 .area INITIALIZER + 118 .area CABS (ABS) |