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authorXavier ASUS <xavi92psx@gmail.com>2019-10-23 03:38:32 +0200
committerXavier ASUS <xavi92psx@gmail.com>2019-10-23 03:38:32 +0200
commit2cece67cb5af0339e4ab1f18b0bce2f0b4e6ebdd (patch)
treeb2fbf4e99f194213527304c9189abe65c163ac0b /device/lib/stm8/_divulonglong.lst
parented26eb00026800d1d2ff6289627216c7d1f0d459 (diff)
downloadsdcc-gas-2cece67cb5af0339e4ab1f18b0bce2f0b4e6ebdd.tar.gz
Removed intermediate files
Diffstat (limited to 'device/lib/stm8/_divulonglong.lst')
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- 1 ;--------------------------------------------------------
- 2 ; File Created by SDCC : free open source ANSI-C Compiler
- 3 ; Version 3.9.3 #11345 (Linux)
- 4 ;--------------------------------------------------------
- 5 .module _divulonglong
- 6 .optsdcc -mstm8
- 7
- 8 ;--------------------------------------------------------
- 9 ; Public variables in this module
- 10 ;--------------------------------------------------------
- 11 .globl __divulonglong
- 12 ;--------------------------------------------------------
- 13 ; ram data
- 14 ;--------------------------------------------------------
- 15 .area DATA
- 16 ;--------------------------------------------------------
- 17 ; ram data
- 18 ;--------------------------------------------------------
- 19 .area INITIALIZED
- 20 ;--------------------------------------------------------
- 21 ; absolute external ram data
- 22 ;--------------------------------------------------------
- 23 .area DABS (ABS)
- 24
- 25 ; default segment ordering for linker
- 26 .area HOME
- 27 .area GSINIT
- 28 .area GSFINAL
- 29 .area CONST
- 30 .area INITIALIZER
- 31 .area CODE
- 32
- 33 ;--------------------------------------------------------
- 34 ; global & static initialisations
- 35 ;--------------------------------------------------------
- 36 .area HOME
- 37 .area GSINIT
- 38 .area GSFINAL
- 39 .area GSINIT
- 40 ;--------------------------------------------------------
- 41 ; Home
- 42 ;--------------------------------------------------------
- 43 .area HOME
- 44 .area HOME
- 45 ;--------------------------------------------------------
- 46 ; code
- 47 ;--------------------------------------------------------
- 48 .area CODE
- 49 ; ../_divulonglong.c: 39: _divulonglong (unsigned long long x, unsigned long long y)
- 50 ; -----------------------------------------
- 51 ; function _divulonglong
- 52 ; -----------------------------------------
- 000000 53 __divulonglong:
- 000000 52 11 [ 2] 54 sub sp, #17
- 55 ; ../_divulonglong.c: 41: unsigned long long reste = 0L;
- 000002 5F [ 1] 56 clrw x
- 000003 1F 10 [ 2] 57 ldw (0x10, sp), x
- 000005 1F 0E [ 2] 58 ldw (0x0e, sp), x
- 000007 1F 0C [ 2] 59 ldw (0x0c, sp), x
- 000009 1F 0A [ 2] 60 ldw (0x0a, sp), x
- 61 ; ../_divulonglong.c: 42: unsigned char count = 64;
- 00000B A6 40 [ 1] 62 ld a, #0x40
- 00000D 6B 01 [ 1] 63 ld (0x01, sp), a
- 64 ; ../_divulonglong.c: 45: do
- 00000F 65 00105$:
- 66 ; ../_divulonglong.c: 48: c = MSB_SET(x);
- 00000F 7B 16 [ 1] 67 ld a, (0x16, sp)
- 000011 48 [ 1] 68 sll a
- 000012 4F [ 1] 69 clr a
- 000013 49 [ 1] 70 rlc a
- 71 ; ../_divulonglong.c: 49: x <<= 1;
- 000014 08 1D [ 1] 72 sll (0x1d, sp)
- 000016 09 1C [ 1] 73 rlc (0x1c, sp)
- 000018 09 1B [ 1] 74 rlc (0x1b, sp)
- 00001A 09 1A [ 1] 75 rlc (0x1a, sp)
- 00001C 09 19 [ 1] 76 rlc (0x19, sp)
- 00001E 09 18 [ 1] 77 rlc (0x18, sp)
- 000020 09 17 [ 1] 78 rlc (0x17, sp)
- 000022 09 16 [ 1] 79 rlc (0x16, sp)
- 80 ; ../_divulonglong.c: 50: reste <<= 1;
- 000024 08 11 [ 1] 81 sll (0x11, sp)
- 000026 09 10 [ 1] 82 rlc (0x10, sp)
- 000028 09 0F [ 1] 83 rlc (0x0f, sp)
- 00002A 09 0E [ 1] 84 rlc (0x0e, sp)
- 00002C 09 0D [ 1] 85 rlc (0x0d, sp)
- 00002E 09 0C [ 1] 86 rlc (0x0c, sp)
- 000030 09 0B [ 1] 87 rlc (0x0b, sp)
- 000032 09 0A [ 1] 88 rlc (0x0a, sp)
- 89 ; ../_divulonglong.c: 51: if (c)
- 000034 4D [ 1] 90 tnz a
- 000035 27 30 [ 1] 91 jreq 00102$
- 92 ; ../_divulonglong.c: 52: reste |= 1L;
- 000037 7B 11 [ 1] 93 ld a, (0x11, sp)
- 000039 AA 01 [ 1] 94 or a, #0x01
- 00003B 6B 09 [ 1] 95 ld (0x09, sp), a
- 00003D 7B 10 [ 1] 96 ld a, (0x10, sp)
- 00003F 6B 08 [ 1] 97 ld (0x08, sp), a
- 000041 7B 0F [ 1] 98 ld a, (0x0f, sp)
- 000043 6B 07 [ 1] 99 ld (0x07, sp), a
- 000045 7B 0E [ 1] 100 ld a, (0x0e, sp)
- 000047 41 [ 1] 101 exg a, xl
- 000048 7B 0D [ 1] 102 ld a, (0x0d, sp)
- 00004A 41 [ 1] 103 exg a, xl
- 00004B 02 [ 1] 104 rlwa x
- 00004C 7B 0C [ 1] 105 ld a, (0x0c, sp)
- 00004E 01 [ 1] 106 rrwa x
- 00004F 61 [ 1] 107 exg a, yl
- 000050 7B 0B [ 1] 108 ld a, (0x0b, sp)
- 000052 61 [ 1] 109 exg a, yl
- 000053 90 02 [ 1] 110 rlwa y
- 000055 7B 0A [ 1] 111 ld a, (0x0a, sp)
- 000057 90 01 [ 1] 112 rrwa y
- 000059 6B 0E [ 1] 113 ld (0x0e, sp), a
- 00005B 1F 0C [ 2] 114 ldw (0x0c, sp), x
- 00005D 17 0A [ 2] 115 ldw (0x0a, sp), y
- 00005F 16 08 [ 2] 116 ldw y, (0x08, sp)
- 000061 17 10 [ 2] 117 ldw (0x10, sp), y
- 000063 7B 07 [ 1] 118 ld a, (0x07, sp)
- 000065 6B 0F [ 1] 119 ld (0x0f, sp), a
- 000067 120 00102$:
- 121 ; ../_divulonglong.c: 54: if (reste >= y)
- 000067 1E 10 [ 2] 122 ldw x, (0x10, sp)
- 000069 13 24 [ 2] 123 cpw x, (0x24, sp)
- 00006B 7B 0F [ 1] 124 ld a, (0x0f, sp)
- 00006D 12 23 [ 1] 125 sbc a, (0x23, sp)
- 00006F 7B 0E [ 1] 126 ld a, (0x0e, sp)
- 000071 12 22 [ 1] 127 sbc a, (0x22, sp)
- 000073 7B 0D [ 1] 128 ld a, (0x0d, sp)
- 000075 12 21 [ 1] 129 sbc a, (0x21, sp)
- 000077 7B 0C [ 1] 130 ld a, (0x0c, sp)
- 000079 12 20 [ 1] 131 sbc a, (0x20, sp)
- 00007B 7B 0B [ 1] 132 ld a, (0x0b, sp)
- 00007D 12 1F [ 1] 133 sbc a, (0x1f, sp)
- 00007F 7B 0A [ 1] 134 ld a, (0x0a, sp)
- 000081 12 1E [ 1] 135 sbc a, (0x1e, sp)
- 000083 25 6D [ 1] 136 jrc 00106$
- 137 ; ../_divulonglong.c: 56: reste -= y;
- 000085 1E 10 [ 2] 138 ldw x, (0x10, sp)
- 000087 72 F0 24 [ 2] 139 subw x, (0x24, sp)
- 00008A 1F 08 [ 2] 140 ldw (0x08, sp), x
- 00008C 7B 0F [ 1] 141 ld a, (0x0f, sp)
- 00008E 12 23 [ 1] 142 sbc a, (0x23, sp)
- 000090 6B 07 [ 1] 143 ld (0x07, sp), a
- 000092 7B 0E [ 1] 144 ld a, (0x0e, sp)
- 000094 12 22 [ 1] 145 sbc a, (0x22, sp)
- 000096 6B 06 [ 1] 146 ld (0x06, sp), a
- 000098 7B 0D [ 1] 147 ld a, (0x0d, sp)
- 00009A 12 21 [ 1] 148 sbc a, (0x21, sp)
- 00009C 6B 05 [ 1] 149 ld (0x05, sp), a
- 00009E 7B 0C [ 1] 150 ld a, (0x0c, sp)
- 0000A0 12 20 [ 1] 151 sbc a, (0x20, sp)
- 0000A2 6B 04 [ 1] 152 ld (0x04, sp), a
- 0000A4 7B 0B [ 1] 153 ld a, (0x0b, sp)
- 0000A6 12 1F [ 1] 154 sbc a, (0x1f, sp)
- 0000A8 6B 03 [ 1] 155 ld (0x03, sp), a
- 0000AA 7B 0A [ 1] 156 ld a, (0x0a, sp)
- 0000AC 12 1E [ 1] 157 sbc a, (0x1e, sp)
- 0000AE 6B 02 [ 1] 158 ld (0x02, sp), a
- 0000B0 16 08 [ 2] 159 ldw y, (0x08, sp)
- 0000B2 17 10 [ 2] 160 ldw (0x10, sp), y
- 0000B4 16 06 [ 2] 161 ldw y, (0x06, sp)
- 0000B6 17 0E [ 2] 162 ldw (0x0e, sp), y
- 0000B8 16 04 [ 2] 163 ldw y, (0x04, sp)
- 0000BA 17 0C [ 2] 164 ldw (0x0c, sp), y
- 0000BC 16 02 [ 2] 165 ldw y, (0x02, sp)
- 0000BE 17 0A [ 2] 166 ldw (0x0a, sp), y
- 167 ; ../_divulonglong.c: 58: x |= 1L;
- 0000C0 7B 1D [ 1] 168 ld a, (0x1d, sp)
- 0000C2 AA 01 [ 1] 169 or a, #0x01
- 0000C4 6B 09 [ 1] 170 ld (0x09, sp), a
- 0000C6 7B 1C [ 1] 171 ld a, (0x1c, sp)
- 0000C8 6B 08 [ 1] 172 ld (0x08, sp), a
- 0000CA 7B 1B [ 1] 173 ld a, (0x1b, sp)
- 0000CC 6B 07 [ 1] 174 ld (0x07, sp), a
- 0000CE 7B 1A [ 1] 175 ld a, (0x1a, sp)
- 0000D0 6B 06 [ 1] 176 ld (0x06, sp), a
- 0000D2 7B 19 [ 1] 177 ld a, (0x19, sp)
- 0000D4 6B 05 [ 1] 178 ld (0x05, sp), a
- 0000D6 7B 18 [ 1] 179 ld a, (0x18, sp)
- 0000D8 6B 04 [ 1] 180 ld (0x04, sp), a
- 0000DA 7B 17 [ 1] 181 ld a, (0x17, sp)
- 0000DC 6B 03 [ 1] 182 ld (0x03, sp), a
- 0000DE 7B 16 [ 1] 183 ld a, (0x16, sp)
- 0000E0 6B 02 [ 1] 184 ld (0x02, sp), a
- 0000E2 16 08 [ 2] 185 ldw y, (0x08, sp)
- 0000E4 17 1C [ 2] 186 ldw (0x1c, sp), y
- 0000E6 16 06 [ 2] 187 ldw y, (0x06, sp)
- 0000E8 17 1A [ 2] 188 ldw (0x1a, sp), y
- 0000EA 16 04 [ 2] 189 ldw y, (0x04, sp)
- 0000EC 17 18 [ 2] 190 ldw (0x18, sp), y
- 0000EE 16 02 [ 2] 191 ldw y, (0x02, sp)
- 0000F0 17 16 [ 2] 192 ldw (0x16, sp), y
- 0000F2 193 00106$:
- 194 ; ../_divulonglong.c: 61: while (--count);
- 0000F2 0A 01 [ 1] 195 dec (0x01, sp)
- 0000F4 27 03 [ 1] 196 jreq 00132$
- 0000F6 CCr00r0F [ 2] 197 jp 00105$
- 0000F9 198 00132$:
- 199 ; ../_divulonglong.c: 62: return x;
- 0000F9 1E 14 [ 2] 200 ldw x, (0x14, sp)
- 0000FB 16 1C [ 2] 201 ldw y, (0x1c, sp)
- 0000FD EF 06 [ 2] 202 ldw (#6, x), y
- 0000FF 16 1A [ 2] 203 ldw y, (0x1a, sp)
- 000101 EF 04 [ 2] 204 ldw (#4, x), y
- 000103 16 18 [ 2] 205 ldw y, (0x18, sp)
- 000105 EF 02 [ 2] 206 ldw (#2, x), y
- 000107 16 16 [ 2] 207 ldw y, (0x16, sp)
- 000109 FF [ 2] 208 ldw (x), y
- 209 ; ../_divulonglong.c: 63: }
- 00010A 5B 11 [ 2] 210 addw sp, #17
- 00010C 81 [ 4] 211 ret
- 212 .area CODE
- 213 .area CONST
- 214 .area INITIALIZER
- 215 .area CABS (ABS)
generated by cgit v1.2.3 (git 2.39.1) at 2026-07-17 15:50:29 +0000