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authorspicyjpeg <88942473+spicyjpeg@users.noreply.github.com>2022-07-17 11:40:02 +0200
committerspicyjpeg <88942473+spicyjpeg@users.noreply.github.com>2022-07-17 11:40:02 +0200
commitc800972bc13ad0c7015b7d44fe9f124b719e792e (patch)
tree7bb6767d786b6828438e55fa8b01d9e43309f59a /libpsn00b/include
parent8deeb216cbff4e578284fc040d8f0b51e96d4b04 (diff)
downloadpsn00bsdk-c800972bc13ad0c7015b7d44fe9f124b719e792e.tar.gz
Change I/O base address to 0xbf80, use size_t in stdlib
Diffstat (limited to 'libpsn00b/include')
-rw-r--r--libpsn00b/include/hwregs_a.h2
-rw-r--r--libpsn00b/include/hwregs_c.h142
-rw-r--r--libpsn00b/include/stdlib.h14
3 files changed, 80 insertions, 78 deletions
diff --git a/libpsn00b/include/hwregs_a.h b/libpsn00b/include/hwregs_a.h
index 8a504f5..d8f6c72 100644
--- a/libpsn00b/include/hwregs_a.h
+++ b/libpsn00b/include/hwregs_a.h
@@ -4,7 +4,7 @@
# 2019 Meido-Tek Productions
-.set IOBASE, 0x1f80 # IO segment base
+.set IOBASE, 0xbf80 # IO segment base (KSEG1)
## GPU
diff --git a/libpsn00b/include/hwregs_c.h b/libpsn00b/include/hwregs_c.h
index e533c56..a9f4ee3 100644
--- a/libpsn00b/include/hwregs_c.h
+++ b/libpsn00b/include/hwregs_c.h
@@ -19,111 +19,111 @@
/* GPU */
-#define GPU_GP0 _MMIO32(0x1f801810)
-#define GPU_GP1 _MMIO32(0x1f801814)
+#define GPU_GP0 _MMIO32(0xbf801810)
+#define GPU_GP1 _MMIO32(0xbf801814)
/* CD drive */
-#define CD_STAT _MMIO8(0x1f801800)
-#define CD_CMD _MMIO8(0x1f801801)
-#define CD_DATA _MMIO8(0x1f801802)
-#define CD_IRQ _MMIO8(0x1f801803)
+#define CD_STAT _MMIO8(0xbf801800)
+#define CD_CMD _MMIO8(0xbf801801)
+#define CD_DATA _MMIO8(0xbf801802)
+#define CD_IRQ _MMIO8(0xbf801803)
-#define CD_REG(N) _MMIO8(0x1f801800 + (N))
+#define CD_REG(N) _MMIO8(0xbf801800 + (N))
/* SPU */
-#define SPU_MASTER_VOL_L _MMIO16(0x1f801d80)
-#define SPU_MASTER_VOL_R _MMIO16(0x1f801d82)
-#define SPU_REVERB_VOL_L _MMIO16(0x1f801d84)
-#define SPU_REVERB_VOL_R _MMIO16(0x1f801d86)
-#define SPU_KEY_ON _MMIO32(0x1f801d88)
-#define SPU_KEY_OFF _MMIO32(0x1f801d8c)
-#define SPU_FM_MODE _MMIO32(0x1f801d90)
-#define SPU_NOISE_MODE _MMIO32(0x1f801d94)
-#define SPU_REVERB_ON _MMIO32(0x1f801d98)
-#define SPU_CHAN_STATUS _MMIO32(0x1f801d9c)
-
-#define SPU_REVERB_ADDR _MMIO16(0x1f801da2)
-#define SPU_IRQ_ADDR _MMIO16(0x1f801da4)
-#define SPU_ADDR _MMIO16(0x1f801da6)
-#define SPU_DATA _MMIO16(0x1f801da8)
-
-#define SPU_CTRL _MMIO16(0x1f801daa)
-#define SPU_DMA_CTRL _MMIO16(0x1f801dac)
-#define SPU_STAT _MMIO16(0x1f801dae)
-
-#define SPU_CD_VOL_L _MMIO16(0x1f801db0)
-#define SPU_CD_VOL_R _MMIO16(0x1f801db2)
-#define SPU_EXT_VOL_L _MMIO16(0x1f801db4)
-#define SPU_EXT_VOL_R _MMIO16(0x1f801db6)
-#define SPU_CURRENT_VOL_L _MMIO16(0x1f801db8)
-#define SPU_CURRENT_VOL_R _MMIO16(0x1f801dba)
+#define SPU_MASTER_VOL_L _MMIO16(0xbf801d80)
+#define SPU_MASTER_VOL_R _MMIO16(0xbf801d82)
+#define SPU_REVERB_VOL_L _MMIO16(0xbf801d84)
+#define SPU_REVERB_VOL_R _MMIO16(0xbf801d86)
+#define SPU_KEY_ON _MMIO32(0xbf801d88)
+#define SPU_KEY_OFF _MMIO32(0xbf801d8c)
+#define SPU_FM_MODE _MMIO32(0xbf801d90)
+#define SPU_NOISE_MODE _MMIO32(0xbf801d94)
+#define SPU_REVERB_ON _MMIO32(0xbf801d98)
+#define SPU_CHAN_STATUS _MMIO32(0xbf801d9c)
+
+#define SPU_REVERB_ADDR _MMIO16(0xbf801da2)
+#define SPU_IRQ_ADDR _MMIO16(0xbf801da4)
+#define SPU_ADDR _MMIO16(0xbf801da6)
+#define SPU_DATA _MMIO16(0xbf801da8)
+
+#define SPU_CTRL _MMIO16(0xbf801daa)
+#define SPU_DMA_CTRL _MMIO16(0xbf801dac)
+#define SPU_STAT _MMIO16(0xbf801dae)
+
+#define SPU_CD_VOL_L _MMIO16(0xbf801db0)
+#define SPU_CD_VOL_R _MMIO16(0xbf801db2)
+#define SPU_EXT_VOL_L _MMIO16(0xbf801db4)
+#define SPU_EXT_VOL_R _MMIO16(0xbf801db6)
+#define SPU_CURRENT_VOL_L _MMIO16(0xbf801db8)
+#define SPU_CURRENT_VOL_R _MMIO16(0xbf801dba)
// These are not named SPU_VOICE_* to avoid name clashes with SPU attribute
// flags defined in psxspu.h.
-#define SPU_CH_VOL_L(N) _MMIO16(0x1f801c00 + 16 * (N))
-#define SPU_CH_VOL_R(N) _MMIO16(0x1f801c02 + 16 * (N))
-#define SPU_CH_FREQ(N) _MMIO16(0x1f801c04 + 16 * (N))
-#define SPU_CH_ADDR(N) _MMIO16(0x1f801c06 + 16 * (N))
-#define SPU_CH_ADSR(N) _MMIO32(0x1f801c08 + 16 * (N))
-#define SPU_CH_LOOP_ADDR(N) _MMIO16(0x1f801c0e + 16 * (N))
+#define SPU_CH_VOL_L(N) _MMIO16(0xbf801c00 + 16 * (N))
+#define SPU_CH_VOL_R(N) _MMIO16(0xbf801c02 + 16 * (N))
+#define SPU_CH_FREQ(N) _MMIO16(0xbf801c04 + 16 * (N))
+#define SPU_CH_ADDR(N) _MMIO16(0xbf801c06 + 16 * (N))
+#define SPU_CH_ADSR(N) _MMIO32(0xbf801c08 + 16 * (N))
+#define SPU_CH_LOOP_ADDR(N) _MMIO16(0xbf801c0e + 16 * (N))
/* MDEC */
-#define MDEC0 _MMIO32(0x1f801820)
-#define MDEC1 _MMIO32(0x1f801824)
+#define MDEC0 _MMIO32(0xbf801820)
+#define MDEC1 _MMIO32(0xbf801824)
/* SPI controller port */
// IMPORTANT: even though JOY_TXRX is a 32-bit register, it should only be
// accessed as 8-bit. Reading it as 16 or 32-bit works fine on real hardware,
// but leads to problems in some emulators.
-#define JOY_TXRX _MMIO8(0x1f801040)
-#define JOY_STAT _MMIO16(0x1f801044)
-#define JOY_MODE _MMIO16(0x1f801048)
-#define JOY_CTRL _MMIO16(0x1f80104a)
-#define JOY_BAUD _MMIO16(0x1f80104e)
+#define JOY_TXRX _MMIO8(0xbf801040)
+#define JOY_STAT _MMIO16(0xbf801044)
+#define JOY_MODE _MMIO16(0xbf801048)
+#define JOY_CTRL _MMIO16(0xbf80104a)
+#define JOY_BAUD _MMIO16(0xbf80104e)
/* Serial port */
-#define SIO_TXRX _MMIO8(0x1f801050)
-#define SIO_STAT _MMIO16(0x1f801054)
-#define SIO_MODE _MMIO16(0x1f801058)
-#define SIO_CTRL _MMIO16(0x1f80105a)
-#define SIO_BAUD _MMIO16(0x1f80105e)
+#define SIO_TXRX _MMIO8(0xbf801050)
+#define SIO_STAT _MMIO16(0xbf801054)
+#define SIO_MODE _MMIO16(0xbf801058)
+#define SIO_CTRL _MMIO16(0xbf80105a)
+#define SIO_BAUD _MMIO16(0xbf80105e)
/* IRQ controller */
-#define IRQ_STAT _MMIO32(0x1f801070)
-#define IRQ_MASK _MMIO32(0x1f801074)
+#define IRQ_STAT _MMIO32(0xbf801070)
+#define IRQ_MASK _MMIO32(0xbf801074)
/* DMA */
-#define DMA_DPCR _MMIO32(0x1f8010f0)
-#define DMA_DICR _MMIO32(0x1f8010f4)
+#define DMA_DPCR _MMIO32(0xbf8010f0)
+#define DMA_DICR _MMIO32(0xbf8010f4)
-#define DMA_MADR(N) _MMIO32(0x1f801080 + 16 * (N))
-#define DMA_BCR(N) _MMIO32(0x1f801084 + 16 * (N))
-#define DMA_CHCR(N) _MMIO32(0x1f801088 + 16 * (N))
+#define DMA_MADR(N) _MMIO32(0xbf801080 + 16 * (N))
+#define DMA_BCR(N) _MMIO32(0xbf801084 + 16 * (N))
+#define DMA_CHCR(N) _MMIO32(0xbf801088 + 16 * (N))
/* Timers */
-#define TIMER_VALUE(N) _MMIO32(0x1f801100 + 16 * (N))
-#define TIMER_CTRL(N) _MMIO32(0x1f801104 + 16 * (N))
-#define TIMER_RELOAD(N) _MMIO32(0x1f801108 + 16 * (N))
+#define TIMER_VALUE(N) _MMIO32(0xbf801100 + 16 * (N))
+#define TIMER_CTRL(N) _MMIO32(0xbf801104 + 16 * (N))
+#define TIMER_RELOAD(N) _MMIO32(0xbf801108 + 16 * (N))
/* Memory control */
-#define EXP1_ADDR _MMIO32(0x1f801000)
-#define EXP2_ADDR _MMIO32(0x1f801004)
-#define EXP1_DELAY_SIZE _MMIO32(0x1f801008)
-#define EXP3_DELAY_SIZE _MMIO32(0x1f80100c)
-#define BIOS_DELAY_SIZE _MMIO32(0x1f801010)
-#define SPU_DELAY_SIZE _MMIO32(0x1f801014)
-#define CD_DELAY_SIZE _MMIO32(0x1f801018)
-#define EXP2_DELAY_SIZE _MMIO32(0x1f80101c)
-#define COM_DELAY_CFG _MMIO32(0x1f801020)
-#define RAM_SIZE_CFG _MMIO32(0x1f801060)
+#define EXP1_ADDR _MMIO32(0xbf801000)
+#define EXP2_ADDR _MMIO32(0xbf801004)
+#define EXP1_DELAY_SIZE _MMIO32(0xbf801008)
+#define EXP3_DELAY_SIZE _MMIO32(0xbf80100c)
+#define BIOS_DELAY_SIZE _MMIO32(0xbf801010)
+#define SPU_DELAY_SIZE _MMIO32(0xbf801014)
+#define CD_DELAY_SIZE _MMIO32(0xbf801018)
+#define EXP2_DELAY_SIZE _MMIO32(0xbf80101c)
+#define COM_DELAY_CFG _MMIO32(0xbf801020)
+#define RAM_SIZE_CFG _MMIO32(0xbf801060)
#endif
diff --git a/libpsn00b/include/stdlib.h b/libpsn00b/include/stdlib.h
index 4c4fcd3..fd4b36c 100644
--- a/libpsn00b/include/stdlib.h
+++ b/libpsn00b/include/stdlib.h
@@ -9,6 +9,8 @@
#ifndef _STDLIB_H
#define _STDLIB_H
+#include <stddef.h>
+
#define RAND_MAX 0x7fff
/* Conversion functions (not yet implemented) */
@@ -30,7 +32,7 @@ extern "C" {
extern int __argc;
extern const char **__argv;
-int rand();
+int rand(void);
void srand(unsigned long seed);
int abs(int j);
@@ -44,11 +46,11 @@ double strtod(const char *nptr, char **endptr);
float strtof(const char *nptr, char **endptr);
// Memory allocation functions
-void _mem_init(int ram_size, int stack_max_size);
-void InitHeap(unsigned int *addr, int size);
-int SetHeapSize(int size);
-void *malloc(int size);
-void *calloc(int number, int size);
+void _mem_init(size_t ram_size, size_t stack_max_size);
+void InitHeap(void *addr, size_t size);
+int SetHeapSize(size_t size);
+void *malloc(size_t size);
+void *calloc(size_t number, size_t size);
void free(void *ptr);
#ifdef __cplusplus