Rename hwregs_a definitions, add hwregs_c, fix io/pads

2 files changed, 230 insertions, 73 deletions

diff --git a/libpsn00b/include/hwregs_a.h b/libpsn00b/include/hwregs_a.h
index 0680679..4d0bade 100644
--- a/libpsn00b/include/hwregs_a.h
+++ b/libpsn00b/include/hwregs_a.h
@@ -6,11 +6,13 @@
 
 .set IOBASE,			0x1f80		# IO segment base
 
-# GPU
+## GPU
+
 .set GP0,				0x1810		# Also GPUREAD
 .set GP1,				0x1814		# Also GPUSTAT
 
-# CD
+## CD drive
+
 .set CD_STAT,			0x1800
 .set CD_CMD,			0x1801		# Also response FIFO
 .set CD_DATA,			0x1802		# Also parameters
@@ -21,14 +23,14 @@
 .set CD_REG2,			0x1802
 .set CD_REG3,			0x1803
 
-.set SBUS_5,			0x1018
-.set COM_DELAY,			0x1020
+## SPU
 
-# SPU (must be used with 16-bit load/store instructions)
 .set SPU_VOICE_BASE,	0x1c00
 
-.set SPU_MASTER_VOL,	0x1d80
-.set SPU_REVERB_VOL,	0x1d84
+.set SPU_MASTER_VOL_L,	0x1d80
+.set SPU_MASTER_VOL_R,	0x1d82
+.set SPU_REVERB_VOL_L,	0x1d84
+.set SPU_REVERB_VOL_R,	0x1d86
 .set SPU_KEY_ON,		0x1d88
 .set SPU_KEY_OFF,		0x1d8c
 .set SPU_FM_MODE,		0x1d90
@@ -41,81 +43,107 @@
 .set SPU_ADDR,			0x1da6
 .set SPU_DATA,			0x1da8
 
-.set SPUCNT,			0x1daa
-.set SPUDTCNT,			0x1dac
-.set SPUSTAT,			0x1dae
+.set SPU_CTRL,			0x1daa
+.set SPU_DMA_CTRL,		0x1dac
+.set SPU_STAT,			0x1dae
 
-.set SPU_CD_VOL,		0x1db0
-.set SPU_EXT_VOL,		0x1db4
-.set SPU_CURRENT_VOL,	0x1db8
+.set SPU_CD_VOL_L,		0x1db0
+.set SPU_CD_VOL_R,		0x1db2
+.set SPU_EXT_VOL_L,		0x1db4
+.set SPU_EXT_VOL_R,		0x1db6
+.set SPU_CURRENT_VOL_L,	0x1db8
+.set SPU_CURRENT_VOL_R,	0x1dba
 
 .set SPU_VOICE_VOL_L,	0x00
 .set SPU_VOICE_VOL_R,	0x02
 .set SPU_VOICE_FREQ,	0x04
 .set SPU_VOICE_ADDR,	0x06
 .set SPU_VOICE_ADSR_L,	0x08
-.set SPU_VOICE_ADSR_H,	0x0a		
+.set SPU_VOICE_ADSR_H,	0x0a
 .set SPU_VOICE_LOOP,	0x0e
 
-# MDEC
+## MDEC
+
 .set MDEC0,				0x1820
 .set MDEC1,				0x1824
 
-# Pads
-.set JOY_TXRX,	0x1040
-.set JOY_STAT,	0x1044
-.set JOY_MODE,	0x1048
-.set JOY_CTRL,	0x104A
-.set JOY_BAUD,	0x104E
-
-# Serial
-.set SIO_TXRX,	0x1050
-.set SIO_STAT,	0x1054
-.set SIO_MODE,	0x1058
-.set SIO_CTRL,	0x105a
-.set SIO_BAUD,	0x105e
-
-# IRQ
-.set ISTAT,		0x1070
-.set IMASK,		0x1074
-
-# DMA
-.set DPCR,		0x10f0     
-.set DICR,		0x10f4
-
-.set D0_MADR,	0x1080
-.set D0_BCR,	0x1084
-.set D0_CHCR,	0x1088
-
-.set D1_MADR,	0x1090
-.set D1_BCR,	0x1094
-.set D1_CHCR,	0x1098
-
-.set D2_MADR,	0x10a0
-.set D2_BCR,	0x10a4
-.set D2_CHCR,	0x10a8
-
-.set D3_MADR,	0x10b0
-.set D3_BCR,	0x10b4
-.set D3_CHCR,	0x10b8
-
-.set D4_MADR,	0x10c0
-.set D4_BCR,	0x10c4
-.set D4_CHCR,	0x10c8
-
-.set D6_MADR,	0x10e0
-.set D6_BCR,	0x10e4
-.set D6_CHCR,	0x10e8
-
-# Timers
-.set T0_CNT,	0x1100
-.set T0_MODE,	0x1104
-.set T0_TGT,	0x1108
-
-.set T1_CNT,	0x1110
-.set T1_MODE,	0x1114
-.set T1_TGT,	0x1118
-
-.set T2_CNT,	0x1120
-.set T2_MODE,	0x1124
-.set T2_TGT,	0x1128
+## SPI controller port
+
+.set JOY_TXRX,			0x1040
+.set JOY_STAT,			0x1044
+.set JOY_MODE,			0x1048
+.set JOY_CTRL,			0x104a
+.set JOY_BAUD,			0x104e
+
+## Serial port
+
+.set SIO_TXRX,			0x1050
+.set SIO_STAT,			0x1054
+.set SIO_MODE,			0x1058
+.set SIO_CTRL,			0x105a
+.set SIO_BAUD,			0x105e
+
+## IRQ controller
+
+.set IRQ_STAT,			0x1070
+.set IRQ_MASK,			0x1074
+
+## DMA
+
+.set DMA_DPCR,			0x10f0
+.set DMA_DICR,			0x10f4
+
+.set DMA0_MADR,			0x1080
+.set DMA0_BCR,			0x1084
+.set DMA0_CHCR,			0x1088
+
+.set DMA1_MADR,			0x1090
+.set DMA1_BCR,			0x1094
+.set DMA1_CHCR,			0x1098
+
+.set DMA2_MADR,			0x10a0
+.set DMA2_BCR,			0x10a4
+.set DMA2_CHCR,			0x10a8
+
+.set DMA3_MADR,			0x10b0
+.set DMA3_BCR,			0x10b4
+.set DMA3_CHCR,			0x10b8
+
+.set DMA4_MADR,			0x10c0
+.set DMA4_BCR,			0x10c4
+.set DMA4_CHCR,			0x10c8
+
+.set DMA5_MADR,			0x10d0
+.set DMA5_BCR,			0x10d4
+.set DMA5_CHCR,			0x10d8
+
+.set DMA6_MADR,			0x10e0
+.set DMA6_BCR,			0x10e4
+.set DMA6_CHCR,			0x10e8
+
+## Timers
+
+.set TIM0_VALUE,		0x1100
+.set TIM0_CTRL,			0x1104
+.set TIM0_RELOAD,		0x1108
+
+.set TIM1_VALUE,		0x1110
+.set TIM1_CTRL,			0x1114
+.set TIM1_RELOAD,		0x1118
+
+.set TIM2_VALUE,		0x1120
+.set TIM2_CTRL,			0x1124
+.set TIM2_RELOAD,		0x1128
+
+## Memory control
+
+.set EXP1_ADDR,			0x1000
+.set EXP2_ADDR,			0x1004
+.set EXP1_DELAY_SIZE,	0x1008
+.set EXP3_DELAY_SIZE,	0x100c
+.set BIOS_DELAY_SIZE,	0x1010
+.set SPU_DELAY_SIZE,	0x1014
+.set CD_DELAY_SIZE,		0x1018
+.set EXP2_DELAY_SIZE,	0x101c
+.set COM_DELAY_CFG,		0x1020
+.set RAM_SIZE_CFG,		0x1060
diff --git a/libpsn00b/include/hwregs_c.h b/libpsn00b/include/hwregs_c.h
new file mode 100644
index 0000000..4222a22
--- /dev/null
+++ b/libpsn00b/include/hwregs_c.h
@@ -0,0 +1,129 @@
+/*
+ * PSn00bSDK hardware registers definitions
+ * (C) 2022 spicyjpeg - MPL licensed
+ */
+
+#ifndef __HWREGS_C_H
+#define __HWREGS_C_H
+
+#include <stdint.h>
+
+#define _MMIO8(addr)		*((volatile uint8_t *) (addr))
+#define _MMIO16(addr)		*((volatile uint16_t *) (addr))
+#define _MMIO32(addr)		*((volatile uint32_t *) (addr))
+
+/* Constants */
+
+#define F_CPU				33868800UL
+#define F_GPU				53222400UL
+
+/* GPU */
+
+#define GP0					_MMIO32(0x1f801810)
+#define GP1					_MMIO32(0x1f801814)
+
+/* CD drive */
+
+#define CD_STAT				_MMIO8(0x1f801800)
+#define CD_CMD				_MMIO8(0x1f801801)
+#define CD_DATA				_MMIO8(0x1f801802)
+#define CD_IRQ				_MMIO8(0x1f801803)
+
+#define CD_REG(N)			_MMIO8(0x1f801800 + (N))
+
+/* SPU */
+
+#define SPU_MASTER_VOL_L	_MMIO16(0x1f801d80)
+#define SPU_MASTER_VOL_R	_MMIO16(0x1f801d82)
+#define SPU_REVERB_VOL_L	_MMIO16(0x1f801d84)
+#define SPU_REVERB_VOL_R	_MMIO16(0x1f801d86)
+#define SPU_KEY_ON			_MMIO32(0x1f801d88)
+#define SPU_KEY_OFF			_MMIO32(0x1f801d8c)
+#define SPU_FM_MODE			_MMIO32(0x1f801d90)
+#define SPU_NOISE_MODE		_MMIO32(0x1f801d94)
+#define SPU_REVERB_ON		_MMIO32(0x1f801d98)
+#define SPU_CHAN_STATUS		_MMIO32(0x1f801d9c)
+
+#define SPU_REVERB_ADDR		_MMIO16(0x1f801da2)
+#define SPU_IRQ_ADDR		_MMIO16(0x1f801da4)
+#define SPU_ADDR			_MMIO16(0x1f801da6)
+#define SPU_DATA			_MMIO16(0x1f801da8)
+
+#define SPU_CTRL			_MMIO16(0x1f801daa)
+#define SPU_DMA_CTRL		_MMIO16(0x1f801dac)
+#define SPU_STAT			_MMIO16(0x1f801dae)
+
+#define SPU_CD_VOL_L		_MMIO16(0x1f801db0)
+#define SPU_CD_VOL_R		_MMIO16(0x1f801db2)
+#define SPU_EXT_VOL_L		_MMIO16(0x1f801db4)
+#define SPU_EXT_VOL_R		_MMIO16(0x1f801db6)
+#define SPU_CURRENT_VOL_L	_MMIO16(0x1f801db8)
+#define SPU_CURRENT_VOL_R	_MMIO16(0x1f801dba)
+
+// These are not named SPU_VOICE_* to avoid name clashes with SPU attribute
+// flags defined in psxspu.h.
+#define SPU_CH_VOL_L(N)		_MMIO16(0x1f801c00 + 16 * (N))
+#define SPU_CH_VOL_R(N)		_MMIO16(0x1f801c02 + 16 * (N))
+#define SPU_CH_FREQ(N)		_MMIO16(0x1f801c04 + 16 * (N))
+#define SPU_CH_ADDR(N)		_MMIO16(0x1f801c06 + 16 * (N))
+#define SPU_CH_ADSR(N)		_MMIO32(0x1f801c08 + 16 * (N))
+#define SPU_CH_LOOP_ADDR(N)	_MMIO16(0x1f801c0e + 16 * (N))
+
+/* MDEC */
+
+#define MDEC0				_MMIO32(0x1f801820)
+#define MDEC1				_MMIO32(0x1f801824)
+
+/* SPI controller port */
+
+// IMPORTANT: even though JOY_TXRX is a 32-bit register, it should only be
+// accessed as 8-bit. Reading it as 16 or 32-bit works fine on real hardware,
+// but leads to problems in some emulators.
+#define JOY_TXRX			_MMIO8(0x1f801040)
+#define JOY_STAT			_MMIO16(0x1f801044)
+#define JOY_MODE			_MMIO16(0x1f801048)
+#define JOY_CTRL			_MMIO16(0x1f80104a)
+#define JOY_BAUD			_MMIO16(0x1f80104e)
+
+/* Serial port */
+
+#define SIO_TXRX			_MMIO8(0x1f801050)
+#define SIO_STAT			_MMIO16(0x1f801054)
+#define SIO_MODE			_MMIO16(0x1f801058)
+#define SIO_CTRL			_MMIO16(0x1f80105a)
+#define SIO_BAUD			_MMIO16(0x1f80105e)
+
+/* IRQ controller */
+
+#define IRQ_STAT			_MMIO32(0x1f801070)
+#define IRQ_MASK			_MMIO32(0x1f801074)
+
+/* DMA */
+
+#define DMA_DPCR			_MMIO32(0x1f8010f0)
+#define DMA_DICR			_MMIO32(0x1f8010f4)
+
+#define DMA_MADR(N)			_MMIO32(0x1f801080 + 16 * (N))
+#define DMA_BCR(N)			_MMIO32(0x1f801084 + 16 * (N))
+#define DMA_CHCR(N)			_MMIO32(0x1f801088 + 16 * (N))
+
+/* Timers */
+
+#define TIM_VALUE(N)		_MMIO32(0x1f801100 + 16 * (N))
+#define TIM_CTRL(N)			_MMIO32(0x1f801104 + 16 * (N))
+#define TIM_RELOAD(N)		_MMIO32(0x1f801108 + 16 * (N))
+
+/* Memory control */
+
+#define EXP1_ADDR			_MMIO32(0x1f801000)
+#define EXP2_ADDR			_MMIO32(0x1f801004)
+#define EXP1_DELAY_SIZE		_MMIO32(0x1f801008)
+#define EXP3_DELAY_SIZE		_MMIO32(0x1f80100c)
+#define BIOS_DELAY_SIZE		_MMIO32(0x1f801010)
+#define SPU_DELAY_SIZE		_MMIO32(0x1f801014)
+#define CD_DELAY_SIZE		_MMIO32(0x1f801018)
+#define EXP2_DELAY_SIZE		_MMIO32(0x1f80101c)
+#define COM_DELAY_CFG		_MMIO32(0x1f801020)
+#define RAM_SIZE_CFG		_MMIO32(0x1f801060)
+
+#endif