Rewrite libpsxspu in C and update sound examples

3 files changed, 122 insertions, 87 deletions

diff --git a/libpsn00b/include/hwregs_a.h b/libpsn00b/include/hwregs_a.h
index d8f6c72..c78b41a 100644
--- a/libpsn00b/include/hwregs_a.h
+++ b/libpsn00b/include/hwregs_a.h
@@ -1,10 +1,11 @@
-# Hardware register definitions for GNU assembler (as)
-#
-# Part of the PSn00bSDK Project by Lameguy64
-# 2019 Meido-Tek Productions
+# PSn00bSDK hardware registers definitions
+# (C) 2019-2022 Lameguy64, spicyjpeg - MPL licensed
 
+## Constants
 
-.set IOBASE,			0xbf80		# IO segment base (KSEG1)
+.set IOBASE,			0x1f80
+.set F_CPU,				33868800
+.set F_GPU,				53222400
 
 ## GPU
 
diff --git a/libpsn00b/include/hwregs_c.h b/libpsn00b/include/hwregs_c.h
index a9f4ee3..7b80590 100644
--- a/libpsn00b/include/hwregs_c.h
+++ b/libpsn00b/include/hwregs_c.h
@@ -14,116 +14,117 @@
 
 /* Constants */
 
+#define IOBASE				0x1f800000
 #define F_CPU				33868800UL
 #define F_GPU				53222400UL
 
 /* GPU */
 
-#define GPU_GP0				_MMIO32(0xbf801810)
-#define GPU_GP1				_MMIO32(0xbf801814)
+#define GPU_GP0				_MMIO32(IOBASE | 0x1810)
+#define GPU_GP1				_MMIO32(IOBASE | 0x1814)
 
 /* CD drive */
 
-#define CD_STAT				_MMIO8(0xbf801800)
-#define CD_CMD				_MMIO8(0xbf801801)
-#define CD_DATA				_MMIO8(0xbf801802)
-#define CD_IRQ				_MMIO8(0xbf801803)
+#define CD_STAT				_MMIO8(IOBASE | 0x1800)
+#define CD_CMD				_MMIO8(IOBASE | 0x1801)
+#define CD_DATA				_MMIO8(IOBASE | 0x1802)
+#define CD_IRQ				_MMIO8(IOBASE | 0x1803)
 
-#define CD_REG(N)			_MMIO8(0xbf801800 + (N))
+#define CD_REG(N)			_MMIO8(IOBASE | 0x1800 + (N))
 
 /* SPU */
 
-#define SPU_MASTER_VOL_L	_MMIO16(0xbf801d80)
-#define SPU_MASTER_VOL_R	_MMIO16(0xbf801d82)
-#define SPU_REVERB_VOL_L	_MMIO16(0xbf801d84)
-#define SPU_REVERB_VOL_R	_MMIO16(0xbf801d86)
-#define SPU_KEY_ON			_MMIO32(0xbf801d88)
-#define SPU_KEY_OFF			_MMIO32(0xbf801d8c)
-#define SPU_FM_MODE			_MMIO32(0xbf801d90)
-#define SPU_NOISE_MODE		_MMIO32(0xbf801d94)
-#define SPU_REVERB_ON		_MMIO32(0xbf801d98)
-#define SPU_CHAN_STATUS		_MMIO32(0xbf801d9c)
-
-#define SPU_REVERB_ADDR		_MMIO16(0xbf801da2)
-#define SPU_IRQ_ADDR		_MMIO16(0xbf801da4)
-#define SPU_ADDR			_MMIO16(0xbf801da6)
-#define SPU_DATA			_MMIO16(0xbf801da8)
-
-#define SPU_CTRL			_MMIO16(0xbf801daa)
-#define SPU_DMA_CTRL		_MMIO16(0xbf801dac)
-#define SPU_STAT			_MMIO16(0xbf801dae)
-
-#define SPU_CD_VOL_L		_MMIO16(0xbf801db0)
-#define SPU_CD_VOL_R		_MMIO16(0xbf801db2)
-#define SPU_EXT_VOL_L		_MMIO16(0xbf801db4)
-#define SPU_EXT_VOL_R		_MMIO16(0xbf801db6)
-#define SPU_CURRENT_VOL_L	_MMIO16(0xbf801db8)
-#define SPU_CURRENT_VOL_R	_MMIO16(0xbf801dba)
+#define SPU_MASTER_VOL_L	_MMIO16(IOBASE | 0x1d80)
+#define SPU_MASTER_VOL_R	_MMIO16(IOBASE | 0x1d82)
+#define SPU_REVERB_VOL_L	_MMIO16(IOBASE | 0x1d84)
+#define SPU_REVERB_VOL_R	_MMIO16(IOBASE | 0x1d86)
+#define SPU_KEY_ON			_MMIO32(IOBASE | 0x1d88)
+#define SPU_KEY_OFF			_MMIO32(IOBASE | 0x1d8c)
+#define SPU_FM_MODE			_MMIO32(IOBASE | 0x1d90)
+#define SPU_NOISE_MODE		_MMIO32(IOBASE | 0x1d94)
+#define SPU_REVERB_ON		_MMIO32(IOBASE | 0x1d98)
+#define SPU_CHAN_STATUS		_MMIO32(IOBASE | 0x1d9c)
+
+#define SPU_REVERB_ADDR		_MMIO16(IOBASE | 0x1da2)
+#define SPU_IRQ_ADDR		_MMIO16(IOBASE | 0x1da4)
+#define SPU_ADDR			_MMIO16(IOBASE | 0x1da6)
+#define SPU_DATA			_MMIO16(IOBASE | 0x1da8)
+
+#define SPU_CTRL			_MMIO16(IOBASE | 0x1daa)
+#define SPU_DMA_CTRL		_MMIO16(IOBASE | 0x1dac)
+#define SPU_STAT			_MMIO16(IOBASE | 0x1dae)
+
+#define SPU_CD_VOL_L		_MMIO16(IOBASE | 0x1db0)
+#define SPU_CD_VOL_R		_MMIO16(IOBASE | 0x1db2)
+#define SPU_EXT_VOL_L		_MMIO16(IOBASE | 0x1db4)
+#define SPU_EXT_VOL_R		_MMIO16(IOBASE | 0x1db6)
+#define SPU_CURRENT_VOL_L	_MMIO16(IOBASE | 0x1db8)
+#define SPU_CURRENT_VOL_R	_MMIO16(IOBASE | 0x1dba)
 
 // These are not named SPU_VOICE_* to avoid name clashes with SPU attribute
 // flags defined in psxspu.h.
-#define SPU_CH_VOL_L(N)		_MMIO16(0xbf801c00 + 16 * (N))
-#define SPU_CH_VOL_R(N)		_MMIO16(0xbf801c02 + 16 * (N))
-#define SPU_CH_FREQ(N)		_MMIO16(0xbf801c04 + 16 * (N))
-#define SPU_CH_ADDR(N)		_MMIO16(0xbf801c06 + 16 * (N))
-#define SPU_CH_ADSR(N)		_MMIO32(0xbf801c08 + 16 * (N))
-#define SPU_CH_LOOP_ADDR(N)	_MMIO16(0xbf801c0e + 16 * (N))
+#define SPU_CH_VOL_L(N)		_MMIO16(IOBASE | 0x1c00 + 16 * (N))
+#define SPU_CH_VOL_R(N)		_MMIO16(IOBASE | 0x1c02 + 16 * (N))
+#define SPU_CH_FREQ(N)		_MMIO16(IOBASE | 0x1c04 + 16 * (N))
+#define SPU_CH_ADDR(N)		_MMIO16(IOBASE | 0x1c06 + 16 * (N))
+#define SPU_CH_ADSR(N)		_MMIO32(IOBASE | 0x1c08 + 16 * (N))
+#define SPU_CH_LOOP_ADDR(N)	_MMIO16(IOBASE | 0x1c0e + 16 * (N))
 
 /* MDEC */
 
-#define MDEC0				_MMIO32(0xbf801820)
-#define MDEC1				_MMIO32(0xbf801824)
+#define MDEC0				_MMIO32(IOBASE | 0x1820)
+#define MDEC1				_MMIO32(IOBASE | 0x1824)
 
 /* SPI controller port */
 
 // IMPORTANT: even though JOY_TXRX is a 32-bit register, it should only be
 // accessed as 8-bit. Reading it as 16 or 32-bit works fine on real hardware,
 // but leads to problems in some emulators.
-#define JOY_TXRX			_MMIO8(0xbf801040)
-#define JOY_STAT			_MMIO16(0xbf801044)
-#define JOY_MODE			_MMIO16(0xbf801048)
-#define JOY_CTRL			_MMIO16(0xbf80104a)
-#define JOY_BAUD			_MMIO16(0xbf80104e)
+#define JOY_TXRX			_MMIO8 (IOBASE | 0x1040)
+#define JOY_STAT			_MMIO16(IOBASE | 0x1044)
+#define JOY_MODE			_MMIO16(IOBASE | 0x1048)
+#define JOY_CTRL			_MMIO16(IOBASE | 0x104a)
+#define JOY_BAUD			_MMIO16(IOBASE | 0x104e)
 
 /* Serial port */
 
-#define SIO_TXRX			_MMIO8(0xbf801050)
-#define SIO_STAT			_MMIO16(0xbf801054)
-#define SIO_MODE			_MMIO16(0xbf801058)
-#define SIO_CTRL			_MMIO16(0xbf80105a)
-#define SIO_BAUD			_MMIO16(0xbf80105e)
+#define SIO_TXRX			_MMIO8 (IOBASE | 0x1050)
+#define SIO_STAT			_MMIO16(IOBASE | 0x1054)
+#define SIO_MODE			_MMIO16(IOBASE | 0x1058)
+#define SIO_CTRL			_MMIO16(IOBASE | 0x105a)
+#define SIO_BAUD			_MMIO16(IOBASE | 0x105e)
 
 /* IRQ controller */
 
-#define IRQ_STAT			_MMIO32(0xbf801070)
-#define IRQ_MASK			_MMIO32(0xbf801074)
+#define IRQ_STAT			_MMIO32(IOBASE | 0x1070)
+#define IRQ_MASK			_MMIO32(IOBASE | 0x1074)
 
 /* DMA */
 
-#define DMA_DPCR			_MMIO32(0xbf8010f0)
-#define DMA_DICR			_MMIO32(0xbf8010f4)
+#define DMA_DPCR			_MMIO32(IOBASE | 0x10f0)
+#define DMA_DICR			_MMIO32(IOBASE | 0x10f4)
 
-#define DMA_MADR(N)			_MMIO32(0xbf801080 + 16 * (N))
-#define DMA_BCR(N)			_MMIO32(0xbf801084 + 16 * (N))
-#define DMA_CHCR(N)			_MMIO32(0xbf801088 + 16 * (N))
+#define DMA_MADR(N)			_MMIO32(IOBASE | 0x1080 + 16 * (N))
+#define DMA_BCR(N)			_MMIO32(IOBASE | 0x1084 + 16 * (N))
+#define DMA_CHCR(N)			_MMIO32(IOBASE | 0x1088 + 16 * (N))
 
 /* Timers */
 
-#define TIMER_VALUE(N)		_MMIO32(0xbf801100 + 16 * (N))
-#define TIMER_CTRL(N)		_MMIO32(0xbf801104 + 16 * (N))
-#define TIMER_RELOAD(N)		_MMIO32(0xbf801108 + 16 * (N))
+#define TIMER_VALUE(N)		_MMIO32(IOBASE | 0x1100 + 16 * (N))
+#define TIMER_CTRL(N)		_MMIO32(IOBASE | 0x1104 + 16 * (N))
+#define TIMER_RELOAD(N)		_MMIO32(IOBASE | 0x1108 + 16 * (N))
 
 /* Memory control */
 
-#define EXP1_ADDR			_MMIO32(0xbf801000)
-#define EXP2_ADDR			_MMIO32(0xbf801004)
-#define EXP1_DELAY_SIZE		_MMIO32(0xbf801008)
-#define EXP3_DELAY_SIZE		_MMIO32(0xbf80100c)
-#define BIOS_DELAY_SIZE		_MMIO32(0xbf801010)
-#define SPU_DELAY_SIZE		_MMIO32(0xbf801014)
-#define CD_DELAY_SIZE		_MMIO32(0xbf801018)
-#define EXP2_DELAY_SIZE		_MMIO32(0xbf80101c)
-#define COM_DELAY_CFG		_MMIO32(0xbf801020)
-#define RAM_SIZE_CFG		_MMIO32(0xbf801060)
+#define EXP1_ADDR			_MMIO32(IOBASE | 0x1000)
+#define EXP2_ADDR			_MMIO32(IOBASE | 0x1004)
+#define EXP1_DELAY_SIZE		_MMIO32(IOBASE | 0x1008)
+#define EXP3_DELAY_SIZE		_MMIO32(IOBASE | 0x100c)
+#define BIOS_DELAY_SIZE		_MMIO32(IOBASE | 0x1010)
+#define SPU_DELAY_SIZE		_MMIO32(IOBASE | 0x1014)
+#define CD_DELAY_SIZE		_MMIO32(IOBASE | 0x1018)
+#define EXP2_DELAY_SIZE		_MMIO32(IOBASE | 0x101c)
+#define COM_DELAY_CFG		_MMIO32(IOBASE | 0x1020)
+#define RAM_SIZE_CFG		_MMIO32(IOBASE | 0x1060)
 
 #endif
diff --git a/libpsn00b/include/psxspu.h b/libpsn00b/include/psxspu.h
index 36bbe70..e4c667a 100644
--- a/libpsn00b/include/psxspu.h
+++ b/libpsn00b/include/psxspu.h
@@ -7,6 +7,8 @@
 #define __PSXSPU_H
 
 #include <stdint.h>
+#include <stddef.h>
+#include <hwregs_c.h>
 
 /* Definitions */
 
@@ -33,10 +35,15 @@ typedef enum _SPU_AttrMask {
 } SPU_AttrMask;
 
 typedef enum _SPU_TransferMode {
-	SPU_TRANSFER_BY_DMA		= 0,
-	SPU_TRANSFER_BY_IO		= 1
+	SPU_TRANSFER_BY_DMA	= 0,
+	SPU_TRANSFER_BY_IO	= 1
 } SPU_TransferMode;
 
+typedef enum _SPU_WaitMode {
+	SPU_TRANSFER_PEEK	= 0,
+	SPU_TRANSFER_WAIT	= 1
+} SPU_WaitMode;
+
 /* Structure definitions */
 
 typedef struct _SpuVolume {
@@ -66,6 +73,36 @@ typedef struct _SpuCommonAttr {
 	SpuExtAttr	cd, ext;
 } SpuCommonAttr;
 
+/* "Useless" macros for official SDK compatibility */
+
+#define SpuSetCommonMasterVolume(left, right) \
+	(SPU_MASTER_VOL_L = (left), SPU_MASTER_VOL_R = (right))
+#define SpuSetCommonCDVolume(left, right) \
+	(SPU_CD_VOL_L = (left), SPU_CD_VOL_R = (right))
+#define SpuSetCommonCDReverb(enable) \
+	((enable) ? (SPU_CTRL |= 0x0004) : (SPU_CTRL &= 0xfffb))
+#define SpuSetCommonExtVolume(left, right) \
+	(SPU_EXT_VOL_L = (left), SPU_EXT_VOL_R = (right))
+#define SpuSetCommonExtReverb(enable) \
+	((enable) ? (SPU_CTRL |= 0x0002) : (SPU_CTRL &= 0xfffd))
+
+#define SpuSetReverbAddr(addr) \
+	(SPU_REVERB_ADDR = ((addr) + 7) / 8)
+#define SpuSetIRQAddr(addr) \
+	(SPU_IRQ_ADDR = ((addr) + 7) / 8)
+
+#define SpuSetVoiceVolume(ch, left, right) \
+	(SPU_CH_VOL_L(ch) = (left), SPU_CH_VOL_R(ch) = (right))
+#define SpuSetVoicePitch(ch, pitch) \
+	(SPU_CH_FREQ(ch) = (pitch))
+#define SpuSetVoiceStartAddr(ch, addr) \
+	(SPU_CH_ADDR(ch) = ((addr) + 7) / 8)
+#define SpuSetVoiceADSR(ch, ar, dr, sr, rr, sl) \
+	(SPU_CH_ADSR(ch) = ((sl)) | ((dr) << 4) | ((ar) << 8) | ((rr) << 16) | ((sr) << 22) | (1 << 30))
+
+#define SpuSetKey(enable, voice_bit) \
+	((enable) ? (SPU_KEY_ON = (voice_bit)) : (SPU_KEY_OFF = (voice_bit)))
+
 /* Public API */
 
 #ifdef __cplusplus
@@ -74,15 +111,11 @@ extern "C" {
 
 void SpuInit(void);
 
-void SpuReverbOn(int voice);
-void SpuSetReverbAddr(int addr);
-void SpuSetReverbVolume(int left, int right);
-void SpuSetKey(int on_off, uint32_t voice_bit);
-
-int SpuSetTransferMode(int mode);
-int SpuSetTransferStartAddr(int addr);
-int SpuWrite(const uint8_t *addr, int size);
-void SpuWait(void);
+void SpuRead(const uint32_t *data, size_t size);
+void SpuWrite(const uint32_t *data, size_t size);
+SPU_TransferMode SpuSetTransferMode(SPU_TransferMode mode);
+uint32_t SpuSetTransferStartAddr(uint32_t addr);
+int SpuIsTransferCompleted(int mode);
 
 #ifdef __cplusplus
 }