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| author | spicyjpeg <thatspicyjpeg@gmail.com> | 2022-10-27 16:55:08 +0200 |
|---|---|---|
| committer | spicyjpeg <thatspicyjpeg@gmail.com> | 2022-10-27 16:55:08 +0200 |
| commit | f6c41f3783c4fce49a9899b710ebb50ba9f647ab (patch) | |
| tree | 7133d4e05008cb11c05995d3c0ce7d938258cd51 /libpsn00b/include/hwregs_c.h | |
| parent | 4dbf47f129a55428b90df2805228fbd481e1d117 (diff) | |
| download | psn00bsdk-f6c41f3783c4fce49a9899b710ebb50ba9f647ab.tar.gz | |
Refactor sound examples, add new spustream example
Diffstat (limited to 'libpsn00b/include/hwregs_c.h')
| -rw-r--r-- | libpsn00b/include/hwregs_c.h | 21 |
1 files changed, 14 insertions, 7 deletions
diff --git a/libpsn00b/include/hwregs_c.h b/libpsn00b/include/hwregs_c.h index b205b87..0e21922 100644 --- a/libpsn00b/include/hwregs_c.h +++ b/libpsn00b/include/hwregs_c.h @@ -38,12 +38,18 @@ #define SPU_MASTER_VOL_R _MMIO16(IOBASE | 0x1d82) #define SPU_REVERB_VOL_L _MMIO16(IOBASE | 0x1d84) #define SPU_REVERB_VOL_R _MMIO16(IOBASE | 0x1d86) -#define SPU_KEY_ON _MMIO32(IOBASE | 0x1d88) -#define SPU_KEY_OFF _MMIO32(IOBASE | 0x1d8c) -#define SPU_FM_MODE _MMIO32(IOBASE | 0x1d90) -#define SPU_NOISE_MODE _MMIO32(IOBASE | 0x1d94) -#define SPU_REVERB_ON _MMIO32(IOBASE | 0x1d98) -#define SPU_CHAN_STATUS _MMIO32(IOBASE | 0x1d9c) +#define SPU_KEY_ON1 _MMIO16(IOBASE | 0x1d88) +#define SPU_KEY_ON2 _MMIO16(IOBASE | 0x1d8a) +#define SPU_KEY_OFF1 _MMIO16(IOBASE | 0x1d8c) +#define SPU_KEY_OFF2 _MMIO16(IOBASE | 0x1d8e) +#define SPU_FM_MODE1 _MMIO16(IOBASE | 0x1d90) +#define SPU_FM_MODE2 _MMIO16(IOBASE | 0x1d92) +#define SPU_NOISE_MODE1 _MMIO16(IOBASE | 0x1d94) +#define SPU_NOISE_MODE2 _MMIO16(IOBASE | 0x1d96) +#define SPU_REVERB_ON1 _MMIO16(IOBASE | 0x1d98) +#define SPU_REVERB_ON2 _MMIO16(IOBASE | 0x1d9a) +#define SPU_CHAN_STATUS1 _MMIO16(IOBASE | 0x1d9c) +#define SPU_CHAN_STATUS2 _MMIO16(IOBASE | 0x1d9e) #define SPU_REVERB_ADDR _MMIO16(IOBASE | 0x1da2) #define SPU_IRQ_ADDR _MMIO16(IOBASE | 0x1da4) @@ -67,7 +73,8 @@ #define SPU_CH_VOL_R(N) _MMIO16(IOBASE | 0x1c02 + 16 * (N)) #define SPU_CH_FREQ(N) _MMIO16(IOBASE | 0x1c04 + 16 * (N)) #define SPU_CH_ADDR(N) _MMIO16(IOBASE | 0x1c06 + 16 * (N)) -#define SPU_CH_ADSR(N) _MMIO32(IOBASE | 0x1c08 + 16 * (N)) +#define SPU_CH_ADSR1(N) _MMIO16(IOBASE | 0x1c08 + 16 * (N)) +#define SPU_CH_ADSR2(N) _MMIO16(IOBASE | 0x1c0a + 16 * (N)) #define SPU_CH_LOOP_ADDR(N) _MMIO16(IOBASE | 0x1c0e + 16 * (N)) /* MDEC */ |