diff options
| author | SND\shalma_cp <SND\shalma_cp@e17a0e51-4ae3-4d35-97c3-1a29b211df97> | 2010-11-05 01:34:18 +0000 |
|---|---|---|
| committer | SND\shalma_cp <SND\shalma_cp@e17a0e51-4ae3-4d35-97c3-1a29b211df97> | 2010-11-05 01:34:18 +0000 |
| commit | fe689494e432a145784ce2330fc0faf683dbf5e0 (patch) | |
| tree | 852603fe2bb842b7ad64d0505c16191832314fea /libpcsxcore | |
| parent | 80b1d885d1e4ff338cadf0e5c210ad87d7b9fdac (diff) | |
| download | pcsxr-fe689494e432a145784ce2330fc0faf683dbf5e0.tar.gz | |
Xenogears Agemo translation - psxinterpreter.c
- load delay slot
- should pass emu detection
- only works with interpreter
git-svn-id: https://pcsxr.svn.codeplex.com/svn/pcsxr@59194 e17a0e51-4ae3-4d35-97c3-1a29b211df97
Diffstat (limited to 'libpcsxcore')
| -rw-r--r-- | libpcsxcore/psxinterpreter.c | 159 |
1 files changed, 156 insertions, 3 deletions
diff --git a/libpcsxcore/psxinterpreter.c b/libpcsxcore/psxinterpreter.c index 633a307b..f6cf99fd 100644 --- a/libpcsxcore/psxinterpreter.c +++ b/libpcsxcore/psxinterpreter.c @@ -607,6 +607,18 @@ void psxJALR() { #define _oB_ (_u32(_rRs_) + _Imm_) void psxLB() { + // load delay = 1 latency
+ if( branch == 0 )
+ {
+ // simulate: beq r0,r0,lw+4 / lw / (delay slot)
+ psxRegs.pc -= 4;
+ doBranch( psxRegs.pc + 4 );
+
+ return;
+ }
+
+
+
if (_Rt_) { _i32(_rRt_) = (signed char)psxMemRead8(_oB_); } else { @@ -615,6 +627,18 @@ void psxLB() { } void psxLBU() { + // load delay = 1 latency
+ if( branch == 0 )
+ {
+ // simulate: beq r0,r0,lw+4 / lw / (delay slot)
+ psxRegs.pc -= 4;
+ doBranch( psxRegs.pc + 4 );
+
+ return;
+ }
+
+
+
if (_Rt_) { _u32(_rRt_) = psxMemRead8(_oB_); } else { @@ -623,6 +647,18 @@ void psxLBU() { } void psxLH() { + // load delay = 1 latency
+ if( branch == 0 )
+ {
+ // simulate: beq r0,r0,lw+4 / lw / (delay slot)
+ psxRegs.pc -= 4;
+ doBranch( psxRegs.pc + 4 );
+
+ return;
+ }
+
+
+
if (_Rt_) { _i32(_rRt_) = (short)psxMemRead16(_oB_); } else { @@ -631,6 +667,18 @@ void psxLH() { } void psxLHU() { + // load delay = 1 latency
+ if( branch == 0 )
+ {
+ // simulate: beq r0,r0,lw+4 / lw / (delay slot)
+ psxRegs.pc -= 4;
+ doBranch( psxRegs.pc + 4 );
+
+ return;
+ }
+
+
+
if (_Rt_) { _u32(_rRt_) = psxMemRead16(_oB_); } else { @@ -639,6 +687,18 @@ void psxLHU() { } void psxLW() { + // load delay = 1 latency
+ if( branch == 0 )
+ {
+ // simulate: beq r0,r0,lw+4 / lw / (delay slot)
+ psxRegs.pc -= 4;
+ doBranch( psxRegs.pc + 4 );
+
+ return;
+ }
+
+
+
if (_Rt_) { _u32(_rRt_) = psxMemRead32(_oB_); } else { @@ -653,7 +713,19 @@ void psxLWL() { u32 addr = _oB_; u32 shift = addr & 3; u32 mem = psxMemRead32(addr & ~3); +
+ // load delay = 1 latency
+ if( branch == 0 )
+ {
+ // simulate: beq r0,r0,lw+4 / lw / (delay slot)
+ psxRegs.pc -= 4;
+ doBranch( psxRegs.pc + 4 );
+
+ return;
+ }
+
+
if (!_Rt_) return; _u32(_rRt_) = ( _u32(_rRt_) & LWL_MASK[shift]) | ( mem << LWL_SHIFT[shift]); @@ -676,6 +748,20 @@ void psxLWR() { u32 shift = addr & 3; u32 mem = psxMemRead32(addr & ~3); +
+
+ // load delay = 1 latency
+ if( branch == 0 )
+ {
+ // simulate: beq r0,r0,lw+4 / lw / (delay slot)
+ psxRegs.pc -= 4;
+ doBranch( psxRegs.pc + 4 );
+
+ return;
+ }
+
+
+
if (!_Rt_) return; _u32(_rRt_) = ( _u32(_rRt_) & LWR_MASK[shift]) | ( mem >> LWR_SHIFT[shift]); @@ -739,8 +825,41 @@ void psxSWR() { * Moves between GPR and COPx * * Format: OP rt, fs * *********************************************************/ -void psxMFC0() { if (!_Rt_) return; _i32(_rRt_) = (int)_rFs_; } -void psxCFC0() { if (!_Rt_) return; _i32(_rRt_) = (int)_rFs_; } +void psxMFC0()
+{
+ // load delay = 1 latency
+ if( branch == 0 )
+ {
+ // simulate: beq r0,r0,lw+4 / lw / (delay slot)
+ psxRegs.pc -= 4;
+ doBranch( psxRegs.pc + 4 );
+
+ return;
+ }
+
+
+ if (!_Rt_) return;
+
+ _i32(_rRt_) = (int)_rFs_;
+}
+ +void psxCFC0()
+{
+ // load delay = 1 latency
+ if( branch == 0 )
+ {
+ // simulate: beq r0,r0,lw+4 / lw / (delay slot)
+ psxRegs.pc -= 4;
+ doBranch( psxRegs.pc + 4 );
+
+ return;
+ }
+
+
+ if (!_Rt_) return;
+
+ _i32(_rRt_) = (int)_rFs_;
+} void psxTestSWInts() { // the next code is untested, if u know please @@ -773,6 +892,40 @@ __inline void MTC0(int reg, u32 val) { void psxMTC0() { MTC0(_Rd_, _u32(_rRt_)); } void psxCTC0() { MTC0(_Rd_, _u32(_rRt_)); } +
+
+void psxMFC2()
+{
+ // load delay = 1 latency
+ if( branch == 0 )
+ {
+ // simulate: beq r0,r0,lw+4 / lw / (delay slot)
+ psxRegs.pc -= 4;
+ doBranch( psxRegs.pc + 4 );
+
+ return;
+ }
+
+ gteMFC2();
+}
+
+
+void psxCFC2()
+{
+ // load delay = 1 latency
+ if( branch == 0 )
+ {
+ // simulate: beq r0,r0,lw+4 / lw / (delay slot)
+ psxRegs.pc -= 4;
+ doBranch( psxRegs.pc + 4 );
+
+ return;
+ }
+
+ gteCFC2();
+}
+
+
/********************************************************* * Unknow instruction (would generate an exception) * * Format: ? * @@ -860,7 +1013,7 @@ void (*psxCP2[64])() = { }; void (*psxCP2BSC[32])() = { - gteMFC2, psxNULL, gteCFC2, psxNULL, gteMTC2, psxNULL, gteCTC2, psxNULL, + psxMFC2, psxNULL, psxCFC2, psxNULL, gteMTC2, psxNULL, gteCTC2, psxNULL, psxNULL, psxNULL, psxNULL, psxNULL, psxNULL, psxNULL, psxNULL, psxNULL, psxNULL, psxNULL, psxNULL, psxNULL, psxNULL, psxNULL, psxNULL, psxNULL, psxNULL, psxNULL, psxNULL, psxNULL, psxNULL, psxNULL, psxNULL, psxNULL |