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authorXavier Del Campo Romero <xavi.dcr@tutanota.com>2020-06-08 00:20:26 +0200
committerXavier Del Campo Romero <xavi.dcr@tutanota.com>2020-06-08 00:20:26 +0200
commitaa89de282b092a6ffd5995add48ee366a1ead119 (patch)
treec4bd936e13804a5b5d61b7935e60249c7bac10da /libpcsxcore
parent4458c537ac243228097a5f43bc287b328dc76258 (diff)
downloadpcsxr-aa89de282b092a6ffd5995add48ee366a1ead119.tar.gz
gdb halt command was not being sent to CPU interpreter
Diffstat (limited to 'libpcsxcore')
-rw-r--r--libpcsxcore/psxinterpreter.c12
-rw-r--r--libpcsxcore/r3000a.h11
2 files changed, 16 insertions, 7 deletions
diff --git a/libpcsxcore/psxinterpreter.c b/libpcsxcore/psxinterpreter.c
index 941fda4b..0066b7c7 100644
--- a/libpcsxcore/psxinterpreter.c
+++ b/libpcsxcore/psxinterpreter.c
@@ -1182,6 +1182,12 @@ static void intReset() {
psxRegs.ICache_valid = FALSE;
}
+static int halt;
+
+static void intHalt() {
+ halt = 1;
+}
+
static void intExecute() {
for (;;)
execI();
@@ -1207,7 +1213,7 @@ static void process_gdb(void) {
if (shutdown)
return;
- if (step || (must_continue && tgt_addr && tgt_addr == psxRegs.pc)) {
+ if (halt || step || (must_continue && tgt_addr && tgt_addr == psxRegs.pc)) {
msg.type = MSG_TYPE_HIT;
#if DEBUG == 1
printf("hit address 0x%08X\n", psxRegs.pc);
@@ -1215,6 +1221,7 @@ static void process_gdb(void) {
gdbstub_sys_send(&msg);
must_continue = 0;
step = 0;
+ halt = 0;
}
if (!must_continue) {
@@ -1283,5 +1290,6 @@ R3000Acpu psxInt = {
intExecuteBlock,
intClear,
intShutdown,
- intSetPGXPMode
+ intSetPGXPMode,
+ intHalt
};
diff --git a/libpcsxcore/r3000a.h b/libpcsxcore/r3000a.h
index b0616256..1592a020 100644
--- a/libpcsxcore/r3000a.h
+++ b/libpcsxcore/r3000a.h
@@ -37,6 +37,7 @@ typedef struct {
void (*Clear)(u32 Addr, u32 Size);
void (*Shutdown)();
void (*SetPGXPMode)(u32 pgxpMode);
+ void (*Halt)(); /* stops CPU */
} R3000Acpu;
extern R3000Acpu *psxCpu;
@@ -291,11 +292,11 @@ static inline u32 *Read_ICache(u32 pc, boolean isolate) {
/**** R3000A Instruction Macros ****/
#define _PC_ psxRegs.pc // The next PC to be executed
-#define _fOp_(code) ((code >> 26) ) // The opcode part of the instruction register
-#define _fFunct_(code) ((code ) & 0x3F) // The funct part of the instruction register
-#define _fRd_(code) ((code >> 11) & 0x1F) // The rd part of the instruction register
-#define _fRt_(code) ((code >> 16) & 0x1F) // The rt part of the instruction register
-#define _fRs_(code) ((code >> 21) & 0x1F) // The rs part of the instruction register
+#define _fOp_(code) ((code >> 26) ) // The opcode part of the instruction register
+#define _fFunct_(code) ((code ) & 0x3F) // The funct part of the instruction register
+#define _fRd_(code) ((code >> 11) & 0x1F) // The rd part of the instruction register
+#define _fRt_(code) ((code >> 16) & 0x1F) // The rt part of the instruction register
+#define _fRs_(code) ((code >> 21) & 0x1F) // The rs part of the instruction register
#define _fSa_(code) ((code >> 6) & 0x1F) // The sa part of the instruction register
#define _fIm_(code) ((u16)code) // The immediate part of the instruction register
#define _fTarget_(code) (code & 0x03ffffff) // The target part of the instruction register