use %x instead of %lx.

git-svn-id: https://pcsxr.svn.codeplex.com/svn/pcsxr@50501 e17a0e51-4ae3-4d35-97c3-1a29b211df97

4 files changed, 96 insertions, 96 deletions

diff --git a/libpcsxcore/cdrom.c b/libpcsxcore/cdrom.c
index 55657e7f..2f03dd46 100644
--- a/libpcsxcore/cdrom.c
+++ b/libpcsxcore/cdrom.c
@@ -1084,7 +1084,7 @@ void psxDma3(u32 madr, u32 bcr, u32 chcr) {
 	u8 *ptr;
 
 #ifdef CDR_LOG
-	CDR_LOG("psxDma3() Log: *** DMA 3 *** %lx addr = %lx size = %lx\n", chcr, madr, bcr);
+	CDR_LOG("psxDma3() Log: *** DMA 3 *** %x addr = %x size = %x\n", chcr, madr, bcr);
 #endif
 
 	switch (chcr) {
@@ -1112,7 +1112,7 @@ void psxDma3(u32 madr, u32 bcr, u32 chcr) {
 			break;
 		default:
 #ifdef CDR_LOG
-			CDR_LOG("psxDma3() Log: Unknown cddma %lx\n", chcr);
+			CDR_LOG("psxDma3() Log: Unknown cddma %x\n", chcr);
 #endif
 			break;
 	}
diff --git a/libpcsxcore/psxbios.c b/libpcsxcore/psxbios.c
index f19ce612..1dc18ccd 100644
--- a/libpcsxcore/psxbios.c
+++ b/libpcsxcore/psxbios.c
@@ -391,7 +391,7 @@ void psxBios_strncat() { // 0x16
 	s32 n = a2;
 
 #ifdef PSXBIOS_LOG
-	PSXBIOS_LOG("psxBios_%s: %s (%lx), %s (%lx), %d\n", biosA0n[0x16], Ra0, a0, Ra1, a1, a2);
+	PSXBIOS_LOG("psxBios_%s: %s (%x), %s (%x), %d\n", biosA0n[0x16], Ra0, a0, Ra1, a1, a2);
 #endif
 
 	while (*p1++);
@@ -410,7 +410,7 @@ void psxBios_strcmp() { // 0x17
 	char *p1 = (char *)Ra0, *p2 = (char *)Ra1;
 
 #ifdef PSXBIOS_LOG
-	PSXBIOS_LOG("psxBios_%s: %s (%lx), %s (%lx)\n", biosA0n[0x17], Ra0, a0, Ra1, a1);
+	PSXBIOS_LOG("psxBios_%s: %s (%x), %s (%x)\n", biosA0n[0x17], Ra0, a0, Ra1, a1);
 #endif
 
 	while (*p1 == *p2++) {
@@ -430,7 +430,7 @@ void psxBios_strncmp() { // 0x18
 	s32 n = a2;
 
 #ifdef PSXBIOS_LOG
-	PSXBIOS_LOG("psxBios_%s: %s (%lx), %s (%lx), %d\n", biosA0n[0x18], Ra0, a0, Ra1, a1, a2);
+	PSXBIOS_LOG("psxBios_%s: %s (%x), %s (%x), %d\n", biosA0n[0x18], Ra0, a0, Ra1, a1, a2);
 #endif
 
 	while (--n >= 0 && *p1 == *p2++) {
@@ -836,7 +836,7 @@ void psxBios_malloc() { // 0x33
 
 	// exit on uninitialized heap
 	if (chunk == NULL) {
-		SysPrintf("malloc %lx,%lx: Uninitialized Heap!\n", v0, a0);
+		SysPrintf("malloc %x,%x: Uninitialized Heap!\n", v0, a0);
 		v0 = 0;
 		pc0 = ra;
 		return;
@@ -850,7 +850,7 @@ void psxBios_malloc() { // 0x33
 	}
 
 	// catch out of memory
-	if(chunk >= heap_end) { SysPrintf("malloc %lx,%lx: Out of memory error!\n", v0, a0); v0 = 0; pc0 = ra; return; }
+	if(chunk >= heap_end) { SysPrintf("malloc %x,%x: Out of memory error!\n", v0, a0); v0 = 0; pc0 = ra; return; }
 	
 	// allocate memory
 	if(dsize == csize) {
@@ -867,7 +867,7 @@ void psxBios_malloc() { // 0x33
 	// return pointer to allocated memory
 	v0 = ((unsigned long)chunk - (unsigned long)psxM) + 4;
 	v0|= 0x80000000;
-	SysPrintf ("malloc %lx,%lx\n", v0, a0);
+	SysPrintf ("malloc %x,%x\n", v0, a0);
 	pc0 = ra;
 }
 
@@ -877,7 +877,7 @@ void psxBios_free() { // 0x34
 	PSXBIOS_LOG("psxBios_%s\n", biosA0n[0x34]);
 #endif
 
-	SysPrintf("free %lx: %lx bytes\n", a0, *(u32*)(Ra0-4));
+	SysPrintf("free %x: %x bytes\n", a0, *(u32*)(Ra0-4));
 
 	*(u32*)(Ra0-4) |= 1;	// set chunk to free
 	pc0 = ra;
@@ -924,7 +924,7 @@ void psxBios_InitHeap() { // 0x39
 	heap_end = (u32 *)((u8 *)heap_addr + size);
 	*heap_addr = SWAP32(size | 1);
 
-	SysPrintf("InitHeap %lx,%lx : %lx %lx\n",a0,a1, (uptr)heap_addr-(uptr)psxM, size);
+	SysPrintf("InitHeap %x,%x : %x %x\n",a0,a1, (uptr)heap_addr-(uptr)psxM, size);
 
 	pc0 = ra;
 }
@@ -2171,7 +2171,7 @@ void psxBios_ChangeClearRCnt() { // 0a
 
 void psxBios_dummy() { 
 #ifdef PSXBIOS_LOG
-	PSXBIOS_LOG("unk %lx call: %lx\n", pc0 & 0x1fffff, t1);
+	PSXBIOS_LOG("unk %x call: %x\n", pc0 & 0x1fffff, t1);
 #endif
 	pc0 = ra; 
 }
diff --git a/libpcsxcore/psxdma.c b/libpcsxcore/psxdma.c
index fa29101f..f59f268e 100644
--- a/libpcsxcore/psxdma.c
+++ b/libpcsxcore/psxdma.c
@@ -38,7 +38,7 @@ void psxDma4(u32 madr, u32 bcr, u32 chcr) { // SPU
 	switch (chcr) {
 		case 0x01000201: //cpu to spu transfer
 #ifdef PSXDMA_LOG
-			PSXDMA_LOG("*** DMA4 SPU - mem2spu *** %lx addr = %lx size = %lx\n", chcr, madr, bcr);
+			PSXDMA_LOG("*** DMA4 SPU - mem2spu *** %x addr = %x size = %x\n", chcr, madr, bcr);
 #endif
 			ptr = (u16 *)PSXM(madr);
 			if (ptr == NULL) {
@@ -53,7 +53,7 @@ void psxDma4(u32 madr, u32 bcr, u32 chcr) { // SPU
 
 		case 0x01000200: //spu to cpu transfer
 #ifdef PSXDMA_LOG
-			PSXDMA_LOG("*** DMA4 SPU - spu2mem *** %lx addr = %lx size = %lx\n", chcr, madr, bcr);
+			PSXDMA_LOG("*** DMA4 SPU - spu2mem *** %x addr = %x size = %x\n", chcr, madr, bcr);
 #endif
 			ptr = (u16 *)PSXM(madr);
 			if (ptr == NULL) {
@@ -69,7 +69,7 @@ void psxDma4(u32 madr, u32 bcr, u32 chcr) { // SPU
 
 #ifdef PSXDMA_LOG
 		default:
-			PSXDMA_LOG("*** DMA4 SPU - unknown *** %lx addr = %lx size = %lx\n", chcr, madr, bcr);
+			PSXDMA_LOG("*** DMA4 SPU - unknown *** %x addr = %x size = %x\n", chcr, madr, bcr);
 			break;
 #endif
 	}
@@ -85,7 +85,7 @@ void psxDma2(u32 madr, u32 bcr, u32 chcr) { // GPU
 	switch(chcr) {
 		case 0x01000200: // vram2mem
 #ifdef PSXDMA_LOG
-			PSXDMA_LOG("*** DMA2 GPU - vram2mem *** %lx addr = %lx size = %lx\n", chcr, madr, bcr);
+			PSXDMA_LOG("*** DMA2 GPU - vram2mem *** %x addr = %x size = %x\n", chcr, madr, bcr);
 #endif
 			ptr = (u32 *)PSXM(madr);
 			if (ptr == NULL) {
@@ -101,7 +101,7 @@ void psxDma2(u32 madr, u32 bcr, u32 chcr) { // GPU
 
 		case 0x01000201: // mem2vram
 #ifdef PSXDMA_LOG
-			PSXDMA_LOG("*** DMA 2 - GPU mem2vram *** %lx addr = %lx size = %lx\n", chcr, madr, bcr);
+			PSXDMA_LOG("*** DMA 2 - GPU mem2vram *** %x addr = %x size = %x\n", chcr, madr, bcr);
 #endif
 			ptr = (u32 *)PSXM(madr);
 			if (ptr == NULL) {
@@ -117,14 +117,14 @@ void psxDma2(u32 madr, u32 bcr, u32 chcr) { // GPU
 
 		case 0x01000401: // dma chain
 #ifdef PSXDMA_LOG
-			PSXDMA_LOG("*** DMA 2 - GPU dma chain *** %lx addr = %lx size = %lx\n", chcr, madr, bcr);
+			PSXDMA_LOG("*** DMA 2 - GPU dma chain *** %x addr = %x size = %x\n", chcr, madr, bcr);
 #endif
 			GPU_dmaChain((u32 *)psxM, madr & 0x1fffff);
 			break;
 
 #ifdef PSXDMA_LOG
 		default:
-			PSXDMA_LOG("*** DMA 2 - GPU unknown *** %lx addr = %lx size = %lx\n", chcr, madr, bcr);
+			PSXDMA_LOG("*** DMA 2 - GPU unknown *** %x addr = %x size = %x\n", chcr, madr, bcr);
 			break;
 #endif
 	}
@@ -142,7 +142,7 @@ void psxDma6(u32 madr, u32 bcr, u32 chcr) {
 	u32 *mem = (u32 *)PSXM(madr);
 
 #ifdef PSXDMA_LOG
-	PSXDMA_LOG("*** DMA6 OT *** %lx addr = %lx size = %lx\n", chcr, madr, bcr);
+	PSXDMA_LOG("*** DMA6 OT *** %x addr = %x size = %x\n", chcr, madr, bcr);
 #endif
 
 	if (chcr == 0x11000002) {
@@ -164,7 +164,7 @@ void psxDma6(u32 madr, u32 bcr, u32 chcr) {
 #ifdef PSXDMA_LOG
 	else {
 		// Unknown option
-		PSXDMA_LOG("*** DMA6 OT - unknown *** %lx addr = %lx size = %lx\n", chcr, madr, bcr);
+		PSXDMA_LOG("*** DMA6 OT - unknown *** %x addr = %x size = %x\n", chcr, madr, bcr);
 	}
 #endif
 
diff --git a/libpcsxcore/psxhw.c b/libpcsxcore/psxhw.c
index 16a749ff..9f48dad0 100644
--- a/libpcsxcore/psxhw.c
+++ b/libpcsxcore/psxhw.c
@@ -49,13 +49,13 @@ u8 psxHwRead8(u32 add) {
 		default:
 			hard = psxHu8(add); 
 #ifdef PSXHW_LOG
-			PSXHW_LOG("*Unkwnown 8bit read at address %lx\n", add);
+			PSXHW_LOG("*Unkwnown 8bit read at address %x\n", add);
 #endif
 			return hard;
 	}
 
 #ifdef PSXHW_LOG
-	PSXHW_LOG("*Known 8bit read at address %lx value %x\n", add, hard);
+	PSXHW_LOG("*Known 8bit read at address %x value %x\n", add, hard);
 #endif
 	return hard;
 }
@@ -77,31 +77,31 @@ u16 psxHwRead16(u32 add) {
 			hard = sioRead8();
 			hard|= sioRead8() << 8;
 #ifdef PAD_LOG
-			PAD_LOG("sio read16 %lx; ret = %x\n", add&0xf, hard);
+			PAD_LOG("sio read16 %x; ret = %x\n", add&0xf, hard);
 #endif
 			return hard;
 		case 0x1f801044:
 			hard = sioReadStat16();
 #ifdef PAD_LOG
-			PAD_LOG("sio read16 %lx; ret = %x\n", add&0xf, hard);
+			PAD_LOG("sio read16 %x; ret = %x\n", add&0xf, hard);
 #endif
 			return hard;
 		case 0x1f801048:
 			hard = sioReadMode16();
 #ifdef PAD_LOG
-			PAD_LOG("sio read16 %lx; ret = %x\n", add&0xf, hard);
+			PAD_LOG("sio read16 %x; ret = %x\n", add&0xf, hard);
 #endif
 			return hard;
 		case 0x1f80104a:
 			hard = sioReadCtrl16();
 #ifdef PAD_LOG
-			PAD_LOG("sio read16 %lx; ret = %x\n", add&0xf, hard);
+			PAD_LOG("sio read16 %x; ret = %x\n", add&0xf, hard);
 #endif
 			return hard;
 		case 0x1f80104e:
 			hard = sioReadBaud16();
 #ifdef PAD_LOG
-			PAD_LOG("sio read16 %lx; ret = %x\n", add&0xf, hard);
+			PAD_LOG("sio read16 %x; ret = %x\n", add&0xf, hard);
 #endif
 			return hard;
 
@@ -175,14 +175,14 @@ u16 psxHwRead16(u32 add) {
 			} else {
 				hard = psxHu16(add); 
 #ifdef PSXHW_LOG
-				PSXHW_LOG("*Unkwnown 16bit read at address %lx\n", add);
+				PSXHW_LOG("*Unkwnown 16bit read at address %x\n", add);
 #endif
 			}
             return hard;
 	}
 	
 #ifdef PSXHW_LOG
-	PSXHW_LOG("*Known 16bit read at address %lx value %x\n", add, hard);
+	PSXHW_LOG("*Known 16bit read at address %x value %x\n", add, hard);
 #endif
 	return hard;
 }
@@ -197,14 +197,14 @@ u32 psxHwRead32(u32 add) {
 			hard |= sioRead8() << 16;
 			hard |= sioRead8() << 24;
 #ifdef PAD_LOG
-			PAD_LOG("sio read32 ;ret = %lx\n", hard);
+			PAD_LOG("sio read32 ;ret = %x\n", hard);
 #endif
 			return hard;
 			
 	//	case 0x1f801050: hard = serial_read32(); break;//serial port
 #ifdef PSXHW_LOG
 		case 0x1f801060:
-			PSXHW_LOG("RAM size read %lx\n", psxHu32(0x1060));
+			PSXHW_LOG("RAM size read %x\n", psxHu32(0x1060));
 			return psxHu32(0x1060);
 #endif
 #ifdef PSXHW_LOG
@@ -219,13 +219,13 @@ u32 psxHwRead32(u32 add) {
 		case 0x1f801810:
 			hard = GPU_readData();
 #ifdef PSXHW_LOG
-			PSXHW_LOG("GPU DATA 32bit read %lx\n", hard);
+			PSXHW_LOG("GPU DATA 32bit read %x\n", hard);
 #endif
 			return hard;
 		case 0x1f801814:
 			hard = GPU_readStatus();
 #ifdef PSXHW_LOG
-			PSXHW_LOG("GPU STATUS 32bit read %lx\n", hard);
+			PSXHW_LOG("GPU STATUS 32bit read %x\n", hard);
 #endif
 			return hard;
 
@@ -234,25 +234,25 @@ u32 psxHwRead32(u32 add) {
 
 #ifdef PSXHW_LOG
 		case 0x1f8010a0:
-			PSXHW_LOG("DMA2 MADR 32bit read %lx\n", psxHu32(0x10a0));
+			PSXHW_LOG("DMA2 MADR 32bit read %x\n", psxHu32(0x10a0));
 			return SWAPu32(HW_DMA2_MADR);
 		case 0x1f8010a4:
-			PSXHW_LOG("DMA2 BCR 32bit read %lx\n", psxHu32(0x10a4));
+			PSXHW_LOG("DMA2 BCR 32bit read %x\n", psxHu32(0x10a4));
 			return SWAPu32(HW_DMA2_BCR);
 		case 0x1f8010a8:
-			PSXHW_LOG("DMA2 CHCR 32bit read %lx\n", psxHu32(0x10a8));
+			PSXHW_LOG("DMA2 CHCR 32bit read %x\n", psxHu32(0x10a8));
 			return SWAPu32(HW_DMA2_CHCR);
 #endif
 
 #ifdef PSXHW_LOG
 		case 0x1f8010b0:
-			PSXHW_LOG("DMA3 MADR 32bit read %lx\n", psxHu32(0x10b0));
+			PSXHW_LOG("DMA3 MADR 32bit read %x\n", psxHu32(0x10b0));
 			return SWAPu32(HW_DMA3_MADR);
 		case 0x1f8010b4:
-			PSXHW_LOG("DMA3 BCR 32bit read %lx\n", psxHu32(0x10b4));
+			PSXHW_LOG("DMA3 BCR 32bit read %x\n", psxHu32(0x10b4));
 			return SWAPu32(HW_DMA3_BCR);
 		case 0x1f8010b8:
-			PSXHW_LOG("DMA3 CHCR 32bit read %lx\n", psxHu32(0x10b8));
+			PSXHW_LOG("DMA3 CHCR 32bit read %x\n", psxHu32(0x10b8));
 			return SWAPu32(HW_DMA3_CHCR);
 #endif
 
@@ -269,67 +269,67 @@ u32 psxHwRead32(u32 add) {
 		case 0x1f801100:
 			hard = psxRcntRcount(0);
 #ifdef PSXHW_LOG
-			PSXHW_LOG("T0 count read32: %lx\n", hard);
+			PSXHW_LOG("T0 count read32: %x\n", hard);
 #endif
 			return hard;
 		case 0x1f801104:
 			hard = psxRcntRmode(0);
 #ifdef PSXHW_LOG
-			PSXHW_LOG("T0 mode read32: %lx\n", hard);
+			PSXHW_LOG("T0 mode read32: %x\n", hard);
 #endif
 			return hard;
 		case 0x1f801108:
 			hard = psxRcntRtarget(0);
 #ifdef PSXHW_LOG
-			PSXHW_LOG("T0 target read32: %lx\n", hard);
+			PSXHW_LOG("T0 target read32: %x\n", hard);
 #endif
 			return hard;
 		case 0x1f801110:
 			hard = psxRcntRcount(1);
 #ifdef PSXHW_LOG
-			PSXHW_LOG("T1 count read32: %lx\n", hard);
+			PSXHW_LOG("T1 count read32: %x\n", hard);
 #endif
 			return hard;
 		case 0x1f801114:
 			hard = psxRcntRmode(1);
 #ifdef PSXHW_LOG
-			PSXHW_LOG("T1 mode read32: %lx\n", hard);
+			PSXHW_LOG("T1 mode read32: %x\n", hard);
 #endif
 			return hard;
 		case 0x1f801118:
 			hard = psxRcntRtarget(1);
 #ifdef PSXHW_LOG
-			PSXHW_LOG("T1 target read32: %lx\n", hard);
+			PSXHW_LOG("T1 target read32: %x\n", hard);
 #endif
 			return hard;
 		case 0x1f801120:
 			hard = psxRcntRcount(2);
 #ifdef PSXHW_LOG
-			PSXHW_LOG("T2 count read32: %lx\n", hard);
+			PSXHW_LOG("T2 count read32: %x\n", hard);
 #endif
 			return hard;
 		case 0x1f801124:
 			hard = psxRcntRmode(2);
 #ifdef PSXHW_LOG
-			PSXHW_LOG("T2 mode read32: %lx\n", hard);
+			PSXHW_LOG("T2 mode read32: %x\n", hard);
 #endif
 			return hard;
 		case 0x1f801128:
 			hard = psxRcntRtarget(2);
 #ifdef PSXHW_LOG
-			PSXHW_LOG("T2 target read32: %lx\n", hard);
+			PSXHW_LOG("T2 target read32: %x\n", hard);
 #endif
 			return hard;
 
 		default:
 			hard = psxHu32(add); 
 #ifdef PSXHW_LOG
-			PSXHW_LOG("*Unkwnown 32bit read at address %lx\n", add);
+			PSXHW_LOG("*Unkwnown 32bit read at address %x\n", add);
 #endif
 			return hard;
 	}
 #ifdef PSXHW_LOG
-	PSXHW_LOG("*Known 32bit read at address %lx\n", add);
+	PSXHW_LOG("*Known 32bit read at address %x\n", add);
 #endif
 	return hard;
 }
@@ -346,13 +346,13 @@ void psxHwWrite8(u32 add, u8 value) {
 		default:
 			psxHu8(add) = value;
 #ifdef PSXHW_LOG
-			PSXHW_LOG("*Unknown 8bit write at address %lx value %x\n", add, value);
+			PSXHW_LOG("*Unknown 8bit write at address %x value %x\n", add, value);
 #endif
 			return;
 	}
 	psxHu8(add) = value;
 #ifdef PSXHW_LOG
-	PSXHW_LOG("*Known 8bit write at address %lx value %x\n", add, value);
+	PSXHW_LOG("*Known 8bit write at address %x value %x\n", add, value);
 #endif
 }
 
@@ -362,31 +362,31 @@ void psxHwWrite16(u32 add, u16 value) {
 			sioWrite8((unsigned char)value);
 			sioWrite8((unsigned char)(value>>8));
 #ifdef PAD_LOG
-			PAD_LOG ("sio write16 %lx, %x\n", add&0xf, value);
+			PAD_LOG ("sio write16 %x, %x\n", add&0xf, value);
 #endif
 			return;
 		case 0x1f801044:
 			sioWriteStat16(value);
 #ifdef PAD_LOG
-			PAD_LOG ("sio write16 %lx, %x\n", add&0xf, value);
+			PAD_LOG ("sio write16 %x, %x\n", add&0xf, value);
 #endif
 			return;
 		case 0x1f801048:
             sioWriteMode16(value);
 #ifdef PAD_LOG
-			PAD_LOG ("sio write16 %lx, %x\n", add&0xf, value);
+			PAD_LOG ("sio write16 %x, %x\n", add&0xf, value);
 #endif
 			return;
 		case 0x1f80104a: // control register
 			sioWriteCtrl16(value);
 #ifdef PAD_LOG
-			PAD_LOG ("sio write16 %lx, %x\n", add&0xf, value);
+			PAD_LOG ("sio write16 %x, %x\n", add&0xf, value);
 #endif
 			return;
 		case 0x1f80104e: // baudrate register
             sioWriteBaud16(value);
 #ifdef PAD_LOG
-			PAD_LOG ("sio write16 %lx, %x\n", add&0xf, value);
+			PAD_LOG ("sio write16 %x, %x\n", add&0xf, value);
 #endif
 			return;
 
@@ -468,13 +468,13 @@ void psxHwWrite16(u32 add, u16 value) {
 
 			psxHu16ref(add) = SWAPu16(value);
 #ifdef PSXHW_LOG
-			PSXHW_LOG("*Unknown 16bit write at address %lx value %x\n", add, value);
+			PSXHW_LOG("*Unknown 16bit write at address %x value %x\n", add, value);
 #endif
 			return;
 	}
 	psxHu16ref(add) = SWAPu16(value);
 #ifdef PSXHW_LOG
-	PSXHW_LOG("*Known 16bit write at address %lx value %x\n", add, value);
+	PSXHW_LOG("*Known 16bit write at address %x value %x\n", add, value);
 #endif
 }
 
@@ -494,20 +494,20 @@ void psxHwWrite32(u32 add, u32 value) {
 			sioWrite8((unsigned char)((value&0xff) >> 16));
 			sioWrite8((unsigned char)((value&0xff) >> 24));
 #ifdef PAD_LOG
-			PAD_LOG("sio write32 %lx\n", value);
+			PAD_LOG("sio write32 %x\n", value);
 #endif
 			return;
 	//	case 0x1f801050: serial_write32(value); break;//serial port
 #ifdef PSXHW_LOG
 		case 0x1f801060:
-			PSXHW_LOG("RAM size write %lx\n", value);
+			PSXHW_LOG("RAM size write %x\n", value);
 			psxHu32ref(add) = SWAPu32(value);
 			return; // Ram size
 #endif
 
 		case 0x1f801070: 
 #ifdef PSXHW_LOG
-			PSXHW_LOG("IREG 32bit write %lx\n", value);
+			PSXHW_LOG("IREG 32bit write %x\n", value);
 #endif
 			if (Config.Sio) psxHu32ref(0x1070) |= SWAPu32(0x80);
 			if (Config.SpuIrq) psxHu32ref(0x1070) |= SWAPu32(0x200);
@@ -515,67 +515,67 @@ void psxHwWrite32(u32 add, u32 value) {
 			return;
 		case 0x1f801074:
 #ifdef PSXHW_LOG
-			PSXHW_LOG("IMASK 32bit write %lx\n", value);
+			PSXHW_LOG("IMASK 32bit write %x\n", value);
 #endif
 			psxHu32ref(0x1074) = SWAPu32(value);
 			return;
 
 #ifdef PSXHW_LOG
 		case 0x1f801080:
-			PSXHW_LOG("DMA0 MADR 32bit write %lx\n", value);
+			PSXHW_LOG("DMA0 MADR 32bit write %x\n", value);
 			HW_DMA0_MADR = SWAPu32(value); return; // DMA0 madr
 		case 0x1f801084:
-			PSXHW_LOG("DMA0 BCR 32bit write %lx\n", value);
+			PSXHW_LOG("DMA0 BCR 32bit write %x\n", value);
 			HW_DMA0_BCR  = SWAPu32(value); return; // DMA0 bcr
 #endif
 		case 0x1f801088:
 #ifdef PSXHW_LOG
-			PSXHW_LOG("DMA0 CHCR 32bit write %lx\n", value);
+			PSXHW_LOG("DMA0 CHCR 32bit write %x\n", value);
 #endif
 			DmaExec(0);	                 // DMA0 chcr (MDEC in DMA)
 			return;
 
 #ifdef PSXHW_LOG
 		case 0x1f801090:
-			PSXHW_LOG("DMA1 MADR 32bit write %lx\n", value);
+			PSXHW_LOG("DMA1 MADR 32bit write %x\n", value);
 			HW_DMA1_MADR = SWAPu32(value); return; // DMA1 madr
 		case 0x1f801094:
-			PSXHW_LOG("DMA1 BCR 32bit write %lx\n", value);
+			PSXHW_LOG("DMA1 BCR 32bit write %x\n", value);
 			HW_DMA1_BCR  = SWAPu32(value); return; // DMA1 bcr
 #endif
 		case 0x1f801098:
 #ifdef PSXHW_LOG
-			PSXHW_LOG("DMA1 CHCR 32bit write %lx\n", value);
+			PSXHW_LOG("DMA1 CHCR 32bit write %x\n", value);
 #endif
 			DmaExec(1);                  // DMA1 chcr (MDEC out DMA)
 			return;
 
 #ifdef PSXHW_LOG
 		case 0x1f8010a0:
-			PSXHW_LOG("DMA2 MADR 32bit write %lx\n", value);
+			PSXHW_LOG("DMA2 MADR 32bit write %x\n", value);
 			HW_DMA2_MADR = SWAPu32(value); return; // DMA2 madr
 		case 0x1f8010a4:
-			PSXHW_LOG("DMA2 BCR 32bit write %lx\n", value);
+			PSXHW_LOG("DMA2 BCR 32bit write %x\n", value);
 			HW_DMA2_BCR  = SWAPu32(value); return; // DMA2 bcr
 #endif
 		case 0x1f8010a8:
 #ifdef PSXHW_LOG
-			PSXHW_LOG("DMA2 CHCR 32bit write %lx\n", value);
+			PSXHW_LOG("DMA2 CHCR 32bit write %x\n", value);
 #endif
 			DmaExec(2);                  // DMA2 chcr (GPU DMA)
 			return;
 
 #ifdef PSXHW_LOG
 		case 0x1f8010b0:
-			PSXHW_LOG("DMA3 MADR 32bit write %lx\n", value);
+			PSXHW_LOG("DMA3 MADR 32bit write %x\n", value);
 			HW_DMA3_MADR = SWAPu32(value); return; // DMA3 madr
 		case 0x1f8010b4:
-			PSXHW_LOG("DMA3 BCR 32bit write %lx\n", value);
+			PSXHW_LOG("DMA3 BCR 32bit write %x\n", value);
 			HW_DMA3_BCR  = SWAPu32(value); return; // DMA3 bcr
 #endif
 		case 0x1f8010b8:
 #ifdef PSXHW_LOG
-			PSXHW_LOG("DMA3 CHCR 32bit write %lx\n", value);
+			PSXHW_LOG("DMA3 CHCR 32bit write %x\n", value);
 #endif
 			DmaExec(3);                  // DMA3 chcr (CDROM DMA)
 			
@@ -583,15 +583,15 @@ void psxHwWrite32(u32 add, u32 value) {
 
 #ifdef PSXHW_LOG
 		case 0x1f8010c0:
-			PSXHW_LOG("DMA4 MADR 32bit write %lx\n", value);
+			PSXHW_LOG("DMA4 MADR 32bit write %x\n", value);
 			HW_DMA4_MADR = SWAPu32(value); return; // DMA4 madr
 		case 0x1f8010c4:
-			PSXHW_LOG("DMA4 BCR 32bit write %lx\n", value);
+			PSXHW_LOG("DMA4 BCR 32bit write %x\n", value);
 			HW_DMA4_BCR  = SWAPu32(value); return; // DMA4 bcr
 #endif
 		case 0x1f8010c8:
 #ifdef PSXHW_LOG
-			PSXHW_LOG("DMA4 CHCR 32bit write %lx\n", value);
+			PSXHW_LOG("DMA4 CHCR 32bit write %x\n", value);
 #endif
 			DmaExec(4);                  // DMA4 chcr (SPU DMA)
 			return;
@@ -604,29 +604,29 @@ void psxHwWrite32(u32 add, u32 value) {
 
 #ifdef PSXHW_LOG
 		case 0x1f8010e0:
-			PSXHW_LOG("DMA6 MADR 32bit write %lx\n", value);
+			PSXHW_LOG("DMA6 MADR 32bit write %x\n", value);
 			HW_DMA6_MADR = SWAPu32(value); return; // DMA6 bcr
 		case 0x1f8010e4:
-			PSXHW_LOG("DMA6 BCR 32bit write %lx\n", value);
+			PSXHW_LOG("DMA6 BCR 32bit write %x\n", value);
 			HW_DMA6_BCR  = SWAPu32(value); return; // DMA6 bcr
 #endif
 		case 0x1f8010e8:
 #ifdef PSXHW_LOG
-			PSXHW_LOG("DMA6 CHCR 32bit write %lx\n", value);
+			PSXHW_LOG("DMA6 CHCR 32bit write %x\n", value);
 #endif
 			DmaExec(6);                   // DMA6 chcr (OT clear)
 			return;
 
 #ifdef PSXHW_LOG
 		case 0x1f8010f0:
-			PSXHW_LOG("DMA PCR 32bit write %lx\n", value);
+			PSXHW_LOG("DMA PCR 32bit write %x\n", value);
 			HW_DMA_PCR = SWAPu32(value);
 			return;
 #endif
 
 		case 0x1f8010f4:
 #ifdef PSXHW_LOG
-			PSXHW_LOG("DMA ICR 32bit write %lx\n", value);
+			PSXHW_LOG("DMA ICR 32bit write %x\n", value);
 #endif
 		{
 			u32 tmp = (~value) & SWAPu32(HW_DMA_ICR);
@@ -636,12 +636,12 @@ void psxHwWrite32(u32 add, u32 value) {
 
 		case 0x1f801810:
 #ifdef PSXHW_LOG
-			PSXHW_LOG("GPU DATA 32bit write %lx\n", value);
+			PSXHW_LOG("GPU DATA 32bit write %x\n", value);
 #endif
 			GPU_writeData(value); return;
 		case 0x1f801814:
 #ifdef PSXHW_LOG
-			PSXHW_LOG("GPU STATUS 32bit write %lx\n", value);
+			PSXHW_LOG("GPU STATUS 32bit write %x\n", value);
 #endif
 			GPU_writeStatus(value); return;
 
@@ -652,62 +652,62 @@ void psxHwWrite32(u32 add, u32 value) {
 
 		case 0x1f801100:
 #ifdef PSXHW_LOG
-			PSXHW_LOG("COUNTER 0 COUNT 32bit write %lx\n", value);
+			PSXHW_LOG("COUNTER 0 COUNT 32bit write %x\n", value);
 #endif
 			psxRcntWcount(0, value & 0xffff); return;
 		case 0x1f801104:
 #ifdef PSXHW_LOG
-			PSXHW_LOG("COUNTER 0 MODE 32bit write %lx\n", value);
+			PSXHW_LOG("COUNTER 0 MODE 32bit write %x\n", value);
 #endif
 			psxRcntWmode(0, value); return;
 		case 0x1f801108:
 #ifdef PSXHW_LOG
-			PSXHW_LOG("COUNTER 0 TARGET 32bit write %lx\n", value);
+			PSXHW_LOG("COUNTER 0 TARGET 32bit write %x\n", value);
 #endif
 			psxRcntWtarget(0, value & 0xffff); return; //  HW_DMA_ICR&= SWAP32((~value)&0xff000000);
 
 		case 0x1f801110:
 #ifdef PSXHW_LOG
-			PSXHW_LOG("COUNTER 1 COUNT 32bit write %lx\n", value);
+			PSXHW_LOG("COUNTER 1 COUNT 32bit write %x\n", value);
 #endif
 			psxRcntWcount(1, value & 0xffff); return;
 		case 0x1f801114:
 #ifdef PSXHW_LOG
-			PSXHW_LOG("COUNTER 1 MODE 32bit write %lx\n", value);
+			PSXHW_LOG("COUNTER 1 MODE 32bit write %x\n", value);
 #endif
 			psxRcntWmode(1, value); return;
 		case 0x1f801118:
 #ifdef PSXHW_LOG
-			PSXHW_LOG("COUNTER 1 TARGET 32bit write %lx\n", value);
+			PSXHW_LOG("COUNTER 1 TARGET 32bit write %x\n", value);
 #endif
 			psxRcntWtarget(1, value & 0xffff); return;
 
 		case 0x1f801120:
 #ifdef PSXHW_LOG
-			PSXHW_LOG("COUNTER 2 COUNT 32bit write %lx\n", value);
+			PSXHW_LOG("COUNTER 2 COUNT 32bit write %x\n", value);
 #endif
 			psxRcntWcount(2, value & 0xffff); return;
 		case 0x1f801124:
 #ifdef PSXHW_LOG
-			PSXHW_LOG("COUNTER 2 MODE 32bit write %lx\n", value);
+			PSXHW_LOG("COUNTER 2 MODE 32bit write %x\n", value);
 #endif
 			psxRcntWmode(2, value); return;
 		case 0x1f801128:
 #ifdef PSXHW_LOG
-			PSXHW_LOG("COUNTER 2 TARGET 32bit write %lx\n", value);
+			PSXHW_LOG("COUNTER 2 TARGET 32bit write %x\n", value);
 #endif
 			psxRcntWtarget(2, value & 0xffff); return;
 
 		default:
 			psxHu32ref(add) = SWAPu32(value);
 #ifdef PSXHW_LOG
-			PSXHW_LOG("*Unknown 32bit write at address %lx value %lx\n", add, value);
+			PSXHW_LOG("*Unknown 32bit write at address %x value %x\n", add, value);
 #endif
 			return;
 	}
 	psxHu32ref(add) = SWAPu32(value);
 #ifdef PSXHW_LOG
-	PSXHW_LOG("*Known 32bit write at address %lx value %lx\n", add, value);
+	PSXHW_LOG("*Known 32bit write at address %x value %x\n", add, value);
 #endif
 }