diff options
| author | iCatButler <i.am.catbutler@gmail.com> | 2016-06-30 11:49:11 +0100 |
|---|---|---|
| committer | iCatButler <i.am.catbutler@gmail.com> | 2016-06-30 11:49:11 +0100 |
| commit | 485432c1988ab203ca85cd122f03118dcc2d9f8d (patch) | |
| tree | 4d68b43dbe68cd9c733fd8a2800608951e976ef6 /libpcsxcore | |
| parent | 6b78a14b0e466ff870aa042185c67539a8c51324 (diff) | |
| download | pcsxr-485432c1988ab203ca85cd122f03118dcc2d9f8d.tar.gz | |
Initialise GTE and CPU regsiters (invalidate)
Diffstat (limited to 'libpcsxcore')
| -rw-r--r-- | libpcsxcore/pgxp_cpu.c | 6 | ||||
| -rw-r--r-- | libpcsxcore/pgxp_cpu.h | 2 | ||||
| -rw-r--r-- | libpcsxcore/pgxp_gte.c | 6 | ||||
| -rw-r--r-- | libpcsxcore/pgxp_gte.h | 2 | ||||
| -rw-r--r-- | libpcsxcore/pgxp_mem.c | 11 |
5 files changed, 25 insertions, 2 deletions
diff --git a/libpcsxcore/pgxp_cpu.c b/libpcsxcore/pgxp_cpu.c index 17853afc..f2fff96e 100644 --- a/libpcsxcore/pgxp_cpu.c +++ b/libpcsxcore/pgxp_cpu.c @@ -20,6 +20,12 @@ PGXP_value* CP0_reg = CP0_reg_mem; #define rs(_instr) ((_instr >> 21) & 0x1F) // The rs part of the instruction register #define imm(_instr) (_instr & 0xFFFF) // The immediate part of the instruction register +void PGXP_InitCPU() +{ + memset(CPU_reg_mem, 0, sizeof(CPU_reg_mem)); + memset(CP0_reg_mem, 0, sizeof(CP0_reg_mem)); +} + // invalidate register (invalid 8 bit read) void InvalidLoad(u32 addr, u32 code, u32 value) { diff --git a/libpcsxcore/pgxp_cpu.h b/libpcsxcore/pgxp_cpu.h index 00a4cd60..a518c312 100644 --- a/libpcsxcore/pgxp_cpu.h +++ b/libpcsxcore/pgxp_cpu.h @@ -39,6 +39,8 @@ extern PGXP_value* CP0_reg; #define CPU_Lo CPU_reg[34] +void PGXP_InitCPU(); + // -- CPU functions // Load 32-bit word diff --git a/libpcsxcore/pgxp_gte.c b/libpcsxcore/pgxp_gte.c index de5f7a37..2ab36d12 100644 --- a/libpcsxcore/pgxp_gte.c +++ b/libpcsxcore/pgxp_gte.c @@ -44,7 +44,11 @@ PGXP_value GTE_ctrl_reg_mem[32]; PGXP_value* GTE_data_reg = GTE_data_reg_mem;
PGXP_value* GTE_ctrl_reg = GTE_ctrl_reg_mem;
-
+void PGXP_InitGTE()
+{
+ memset(GTE_data_reg_mem, 0, sizeof(GTE_data_reg_mem));
+ memset(GTE_ctrl_reg_mem, 0, sizeof(GTE_ctrl_reg_mem));
+}
// Instruction register decoding
#define op(_instr) (_instr >> 26) // The op part of the instruction register
diff --git a/libpcsxcore/pgxp_gte.h b/libpcsxcore/pgxp_gte.h index 4b628026..5c068eeb 100644 --- a/libpcsxcore/pgxp_gte.h +++ b/libpcsxcore/pgxp_gte.h @@ -36,6 +36,8 @@ typedef struct PGXP_value_Tag PGXP_value; extern PGXP_value* GTE_data_reg;
extern PGXP_value* GTE_ctrl_reg;
+void PGXP_InitGTE();
+
// -- GTE functions
// Transforms
void PGXP_pushSXYZ2f(float _x, float _y, float _z, unsigned int _v);
diff --git a/libpcsxcore/pgxp_mem.c b/libpcsxcore/pgxp_mem.c index 6aa3f1f2..c3fdc9eb 100644 --- a/libpcsxcore/pgxp_mem.c +++ b/libpcsxcore/pgxp_mem.c @@ -1,4 +1,6 @@ #include "pgxp_mem.h" +#include "pgxp_cpu.h" +#include "pgxp_gte.h" #include "pgxp_value.h" PGXP_value Mem[3 * 2048 * 1024 / 4]; // mirror 2MB in 32-bit words * 3 @@ -7,11 +9,18 @@ const u32 ScratchOffset = 2048 * 1024 / 4; const u32 RegisterOffset = 2 * 2048 * 1024 / 4; const u32 InvalidAddress = 3 * 2048 * 1024 / 4; -void PGXP_Init() +void PGXP_InitMem() { memset(Mem, 0, sizeof(Mem)); } +void PGXP_Init() +{ + PGXP_InitMem(); + PGXP_InitCPU(); + PGXP_InitGTE(); +} + char* PGXP_GetMem() { return (char*)(Mem); // Config.PGXP_GTE ? (char*)(Mem) : NULL; |
