Imporved CPU integration

- Change PGXP integration to use wrapper functions
- Use modified function lookup tables to call wrappers or default funnctions based on mode
- Implement wrappers for interpreter too, recompiler sometimes calls interpreter functions
- Add UI elements for selecting CPU modes
- Only call precision version of NCLIP in modes where there are not going to be stale vertices in GTE registers

- Added support for CP0 co-processor functions
- Improve support for CPU functions (still broken in many games)

- Improved debug output to show values for inputs before they're modified

GPU plugin
- Ignore stale vertices (occurs when CPU  mode no longer writes to memory)
- Add Cyan vertex colouring for stale vertices

18 files changed, 1207 insertions, 1398 deletions

diff --git a/libpcsxcore/gte.c b/libpcsxcore/gte.c
index b902ea48..95bf5d34 100755
--- a/libpcsxcore/gte.c
+++ b/libpcsxcore/gte.c
@@ -250,29 +250,27 @@ static void CTC2(u32 value, int reg) {
 	psxRegs.CP2C.p[reg].d = value;
 }
 
-void gteMFC2() {
+void gteMFC2()
+{
+	// CPU[Rt] = GTE_D[Rd]
 	if (!_Rt_) return;
 	psxRegs.GPR.r[_Rt_] = MFC2(_Rd_);
-	PGXP_MFC2(_Rt_, _Rd_, psxRegs.CP2D.p[_Rd_].d);
 }
 
-void gteCFC2() {
+void gteCFC2()
+{
+	// CPU[Rt] = GTE_C[Rd]
 	if (!_Rt_) return;
 	psxRegs.GPR.r[_Rt_] = psxRegs.CP2C.p[_Rd_].d;
-#ifdef GTE_LOG
-	GTE_LOG("GTE_CFC2 [%x]<-[%x] %x (%u %u)|", _Rt_, _Rd_, psxRegs.CP2C.p[_Rd_].d);
-#endif
 }
 
-void gteMTC2() {
-	PGXP_MTC2(_Rt_, _Rd_, psxRegs.GPR.p[_Rt_].d);
+void gteMTC2()
+{
 	MTC2(psxRegs.GPR.r[_Rt_], _Rd_);
 }
 
-void gteCTC2() {
-#ifdef GTE_LOG
-	GTE_LOG("GTE_CFC2 [%x]->[%x] %x (%u %u)|", _Rt_, _Rd_, psxRegs.GPR.r[_Rt_]);
-#endif
+void gteCTC2()
+{
 	CTC2(psxRegs.GPR.r[_Rt_], _Rd_);
 }
 
@@ -280,13 +278,11 @@ void gteCTC2() {
 
 void gteLWC2() {
 	u32 val = psxMemRead32(_oB_);
-	PGXP_LWC2(_oB_, _Rt_, val);
 	MTC2(val, _Rt_);
 }
 
 void gteSWC2() {
 	u32 val = MFC2(_Rt_);
-	PGXP_SWC2(_oB_, _Rt_, val);
 	psxMemWrite32(_oB_, val);
 }
 
diff --git a/libpcsxcore/ix86/iPGXP.h b/libpcsxcore/ix86/iPGXP.h
new file mode 100644
index 00000000..b4e47d3e
--- /dev/null
+++ b/libpcsxcore/ix86/iPGXP.h
@@ -0,0 +1,161 @@
+#ifndef _I_PGXP_H_
+#define _I_PGXP_H_
+
+
+/////////////////////////////////////////////
+// PGXP wrapper functions
+/////////////////////////////////////////////
+
+pgxpRecNULL() {}
+
+// Choose between debug and direct function
+#ifdef PGXP_CPU_DEBUG
+#define PGXP_REC_FUNC_OP(pu, op, nReg) PGXP_psxTraceOp##nReg
+#else
+#define PGXP_REC_FUNC_OP(pu, op, nReg) PGXP_##pu##_##op
+#endif
+
+#define PGXP_REC_FUNC_PASS(pu, op) \
+static void pgxpRec##op() { \
+	rec##op();\
+}
+
+#define PGXP_REC_FUNC(pu, op) \
+static void pgxpRec##op() { \
+	PUSH32I(psxRegs.code); \
+	CALLFunc((u32)PGXP_REC_FUNC_OP(pu, op, )); \
+	resp += 4; \
+	rec##op();\
+}
+
+#define PGXP_REC_FUNC_1(pu, op, reg1) \
+static void pgxpRec##op() { \
+	reg1;\
+	PUSH32I(psxRegs.code); \
+	CALLFunc((u32)PGXP_REC_FUNC_OP(pu, op, 1)); \
+	resp += 8; \
+	rec##op();\
+}
+
+#define PGXP_REC_FUNC_2_2(pu, op, test, nReg, reg1, reg2, reg3, reg4) \
+static void pgxpRec##op() { \
+	if(test) return;\
+	reg1;\
+	reg2;\
+	rec##op();\
+	reg3;\
+	reg4;\
+	PUSH32I(psxRegs.code); \
+	CALLFunc((u32)PGXP_REC_FUNC_OP(pu, op, nReg)); \
+	resp += (4 * nReg) + 4; \
+}
+
+#define PGXP_REC_FUNC_2(pu, op, reg1, reg2) \
+static void pgxpRec##op() { \
+	reg1;\
+	reg2;\
+	PUSH32I(psxRegs.code); \
+	CALLFunc((u32)PGXP_REC_FUNC_OP(pu, op, 2)); \
+	resp += 12; \
+	rec##op();\
+}
+
+#define PGXP_REC_FUNC_ADDR_1(pu, op, reg1) \
+static void pgxpRec##op()	\
+{	\
+	if (IsConst(_Rs_))	\
+	{	\
+		MOV32ItoR(EBX, iRegs[_Rs_].k + _Imm_);	\
+	}	\
+	else\
+	{\
+		MOV32MtoR(EBX, (u32)&psxRegs.GPR.r[_Rs_]);\
+		if (_Imm_)\
+		{\
+			ADD32ItoR(EBX, _Imm_);\
+		}\
+	}\
+	rec##op();\
+	PUSH32R(EBX);\
+	reg1;\
+	PUSH32I(psxRegs.code);	\
+	CALLFunc((u32)PGXP_REC_FUNC_OP(pu, op, 2)); \
+	resp += 12; \
+}
+
+// Rt = Rs op imm 
+PGXP_REC_FUNC_2_2(CPU, ADDI, !_Rt_, 2, iPushReg(_Rs_), , iPushReg(_Rt_), )
+PGXP_REC_FUNC_2_2(CPU, ADDIU, !_Rt_, 2, iPushReg(_Rs_), , iPushReg(_Rt_), )
+PGXP_REC_FUNC_2_2(CPU, ANDI, !_Rt_, 2, iPushReg(_Rs_), , iPushReg(_Rt_), )
+PGXP_REC_FUNC_2_2(CPU, ORI, !_Rt_, 2, iPushReg(_Rs_), , iPushReg(_Rt_), )
+PGXP_REC_FUNC_2_2(CPU, XORI, !_Rt_, 2, iPushReg(_Rs_), , iPushReg(_Rt_), )
+PGXP_REC_FUNC_2_2(CPU, SLTI, !_Rt_, 2, iPushReg(_Rs_), , iPushReg(_Rt_), )
+PGXP_REC_FUNC_2_2(CPU, SLTIU, !_Rt_, 2, iPushReg(_Rs_), , iPushReg(_Rt_), )
+
+// Rt = imm
+PGXP_REC_FUNC_2_2(CPU, LUI, !_Rt_, 1, , , iPushReg(_Rt_), )
+
+// Rd = Rs op Rt 
+PGXP_REC_FUNC_2_2(CPU, ADD, !_Rd_, 3, iPushReg(_Rt_), iPushReg(_Rs_), iPushReg(_Rd_), )
+PGXP_REC_FUNC_2_2(CPU, ADDU, !_Rd_, 3, iPushReg(_Rt_), iPushReg(_Rs_), iPushReg(_Rd_), )
+PGXP_REC_FUNC_2_2(CPU, SUB, !_Rd_, 3, iPushReg(_Rt_), iPushReg(_Rs_), iPushReg(_Rd_), )
+PGXP_REC_FUNC_2_2(CPU, SUBU, !_Rd_, 3, iPushReg(_Rt_), iPushReg(_Rs_), iPushReg(_Rd_), )
+PGXP_REC_FUNC_2_2(CPU, AND, !_Rd_, 3, iPushReg(_Rt_), iPushReg(_Rs_), iPushReg(_Rd_), )
+PGXP_REC_FUNC_2_2(CPU, OR, !_Rd_, 3, iPushReg(_Rt_), iPushReg(_Rs_), iPushReg(_Rd_), )
+PGXP_REC_FUNC_2_2(CPU, XOR, !_Rd_, 3, iPushReg(_Rt_), iPushReg(_Rs_), iPushReg(_Rd_), )
+PGXP_REC_FUNC_2_2(CPU, NOR, !_Rd_, 3, iPushReg(_Rt_), iPushReg(_Rs_), iPushReg(_Rd_), )
+PGXP_REC_FUNC_2_2(CPU, SLT, !_Rd_, 3, iPushReg(_Rt_), iPushReg(_Rs_), iPushReg(_Rd_), )
+PGXP_REC_FUNC_2_2(CPU, SLTU, !_Rd_, 3, iPushReg(_Rt_), iPushReg(_Rs_), iPushReg(_Rd_), )
+
+// Hi/Lo = Rs op Rt
+PGXP_REC_FUNC_2_2(CPU, MULT, 0, 4, iPushReg(_Rt_), iPushReg(_Rs_), PUSH32M((u32)&psxRegs.GPR.n.lo), PUSH32M((u32)&psxRegs.GPR.n.hi))
+PGXP_REC_FUNC_2_2(CPU, MULTU, 0, 4, iPushReg(_Rt_), iPushReg(_Rs_), PUSH32M((u32)&psxRegs.GPR.n.lo), PUSH32M((u32)&psxRegs.GPR.n.hi))
+PGXP_REC_FUNC_2_2(CPU, DIV, 0, 4, iPushReg(_Rt_), iPushReg(_Rs_), PUSH32M((u32)&psxRegs.GPR.n.lo), PUSH32M((u32)&psxRegs.GPR.n.hi))
+PGXP_REC_FUNC_2_2(CPU, DIVU, 0, 4, iPushReg(_Rt_), iPushReg(_Rs_), PUSH32M((u32)&psxRegs.GPR.n.lo), PUSH32M((u32)&psxRegs.GPR.n.hi))
+
+PGXP_REC_FUNC_2(CPU, SB, iPushOfB(), iPushReg(_Rt_))
+PGXP_REC_FUNC_2(CPU, SH, iPushOfB(), iPushReg(_Rt_))
+PGXP_REC_FUNC_2(CPU, SW, iPushOfB(), iPushReg(_Rt_))
+PGXP_REC_FUNC_2(CPU, SWL, iPushOfB(), iPushReg(_Rt_))
+PGXP_REC_FUNC_2(CPU, SWR, iPushOfB(), iPushReg(_Rt_))
+
+PGXP_REC_FUNC_ADDR_1(CPU, LWL, iPushReg(_Rt_))
+PGXP_REC_FUNC_ADDR_1(CPU, LW, iPushReg(_Rt_))
+PGXP_REC_FUNC_ADDR_1(CPU, LWR, iPushReg(_Rt_))
+PGXP_REC_FUNC_ADDR_1(CPU, LH, iPushReg(_Rt_))
+PGXP_REC_FUNC_ADDR_1(CPU, LHU, iPushReg(_Rt_))
+PGXP_REC_FUNC_ADDR_1(CPU, LB, iPushReg(_Rt_))
+PGXP_REC_FUNC_ADDR_1(CPU, LBU, iPushReg(_Rt_))
+
+//Rd = Rt op Sa
+PGXP_REC_FUNC_2_2(CPU, SLL, !_Rd_, 2, iPushReg(_Rt_), , iPushReg(_Rd_), )
+PGXP_REC_FUNC_2_2(CPU, SRL, !_Rd_, 2, iPushReg(_Rt_), , iPushReg(_Rd_), )
+PGXP_REC_FUNC_2_2(CPU, SRA, !_Rd_, 2, iPushReg(_Rt_), , iPushReg(_Rd_), )
+
+// Rd = Rt op Rs
+PGXP_REC_FUNC_2_2(CPU, SLLV, !_Rd_, 3, iPushReg(_Rs_), iPushReg(_Rt_), iPushReg(_Rd_), )
+PGXP_REC_FUNC_2_2(CPU, SRLV, !_Rd_, 3, iPushReg(_Rs_), iPushReg(_Rt_), iPushReg(_Rd_), )
+PGXP_REC_FUNC_2_2(CPU, SRAV, !_Rd_, 3, iPushReg(_Rs_), iPushReg(_Rt_), iPushReg(_Rd_), )
+
+PGXP_REC_FUNC_2_2(CPU, MFHI, !_Rd_, 2, PUSH32M((u32)&psxRegs.GPR.n.hi), , iPushReg(_Rd_), )
+PGXP_REC_FUNC_2_2(CPU, MTHI, 0, 2, iPushReg(_Rd_), , PUSH32M((u32)&psxRegs.GPR.n.hi), )
+PGXP_REC_FUNC_2_2(CPU, MFLO, !_Rd_, 2, PUSH32M((u32)&psxRegs.GPR.n.lo), , iPushReg(_Rd_), )
+PGXP_REC_FUNC_2_2(CPU, MTLO, 0, 2, iPushReg(_Rd_), , PUSH32M((u32)&psxRegs.GPR.n.lo), )
+
+// COP2 (GTE)
+PGXP_REC_FUNC_2_2(GTE, MFC2, !_Rt_, 1, , , , PUSH32M((u32)&psxRegs.CP2D.r[_Rd_]))
+PGXP_REC_FUNC_2_2(GTE, CFC2, !_Rt_, 1, , , , PUSH32M((u32)&psxRegs.CP2C.r[_Rd_]))
+PGXP_REC_FUNC_2_2(GTE, MTC2, 0, 1, , , , iPushReg(_Rt_))
+PGXP_REC_FUNC_2_2(GTE, CTC2, 0, 1, , , , iPushReg(_Rt_))
+
+PGXP_REC_FUNC_ADDR_1(GTE, LWC2, PUSH32M((u32)&psxRegs.CP2D.r[_Rt_]))
+PGXP_REC_FUNC_ADDR_1(GTE, SWC2, PUSH32M((u32)&psxRegs.CP2D.r[_Rt_]))
+
+// COP0
+PGXP_REC_FUNC_2_2(CP0, MFC0, !_Rd_, 1, , , , PUSH32M((u32)&psxRegs.CP0.r[_Rd_]))
+PGXP_REC_FUNC_2_2(CP0, CFC0, !_Rd_, 1, , , , PUSH32M((u32)&psxRegs.CP0.r[_Rd_]))
+PGXP_REC_FUNC_2_2(CP0, MTC0, !_Rt_, 1, , , , iPushReg(_Rt_))
+PGXP_REC_FUNC_2_2(CP0, CTC0, !_Rt_, 1, , , , iPushReg(_Rt_))
+PGXP_REC_FUNC(CP0, RFE)
+
+#endif//_I_PGXP_H_
diff --git a/libpcsxcore/ix86/iR3000A.c b/libpcsxcore/ix86/iR3000A.c
index 726dbc3c..e2fd7aee 100755
--- a/libpcsxcore/ix86/iR3000A.c
+++ b/libpcsxcore/ix86/iR3000A.c
@@ -26,6 +26,7 @@
 #include "ix86.h"
 #include <sys/mman.h>
 #include "pgxp_cpu.h"
+#include "pgxp_gte.h"
 #include "pgxp_debug.h"
 
 #ifndef MAP_ANONYMOUS
@@ -79,6 +80,60 @@ static void (*recCP0[32])();
 static void (*recCP2[64])();
 static void (*recCP2BSC[32])();
 
+/// PGXP function tables
+static void (*pgxpRecBSC[64])();
+static void (*pgxpRecSPC[64])();
+static void (*pgxpRecCP0[32])();
+static void (*pgxpRecCP2BSC[32])();
+
+static void(*pgxpRecBSCMem[64])();
+///
+
+static void(**pRecBSC)() = recBSC;
+static void(**pRecSPC)() = recSPC;
+static void(**pRecREG)() = recREG;
+static void(**pRecCP0)() = recCP0;
+static void(**pRecCP2)() = recCP2;
+static void(**pRecCP2BSC)() = recCP2BSC;
+
+
+static void recReset();
+void recSetPGXPMode(u32 pgxpMode)
+{
+	switch(pgxpMode)
+	{
+	case 0: //PGXP_MODE_DISABLED:
+		pRecBSC		= recBSC;
+		pRecSPC		= recSPC;
+		pRecREG		= recREG;
+		pRecCP0		= recCP0;
+		pRecCP2		= recCP2;
+		pRecCP2BSC	= recCP2BSC;
+		break;
+	case 1: //PGXP_MODE_MEM:
+		pRecBSC		= pgxpRecBSCMem;
+		pRecSPC		= recSPC;
+		pRecREG		= recREG;
+		pRecCP0		= pgxpRecCP0;
+		pRecCP2		= recCP2;
+		pRecCP2BSC	= pgxpRecCP2BSC;
+		break;
+	case 2: //PGXP_MODE_FULL:
+		pRecBSC		= pgxpRecBSC;
+		pRecSPC		= pgxpRecSPC;
+		pRecREG		= recREG;
+		pRecCP0		= pgxpRecCP0;
+		pRecCP2		= recCP2;
+		pRecCP2BSC	= pgxpRecCP2BSC;
+		break;
+	}
+
+	// set interpreter mode too
+	intSetPGXPMode(pgxpMode);
+	// reset to ensure new func tables are used
+	recReset();
+}
+
 #define DYNAREC_BLOCK 50
 
 static void MapConst(int reg, u32 _const) {
@@ -101,6 +156,16 @@ static void iFlushRegs() {
 	}
 }
 
+static void iPushReg(int reg) 
+{
+	if (IsConst(reg)) {
+		PUSH32I(iRegs[reg].k);
+	}
+	else {
+		PUSH32M((u32)&psxRegs.GPR.r[reg]);
+	}
+}
+
 static void iStoreCycle() {
 	count = ((pc - pcold) / 4) * BIAS;
 	ADD32ItoM((u32)&psxRegs.cycle, count);
@@ -181,7 +246,7 @@ static void SetBranch() {
 			break;
 
 		default:
-			recBSC[psxRegs.code>>26]();
+			pRecBSC[psxRegs.code>>26]();
 			break;
 	}
 
@@ -217,7 +282,7 @@ static void iJump(u32 branchPC) {
 		return;
 	}
 
-	recBSC[psxRegs.code>>26]();
+	pRecBSC[psxRegs.code>>26]();
 
 	iFlushRegs();
 	iStoreCycle();
@@ -273,7 +338,7 @@ static void iBranch(u32 branchPC, int savectx) {
 	}
 
 	pc+= 4;
-	recBSC[psxRegs.code>>26]();
+	pRecBSC[psxRegs.code>>26]();
 
 	iFlushRegs();
 	iStoreCycle();
@@ -507,15 +572,15 @@ static void recNULL() {
 
 //REC_SYS(SPECIAL);
 static void recSPECIAL() {
-	recSPC[_Funct_]();
+	pRecSPC[_Funct_]();
 }
 
 static void recREGIMM() {
-	recREG[_Rt_]();
+	pRecREG[_Rt_]();
 }
 
 static void recCOP0() {
-	recCP0[_Rs_]();
+	pRecCP0[_Rs_]();
 }
 
 //REC_SYS(COP2);
@@ -524,13 +589,13 @@ static void recCOP2() {
 	AND32ItoR(EAX, 0x40000000);
 	j8Ptr[31] = JZ8(0);
 
-	recCP2[_Funct_]();
+	pRecCP2[_Funct_]();
 
 	x86SetJ8(j8Ptr[31]);
 }
 
 static void recBASIC() {
-	recCP2BSC[_Rs_]();
+	pRecCP2BSC[_Rs_]();
 }
 
 //end of Tables opcodes...
@@ -554,12 +619,6 @@ static void recADDIU()  {
 
 //	iFlushRegs();
 
-	#if PGXP_TRACE >= 1 // iCB: Tracing
-	if (IsConst(_Rs_))
-		PUSH32I(iRegs[_Rs_].k);
-	else
-		PUSH32M((u32)&psxRegs.GPR.r[_Rs_]);
-	#endif // iCB: /Tracing
 
 
 
@@ -593,20 +652,6 @@ static void recADDIU()  {
 		}
 	}
 
-	#if PGXP_TRACE >= 1 // iCB: Tracing
-	if (IsConst(_Rt_)) 
-			PUSH32I(iRegs[_Rt_].k);
-	else 
-			PUSH32M((u32)&psxRegs.GPR.r[_Rt_]); 
-
-	PUSH32I(psxRegs.code);
-#ifdef PGXP_CPU_DEBUG
-	CALLFunc((u32)PGXP_psxTraceOp2);
-#else
-	CALLFunc((u32)PGXP_CPU_ADDI);
-#endif
-	resp += 12;
-	#endif // iCB: /Tracing
 }
 
 static void recADDI()  {
@@ -615,12 +660,6 @@ static void recADDI()  {
 
 	//	iFlushRegs();
 
-#if PGXP_TRACE >= 1 // iCB: Tracing
-	if (IsConst(_Rs_))
-		PUSH32I(iRegs[_Rs_].k);
-	else
-		PUSH32M((u32)&psxRegs.GPR.r[_Rs_]);
-#endif // iCB: /Tracing
 
 
 
@@ -661,20 +700,6 @@ static void recADDI()  {
 		}
 	}
 
-#if PGXP_TRACE >= 1 // iCB: Tracing
-	if (IsConst(_Rt_))
-		PUSH32I(iRegs[_Rt_].k);
-	else
-		PUSH32M((u32)&psxRegs.GPR.r[_Rt_]);
-
-	PUSH32I(psxRegs.code);
-#ifdef PGXP_CPU_DEBUG
-	CALLFunc((u32)PGXP_psxTraceOp2);
-#else
-	CALLFunc((u32)PGXP_CPU_ADDIU);
-#endif
-	resp += 12;
-#endif // iCB: /Tracing
 }
 
 static void recSLTI() {
@@ -683,12 +708,6 @@ static void recSLTI() {
 
 //	iFlushRegs();
 
-	#if PGXP_TRACE >= 1 // iCB: Tracing
-	if (IsConst(_Rs_))
-		PUSH32I(iRegs[_Rs_].k);
-	else
-		PUSH32M((u32)&psxRegs.GPR.r[_Rs_]);
-	#endif // iCB: /Tracing
 
 	if (IsConst(_Rs_)) {
 		MapConst(_Rt_, (s32)iRegs[_Rs_].k < _Imm_);
@@ -702,20 +721,7 @@ static void recSLTI() {
 		MOV32RtoM((u32)&psxRegs.GPR.r[_Rt_], EAX);
 	}
 
-	#if PGXP_TRACE >= 1 // iCB: Tracing
-	if (IsConst(_Rt_))
-		PUSH32I(iRegs[_Rt_].k);
-	else
-		PUSH32M((u32)&psxRegs.GPR.r[_Rt_]);
-
-	PUSH32I(psxRegs.code);
-#ifdef PGXP_CPU_DEBUG
-	CALLFunc((u32)PGXP_psxTraceOp2);
-#else
-	CALLFunc((u32)PGXP_CPU_SLTI);
-#endif
-	resp += 12;
-	#endif // iCB: /Tracing
+
 }
 
 static void recSLTIU() {
@@ -724,12 +730,6 @@ static void recSLTIU() {
 
 //	iFlushRegs();
 
-	#if PGXP_TRACE >= 1 // iCB: Tracing
-	if (IsConst(_Rs_))
-		PUSH32I(iRegs[_Rs_].k);
-	else
-		PUSH32M((u32)&psxRegs.GPR.r[_Rs_]);
-	#endif // iCB: /Tracing
 
 	if (IsConst(_Rs_)) {
 		MapConst(_Rt_, iRegs[_Rs_].k < _ImmU_);
@@ -743,20 +743,7 @@ static void recSLTIU() {
 		MOV32RtoM((u32)&psxRegs.GPR.r[_Rt_], EAX);
 	}
 
-	#if PGXP_TRACE >= 1 // iCB: Tracing
-	if (IsConst(_Rt_))
-		PUSH32I(iRegs[_Rt_].k);
-	else
-		PUSH32M((u32)&psxRegs.GPR.r[_Rt_]);
-
-	PUSH32I(psxRegs.code);
-#ifdef PGXP_CPU_DEBUG
-	CALLFunc((u32)PGXP_psxTraceOp2);
-#else
-	CALLFunc((u32)PGXP_CPU_SLTIU);
-#endif
-	resp += 12;
-	#endif // iCB: /Tracing
+
 }
 
 static void recANDI() {
@@ -765,12 +752,6 @@ static void recANDI() {
 
 //	iFlushRegs();
 
-	#if PGXP_TRACE >= 1 // iCB: Tracing
-	if (IsConst(_Rs_))
-		PUSH32I(iRegs[_Rs_].k);
-	else
-		PUSH32M((u32)&psxRegs.GPR.r[_Rs_]);
-	#endif // iCB: /Tracing
 
 	if (_Rs_ == _Rt_) {
 		if (IsConst(_Rt_)) {
@@ -790,32 +771,13 @@ static void recANDI() {
 		}
 	}
 
-	#if PGXP_TRACE >= 1 // iCB: Tracing
-	if (IsConst(_Rt_))
-		PUSH32I(iRegs[_Rt_].k);
-	else
-		PUSH32M((u32)&psxRegs.GPR.r[_Rt_]);
-
-	PUSH32I(psxRegs.code);
-#ifdef PGXP_CPU_DEBUG
-	CALLFunc((u32)PGXP_psxTraceOp2);
-#else
-	CALLFunc((u32)PGXP_CPU_ANDI);
-#endif
-	resp += 12;
-	#endif // iCB: /Tracing
+
 }
 
 static void recORI() {
 // Rt = Rs Or Im
 	if (!_Rt_) return;
 
-	#if PGXP_TRACE >= 1 // iCB: Tracing
-	if (IsConst(_Rs_))
-		PUSH32I(iRegs[_Rs_].k);
-	else
-		PUSH32M((u32)&psxRegs.GPR.r[_Rs_]);
-	#endif // iCB: /Tracing
 
 	if (_Rs_ == _Rt_) {
 		if (IsConst(_Rt_)) {
@@ -835,32 +797,13 @@ static void recORI() {
 		}
 	}
 
-	#if PGXP_TRACE >= 1 // iCB: Tracing
-	if (IsConst(_Rt_))
-		PUSH32I(iRegs[_Rt_].k);
-	else
-		PUSH32M((u32)&psxRegs.GPR.r[_Rt_]);
-
-	PUSH32I(psxRegs.code);
-#ifdef PGXP_CPU_DEBUG
-	CALLFunc((u32)PGXP_psxTraceOp2);
-#else
-	CALLFunc((u32)PGXP_CPU_ORI);
-#endif
-	resp += 12;
-	#endif // iCB: /Tracing
+
 }
 
 static void recXORI() {
 // Rt = Rs Xor Im
 	if (!_Rt_) return;
 
-	#if PGXP_TRACE >= 1 // iCB: Tracing
-	if (IsConst(_Rs_))
-		PUSH32I(iRegs[_Rs_].k);
-	else
-		PUSH32M((u32)&psxRegs.GPR.r[_Rs_]);
-	#endif // iCB: /Tracing
 
 	if (_Rs_ == _Rt_) {
 		if (IsConst(_Rt_)) {
@@ -880,20 +823,7 @@ static void recXORI() {
 		}
 	}
 
-	#if PGXP_TRACE >= 1 // iCB: Tracing
-	if (IsConst(_Rt_))
-		PUSH32I(iRegs[_Rt_].k);
-	else
-		PUSH32M((u32)&psxRegs.GPR.r[_Rt_]);
-
-	PUSH32I(psxRegs.code);
-#ifdef PGXP_CPU_DEBUG
-	CALLFunc((u32)PGXP_psxTraceOp2);
-#else
-	CALLFunc((u32)PGXP_CPU_XORI);
-#endif
-	resp += 12;
-	#endif // iCB: /Tracing
+
 }
 //#endif
 //end of * Arithmetic with immediate operand  
@@ -910,20 +840,7 @@ static void recLUI()  {
 
 	MapConst(_Rt_, psxRegs.code << 16);
 
-	#if PGXP_TRACE >= 2 // iCB: Tracing
-	if (IsConst(_Rt_))
-		PUSH32I(iRegs[_Rt_].k);
-	else
-		PUSH32M((u32)&psxRegs.GPR.r[_Rt_]);
-
-	PUSH32I(psxRegs.code);
-#ifdef PGXP_CPU_DEBUG
-	CALLFunc((u32)PGXP_psxTraceOp1);
-#else
-	CALLFunc((u32)PGXP_CPU_LUI);
-#endif
-	resp += 8;
-	#endif // iCB: /Tracing
+
 }
 //#endif
 //End of Load Higher .....
@@ -952,17 +869,7 @@ static void recADDU() {
 
 //	iFlushRegs();
 
-	#if PGXP_TRACE >= 3 // iCB: Tracing
-	if (IsConst(_Rt_))
-		PUSH32I(iRegs[_Rt_].k);
-	else
-		PUSH32M((u32)&psxRegs.GPR.r[_Rt_]);
 
-	if (IsConst(_Rs_))
-		PUSH32I(iRegs[_Rs_].k);
-	else
-		PUSH32M((u32)&psxRegs.GPR.r[_Rs_]);
-	#endif // iCB: /Tracing
 
 
 	if (IsConst(_Rs_) && IsConst(_Rt_)) {
@@ -1027,20 +934,7 @@ static void recADDU() {
 		}
 	}
 
-	#if PGXP_TRACE >= 3 // iCB: Tracing
-	if (IsConst(_Rd_))
-		PUSH32I(iRegs[_Rd_].k);
-	else
-		PUSH32M((u32)&psxRegs.GPR.r[_Rd_]);
-
-	PUSH32I(psxRegs.code);
-#ifdef PGXP_CPU_DEBUG
-	CALLFunc((u32)PGXP_psxTraceOp3);
-#else
-	CALLFunc((u32)PGXP_CPU_ADDU);
-#endif
-	resp += 16;
-	#endif // iCB: /Tracing
+
 }
 
 static void recADD() {
@@ -1054,17 +948,7 @@ static void recSUBU() {
 
 //	iFlushRegs();
 
-	#if PGXP_TRACE >= 3 // iCB: Tracing
-	if (IsConst(_Rt_))
-		PUSH32I(iRegs[_Rt_].k);
-	else
-		PUSH32M((u32)&psxRegs.GPR.r[_Rt_]);
 
-	if (IsConst(_Rs_))
-		PUSH32I(iRegs[_Rs_].k);
-	else
-		PUSH32M((u32)&psxRegs.GPR.r[_Rs_]);
-	#endif // iCB: /Tracing
 
 	if (IsConst(_Rs_) && IsConst(_Rt_)) {
 		MapConst(_Rd_, iRegs[_Rs_].k - iRegs[_Rt_].k);
@@ -1088,20 +972,7 @@ static void recSUBU() {
 		MOV32RtoM((u32)&psxRegs.GPR.r[_Rd_], EAX);
 	}
 
-	#if PGXP_TRACE >= 3 // iCB: Tracing
-	if (IsConst(_Rd_))
-		PUSH32I(iRegs[_Rd_].k);
-	else
-		PUSH32M((u32)&psxRegs.GPR.r[_Rd_]);
-
-	PUSH32I(psxRegs.code);
-#ifdef PGXP_CPU_DEBUG
-	CALLFunc((u32)PGXP_psxTraceOp3);
-#else
-	CALLFunc((u32)PGXP_CPU_SUBU);
-#endif
-	resp += 16;
-	#endif // iCB: /Tracing
+
 }   
 
 static void recSUB() {
@@ -1115,17 +986,6 @@ static void recAND() {
 
 //	iFlushRegs();
 
-	#if PGXP_TRACE >= 3 // iCB: Tracing
-	if (IsConst(_Rt_))
-		PUSH32I(iRegs[_Rt_].k);
-	else
-		PUSH32M((u32)&psxRegs.GPR.r[_Rt_]);
-
-	if (IsConst(_Rs_))
-		PUSH32I(iRegs[_Rs_].k);
-	else
-		PUSH32M((u32)&psxRegs.GPR.r[_Rs_]);
-	#endif // iCB: /Tracing
 
 	if (IsConst(_Rs_) && IsConst(_Rt_)) {
 		MapConst(_Rd_, iRegs[_Rs_].k & iRegs[_Rt_].k);
@@ -1165,20 +1025,7 @@ static void recAND() {
 		}
 	}
 
-	#if PGXP_TRACE >= 3 // iCB: Tracing
-	if (IsConst(_Rd_))
-		PUSH32I(iRegs[_Rd_].k);
-	else
-		PUSH32M((u32)&psxRegs.GPR.r[_Rd_]);
-
-	PUSH32I(psxRegs.code);
-#ifdef PGXP_CPU_DEBUG
-	CALLFunc((u32)PGXP_psxTraceOp3);
-#else
-	CALLFunc((u32)PGXP_CPU_AND);
-#endif
-	resp += 16;
-	#endif // iCB: /Tracing
+
 }   
 
 static void recOR() {
@@ -1187,17 +1034,7 @@ static void recOR() {
 
 //	iFlushRegs();
 
-	#if PGXP_TRACE >= 3 // iCB: Tracing
-	if (IsConst(_Rt_))
-		PUSH32I(iRegs[_Rt_].k);
-	else
-		PUSH32M((u32)&psxRegs.GPR.r[_Rt_]);
 
-	if (IsConst(_Rs_))
-		PUSH32I(iRegs[_Rs_].k);
-	else
-		PUSH32M((u32)&psxRegs.GPR.r[_Rs_]);
-	#endif // iCB: /Tracing
 
 	if (IsConst(_Rs_) && IsConst(_Rt_)) {
 		MapConst(_Rd_, iRegs[_Rs_].k | iRegs[_Rt_].k);
@@ -1221,20 +1058,7 @@ static void recOR() {
 		MOV32RtoM((u32)&psxRegs.GPR.r[_Rd_], EAX);
 	}
 
-	#if PGXP_TRACE >= 3 // iCB: Tracing
-	if (IsConst(_Rd_))
-		PUSH32I(iRegs[_Rd_].k);
-	else
-		PUSH32M((u32)&psxRegs.GPR.r[_Rd_]);
-
-	PUSH32I(psxRegs.code);
-#ifdef PGXP_CPU_DEBUG
-	CALLFunc((u32)PGXP_psxTraceOp3);
-#else
-	CALLFunc((u32)PGXP_CPU_OR);
-#endif
-	resp += 16;
-	#endif // iCB: /Tracing
+
 }   
 
 static void recXOR() {
@@ -1243,17 +1067,7 @@ static void recXOR() {
 
 //	iFlushRegs();
 
-	#if PGXP_TRACE >= 3 // iCB: Tracing
-	if (IsConst(_Rt_))
-		PUSH32I(iRegs[_Rt_].k);
-	else
-		PUSH32M((u32)&psxRegs.GPR.r[_Rt_]);
 
-	if (IsConst(_Rs_))
-		PUSH32I(iRegs[_Rs_].k);
-	else
-		PUSH32M((u32)&psxRegs.GPR.r[_Rs_]);
-	#endif // iCB: /Tracing
 
 	if (IsConst(_Rs_) && IsConst(_Rt_)) {
 		MapConst(_Rd_, iRegs[_Rs_].k ^ iRegs[_Rt_].k);
@@ -1277,20 +1091,7 @@ static void recXOR() {
 		MOV32RtoM((u32)&psxRegs.GPR.r[_Rd_], EAX);
 	}
 
-	#if PGXP_TRACE >= 3 // iCB: Tracing
-	if (IsConst(_Rd_))
-		PUSH32I(iRegs[_Rd_].k);
-	else
-		PUSH32M((u32)&psxRegs.GPR.r[_Rd_]);
-
-	PUSH32I(psxRegs.code);
-#ifdef PGXP_CPU_DEBUG
-	CALLFunc((u32)PGXP_psxTraceOp3);
-#else
-	CALLFunc((u32)PGXP_CPU_XOR);
-#endif
-	resp += 16;
-	#endif // iCB: /Tracing
+
 }
 
 static void recNOR() {
@@ -1299,17 +1100,6 @@ static void recNOR() {
 
 //	iFlushRegs();
 
-	#if PGXP_TRACE >= 3 // iCB: Tracing
-	if (IsConst(_Rt_))
-		PUSH32I(iRegs[_Rt_].k);
-	else
-		PUSH32M((u32)&psxRegs.GPR.r[_Rt_]);
-
-	if (IsConst(_Rs_))
-		PUSH32I(iRegs[_Rs_].k);
-	else
-		PUSH32M((u32)&psxRegs.GPR.r[_Rs_]);
-	#endif // iCB: /Tracing
 
 	if (IsConst(_Rs_) && IsConst(_Rt_)) {
 		MapConst(_Rd_, ~(iRegs[_Rs_].k | iRegs[_Rt_].k));
@@ -1336,20 +1126,7 @@ static void recNOR() {
 		MOV32RtoM((u32)&psxRegs.GPR.r[_Rd_], EAX);
 	}
 
-	#if PGXP_TRACE >= 3 // iCB: Tracing
-	if (IsConst(_Rd_))
-		PUSH32I(iRegs[_Rd_].k);
-	else
-		PUSH32M((u32)&psxRegs.GPR.r[_Rd_]);
-
-	PUSH32I(psxRegs.code);
-#ifdef PGXP_CPU_DEBUG
-	CALLFunc((u32)PGXP_psxTraceOp3);
-#else
-	CALLFunc((u32)PGXP_CPU_NOR);
-#endif
-	resp += 16;
-	#endif // iCB: /Tracing
+
 }
 
 static void recSLT() {
@@ -1358,17 +1135,7 @@ static void recSLT() {
 
 //	iFlushRegs();
 
-	#if PGXP_TRACE >= 3 // iCB: Tracing
-	if (IsConst(_Rt_))
-		PUSH32I(iRegs[_Rt_].k);
-	else
-		PUSH32M((u32)&psxRegs.GPR.r[_Rt_]);
 
-	if (IsConst(_Rs_))
-		PUSH32I(iRegs[_Rs_].k);
-	else
-		PUSH32M((u32)&psxRegs.GPR.r[_Rs_]);
-	#endif // iCB: /Tracing
 
 	if (IsConst(_Rs_) && IsConst(_Rt_)) {
 		MapConst(_Rd_, (s32)iRegs[_Rs_].k < (s32)iRegs[_Rt_].k);
@@ -1398,20 +1165,7 @@ static void recSLT() {
 		MOV32RtoM((u32)&psxRegs.GPR.r[_Rd_], EAX);
 	}
 
-	#if PGXP_TRACE >= 3 // iCB: Tracing
-	if (IsConst(_Rd_))
-		PUSH32I(iRegs[_Rd_].k);
-	else
-		PUSH32M((u32)&psxRegs.GPR.r[_Rd_]);
-
-	PUSH32I(psxRegs.code);
-#ifdef PGXP_CPU_DEBUG
-	CALLFunc((u32)PGXP_psxTraceOp3);
-#else
-	CALLFunc((u32)PGXP_CPU_SLT);
-#endif
-	resp += 16;
-	#endif // iCB: /Tracing
+
 }  
 
 static void recSLTU() { 
@@ -1420,17 +1174,7 @@ static void recSLTU() {
 
 //	iFlushRegs();
 
-	#if PGXP_TRACE >= 3 // iCB: Tracing
-	if (IsConst(_Rt_))
-		PUSH32I(iRegs[_Rt_].k);
-	else
-		PUSH32M((u32)&psxRegs.GPR.r[_Rt_]);
 
-	if (IsConst(_Rs_))
-		PUSH32I(iRegs[_Rs_].k);
-	else
-		PUSH32M((u32)&psxRegs.GPR.r[_Rs_]);
-	#endif // iCB: /Tracing
 
 	if (IsConst(_Rs_) && IsConst(_Rt_)) {
 		MapConst(_Rd_, iRegs[_Rs_].k < iRegs[_Rt_].k);
@@ -1460,20 +1204,7 @@ static void recSLTU() {
 		MOV32RtoM((u32)&psxRegs.GPR.r[_Rd_], EAX);
 	}
 
-	#if PGXP_TRACE >= 3 // iCB: Tracing
-	if (IsConst(_Rd_))
-		PUSH32I(iRegs[_Rd_].k);
-	else
-		PUSH32M((u32)&psxRegs.GPR.r[_Rd_]);
-
-	PUSH32I(psxRegs.code);
-#ifdef PGXP_CPU_DEBUG
-	CALLFunc((u32)PGXP_psxTraceOp3);
-#else
-	CALLFunc((u32)PGXP_CPU_SLTU);
-#endif
-	resp += 16;
-	#endif // iCB: /Tracing
+
 }
 //#endif
 //End of * Register arithmetic
@@ -1493,16 +1224,6 @@ static void recMULT() {
 
 //	iFlushRegs();
 
-	#if PGXP_TRACE >= 4 // iCB: Tracing
-	if (IsConst(_Rt_))
-		PUSH32I(iRegs[_Rt_].k);
-	else
-		PUSH32M((u32)&psxRegs.GPR.r[_Rt_]);
-	if (IsConst(_Rs_))
-		PUSH32I(iRegs[_Rs_].k);
-	else
-		PUSH32M((u32)&psxRegs.GPR.r[_Rs_]);
-	#endif // iCB: /Tracing
 
 	if ((IsConst(_Rs_) && iRegs[_Rs_].k == 0) ||
 		(IsConst(_Rt_) && iRegs[_Rt_].k == 0)) {
@@ -1510,18 +1231,7 @@ static void recMULT() {
 		MOV32RtoM((u32)&psxRegs.GPR.n.lo, EAX);
 		MOV32RtoM((u32)&psxRegs.GPR.n.hi, EAX);
 
-		#if PGXP_TRACE >= 4 // iCB: Tracing
-		PUSH32M((u32)&psxRegs.GPR.n.lo);
-		PUSH32M((u32)&psxRegs.GPR.n.hi);
 
-		PUSH32I(psxRegs.code);
-#ifdef PGXP_CPU_DEBUG
-		CALLFunc((u32)PGXP_psxTraceOp4);
-#else
-		CALLFunc((u32)PGXP_CPU_MULT);
-#endif
-		resp += 20;
-		#endif // iCB: /Tracing
 		return;
 	}
 
@@ -1539,18 +1249,7 @@ static void recMULT() {
 	MOV32RtoM((u32)&psxRegs.GPR.n.lo, EAX);
 	MOV32RtoM((u32)&psxRegs.GPR.n.hi, EDX);
 
-	#if PGXP_TRACE >= 4 // iCB: Tracing
-	PUSH32M((u32)&psxRegs.GPR.n.lo);
-	PUSH32M((u32)&psxRegs.GPR.n.hi);
 
-	PUSH32I(psxRegs.code);
-#ifdef PGXP_CPU_DEBUG
-	CALLFunc((u32)PGXP_psxTraceOp4);
-#else
-	CALLFunc((u32)PGXP_CPU_MULT);
-#endif
-	resp += 20;
-	#endif // iCB: /Tracing
 }
 
 static void recMULTU() {
@@ -1558,16 +1257,6 @@ static void recMULTU() {
 
 //	iFlushRegs();
 
-	#if PGXP_TRACE >= 4 // iCB: Tracing
-	if (IsConst(_Rt_))
-		PUSH32I(iRegs[_Rt_].k);
-	else
-		PUSH32M((u32)&psxRegs.GPR.r[_Rt_]);
-	if (IsConst(_Rs_))
-		PUSH32I(iRegs[_Rs_].k);
-	else
-		PUSH32M((u32)&psxRegs.GPR.r[_Rs_]);
-	#endif // iCB: /Tracing
 
 
 	if ((IsConst(_Rs_) && iRegs[_Rs_].k == 0) ||
@@ -1576,18 +1265,7 @@ static void recMULTU() {
 		MOV32RtoM((u32)&psxRegs.GPR.n.lo, EAX);
 		MOV32RtoM((u32)&psxRegs.GPR.n.hi, EAX);
 
-		#if PGXP_TRACE >= 4 // iCB: Tracing
-		PUSH32M((u32)&psxRegs.GPR.n.lo);
-		PUSH32M((u32)&psxRegs.GPR.n.hi);
 
-		PUSH32I(psxRegs.code);
-#ifdef PGXP_CPU_DEBUG
-		CALLFunc((u32)PGXP_psxTraceOp4);
-#else
-		CALLFunc((u32)PGXP_CPU_MULTU);
-#endif
-		resp += 20;
-		#endif // iCB: /Tracing
 		return;
 	}
 
@@ -1605,18 +1283,7 @@ static void recMULTU() {
 	MOV32RtoM((u32)&psxRegs.GPR.n.lo, EAX);
 	MOV32RtoM((u32)&psxRegs.GPR.n.hi, EDX);
 
-	#if PGXP_TRACE >= 4 // iCB: Tracing
-	PUSH32M((u32)&psxRegs.GPR.n.lo);
-	PUSH32M((u32)&psxRegs.GPR.n.hi);
 
-	PUSH32I(psxRegs.code);
-#ifdef PGXP_CPU_DEBUG
-	CALLFunc((u32)PGXP_psxTraceOp4);
-#else
-	CALLFunc((u32)PGXP_CPU_MULTU);
-#endif
-	resp += 20;
-	#endif // iCB: /Tracing
 }
 
 static void recDIV() {
@@ -1624,16 +1291,6 @@ static void recDIV() {
 
 //	iFlushRegs();
 
-	#if PGXP_TRACE >= 4 // iCB: Tracing
-	if (IsConst(_Rt_))
-		PUSH32I(iRegs[_Rt_].k);
-	else
-		PUSH32M((u32)&psxRegs.GPR.r[_Rt_]);
-	if (IsConst(_Rs_))
-		PUSH32I(iRegs[_Rs_].k);
-	else
-		PUSH32M((u32)&psxRegs.GPR.r[_Rs_]);
-	#endif // iCB: /Tracing
 
 
 	if (IsConst(_Rt_)) {
@@ -1646,18 +1303,7 @@ static void recDIV() {
 				MOV32RtoM((u32)&psxRegs.GPR.n.hi, EAX);
 			}
 
-			#if PGXP_TRACE >= 4 // iCB: Tracing
-			PUSH32M((u32)&psxRegs.GPR.n.lo);
-			PUSH32M((u32)&psxRegs.GPR.n.hi);
 
-			PUSH32I(psxRegs.code);
-#ifdef PGXP_CPU_DEBUG
-			CALLFunc((u32)PGXP_psxTraceOp4);
-#else
-			CALLFunc((u32)PGXP_CPU_DIV);
-#endif
-			resp += 20;
-			#endif // iCB: /Tracing
 			return;
 		}
 		MOV32ItoR(ECX, iRegs[_Rt_].k);// printf("divrtk %x\n", iRegs[_Rt_].k);
@@ -1692,18 +1338,7 @@ static void recDIV() {
 		x86SetJ8(j8Ptr[1]);
 	}
 
-	#if PGXP_TRACE >= 4 // iCB: Tracing
-	PUSH32M((u32)&psxRegs.GPR.n.lo);
-	PUSH32M((u32)&psxRegs.GPR.n.hi);
 
-	PUSH32I(psxRegs.code);
-#ifdef PGXP_CPU_DEBUG
-	CALLFunc((u32)PGXP_psxTraceOp4);
-#else
-	CALLFunc((u32)PGXP_CPU_DIV);
-#endif
-	resp += 20;
-	#endif // iCB: /Tracing
 }
 
 static void recDIVU() {
@@ -1711,16 +1346,6 @@ static void recDIVU() {
 
 //	iFlushRegs();
 
-	#if PGXP_TRACE >= 4 // iCB: Tracing
-	if (IsConst(_Rt_))
-		PUSH32I(iRegs[_Rt_].k);
-	else
-		PUSH32M((u32)&psxRegs.GPR.r[_Rt_]);
-	if (IsConst(_Rs_))
-		PUSH32I(iRegs[_Rs_].k);
-	else
-		PUSH32M((u32)&psxRegs.GPR.r[_Rs_]);
-	#endif // iCB: /Tracing
 
 
 	if (IsConst(_Rt_)) {
@@ -1733,18 +1358,7 @@ static void recDIVU() {
 				MOV32RtoM((u32)&psxRegs.GPR.n.hi, EAX);
 			}
 
-			#if PGXP_TRACE >= 4 // iCB: Tracing
-			PUSH32M((u32)&psxRegs.GPR.n.lo);
-			PUSH32M((u32)&psxRegs.GPR.n.hi);
 
-			PUSH32I(psxRegs.code);
-#ifdef PGXP_CPU_DEBUG
-			CALLFunc((u32)PGXP_psxTraceOp4);
-#else
-			CALLFunc((u32)PGXP_CPU_DIVU);
-#endif
-			resp += 20;
-			#endif // iCB: /Tracing
 			return;
 		}
 		MOV32ItoR(ECX, iRegs[_Rt_].k);// printf("divurtk %x\n", iRegs[_Rt_].k);
@@ -1779,18 +1393,7 @@ static void recDIVU() {
 		x86SetJ8(j8Ptr[1]);
 	}
 
-	#if PGXP_TRACE >= 4 // iCB: Tracing
-	PUSH32M((u32)&psxRegs.GPR.n.lo);
-	PUSH32M((u32)&psxRegs.GPR.n.hi);
 
-	PUSH32I(psxRegs.code);
-#ifdef PGXP_CPU_DEBUG
-	CALLFunc((u32)PGXP_psxTraceOp4);
-#else
-	CALLFunc((u32)PGXP_CPU_DIVU);
-#endif
-	resp += 20;
-	#endif // iCB: /Tracing
 }
 //#endif
 //End of * Register mult/div & Register trap logic  
@@ -1825,17 +1428,6 @@ static void iPushOfB() {
 	}
 }
 
-u8 PGXP_LB_psxMemRead8(u32 mem, u32 code)
-{
-	u8 value = psxMemRead8(mem);
-#ifdef PGXP_CPU_DEBUG
-	PGXP_psxTraceOp2(code, value, mem);
-#else
-	PGXP_CPU_LB(code, value, mem);
-#endif
-	return value;
-}
-
 //#if 0
 static void recLB() {
 // Rt = mem[Rs + Im] (signed)
@@ -1858,18 +1450,6 @@ static void recLB() {
 
 			MOVSX32M8toR(EAX, (u32)&psxM[addr & 0x1fffff]);
 			MOV32RtoM((u32)&psxRegs.GPR.r[_Rt_], EAX);
-
-			// iCB: PGXP hook
-			PUSH32I(addr);
-			PUSH32M((u32)&psxRegs.GPR.r[_Rt_]);
-			PUSH32I(psxRegs.code);	// iCB: Needed to extract reg and opcode
-#ifdef PGXP_CPU_DEBUG
-			CALLFunc((u32)PGXP_psxTraceOp2);
-#else
-			CALLFunc((u32)PGXP_CPU_LB);
-#endif
-			resp += 12;
-			// iCB: PGXP /hook
 			return;
 		}
 		if (t == 0x1f80 && addr < 0x1f801000) {
@@ -1878,45 +1458,22 @@ static void recLB() {
 
 			MOVSX32M8toR(EAX, (u32)&psxH[addr & 0xfff]);
 			MOV32RtoM((u32)&psxRegs.GPR.r[_Rt_], EAX);
-
-			// iCB: PGXP hook
-			PUSH32I(addr);
-			PUSH32M((u32)&psxRegs.GPR.r[_Rt_]);
-			PUSH32I(psxRegs.code);	// iCB: Needed to extract reg and opcode
-#ifdef PGXP_CPU_DEBUG
-			CALLFunc((u32)PGXP_psxTraceOp2);
-#else
-			CALLFunc((u32)PGXP_CPU_LB);
-#endif
-			resp += 12;
-			// iCB: PGXP /hook
 			return;
 		}
 //		SysPrintf("unhandled r8 %x\n", addr);
 	}
 
-	PUSH32I(psxRegs.code);	// iCB: Needed to extract reg and opcode
 	iPushOfB();
-	CALLFunc((u32)PGXP_LB_psxMemRead8);
+	CALLFunc((u32)psxMemRead8);
 	if (_Rt_) {
 		iRegs[_Rt_].state = ST_UNK;
 		MOVSX32R8toR(EAX, EAX);
 		MOV32RtoM((u32)&psxRegs.GPR.r[_Rt_], EAX);
 	}
 //	ADD32ItoR(ESP, 4);
-	resp+= 8;
+	resp+= 4;
 }
 
-u8 PGXP_LBU_psxMemRead8(u32 mem, u32 code)
-{
-	u8 value = psxMemRead8(mem);
-#ifdef PGXP_CPU_DEBUG
-	PGXP_psxTraceOp2(code, value, mem);
-#else
-	PGXP_CPU_LBU(code, value, mem);
-#endif
-	return value;
-}
 
 static void recLBU() {
 // Rt = mem[Rs + Im] (unsigned)
@@ -1939,18 +1496,6 @@ static void recLBU() {
 
 			MOVZX32M8toR(EAX, (u32)&psxM[addr & 0x1fffff]);
 			MOV32RtoM((u32)&psxRegs.GPR.r[_Rt_], EAX);
-
-			// iCB: PGXP hook
-			PUSH32I(addr);
-			PUSH32M((u32)&psxRegs.GPR.r[_Rt_]);
-			PUSH32I(psxRegs.code);	// iCB: Needed to extract reg and opcode
-#ifdef PGXP_CPU_DEBUG
-			CALLFunc((u32)PGXP_psxTraceOp2);
-#else
-			CALLFunc((u32)PGXP_CPU_LBU);
-#endif
-			resp += 12;
-			// iCB: PGXP /hook
 			return;
 		}
 		if (t == 0x1f80 && addr < 0x1f801000) {
@@ -1959,45 +1504,22 @@ static void recLBU() {
 
 			MOVZX32M8toR(EAX, (u32)&psxH[addr & 0xfff]);
 			MOV32RtoM((u32)&psxRegs.GPR.r[_Rt_], EAX);
-
-			// iCB: PGXP hook
-			PUSH32I(addr);
-			PUSH32M((u32)&psxRegs.GPR.r[_Rt_]);
-			PUSH32I(psxRegs.code);	// iCB: Needed to extract reg and opcode
-#ifdef PGXP_CPU_DEBUG
-			CALLFunc((u32)PGXP_psxTraceOp2);
-#else
-			CALLFunc((u32)PGXP_CPU_LBU);
-#endif
-			resp += 12;
-			// iCB: PGXP /hook
 			return;
 		}
 //		SysPrintf("unhandled r8u %x\n", addr);
 	}
 
-	PUSH32I(psxRegs.code);	// iCB: Needed to extract reg and opcode
 	iPushOfB();
-	CALLFunc((u32)PGXP_LBU_psxMemRead8);
+	CALLFunc((u32)psxMemRead8);
 	if (_Rt_) {
 		iRegs[_Rt_].state = ST_UNK;
 		MOVZX32R8toR(EAX, EAX);
 		MOV32RtoM((u32)&psxRegs.GPR.r[_Rt_], EAX);
 	}
 //	ADD32ItoR(ESP, 4);
-	resp+= 8;
+	resp+= 4;
 }
 
-u16 PGXP_LH_psxMemRead16(u32 mem, u32 code)
-{
-	u16 value = psxMemRead16(mem);
-#ifdef PGXP_CPU_DEBUG
-	PGXP_psxTraceOp2(code, value, mem);
-#else
-	PGXP_CPU_LH(code, value, mem);
-#endif
-	return value;
-}
 
 static void recLH() {
 // Rt = mem[Rs + Im] (signed)
@@ -2020,18 +1542,6 @@ static void recLH() {
 
 			MOVSX32M16toR(EAX, (u32)&psxM[addr & 0x1fffff]);
 			MOV32RtoM((u32)&psxRegs.GPR.r[_Rt_], EAX);
-
-			// iCB: PGXP hook
-			PUSH32I(addr);
-			PUSH32M((u32)&psxRegs.GPR.r[_Rt_]);
-			PUSH32I(psxRegs.code);	// iCB: Needed to extract reg and opcode
-#ifdef PGXP_CPU_DEBUG
-			CALLFunc((u32)PGXP_psxTraceOp2);
-#else
-			CALLFunc((u32)PGXP_CPU_LH);
-#endif
-			resp += 12;
-			// iCB: PGXP /hook
 			return;
 		}
 		if (t == 0x1f80 && addr < 0x1f801000) {
@@ -2040,45 +1550,22 @@ static void recLH() {
 
 			MOVSX32M16toR(EAX, (u32)&psxH[addr & 0xfff]);
 			MOV32RtoM((u32)&psxRegs.GPR.r[_Rt_], EAX);
-
-			// iCB: PGXP hook
-			PUSH32I(addr);
-			PUSH32M((u32)&psxRegs.GPR.r[_Rt_]);
-			PUSH32I(psxRegs.code);	// iCB: Needed to extract reg and opcode
-#ifdef PGXP_CPU_DEBUG
-			CALLFunc((u32)PGXP_psxTraceOp2);
-#else
-			CALLFunc((u32)PGXP_CPU_LH);
-#endif
-			resp += 12;
-			// iCB: PGXP /hook
 			return;
 		}
 //		SysPrintf("unhandled r16 %x\n", addr);
 	}
 
-	PUSH32I(psxRegs.code);	// iCB: Needed to extract reg and opcode
 	iPushOfB();
-	CALLFunc((u32)PGXP_LH_psxMemRead16);
+	CALLFunc((u32)psxMemRead16);
 	if (_Rt_) {
 		iRegs[_Rt_].state = ST_UNK;
 		MOVSX32R16toR(EAX, EAX);
 		MOV32RtoM((u32)&psxRegs.GPR.r[_Rt_], EAX);
 	}
 //	ADD32ItoR(ESP, 4);
-	resp+= 8;
+	resp+= 4;
 }
 
-u16 PGXP_LHU_psxMemRead16(u32 mem, u32 code)
-{
-	u16 value = psxMemRead16(mem);
-#ifdef PGXP_CPU_DEBUG
-	PGXP_psxTraceOp2(code, value, mem);
-#else
-	PGXP_CPU_LHU(code, value, mem);
-#endif
-	return value;
-}
 
 static void recLHU() {
 // Rt = mem[Rs + Im] (unsigned)
@@ -2101,18 +1588,6 @@ static void recLHU() {
 
 			MOVZX32M16toR(EAX, (u32)&psxM[addr & 0x1fffff]);
 			MOV32RtoM((u32)&psxRegs.GPR.r[_Rt_], EAX);
-
-			// iCB: PGXP hook
-			PUSH32I(addr);
-			PUSH32M((u32)&psxRegs.GPR.r[_Rt_]);
-			PUSH32I(psxRegs.code);	// iCB: Needed to extract reg and opcode
-#ifdef PGXP_CPU_DEBUG
-			CALLFunc((u32)PGXP_psxTraceOp2);
-#else
-			CALLFunc((u32)PGXP_CPU_LHU);
-#endif
-			resp += 12;
-			// iCB: PGXP /hook
 			return;
 		}
 		if (t == 0x1f80 && addr < 0x1f801000) {
@@ -2121,18 +1596,6 @@ static void recLHU() {
 
 			MOVZX32M16toR(EAX, (u32)&psxH[addr & 0xfff]);
 			MOV32RtoM((u32)&psxRegs.GPR.r[_Rt_], EAX);
-
-			// iCB: PGXP hook
-			PUSH32I(addr);
-			PUSH32M((u32)&psxRegs.GPR.r[_Rt_]);
-			PUSH32I(psxRegs.code);	// iCB: Needed to extract reg and opcode
-#ifdef PGXP_CPU_DEBUG
-			CALLFunc((u32)PGXP_psxTraceOp2);
-#else
-			CALLFunc((u32)PGXP_CPU_LHU);
-#endif
-			resp += 12;
-			// iCB: PGXP /hook
 			return;
 		}
 		if (t == 0x1f80) {
@@ -2187,28 +1650,17 @@ static void recLHU() {
 //		SysPrintf("unhandled r16u %x\n", addr);
 	}
 
-	PUSH32I(psxRegs.code);	// iCB: Needed to extract reg and opcode
 	iPushOfB();
-	CALLFunc((u32)PGXP_LHU_psxMemRead16);
+	CALLFunc((u32)psxMemRead16);
 	if (_Rt_) {
 		iRegs[_Rt_].state = ST_UNK;
 		MOVZX32R16toR(EAX, EAX);
 		MOV32RtoM((u32)&psxRegs.GPR.r[_Rt_], EAX);
 	}
 //	ADD32ItoR(ESP, 4);
-	resp+= 8;
+	resp+= 4;
 }
 
-u32 PGXP_LW_psxMemRead32(u32 mem, u32 code)
-{
-	u32 value = psxMemRead32(mem);
-#ifdef PGXP_CPU_DEBUG
-	PGXP_psxTraceOp2(code, value, mem);
-#else
-	PGXP_CPU_LW(code, value, mem);
-#endif
-	return value;
-}
 
 static void recLW() {
 // Rt = mem[Rs + Im] (unsigned)
@@ -2239,18 +1691,6 @@ static void recLW() {
 
 			MOV32MtoR(EAX, (u32)&psxH[addr & 0xfff]);
 			MOV32RtoM((u32)&psxRegs.GPR.r[_Rt_], EAX);
-
-			// iCB: PGXP hook
-			PUSH32I(addr);
-			PUSH32M((u32)&psxRegs.GPR.r[_Rt_]);
-			PUSH32I(psxRegs.code);	// iCB: Needed to extract reg and opcode
-#ifdef PGXP_CPU_DEBUG
-			CALLFunc((u32)PGXP_psxTraceOp2);
-#else
-			CALLFunc((u32)PGXP_CPU_LW);
-#endif
-			resp += 12;
-			// iCB: PGXP /hook
 			return;
 		}
 		if (t == 0x1f80) {
@@ -2269,18 +1709,6 @@ static void recLW() {
 
 					MOV32MtoR(EAX, (u32)&psxH[addr & 0xffff]);
 					MOV32RtoM((u32)&psxRegs.GPR.r[_Rt_], EAX);
-
-					// iCB: PGXP hook
-					PUSH32I(addr);
-					PUSH32M((u32)&psxRegs.GPR.r[_Rt_]);
-					PUSH32I(psxRegs.code);	// iCB: Needed to extract reg and opcode
-#ifdef PGXP_CPU_DEBUG
-					CALLFunc((u32)PGXP_psxTraceOp2);
-#else
-					CALLFunc((u32)PGXP_CPU_LW);
-#endif
-					resp += 12;
-					// iCB: PGXP /hook
 					return;
 
 				case 0x1f801810:
@@ -2303,15 +1731,14 @@ static void recLW() {
 //		SysPrintf("unhandled r32 %x\n", addr);
 	}
 
-	PUSH32I(psxRegs.code);	// iCB: Needed to extract reg and opcode
 	iPushOfB();
-	CALLFunc((u32)PGXP_LW_psxMemRead32);
+	CALLFunc((u32)psxMemRead32);
 	if (_Rt_) {
 		iRegs[_Rt_].state = ST_UNK;
 		MOV32RtoM((u32)&psxRegs.GPR.r[_Rt_], EAX);
 	}
 //	ADD32ItoR(ESP, 4);
-	resp+= 8;
+	resp+= 4;
 }
 
 extern u32 LWL_MASK[4];
@@ -2328,17 +1755,6 @@ void iLWLk(u32 shift) {
 	OR32RtoR (EAX, ECX);
 }
 
-u32 PGXP_LWL_psxMemRead32(u32 mem, u32 code)
-{
-	u32 value = psxMemRead32(mem);
-#ifdef PGXP_CPU_DEBUG
-	PGXP_psxTraceOp2(code, value, mem);
-#else
-	PGXP_CPU_LWL(code, value, mem);
-#endif
-	return value;
-}
-
 void recLWL() {
 // Rt = Rt Merge mem[Rs + Im]
 
@@ -2360,18 +1776,6 @@ void recLWL() {
 
 			iRegs[_Rt_].state = ST_UNK;
 			MOV32RtoM((u32)&psxRegs.GPR.r[_Rt_], EAX);
-
-			// iCB: PGXP hook
-			PUSH32I(addr);
-			PUSH32M((u32)&psxRegs.GPR.r[_Rt_]);
-			PUSH32I(psxRegs.code);				// iCB: Needed to extract reg and opcode
-#ifdef PGXP_CPU_DEBUG
-			CALLFunc((u32)PGXP_psxTraceOp2);
-#else
-			CALLFunc((u32)PGXP_CPU_LWL);
-#endif
-			resp += 12;
-			// iCB: PGXP /hook
 			return;
 		}
 	}
@@ -2382,13 +1786,12 @@ void recLWL() {
 		if (_Imm_) ADD32ItoR(EAX, _Imm_);
 	}
 	PUSH32R  (EAX);
-	PUSH32I(psxRegs.code);	// iCB: Needed to extract reg and opcode
 	AND32ItoR(EAX, ~3);
 	PUSH32R  (EAX);
-	CALLFunc((u32)PGXP_LWL_psxMemRead32);
+	CALLFunc((u32)psxMemRead32);
 
 	if (_Rt_) {
-		ADD32ItoR(ESP, 8);
+		ADD32ItoR(ESP, 4);
 		POP32R   (EDX);
 		AND32ItoR(EDX, 0x3); // shift = addr & 3;
 
@@ -2411,7 +1814,7 @@ void recLWL() {
 		MOV32RtoM((u32)&psxRegs.GPR.r[_Rt_], EAX);
 	} else {
 //		ADD32ItoR(ESP, 8);
-		resp+= 12;
+		resp+= 8;
 	}
 }
 
@@ -2506,17 +1909,6 @@ void iLWRk(u32 shift) {
 	OR32RtoR(EAX, ECX);
 }
 
-u32 PGXP_LWR_psxMemRead32(u32 mem, u32 code)
-{
-	u32 value = psxMemRead32(mem);
-#ifdef PGXP_CPU_DEBUG
-	PGXP_psxTraceOp2(code, value, mem);
-#else
-	PGXP_CPU_LWR(code, value, mem);
-#endif
-	return value;
-}
-
 void recLWR() {
 // Rt = Rt Merge mem[Rs + Im]
 
@@ -2538,18 +1930,6 @@ void recLWR() {
 
 			iRegs[_Rt_].state = ST_UNK;
 			MOV32RtoM((u32)&psxRegs.GPR.r[_Rt_], EAX);
-
-			// iCB: PGXP hook
-			PUSH32I(addr);
-			PUSH32M((u32)&psxRegs.GPR.r[_Rt_]);
-			PUSH32I(psxRegs.code);	// iCB: Needed to extract reg and opcode
-#ifdef PGXP_CPU_DEBUG
-			CALLFunc((u32)PGXP_psxTraceOp2);
-#else
-			CALLFunc((u32)PGXP_CPU_LWR);
-#endif
-			resp += 12;
-			// iCB: PGXP /hook
 			return;
 		}
 	}
@@ -2561,13 +1941,12 @@ void recLWR() {
 		if (_Imm_) ADD32ItoR(EAX, _Imm_);
 	}
 	PUSH32R  (EAX);
-	PUSH32I(psxRegs.code);	// iCB: Needed to extract reg and opcode
 	AND32ItoR(EAX, ~3);
 	PUSH32R  (EAX);
-	CALLFunc((u32)PGXP_LWR_psxMemRead32);
+	CALLFunc((u32)psxMemRead32);
 
 	if (_Rt_) {
-		ADD32ItoR(ESP, 8);
+		ADD32ItoR(ESP, 4);
 		POP32R   (EDX);
 		AND32ItoR(EDX, 0x3); // shift = addr & 3;
 
@@ -2591,19 +1970,10 @@ void recLWR() {
 		MOV32RtoM((u32)&psxRegs.GPR.r[_Rt_], EAX);
 	} else {
 //		ADD32ItoR(ESP, 8);
-		resp+= 12;
+		resp+= 8;
 	}
 }
 
-void PGXP_SB_psxMemWrite8(u32 addr, u16 value, u32 code)
-{
-#ifdef PGXP_CPU_DEBUG
-	PGXP_psxTraceOp2(code, value, addr);
-#else
-	PGXP_CPU_SH(code, value, addr);
-#endif
-	psxMemWrite8(addr, value);
-}
 
 static void recSB() {
 // mem[Rs + Im] = Rt
@@ -2636,48 +2006,20 @@ static void recSB() {
 				MOV8MtoR(EAX, (u32)&psxRegs.GPR.r[_Rt_]);
 				MOV8RtoM((u32)&psxH[addr & 0xfff], EAX);
 			}
-
-			// iCB: PGXP hook
-			PUSH32I(addr);
-			if (IsConst(_Rt_)) {
-				PUSH32I(iRegs[_Rt_].k);
-			}
-			else {
-				PUSH32M((u32)&psxRegs.GPR.r[_Rt_]);
-			}
-			PUSH32I(psxRegs.code);	// iCB: Needed to extract reg and opcode
-#ifdef PGXP_CPU_DEBUG
-			CALLFunc((u32)PGXP_psxTraceOp2);
-#else
-			CALLFunc((u32)PGXP_CPU_SB);
-#endif
-			resp += 12;
-			// iCB: PGXP /hook
 			return;
 		}
 //		SysPrintf("unhandled w8 %x\n", addr);
 	}
 
-	PUSH32I(psxRegs.code);	// iCB: Needed to extract reg and opcode
 	if (IsConst(_Rt_)) {
 		PUSH32I  (iRegs[_Rt_].k);
 	} else {
 		PUSH32M  ((u32)&psxRegs.GPR.r[_Rt_]);
 	}
 	iPushOfB();
-	CALLFunc((u32)PGXP_SB_psxMemWrite8);
+	CALLFunc((u32)psxMemWrite8);
 //	ADD32ItoR(ESP, 8);
-	resp+= 12;
-}
-
-void PGXP_SH_psxMemWrite16(u32 addr, u16 value, u32 code)
-{
-#ifdef PGXP_CPU_DEBUG
-	PGXP_psxTraceOp2(code, value, addr);
-#else
-	PGXP_CPU_SH(code, value, addr);
-#endif
-	psxMemWrite16(addr, value);
+	resp+= 8;
 }
 
 static void recSH() {
@@ -2712,22 +2054,6 @@ static void recSH() {
 				MOV16RtoM((u32)&psxH[addr & 0xfff], EAX);
 			}
 
-			// iCB: PGXP hook
-			PUSH32I(addr);
-			if (IsConst(_Rt_)) {
-				PUSH32I(iRegs[_Rt_].k);
-			}
-			else {
-				PUSH32M((u32)&psxRegs.GPR.r[_Rt_]);
-			}
-			PUSH32I(psxRegs.code);	// iCB: Needed to extract reg and opcode
-#ifdef PGXP_CPU_DEBUG
-			CALLFunc((u32)PGXP_psxTraceOp2);
-#else
-			CALLFunc((u32)PGXP_CPU_SH);
-#endif
-			resp += 12;
-			// iCB: PGXP /hook
 			return;
 		}
 		if (t == 0x1f80) {
@@ -2748,26 +2074,15 @@ static void recSH() {
 //		SysPrintf("unhandled w16 %x\n", addr);
 	}
 
-	PUSH32I(psxRegs.code);	// iCB: Needed to extract reg and opcode
 	if (IsConst(_Rt_)) {
 		PUSH32I  (iRegs[_Rt_].k);
 	} else {
 		PUSH32M  ((u32)&psxRegs.GPR.r[_Rt_]);
 	}
 	iPushOfB();
-	CALLFunc((u32)PGXP_SH_psxMemWrite16);
+	CALLFunc((u32)psxMemWrite16);
 //	ADD32ItoR(ESP, 8);
-	resp+= 12;
-}
-
-void PGXP_SW_psxMemWrite32(u32 addr, u32 value, u32 code)
-{
-#ifdef PGXP_CPU_DEBUG
-	PGXP_psxTraceOp2(code, value, addr);
-#else
-	PGXP_CPU_SW(code, value, addr);
-#endif
-	psxMemWrite32(addr, value);
+	resp+= 8;
 }
 
 static void recSW() {
@@ -2801,23 +2116,6 @@ static void recSW() {
 				MOV32MtoR(EAX, (u32)&psxRegs.GPR.r[_Rt_]);
 				MOV32RtoM((u32)&psxH[addr & 0xfff], EAX);
 			}
-
-			// iCB: PGXP hook
-			PUSH32I(addr);
-			if (IsConst(_Rt_)) {
-				PUSH32I(iRegs[_Rt_].k);
-			}
-			else {
-				PUSH32M((u32)&psxRegs.GPR.r[_Rt_]);
-			}
-			PUSH32I(psxRegs.code);	// iCB: Needed to extract reg and opcode
-#ifdef PGXP_CPU_DEBUG
-			CALLFunc((u32)PGXP_psxTraceOp2);
-#else
-			CALLFunc((u32)PGXP_CPU_SW);
-#endif
-			resp += 12;
-			// iCB: PGXP /hook
 			return;
 		}
 		if (t == 0x1f80) {
@@ -2837,23 +2135,6 @@ static void recSW() {
 						MOV32MtoR(EAX, (u32)&psxRegs.GPR.r[_Rt_]);
 						MOV32RtoM((u32)&psxH[addr & 0xffff], EAX);
 					}
-
-					// iCB: PGXP hook
-					PUSH32I(addr);
-					if (IsConst(_Rt_)) {
-						PUSH32I(iRegs[_Rt_].k);
-					}
-					else {
-						PUSH32M((u32)&psxRegs.GPR.r[_Rt_]);
-					}
-					PUSH32I(psxRegs.code);	// iCB: Needed to extract reg and opcode
-#ifdef PGXP_CPU_DEBUG
-					CALLFunc((u32)PGXP_psxTraceOp2);
-#else
-					CALLFunc((u32)PGXP_CPU_SW);
-#endif
-					resp += 12;
-					// iCB: PGXP /hook
 					return;
 
 				case 0x1f801810:
@@ -2884,16 +2165,15 @@ static void recSW() {
 //		SysPrintf("unhandled w32 %x\n", addr);
 	}
 
-	PUSH32I(psxRegs.code);	// iCB: Needed to extract reg and opcode
 	if (IsConst(_Rt_)) {
 		PUSH32I  (iRegs[_Rt_].k);
 	} else {
 		PUSH32M  ((u32)&psxRegs.GPR.r[_Rt_]);
 	}
 	iPushOfB();
-	CALLFunc((u32)PGXP_SW_psxMemWrite32);
+	CALLFunc((u32)psxMemWrite32);
 //	ADD32ItoR(ESP, 8);
-	resp+= 12;
+	resp+= 8;
 }
 //#endif
 
@@ -2981,15 +2261,6 @@ void iSWLk(u32 shift) {
 	OR32RtoR (EAX, ECX);
 }
 
-void PGXP_SWL_psxMemWrite32(u32 addr, u32 value, u32 code)
-{
-#ifdef PGXP_CPU_DEBUG
-	PGXP_psxTraceOp2(code, value, addr);
-#else
-	PGXP_CPU_SWL(code, value, addr);
-#endif
-	psxMemWrite32(addr, value);
-}
 
 void recSWL() {
 // mem[Rs + Im] = Rt Merge mem[Rs + Im]
@@ -3011,22 +2282,6 @@ void recSWL() {
 			iSWLk(addr & 3);
 			MOV32RtoM((u32)&psxH[addr & 0xffc], EAX);
 
-			// iCB: PGXP hook
-			PUSH32I(addr);
-			if (IsConst(_Rt_)) {
-				PUSH32I(iRegs[_Rt_].k);
-			}
-			else {
-				PUSH32M((u32)&psxRegs.GPR.r[_Rt_]);
-			}
-			PUSH32I(psxRegs.code);	// iCB: Needed to extract reg and opcode
-#ifdef PGXP_CPU_DEBUG
-			CALLFunc((u32)PGXP_psxTraceOp2);
-#else
-			CALLFunc((u32)PGXP_CPU_SWL);
-#endif
-			resp += 12;
-			// iCB: PGXP /hook
 			return;
 		}
 	}
@@ -3060,8 +2315,6 @@ void recSWL() {
 	}
 	SHR32CLtoR(EDX); // _rRt_ >> SWL_SHIFT[shift]
 
-	PUSH32I(psxRegs.code);	// iCB: Needed to extract reg and opcode
-
 	OR32RtoR (EAX, EDX);
 	PUSH32R  (EAX);
 
@@ -3073,9 +2326,9 @@ void recSWL() {
 	AND32ItoR(EAX, ~3);
 	PUSH32R  (EAX);
 
-	CALLFunc((u32)PGXP_SWL_psxMemWrite32);
+	CALLFunc((u32)psxMemWrite32);
 //	ADD32ItoR(ESP, 8);
-	resp+= 12;
+	resp+= 8;
 }
 
 extern u32 SWR_MASK[4];
@@ -3092,16 +2345,6 @@ void iSWRk(u32 shift) {
 	OR32RtoR (EAX, ECX);
 }
 
-void PGXP_SWR_psxMemWrite32(u32 addr, u32 value, u32 code)
-{
-#ifdef PGXP_CPU_DEBUG
-	PGXP_psxTraceOp2(code, value, addr);
-#else
-	PGXP_CPU_SWR(code, value, addr);
-#endif
-	psxMemWrite32(addr, value);
-}
-
 void recSWR() {
 // mem[Rs + Im] = Rt Merge mem[Rs + Im]
 
@@ -3121,23 +2364,6 @@ void recSWR() {
 			MOV32MtoR(EAX, (u32)&psxH[addr & 0xffc]);
 			iSWRk(addr & 3);
 			MOV32RtoM((u32)&psxH[addr & 0xffc], EAX);
-
-			// iCB: PGXP hook
-			PUSH32I(addr);
-			if (IsConst(_Rt_)) {
-				PUSH32I(iRegs[_Rt_].k);
-			}
-			else {
-				PUSH32M((u32)&psxRegs.GPR.r[_Rt_]);
-			}
-			PUSH32I(psxRegs.code);	// iCB: Needed to extract reg and opcode
-#ifdef PGXP_CPU_DEBUG
-			CALLFunc((u32)PGXP_psxTraceOp2);
-#else
-			CALLFunc((u32)PGXP_CPU_SWR);
-#endif
-			resp += 12;
-			// iCB: PGXP /hook
 			return;
 		}
 	}
@@ -3171,8 +2397,6 @@ void recSWR() {
 	}
 	SHL32CLtoR(EDX); // _rRt_ << SWR_SHIFT[shift]
 
-	PUSH32I(psxRegs.code);	// iCB: Needed to extract reg and opcode
-
 	OR32RtoR (EAX, EDX);
 	PUSH32R  (EAX);
 
@@ -3184,9 +2408,9 @@ void recSWR() {
 	AND32ItoR(EAX, ~3);
 	PUSH32R  (EAX);
 
-	CALLFunc((u32)PGXP_SWR_psxMemWrite32);
+	CALLFunc((u32)psxMemWrite32);
 //	ADD32ItoR(ESP, 8);
-	resp += 12;
+	resp += 8;
 }
 
 /*REC_FUNC(SLL);
@@ -3200,12 +2424,6 @@ static void recSLL() {
 
 //	iFlushRegs();
 
-	#if PGXP_TRACE >= 5 // iCB: Tracing
-	if (IsConst(_Rt_))
-		PUSH32I(iRegs[_Rt_].k);
-	else
-		PUSH32M((u32)&psxRegs.GPR.r[_Rt_]);
-	#endif // iCB: /Tracing
 
 
 	if (IsConst(_Rt_)) {
@@ -3218,17 +2436,7 @@ static void recSLL() {
 		MOV32RtoM((u32)&psxRegs.GPR.r[_Rd_], EAX);
 	}
 
-	#if PGXP_TRACE >= 5 // iCB: Tracing
-	PUSH32M((u32)&psxRegs.GPR.r[_Rd_]);
 
-	PUSH32I(psxRegs.code);
-#ifdef PGXP_CPU_DEBUG
-	CALLFunc((u32)PGXP_psxTraceOp2);
-#else
-	CALLFunc((u32)PGXP_CPU_SLL);
-#endif
-	resp += 12;
-	#endif // iCB: /Tracing
 }
 
 static void recSRL() {
@@ -3238,12 +2446,6 @@ static void recSRL() {
 
 //	iFlushRegs();
 
-	#if PGXP_TRACE >= 5 // iCB: Tracing
-	if (IsConst(_Rt_))
-		PUSH32I(iRegs[_Rt_].k);
-	else
-		PUSH32M((u32)&psxRegs.GPR.r[_Rt_]);
-	#endif // iCB: /Tracing
 
 	if (IsConst(_Rt_)) {
 		MapConst(_Rd_, iRegs[_Rt_].k >> _Sa_);
@@ -3255,17 +2457,7 @@ static void recSRL() {
 		MOV32RtoM((u32)&psxRegs.GPR.r[_Rd_], EAX);
 	}
 
-	#if PGXP_TRACE >= 5 // iCB: Tracing
-	PUSH32M((u32)&psxRegs.GPR.r[_Rd_]);
 
-	PUSH32I(psxRegs.code);
-#ifdef PGXP_CPU_DEBUG
-	CALLFunc((u32)PGXP_psxTraceOp2);
-#else
-	CALLFunc((u32)PGXP_CPU_SRL); 
-#endif
-	resp += 12;
-	#endif // iCB: /Tracing
 }
 
 static void recSRA() {
@@ -3275,12 +2467,6 @@ static void recSRA() {
 
 //	iFlushRegs();
 
-	#if PGXP_TRACE >= 5 // iCB: Tracing
-	if (IsConst(_Rt_))
-		PUSH32I(iRegs[_Rt_].k);
-	else
-		PUSH32M((u32)&psxRegs.GPR.r[_Rt_]);
-	#endif // iCB: /Tracing
 
 	if (IsConst(_Rt_)) {
 		MapConst(_Rd_, (s32)iRegs[_Rt_].k >> _Sa_);
@@ -3292,17 +2478,7 @@ static void recSRA() {
 		MOV32RtoM((u32)&psxRegs.GPR.r[_Rd_], EAX);
 	}
 
-	#if PGXP_TRACE >= 5 // iCB: Tracing
-	PUSH32M((u32)&psxRegs.GPR.r[_Rd_]);
 
-	PUSH32I(psxRegs.code);
-#ifdef PGXP_CPU_DEBUG
-	CALLFunc((u32)PGXP_psxTraceOp2);
-#else
-	CALLFunc((u32)PGXP_CPU_SRA);
-#endif
-	resp += 12;
-	#endif // iCB: /Tracing
 }
 //#endif
 
@@ -3317,16 +2493,6 @@ static void recSLLV() {
 
 //	iFlushRegs();
 
-	#if PGXP_TRACE >= 6 // iCB: Tracing
-	if (IsConst(_Rs_))
-		PUSH32I(iRegs[_Rs_].k);
-	else
-		PUSH32M((u32)&psxRegs.GPR.r[_Rs_]);
-	if (IsConst(_Rt_))
-		PUSH32I(iRegs[_Rt_].k);
-	else
-		PUSH32M((u32)&psxRegs.GPR.r[_Rt_]);
-	#endif // iCB: /Tracing
 
 	if (IsConst(_Rt_) && IsConst(_Rs_)) {
 		MapConst(_Rd_, iRegs[_Rt_].k << iRegs[_Rs_].k);
@@ -3353,17 +2519,7 @@ static void recSLLV() {
 		MOV32RtoM((u32)&psxRegs.GPR.r[_Rd_], EAX);
 	}
 
-	#if PGXP_TRACE >= 6 // iCB: Tracing
-	PUSH32M((u32)&psxRegs.GPR.r[_Rd_]);
 
-	PUSH32I(psxRegs.code);
-#ifdef PGXP_CPU_DEBUG
-	CALLFunc((u32)PGXP_psxTraceOp3);
-#else
-	CALLFunc((u32)PGXP_CPU_SLLV);
-#endif
-	resp += 16;
-	#endif // iCB: /Tracing
 }
 
 static void recSRLV() {
@@ -3372,16 +2528,6 @@ static void recSRLV() {
 
 //	iFlushRegs();
 
-	#if PGXP_TRACE >= 6 // iCB: Tracing
-	if (IsConst(_Rs_))
-		PUSH32I(iRegs[_Rs_].k);
-	else
-		PUSH32M((u32)&psxRegs.GPR.r[_Rs_]);
-	if (IsConst(_Rt_))
-		PUSH32I(iRegs[_Rt_].k);
-	else
-		PUSH32M((u32)&psxRegs.GPR.r[_Rt_]);
-	#endif // iCB: /Tracing
 
 	if (IsConst(_Rt_) && IsConst(_Rs_)) {
 		MapConst(_Rd_, iRegs[_Rt_].k >> iRegs[_Rs_].k);
@@ -3408,17 +2554,7 @@ static void recSRLV() {
 		MOV32RtoM((u32)&psxRegs.GPR.r[_Rd_], EAX);
 	}
 
-	#if PGXP_TRACE >= 6 // iCB: Tracing
-	PUSH32M((u32)&psxRegs.GPR.r[_Rd_]);
 
-	PUSH32I(psxRegs.code);
-#ifdef PGXP_CPU_DEBUG
-	CALLFunc((u32)PGXP_psxTraceOp3);
-#else
-	CALLFunc((u32)PGXP_CPU_SRLV);
-#endif
-	resp += 16;
-	#endif // iCB: /Tracing
 }
 
 static void recSRAV() {
@@ -3428,16 +2564,6 @@ static void recSRAV() {
 
 //	iFlushRegs();
 
-	#if PGXP_TRACE >= 6 // iCB: Tracing
-	if (IsConst(_Rs_))
-		PUSH32I(iRegs[_Rs_].k);
-	else
-		PUSH32M((u32)&psxRegs.GPR.r[_Rs_]);
-	if (IsConst(_Rt_))
-		PUSH32I(iRegs[_Rt_].k);
-	else
-		PUSH32M((u32)&psxRegs.GPR.r[_Rt_]);
-	#endif // iCB: /Tracing
 
 	if (IsConst(_Rt_) && IsConst(_Rs_)) {
 		MapConst(_Rd_, (s32)iRegs[_Rt_].k >> iRegs[_Rs_].k);
@@ -3464,17 +2590,7 @@ static void recSRAV() {
 		MOV32RtoM((u32)&psxRegs.GPR.r[_Rd_], EAX);
 	}
 
-	#if PGXP_TRACE >= 6 // iCB: Tracing
-	PUSH32M((u32)&psxRegs.GPR.r[_Rd_]);
 
-	PUSH32I(psxRegs.code);
-#ifdef PGXP_CPU_DEBUG
-	CALLFunc((u32)PGXP_psxTraceOp3);
-#else
-	CALLFunc((u32)PGXP_CPU_SRAV);
-#endif
-	resp += 16;
-	#endif // iCB: /Tracing
 }
 //#endif
 
@@ -3512,36 +2628,17 @@ static void recMFHI() {
 	if (!_Rd_)
 		return;
 
-	#if PGXP_TRACE >= 7 // iCB: Tracing
-	PUSH32M((u32)&psxRegs.GPR.n.hi);
-	#endif // iCB: /Tracing
 
 	iRegs[_Rd_].state = ST_UNK;
 	MOV32MtoR(EAX, (u32)&psxRegs.GPR.n.hi);
 	MOV32RtoM((u32)&psxRegs.GPR.r[_Rd_], EAX);
 
-	#if PGXP_TRACE >= 7 // iCB: Tracing
-	PUSH32M((u32)&psxRegs.GPR.r[_Rd_]);
 
-	PUSH32I(psxRegs.code);
-#ifdef PGXP_CPU_DEBUG
-	CALLFunc((u32)PGXP_psxTraceOp2);
-#else
-	CALLFunc((u32)PGXP_CPU_MFHI);
-#endif
-	resp += 12;
-	#endif // iCB: /Tracing
 }
 
 static void recMTHI() {
 // Hi = Rs
 
-	#if PGXP_TRACE >= 7 // iCB: Tracing
-	if (IsConst(_Rs_))
-		PUSH32I(iRegs[_Rs_].k);
-	else
-		PUSH32M((u32)&psxRegs.GPR.r[_Rs_]);
-	#endif // iCB: /Tracing
 
 	if (IsConst(_Rs_)) {
 		MOV32ItoM((u32)&psxRegs.GPR.n.hi, iRegs[_Rs_].k);
@@ -3550,17 +2647,7 @@ static void recMTHI() {
 		MOV32RtoM((u32)&psxRegs.GPR.n.hi, EAX);
 	}
 
-	#if PGXP_TRACE >= 7 // iCB: Tracing
-	PUSH32M((u32)&psxRegs.GPR.n.hi);
 
-	PUSH32I(psxRegs.code);
-#ifdef PGXP_CPU_DEBUG
-	CALLFunc((u32)PGXP_psxTraceOp2);
-#else
-	CALLFunc((u32)PGXP_CPU_MTHI);
-#endif
-	resp += 12;
-	#endif // iCB: /Tracing
 }
 
 static void recMFLO() {
@@ -3568,35 +2655,16 @@ static void recMFLO() {
 	if (!_Rd_)
 		return;
 
-	#if PGXP_TRACE >= 7 // iCB: Tracing
-	PUSH32M((u32)&psxRegs.GPR.n.lo);
-	#endif // iCB: /Tracing
 
 	iRegs[_Rd_].state = ST_UNK;
 	MOV32MtoR(EAX, (u32)&psxRegs.GPR.n.lo);
 	MOV32RtoM((u32)&psxRegs.GPR.r[_Rd_], EAX);
 
-	#if PGXP_TRACE >= 7 // iCB: Tracing
-	PUSH32M((u32)&psxRegs.GPR.r[_Rd_]);
-	PUSH32I(psxRegs.code);
-#ifdef PGXP_CPU_DEBUG
-	CALLFunc((u32)PGXP_psxTraceOp2);
-#else
-	CALLFunc((u32)PGXP_CPU_MFLO);
-#endif
-	resp += 12;
-	#endif // iCB: /Tracing
 }
 
 static void recMTLO() {
 // Lo = Rs
 
-	#if PGXP_TRACE >= 7 // iCB: Tracing
-	if (IsConst(_Rs_))
-		PUSH32I(iRegs[_Rs_].k);
-	else
-		PUSH32M((u32)&psxRegs.GPR.r[_Rs_]);
-	#endif // iCB: /Tracing
 
 	if (IsConst(_Rs_)) {
 		MOV32ItoM((u32)&psxRegs.GPR.n.lo, iRegs[_Rs_].k);
@@ -3605,17 +2673,7 @@ static void recMTLO() {
 		MOV32RtoM((u32)&psxRegs.GPR.n.lo, EAX);
 	}
 
-	#if PGXP_TRACE >= 7 // iCB: Tracing
-	PUSH32M((u32)&psxRegs.GPR.n.lo);
 
-	PUSH32I(psxRegs.code);
-#ifdef PGXP_CPU_DEBUG
-	CALLFunc((u32)PGXP_psxTraceOp2);
-#else
-	CALLFunc((u32)PGXP_CPU_MTLO);
-#endif
-	resp += 12;
-	#endif // iCB: /Tracing
 }
 //#endif
 
@@ -3950,7 +3008,7 @@ static void recMFC0() {
 }
 
 static void recCFC0() {
-// Rt = Cop0->Rd
+	// Rt = Cop0->Rd
 
 	recMFC0();
 }
@@ -4032,6 +3090,8 @@ static void recHLE() {
 
 //
 
+#include "iPGXP.h"
+
 static void (*recBSC[64])() = {
 	recSPECIAL, recREGIMM, recJ   , recJAL  , recBEQ , recBNE , recBLEZ, recBGTZ,
 	recADDI   , recADDIU , recSLTI, recSLTIU, recANDI, recORI , recXORI, recLUI ,
@@ -4086,6 +3146,56 @@ static void (*recCP2BSC[32])() = {
 	recNULL, recNULL, recNULL, recNULL, recNULL, recNULL, recNULL, recNULL
 };
 
+
+// Trace all functions using PGXP
+static void(*pgxpRecBSC[64])() = {
+	recSPECIAL, recREGIMM, recJ   , recJAL  , recBEQ , recBNE , recBLEZ, recBGTZ,
+	pgxpRecADDI   , pgxpRecADDIU , pgxpRecSLTI, pgxpRecSLTIU, pgxpRecANDI, pgxpRecORI , pgxpRecXORI, pgxpRecLUI ,
+	recCOP0   , recNULL  , recCOP2, recNULL , recNULL, recNULL, recNULL, recNULL,
+	recNULL   , recNULL  , recNULL, recNULL , recNULL, recNULL, recNULL, recNULL,
+	pgxpRecLB     , pgxpRecLH    , pgxpRecLWL , pgxpRecLW   , pgxpRecLBU , pgxpRecLHU , pgxpRecLWR , pgxpRecNULL,
+	pgxpRecSB     , pgxpRecSH    , pgxpRecSWL , pgxpRecSW   , pgxpRecNULL, pgxpRecNULL, pgxpRecSWR , pgxpRecNULL,
+	recNULL   , recNULL  , pgxpRecLWC2, recNULL , recNULL, recNULL, recNULL, recNULL,
+	recNULL   , recNULL  , pgxpRecSWC2, recHLE  , recNULL, recNULL, recNULL, recNULL
+};
+
+static void(*pgxpRecSPC[64])() = {
+	pgxpRecSLL , pgxpRecNULL, pgxpRecSRL , pgxpRecSRA , pgxpRecSLLV   , pgxpRecNULL , pgxpRecSRLV, pgxpRecSRAV,
+	recJR  , recJALR, recNULL, recNULL, recSYSCALL, recBREAK, recNULL, recNULL,
+	pgxpRecMFHI, pgxpRecMTHI, pgxpRecMFLO, pgxpRecMTLO, pgxpRecNULL   , pgxpRecNULL , pgxpRecNULL, pgxpRecNULL,
+	pgxpRecMULT, pgxpRecMULTU, pgxpRecDIV, pgxpRecDIVU, pgxpRecNULL   , pgxpRecNULL , pgxpRecNULL, pgxpRecNULL,
+	pgxpRecADD , pgxpRecADDU, pgxpRecSUB , pgxpRecSUBU, pgxpRecAND    , pgxpRecOR   , pgxpRecXOR , pgxpRecNOR ,
+	pgxpRecNULL, pgxpRecNULL, pgxpRecSLT , pgxpRecSLTU, pgxpRecNULL   , pgxpRecNULL , pgxpRecNULL, pgxpRecNULL,
+	pgxpRecNULL, pgxpRecNULL, pgxpRecNULL, pgxpRecNULL, pgxpRecNULL   , pgxpRecNULL , pgxpRecNULL, pgxpRecNULL,
+	pgxpRecNULL, pgxpRecNULL, pgxpRecNULL, pgxpRecNULL, pgxpRecNULL   , pgxpRecNULL , pgxpRecNULL, pgxpRecNULL
+};
+
+static void(*pgxpRecCP0[32])() = {
+	pgxpRecMFC0, pgxpRecNULL, pgxpRecCFC0, pgxpRecNULL, pgxpRecMTC0, pgxpRecNULL, pgxpRecCTC0, pgxpRecNULL,
+	pgxpRecNULL, pgxpRecNULL, pgxpRecNULL, pgxpRecNULL, pgxpRecNULL, pgxpRecNULL, pgxpRecNULL, pgxpRecNULL,
+	pgxpRecRFE , pgxpRecNULL, pgxpRecNULL, pgxpRecNULL, pgxpRecNULL, pgxpRecNULL, pgxpRecNULL, pgxpRecNULL,
+	pgxpRecNULL, pgxpRecNULL, pgxpRecNULL, pgxpRecNULL, pgxpRecNULL, pgxpRecNULL, pgxpRecNULL, pgxpRecNULL
+};
+
+static void(*pgxpRecCP2BSC[32])() = {
+	pgxpRecMFC2, pgxpRecNULL, pgxpRecCFC2, pgxpRecNULL, pgxpRecMTC2, pgxpRecNULL, pgxpRecCTC2, pgxpRecNULL,
+	pgxpRecNULL, pgxpRecNULL, pgxpRecNULL, pgxpRecNULL, pgxpRecNULL, pgxpRecNULL, pgxpRecNULL, pgxpRecNULL,
+	pgxpRecNULL, pgxpRecNULL, pgxpRecNULL, pgxpRecNULL, pgxpRecNULL, pgxpRecNULL, pgxpRecNULL, pgxpRecNULL,
+	pgxpRecNULL, pgxpRecNULL, pgxpRecNULL, pgxpRecNULL, pgxpRecNULL, pgxpRecNULL, pgxpRecNULL, pgxpRecNULL
+};
+
+// Trace memory functions only
+static void(*pgxpRecBSCMem[64])() = {
+	recSPECIAL, recREGIMM, recJ   , recJAL  , recBEQ , recBNE , recBLEZ, recBGTZ,
+	recADDI   , recADDIU , recSLTI, recSLTIU, recANDI, recORI , recXORI, recLUI ,
+	recCOP0   , recNULL  , recCOP2, recNULL , recNULL, recNULL, recNULL, recNULL,
+	recNULL   , recNULL  , recNULL, recNULL , recNULL, recNULL, recNULL, recNULL,
+	pgxpRecLB     , pgxpRecLH    , pgxpRecLWL , pgxpRecLW   , pgxpRecLBU , pgxpRecLHU , pgxpRecLWR , pgxpRecNULL,
+	pgxpRecSB     , pgxpRecSH    , pgxpRecSWL , pgxpRecSW   , pgxpRecNULL, pgxpRecNULL, pgxpRecSWR , pgxpRecNULL,
+	recNULL   , recNULL  , pgxpRecLWC2, recNULL , recNULL, recNULL, recNULL, recNULL,
+	recNULL   , recNULL  , pgxpRecSWC2, recHLE  , recNULL, recNULL, recNULL, recNULL
+};
+
 static void recRecompile() {
 	char *p;
 	char *ptr;
@@ -4151,7 +3261,7 @@ static void recRecompile() {
 
 		pc += 4;
 		count++;
-		recBSC[psxRegs.code >> 26]();
+		pRecBSC[psxRegs.code >> 26]();
 
 		if (branch) {
 			branch = 0;
@@ -4173,7 +3283,8 @@ R3000Acpu psxRec = {
 	recExecute,
 	recExecuteBlock,
 	recClear,
-	recShutdown
+	recShutdown,
+	recSetPGXPMode
 };
 
 #endif
diff --git a/libpcsxcore/pgxp_cpu.c b/libpcsxcore/pgxp_cpu.c
index 99c507be..a5484740 100644
--- a/libpcsxcore/pgxp_cpu.c
+++ b/libpcsxcore/pgxp_cpu.c
@@ -6,8 +6,10 @@
 // CPU registers
 PGXP_value CPU_reg_mem[34];
 //PGXP_value CPU_Hi, CPU_Lo;
+PGXP_value CP0_reg_mem[32];
 
 PGXP_value* CPU_reg = CPU_reg_mem;
+PGXP_value* CP0_reg = CP0_reg_mem;
 
 // Instruction register decoding
 #define op(_instr)		(_instr >> 26)			// The op part of the instruction register 
@@ -197,6 +199,7 @@ void PGXP_CPU_LUI(u32 instr, u32 rtVal)
 void PGXP_CPU_ADD(u32 instr, u32 rdVal, u32 rsVal, u32 rtVal)
 {
 	// Rd = Rs + Rt (signed)
+	PGXP_value ret;
 	Validate(&CPU_reg[rs(instr)], rsVal);
 	Validate(&CPU_reg[rt(instr)], rtVal);
 
@@ -207,17 +210,19 @@ void PGXP_CPU_ADD(u32 instr, u32 rdVal, u32 rsVal, u32 rtVal)
 		MakeValid(&CPU_reg[rt(instr)], rtVal);
 	}
 
-	CPU_reg[rd(instr)] = CPU_reg[rs(instr)];
+	ret = CPU_reg[rs(instr)];
 
-	CPU_reg[rd(instr)].x += CPU_reg[rt(instr)].x;
-	CPU_reg[rd(instr)].y += CPU_reg[rt(instr)].y;
+	ret.x += CPU_reg[rt(instr)].x;
+	ret.y += CPU_reg[rt(instr)].y;
 
-	CPU_reg[rd(instr)].valid &= CPU_reg[rt(instr)].valid;
-	CPU_reg[rd(instr)].gFlags |= CPU_reg[rt(instr)].gFlags;
-	CPU_reg[rd(instr)].lFlags |= CPU_reg[rt(instr)].lFlags;
-	CPU_reg[rd(instr)].hFlags |= CPU_reg[rt(instr)].hFlags;
+	ret.valid &= CPU_reg[rt(instr)].valid;
+	ret.gFlags |= CPU_reg[rt(instr)].gFlags;
+	ret.lFlags |= CPU_reg[rt(instr)].lFlags;
+	ret.hFlags |= CPU_reg[rt(instr)].hFlags;
 
-	CPU_reg[rd(instr)].value = rdVal;
+	ret.value = rdVal;
+
+	CPU_reg[rd(instr)] = ret;
 }
 
 void PGXP_CPU_ADDU(u32 instr, u32 rdVal, u32 rsVal, u32 rtVal)
@@ -229,27 +234,30 @@ void PGXP_CPU_ADDU(u32 instr, u32 rdVal, u32 rsVal, u32 rtVal)
 void PGXP_CPU_SUB(u32 instr, u32 rdVal, u32 rsVal, u32 rtVal)
 {
 	// Rd = Rs - Rt (signed)
+	PGXP_value ret;
 	Validate(&CPU_reg[rs(instr)], rsVal);
 	Validate(&CPU_reg[rt(instr)], rtVal);
 
 	// iCB: Only require one valid input
-	//if (!(CPU_reg[rs(instr)].valid && CPU_reg[rt(instr)].valid) && (CPU_reg[rs(instr)].valid || CPU_reg[rt(instr)].valid))
-	//{
-	//	MakeValid(&CPU_reg[rs(instr)], rsVal);
-	//	MakeValid(&CPU_reg[rt(instr)], rtVal);
-	//}
+	if (!(CPU_reg[rs(instr)].valid && CPU_reg[rt(instr)].valid) && (CPU_reg[rs(instr)].valid || CPU_reg[rt(instr)].valid))
+	{
+		MakeValid(&CPU_reg[rs(instr)], rsVal);
+		MakeValid(&CPU_reg[rt(instr)], rtVal);
+	}
 
-	CPU_reg[rd(instr)] = CPU_reg[rs(instr)];
+	ret = CPU_reg[rs(instr)];
 
-	CPU_reg[rd(instr)].x -= CPU_reg[rt(instr)].x;
-	CPU_reg[rd(instr)].y -= CPU_reg[rt(instr)].y;
+	ret.x -= CPU_reg[rt(instr)].x;
+	ret.y -= CPU_reg[rt(instr)].y;
 
-	CPU_reg[rd(instr)].valid &= CPU_reg[rt(instr)].valid;
-	CPU_reg[rd(instr)].gFlags |= CPU_reg[rt(instr)].gFlags;
-	CPU_reg[rd(instr)].lFlags |= CPU_reg[rt(instr)].lFlags;
-	CPU_reg[rd(instr)].hFlags |= CPU_reg[rt(instr)].hFlags;
+	ret.valid &= CPU_reg[rt(instr)].valid;
+	ret.gFlags |= CPU_reg[rt(instr)].gFlags;
+	ret.lFlags |= CPU_reg[rt(instr)].lFlags;
+	ret.hFlags |= CPU_reg[rt(instr)].hFlags;
 
-	CPU_reg[rd(instr)].value = rdVal;
+	ret.value = rdVal;
+
+	CPU_reg[rd(instr)] = ret;
 }
 
 void PGXP_CPU_SUBU(u32 instr, u32 rdVal, u32 rsVal, u32 rtVal)
@@ -262,76 +270,78 @@ void PGXP_CPU_AND(u32 instr, u32 rdVal, u32 rsVal, u32 rtVal)
 {
 	// Rd = Rs & Rt
 	psx_value vald, vals, valt;
+	PGXP_value ret;
 
 	Validate(&CPU_reg[rs(instr)], rsVal);
 	Validate(&CPU_reg[rt(instr)], rtVal);
 
 	// iCB: Only require one valid input
-	//if (!(CPU_reg[rs(instr)].valid && CPU_reg[rt(instr)].valid) && (CPU_reg[rs(instr)].valid || CPU_reg[rt(instr)].valid))
-	//{
-	//	MakeValid(&CPU_reg[rs(instr)], rsVal);
-	//	MakeValid(&CPU_reg[rt(instr)], rtVal);
-	//}
+	if (!(CPU_reg[rs(instr)].valid && CPU_reg[rt(instr)].valid) && (CPU_reg[rs(instr)].valid || CPU_reg[rt(instr)].valid))
+	{
+		MakeValid(&CPU_reg[rs(instr)], rsVal);
+		MakeValid(&CPU_reg[rt(instr)], rtVal);
+	}
 
 	vald.d = rdVal;
 	vals.d = rsVal;
 	valt.d = rtVal;
 
 	//	CPU_reg[rd(instr)].valid = CPU_reg[rs(instr)].valid && CPU_reg[rt(instr)].valid;
-	CPU_reg[rd(instr)].valid = 1;
+	ret.valid = 1;
 
 	if (vald.w.l == 0)
 	{
-		CPU_reg[rd(instr)].x = 0.f;
-		CPU_reg[rd(instr)].lFlags = VALID_HALF;
+		ret.x = 0.f;
+		ret.lFlags = VALID_HALF;
 	}
 	else if (vald.w.l == vals.w.l)
 	{
-		CPU_reg[rd(instr)].x = CPU_reg[rs(instr)].x;
-		CPU_reg[rd(instr)].lFlags = CPU_reg[rs(instr)].lFlags;
-		CPU_reg[rd(instr)].valid &= CPU_reg[rs(instr)].valid;
+		ret.x = CPU_reg[rs(instr)].x;
+		ret.lFlags = CPU_reg[rs(instr)].lFlags;
+		ret.valid &= CPU_reg[rs(instr)].valid;
 	}
 	else if (vald.w.l == valt.w.l)
 	{
-		CPU_reg[rd(instr)].x = CPU_reg[rt(instr)].x;
-		CPU_reg[rd(instr)].lFlags = CPU_reg[rt(instr)].lFlags;
-		CPU_reg[rd(instr)].valid &= CPU_reg[rt(instr)].valid;
+		ret.x = CPU_reg[rt(instr)].x;
+		ret.lFlags = CPU_reg[rt(instr)].lFlags;
+		ret.valid &= CPU_reg[rt(instr)].valid;
 	}
 	else
 	{
-		CPU_reg[rd(instr)].valid = 0;
-		CPU_reg[rd(instr)].lFlags = 0;
+		ret.valid = 0;
+		ret.lFlags = 0;
 	}
 
 	if (vald.w.h == 0)
 	{
-		CPU_reg[rd(instr)].y = 0.f;
-		CPU_reg[rd(instr)].hFlags = VALID_HALF;
+		ret.y = 0.f;
+		ret.hFlags = VALID_HALF;
 	}
 	else if (vald.w.h == vals.w.h)
 	{
-		CPU_reg[rd(instr)].y = CPU_reg[rs(instr)].y;
-		CPU_reg[rd(instr)].hFlags = CPU_reg[rs(instr)].hFlags;
-		CPU_reg[rd(instr)].valid &= CPU_reg[rs(instr)].valid;
+		ret.y = CPU_reg[rs(instr)].y;
+		ret.hFlags = CPU_reg[rs(instr)].hFlags;
+		ret.valid &= CPU_reg[rs(instr)].valid;
 	}
 	else if (vald.w.h == valt.w.h)
 	{
-		CPU_reg[rd(instr)].y = CPU_reg[rt(instr)].y;
-		CPU_reg[rd(instr)].hFlags = CPU_reg[rt(instr)].hFlags;
-		CPU_reg[rd(instr)].valid &= CPU_reg[rt(instr)].valid;
+		ret.y = CPU_reg[rt(instr)].y;
+		ret.hFlags = CPU_reg[rt(instr)].hFlags;
+		ret.valid &= CPU_reg[rt(instr)].valid;
 	}
 	else
 	{
-		CPU_reg[rd(instr)].valid = 0;
-		CPU_reg[rd(instr)].hFlags = 0;
+		ret.valid = 0;
+		ret.hFlags = 0;
 	}
 
 	// iCB Hack: Force validity if even one half is valid
-	if ((CPU_reg[rd(instr)].hFlags & VALID_HALF) || (CPU_reg[rd(instr)].lFlags & VALID_HALF))
-		CPU_reg[rd(instr)].valid = 1;
+	if ((ret.hFlags & VALID_HALF) || (ret.lFlags & VALID_HALF))
+		ret.valid = 1;
 	// /iCB Hack
 
-	CPU_reg[rd(instr)].value = rdVal;
+	ret.value = rdVal;
+	CPU_reg[rd(instr)] = ret;
 }
 
 void PGXP_CPU_OR(u32 instr, u32 rdVal, u32 rsVal, u32 rtVal)
@@ -355,44 +365,48 @@ void PGXP_CPU_NOR(u32 instr, u32 rdVal, u32 rsVal, u32 rtVal)
 void PGXP_CPU_SLT(u32 instr, u32 rdVal, u32 rsVal, u32 rtVal)
 {
 	// Rd = Rs < Rt (signed)
+	PGXP_value ret;
 	Validate(&CPU_reg[rs(instr)], rsVal);
 	Validate(&CPU_reg[rt(instr)], rtVal);
 
 	// iCB: Only require one valid input
-	//if (!(CPU_reg[rs(instr)].valid && CPU_reg[rt(instr)].valid) && (CPU_reg[rs(instr)].valid || CPU_reg[rt(instr)].valid))
-	//{
-	//	MakeValid(&CPU_reg[rs(instr)], rsVal);
-	//	MakeValid(&CPU_reg[rt(instr)], rtVal);
-	//}
+	if (!(CPU_reg[rs(instr)].valid && CPU_reg[rt(instr)].valid) && (CPU_reg[rs(instr)].valid || CPU_reg[rt(instr)].valid))
+	{
+		MakeValid(&CPU_reg[rs(instr)], rsVal);
+		MakeValid(&CPU_reg[rt(instr)], rtVal);
+	}
 
-	CPU_reg[rd(instr)] = CPU_reg[rs(instr)];
+	ret = CPU_reg[rs(instr)];
 
 	// TODO: fix for single or double values?
-	CPU_reg[rd(instr)].y = 0.f;
-	CPU_reg[rd(instr)].x = (CPU_reg[rs(instr)].x < CPU_reg[rt(instr)].x) ? 1.f : 0.f;
+	ret.y = 0.f;
+	ret.x = (CPU_reg[rs(instr)].x < CPU_reg[rt(instr)].x) ? 1.f : 0.f;
 
-	CPU_reg[rd(instr)].value = rdVal;
+	ret.value = rdVal;
+	CPU_reg[rd(instr)] = ret;
 }
 
 void PGXP_CPU_SLTU(u32 instr, u32 rdVal, u32 rsVal, u32 rtVal)
 {
 	// Rd = Rs < Rt (unsigned)
+	PGXP_value ret;
 	Validate(&CPU_reg[rs(instr)], rsVal);
 	Validate(&CPU_reg[rt(instr)], rtVal);
 
 	// iCB: Only require one valid input
-	//if (!(CPU_reg[rs(instr)].valid && CPU_reg[rt(instr)].valid) && (CPU_reg[rs(instr)].valid || CPU_reg[rt(instr)].valid))
-	//{
-	//	MakeValid(&CPU_reg[rs(instr)], rsVal);
-	//	MakeValid(&CPU_reg[rt(instr)], rtVal);
-	//}
+	if (!(CPU_reg[rs(instr)].valid && CPU_reg[rt(instr)].valid) && (CPU_reg[rs(instr)].valid || CPU_reg[rt(instr)].valid))
+	{
+		MakeValid(&CPU_reg[rs(instr)], rsVal);
+		MakeValid(&CPU_reg[rt(instr)], rtVal);
+	}
 
-	CPU_reg[rd(instr)] = CPU_reg[rs(instr)];
+	ret = CPU_reg[rs(instr)];
 
-	CPU_reg[rd(instr)].y = 0.f;
-	CPU_reg[rd(instr)].x = (fabs(CPU_reg[rs(instr)].x) < fabs(CPU_reg[rt(instr)].x)) ? 1.f : 0.f;
+	ret.y = 0.f;
+	ret.x = (fabs(CPU_reg[rs(instr)].x) < fabs(CPU_reg[rt(instr)].x)) ? 1.f : 0.f;
 
-	CPU_reg[rd(instr)].value = rdVal;
+	ret.value = rdVal;
+	CPU_reg[rd(instr)] = ret;
 }
 
 ////////////////////////////////////
@@ -414,8 +428,8 @@ void PGXP_CPU_MULT(u32 instr, u32 hiVal, u32 loVal, u32 rsVal, u32 rtVal)
 	float vs = CPU_reg[rs(instr)].y + (CPU_reg[rs(instr)].x / (float)(1 << 16));
 	float vt = CPU_reg[rt(instr)].y + (CPU_reg[rt(instr)].x / (float)(1 << 16));
 
-	CPU_Lo.x = 0;// CPU_reg[rs(instr)].x * CPU_reg[rt(instr)].x;
 	CPU_Hi.x = vs * vt;// CPU_reg[rs(instr)].y * CPU_reg[rt(instr)].y;
+	CPU_Lo.y = (CPU_Hi.x - ((s32)CPU_Hi.x)) * (float)(1 << 16);// CPU_reg[rs(instr)].x * CPU_reg[rt(instr)].x; // Get fractional part
 
 	CPU_Lo.valid = CPU_Hi.valid = CPU_reg[rs(instr)].valid && CPU_reg[rt(instr)].valid;
 
@@ -439,8 +453,8 @@ void PGXP_CPU_MULTU(u32 instr, u32 hiVal, u32 loVal, u32 rsVal, u32 rtVal)
 	float vs = fabs(CPU_reg[rs(instr)].y) + (fabs(CPU_reg[rs(instr)].x) / (float)(1 << 16));
 	float vt = fabs(CPU_reg[rt(instr)].y) + (fabs(CPU_reg[rt(instr)].x) / (float)(1 << 16));
 
-	CPU_Lo.x = 0;// fabs(CPU_reg[rs(instr)].x) * fabs(CPU_reg[rt(instr)].x);
 	CPU_Hi.x = vs * vt;// fabs(CPU_reg[rs(instr)].y) * fabs(CPU_reg[rt(instr)].y);
+	CPU_Lo.y = (CPU_Hi.x - ((s32)CPU_Hi.x)) * (float)(1 << 16);// fabs(CPU_reg[rs(instr)].x) * fabs(CPU_reg[rt(instr)].x);	// Get fractional part
 
 	CPU_Lo.valid = CPU_Hi.valid = CPU_reg[rs(instr)].valid && CPU_reg[rt(instr)].valid;
 
@@ -456,11 +470,11 @@ void PGXP_CPU_DIV(u32 instr, u32 hiVal, u32 loVal, u32 rsVal, u32 rtVal)
 	Validate(&CPU_reg[rt(instr)], rtVal);
 
 	//// iCB: Only require one valid input
-	//if (!(CPU_reg[rs(instr)].valid && CPU_reg[rt(instr)].valid) && (CPU_reg[rs(instr)].valid || CPU_reg[rt(instr)].valid))
-	//{
-	//	MakeValid(&CPU_reg[rs(instr)], rsVal);
-	//	MakeValid(&CPU_reg[rt(instr)], rtVal);
-	//}
+	if (!(CPU_reg[rs(instr)].valid && CPU_reg[rt(instr)].valid) && (CPU_reg[rs(instr)].valid || CPU_reg[rt(instr)].valid))
+	{
+		MakeValid(&CPU_reg[rs(instr)], rsVal);
+		MakeValid(&CPU_reg[rt(instr)], rtVal);
+	}
 
 	float vs = CPU_reg[rs(instr)].y + (CPU_reg[rs(instr)].x / (float)(1 << 16));
 	float vt = CPU_reg[rt(instr)].y + (CPU_reg[rt(instr)].x / (float)(1 << 16));
@@ -483,11 +497,11 @@ void PGXP_CPU_DIVU(u32 instr, u32 hiVal, u32 loVal, u32 rsVal, u32 rtVal)
 	Validate(&CPU_reg[rt(instr)], rtVal);
 
 	//// iCB: Only require one valid input
-	//if (!(CPU_reg[rs(instr)].valid && CPU_reg[rt(instr)].valid) && (CPU_reg[rs(instr)].valid || CPU_reg[rt(instr)].valid))
-	//{
-	//	MakeValid(&CPU_reg[rs(instr)], rsVal);
-	//	MakeValid(&CPU_reg[rt(instr)], rtVal);
-	//}
+	if (!(CPU_reg[rs(instr)].valid && CPU_reg[rt(instr)].valid) && (CPU_reg[rs(instr)].valid || CPU_reg[rt(instr)].valid))
+	{
+		MakeValid(&CPU_reg[rs(instr)], rsVal);
+		MakeValid(&CPU_reg[rt(instr)], rtVal);
+	}
 
 	float vs = CPU_reg[rs(instr)].y + (CPU_reg[rs(instr)].x / (float)(1 << 16));
 	float vt = CPU_reg[rt(instr)].y + (CPU_reg[rt(instr)].x / (float)(1 << 16));
@@ -508,49 +522,53 @@ void PGXP_CPU_DIVU(u32 instr, u32 hiVal, u32 loVal, u32 rsVal, u32 rtVal)
 void PGXP_CPU_SLL(u32 instr, u32 rdVal, u32 rtVal)
 {
 	// Rd = Rt << Sa
+	PGXP_value ret;
 	u32 sh = sa(instr);
 	Validate(&CPU_reg[rt(instr)], rtVal);
-	CPU_reg[rd(instr)] = CPU_reg[rt(instr)];
+	ret = CPU_reg[rt(instr)];
 
 	// Shift y into x?
 	if (sh >= 16)
 	{
-		CPU_reg[rd(instr)].y = CPU_reg[rd(instr)].x;
-		CPU_reg[rd(instr)].x = 0;
-		CPU_reg[rd(instr)].hFlags = CPU_reg[rd(instr)].lFlags;
-		CPU_reg[rd(instr)].lFlags = 0;
+		ret.y = ret.x;
+		ret.x = 0;
+		ret.hFlags = ret.lFlags;
+		ret.lFlags = 0;
 		sh -= 16;
 	}
 	
 	// assume multiply with no overflow
-	CPU_reg[rd(instr)].x *= (float)(1 << sh);
-	CPU_reg[rd(instr)].y *= (float)(1 << sh);
+	ret.x *= (float)(1 << sh);
+	ret.y *= (float)(1 << sh);
 
-	CPU_reg[rd(instr)].value = rdVal;
+	ret.value = rdVal;
+	CPU_reg[rd(instr)] = ret;
 }
 
 void PGXP_CPU_SRL(u32 instr, u32 rdVal, u32 rtVal)
 {
 	// Rd = Rt >> Sa
+	PGXP_value ret;
 	u32 sh = sa(instr);
 	Validate(&CPU_reg[rt(instr)], rtVal);
-	CPU_reg[rd(instr)] = CPU_reg[rt(instr)];
+	ret = CPU_reg[rt(instr)];
 
 	// Shift x into y?
 	if (sh >= 16)
 	{
-		CPU_reg[rd(instr)].x = CPU_reg[rd(instr)].y;
-		CPU_reg[rd(instr)].y = 0;
-		CPU_reg[rd(instr)].lFlags = CPU_reg[rd(instr)].hFlags;
-		CPU_reg[rd(instr)].hFlags = 0;
+		ret.x = ret.y;
+		ret.y = 0;
+		ret.lFlags = ret.hFlags;
+		ret.hFlags = 0;
 		sh -= 16;
 	}
 	
 	// assume divide with no overflow
-	CPU_reg[rd(instr)].x /= (float)(1 << sh);
-	CPU_reg[rd(instr)].y /= (float)(1 << sh);
+	ret.x /= (float)(1 << sh);
+	ret.y /= (float)(1 << sh);
 
-	CPU_reg[rd(instr)].value = rdVal;
+	ret.value = rdVal;
+	CPU_reg[rd(instr)] = ret;
 }
 
 void PGXP_CPU_SRA(u32 instr, u32 rdVal, u32 rtVal)
@@ -565,53 +583,57 @@ void PGXP_CPU_SRA(u32 instr, u32 rdVal, u32 rtVal)
 void PGXP_CPU_SLLV(u32 instr, u32 rdVal, u32 rtVal, u32 rsVal)
 {
 	// Rd = Rt << Rs
+	PGXP_value ret;
 	u32 sh = rsVal & 0x1F;
 	Validate(&CPU_reg[rt(instr)], rtVal);
 	Validate(&CPU_reg[rs(instr)], rsVal);
 
-	CPU_reg[rd(instr)] = CPU_reg[rt(instr)];
+	ret = CPU_reg[rt(instr)];
 
 	// Shift y into x?
 	if (sh >= 16)
 	{
-		CPU_reg[rd(instr)].y = CPU_reg[rd(instr)].x;
-		CPU_reg[rd(instr)].x = 0;
-		CPU_reg[rd(instr)].hFlags = CPU_reg[rd(instr)].lFlags;
-		CPU_reg[rd(instr)].lFlags = 0;
+		ret.y = ret.x;
+		ret.x = 0;
+		ret.hFlags = ret.lFlags;
+		ret.lFlags = 0;
 		sh -= 16;
 	}
 
 	// assume multiply with no overflow
-	CPU_reg[rd(instr)].x *= (float)(1 << sh);
-	CPU_reg[rd(instr)].y *= (float)(1 << sh);
+	ret.x *= (float)(1 << sh);
+	ret.y *= (float)(1 << sh);
 
-	CPU_reg[rd(instr)].value = rdVal;
+	ret.value = rdVal;
+	CPU_reg[rd(instr)] = ret;
 }
 
 void PGXP_CPU_SRLV(u32 instr, u32 rdVal, u32 rtVal, u32 rsVal)
 {
 	// Rd = Rt >> Sa
+	PGXP_value ret;
 	u32 sh = rsVal & 0x1F;
 	Validate(&CPU_reg[rt(instr)], rtVal);
 	Validate(&CPU_reg[rs(instr)], rsVal);
 
-	CPU_reg[rd(instr)] = CPU_reg[rt(instr)];
+	ret = CPU_reg[rt(instr)];
 
 	// Shift x into y?
 	if (sh >= 16)
 	{
-		CPU_reg[rd(instr)].x = CPU_reg[rd(instr)].y;
-		CPU_reg[rd(instr)].y = 0;
-		CPU_reg[rd(instr)].lFlags = CPU_reg[rd(instr)].hFlags;
-		CPU_reg[rd(instr)].hFlags = 0;
+		ret.x = ret.y;
+		ret.y = 0;
+		ret.lFlags = ret.hFlags;
+		ret.hFlags = 0;
 		sh -= 16;
 	}
 
 	// assume divide with no overflow
-	CPU_reg[rd(instr)].x /= (float)(1 << sh);
-	CPU_reg[rd(instr)].y /= (float)(1 << sh);
+	ret.x /= (float)(1 << sh);
+	ret.y /= (float)(1 << sh);
 
-	CPU_reg[rd(instr)].value = rdVal;
+	ret.value = rdVal;
+	CPU_reg[rd(instr)] = ret;
 }
 
 void PGXP_CPU_SRAV(u32 instr, u32 rdVal, u32 rtVal, u32 rsVal)
@@ -742,3 +764,33 @@ void PGXP_CPU_SB(u32 instr, u8 rtVal, u32 addr)
 	InvalidStore(addr, instr, 208);
 }
 
+////////////////////////////////////
+// Data transfer tracking
+////////////////////////////////////
+void PGXP_CP0_MFC0(u32 instr, u32 rdVal)
+{
+	// CPU[Rt] = CP0[Rd]
+	Validate(&CP0_reg[rd(instr)], rdVal);
+	CPU_reg[rt(instr)] = CP0_reg[rd(instr)];
+}
+
+void PGXP_CP0_MTC0(u32 instr, u32 rtVal)
+{
+	// CP0[Rd] = CPU[Rt]
+	Validate(&CPU_reg[rt(instr)], rtVal);
+	CP0_reg[rd(instr)] = CPU_reg[rt(instr)];
+}
+
+void PGXP_CP0_CFC0(u32 instr, u32 rdVal)
+{
+	// CPU[Rt] = CP0[Rd]
+	Validate(&CP0_reg[rd(instr)], rdVal);
+	CPU_reg[rt(instr)] = CP0_reg[rd(instr)];
+}
+
+void PGXP_CP0_CTC0(u32 instr, u32 rtVal)
+{
+	// CP0[Rd] = CPU[Rt]
+	Validate(&CPU_reg[rt(instr)], rtVal);
+	CP0_reg[rd(instr)] = CPU_reg[rt(instr)];
+}
\ No newline at end of file
diff --git a/libpcsxcore/pgxp_cpu.h b/libpcsxcore/pgxp_cpu.h
index c97929b1..50236d54 100644
--- a/libpcsxcore/pgxp_cpu.h
+++ b/libpcsxcore/pgxp_cpu.h
@@ -30,16 +30,15 @@
 
 #include "psxcommon.h"
 
-#define PGXP_TRACE 9
-#define PGXP_CPU_DEBUG
-
 struct PGXP_value_Tag;
 typedef struct PGXP_value_Tag PGXP_value;
 
 extern PGXP_value* CPU_reg;
+extern PGXP_value* CP0_reg;
 #define CPU_Hi CPU_reg[33]
 #define CPU_Lo CPU_reg[34]
 
+
 // -- CPU functions
 
 // Load 32-bit word
@@ -112,4 +111,10 @@ void PGXP_CPU_MTHI(u32 instr, u32 hiVal, u32 rdVal);
 void PGXP_CPU_MFLO(u32 instr, u32 rdVal, u32 loVal);
 void PGXP_CPU_MTLO(u32 instr, u32 loVal, u32 rdVal);
 
+// CP0 Data transfer tracking
+void PGXP_CP0_MFC0(u32 instr, u32 rdVal);
+void PGXP_CP0_MTC0(u32 instr, u32 rtVal);
+void PGXP_CP0_CFC0(u32 instr, u32 rdVal);
+void PGXP_CP0_CTC0(u32 instr, u32 rtVal);
+
 #endif //_PGXP_CPU_H_
\ No newline at end of file
diff --git a/libpcsxcore/pgxp_debug.c b/libpcsxcore/pgxp_debug.c
index da8cacae..5349a2b7 100644
--- a/libpcsxcore/pgxp_debug.c
+++ b/libpcsxcore/pgxp_debug.c
@@ -1,5 +1,7 @@
 #include "pgxp_debug.h"
 #include "pgxp_cpu.h"
+#include "pgxp_gte.h"
+#include "pgxp_mem.h"
 #include "pgxp_value.h"
 
 unsigned int pgxp_debug = 0;
@@ -16,20 +18,29 @@ unsigned int pgxp_debug = 0;
 // Operand ID flags
 typedef enum
 {
-	fOp_Hi = 1 << 0,
-	fOp_Lo = 1 << 1,
-	fOp_Rd = 1 << 2,
-	fOp_Rs = 1 << 3,
-	fOp_Rt = 1 << 4,
-	fOp_Sa = 1 << 5,
-	fOp_Im = 1 << 6,
-	fOp_Ad = 1 << 7
+	fOp_CPU_Hi = 1 << 0,
+	fOp_CPU_Lo = 1 << 1,
+	fOp_CPU_Rd = 1 << 2,
+	fOp_CPU_Rs = 1 << 3,
+	fOp_CPU_Rt = 1 << 4,
+
+	fOp_GTE_Dd = 1 << 5,
+	fOp_GTE_Dt = 1 << 6,
+	fOp_GTE_Cd = 1 << 7,
+	fOp_GTE_Ct = 1 << 8,
+
+	fOp_CP0_Dd = 1 << 9,
+	fOp_CP0_Cd = 1 << 10,
+
+	fOp_Ad = 1 << 11,
+	fOp_Sa = 1 << 12,
+	fOp_Im = 1 << 13
 } PGXP_CPU_OperandIDs;
 
 typedef struct
 {
-	unsigned char OutputFlags;
-	unsigned char InputFlags;
+	unsigned short OutputFlags;
+	unsigned short InputFlags;
 	unsigned char numRegisters;
 	unsigned char numArgs;
 	const char* szOpString;
@@ -37,38 +48,45 @@ typedef struct
 	void(*funcPtr)();
 } PGXP_CPU_OpData;
 
-#define PGXP_Data_NULL		{ 0, 0, 0, 0, NULL }
-#define PGXP_Data_SPECIAL	{ 0, 0, 0, 0, NULL }
-#define PGXP_Data_COP0		{ 0, 0, 0, 0, NULL }
-#define PGXP_Data_COP2		{ 0, 0, 0, 0, NULL }
-#define PGXP_Data_LWC2		{ 0, 0, 0, 0, NULL }
-#define PGXP_Data_SWC2		{ 0, 0, 0, 0, NULL }
-#define PGXP_Data_HLE		{ 0, 0, 0, 0, NULL }
+void PGXP_CPU_EMPTY() {}
+void PGXP_CPU_NULL() { int* pi = NULL; *pi = 5; }
+void PGXP_CPU_ERROR() { int* pi = NULL; *pi = 5; }
+
+#define PGXP_Data_ERROR		{ 0, 0, 0, 0, "", "ERROR",		(void(*)())PGXP_CPU_ERROR }
+#define PGXP_Data_NULL		{ 0, 0, 0, 0, "", "NULL",		(void(*)())PGXP_CPU_NULL }
+#define PGXP_Data_SPECIAL	{ 0, 0, 0, 0, "", "SPECIAL",	(void(*)())PGXP_CPU_EMPTY }
+#define PGXP_Data_COP0		{ 0, 0, 0, 0, "", "COP0",		(void(*)())PGXP_CPU_EMPTY }
+#define PGXP_Data_COP2		{ 0, 0, 0, 0, "", "COP2",		(void(*)())PGXP_CPU_EMPTY }
+#define PGXP_Data_HLE		{ 0, 0, 0, 0, "", "HLE",		(void(*)())PGXP_CPU_EMPTY }
 
 // Arithmetic with immediate value
-#define PGXP_Data_ADDI	{ fOp_Rt, fOp_Rs | fOp_Im, 2, 2, "+", "ADDI",	(void(*)())PGXP_CPU_ADDI }
-#define PGXP_Data_ADDIU	{ fOp_Rt, fOp_Rs | fOp_Im, 2, 2, "+", "ADDIU",	(void(*)())PGXP_CPU_ADDIU }
-#define PGXP_Data_ANDI	{ fOp_Rt, fOp_Rs | fOp_Im, 2, 2, "&", "ANDI",	(void(*)())PGXP_CPU_ANDI }
-#define PGXP_Data_ORI	{ fOp_Rt, fOp_Rs | fOp_Im, 2, 2, "|", "ORI",	(void(*)())PGXP_CPU_ORI }
-#define PGXP_Data_XORI	{ fOp_Rt, fOp_Rs | fOp_Im, 2, 2, "^", "XORI",	(void(*)())PGXP_CPU_XORI }
-#define PGXP_Data_SLTI	{ fOp_Rt, fOp_Rs | fOp_Im, 2, 2, "<", "SLTI",	(void(*)())PGXP_CPU_SLTI }
-#define PGXP_Data_SLTIU	{ fOp_Rt, fOp_Rs | fOp_Im, 2, 2, "<", "SLTIU",	(void(*)())PGXP_CPU_SLTIU }
+#define PGXP_Data_ADDI	{ fOp_CPU_Rt, fOp_CPU_Rs | fOp_Im, 2, 2, "+", "ADDI",	(void(*)())PGXP_CPU_ADDI }
+#define PGXP_Data_ADDIU	{ fOp_CPU_Rt, fOp_CPU_Rs | fOp_Im, 2, 2, "+", "ADDIU",	(void(*)())PGXP_CPU_ADDIU }
+#define PGXP_Data_ANDI	{ fOp_CPU_Rt, fOp_CPU_Rs | fOp_Im, 2, 2, "&", "ANDI",	(void(*)())PGXP_CPU_ANDI }
+#define PGXP_Data_ORI	{ fOp_CPU_Rt, fOp_CPU_Rs | fOp_Im, 2, 2, "|", "ORI",	(void(*)())PGXP_CPU_ORI }
+#define PGXP_Data_XORI	{ fOp_CPU_Rt, fOp_CPU_Rs | fOp_Im, 2, 2, "^", "XORI",	(void(*)())PGXP_CPU_XORI }
+#define PGXP_Data_SLTI	{ fOp_CPU_Rt, fOp_CPU_Rs | fOp_Im, 2, 2, "<", "SLTI",	(void(*)())PGXP_CPU_SLTI }
+#define PGXP_Data_SLTIU	{ fOp_CPU_Rt, fOp_CPU_Rs | fOp_Im, 2, 2, "<", "SLTIU",	(void(*)())PGXP_CPU_SLTIU }
 // Load Upper
-#define PGXP_Data_LUI	{ fOp_Rt, fOp_Im, 1, 1, "<<", "LUI", (void(*)())PGXP_CPU_LUI }
+#define PGXP_Data_LUI	{ fOp_CPU_Rt, fOp_Im, 1, 1, "<<", "LUI", (void(*)())PGXP_CPU_LUI }
 
 // Load/Store
-#define PGXP_Data_LWL	{ fOp_Rt, fOp_Ad, 1, 2, "", "LWL",	(void(*)())PGXP_CPU_LWL }	// 32-bit Loads
-#define PGXP_Data_LW	{ fOp_Rt, fOp_Ad, 1, 2, "", "LW",	(void(*)())PGXP_CPU_LW	}
-#define PGXP_Data_LWR	{ fOp_Rt, fOp_Ad, 1, 2, "", "LWR",	(void(*)())PGXP_CPU_LWR }
-#define PGXP_Data_LH	{ fOp_Rt, fOp_Ad, 1, 2, "", "LH",	(void(*)())PGXP_CPU_LH }	// 16-bit Loads
-#define PGXP_Data_LHU	{ fOp_Rt, fOp_Ad, 1, 2, "", "LHU",	(void(*)())PGXP_CPU_LHU }
-#define PGXP_Data_LB	{ fOp_Rt, fOp_Ad, 1, 2, "", "LB",	(void(*)())PGXP_CPU_LB }	// 8-bit Loads
-#define PGXP_Data_LBU	{ fOp_Rt, fOp_Ad, 1, 2, "", "LBU",	(void(*)())PGXP_CPU_LBU }
-#define PGXP_Data_SWL	{ fOp_Ad, fOp_Rt, 1, 2, "", "SWL",	(void(*)())PGXP_CPU_SWL }	// 32-bit Store
-#define PGXP_Data_SW	{ fOp_Ad, fOp_Rt, 1, 2, "", "SW",	(void(*)())PGXP_CPU_SW }
-#define PGXP_Data_SWR	{ fOp_Ad, fOp_Rt, 1, 2, "", "SWR",	(void(*)())PGXP_CPU_SWR }
-#define PGXP_Data_SH	{ fOp_Ad, fOp_Rt, 1, 2, "", "SH",	(void(*)())PGXP_CPU_SH }	// 16-bit Store
-#define PGXP_Data_SB	{ fOp_Ad, fOp_Rt, 1, 2, "", "SU",	(void(*)())PGXP_CPU_SB }	// 8-bit Store
+#define PGXP_Data_LWL	{ fOp_CPU_Rt, fOp_Ad, 1, 2, "", "LWL",	(void(*)())PGXP_CPU_LWL }	// 32-bit Loads
+#define PGXP_Data_LW	{ fOp_CPU_Rt, fOp_Ad, 1, 2, "", "LW",	(void(*)())PGXP_CPU_LW	}
+#define PGXP_Data_LWR	{ fOp_CPU_Rt, fOp_Ad, 1, 2, "", "LWR",	(void(*)())PGXP_CPU_LWR }
+#define PGXP_Data_LH	{ fOp_CPU_Rt, fOp_Ad, 1, 2, "", "LH",	(void(*)())PGXP_CPU_LH }	// 16-bit Loads
+#define PGXP_Data_LHU	{ fOp_CPU_Rt, fOp_Ad, 1, 2, "", "LHU",	(void(*)())PGXP_CPU_LHU }
+#define PGXP_Data_LB	{ fOp_CPU_Rt, fOp_Ad, 1, 2, "", "LB",	(void(*)())PGXP_CPU_LB }	// 8-bit Loads
+#define PGXP_Data_LBU	{ fOp_CPU_Rt, fOp_Ad, 1, 2, "", "LBU",	(void(*)())PGXP_CPU_LBU }
+#define PGXP_Data_SWL	{ fOp_Ad, fOp_CPU_Rt, 1, 2, "", "SWL",	(void(*)())PGXP_CPU_SWL }	// 32-bit Store
+#define PGXP_Data_SW	{ fOp_Ad, fOp_CPU_Rt, 1, 2, "", "SW",	(void(*)())PGXP_CPU_SW }
+#define PGXP_Data_SWR	{ fOp_Ad, fOp_CPU_Rt, 1, 2, "", "SWR",	(void(*)())PGXP_CPU_SWR }
+#define PGXP_Data_SH	{ fOp_Ad, fOp_CPU_Rt, 1, 2, "", "SH",	(void(*)())PGXP_CPU_SH }	// 16-bit Store
+#define PGXP_Data_SB	{ fOp_Ad, fOp_CPU_Rt, 1, 2, "", "SB",	(void(*)())PGXP_CPU_SB }	// 8-bit Store
+
+// Load/Store GTE
+#define PGXP_Data_LWC2	{ fOp_GTE_Dt, fOp_Ad, 1, 2, "", "LWC2",	(void(*)())PGXP_GTE_LWC2 }	// 32-bit Loads
+#define PGXP_Data_SWC2	{ fOp_Ad, fOp_GTE_Dt, 1, 2, "", "SWC2",	(void(*)())PGXP_GTE_SWC2 }	// 32-bit Store
 
 static PGXP_CPU_OpData PGXP_BSC_LUT[64] = {
 	PGXP_Data_SPECIAL, PGXP_Data_NULL  , PGXP_Data_NULL, PGXP_Data_NULL , PGXP_Data_NULL, PGXP_Data_NULL, PGXP_Data_NULL, PGXP_Data_NULL,
@@ -82,38 +100,38 @@ static PGXP_CPU_OpData PGXP_BSC_LUT[64] = {
 };
 
 // Register Arithmetic
-#define PGXP_Data_ADD	{ fOp_Rd, fOp_Rs | fOp_Rt, 3, 3, "+", "ADD",	(void(*)())PGXP_CPU_ADD }
-#define PGXP_Data_ADDU	{ fOp_Rd, fOp_Rs | fOp_Rt, 3, 3, "+", "ADDU",	(void(*)())PGXP_CPU_ADDU }
-#define PGXP_Data_SUB	{ fOp_Rd, fOp_Rs | fOp_Rt, 3, 3, "+", "SUB",	(void(*)())PGXP_CPU_SUB }
-#define PGXP_Data_SUBU	{ fOp_Rd, fOp_Rs | fOp_Rt, 3, 3, "+", "SUBU",	(void(*)())PGXP_CPU_SUBU }
-#define PGXP_Data_AND	{ fOp_Rd, fOp_Rs | fOp_Rt, 3, 3, "&", "AND",	(void(*)())PGXP_CPU_AND }
-#define PGXP_Data_OR	{ fOp_Rd, fOp_Rs | fOp_Rt, 3, 3, "|", "OR",		(void(*)())PGXP_CPU_OR }
-#define PGXP_Data_XOR	{ fOp_Rd, fOp_Rs | fOp_Rt, 3, 3, "^", "XOR",	(void(*)())PGXP_CPU_XOR }
-#define PGXP_Data_NOR	{ fOp_Rd, fOp_Rs | fOp_Rt, 3, 3, "^", "NOR",	(void(*)())PGXP_CPU_NOR }
-#define PGXP_Data_SLT	{ fOp_Rd, fOp_Rs | fOp_Rt, 3, 3, "<", "SLT",	(void(*)())PGXP_CPU_SLT }
-#define PGXP_Data_SLTU	{ fOp_Rd, fOp_Rs | fOp_Rt, 3, 3, "<", "SLTU",	(void(*)())PGXP_CPU_SLTU }
+#define PGXP_Data_ADD	{ fOp_CPU_Rd, fOp_CPU_Rs | fOp_CPU_Rt, 3, 3, "+", "ADD",	(void(*)())PGXP_CPU_ADD }
+#define PGXP_Data_ADDU	{ fOp_CPU_Rd, fOp_CPU_Rs | fOp_CPU_Rt, 3, 3, "+", "ADDU",	(void(*)())PGXP_CPU_ADDU }
+#define PGXP_Data_SUB	{ fOp_CPU_Rd, fOp_CPU_Rs | fOp_CPU_Rt, 3, 3, "-", "SUB",	(void(*)())PGXP_CPU_SUB }
+#define PGXP_Data_SUBU	{ fOp_CPU_Rd, fOp_CPU_Rs | fOp_CPU_Rt, 3, 3, "-", "SUBU",	(void(*)())PGXP_CPU_SUBU }
+#define PGXP_Data_AND	{ fOp_CPU_Rd, fOp_CPU_Rs | fOp_CPU_Rt, 3, 3, "&", "AND",	(void(*)())PGXP_CPU_AND }
+#define PGXP_Data_OR	{ fOp_CPU_Rd, fOp_CPU_Rs | fOp_CPU_Rt, 3, 3, "|", "OR",		(void(*)())PGXP_CPU_OR }
+#define PGXP_Data_XOR	{ fOp_CPU_Rd, fOp_CPU_Rs | fOp_CPU_Rt, 3, 3, "^", "XOR",	(void(*)())PGXP_CPU_XOR }
+#define PGXP_Data_NOR	{ fOp_CPU_Rd, fOp_CPU_Rs | fOp_CPU_Rt, 3, 3, "^", "NOR",	(void(*)())PGXP_CPU_NOR }
+#define PGXP_Data_SLT	{ fOp_CPU_Rd, fOp_CPU_Rs | fOp_CPU_Rt, 3, 3, "<", "SLT",	(void(*)())PGXP_CPU_SLT }
+#define PGXP_Data_SLTU	{ fOp_CPU_Rd, fOp_CPU_Rs | fOp_CPU_Rt, 3, 3, "<", "SLTU",	(void(*)())PGXP_CPU_SLTU }
 
 // Register mult/div
-#define PGXP_Data_MULT	{ fOp_Hi | fOp_Lo, fOp_Rs | fOp_Rt, 4, 4, "*", "MULT",	(void(*)())PGXP_CPU_MULT }
-#define PGXP_Data_MULTU	{ fOp_Hi | fOp_Lo, fOp_Rs | fOp_Rt, 4, 4, "*", "MULTU",	(void(*)())PGXP_CPU_MULTU }
-#define PGXP_Data_DIV	{ fOp_Hi | fOp_Lo, fOp_Rs | fOp_Rt, 4, 4, "/", "DIV",	(void(*)())PGXP_CPU_DIV }
-#define PGXP_Data_DIVU	{ fOp_Hi | fOp_Lo, fOp_Rs | fOp_Rt, 4, 4, "/", "DIVU",	(void(*)())PGXP_CPU_DIVU }
+#define PGXP_Data_MULT	{ fOp_CPU_Hi | fOp_CPU_Lo, fOp_CPU_Rs | fOp_CPU_Rt, 4, 4, "*", "MULT",	(void(*)())PGXP_CPU_MULT }
+#define PGXP_Data_MULTU	{ fOp_CPU_Hi | fOp_CPU_Lo, fOp_CPU_Rs | fOp_CPU_Rt, 4, 4, "*", "MULTU",	(void(*)())PGXP_CPU_MULTU }
+#define PGXP_Data_DIV	{ fOp_CPU_Hi | fOp_CPU_Lo, fOp_CPU_Rs | fOp_CPU_Rt, 4, 4, "/", "DIV",	(void(*)())PGXP_CPU_DIV }
+#define PGXP_Data_DIVU	{ fOp_CPU_Hi | fOp_CPU_Lo, fOp_CPU_Rs | fOp_CPU_Rt, 4, 4, "/", "DIVU",	(void(*)())PGXP_CPU_DIVU }
 
 // Shift operations (sa)
-#define PGXP_Data_SLL	{ fOp_Rd, fOp_Rt | fOp_Sa, 2, 2, ">>", "SLL",	(void(*)())PGXP_CPU_SLL }
-#define PGXP_Data_SRL	{ fOp_Rd, fOp_Rt | fOp_Sa, 2, 2, "<<", "SRL",	(void(*)())PGXP_CPU_SRL }
-#define PGXP_Data_SRA	{ fOp_Rd, fOp_Rt | fOp_Sa, 2, 2, "<<", "SRA",	(void(*)())PGXP_CPU_SRA }
+#define PGXP_Data_SLL	{ fOp_CPU_Rd, fOp_CPU_Rt | fOp_Sa, 2, 2, ">>", "SLL",	(void(*)())PGXP_CPU_SLL }
+#define PGXP_Data_SRL	{ fOp_CPU_Rd, fOp_CPU_Rt | fOp_Sa, 2, 2, "<<", "SRL",	(void(*)())PGXP_CPU_SRL }
+#define PGXP_Data_SRA	{ fOp_CPU_Rd, fOp_CPU_Rt | fOp_Sa, 2, 2, "<<", "SRA",	(void(*)())PGXP_CPU_SRA }
 
 // Shift operations variable
-#define PGXP_Data_SLLV	{ fOp_Rd, fOp_Rt | fOp_Rs, 3, 3, ">>", "SLLV",	(void(*)())PGXP_CPU_SLLV }
-#define PGXP_Data_SRLV	{ fOp_Rd, fOp_Rt | fOp_Rs, 3, 3, "<<", "SRLV",	(void(*)())PGXP_CPU_SRLV }
-#define PGXP_Data_SRAV	{ fOp_Rd, fOp_Rt | fOp_Rs, 3, 3, "<<", "SRAV",	(void(*)())PGXP_CPU_SRAV }
+#define PGXP_Data_SLLV	{ fOp_CPU_Rd, fOp_CPU_Rt | fOp_CPU_Rs, 3, 3, ">>", "SLLV",	(void(*)())PGXP_CPU_SLLV }
+#define PGXP_Data_SRLV	{ fOp_CPU_Rd, fOp_CPU_Rt | fOp_CPU_Rs, 3, 3, "<<", "SRLV",	(void(*)())PGXP_CPU_SRLV }
+#define PGXP_Data_SRAV	{ fOp_CPU_Rd, fOp_CPU_Rt | fOp_CPU_Rs, 3, 3, "<<", "SRAV",	(void(*)())PGXP_CPU_SRAV }
 
 // Move registers
-#define PGXP_Data_MFHI	{ fOp_Rd, fOp_Hi, 2, 2, "<-", "MFHI",	(void(*)())PGXP_CPU_MFHI }
-#define PGXP_Data_MTHI	{ fOp_Hi, fOp_Rd, 2, 2, "<-", "MTHI",	(void(*)())PGXP_CPU_MTHI }
-#define PGXP_Data_MFLO	{ fOp_Rd, fOp_Lo, 2, 2, "<-", "MFLO",	(void(*)())PGXP_CPU_MFLO }
-#define PGXP_Data_MTLO	{ fOp_Lo, fOp_Rd, 2, 2, "<-", "MFHI",	(void(*)())PGXP_CPU_MTLO }
+#define PGXP_Data_MFHI	{ fOp_CPU_Rd, fOp_CPU_Hi, 2, 2, "<-", "MFHI",	(void(*)())PGXP_CPU_MFHI }
+#define PGXP_Data_MTHI	{ fOp_CPU_Hi, fOp_CPU_Rd, 2, 2, "<-", "MTHI",	(void(*)())PGXP_CPU_MTHI }
+#define PGXP_Data_MFLO	{ fOp_CPU_Rd, fOp_CPU_Lo, 2, 2, "<-", "MFLO",	(void(*)())PGXP_CPU_MFLO }
+#define PGXP_Data_MTLO	{ fOp_CPU_Lo, fOp_CPU_Rd, 2, 2, "<-", "MFHI",	(void(*)())PGXP_CPU_MTLO }
 
 static PGXP_CPU_OpData PGXP_SPC_LUT[64] = {
 	PGXP_Data_SLL , PGXP_Data_NULL, PGXP_Data_SRL , PGXP_Data_SRA , PGXP_Data_SLLV   , PGXP_Data_NULL , PGXP_Data_SRLV, PGXP_Data_SRAV,
@@ -126,28 +144,58 @@ static PGXP_CPU_OpData PGXP_SPC_LUT[64] = {
 	PGXP_Data_NULL, PGXP_Data_NULL, PGXP_Data_NULL, PGXP_Data_NULL, PGXP_Data_NULL   , PGXP_Data_NULL , PGXP_Data_NULL, PGXP_Data_NULL
 };
 
+// GTE transfer registers
+#define PGXP_Data_MFC2	{ fOp_CPU_Rt, fOp_GTE_Dd, 2, 1, "<-", "MFC2",	(void(*)())PGXP_GTE_MFC2 }
+#define PGXP_Data_MTC2	{ fOp_GTE_Dd, fOp_CPU_Rt, 2, 1, "<-", "MTC2",	(void(*)())PGXP_GTE_MTC2 }
+#define PGXP_Data_CFC2	{ fOp_CPU_Rt, fOp_GTE_Cd, 2, 1, "<-", "CFC2",	(void(*)())PGXP_GTE_CFC2 }
+#define PGXP_Data_CTC2	{ fOp_GTE_Cd, fOp_CPU_Rt, 2, 1, "<-", "CTC2",	(void(*)())PGXP_GTE_CTC2 }
+
+static PGXP_CPU_OpData  PGXP_CO2BSC_LUT[32] = {
+	PGXP_Data_MFC2, PGXP_Data_NULL, PGXP_Data_CFC2, PGXP_Data_NULL, PGXP_Data_MTC2, PGXP_Data_NULL, PGXP_Data_CTC2, PGXP_Data_NULL,
+	PGXP_Data_NULL, PGXP_Data_NULL, PGXP_Data_NULL, PGXP_Data_NULL, PGXP_Data_NULL, PGXP_Data_NULL, PGXP_Data_NULL, PGXP_Data_NULL,
+	PGXP_Data_NULL, PGXP_Data_NULL, PGXP_Data_NULL, PGXP_Data_NULL, PGXP_Data_NULL, PGXP_Data_NULL, PGXP_Data_NULL, PGXP_Data_NULL,
+	PGXP_Data_NULL, PGXP_Data_NULL, PGXP_Data_NULL, PGXP_Data_NULL, PGXP_Data_NULL, PGXP_Data_NULL, PGXP_Data_NULL, PGXP_Data_NULL
+};
+
+// CP0 transfer registers
+#define PGXP_Data_MFC0	{ fOp_CPU_Rt, fOp_CP0_Dd, 2, 1, "<-", "MFC0",	(void(*)())PGXP_CP0_MFC0 }
+#define PGXP_Data_MTC0	{ fOp_CP0_Dd, fOp_CPU_Rt, 2, 1, "<-", "MTC0",	(void(*)())PGXP_CP0_MTC0 }
+#define PGXP_Data_CFC0	{ fOp_CPU_Rt, fOp_CP0_Cd, 2, 1, "<-", "CFC0",	(void(*)())PGXP_CP0_CFC0 }
+#define PGXP_Data_CTC0	{ fOp_CP0_Cd, fOp_CPU_Rt, 2, 1, "<-", "CTC0",	(void(*)())PGXP_CP0_CTC0 }
+#define PGXP_Data_RFE	{ 0, 0, 0, 0,"", "RFE", PGXP_CPU_EMPTY }
+
+static PGXP_CPU_OpData PGXP_COP0_LUT[32] = {
+	PGXP_Data_MFC0, PGXP_Data_NULL, PGXP_Data_CFC0, PGXP_Data_NULL, PGXP_Data_MTC0, PGXP_Data_NULL, PGXP_Data_CTC0, PGXP_Data_NULL,
+	PGXP_Data_NULL, PGXP_Data_NULL, PGXP_Data_NULL, PGXP_Data_NULL, PGXP_Data_NULL, PGXP_Data_NULL, PGXP_Data_NULL, PGXP_Data_NULL,
+	PGXP_Data_RFE , PGXP_Data_NULL, PGXP_Data_NULL, PGXP_Data_NULL, PGXP_Data_NULL, PGXP_Data_NULL, PGXP_Data_NULL, PGXP_Data_NULL,
+	PGXP_Data_NULL, PGXP_Data_NULL, PGXP_Data_NULL, PGXP_Data_NULL, PGXP_Data_NULL, PGXP_Data_NULL, PGXP_Data_NULL, PGXP_Data_NULL
+};
+
 PGXP_CPU_OpData GetOpData(u32 instr)
 {
-	PGXP_CPU_OpData pOpData = PGXP_Data_NULL;
+	PGXP_CPU_OpData pOpData = PGXP_Data_ERROR;
 	switch (op(instr))
 	{
 	case 0:
-		pOpData = PGXP_SPC_LUT[func(instr)];
+		if (func(instr) < 64)
+			pOpData = PGXP_SPC_LUT[func(instr)];
 		break;
 	case 1:
 		//pOpData = PGXP_BCOND_LUT[rt(instr)];
 		break;
 	case 16:
-		//pOpData = PGXP_COP0_LUT[rs(instr)];
+		if (rs(instr) < 32)
+			pOpData = PGXP_COP0_LUT[rs(instr)];
 		break;
 	case 18:
-		//if (func(instr) == 1)
-		//	pOpData = PGXP_CO2BSC_LUT[rs(instr)];
+		if ((func(instr) == 0) && (rs(instr) < 32))
+			pOpData = PGXP_CO2BSC_LUT[rs(instr)];
 		//else
 		//	pOpData = PGXP_COP2_LUT[func(instr)];
 		break;
 	default:
-		pOpData = PGXP_BSC_LUT[op(instr)];
+		if(op(instr) < 64)
+			pOpData = PGXP_BSC_LUT[op(instr)];
 		break;
 	}
 
@@ -159,48 +207,83 @@ void PrintOperands(char* szBuffer, u32 instr, u32 flags, const char* szDelim, ps
 	char		szTempBuffer[256];
 	PGXP_value* pReg = NULL;
 	psx_value	psx_reg;
-	char		szOpdName[8];
+	char		szOpdName[16];
 	const char*	szPre = "";
 
 	memset(szTempBuffer, 0, sizeof(szTempBuffer));
-	for (u32 opdIdx = 0; opdIdx < 8; opdIdx++)
+	for (u32 opdIdx = 0; opdIdx < 14; opdIdx++)
 	{
 		u32 flag = 1 << opdIdx;
 
 		// iCB Hack: reorder Rs and Rt for SLLV SRLV and SRAV
 		if ((op(instr) < 8) && (op(instr) > 3))
-			flag = (flag == fOp_Rs) ? fOp_Rt : ((flag == fOp_Rt) ? fOp_Rs : flag);
+			flag = (flag == fOp_CPU_Rs) ? fOp_CPU_Rt : ((flag == fOp_CPU_Rt) ? fOp_CPU_Rs : flag);
 		// /iCB Hack
 
 		if (flags & flag)
 		{
 			switch (flag)
 			{
-			case fOp_Hi:
+			case fOp_CPU_Hi:
 				pReg = &CPU_Hi;
 				sprintf(szOpdName, "Hi");
 				psx_reg = psx_regs[(*regIdx)++];
 				break;
-			case fOp_Lo:
+			case fOp_CPU_Lo:
 				pReg = &CPU_Lo;
 				sprintf(szOpdName, "Lo");
 				psx_reg = psx_regs[(*regIdx)++];
 				break;
-			case fOp_Rd:
+			case fOp_CPU_Rd:
 				pReg = &CPU_reg[rd(instr)];
 				sprintf(szOpdName, "Rd[%d]", rd(instr));
 				psx_reg = psx_regs[(*regIdx)++];
 				break;
-			case fOp_Rs:
+			case fOp_CPU_Rs:
 				pReg = &CPU_reg[rs(instr)];
 				sprintf(szOpdName, "Rs[%d]", rs(instr));
 				psx_reg = psx_regs[(*regIdx)++];
 				break;
-			case fOp_Rt:
+			case fOp_CPU_Rt:
 				pReg = &CPU_reg[rt(instr)];
 				sprintf(szOpdName, "Rt[%d]", rt(instr));
 				psx_reg = psx_regs[(*regIdx)++];
 				break;
+			case fOp_GTE_Dd:
+				pReg = &GTE_data_reg[rd(instr)];
+				sprintf(szOpdName, "GTE_Dd[%d]", rd(instr));
+				psx_reg = psx_regs[(*regIdx)++];
+				break;
+			case fOp_GTE_Dt:
+				pReg = &GTE_data_reg[rt(instr)];
+				sprintf(szOpdName, "GTE_Dt[%d]", rt(instr));
+				psx_reg = psx_regs[(*regIdx)++];
+				break;
+			case fOp_GTE_Cd:
+				pReg = &GTE_ctrl_reg[rd(instr)];
+				sprintf(szOpdName, "GTE_Cd[%d]", rd(instr));
+				psx_reg = psx_regs[(*regIdx)++];
+				break;
+			case fOp_GTE_Ct:
+				pReg = &GTE_ctrl_reg[rt(instr)];
+				sprintf(szOpdName, "GTE_Ct[%d]", rt(instr));
+				psx_reg = psx_regs[(*regIdx)++];
+				break;
+			case fOp_CP0_Dd:
+				pReg = &CP0_reg[rd(instr)];
+				sprintf(szOpdName, "CP0_Dd[%d]", rd(instr));
+				psx_reg = psx_regs[(*regIdx)++];
+				break;
+			case fOp_CP0_Cd:
+				pReg = &CP0_reg[rd(instr)];
+				sprintf(szOpdName, "CP0_Cd[%d]", rd(instr));
+				psx_reg = psx_regs[(*regIdx)++];
+				break;
+			case fOp_Ad:
+				pReg = NULL;
+				sprintf(szOpdName, "Addr");
+				psx_reg = psx_regs[(*regIdx)++];
+				break;
 			case fOp_Sa:
 				pReg = NULL;
 				sprintf(szOpdName, "Sa");
@@ -210,12 +293,7 @@ void PrintOperands(char* szBuffer, u32 instr, u32 flags, const char* szDelim, ps
 				pReg = NULL;
 				sprintf(szOpdName, "Imm");
 				psx_reg.d = imm(instr);
-				break;
-			case fOp_Ad:
-				pReg = NULL;
-				sprintf(szOpdName, "Addr");
-				psx_reg = psx_regs[(*regIdx)++];
-				break;
+				break;	
 			}
 
 			if (pReg)
@@ -225,6 +303,12 @@ void PrintOperands(char* szBuffer, u32 instr, u32 flags, const char* szDelim, ps
 					pReg->value, pReg->x, pReg->y, pReg->z, pReg->count, pReg->valid);
 				strcat(szBuffer, szTempBuffer);
 			}
+			else if(flag == fOp_Ad)
+			{
+				sprintf(szTempBuffer, "%s %s [%x(%d, %d) (%x)] ", szPre, szOpdName,
+					psx_reg.d, psx_reg.sw.l, psx_reg.sw.h, PGXP_ConvertAddress(psx_reg.d));
+				strcat(szBuffer, szTempBuffer);
+			}
 			else
 			{
 				sprintf(szTempBuffer, "%s %s [%x(%d, %d)] ", szPre, szOpdName,
@@ -239,7 +323,8 @@ void PrintOperands(char* szBuffer, u32 instr, u32 flags, const char* szDelim, ps
 
 void PGXP_CPU_DebugOutput(u32 instr, u32 numOps, u32 op1, u32 op2, u32 op3, u32 op4)
 {
-	char szBuffer[512];
+	char szOutputBuffer[256];
+	char szInputBuffer[512];
 	PGXP_CPU_OpData opData = GetOpData(instr);
 	psx_value psx_regs[4];
 	u32 regIdx = 0;
@@ -249,66 +334,109 @@ void PGXP_CPU_DebugOutput(u32 instr, u32 numOps, u32 op1, u32 op2, u32 op3, u32
 	psx_regs[3].d = op4;
 
 	// iCB Hack: Switch operands around for store functions
-	if ((op(instr) >= 40) && (op(instr) < 48))
+	if ((op(instr) >= 40)&& (op(instr) != 50))
 	{
 		psx_regs[0].d = op2;
 		psx_regs[1].d = op1;
 	}
+
+	// Hack: duplicate psx register data for GTE register movement funcs
+	if ((op(instr) == 18) && (func(instr) == 0))
+		psx_regs[1] = psx_regs[0];
+
 	// /iCB Hack
 
-	if (!pgxp_debug)
-		return;
+	// reset buffers
+	if (pgxp_debug)
+	{
+		memset(szInputBuffer, 0, sizeof(szInputBuffer));
+		memset(szOutputBuffer, 0, sizeof(szOutputBuffer));
+
+		// skip output arguments
+		for (u32 opdIdx = 0; opdIdx < 12; opdIdx++)
+		{
+			if (opData.OutputFlags & (1 << opdIdx))
+				regIdx++;
+		}
+
+		// Print inputs
+		PrintOperands(szInputBuffer, instr, opData.InputFlags, opData.szOpString, psx_regs, &regIdx);
+	}
+
+	// Call function
+	if (numOps != opData.numArgs)
+		PGXP_CPU_ERROR();
+
+	switch (numOps)
+	{
+	case 0:
+		((void(*)(u32))opData.funcPtr)(instr);
+		break;
+	case 1:
+		((void(*)(u32, u32))opData.funcPtr)(instr, op1);
+		break;
+	case 2:
+		((void(*)(u32, u32, u32))opData.funcPtr)(instr, op1, op2);
+		break;
+	case 3:
+		((void(*)(u32, u32, u32, u32))opData.funcPtr)(instr, op1, op2, op3);
+		break;
+	case 4:
+		((void(*)(u32, u32, u32, u32, u32))opData.funcPtr)(instr, op1, op2, op3, op4);
+		break;
+	}
 
-	memset(szBuffer, 0, sizeof(szBuffer));
 	// Print operation details
-	sprintf(szBuffer, "%s %x %x: ", opData.szOpName, op(instr), func(instr));
-	// Print outputs
-	PrintOperands(szBuffer, instr, opData.OutputFlags, "/", psx_regs, &regIdx);
-	strcat(szBuffer, "= ");
-	// Print inputs
-	PrintOperands(szBuffer, instr, opData.InputFlags, opData.szOpString, psx_regs, &regIdx);
+	if (pgxp_debug)
+	{
+		sprintf(szOutputBuffer, "%s %x %x: ", opData.szOpName, op(instr), func(instr));
+		// Print outputs
+		regIdx = 0;
+		PrintOperands(szOutputBuffer, instr, opData.OutputFlags, "/", psx_regs, &regIdx);
+		strcat(szOutputBuffer, "=");
 
 #ifdef GTE_LOG
-	GTE_LOG("PGXP_Trace: %s |", szBuffer);
+		GTE_LOG("PGXP_Trace: %s %s|", szOutputBuffer, szInputBuffer);
 #endif
+	}
 }
 
-void PGXP_psxTrace(u32 instr)
+void PGXP_psxTraceOp(u32 instr)
 {
-	PGXP_CPU_OpData opData = GetOpData(instr);
-	if (opData.funcPtr && (opData.numArgs == 0))
-		((void(*)(u32))opData.funcPtr)(instr);
+	//PGXP_CPU_OpData opData = GetOpData(instr);
+	//if (opData.funcPtr && (opData.numArgs == 0))
+	//	((void(*)(u32))opData.funcPtr)(instr);
 	PGXP_CPU_DebugOutput(instr, 0, 0, 0, 0, 0);
 }
 
 void PGXP_psxTraceOp1(u32 instr, u32 op1)
 {
-	PGXP_CPU_OpData opData = GetOpData(instr);
-	if (opData.funcPtr && (opData.numArgs == 1))
-		((void(*)(u32, u32))opData.funcPtr)(instr, op1);
+	//PGXP_CPU_OpData opData = GetOpData(instr);
+	//if (opData.funcPtr && (opData.numArgs == 1))
+	//	((void(*)(u32, u32))opData.funcPtr)(instr, op1);
 	PGXP_CPU_DebugOutput(instr, 1, op1, 0, 0, 0);
 }
 
 void PGXP_psxTraceOp2(u32 instr, u32 op1, u32 op2)
 {
-	PGXP_CPU_OpData opData = GetOpData(instr);
-	if (opData.funcPtr && (opData.numArgs == 2))
-		((void(*)(u32, u32, u32))opData.funcPtr)(instr, op1, op2);
+	//PGXP_CPU_OpData opData = GetOpData(instr);
+	//if (opData.funcPtr && (opData.numArgs == 2))
+	//	((void(*)(u32, u32, u32))opData.funcPtr)(instr, op1, op2);
 	PGXP_CPU_DebugOutput(instr, 2, op1, op2, 0, 0);
 }
 
 void PGXP_psxTraceOp3(u32 instr, u32 op1, u32 op2, u32 op3)
 {
-	PGXP_CPU_OpData opData = GetOpData(instr);
-	if (opData.funcPtr && (opData.numArgs == 3))
-		((void(*)(u32, u32, u32, u32))opData.funcPtr)(instr, op1, op2, op3);
+	//PGXP_CPU_OpData opData = GetOpData(instr);
+	//if (opData.funcPtr && (opData.numArgs == 3))
+	//	((void(*)(u32, u32, u32, u32))opData.funcPtr)(instr, op1, op2, op3);
 	PGXP_CPU_DebugOutput(instr, 3, op1, op2, op3, 0);
 }
 
 void PGXP_psxTraceOp4(u32 instr, u32 op1, u32 op2, u32 op3, u32 op4)
 {
-	PGXP_CPU_OpData opData = GetOpData(instr);
-	if (opData.funcPtr && (opData.numArgs == 4))
-		((void(*)(u32, u32, u32, u32, u32))opData.funcPtr)(instr, op1, op2, op3, op4);
+	//PGXP_CPU_OpData opData = GetOpData(instr);
+	//if (opData.funcPtr && (opData.numArgs == 4))
+	//	((void(*)(u32, u32, u32, u32, u32))opData.funcPtr)(instr, op1, op2, op3, op4);
 	PGXP_CPU_DebugOutput(instr, 4, op1, op2, op3, op4);
 }
\ No newline at end of file
diff --git a/libpcsxcore/pgxp_debug.h b/libpcsxcore/pgxp_debug.h
index caea2b67..1c9cb79e 100644
--- a/libpcsxcore/pgxp_debug.h
+++ b/libpcsxcore/pgxp_debug.h
@@ -30,8 +30,10 @@
 
 #include "psxcommon.h"
 
+#define PGXP_CPU_DEBUG
+
 // Debug wrappers
-void	PGXP_psxTrace(u32 code);
+void	PGXP_psxTraceOp(u32 code);
 void	PGXP_psxTraceOp1(u32 code, u32 op1);
 void	PGXP_psxTraceOp2(u32 code, u32 op1, u32 op2);
 void	PGXP_psxTraceOp3(u32 code, u32 op1, u32 op2, u32 op3);
diff --git a/libpcsxcore/pgxp_gte.c b/libpcsxcore/pgxp_gte.c
index 5fa021c8..de5f7a37 100644
--- a/libpcsxcore/pgxp_gte.c
+++ b/libpcsxcore/pgxp_gte.c
@@ -35,19 +35,37 @@
 #include "psxmem.h"

 #include "r3000a.h"

 

-PGXP_value GTE_reg[32];

 

-#define SX0 (GTE_reg[ 12 ].x)

-#define SY0 (GTE_reg[ 12 ].y)

-#define SX1 (GTE_reg[ 13 ].x)

-#define SY1 (GTE_reg[ 13 ].y)

-#define SX2 (GTE_reg[ 14 ].x)

-#define SY2 (GTE_reg[ 14 ].y)

+// GTE registers

+PGXP_value GTE_data_reg_mem[32];

+PGXP_value GTE_ctrl_reg_mem[32];

 

-#define SXY0 (GTE_reg[ 12 ])

-#define SXY1 (GTE_reg[ 13 ])

-#define SXY2 (GTE_reg[ 14 ])

-#define SXYP (GTE_reg[ 15 ])

+

+PGXP_value* GTE_data_reg = GTE_data_reg_mem;

+PGXP_value* GTE_ctrl_reg = GTE_ctrl_reg_mem;

+

+

+

+// Instruction register decoding

+#define op(_instr)		(_instr >> 26)			// The op part of the instruction register 

+#define func(_instr)	((_instr) & 0x3F)		// The funct part of the instruction register 

+#define sa(_instr)		((_instr >>  6) & 0x1F) // The sa part of the instruction register

+#define rd(_instr)		((_instr >> 11) & 0x1F)	// The rd part of the instruction register 

+#define rt(_instr)		((_instr >> 16) & 0x1F)	// The rt part of the instruction register 

+#define rs(_instr)		((_instr >> 21) & 0x1F)	// The rs part of the instruction register 

+#define imm(_instr)		(_instr & 0xFFFF)		// The immediate part of the instruction register

+

+#define SX0 (GTE_data_reg[ 12 ].x)

+#define SY0 (GTE_data_reg[ 12 ].y)

+#define SX1 (GTE_data_reg[ 13 ].x)

+#define SY1 (GTE_data_reg[ 13 ].y)

+#define SX2 (GTE_data_reg[ 14 ].x)

+#define SY2 (GTE_data_reg[ 14 ].y)

+

+#define SXY0 (GTE_data_reg[ 12 ])

+#define SXY1 (GTE_data_reg[ 13 ])

+#define SXY2 (GTE_data_reg[ 14 ])

+#define SXYP (GTE_data_reg[ 15 ])

 

 void PGXP_pushSXYZ2f(float _x, float _y, float _z, unsigned int _v)

 {

@@ -82,7 +100,8 @@ void PGXP_pushSXYZ2s(s64 _x, s64 _y, s64 _z, u32 v)
 	float fy = (float)(_y) / (float)(1 << 16);

 	float fz = (float)(_z);

 

-	PGXP_pushSXYZ2f(fx, fy, fz, v);

+	if(Config.PGXP_GTE)

+		PGXP_pushSXYZ2f(fx, fy, fz, v);

 }

 

 #define VX(n) (psxRegs.CP2D.p[ n << 1 ].sw.l)

@@ -156,7 +175,7 @@ void PGXP_RTPS(u32 _n, u32 _v)
 

 int PGXP_NLCIP_valid()

 {

-	if (SXY0.valid && SXY1.valid && SXY2.valid)

+	if (SXY0.valid && SXY1.valid && SXY2.valid && Config.PGXP_GTE && (Config.PGXP_Mode > 0))

 		return 1;

 	return 0;

 }

@@ -190,11 +209,11 @@ static PGXP_value PGXP_MFC2_int(u32 reg)
 	switch (reg) 

 	{

 	case 15:

-		GTE_reg[reg] = SXYP = SXY2;

+		GTE_data_reg[reg] = SXYP = SXY2;

 		break;

 	}

 

-	return GTE_reg[reg];

+	return GTE_data_reg[reg];

 }

 

 

@@ -214,63 +233,91 @@ static void PGXP_MTC2_int(PGXP_value value, u32 reg)
 			return;

 	}

 

-	GTE_reg[reg] = value;

+	GTE_data_reg[reg] = value;

 }

 

-// copy GTE data reg to GPR reg (MFC2)

-void PGXP_MFC2(u32 gpr, u32 gtr, u32 value)

-{

-	if (!gpr) return;

-#ifdef GTE_LOG

-	GTE_LOG("PGXP_MFC2 [%x]<-[%x] %x (%u %u)|", gpr, gtr, value, GTE_reg[gtr].valid, GTE_reg[gtr].count);

-#endif

+////////////////////////////////////

+// Data transfer tracking

+////////////////////////////////////

+

+void MFC2(int reg) {

+	psx_value val;

+	val.d = GTE_data_reg[reg].value;

+	switch (reg) {

+	case 1:

+	case 3:

+	case 5:

+	case 8:

+	case 9:

+	case 10:

+	case 11:

+		GTE_data_reg[reg].value = (s32)val.sw.l;

+		GTE_data_reg[reg].y = 0.f;

+		break;

+

+	case 7:

+	case 16:

+	case 17:

+	case 18:

+	case 19:

+		GTE_data_reg[reg].value = (u32)val.w.l;

+		GTE_data_reg[reg].y = 0.f;

+		break;

 

-	Validate(&GTE_reg[gtr], value);

-	CPU_reg[gpr] = GTE_reg[gtr];

+	case 15:

+		GTE_data_reg[reg] = SXY2;

+		break;

+

+	case 28:

+	case 29:

+	//	psxRegs.CP2D.p[reg].d = LIM(IR1 >> 7, 0x1f, 0, 0) | (LIM(IR2 >> 7, 0x1f, 0, 0) << 5) | (LIM(IR3 >> 7, 0x1f, 0, 0) << 10);

+		break;

+	}

 }

 

-// copy GPR reg to GTE data reg (MTC2)

-void PGXP_MTC2(u32 gpr, u32 gtr, u32 value)

+void PGXP_GTE_MFC2(u32 instr, u32 rdVal)

 {

-#ifdef GTE_LOG

-	GTE_LOG("PGXP_MTC2 [%x]->[%x] %x (%u %u)|", gpr, gtr, value, CPU_reg[gpr].valid, CPU_reg[gpr].count);

-#endif

-	Validate(&CPU_reg[gpr], value);

-	PGXP_MTC2_int(CPU_reg[gpr], gtr);

+	// CPU[Rt] = GTE_D[Rd]

+	Validate(&GTE_data_reg[rd(instr)], rdVal);

+	//MFC2(rd(instr));

+	CPU_reg[rt(instr)] = GTE_data_reg[rd(instr)];

 }

 

-// copy memory to GTE reg

-void PGXP_LWC2(u32 addr, u32 gtr, u32 value)

+void PGXP_GTE_MTC2(u32 instr, u32 rtVal)

 {

-	PGXP_value val;

-	ValidateAndCopyMem(&val, addr, value);

-#ifdef GTE_LOG

-	PGXP_value* pp = ReadMem(addr);

-	PGXP_value p;

-	low_value temp;

-	temp.word = value;

-

-	p.x = p.y = p.valid = 0;

-

-	if (pp)

-		p = *pp;

+	// GTE_D[Rd] = CPU[Rt]

+	Validate(&CPU_reg[rt(instr)], rtVal);

+	PGXP_MTC2_int(CPU_reg[rt(instr)], rd(instr));

+}

 

-	GTE_LOG("PGXP_LWC2 %x [%x] %x (%d, %d) (%f, %f) %u %u|", addr, gtr, value, temp.x, temp.y, p.x, p.y, p.valid, p.count);

-#endif

-	PGXP_MTC2_int(val, gtr);

+void PGXP_GTE_CFC2(u32 instr, u32 rdVal)

+{

+	// CPU[Rt] = GTE_C[Rd]

+	Validate(&GTE_ctrl_reg[rd(instr)], rdVal);

+	CPU_reg[rt(instr)] = GTE_ctrl_reg[rd(instr)];

 }

 

-//copy GTE reg to memory

-void PGXP_SWC2(u32 addr, u32 gtr, u32 value)

+void PGXP_GTE_CTC2(u32 instr, u32 rtVal)

 {

-#ifdef GTE_LOG

-	low_value temp;

-	temp.word = value;

+	// GTE_C[Rd] = CPU[Rt]

+	Validate(&CPU_reg[rt(instr)], rtVal);

+	GTE_ctrl_reg[rd(instr)] = CPU_reg[rt(instr)];

+}

 

-//	if (PGXP_compareXY(GTE_reg[gtr], value))

-		GTE_LOG("PGXP_SWC2 %x [%x] %x (%d, %d) (%f, %f) %u %u|", addr, gtr, value, temp.x, temp.y, GTE_reg[gtr].x, GTE_reg[gtr].y, GTE_reg[gtr].valid, GTE_reg[gtr].count);

-#endif

-	Validate(&GTE_reg[gtr], value);

-	WriteMem(&GTE_reg[gtr], addr);

+////////////////////////////////////

+// Memory Access

+////////////////////////////////////

+void	PGXP_GTE_LWC2(u32 instr, u32 rtVal, u32 addr)

+{

+	// GTE_D[Rt] = Mem[addr]

+	PGXP_value val;

+	ValidateAndCopyMem(&val, addr, rtVal);

+	PGXP_MTC2_int(val, rt(instr));

 }

 

+void	PGXP_GTE_SWC2(u32 instr, u32 rtVal, u32 addr)

+{

+	//  Mem[addr] = GTE_D[Rt]

+	Validate(&GTE_data_reg[rt(instr)], rtVal);

+	WriteMem(&GTE_data_reg[rt(instr)], addr);

+}

diff --git a/libpcsxcore/pgxp_gte.h b/libpcsxcore/pgxp_gte.h
index 9df36b19..4b628026 100644
--- a/libpcsxcore/pgxp_gte.h
+++ b/libpcsxcore/pgxp_gte.h
@@ -30,6 +30,12 @@
 

 #include "psxcommon.h"

 

+struct PGXP_value_Tag;

+typedef struct PGXP_value_Tag PGXP_value;

+

+extern PGXP_value* GTE_data_reg;

+extern PGXP_value* GTE_ctrl_reg;

+

 // -- GTE functions

 // Transforms

 void	PGXP_pushSXYZ2f(float _x, float _y, float _z, unsigned int _v);

@@ -41,10 +47,13 @@ int		PGXP_NLCIP_valid();
 float	PGXP_NCLIP();

 

 // Data transfer tracking

-void	PGXP_MFC2(u32 gpr, u32 gtr, u32 value);		// copy GTE reg to GPR reg (MFC2)

-void	PGXP_MTC2(u32 gpr, u32 gtr, u32 value);		// copy GPR reg to GTR reg (MTC2)

-void	PGXP_LWC2(u32 addr, u32 gtr, u32 value);	// copy memory to GTE reg

-void	PGXP_SWC2(u32 addr, u32 gtr, u32 value);	// copy GTE reg to memory

+void	PGXP_GTE_MFC2(u32 instr, u32 rdVal);		// copy GTE data reg to GPR reg (MFC2)

+void	PGXP_GTE_MTC2(u32 instr, u32 rtVal);		// copy GPR reg to GTE data reg (MTC2)

+void	PGXP_GTE_CFC2(u32 instr, u32 rdVal);		// copy GTE ctrl reg to GPR reg (CFC2)

+void	PGXP_GTE_CTC2(u32 instr, u32 rtVal);		// copy GPR reg to GTE ctrl reg (CTC2)

+// Memory Access

+void	PGXP_GTE_LWC2(u32 instr, u32 rtVal, u32 addr);	// copy memory to GTE reg

+void	PGXP_GTE_SWC2(u32 instr, u32 rtVal, u32 addr);	// copy GTE reg to memory

 

 #ifndef max

 #   define max(a, b) ((a) > (b) ? (a) : (b))

diff --git a/libpcsxcore/pgxp_mem.c b/libpcsxcore/pgxp_mem.c
index 4dfb4bd5..6aa3f1f2 100644
--- a/libpcsxcore/pgxp_mem.c
+++ b/libpcsxcore/pgxp_mem.c
@@ -14,7 +14,7 @@ void PGXP_Init()
 
 char* PGXP_GetMem()
 {
-	return Config.PGXP_GTE ? (char*)(Mem) : NULL;
+	return (char*)(Mem); // Config.PGXP_GTE ? (char*)(Mem) : NULL;
 }
 
 /*  Playstation Memory Map (from Playstation doc by Joshua Walker)
diff --git a/libpcsxcore/pgxp_value.c b/libpcsxcore/pgxp_value.c
new file mode 100644
index 00000000..5d29097d
--- /dev/null
+++ b/libpcsxcore/pgxp_value.c
@@ -0,0 +1,28 @@
+#include "pgxp_value.h"
+
+
+void MakeValid(PGXP_value *pV, u32 psxV)
+{
+	psx_value psx;
+	psx.d = psxV;
+	if (!pV->valid)
+	{
+		pV->x = psx.sw.l;
+		pV->y = psx.sw.h;
+		pV->z = 1.f;
+		pV->valid = 1;
+		pV->value = psx.d;
+	}
+}
+
+void Validate(PGXP_value *pV, u32 psxV)
+{
+	// assume pV is not NULL
+	pV->valid = (pV->valid) && (pV->value == psxV);
+}
+
+void MaskValidate(PGXP_value *pV, u32 psxV, u32 mask)
+{
+	// assume pV is not NULL
+	pV->valid = (pV->valid) && ((pV->value & mask) == (psxV & mask));
+}
\ No newline at end of file
diff --git a/libpcsxcore/pgxp_value.h b/libpcsxcore/pgxp_value.h
index 09bd8925..4dad4d20 100644
--- a/libpcsxcore/pgxp_value.h
+++ b/libpcsxcore/pgxp_value.h
@@ -62,8 +62,14 @@ typedef struct PGXP_value_Tag
 
 typedef enum
 {
-	INVALID_ADDRESS = (1 << 1),
-} PGXP_value_flags;
+	UNINITIALISED		= 0,
+	INVALID_PSX_VALUE	= 1,
+	INVALID_ADDRESS		= 2,
+	INVALID_BITWISE_OP	= 3,
+	DIVIDE_BY_ZERO		= 4,
+	INVALID_8BIT_LOAD	= 5,
+	INVALID_8BIT_STORE	= 6
+} PGXP_error_states;
 
 typedef enum
 {
@@ -73,30 +79,10 @@ typedef enum
 static const PGXP_value PGXP_value_invalid_address = { 0.f, 0.f, 0.f, 0, 0, 0, INVALID_ADDRESS, 0, 0 };
 static const PGXP_value PGXP_value_zero = { 0.f, 0.f, 0.f, 0, 0, 1, 0, 0, 0 };
 
-inline void MakeValid(PGXP_value *pV, u32 psxV)
-{
-	psx_value psx;
-	psx.d = psxV;
-	if (!pV->valid)
-	{
-		pV->x = (float)psx.sw.l;
-		pV->y = (float)psx.sw.h;
-		pV->valid = 1;
-		pV->value = psx.d;
-	}
-}
+void MakeValid(PGXP_value *pV, u32 psxV);
+void Validate(PGXP_value *pV, u32 psxV);
+void MaskValidate(PGXP_value *pV, u32 psxV, u32 mask);
 
-inline void Validate(PGXP_value *pV, u32 psxV)
-{
-	// assume pV is not NULL
-	pV->valid = (pV->valid) && (pV->value == psxV);
-}
-
-inline void MaskValidate(PGXP_value *pV, u32 psxV, u32 mask)
-{
-	// assume pV is not NULL
-	pV->valid = (pV->valid) && ((pV->value & mask) == (psxV & mask));
-}
 
 typedef union
 {
diff --git a/libpcsxcore/psxcommon.c b/libpcsxcore/psxcommon.c
index a60aa48b..ff846a11 100755
--- a/libpcsxcore/psxcommon.c
+++ b/libpcsxcore/psxcommon.c
@@ -38,7 +38,9 @@ u8 vblank_count_hideafter=0;
 u32 PsxClockSpeed = 33868800;
 
 int EmuInit() {
-	return psxInit();
+	int ret = psxInit();
+	EmuSetPGXPMode(Config.PGXP_Mode);
+	return ret;
 }
 
 void EmuReset() {
@@ -78,6 +80,11 @@ void EmuUpdate() {
 	}
 }
 
+void EmuSetPGXPMode(u32 pgxpMode)
+{
+	psxSetPGXPMode(pgxpMode);
+}
+
 void __Log(char *fmt, ...) {
 	va_list list;
 #ifdef LOG_STDOUT
diff --git a/libpcsxcore/psxcommon.h b/libpcsxcore/psxcommon.h
index 894b1a31..d9cf2bdb 100755
--- a/libpcsxcore/psxcommon.h
+++ b/libpcsxcore/psxcommon.h
@@ -171,6 +171,7 @@ typedef struct {
 	boolean PGXP_GTE;
 	boolean PGXP_Cache;
 	boolean PGXP_Texture;
+	u32		PGXP_Mode;
 #ifdef _WIN32
 	char Lang[256];
 #endif
@@ -215,6 +216,7 @@ int EmuInit();
 void EmuReset();
 void EmuShutdown();
 void EmuUpdate();
+void EmuSetPGXPMode(u32 pgxpMode);
 
 #ifdef __cplusplus
 }
diff --git a/libpcsxcore/psxinterpreter.c b/libpcsxcore/psxinterpreter.c
index e49c88bf..26d9f825 100755
--- a/libpcsxcore/psxinterpreter.c
+++ b/libpcsxcore/psxinterpreter.c
@@ -25,6 +25,9 @@
 #include "r3000a.h"
 #include "gte.h"
 #include "psxhle.h"
+#include "pgxp_debug.h"
+#include "pgxp_cpu.h"
+#include "pgxp_gte.h"
 
 static int branch = 0;
 static int branch2 = 0;
@@ -48,13 +51,65 @@ void (*psxCP0[32])();
 void (*psxCP2[64])();
 void (*psxCP2BSC[32])();
 
+/// PGXP function tables
+static void(*pgxpPsxBSC[64])();
+static void(*pgxpPsxSPC[64])();
+static void(*pgxpPsxCP0[32])();
+static void(*pgxpPsxCP2BSC[32])();
+
+static void(*pgxpPsxBSCMem[64])();
+///
+
+static void(**pPsxBSC)() = psxBSC;
+static void(**pPsxSPC)() = psxSPC;
+static void(**pPsxREG)() = psxREG;
+static void(**pPsxCP0)() = psxCP0;
+static void(**pPsxCP2)() = psxCP2;
+static void(**pPsxCP2BSC)() = psxCP2BSC;
+
+
+static void intReset();
+void intSetPGXPMode(u32 pgxpMode)
+{
+	switch (pgxpMode)
+	{
+	case 0: //PGXP_MODE_DISABLED:
+		pPsxBSC		= psxBSC;
+		pPsxSPC		= psxSPC;
+		pPsxREG		= psxREG;
+		pPsxCP0		= psxCP0;
+		pPsxCP2		= psxCP2;
+		pPsxCP2BSC	= psxCP2BSC;
+		break;
+	case 1: //PGXP_MODE_MEM:
+		pPsxBSC		= pgxpPsxBSCMem;
+		pPsxSPC		= psxSPC;
+		pPsxREG		= psxREG;
+		pPsxCP0		= pgxpPsxCP0;
+		pPsxCP2		= psxCP2;
+		pPsxCP2BSC	= pgxpPsxCP2BSC;
+		break;
+	case 2: //PGXP_MODE_FULL:
+		pPsxBSC		= pgxpPsxBSC;
+		pPsxSPC		= pgxpPsxSPC;
+		pPsxREG		= psxREG;
+		pPsxCP0		= pgxpPsxCP0;
+		pPsxCP2		= psxCP2;
+		pPsxCP2BSC	= pgxpPsxCP2BSC;
+		break;
+	}
+
+	// reset to ensure new func tables are used
+	intReset();
+}
+
 static void delayRead(int reg, u32 bpc) {
 	u32 rold, rnew;
 
 //	SysPrintf("delayRead at %x!\n", psxRegs.pc);
 
 	rold = psxRegs.GPR.r[reg];
-	psxBSC[psxRegs.code >> 26](); // branch delay load
+	pPsxBSC[psxRegs.code >> 26](); // branch delay load
 	rnew = psxRegs.GPR.r[reg];
 
 	psxRegs.pc = bpc;
@@ -77,7 +132,7 @@ static void delayWrite(int reg, u32 bpc) {
 
 	// no changes from normal behavior
 
-	psxBSC[psxRegs.code >> 26]();
+	pPsxBSC[psxRegs.code >> 26]();
 
 	branch = 0;
 	psxRegs.pc = bpc;
@@ -279,7 +334,7 @@ void psxDelayTest(int reg, u32 bpc) {
 		case 3:
 			delayWrite(reg, bpc); return;
 	}
-	psxBSC[psxRegs.code >> 26]();
+	pPsxBSC[psxRegs.code >> 26]();
 
 	branch = 0;
 	psxRegs.pc = bpc;
@@ -464,7 +519,7 @@ static __inline void doBranch(u32 tar) {
 			break;
 	}
 
-	psxBSC[psxRegs.code >> 26]();
+	pPsxBSC[psxRegs.code >> 26]();
 
 	branch = 0;
 	psxRegs.pc = branchPC;
@@ -977,26 +1032,26 @@ void psxNULL() {
 }
 
 void psxSPECIAL() {
-	psxSPC[_Funct_]();
+	pPsxSPC[_Funct_]();
 }
 
 void psxREGIMM() {
-	psxREG[_Rt_]();
+	pPsxREG[_Rt_]();
 }
 
 void psxCOP0() {
-	psxCP0[_Rs_]();
+	pPsxCP0[_Rs_]();
 }
 
 void psxCOP2() {
 	if ((psxRegs.CP0.n.Status & 0x40000000) == 0 )
 		return;
 
-	psxCP2[_Funct_]();
+	pPsxCP2[_Funct_]();
 }
 
 void psxBASIC() {
-	psxCP2BSC[_Rs_]();
+	pPsxCP2BSC[_Rs_]();
 }
 
 void psxHLE() {
@@ -1059,6 +1114,57 @@ void (*psxCP2BSC[32])() = {
 	psxNULL, psxNULL, psxNULL, psxNULL, psxNULL, psxNULL, psxNULL, psxNULL
 };
 
+#include "psxinterpreter_pgxp.h"
+
+// Trace all functions using PGXP
+static void(*pgxpPsxBSC[64])() = {
+	psxSPECIAL, psxREGIMM, psxJ   , psxJAL  , psxBEQ , psxBNE , psxBLEZ, psxBGTZ,
+	pgxpPsxADDI   , pgxpPsxADDIU , pgxpPsxSLTI, pgxpPsxSLTIU, pgxpPsxANDI, pgxpPsxORI , pgxpPsxXORI, pgxpPsxLUI ,
+	psxCOP0   , psxNULL  , psxCOP2, psxNULL , psxNULL, psxNULL, psxNULL, psxNULL,
+	psxNULL   , psxNULL  , psxNULL, psxNULL , psxNULL, psxNULL, psxNULL, psxNULL,
+	pgxpPsxLB     , pgxpPsxLH    , pgxpPsxLWL , pgxpPsxLW   , pgxpPsxLBU , pgxpPsxLHU , pgxpPsxLWR , pgxpPsxNULL,
+	pgxpPsxSB     , pgxpPsxSH    , pgxpPsxSWL , pgxpPsxSW   , pgxpPsxNULL, pgxpPsxNULL, pgxpPsxSWR , pgxpPsxNULL,
+	psxNULL   , psxNULL  , pgxpPsxLWC2, psxNULL , psxNULL, psxNULL, psxNULL, psxNULL,
+	psxNULL   , psxNULL  , pgxpPsxSWC2, psxHLE  , psxNULL, psxNULL, psxNULL, psxNULL
+};
+
+static void(*pgxpPsxSPC[64])() = {
+	pgxpPsxSLL , pgxpPsxNULL, pgxpPsxSRL , pgxpPsxSRA , pgxpPsxSLLV   , pgxpPsxNULL , pgxpPsxSRLV, pgxpPsxSRAV,
+	psxJR  , psxJALR, psxNULL, psxNULL, psxSYSCALL, psxBREAK, psxNULL, psxNULL,
+	pgxpPsxMFHI, pgxpPsxMTHI, pgxpPsxMFLO, pgxpPsxMTLO, pgxpPsxNULL   , pgxpPsxNULL , pgxpPsxNULL, pgxpPsxNULL,
+	pgxpPsxMULT, pgxpPsxMULTU, pgxpPsxDIV, pgxpPsxDIVU, pgxpPsxNULL   , pgxpPsxNULL , pgxpPsxNULL, pgxpPsxNULL,
+	pgxpPsxADD , pgxpPsxADDU, pgxpPsxSUB , pgxpPsxSUBU, pgxpPsxAND    , pgxpPsxOR   , pgxpPsxXOR , pgxpPsxNOR ,
+	pgxpPsxNULL, pgxpPsxNULL, pgxpPsxSLT , pgxpPsxSLTU, pgxpPsxNULL   , pgxpPsxNULL , pgxpPsxNULL, pgxpPsxNULL,
+	pgxpPsxNULL, pgxpPsxNULL, pgxpPsxNULL, pgxpPsxNULL, pgxpPsxNULL   , pgxpPsxNULL , pgxpPsxNULL, pgxpPsxNULL,
+	pgxpPsxNULL, pgxpPsxNULL, pgxpPsxNULL, pgxpPsxNULL, pgxpPsxNULL   , pgxpPsxNULL , pgxpPsxNULL, pgxpPsxNULL
+};
+
+static void(*pgxpPsxCP0[32])() = {
+	pgxpPsxMFC0, pgxpPsxNULL, pgxpPsxCFC0, pgxpPsxNULL, pgxpPsxMTC0, pgxpPsxNULL, pgxpPsxCTC0, pgxpPsxNULL,
+	pgxpPsxNULL, pgxpPsxNULL, pgxpPsxNULL, pgxpPsxNULL, pgxpPsxNULL, pgxpPsxNULL, pgxpPsxNULL, pgxpPsxNULL,
+	pgxpPsxRFE , pgxpPsxNULL, pgxpPsxNULL, pgxpPsxNULL, pgxpPsxNULL, pgxpPsxNULL, pgxpPsxNULL, pgxpPsxNULL,
+	pgxpPsxNULL, pgxpPsxNULL, pgxpPsxNULL, pgxpPsxNULL, pgxpPsxNULL, pgxpPsxNULL, pgxpPsxNULL, pgxpPsxNULL
+};
+
+static void(*pgxpPsxCP2BSC[32])() = {
+	pgxpPsxMFC2, pgxpPsxNULL, pgxpPsxCFC2, pgxpPsxNULL, pgxpPsxMTC2, pgxpPsxNULL, pgxpPsxCTC2, pgxpPsxNULL,
+	pgxpPsxNULL, pgxpPsxNULL, pgxpPsxNULL, pgxpPsxNULL, pgxpPsxNULL, pgxpPsxNULL, pgxpPsxNULL, pgxpPsxNULL,
+	pgxpPsxNULL, pgxpPsxNULL, pgxpPsxNULL, pgxpPsxNULL, pgxpPsxNULL, pgxpPsxNULL, pgxpPsxNULL, pgxpPsxNULL,
+	pgxpPsxNULL, pgxpPsxNULL, pgxpPsxNULL, pgxpPsxNULL, pgxpPsxNULL, pgxpPsxNULL, pgxpPsxNULL, pgxpPsxNULL
+};
+
+// Trace memory functions only
+static void(*pgxpPsxBSCMem[64])() = {
+	psxSPECIAL, psxREGIMM, psxJ   , psxJAL  , psxBEQ , psxBNE , psxBLEZ, psxBGTZ,
+	psxADDI   , psxADDIU , psxSLTI, psxSLTIU, psxANDI, psxORI , psxXORI, psxLUI ,
+	psxCOP0   , psxNULL  , psxCOP2, psxNULL , psxNULL, psxNULL, psxNULL, psxNULL,
+	psxNULL   , psxNULL  , psxNULL, psxNULL , psxNULL, psxNULL, psxNULL, psxNULL,
+	pgxpPsxLB     , pgxpPsxLH    , pgxpPsxLWL , pgxpPsxLW   , pgxpPsxLBU , pgxpPsxLHU , pgxpPsxLWR , pgxpPsxNULL,
+	pgxpPsxSB     , pgxpPsxSH    , pgxpPsxSWL , pgxpPsxSW   , pgxpPsxNULL, pgxpPsxNULL, pgxpPsxSWR , pgxpPsxNULL,
+	psxNULL   , psxNULL  , pgxpPsxLWC2, psxNULL , psxNULL, psxNULL, psxNULL, psxNULL,
+	psxNULL   , psxNULL  , pgxpPsxSWC2, psxHLE  , psxNULL, psxNULL, psxNULL, psxNULL
+};
+
 
 ///////////////////////////////////////////
 
@@ -1098,7 +1204,7 @@ static inline void execI() {
 	psxRegs.pc += 4;
 	psxRegs.cycle += BIAS;
 
-	psxBSC[psxRegs.code >> 26]();
+	pPsxBSC[psxRegs.code >> 26]();
 }
 
 R3000Acpu psxInt = {
@@ -1107,5 +1213,6 @@ R3000Acpu psxInt = {
 	intExecute,
 	intExecuteBlock,
 	intClear,
-	intShutdown
+	intShutdown,
+	intSetPGXPMode
 };
diff --git a/libpcsxcore/psxinterpreter_pgxp.h b/libpcsxcore/psxinterpreter_pgxp.h
new file mode 100644
index 00000000..a61e8ed3
--- /dev/null
+++ b/libpcsxcore/psxinterpreter_pgxp.h
@@ -0,0 +1,159 @@
+#ifndef _PSX_INTERPRETER_PGXP_H_
+#define _PSX_INTERPRETER_PGXP_H_
+
+
+/////////////////////////////////////////////
+// PGXP wrapper functions
+/////////////////////////////////////////////
+
+pgxpPsxNULL() {}
+
+#define psxMTC2 gteMTC2
+#define psxCTC2 gteCTC2
+#define psxLWC2 gteLWC2
+#define psxSWC2 gteSWC2
+
+// Choose between debug and direct function
+#ifdef PGXP_CPU_DEBUG
+#define PGXP_PSX_FUNC_OP(pu, op, nReg) PGXP_psxTraceOp##nReg
+#else
+#define PGXP_PSX_FUNC_OP(pu, op, nReg) PGXP_##pu##_##op
+#endif
+
+#define PGXP_INT_FUNC(pu, op) \
+static void pgxpPsx##op() { \
+	PGXP_PSX_FUNC_OP(pu, op, )(psxRegs.code); \
+}
+
+#define PGXP_INT_FUNC_0_1(pu, op, test, nReg, reg1) \
+static void pgxpPsx##op()	\
+{ \
+	if (test) return; \
+		psx##op(); \
+	PGXP_PSX_FUNC_OP(pu, op, nReg)(psxRegs.code, reg1); \
+}
+
+#define PGXP_INT_FUNC_1_0(pu, op, test, nReg, reg1)\
+static void pgxpPsx##op()	\
+{ \
+	if (test) return; \
+	PGXP_PSX_FUNC_OP(pu, op, nReg)(psxRegs.code, reg1); \
+	psx##op(); \
+}
+
+#define PGXP_INT_FUNC_1_1(pu, op, test, nReg, reg1, reg2)\
+static void pgxpPsx##op()	\
+{ \
+	if (test) return; \
+	u32 temp2 = reg2; \
+	psx##op(); \
+	PGXP_PSX_FUNC_OP(pu, op, nReg)(psxRegs.code, reg1, temp2); \
+}
+
+#define PGXP_INT_FUNC_0_2(pu, op, test, nReg, reg1, reg2) \
+static void pgxpPsx##op()	\
+{ \
+	if (test) return; \
+		psx##op(); \
+	PGXP_PSX_FUNC_OP(pu, op, nReg)(psxRegs.code, reg1, reg2); \
+}
+
+#define PGXP_INT_FUNC_2_1(pu, op, test, nReg, reg1, reg2, reg3) \
+static void pgxpPsx##op()	\
+{ \
+	if (test) return; \
+	u32 temp2 = reg2; \
+	u32 temp3 = reg3; \
+	psx##op(); \
+	PGXP_PSX_FUNC_OP(pu, op, nReg)(psxRegs.code, reg1, temp2, temp3); \
+}
+
+#define PGXP_INT_FUNC_2_2(pu, op, test, nReg, reg1, reg2, reg3, reg4) \
+static void pgxpPsx##op()	\
+{ \
+	if (test) return; \
+	u32 temp3 = reg3; \
+	u32 temp4 = reg4; \
+	psx##op(); \
+	PGXP_PSX_FUNC_OP(pu, op, nReg)(psxRegs.code, reg1, reg2, temp3, temp4); \
+}
+
+// Rt = Rs op imm 
+PGXP_INT_FUNC_1_1(CPU, ADDI,	!_Rt_, 2, psxRegs.GPR.r[_Rt_], psxRegs.GPR.r[_Rs_])
+PGXP_INT_FUNC_1_1(CPU, ADDIU,	!_Rt_, 2, psxRegs.GPR.r[_Rt_], psxRegs.GPR.r[_Rs_])
+PGXP_INT_FUNC_1_1(CPU, ANDI,	!_Rt_, 2, psxRegs.GPR.r[_Rt_], psxRegs.GPR.r[_Rs_])
+PGXP_INT_FUNC_1_1(CPU, ORI,		!_Rt_, 2, psxRegs.GPR.r[_Rt_], psxRegs.GPR.r[_Rs_])
+PGXP_INT_FUNC_1_1(CPU, XORI,	!_Rt_, 2, psxRegs.GPR.r[_Rt_], psxRegs.GPR.r[_Rs_])
+PGXP_INT_FUNC_1_1(CPU, SLTI,	!_Rt_, 2, psxRegs.GPR.r[_Rt_], psxRegs.GPR.r[_Rs_])
+PGXP_INT_FUNC_1_1(CPU, SLTIU,	!_Rt_, 2, psxRegs.GPR.r[_Rt_], psxRegs.GPR.r[_Rs_])
+
+// Rt = imm
+PGXP_INT_FUNC_0_1(CPU, LUI, !_Rt_, 1, psxRegs.GPR.r[_Rt_])
+
+// Rd = Rs op Rt 
+PGXP_INT_FUNC_2_1(CPU, ADD,		!_Rd_, 3, psxRegs.GPR.r[_Rd_], psxRegs.GPR.r[_Rs_], psxRegs.GPR.r[_Rt_])
+PGXP_INT_FUNC_2_1(CPU, ADDU,	!_Rd_, 3, psxRegs.GPR.r[_Rd_], psxRegs.GPR.r[_Rs_], psxRegs.GPR.r[_Rt_])
+PGXP_INT_FUNC_2_1(CPU, SUB,		!_Rd_, 3, psxRegs.GPR.r[_Rd_], psxRegs.GPR.r[_Rs_], psxRegs.GPR.r[_Rt_])
+PGXP_INT_FUNC_2_1(CPU, SUBU,	!_Rd_, 3, psxRegs.GPR.r[_Rd_], psxRegs.GPR.r[_Rs_], psxRegs.GPR.r[_Rt_])
+PGXP_INT_FUNC_2_1(CPU, AND,		!_Rd_, 3, psxRegs.GPR.r[_Rd_], psxRegs.GPR.r[_Rs_], psxRegs.GPR.r[_Rt_])
+PGXP_INT_FUNC_2_1(CPU, OR,		!_Rd_, 3, psxRegs.GPR.r[_Rd_], psxRegs.GPR.r[_Rs_], psxRegs.GPR.r[_Rt_])
+PGXP_INT_FUNC_2_1(CPU, XOR,		!_Rd_, 3, psxRegs.GPR.r[_Rd_], psxRegs.GPR.r[_Rs_], psxRegs.GPR.r[_Rt_])
+PGXP_INT_FUNC_2_1(CPU, NOR,		!_Rd_, 3, psxRegs.GPR.r[_Rd_], psxRegs.GPR.r[_Rs_], psxRegs.GPR.r[_Rt_])
+PGXP_INT_FUNC_2_1(CPU, SLT,		!_Rd_, 3, psxRegs.GPR.r[_Rd_], psxRegs.GPR.r[_Rs_], psxRegs.GPR.r[_Rt_])
+PGXP_INT_FUNC_2_1(CPU, SLTU,	!_Rd_, 3, psxRegs.GPR.r[_Rd_], psxRegs.GPR.r[_Rs_], psxRegs.GPR.r[_Rt_])
+
+// Hi/Lo = Rs op Rt
+PGXP_INT_FUNC_2_2(CPU, MULT,	0, 4, psxRegs.GPR.n.hi, psxRegs.GPR.n.lo, psxRegs.GPR.r[_Rs_], psxRegs.GPR.r[_Rt_])
+PGXP_INT_FUNC_2_2(CPU, MULTU,	0, 4, psxRegs.GPR.n.hi, psxRegs.GPR.n.lo, psxRegs.GPR.r[_Rs_], psxRegs.GPR.r[_Rt_])
+PGXP_INT_FUNC_2_2(CPU, DIV,		0, 4, psxRegs.GPR.n.hi, psxRegs.GPR.n.lo, psxRegs.GPR.r[_Rs_], psxRegs.GPR.r[_Rt_])
+PGXP_INT_FUNC_2_2(CPU, DIVU,	0, 4, psxRegs.GPR.n.hi, psxRegs.GPR.n.lo, psxRegs.GPR.r[_Rs_], psxRegs.GPR.r[_Rt_])
+
+// Mem[addr] = Rt
+PGXP_INT_FUNC_0_2(CPU, SB,	0, 2, psxRegs.GPR.r[_Rt_],  _oB_)
+PGXP_INT_FUNC_0_2(CPU, SH,	0, 2, psxRegs.GPR.r[_Rt_],  _oB_)
+PGXP_INT_FUNC_0_2(CPU, SW,	0, 2, psxRegs.GPR.r[_Rt_],  _oB_)
+PGXP_INT_FUNC_0_2(CPU, SWL, 0, 2, psxRegs.GPR.r[_Rt_],  _oB_)
+PGXP_INT_FUNC_0_2(CPU, SWR, 0, 2, psxRegs.GPR.r[_Rt_],  _oB_)
+
+// Rt = Mem[addr]
+PGXP_INT_FUNC_0_2(CPU, LWL, 0, 2, psxRegs.GPR.r[_Rt_],  _oB_)
+PGXP_INT_FUNC_0_2(CPU, LW,	0, 2, psxRegs.GPR.r[_Rt_],  _oB_)
+PGXP_INT_FUNC_0_2(CPU, LWR, 0, 2, psxRegs.GPR.r[_Rt_],  _oB_)
+PGXP_INT_FUNC_0_2(CPU, LH,	0, 2, psxRegs.GPR.r[_Rt_],  _oB_)
+PGXP_INT_FUNC_0_2(CPU, LHU, 0, 2, psxRegs.GPR.r[_Rt_],  _oB_)
+PGXP_INT_FUNC_0_2(CPU, LB,	0, 2, psxRegs.GPR.r[_Rt_],  _oB_)
+PGXP_INT_FUNC_0_2(CPU, LBU, 0, 2, psxRegs.GPR.r[_Rt_],  _oB_)
+
+//Rd = Rt op Sa
+PGXP_INT_FUNC_1_1(CPU, SLL, !_Rd_, 2, psxRegs.GPR.r[_Rd_], psxRegs.GPR.r[_Rt_])
+PGXP_INT_FUNC_1_1(CPU, SRL, !_Rd_, 2, psxRegs.GPR.r[_Rd_], psxRegs.GPR.r[_Rt_])
+PGXP_INT_FUNC_1_1(CPU, SRA, !_Rd_, 2, psxRegs.GPR.r[_Rd_], psxRegs.GPR.r[_Rt_])
+
+// Rd = Rt op Rs
+PGXP_INT_FUNC_2_1(CPU, SLLV, !_Rd_, 3, psxRegs.GPR.r[_Rd_], psxRegs.GPR.r[_Rt_], psxRegs.GPR.r[_Rs_])
+PGXP_INT_FUNC_2_1(CPU, SRLV, !_Rd_, 3, psxRegs.GPR.r[_Rd_], psxRegs.GPR.r[_Rt_], psxRegs.GPR.r[_Rs_])
+PGXP_INT_FUNC_2_1(CPU, SRAV, !_Rd_, 3, psxRegs.GPR.r[_Rd_], psxRegs.GPR.r[_Rt_], psxRegs.GPR.r[_Rs_])
+
+PGXP_INT_FUNC_1_1(CPU, MFHI, !_Rd_	, 2, psxRegs.GPR.r[_Rd_], psxRegs.GPR.n.hi)
+PGXP_INT_FUNC_1_1(CPU, MTHI, 0		, 2, psxRegs.GPR.n.hi, psxRegs.GPR.r[_Rd_])
+PGXP_INT_FUNC_1_1(CPU, MFLO, !_Rd_	, 2, psxRegs.GPR.r[_Rd_], psxRegs.GPR.n.lo)
+PGXP_INT_FUNC_1_1(CPU, MTLO, 0		, 2, psxRegs.GPR.n.lo, psxRegs.GPR.r[_Rd_])
+
+
+// COP2 (GTE)
+PGXP_INT_FUNC_0_1(GTE, MFC2, !_Rt_, 1, psxRegs.CP2D.r[_Rd_])
+PGXP_INT_FUNC_0_1(GTE, CFC2, !_Rt_, 1, psxRegs.CP2C.r[_Rd_])
+PGXP_INT_FUNC_1_0(GTE, MTC2, 0, 1, psxRegs.GPR.r[_Rt_])
+PGXP_INT_FUNC_1_0(GTE, CTC2, 0, 1, psxRegs.GPR.r[_Rt_])
+
+PGXP_INT_FUNC_0_2(GTE, LWC2, 0, 2, psxRegs.CP2D.r[_Rt_], _oB_)
+PGXP_INT_FUNC_0_2(GTE, SWC2, 0, 2, psxRegs.CP2D.r[_Rt_], _oB_)
+
+// COP0
+PGXP_INT_FUNC_0_1(CP0, MFC0, !_Rd_, 1, psxRegs.CP0.r[_Rd_])
+PGXP_INT_FUNC_0_1(CP0, CFC0, !_Rd_, 1, psxRegs.CP0.r[_Rd_])
+PGXP_INT_FUNC_1_0(CP0, MTC0, !_Rt_, 1, psxRegs.CP2D.r[_Rt_])
+PGXP_INT_FUNC_1_0(CP0, CTC0, !_Rt_, 1, psxRegs.CP2D.r[_Rt_])
+PGXP_INT_FUNC(CP0, RFE)
+
+#endif//_PSX_INTERPRETER_PGXP_H_
diff --git a/libpcsxcore/r3000a.c b/libpcsxcore/r3000a.c
index 437d0b15..61adc5c0 100755
--- a/libpcsxcore/r3000a.c
+++ b/libpcsxcore/r3000a.c
@@ -275,3 +275,9 @@ void psxExecuteBios() {
 	while (psxRegs.pc != 0x80030000)
 		psxCpu->ExecuteBlock();
 }
+
+void psxSetPGXPMode(u32 pgxpMode)
+{
+	psxCpu->SetPGXPMode(pgxpMode);
+	//psxCpu->Reset();
+}
diff --git a/libpcsxcore/r3000a.h b/libpcsxcore/r3000a.h
index cbd0e20f..b0616256 100755
--- a/libpcsxcore/r3000a.h
+++ b/libpcsxcore/r3000a.h
@@ -36,6 +36,7 @@ typedef struct {
 	void (*ExecuteBlock)();	/* executes up to a jump */
 	void (*Clear)(u32 Addr, u32 Size);
 	void (*Shutdown)();
+	void (*SetPGXPMode)(u32 pgxpMode);
 } R3000Acpu;
 
 extern R3000Acpu *psxCpu;
@@ -346,6 +347,8 @@ void psxDelayTest(int reg, u32 bpc);
 void psxTestSWInts();
 void psxJumpTest();
 
+void psxSetPGXPMode(u32 pgxpMode);
+
 #ifdef __cplusplus
 }
 #endif