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authorSND\ckain_cp <SND\ckain_cp@e17a0e51-4ae3-4d35-97c3-1a29b211df97>2013-10-02 16:19:04 +0000
committerSND\ckain_cp <SND\ckain_cp@e17a0e51-4ae3-4d35-97c3-1a29b211df97>2013-10-02 16:19:04 +0000
commit2ee144472e54c451a26b71489f1abde0dcd5bd64 (patch)
treeda66b1d2c836ba2ca07566aa11b06a39f40c036c /libpcsxcore
parent72053c4cecb4527928b6a62c1a95c892f4463c0f (diff)
downloadpcsxr-2ee144472e54c451a26b71489f1abde0dcd5bd64.tar.gz
Fix Toshinden Subaru with a hack for now. Seems that xa.c needs some further debugging.
git-svn-id: https://pcsxr.svn.codeplex.com/svn/pcsxr@87349 e17a0e51-4ae3-4d35-97c3-1a29b211df97
Diffstat (limited to 'libpcsxcore')
-rwxr-xr-xlibpcsxcore/gpu.c2
-rwxr-xr-xlibpcsxcore/psxhw.c25
2 files changed, 20 insertions, 7 deletions
diff --git a/libpcsxcore/gpu.c b/libpcsxcore/gpu.c
index 60886aa7..324c2a00 100755
--- a/libpcsxcore/gpu.c
+++ b/libpcsxcore/gpu.c
@@ -129,7 +129,7 @@ void psxDma2(u32 madr, u32 bcr, u32 chcr) { // GPU
return;
case 0x01000201: // mem2vram
- bs=(bcr & 0xffff);
+ bs=(bcr & 0xffff);
size = (bcr >> 16) * bs; // BA blocks * BS words (word = 32-bits)
#ifdef PSXDMA_LOG
PSXDMA_LOG("*** DMA 2 - GPU mem2vram *** %lx addr = %lxh, BCR %lxh => size %d = BA(%d) * BS(%xh)\n",
diff --git a/libpcsxcore/psxhw.c b/libpcsxcore/psxhw.c
index b753c2f3..2ac9a609 100755
--- a/libpcsxcore/psxhw.c
+++ b/libpcsxcore/psxhw.c
@@ -298,12 +298,12 @@ u32 psxHwRead32(u32 add) {
#endif
#ifdef PSXHW_LOG
-/* case 0x1f8010f0:
- PSXHW_LOG("DMA PCR 32bit read %x\n", psxHu32(0x10f0));
- return SWAPu32(HW_DMA_PCR); // dma rest channel
+ case 0x1f8010f0:
+ PSXHW_LOG("DMA PCR 32bit read %x\n", HW_DMA_PCR);
+ return SWAPu32(HW_DMA_PCR); // DMA control register
case 0x1f8010f4:
- PSXHW_LOG("DMA ICR 32bit read %x\n", psxHu32(0x10f4));
- return SWAPu32(HW_DMA_ICR); // interrupt enabler?*/
+ PSXHW_LOG("DMA ICR 32bit read %x\n", HW_DMA_ICR);
+ return SWAPu32(HW_DMA_ICR); // DMA interrupt register (enable/ack)
#endif
// time for rootcounters :)
@@ -361,11 +361,17 @@ u32 psxHwRead32(u32 add) {
PSXHW_LOG("T2 target read32: %x\n", hard);
#endif
return hard;
+ case 0x1f801014:
+ hard = psxHu32(add);
+#ifdef PSXHW_LOG
+ PSXHW_LOG("SPU delay [0x1014] read32: %8.8lx\n", hard);
+#endif
+ return hard;
default:
hard = psxHu32(add);
#ifdef PSXHW_LOG
- PSXHW_LOG("*Unkwnown 32bit read at address %x\n", add);
+ PSXHW_LOG("*Unknown 32bit read at address %x (0x%8.8lx)\n", add, hard);
#endif
return hard;
}
@@ -721,6 +727,13 @@ void psxHwWrite32(u32 add, u32 value) {
return;
}
+
+ case 0x1f801014:
+#ifdef PSXHW_LOG
+ PSXHW_LOG("SPU delay [0x1014] write32: %8.8lx\n", value);
+#endif
+ psxHu32ref(add) = SWAPu32(value);
+ return;
case 0x1f801810:
#ifdef PSXHW_LOG
PSXHW_LOG("GPU DATA 32bit write %x\n", value);