Commited patch in issue #8171 (by darktjm).

git-svn-id: https://pcsxr.svn.codeplex.com/svn/pcsxr@64524 e17a0e51-4ae3-4d35-97c3-1a29b211df97

1 files changed, 190 insertions, 190 deletions

diff --git a/libpcsxcore/psxinterpreter.c b/libpcsxcore/psxinterpreter.c
index 69d0061f..eedb7452 100644
--- a/libpcsxcore/psxinterpreter.c
+++ b/libpcsxcore/psxinterpreter.c
@@ -47,7 +47,7 @@ void (*psxREG[32])();
 void (*psxCP0[32])();
 void (*psxCP2[64])();
 void (*psxCP2BSC[32])();
-

+
 static void delayRead(int reg, u32 bpc) {
 	u32 rold, rnew;
 
@@ -155,10 +155,10 @@ int psxTestLoadDelay(int reg, u32 tmp) {
 			switch (_tRt_) {
 				case 0x00: case 0x01:
 				case 0x10: case 0x11: // BLTZ/BGEZ...
-					// Xenogears - lbu v0 / beq v0

-					// - no load delay (fixes battle loading)

-					break;

-

+					// Xenogears - lbu v0 / beq v0
+					// - no load delay (fixes battle loading)
+					break;
+
 					if (_tRs_ == reg) return 2;
 					break;
 			}
@@ -170,18 +170,18 @@ int psxTestLoadDelay(int reg, u32 tmp) {
 			break;
 
 		case 0x04: case 0x05: // BEQ/BNE
-			// Xenogears - lbu v0 / beq v0

-			// - no load delay (fixes battle loading)

-			break;

-

+			// Xenogears - lbu v0 / beq v0
+			// - no load delay (fixes battle loading)
+			break;
+
 			if (_tRs_ == reg || _tRt_ == reg) return 2;
 			break;
 
 		case 0x06: case 0x07: // BLEZ/BGTZ
-			// Xenogears - lbu v0 / beq v0

-			// - no load delay (fixes battle loading)

-			break;

-

+			// Xenogears - lbu v0 / beq v0
+			// - no load delay (fixes battle loading)
+			break;
+
 			if (_tRs_ == reg) return 2;
 			break;
 
@@ -265,9 +265,9 @@ void psxDelayTest(int reg, u32 bpc) {
 	u32 *code;
 	u32 tmp;
 
-	// Don't execute yet - just peek

-	code = Read_ICache(bpc, TRUE);

-

+	// Don't execute yet - just peek
+	code = Read_ICache(bpc, TRUE);
+
 	tmp = ((code == NULL) ? 0 : SWAP32(*code));
 	branch = 1;
 
@@ -409,7 +409,7 @@ static int psxDelayBranchTest(u32 tar1) {
 	return psxDelayBranchExec(tmp2);
 }
 
-__inline void doBranch(u32 tar) {
+static __inline void doBranch(u32 tar) {
 	u32 *code;
 	u32 tmp;
 
@@ -420,9 +420,9 @@ __inline void doBranch(u32 tar) {
 	if (psxDelayBranchTest(tar))
 		return;
 
-	// branch delay slot

-	code = Read_ICache(psxRegs.pc, TRUE);

-

+	// branch delay slot
+	code = Read_ICache(psxRegs.pc, TRUE);
+
 	psxRegs.code = ((code == NULL) ? 0 : SWAP32(*code));
 
 	debugI();
@@ -508,10 +508,10 @@ void psxDIV() {
 		_i32(_rLo_) = _i32(_rRs_) / _i32(_rRt_);
 		_i32(_rHi_) = _i32(_rRs_) % _i32(_rRt_);
 	}
-	else {

-		_i32(_rLo_) = 0xffffffff;

-		_i32(_rHi_) = _i32(_rRs_);

-	}

+	else {
+		_i32(_rLo_) = 0xffffffff;
+		_i32(_rHi_) = _i32(_rRs_);
+	}
 }
 
 void psxDIVU() {
@@ -519,10 +519,10 @@ void psxDIVU() {
 		_rLo_ = _rRs_ / _rRt_;
 		_rHi_ = _rRs_ % _rRt_;
 	}
-	else {

-		_rLo_ = 0xffffffff;

-		_rHi_ = _rRs_;

-	}

+	else {
+		_rLo_ = 0xffffffff;
+		_rHi_ = _rRs_;
+	}
 }
 
 void psxMULT() {
@@ -647,18 +647,18 @@ void psxJALR() {
 #define _oB_ (_u32(_rRs_) + _Imm_)
 
 void psxLB() {
-	// load delay = 1 latency

-	if( branch == 0 )

-	{

-		// simulate: beq r0,r0,lw+4 / lw / (delay slot)

-		psxRegs.pc -= 4;

-		doBranch( psxRegs.pc + 4 );

-

-		return;

-	}

-

-

-

+	// load delay = 1 latency
+	if( branch == 0 )
+	{
+		// simulate: beq r0,r0,lw+4 / lw / (delay slot)
+		psxRegs.pc -= 4;
+		doBranch( psxRegs.pc + 4 );
+
+		return;
+	}
+
+
+
 	if (_Rt_) {
 		_i32(_rRt_) = (signed char)psxMemRead8(_oB_); 
 	} else {
@@ -667,18 +667,18 @@ void psxLB() {
 }
 
 void psxLBU() {
-	// load delay = 1 latency

-	if( branch == 0 )

-	{

-		// simulate: beq r0,r0,lw+4 / lw / (delay slot)

-		psxRegs.pc -= 4;

-		doBranch( psxRegs.pc + 4 );

-

-		return;

-	}

-

-

-

+	// load delay = 1 latency
+	if( branch == 0 )
+	{
+		// simulate: beq r0,r0,lw+4 / lw / (delay slot)
+		psxRegs.pc -= 4;
+		doBranch( psxRegs.pc + 4 );
+
+		return;
+	}
+
+
+
 	if (_Rt_) {
 		_u32(_rRt_) = psxMemRead8(_oB_);
 	} else {
@@ -687,18 +687,18 @@ void psxLBU() {
 }
 
 void psxLH() {
-	// load delay = 1 latency

-	if( branch == 0 )

-	{

-		// simulate: beq r0,r0,lw+4 / lw / (delay slot)

-		psxRegs.pc -= 4;

-		doBranch( psxRegs.pc + 4 );

-

-		return;

-	}

-

-

-

+	// load delay = 1 latency
+	if( branch == 0 )
+	{
+		// simulate: beq r0,r0,lw+4 / lw / (delay slot)
+		psxRegs.pc -= 4;
+		doBranch( psxRegs.pc + 4 );
+
+		return;
+	}
+
+
+
 	if (_Rt_) {
 		_i32(_rRt_) = (short)psxMemRead16(_oB_);
 	} else {
@@ -707,18 +707,18 @@ void psxLH() {
 }
 
 void psxLHU() {
-	// load delay = 1 latency

-	if( branch == 0 )

-	{

-		// simulate: beq r0,r0,lw+4 / lw / (delay slot)

-		psxRegs.pc -= 4;

-		doBranch( psxRegs.pc + 4 );

-

-		return;

-	}

-

-

-

+	// load delay = 1 latency
+	if( branch == 0 )
+	{
+		// simulate: beq r0,r0,lw+4 / lw / (delay slot)
+		psxRegs.pc -= 4;
+		doBranch( psxRegs.pc + 4 );
+
+		return;
+	}
+
+
+
 	if (_Rt_) {
 		_u32(_rRt_) = psxMemRead16(_oB_);
 	} else {
@@ -727,18 +727,18 @@ void psxLHU() {
 }
 
 void psxLW() {
-	// load delay = 1 latency

-	if( branch == 0 )

-	{

-		// simulate: beq r0,r0,lw+4 / lw / (delay slot)

-		psxRegs.pc -= 4;

-		doBranch( psxRegs.pc + 4 );

-

-		return;

-	}

-

-

-

+	// load delay = 1 latency
+	if( branch == 0 )
+	{
+		// simulate: beq r0,r0,lw+4 / lw / (delay slot)
+		psxRegs.pc -= 4;
+		doBranch( psxRegs.pc + 4 );
+
+		return;
+	}
+
+
+
 	if (_Rt_) {
 		_u32(_rRt_) = psxMemRead32(_oB_);
 	} else {
@@ -753,19 +753,19 @@ void psxLWL() {
 	u32 addr = _oB_;
 	u32 shift = addr & 3;
 	u32 mem = psxMemRead32(addr & ~3);
-

-
-	// load delay = 1 latency

-	if( branch == 0 )

-	{

-		// simulate: beq r0,r0,lw+4 / lw / (delay slot)

-		psxRegs.pc -= 4;

-		doBranch( psxRegs.pc + 4 );

-

-		return;

-	}

-

-

+
+
+	// load delay = 1 latency
+	if( branch == 0 )
+	{
+		// simulate: beq r0,r0,lw+4 / lw / (delay slot)
+		psxRegs.pc -= 4;
+		doBranch( psxRegs.pc + 4 );
+
+		return;
+	}
+
+
 	if (!_Rt_) return;
 	_u32(_rRt_) =	( _u32(_rRt_) & LWL_MASK[shift]) | 
 					( mem << LWL_SHIFT[shift]);
@@ -788,20 +788,20 @@ void psxLWR() {
 	u32 shift = addr & 3;
 	u32 mem = psxMemRead32(addr & ~3);
 
-

-	

-	// load delay = 1 latency

-	if( branch == 0 )

-	{

-		// simulate: beq r0,r0,lw+4 / lw / (delay slot)

-		psxRegs.pc -= 4;

-		doBranch( psxRegs.pc + 4 );

-

-		return;

-	}

-

-

-

+
+	
+	// load delay = 1 latency
+	if( branch == 0 )
+	{
+		// simulate: beq r0,r0,lw+4 / lw / (delay slot)
+		psxRegs.pc -= 4;
+		doBranch( psxRegs.pc + 4 );
+
+		return;
+	}
+
+
+
 	if (!_Rt_) return;
 	_u32(_rRt_) =	( _u32(_rRt_) & LWR_MASK[shift]) | 
 					( mem >> LWR_SHIFT[shift]);
@@ -865,40 +865,40 @@ void psxSWR() {
 * Moves between GPR and COPx                             *
 * Format:  OP rt, fs                                     *
 *********************************************************/
-void psxMFC0()

-{

-	// load delay = 1 latency

-	if( branch == 0 )

-	{

-		// simulate: beq r0,r0,lw+4 / lw / (delay slot)

-		psxRegs.pc -= 4;

-		doBranch( psxRegs.pc + 4 );

-

-		return;

-	}

-

-

-	if (!_Rt_) return;

-	

-	_i32(_rRt_) = (int)_rFs_;

-}

-
-void psxCFC0()

-{

-	// load delay = 1 latency

-	if( branch == 0 )

-	{

-		// simulate: beq r0,r0,lw+4 / lw / (delay slot)

-		psxRegs.pc -= 4;

-		doBranch( psxRegs.pc + 4 );

-

-		return;

-	}

-

-

-	if (!_Rt_) return;

-	

-	_i32(_rRt_) = (int)_rFs_;

+void psxMFC0()
+{
+	// load delay = 1 latency
+	if( branch == 0 )
+	{
+		// simulate: beq r0,r0,lw+4 / lw / (delay slot)
+		psxRegs.pc -= 4;
+		doBranch( psxRegs.pc + 4 );
+
+		return;
+	}
+
+
+	if (!_Rt_) return;
+	
+	_i32(_rRt_) = (int)_rFs_;
+}
+
+void psxCFC0()
+{
+	// load delay = 1 latency
+	if( branch == 0 )
+	{
+		// simulate: beq r0,r0,lw+4 / lw / (delay slot)
+		psxRegs.pc -= 4;
+		doBranch( psxRegs.pc + 4 );
+
+		return;
+	}
+
+
+	if (!_Rt_) return;
+	
+	_i32(_rRt_) = (int)_rFs_;
 }
 
 void psxTestSWInts() {
@@ -932,40 +932,40 @@ __inline void MTC0(int reg, u32 val) {
 void psxMTC0() { MTC0(_Rd_, _u32(_rRt_)); }
 void psxCTC0() { MTC0(_Rd_, _u32(_rRt_)); }
 
-

-

-void psxMFC2()

-{

-	// load delay = 1 latency

-	if( branch == 0 )

-	{

-		// simulate: beq r0,r0,lw+4 / lw / (delay slot)

-		psxRegs.pc -= 4;

-		doBranch( psxRegs.pc + 4 );

-

-		return;

-	}

-

-	gteMFC2();

-}

-

-

-void psxCFC2()

-{

-	// load delay = 1 latency

-	if( branch == 0 )

-	{

-		// simulate: beq r0,r0,lw+4 / lw / (delay slot)

-		psxRegs.pc -= 4;

-		doBranch( psxRegs.pc + 4 );

-

-		return;

-	}

-

-	gteCFC2();

-}

-

-

+
+
+void psxMFC2()
+{
+	// load delay = 1 latency
+	if( branch == 0 )
+	{
+		// simulate: beq r0,r0,lw+4 / lw / (delay slot)
+		psxRegs.pc -= 4;
+		doBranch( psxRegs.pc + 4 );
+
+		return;
+	}
+
+	gteMFC2();
+}
+
+
+void psxCFC2()
+{
+	// load delay = 1 latency
+	if( branch == 0 )
+	{
+		// simulate: beq r0,r0,lw+4 / lw / (delay slot)
+		psxRegs.pc -= 4;
+		doBranch( psxRegs.pc + 4 );
+
+		return;
+	}
+
+	gteCFC2();
+}
+
+
 /*********************************************************
 * Unknow instruction (would generate an exception)       *
 * Format:  ?                                             *
@@ -989,13 +989,13 @@ void psxCOP0() {
 }
 
 void psxCOP2() {
-	if ((psxRegs.CP0.n.Status & 0x40000000) == 0 )

-		return;

-

+	if ((psxRegs.CP0.n.Status & 0x40000000) == 0 )
+		return;
+
 	psxCP2[_Funct_]();
 }
 
-void psxBASIC() {

+void psxBASIC() {
 	psxCP2BSC[_Rs_]();
 }
 
@@ -1067,7 +1067,7 @@ static int intInit() {
 }
 
 static void intReset() {
-	psxRegs.ICache_valid = FALSE;

+	psxRegs.ICache_valid = FALSE;
 }
 
 static void intExecute() {
@@ -1087,8 +1087,8 @@ static void intShutdown() {
 }
 
 // interpreter execution
-inline void execI() { 

-	u32 *code = Read_ICache(psxRegs.pc, FALSE);

+inline void execI() { 
+	u32 *code = Read_ICache(psxRegs.pc, FALSE);
 	psxRegs.code = ((code == NULL) ? 0 : SWAP32(*code));
 
 	debugI();