- Added -slowboot parameter.

- Load SBI file from patches/SLUS_xxx.xx.sbi instead.
- Inlined the I-cache code for performance improvement.
- Fixed endianness issue (not tested).


git-svn-id: https://pcsxr.svn.codeplex.com/svn/pcsxr@62024 e17a0e51-4ae3-4d35-97c3-1a29b211df97

1 files changed, 5 insertions, 104 deletions

diff --git a/libpcsxcore/psxinterpreter.c b/libpcsxcore/psxinterpreter.c
index 1ddc73cd..77791897 100644
--- a/libpcsxcore/psxinterpreter.c
+++ b/libpcsxcore/psxinterpreter.c
@@ -47,102 +47,6 @@ void (*psxREG[32])();
 void (*psxCP0[32])();
 void (*psxCP2[64])();
 void (*psxCP2BSC[32])();
-
-/*

-Formula One 2001

-- Use old CPU cache code when the RAM location is

-  updated with new code (affects in-game racing)

-

-TODO:

-- I-cache / D-cache swapping

-- Isolate D-cache from RAM

-*/

-

-u32 *Read_ICache( u32 pc, u32 isolate )

-{

-#define U32_PTR(x) (SWAP32(* (u32 *)(x)))

-#define U32_PTR_REF(x) (* (u32 *)(x))

-

-

-	u32 pc_bank, pc_offset, pc_cache;

-	u8 *IAddr, *ICode;

-

-	pc_bank = pc >> 24;

-	pc_offset = pc & 0xffffff;

-	pc_cache = pc & 0xfff;

-

-	IAddr = psxRegs.ICache_Addr;

-	ICode = psxRegs.ICache_Code;

-

-

-	//return PSXM(pc);

-

-

-	

-	// clear I-cache

-	if( psxRegs.ICache_valid == 0 )

-	{

-		memset( psxRegs.ICache_Addr, 0xff, sizeof(psxRegs.ICache_Addr) );

-		memset( psxRegs.ICache_Code, 0xff, sizeof(psxRegs.ICache_Code) );

-

-		psxRegs.ICache_valid = 1;

-	}

-

-

-

-	// uncached

-	if( pc_bank >= 0xa0 )

-		return PSXM(pc);

-

-

-	// cached - RAM

-	if( pc_bank == 0x80 || pc_bank == 0x00 )

-	{

-		if( U32_PTR( IAddr + pc_cache ) == pc_offset )

-		{

-			// Cache hit - return last opcode used

-			return ICode + pc_cache;

-		}

-		else

-		{

-			// Cache miss - addresses don't match

-			// - default: 0xffffffff (not init)

-

-			if( isolate == 0 )

-			{

-				// cache line is 4 bytes wide

-				pc_offset &= ~0xf;

-				pc_cache &= ~0xf;

-

-				// address line

-				U32_PTR_REF( IAddr + pc_cache + 0x0 ) = pc_offset + 0x0;

-				U32_PTR_REF( IAddr + pc_cache + 0x4 ) = pc_offset + 0x4;

-				U32_PTR_REF( IAddr + pc_cache + 0x8 ) = pc_offset + 0x8;

-				U32_PTR_REF( IAddr + pc_cache + 0xc ) = pc_offset + 0xc;

-

-				// opcode line

-				pc_offset = pc & ~0xf;

-				U32_PTR_REF( ICode + pc_cache + 0x0 ) = psxMu32( pc_offset + 0x0 );

-				U32_PTR_REF( ICode + pc_cache + 0x4 ) = psxMu32( pc_offset + 0x4 );

-				U32_PTR_REF( ICode + pc_cache + 0x8 ) = psxMu32( pc_offset + 0x8 );

-				U32_PTR_REF( ICode + pc_cache + 0xc ) = psxMu32( pc_offset + 0xc );

-			}

-

-			// normal code

-			return PSXM(pc);

-		}

-	}

-

-

-	/*

-	TODO: Probably should add cached BIOS

-	*/

-

-

-	// default

-	return PSXM(pc);

-}

-

 

 static void delayRead(int reg, u32 bpc) {
 	u32 rold, rnew;
@@ -362,8 +266,7 @@ void psxDelayTest(int reg, u32 bpc) {
 	u32 tmp;
 
 	// Don't execute yet - just peek

-	//code = (u32 *)PSXM(bpc);

-	code = Read_ICache(bpc,1);

+	code = Read_ICache(bpc, TRUE);

 

 	tmp = ((code == NULL) ? 0 : SWAP32(*code));
 	branch = 1;
@@ -392,8 +295,7 @@ __inline void doBranch(u32 tar) {
 	branchPC = tar;
 
 	// branch delay slot

-	//code = (u32 *)PSXM(psxRegs.pc);

-	code = Read_ICache( psxRegs.pc, 1 );

+	code = Read_ICache(psxRegs.pc, TRUE);

 

 	psxRegs.code = ((code == NULL) ? 0 : SWAP32(*code));
 
@@ -1039,7 +941,7 @@ static int intInit() {
 }
 
 static void intReset() {
-	psxRegs.ICache_valid = 0;

+	psxRegs.ICache_valid = FALSE;

 }
 
 static void intExecute() {
@@ -1059,9 +961,8 @@ static void intShutdown() {
 }
 
 // interpreter execution
-inline void execI() { 
-	//u32 *code = (u32 *)PSXM(psxRegs.pc); 

-	u32 *code = Read_ICache( psxRegs.pc,0 );

+inline void execI() { 

+	u32 *code = Read_ICache(psxRegs.pc, FALSE);

 	psxRegs.code = ((code == NULL) ? 0 : SWAP32(*code));
 
 	debugI();