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| author | SND\edgbla_cp <SND\edgbla_cp@e17a0e51-4ae3-4d35-97c3-1a29b211df97> | 2010-07-02 21:58:25 +0000 |
|---|---|---|
| committer | SND\edgbla_cp <SND\edgbla_cp@e17a0e51-4ae3-4d35-97c3-1a29b211df97> | 2010-07-02 21:58:25 +0000 |
| commit | 8410fc0c2eed060e79d5801a37583b6c729b85f6 (patch) | |
| tree | 5c25ae53da52e53becd8deeb7642569e0c013b21 /libpcsxcore/psxhw.c | |
| parent | a6d7aa989a0c665480196b6d49071086cef0b196 (diff) | |
| download | pcsxr-8410fc0c2eed060e79d5801a37583b6c729b85f6.tar.gz | |
Sio1 interface (link cable).
git-svn-id: https://pcsxr.svn.codeplex.com/svn/pcsxr@54110 e17a0e51-4ae3-4d35-97c3-1a29b211df97
Diffstat (limited to 'libpcsxcore/psxhw.c')
| -rw-r--r-- | libpcsxcore/psxhw.c | 51 |
1 files changed, 32 insertions, 19 deletions
diff --git a/libpcsxcore/psxhw.c b/libpcsxcore/psxhw.c index 9f48dad0..b07b035e 100644 --- a/libpcsxcore/psxhw.c +++ b/libpcsxcore/psxhw.c @@ -41,7 +41,7 @@ u8 psxHwRead8(u32 add) { switch (add) { case 0x1f801040: hard = sioRead8();break; - // case 0x1f801050: hard = serial_read8(); break;//for use of serial port ignore for now + case 0x1f801050: hard = SIO1_readData8(); break; case 0x1f801800: hard = cdrRead0(); break; case 0x1f801801: hard = cdrRead1(); break; case 0x1f801802: hard = cdrRead2(); break; @@ -104,13 +104,18 @@ u16 psxHwRead16(u32 add) { PAD_LOG("sio read16 %x; ret = %x\n", add&0xf, hard); #endif return hard; - - //Serial port stuff not support now ;P - // case 0x1f801050: hard = serial_read16(); break; - // case 0x1f801054: hard = serial_status_read(); break; - // case 0x1f80105a: hard = serial_control_read(); break; - // case 0x1f80105e: hard = serial_baud_read(); break; - + case 0x1f801050: + hard = SIO1_readData16(); + return hard; + case 0x1f801054: + hard = SIO1_readStat16(); + return hard; + case 0x1f80105a: + hard = SIO1_readCtrl16(); + return hard; + case 0x1f80105e: + hard = SIO1_readBaud16(); + return hard; case 0x1f801100: hard = psxRcntRcount(0); #ifdef PSXHW_LOG @@ -200,8 +205,9 @@ u32 psxHwRead32(u32 add) { PAD_LOG("sio read32 ;ret = %x\n", hard); #endif return hard; - - // case 0x1f801050: hard = serial_read32(); break;//serial port + case 0x1f801050: + hard = SIO1_readData32(); + return hard; #ifdef PSXHW_LOG case 0x1f801060: PSXHW_LOG("RAM size read %x\n", psxHu32(0x1060)); @@ -337,7 +343,7 @@ u32 psxHwRead32(u32 add) { void psxHwWrite8(u32 add, u8 value) { switch (add) { case 0x1f801040: sioWrite8(value); break; - // case 0x1f801050: serial_write8(value); break;//serial port + case 0x1f801050: SIO1_writeData8(value); break; case 0x1f801800: cdrWrite0(value); break; case 0x1f801801: cdrWrite1(value); break; case 0x1f801802: cdrWrite2(value); break; @@ -389,13 +395,18 @@ void psxHwWrite16(u32 add, u16 value) { PAD_LOG ("sio write16 %x, %x\n", add&0xf, value); #endif return; - - //serial port ;P - // case 0x1f801050: serial_write16(value); break; - // case 0x1f80105a: serial_control_write(value);break; - // case 0x1f80105e: serial_baud_write(value); break; - // case 0x1f801054: serial_status_write(value); break; - + case 0x1f801050: + SIO1_writeData16(value); + return; + case 0x1f801054: + SIO1_writeStat16(value); + return; + case 0x1f80105a: + SIO1_writeCtrl16(value); + return; + case 0x1f80105e: + SIO1_writeBaud16(value); + return; case 0x1f801070: #ifdef PSXHW_LOG PSXHW_LOG("IREG 16bit write %x\n", value); @@ -497,7 +508,9 @@ void psxHwWrite32(u32 add, u32 value) { PAD_LOG("sio write32 %x\n", value); #endif return; - // case 0x1f801050: serial_write32(value); break;//serial port + case 0x1f801050: + SIO1_writeData32(value); + return; #ifdef PSXHW_LOG case 0x1f801060: PSXHW_LOG("RAM size write %x\n", value); |