Commited patch in issue #8171 (by darktjm).

git-svn-id: https://pcsxr.svn.codeplex.com/svn/pcsxr@64524 e17a0e51-4ae3-4d35-97c3-1a29b211df97

6 files changed, 545 insertions, 545 deletions

diff --git a/libpcsxcore/ix86_64/iR3000A-64.c b/libpcsxcore/ix86_64/iR3000A-64.c
index fe146589..7f9a35cb 100644
--- a/libpcsxcore/ix86_64/iR3000A-64.c
+++ b/libpcsxcore/ix86_64/iR3000A-64.c
@@ -354,9 +354,10 @@ static void iDumpRegs() {
 	}
 }
 
-void iDumpBlock(char *ptr) {
+static void iDumpBlock(s8 *ptr) {
 	FILE *f;
 	u32 i;
+	char buf[200];
 
 	SysPrintf("dump1 %x:%x, %x\n", psxRegs.pc, pc, psxRegs.cycle);
 
@@ -364,11 +365,31 @@ void iDumpBlock(char *ptr) {
 		SysPrintf("%s\n", disR3000AF(PSXMu32(i), i));
 
 	fflush(stdout);
+#if 1
 	f = fopen("dump1", "w");
-	fwrite(ptr, 1, (uptr)x86Ptr - (uptr)ptr, f);
-	fclose(f);
-	//system("ndisasm -b64 dump1");
-	fflush(stdout);
+	if(f) {
+		/* errors don't really matter, but gcc complains if ignored */
+		int err;
+		err = fwrite(ptr, (uptr)x86Ptr - (uptr)ptr, 1, f) != 1;
+		err = fclose(f) != 0 || err;
+		if(!err) {
+			sprintf(buf, "objdump -m i386 -M x86-64 -D -b binary --adjust-vma=0x%lx dump1", (unsigned long)ptr);
+			err = system(buf);
+		} else
+			perror("dump1");
+		remove("dump1");
+	}
+#else
+	/* probably pointless; branch targets are still not symbols */
+	sprintf(buf,
+		"gdb --batch --quiet"
+		" -ex 'set verbose 0'"
+		" -ex 'set confirm 0'"
+		" -ex 'attach %d'"
+		" -ex 'disas/r %p,%p'"
+		, getpid(), ptr, x86Ptr - 1);
+	system(buf);
+#endif
 }
 
 #define REC_FUNC(f) \
diff --git a/libpcsxcore/ix86_64/ix86-64.c b/libpcsxcore/ix86_64/ix86-64.c
index 582b3a40..31ae8ea8 100644
--- a/libpcsxcore/ix86_64/ix86-64.c
+++ b/libpcsxcore/ix86_64/ix86-64.c
@@ -119,7 +119,7 @@ void CheckX86Ptr( void )
 {
 }
 
-void writeVAROP(unsigned opl, u64 op)
+static void writeVAROP(unsigned opl, u64 op)
 {
 	while (opl--)
 	{
@@ -177,14 +177,14 @@ void SET8R( int cc, int to )
 	write8( 0xC0 | ( to ) );
 }
 
-u8* J8Rel( int cc, int to )
+u8* J8Rel( int cc, u8 to )
 {
 	write8( cc );
     write8( to );
-    return x86Ptr - 1;
+    return (u8 *)x86Ptr - 1;
 }
 
-u16* J16Rel( int cc, u32 to )
+u16* J16Rel( int cc, u16 to )
 {
 	write16( 0x0F66 );
 	write8( cc );
@@ -214,7 +214,7 @@ void CMOV32MtoR( int cc, x86IntRegType to, uptr from )
 }
 
 ////////////////////////////////////////////////////
-void x86SetPtr( char* ptr ) 
+void x86SetPtr( s8* ptr )
 {
 	x86Ptr = ptr;
 }
@@ -2364,7 +2364,7 @@ u8* JMP8( u8 to )
 {
 	write8( 0xEB ); 
 	write8( to );
-	return x86Ptr - 1;
+	return (u8 *)x86Ptr - 1;
 }
 
 /* jmp rel32 */
@@ -2687,7 +2687,7 @@ void CMP64I32toR( x86IntRegType to, u32 from )
 /* cmp m64 to r64 */
 void CMP64MtoR( x86IntRegType to, uptr from ) 
 {
-	MEMADDR_OP(1, VAROP1(0x3B), true, 2, from, 0);
+	MEMADDR_OP(1, VAROP1(0x3B), true, to, from, 0);
 }
 
 // cmp r64 to r64 
@@ -2935,7 +2935,7 @@ void SETG8R( x86IntRegType to ) { SET8R(0x9f, to); }
 // seta r8 
 void SETA8R( x86IntRegType to ) { SET8R(0x97, to); }
 // setae r8 
-void SETAE8R( x86IntRegType to ) { SET8R(0x99, to); }
+void SETAE8R( x86IntRegType to ) { SET8R(0x93, to); }
 /* setb r8 */
 void SETB8R( x86IntRegType to ) { SET8R( 0x92, to ); }
 /* setb r8 */
diff --git a/libpcsxcore/ix86_64/ix86-64.h b/libpcsxcore/ix86_64/ix86-64.h
index 009fa5a1..95945a0f 100644
--- a/libpcsxcore/ix86_64/ix86-64.h
+++ b/libpcsxcore/ix86_64/ix86-64.h
@@ -191,9 +191,9 @@ typedef struct {
    u32 x86Flags;	   // Feature Flags
    u32 x86EFlags;	   // Extended Feature Flags
    //all the above returns hex values
-   s8  x86ID[16];	   // Vendor ID  //the vendor creator (in %s)
-   s8  x86Type[20];   //cpu type in char format //the cpu type (in %s)
-   s8  x86Fam[50];    // family in char format //the original cpu name string (in %s)
+   char x86ID[16];	   // Vendor ID  //the vendor creator (in %s)
+   char x86Type[20];   //cpu type in char format //the cpu type (in %s)
+   char x86Fam[50];    // family in char format //the original cpu name string (in %s)
    u32 cpuspeed;      // speed of cpu //this will give cpu speed (in %d)
 } CPUINFO;
 
@@ -228,7 +228,7 @@ extern u32 *j32Ptr[32];
 #define RexB(w, base) RexRXB(w, 0, 0, base)
 #define RexRB(w, reg, base) RexRXB(w, reg, 0, base)
 
-void x86SetPtr( char *ptr );
+void x86SetPtr( s8 *ptr );
 void x86Shutdown( void );
 
 void x86SetJ8( u8 *j8 );
@@ -245,7 +245,8 @@ u64 GetCPUTick( void );
 #define ModRM(mod, rm, reg) write8( ( mod << 6 ) | ( (rm & 7) << 3 ) | ( reg & 7 ) )
 #define SibSB(ss, rm, index) write8( ( ss << 6 ) | ( rm << 3 ) | ( index ) )
 void SET8R( int cc, int to );
-u8* J8Rel( int cc, int to );
+u8* J8Rel( int cc, u8 to );
+u16* J16Rel( int cc, u16 to );
 u32* J32Rel( int cc, u32 to );
 void CMOV32RtoR( int cc, int to, int from );
 void CMOV32MtoR( int cc, int to, uptr from );
@@ -478,6 +479,8 @@ void CMOVLE32MtoR( x86IntRegType to, uptr from );
 void ADD64ItoR( x86IntRegType to, u32 from );
 // add m64 to r64 
 void ADD64MtoR( x86IntRegType to, uptr from );
+// add r64 to r64
+void ADD64RtoR( x86IntRegType to, x86IntRegType from );
 
 // add imm32 to r32 
 void ADD32ItoR( x86IntRegType to, u32 from );
@@ -529,6 +532,7 @@ void INC16M( uptr to );
 // sub m64 to r64 
 void SUB64MtoR( x86IntRegType to, uptr from );
 void SUB64ItoR( x86IntRegType to, u32 from );
+void SUB64RtoR( x86IntRegType to, x86IntRegType from );
 
 // sub imm32 to r32 
 void SUB32ItoR( x86IntRegType to, u32 from );
@@ -795,6 +799,10 @@ u8*  JMP8( u8 to );
 
 // jmp rel32 
 u32* JMP32( uptr to );
+
+// jump rel8/rel32 (back jump only)
+u8* JMP( uptr to );
+
 // jmp r32 (r64 if __x86_64__)
 void JMPR( x86IntRegType to );
 // jmp m32 
@@ -1751,6 +1759,7 @@ void SSE2EMU_MOVD_XMM_to_M32( uptr to, x86SSERegType from );
 void SSE2EMU_MOVD_R_to_XMM( x86SSERegType to, x86IntRegType from );
 
 ////////////////////////////////////////////////////
+void CheckX86Ptr(void);
 #ifdef _DEBUG
 #define WRITECHECK() CheckX86Ptr()
 #else
@@ -1769,6 +1778,9 @@ void SSE2EMU_MOVD_R_to_XMM( x86SSERegType to, x86IntRegType from );
 #define write32( val ) writeVAL((u32)(val))
 #define write64( val ) writeVAL((u64)(val))
 
+void WriteRmOffset(x86IntRegType to, int offset);
+void WriteRmOffsetFrom(x86IntRegType to, x86IntRegType from, int offset);
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/libpcsxcore/ix86_64/ix86_cpudetect.c b/libpcsxcore/ix86_64/ix86_cpudetect.c
index 664e6b7d..76305974 100644
--- a/libpcsxcore/ix86_64/ix86_cpudetect.c
+++ b/libpcsxcore/ix86_64/ix86_cpudetect.c
@@ -1,492 +1,492 @@
-/*  Cpudetection lib 

- *  Copyright (C) 2002-2003  Pcsx2 Team

- *

- *  This program is free software; you can redistribute it and/or modify

- *  it under the terms of the GNU General Public License as published by

- *  the Free Software Foundation; either version 2 of the License, or

- *  (at your option) any later version.

- *

- *  This program is distributed in the hope that it will be useful,

- *  but WITHOUT ANY WARRANTY; without even the implied warranty of

- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

- *  GNU General Public License for more details.

- *

- *  You should have received a copy of the GNU General Public License

- *  along with this program; if not, write to the Free Software

- *  Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02111-1307 USA

- */

-

-#ifdef __x86_64__

-

-#if defined (_WIN32)

-#include <windows.h>

-#endif

-

-#include <string.h>

-#include <stdio.h>

-

-#include "ix86-64.h"

-

-#if defined (_MSC_VER) && _MSC_VER >= 1400

-

-   void __cpuid(int* CPUInfo, int InfoType);

-   unsigned __int64 __rdtsc();

-

-   #pragma intrinsic(__cpuid)

-   #pragma intrinsic(__rdtsc)

-

-#endif

-

-CAPABILITIES cpucaps;

-CPUINFO cpuinfo;

-

-#define cpuid(cmd,a,b,c,d) \

-  __asm__ __volatile__("cpuid" \

-		: "=a" (a), "=b" (b), "=c" (c), "=d" (d)  : "0" (cmd))

-

-static s32 iCpuId( u32 cmd, u32 *regs ) 

-{

-   int flag=1;

-

-#if defined (_MSC_VER) && _MSC_VER >= 1400

-

-   __cpuid( regs, cmd );

-

-   return 0;

-

-#elif defined (_MSC_VER) 

-

-#ifdef __x86_64__

-   assert(0);

-#else // __x86_64__

-   __asm 

-   {

-      push ebx;

-      push edi;

-

-      pushfd;

-      pop eax;

-      mov edx, eax;

-      xor eax, 1 << 21;

-      push eax;

-      popfd;

-      pushfd;

-      pop eax;

-      xor eax, edx;

-      mov flag, eax;

-   }

-   if ( ! flag )

-   {

-      return -1;

-   }

-

-   __asm 

-   {

-      mov eax, cmd;

-      cpuid;

-      mov edi, [regs]

-      mov [edi], eax;

-      mov [edi+4], ebx;

-      mov [edi+8], ecx;

-      mov [edi+12], edx;

-

-      pop edi;

-      pop ebx;

-   }

-#endif // __x86_64__

-   return 0;

-

-

-#else

-

-#ifndef __x86_64__

-   // see if we can use cpuid

-   __asm__ __volatile__ (

-      "sub $0x18, %%esp\n"

-      "pushf\n"

-      "pop %%eax\n"

-      "mov %%eax, %%edx\n"

-      "xor $0x200000, %%eax\n"

-      "push %%eax\n"

-      "popf\n"

-      "pushf\n"

-      "pop %%eax\n"

-      "xor %%edx, %%eax\n"

-      "mov %%eax, %0\n"

-	  "add $0x18, %%esp\n"

-      : "=r"(flag) :

-   );

-#endif

-

-   if ( !flag )

-       return -1;

-

-   cpuid(cmd, regs[0], regs[1], regs[2], regs[3]);

-   return 0;

-#endif // _MSC_VER

-}

-

-u64 GetCPUTick( void ) 

-{

-#if defined (_MSC_VER) && _MSC_VER >= 1400

-

-   return __rdtsc();

-

-#elif defined(__MSCW32__) && !defined(__x86_64__)

-

-   __asm rdtsc;

-

-#else

-

-   u32 _a, _d;

-	__asm__ __volatile__ ("rdtsc" : "=a"(_a), "=d"(_d));

-	return (u64)_a | ((u64)_d << 32);

-

-#endif

-}

-

-#if defined(__LINUX__) || defined(__APPLE__)

-

-#include <sys/time.h>

-#include <errno.h>

-//*

-unsigned long timeGetTime2()

-{

- struct timeval tv;

- gettimeofday(&tv, 0);                                 // well, maybe there are better ways

- return (unsigned long)tv.tv_sec * 1000 + tv.tv_usec/1000;            // to do that, but at least it works

-}

-//*/

-#endif

-

-s64 CPUSpeedHz( unsigned int time )

-{

-   s64 timeStart, 

-            timeStop;

-   s64 startTick, 

-            endTick;

-   s64 overhead;

-

-   if( ! cpucaps.hasTimeStampCounter )

-   {

-      return 0; //check if function is supported

-   }

-

-	overhead = GetCPUTick() - GetCPUTick();

-	

-	timeStart = timeGetTime2( );

-	while( timeGetTime2( ) == timeStart ) 

-   {

-      timeStart = timeGetTime2( );

-   }

-	for(;;)

-	{

-		timeStop = timeGetTime2( );

-		if ( ( timeStop - timeStart ) > 1 )	

-		{

-			startTick = GetCPUTick( );

-			break;

-		}

-	}

-

-	timeStart = timeStop;

-	for(;;)

-	{

-		timeStop = timeGetTime2( );

-		if ( ( timeStop - timeStart ) > time )	

-		{

-			endTick = GetCPUTick( );

-			break;

-		}

-	}

-

-	return (s64)( ( endTick - startTick ) + ( overhead ) );

-}

-

-////////////////////////////////////////////////////

-void cpudetectInit( void ) 

-{

-   u32 regs[ 4 ];

-   u32 cmds;

-   u32 AMDspeed;

-   s8 AMDspeedString[10];

-   int cputype=0;            // Cpu type

-   //AMD 64 STUFF

-   u32 x86_64_8BITBRANDID;

-   u32 x86_64_12BITBRANDID; 

-   memset( cpuinfo.x86ID, 0, sizeof( cpuinfo.x86ID ) );

-   cpuinfo.x86Family = 0;

-   cpuinfo.x86Model  = 0;

-   cpuinfo.x86PType  = 0;

-   cpuinfo.x86StepID = 0;

-   cpuinfo.x86Flags  = 0;

-   cpuinfo.x86EFlags = 0;

-   

-   if ( iCpuId( 0, regs ) == -1 ) return;

-

-   cmds = regs[ 0 ];

-   ((u32*)cpuinfo.x86ID)[ 0 ] = regs[ 1 ];

-   ((u32*)cpuinfo.x86ID)[ 1 ] = regs[ 3 ];

-   ((u32*)cpuinfo.x86ID)[ 2 ] = regs[ 2 ];

-   if ( cmds >= 0x00000001 ) 

-   {

-      if ( iCpuId( 0x00000001, regs ) != -1 )

-      {

-         cpuinfo.x86StepID =  regs[ 0 ]        & 0xf;

-         cpuinfo.x86Model  = (regs[ 0 ] >>  4) & 0xf;

-         cpuinfo.x86Family = (regs[ 0 ] >>  8) & 0xf;

-         cpuinfo.x86PType  = (regs[ 0 ] >> 12) & 0x3;

-         x86_64_8BITBRANDID = regs[1] & 0xff;

-         cpuinfo.x86Flags  =  regs[ 3 ];

-      }

-   }

-   if ( iCpuId( 0x80000000, regs ) != -1 )

-   {

-      cmds = regs[ 0 ];

-      if ( cmds >= 0x80000001 ) 

-      {

-		 if ( iCpuId( 0x80000001, regs ) != -1 )

-         {

-			x86_64_12BITBRANDID = regs[1] & 0xfff;

-            cpuinfo.x86EFlags = regs[ 3 ];

-            

-         }

-      }

-   }

-   switch(cpuinfo.x86PType)

-   {

-      case 0:

-         strcpy( cpuinfo.x86Type, "Standard OEM");

-         break;

-      case 1:

-         strcpy( cpuinfo.x86Type, "Overdrive");

-         break;

-      case 2:

-         strcpy( cpuinfo.x86Type, "Dual");

-         break;

-      case 3:

-         strcpy( cpuinfo.x86Type, "Reserved");

-         break;

-      default:

-         strcpy( cpuinfo.x86Type, "Unknown");

-         break;

-   }

-   if ( cpuinfo.x86ID[ 0 ] == 'G' ){ cputype=0;}//trick lines but if you know a way better ;p

-   if ( cpuinfo.x86ID[ 0 ] == 'A' ){ cputype=1;}

-   

-   if ( cputype == 0 ) //intel cpu

-   {

-      if( ( cpuinfo.x86Family >= 7 ) && ( cpuinfo.x86Family < 15 ) )

-      {

-         strcpy( cpuinfo.x86Fam, "Intel P6 family (Not PIV and Higher then PPro" );

-      }

-      else

-      {

-         switch( cpuinfo.x86Family )

-         {     

-            // Start at 486 because if it's below 486 there is no cpuid instruction

-            case 4:

-               strcpy( cpuinfo.x86Fam, "Intel 486" );

-               break;

-            case 5:     

-               switch( cpuinfo.x86Model )

-               {

-               case 4:

-               case 8:     // 0.25 µm

-                  strcpy( cpuinfo.x86Fam, "Intel Pentium (MMX)");

-                  break;

-               default:

-                  strcpy( cpuinfo.x86Fam, "Intel Pentium" );

-               }

-               break;

-            case 6:     

-               switch( cpuinfo.x86Model )

-               {

-               case 0:     // Pentium pro (P6 A-Step)

-               case 1:     // Pentium pro

-                  strcpy( cpuinfo.x86Fam, "Intel Pentium Pro" );

-                  break;

-

-               case 2:     // 66 MHz FSB

-               case 5:     // Xeon/Celeron (0.25 µm)

-               case 6:     // Internal L2 cache

-                  strcpy( cpuinfo.x86Fam, "Intel Pentium II" );

-                  break;

-

-               case 7:     // Xeon external L2 cache

-               case 8:     // Xeon/Celeron with 256 KB on-die L2 cache

-               case 10:    // Xeon/Celeron with 1 or 2 MB on-die L2 cache

-               case 11:    // Xeon/Celeron with Tualatin core, on-die cache

-                  strcpy( cpuinfo.x86Fam, "Intel Pentium III" );

-                  break;

-			   case 15:    // Core 2 Duo Allendale/Conroe

-				  strcpy( cpuinfo.x86Fam, "Intel Core 2 Duo" );

-				  break;

-

-               default:

-                  strcpy( cpuinfo.x86Fam, "Intel Pentium Pro (Unknown)" );

-               }

-               break;

-            case 15:

-               switch( cpuinfo.x86Model )

-               {

-               case 0:     // Willamette (A-Step)

-               case 1:     // Willamette 

-                  strcpy( cpuinfo.x86Fam, "Willamette Intel Pentium IV" );

-                  break;

-               case 2:     // Northwood 

-                  strcpy( cpuinfo.x86Fam, "Northwood Intel Pentium IV" );

-                  break;

-

-               default:

-                  strcpy( cpuinfo.x86Fam, "Intel Pentium IV (Unknown)" );

-                  break;

-               }

-               break;

-            default:

-               strcpy( cpuinfo.x86Fam, "Unknown Intel CPU" );

-         }

-      }

-   }

-   else if ( cputype == 1 ) //AMD cpu

-   {

-      if( cpuinfo.x86Family >= 7 )

-      {

-		  if((x86_64_12BITBRANDID !=0) || (x86_64_8BITBRANDID !=0))

-		  {

-		    if(x86_64_8BITBRANDID == 0 )

-		    {

-               switch((x86_64_12BITBRANDID >>6)& 0x3f)

-			   {

-			    case 4:

-				 strcpy(cpuinfo.x86Fam,"AMD Athlon(tm) 64 Processor");

-                 AMDspeed = 22 + (x86_64_12BITBRANDID & 0x1f);

-				 //AMDspeedString = strtol(AMDspeed, (char**)NULL,10);

-				 sprintf(AMDspeedString," %d",AMDspeed);

-				 strcat(AMDspeedString,"00+");

-				 strcat(cpuinfo.x86Fam,AMDspeedString);

-				 break;

-			    case 12: 

-				 strcpy(cpuinfo.x86Fam,"AMD Opteron(tm) Processor");

-				 break;

-			    case 5:

-				  strcpy( cpuinfo.x86Fam, "AMD Athlon X2 Processor" );

-				  AMDspeed = 22 + (x86_64_12BITBRANDID & 0x1f);

-				 //AMDspeedString = strtol(AMDspeed, (char**)NULL,10);

-				 sprintf(AMDspeedString," %d",AMDspeed);

-				 strcat(AMDspeedString,"00+");

-				 strcat(cpuinfo.x86Fam,AMDspeedString);

-                  break;

-			   case 44:

-				   strcpy( cpuinfo.x86Fam, "AMD Opteron(tm) Dual Core Processor" );

-                  break;

-			    default:

-				   strcpy(cpuinfo.x86Fam,"Unknown AMD 64 proccesor");

-				   

-			    }

-		     }

-		     else //8bit brand id is non zero

-		     {

-                strcpy(cpuinfo.x86Fam,"Unsupported yet AMD64 cpu");

-		     }

-		  }

-		  else

-		  {		 

-			  strcpy( cpuinfo.x86Fam, "AMD K7+ Processor" );

-		  }

-      }

-      else

-      {

-         switch ( cpuinfo.x86Family )

-         {

-            case 4:

-               switch( cpuinfo.x86Model )

-               {

-               case 14: 

-               case 15:       // Write-back enhanced

-                  strcpy( cpuinfo.x86Fam, "AMD 5x86 Processor" );

-                  break;

-

-               case 3:        // DX2

-               case 7:        // Write-back enhanced DX2

-               case 8:        // DX4

-               case 9:        // Write-back enhanced DX4

-                  strcpy( cpuinfo.x86Fam, "AMD 486 Processor" );

-                  break;

-			   			   

-

-               default:

-                  strcpy( cpuinfo.x86Fam, "AMD Unknown Processor" );

-

-               }

-               break;

-

-            case 5:     

-               switch( cpuinfo.x86Model)

-               {

-               case 0:     // SSA 5 (75, 90 and 100 Mhz)

-               case 1:     // 5k86 (PR 120 and 133 MHz)

-               case 2:     // 5k86 (PR 166 MHz)

-               case 3:     // K5 5k86 (PR 200 MHz)

-                  strcpy( cpuinfo.x86Fam, "AMD K5 Processor" );

-                  break;

-

-               case 6:     

-               case 7:     // (0.25 µm)

-               case 8:     // K6-2

-               case 9:     // K6-III

-               case 14:    // K6-2+ / K6-III+

-                  strcpy( cpuinfo.x86Fam, "AMD K6 Series Processor" );

-                  break;

-

-               default:

-                  strcpy( cpuinfo.x86Fam, "AMD Unknown Processor" );

-               }

-               break;

-            case 6:     

-               strcpy( cpuinfo.x86Fam, "AMD Athlon XP Processor" );

-               break;

-            default:

-               strcpy( cpuinfo.x86Fam, "Unknown AMD CPU" ); 

-         }

-      }

-   }

-   //capabilities

-   cpucaps.hasFloatingPointUnit                         = ( cpuinfo.x86Flags >>  0 ) & 1;

-   cpucaps.hasVirtual8086ModeEnhancements               = ( cpuinfo.x86Flags >>  1 ) & 1;

-   cpucaps.hasDebuggingExtensions                       = ( cpuinfo.x86Flags >>  2 ) & 1;

-   cpucaps.hasPageSizeExtensions                        = ( cpuinfo.x86Flags >>  3 ) & 1;

-   cpucaps.hasTimeStampCounter                          = ( cpuinfo.x86Flags >>  4 ) & 1;

-   cpucaps.hasModelSpecificRegisters                    = ( cpuinfo.x86Flags >>  5 ) & 1;

-   cpucaps.hasPhysicalAddressExtension                  = ( cpuinfo.x86Flags >>  6 ) & 1;

-   cpucaps.hasMachineCheckArchitecture                  = ( cpuinfo.x86Flags >>  7 ) & 1;

-   cpucaps.hasCOMPXCHG8BInstruction                     = ( cpuinfo.x86Flags >>  8 ) & 1;

-   cpucaps.hasAdvancedProgrammableInterruptController   = ( cpuinfo.x86Flags >>  9 ) & 1;

-   cpucaps.hasSEPFastSystemCall                         = ( cpuinfo.x86Flags >> 11 ) & 1;

-   cpucaps.hasMemoryTypeRangeRegisters                  = ( cpuinfo.x86Flags >> 12 ) & 1;

-   cpucaps.hasPTEGlobalFlag                             = ( cpuinfo.x86Flags >> 13 ) & 1;

-   cpucaps.hasMachineCheckArchitecture                  = ( cpuinfo.x86Flags >> 14 ) & 1;

-   cpucaps.hasConditionalMoveAndCompareInstructions     = ( cpuinfo.x86Flags >> 15 ) & 1;

-   cpucaps.hasFGPageAttributeTable                      = ( cpuinfo.x86Flags >> 16 ) & 1;

-   cpucaps.has36bitPageSizeExtension                    = ( cpuinfo.x86Flags >> 17 ) & 1;

-   cpucaps.hasProcessorSerialNumber                     = ( cpuinfo.x86Flags >> 18 ) & 1;

-   cpucaps.hasCFLUSHInstruction                         = ( cpuinfo.x86Flags >> 19 ) & 1;

-   cpucaps.hasDebugStore                                = ( cpuinfo.x86Flags >> 21 ) & 1;

-   cpucaps.hasACPIThermalMonitorAndClockControl         = ( cpuinfo.x86Flags >> 22 ) & 1;

-   cpucaps.hasMultimediaExtensions                      = ( cpuinfo.x86Flags >> 23 ) & 1; //mmx

-   cpucaps.hasFastStreamingSIMDExtensionsSaveRestore    = ( cpuinfo.x86Flags >> 24 ) & 1;

-   cpucaps.hasStreamingSIMDExtensions                   = ( cpuinfo.x86Flags >> 25 ) & 1; //sse

-   cpucaps.hasStreamingSIMD2Extensions                  = ( cpuinfo.x86Flags >> 26 ) & 1; //sse2

-   cpucaps.hasSelfSnoop                                 = ( cpuinfo.x86Flags >> 27 ) & 1;

-   cpucaps.hasHyperThreading                            = ( cpuinfo.x86Flags >> 28 ) & 1;

-   cpucaps.hasThermalMonitor                            = ( cpuinfo.x86Flags >> 29 ) & 1;

-   cpucaps.hasIntel64BitArchitecture                    = ( cpuinfo.x86Flags >> 30 ) & 1;

-    //that is only for AMDs

-   cpucaps.hasMultimediaExtensionsExt                   = ( cpuinfo.x86EFlags >> 22 ) & 1; //mmx2

-   cpucaps.hasAMD64BitArchitecture                      = ( cpuinfo.x86EFlags >> 29 ) & 1; //64bit cpu

-   cpucaps.has3DNOWInstructionExtensionsExt             = ( cpuinfo.x86EFlags >> 30 ) & 1; //3dnow+

-   cpucaps.has3DNOWInstructionExtensions                = ( cpuinfo.x86EFlags >> 31 ) & 1; //3dnow   

-   cpuinfo.cpuspeed = (u32 )(CPUSpeedHz( 1000 ) / 1000000);

-}

-

-#endif

+/*  Cpudetection lib 
+ *  Copyright (C) 2002-2003  Pcsx2 Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02111-1307 USA
+ */
+
+#ifdef __x86_64__
+
+#if defined (_WIN32)
+#include <windows.h>
+#endif
+
+#include <string.h>
+#include <stdio.h>
+
+#include "ix86-64.h"
+
+#if defined (_MSC_VER) && _MSC_VER >= 1400
+
+   void __cpuid(int* CPUInfo, int InfoType);
+   unsigned __int64 __rdtsc();
+
+   #pragma intrinsic(__cpuid)
+   #pragma intrinsic(__rdtsc)
+
+#endif
+
+CAPABILITIES cpucaps;
+CPUINFO cpuinfo;
+
+#define cpuid(cmd,a,b,c,d) \
+  __asm__ __volatile__("cpuid" \
+		: "=a" (a), "=b" (b), "=c" (c), "=d" (d)  : "0" (cmd))
+
+static s32 iCpuId( u32 cmd, u32 *regs ) 
+{
+   int flag=1;
+
+#if defined (_MSC_VER) && _MSC_VER >= 1400
+
+   __cpuid( regs, cmd );
+
+   return 0;
+
+#elif defined (_MSC_VER) 
+
+#ifdef __x86_64__
+   assert(0);
+#else // __x86_64__
+   __asm 
+   {
+      push ebx;
+      push edi;
+
+      pushfd;
+      pop eax;
+      mov edx, eax;
+      xor eax, 1 << 21;
+      push eax;
+      popfd;
+      pushfd;
+      pop eax;
+      xor eax, edx;
+      mov flag, eax;
+   }
+   if ( ! flag )
+   {
+      return -1;
+   }
+
+   __asm 
+   {
+      mov eax, cmd;
+      cpuid;
+      mov edi, [regs]
+      mov [edi], eax;
+      mov [edi+4], ebx;
+      mov [edi+8], ecx;
+      mov [edi+12], edx;
+
+      pop edi;
+      pop ebx;
+   }
+#endif // __x86_64__
+   return 0;
+
+
+#else
+
+#ifndef __x86_64__
+   // see if we can use cpuid
+   __asm__ __volatile__ (
+      "sub $0x18, %%esp\n"
+      "pushf\n"
+      "pop %%eax\n"
+      "mov %%eax, %%edx\n"
+      "xor $0x200000, %%eax\n"
+      "push %%eax\n"
+      "popf\n"
+      "pushf\n"
+      "pop %%eax\n"
+      "xor %%edx, %%eax\n"
+      "mov %%eax, %0\n"
+	  "add $0x18, %%esp\n"
+      : "=r"(flag) :
+   );
+#endif
+
+   if ( !flag )
+       return -1;
+
+   cpuid(cmd, regs[0], regs[1], regs[2], regs[3]);
+   return 0;
+#endif // _MSC_VER
+}
+
+u64 GetCPUTick( void ) 
+{
+#if defined (_MSC_VER) && _MSC_VER >= 1400
+
+   return __rdtsc();
+
+#elif defined(__MSCW32__) && !defined(__x86_64__)
+
+   __asm rdtsc;
+
+#else
+
+   u32 _a, _d;
+	__asm__ __volatile__ ("rdtsc" : "=a"(_a), "=d"(_d));
+	return (u64)_a | ((u64)_d << 32);
+
+#endif
+}
+
+#if defined(__LINUX__) || defined(__APPLE__)
+
+#include <sys/time.h>
+#include <errno.h>
+//*
+static unsigned long timeGetTime2()
+{
+ struct timeval tv;
+ gettimeofday(&tv, 0);                                 // well, maybe there are better ways
+ return (unsigned long)tv.tv_sec * 1000 + tv.tv_usec/1000;            // to do that, but at least it works
+}
+//*/
+#endif
+
+static s64 CPUSpeedHz( unsigned int time )
+{
+   s64 timeStart, 
+            timeStop;
+   s64 startTick, 
+            endTick;
+   s64 overhead;
+
+   if( ! cpucaps.hasTimeStampCounter )
+   {
+      return 0; //check if function is supported
+   }
+
+	overhead = GetCPUTick() - GetCPUTick();
+	
+	timeStart = timeGetTime2( );
+	while( timeGetTime2( ) == timeStart ) 
+   {
+      timeStart = timeGetTime2( );
+   }
+	for(;;)
+	{
+		timeStop = timeGetTime2( );
+		if ( ( timeStop - timeStart ) > 1 )	
+		{
+			startTick = GetCPUTick( );
+			break;
+		}
+	}
+
+	timeStart = timeStop;
+	for(;;)
+	{
+		timeStop = timeGetTime2( );
+		if ( ( timeStop - timeStart ) > time )	
+		{
+			endTick = GetCPUTick( );
+			break;
+		}
+	}
+
+	return (s64)( ( endTick - startTick ) + ( overhead ) );
+}
+
+////////////////////////////////////////////////////
+void cpudetectInit( void ) 
+{
+   u32 regs[ 4 ];
+   u32 cmds;
+   u32 AMDspeed;
+   char AMDspeedString[10];
+   int cputype=0;            // Cpu type
+   //AMD 64 STUFF
+   u32 x86_64_8BITBRANDID = 0;
+   u32 x86_64_12BITBRANDID = 0;
+   memset( cpuinfo.x86ID, 0, sizeof( cpuinfo.x86ID ) );
+   cpuinfo.x86Family = 0;
+   cpuinfo.x86Model  = 0;
+   cpuinfo.x86PType  = 0;
+   cpuinfo.x86StepID = 0;
+   cpuinfo.x86Flags  = 0;
+   cpuinfo.x86EFlags = 0;
+   
+   if ( iCpuId( 0, regs ) == -1 ) return;
+
+   cmds = regs[ 0 ];
+   ((u32*)cpuinfo.x86ID)[ 0 ] = regs[ 1 ];
+   ((u32*)cpuinfo.x86ID)[ 1 ] = regs[ 3 ];
+   ((u32*)cpuinfo.x86ID)[ 2 ] = regs[ 2 ];
+   if ( cmds >= 0x00000001 ) 
+   {
+      if ( iCpuId( 0x00000001, regs ) != -1 )
+      {
+         cpuinfo.x86StepID =  regs[ 0 ]        & 0xf;
+         cpuinfo.x86Model  = (regs[ 0 ] >>  4) & 0xf;
+         cpuinfo.x86Family = (regs[ 0 ] >>  8) & 0xf;
+         cpuinfo.x86PType  = (regs[ 0 ] >> 12) & 0x3;
+         x86_64_8BITBRANDID = regs[1] & 0xff;
+         cpuinfo.x86Flags  =  regs[ 3 ];
+      }
+   }
+   if ( iCpuId( 0x80000000, regs ) != -1 )
+   {
+      cmds = regs[ 0 ];
+      if ( cmds >= 0x80000001 ) 
+      {
+		 if ( iCpuId( 0x80000001, regs ) != -1 )
+         {
+			x86_64_12BITBRANDID = regs[1] & 0xfff;
+            cpuinfo.x86EFlags = regs[ 3 ];
+            
+         }
+      }
+   }
+   switch(cpuinfo.x86PType)
+   {
+      case 0:
+         strcpy( cpuinfo.x86Type, "Standard OEM");
+         break;
+      case 1:
+         strcpy( cpuinfo.x86Type, "Overdrive");
+         break;
+      case 2:
+         strcpy( cpuinfo.x86Type, "Dual");
+         break;
+      case 3:
+         strcpy( cpuinfo.x86Type, "Reserved");
+         break;
+      default:
+         strcpy( cpuinfo.x86Type, "Unknown");
+         break;
+   }
+   if ( cpuinfo.x86ID[ 0 ] == 'G' ){ cputype=0;}//trick lines but if you know a way better ;p
+   if ( cpuinfo.x86ID[ 0 ] == 'A' ){ cputype=1;}
+   
+   if ( cputype == 0 ) //intel cpu
+   {
+      if( ( cpuinfo.x86Family >= 7 ) && ( cpuinfo.x86Family < 15 ) )
+      {
+         strcpy( cpuinfo.x86Fam, "Intel P6 family (Not PIV and Higher then PPro" );
+      }
+      else
+      {
+         switch( cpuinfo.x86Family )
+         {     
+            // Start at 486 because if it's below 486 there is no cpuid instruction
+            case 4:
+               strcpy( cpuinfo.x86Fam, "Intel 486" );
+               break;
+            case 5:     
+               switch( cpuinfo.x86Model )
+               {
+               case 4:
+               case 8:     // 0.25 �m
+                  strcpy( cpuinfo.x86Fam, "Intel Pentium (MMX)");
+                  break;
+               default:
+                  strcpy( cpuinfo.x86Fam, "Intel Pentium" );
+               }
+               break;
+            case 6:     
+               switch( cpuinfo.x86Model )
+               {
+               case 0:     // Pentium pro (P6 A-Step)
+               case 1:     // Pentium pro
+                  strcpy( cpuinfo.x86Fam, "Intel Pentium Pro" );
+                  break;
+
+               case 2:     // 66 MHz FSB
+               case 5:     // Xeon/Celeron (0.25 �m)
+               case 6:     // Internal L2 cache
+                  strcpy( cpuinfo.x86Fam, "Intel Pentium II" );
+                  break;
+
+               case 7:     // Xeon external L2 cache
+               case 8:     // Xeon/Celeron with 256 KB on-die L2 cache
+               case 10:    // Xeon/Celeron with 1 or 2 MB on-die L2 cache
+               case 11:    // Xeon/Celeron with Tualatin core, on-die cache
+                  strcpy( cpuinfo.x86Fam, "Intel Pentium III" );
+                  break;
+			   case 15:    // Core 2 Duo Allendale/Conroe
+				  strcpy( cpuinfo.x86Fam, "Intel Core 2 Duo" );
+				  break;
+
+               default:
+                  strcpy( cpuinfo.x86Fam, "Intel Pentium Pro (Unknown)" );
+               }
+               break;
+            case 15:
+               switch( cpuinfo.x86Model )
+               {
+               case 0:     // Willamette (A-Step)
+               case 1:     // Willamette 
+                  strcpy( cpuinfo.x86Fam, "Willamette Intel Pentium IV" );
+                  break;
+               case 2:     // Northwood 
+                  strcpy( cpuinfo.x86Fam, "Northwood Intel Pentium IV" );
+                  break;
+
+               default:
+                  strcpy( cpuinfo.x86Fam, "Intel Pentium IV (Unknown)" );
+                  break;
+               }
+               break;
+            default:
+               strcpy( cpuinfo.x86Fam, "Unknown Intel CPU" );
+         }
+      }
+   }
+   else if ( cputype == 1 ) //AMD cpu
+   {
+      if( cpuinfo.x86Family >= 7 )
+      {
+		  if((x86_64_12BITBRANDID !=0) || (x86_64_8BITBRANDID !=0))
+		  {
+		    if(x86_64_8BITBRANDID == 0 )
+		    {
+               switch((x86_64_12BITBRANDID >>6)& 0x3f)
+			   {
+			    case 4:
+				 strcpy(cpuinfo.x86Fam,"AMD Athlon(tm) 64 Processor");
+                 AMDspeed = 22 + (x86_64_12BITBRANDID & 0x1f);
+				 //AMDspeedString = strtol(AMDspeed, (char**)NULL,10);
+				 sprintf(AMDspeedString," %d",AMDspeed);
+				 strcat(AMDspeedString,"00+");
+				 strcat(cpuinfo.x86Fam,AMDspeedString);
+				 break;
+			    case 12: 
+				 strcpy(cpuinfo.x86Fam,"AMD Opteron(tm) Processor");
+				 break;
+			    case 5:
+				  strcpy( cpuinfo.x86Fam, "AMD Athlon X2 Processor" );
+				  AMDspeed = 22 + (x86_64_12BITBRANDID & 0x1f);
+				 //AMDspeedString = strtol(AMDspeed, (char**)NULL,10);
+				 sprintf(AMDspeedString," %d",AMDspeed);
+				 strcat(AMDspeedString,"00+");
+				 strcat(cpuinfo.x86Fam,AMDspeedString);
+                  break;
+			   case 44:
+				   strcpy( cpuinfo.x86Fam, "AMD Opteron(tm) Dual Core Processor" );
+                  break;
+			    default:
+				   strcpy(cpuinfo.x86Fam,"Unknown AMD 64 proccesor");
+				   
+			    }
+		     }
+		     else //8bit brand id is non zero
+		     {
+                strcpy(cpuinfo.x86Fam,"Unsupported yet AMD64 cpu");
+		     }
+		  }
+		  else
+		  {		 
+			  strcpy( cpuinfo.x86Fam, "AMD K7+ Processor" );
+		  }
+      }
+      else
+      {
+         switch ( cpuinfo.x86Family )
+         {
+            case 4:
+               switch( cpuinfo.x86Model )
+               {
+               case 14: 
+               case 15:       // Write-back enhanced
+                  strcpy( cpuinfo.x86Fam, "AMD 5x86 Processor" );
+                  break;
+
+               case 3:        // DX2
+               case 7:        // Write-back enhanced DX2
+               case 8:        // DX4
+               case 9:        // Write-back enhanced DX4
+                  strcpy( cpuinfo.x86Fam, "AMD 486 Processor" );
+                  break;
+			   			   
+
+               default:
+                  strcpy( cpuinfo.x86Fam, "AMD Unknown Processor" );
+
+               }
+               break;
+
+            case 5:     
+               switch( cpuinfo.x86Model)
+               {
+               case 0:     // SSA 5 (75, 90 and 100 Mhz)
+               case 1:     // 5k86 (PR 120 and 133 MHz)
+               case 2:     // 5k86 (PR 166 MHz)
+               case 3:     // K5 5k86 (PR 200 MHz)
+                  strcpy( cpuinfo.x86Fam, "AMD K5 Processor" );
+                  break;
+
+               case 6:     
+               case 7:     // (0.25 �m)
+               case 8:     // K6-2
+               case 9:     // K6-III
+               case 14:    // K6-2+ / K6-III+
+                  strcpy( cpuinfo.x86Fam, "AMD K6 Series Processor" );
+                  break;
+
+               default:
+                  strcpy( cpuinfo.x86Fam, "AMD Unknown Processor" );
+               }
+               break;
+            case 6:     
+               strcpy( cpuinfo.x86Fam, "AMD Athlon XP Processor" );
+               break;
+            default:
+               strcpy( cpuinfo.x86Fam, "Unknown AMD CPU" ); 
+         }
+      }
+   }
+   //capabilities
+   cpucaps.hasFloatingPointUnit                         = ( cpuinfo.x86Flags >>  0 ) & 1;
+   cpucaps.hasVirtual8086ModeEnhancements               = ( cpuinfo.x86Flags >>  1 ) & 1;
+   cpucaps.hasDebuggingExtensions                       = ( cpuinfo.x86Flags >>  2 ) & 1;
+   cpucaps.hasPageSizeExtensions                        = ( cpuinfo.x86Flags >>  3 ) & 1;
+   cpucaps.hasTimeStampCounter                          = ( cpuinfo.x86Flags >>  4 ) & 1;
+   cpucaps.hasModelSpecificRegisters                    = ( cpuinfo.x86Flags >>  5 ) & 1;
+   cpucaps.hasPhysicalAddressExtension                  = ( cpuinfo.x86Flags >>  6 ) & 1;
+   cpucaps.hasMachineCheckArchitecture                  = ( cpuinfo.x86Flags >>  7 ) & 1;
+   cpucaps.hasCOMPXCHG8BInstruction                     = ( cpuinfo.x86Flags >>  8 ) & 1;
+   cpucaps.hasAdvancedProgrammableInterruptController   = ( cpuinfo.x86Flags >>  9 ) & 1;
+   cpucaps.hasSEPFastSystemCall                         = ( cpuinfo.x86Flags >> 11 ) & 1;
+   cpucaps.hasMemoryTypeRangeRegisters                  = ( cpuinfo.x86Flags >> 12 ) & 1;
+   cpucaps.hasPTEGlobalFlag                             = ( cpuinfo.x86Flags >> 13 ) & 1;
+   cpucaps.hasMachineCheckArchitecture                  = ( cpuinfo.x86Flags >> 14 ) & 1;
+   cpucaps.hasConditionalMoveAndCompareInstructions     = ( cpuinfo.x86Flags >> 15 ) & 1;
+   cpucaps.hasFGPageAttributeTable                      = ( cpuinfo.x86Flags >> 16 ) & 1;
+   cpucaps.has36bitPageSizeExtension                    = ( cpuinfo.x86Flags >> 17 ) & 1;
+   cpucaps.hasProcessorSerialNumber                     = ( cpuinfo.x86Flags >> 18 ) & 1;
+   cpucaps.hasCFLUSHInstruction                         = ( cpuinfo.x86Flags >> 19 ) & 1;
+   cpucaps.hasDebugStore                                = ( cpuinfo.x86Flags >> 21 ) & 1;
+   cpucaps.hasACPIThermalMonitorAndClockControl         = ( cpuinfo.x86Flags >> 22 ) & 1;
+   cpucaps.hasMultimediaExtensions                      = ( cpuinfo.x86Flags >> 23 ) & 1; //mmx
+   cpucaps.hasFastStreamingSIMDExtensionsSaveRestore    = ( cpuinfo.x86Flags >> 24 ) & 1;
+   cpucaps.hasStreamingSIMDExtensions                   = ( cpuinfo.x86Flags >> 25 ) & 1; //sse
+   cpucaps.hasStreamingSIMD2Extensions                  = ( cpuinfo.x86Flags >> 26 ) & 1; //sse2
+   cpucaps.hasSelfSnoop                                 = ( cpuinfo.x86Flags >> 27 ) & 1;
+   cpucaps.hasHyperThreading                            = ( cpuinfo.x86Flags >> 28 ) & 1;
+   cpucaps.hasThermalMonitor                            = ( cpuinfo.x86Flags >> 29 ) & 1;
+   cpucaps.hasIntel64BitArchitecture                    = ( cpuinfo.x86Flags >> 30 ) & 1;
+    //that is only for AMDs
+   cpucaps.hasMultimediaExtensionsExt                   = ( cpuinfo.x86EFlags >> 22 ) & 1; //mmx2
+   cpucaps.hasAMD64BitArchitecture                      = ( cpuinfo.x86EFlags >> 29 ) & 1; //64bit cpu
+   cpucaps.has3DNOWInstructionExtensionsExt             = ( cpuinfo.x86EFlags >> 30 ) & 1; //3dnow+
+   cpucaps.has3DNOWInstructionExtensions                = ( cpuinfo.x86EFlags >> 31 ) & 1; //3dnow   
+   cpuinfo.cpuspeed = (u32 )(CPUSpeedHz( 1000 ) / 1000000);
+}
+
+#endif
diff --git a/libpcsxcore/ix86_64/ix86_mmx.c b/libpcsxcore/ix86_64/ix86_mmx.c
index 09784a9c..4df678f0 100644
--- a/libpcsxcore/ix86_64/ix86_mmx.c
+++ b/libpcsxcore/ix86_64/ix86_mmx.c
@@ -1,6 +1,7 @@
 // stop compiling if NORECBUILD build (only for Visual Studio)
 
-#ifdef __x86_64__
+/* note that ix86-64.h disables all MMX, so no point in compiling this, ever */
+#ifndef __x86_64__
 
 #if !(defined(_MSC_VER) && defined(PCSX2_NORECBUILD))
 
diff --git a/libpcsxcore/ix86_64/ix86_sse.c b/libpcsxcore/ix86_64/ix86_sse.c
index 8a4f0217..09907043 100644
--- a/libpcsxcore/ix86_64/ix86_sse.c
+++ b/libpcsxcore/ix86_64/ix86_sse.c
@@ -89,9 +89,6 @@ XMMSSEType g_xmmtypes[XMMREGS] = {0};
 
 
 
-void WriteRmOffset(x86IntRegType to, int offset);
-void WriteRmOffsetFrom(x86IntRegType to, x86IntRegType from, int offset);
-
 /* movups [r32][r32*scale] to xmm1 */
 void SSE_MOVUPSRmStoR( x86SSERegType to, x86IntRegType from, x86IntRegType from2, int scale )
 {
@@ -1326,24 +1323,6 @@ void SSE2EMU_MOVD_XMM_to_RmOffset(x86IntRegType to, x86SSERegType from, int offs
 	MOV32RtoRmOffset(to, EAX, offset);
 }
 
-#ifndef __x86_64__
-extern void SetMMXstate();
-
-void SSE2EMU_MOVDQ2Q_XMM_to_MM( x86MMXRegType to, x86SSERegType from)
-{
-	SSE_MOVLPS_XMM_to_M64(p, from);
-	MOVQMtoR(to, p);
-	SetMMXstate();
-}
-
-void SSE2EMU_MOVQ2DQ_MM_to_XMM( x86SSERegType to, x86MMXRegType from)
-{
-	MOVQRtoM(p, from);
-	SSE_MOVLPS_M64_to_XMM(to, p);
-	SetMMXstate();
-}
-#endif
-
 /****************************************************************************/
 /*  SSE2 Emulated functions for SSE CPU's by kekko							*/
 /****************************************************************************/
@@ -1398,16 +1377,7 @@ void SSE2EMU_MOVD_XMM_to_R( x86IntRegType to, x86SSERegType from ) {
 	MOV32RmtoR(to, to);
 }
 
-#ifndef __x86_64__
-extern void SetFPUstate();
-extern void _freeMMXreg(int mmxreg);
-#endif
-
 void SSE2EMU_CVTPS2DQ_XMM_to_XMM( x86SSERegType to, x86SSERegType from ) {
-#ifndef __x86_64__
-    SetFPUstate();
-	_freeMMXreg(7);
-#endif
 	SSE_MOVAPS_XMM_to_M128((uptr)f, from);
 	
 	FLD32((uptr)&f[0]);
@@ -1423,10 +1393,6 @@ void SSE2EMU_CVTPS2DQ_XMM_to_XMM( x86SSERegType to, x86SSERegType from ) {
 }
 
 void SSE2EMU_CVTDQ2PS_M128_to_XMM( x86SSERegType to, uptr from ) {
-#ifndef __x86_64__
-    SetFPUstate();
-	_freeMMXreg(7);
-#endif
 	FILD32(from);
 	FSTP32((uptr)&f[0]);
 	FILD32(from+4);