mtk: headers: update from CyanogenMod/mt6753_common

46 files changed, 5109 insertions, 77 deletions

diff --git a/kernel-headers/asm/cache.h b/kernel-headers/asm/cache.h
new file mode 100644
index 0000000..ea94fdd
--- /dev/null
+++ b/kernel-headers/asm/cache.h
@@ -0,0 +1,24 @@
+/****************************************************************************
+ ****************************************************************************
+ ***
+ ***   This header was automatically generated from a Linux kernel header
+ ***   of the same name, to make information necessary for userspace to
+ ***   call into the kernel available to libc.  It contains only constants,
+ ***   structures, and macros generated from the original header, and thus,
+ ***   contains no copyrightable information.
+ ***
+ ***   To edit the content of this header, modify the corresponding
+ ***   source file (e.g. under external/kernel-headers/original/) then
+ ***   run bionic/libc/kernel/tools/update_all.py
+ ***
+ ***   Any manual change here will be lost the next time this script will
+ ***   be run. You've been warned!
+ ***
+ ****************************************************************************
+ ****************************************************************************/
+#ifndef __ASMARM_CACHE_H
+#define __ASMARM_CACHE_H
+#define L1_CACHE_SHIFT 5
+#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
+/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
+#endif
diff --git a/kernel-headers/bits_api.h b/kernel-headers/bits_api.h
index 845b6d1..845b6d1 100644..100755
--- a/kernel-headers/bits_api.h
+++ b/kernel-headers/bits_api.h
diff --git a/kernel-headers/camera_fdvt.h b/kernel-headers/camera_fdvt.h
new file mode 100644
index 0000000..6ee8c1d
--- /dev/null
+++ b/kernel-headers/camera_fdvt.h
@@ -0,0 +1,59 @@
+#ifndef __CAMERA_FDVT_H__
+#define __CAMERA_FDVT_H__
+
+#include <linux/ioctl.h>
+#define FDVT_IOC_MAGIC    'N'
+
+
+typedef struct 
+{
+    unsigned int  *pAddr;
+    unsigned int  *pData;
+    unsigned int  u4Count;
+} MT6573FDVTRegIO;
+
+//below is control message
+#define MT6573FDVT_INIT_SETPARA_CMD       _IO(FDVT_IOC_MAGIC, 0x00)
+#define MT6573FDVTIOC_STARTFD_CMD         _IO(FDVT_IOC_MAGIC, 0x01)
+#define MT6573FDVTIOC_G_WAITIRQ           _IOR(FDVT_IOC_MAGIC, 0x02, unsigned int )
+#define MT6573FDVTIOC_T_SET_FDCONF_CMD    _IOW(FDVT_IOC_MAGIC, 0x03, MT6573FDVTRegIO)
+#define MT6573FDVTIOC_G_READ_FDREG_CMD    _IOWR(FDVT_IOC_MAGIC, 0x04, MT6573FDVTRegIO)
+#define MT6573FDVTIOC_T_SET_SDCONF_CMD    _IOW(FDVT_IOC_MAGIC, 0x05, MT6573FDVTRegIO)
+//#define FDVT_DESTROY_CMD                _IO(FDVT_IOC_MAGIC, 0x10)
+
+#define MT6573FDVTIOC_T_DUMPREG           _IO(FDVT_IOC_MAGIC, 0x80)
+
+//#define FDVT_SET_CMD_CMD            _IOW(FDVT_IOC_MAGIC, 0x03, unsigned int)
+//#define FDVT_SET_PWR_CMD            _IOW(FDVT_IOC_MAGIC, 0x04, unsigned int)
+//#define FDVT_SET_ISR_CMD            _IOW(FDVT_IOC_MAGIC, 0x05, unsigned int)
+//#define FDVT_GET_CACHECTRLADDR_CMD  _IOR(FDVT_IOC_MAGIC, 0x06, int)
+
+
+
+#endif //__CAMERA_FDVT_H__
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/kernel-headers/camera_isp.h b/kernel-headers/camera_isp.h
new file mode 100644
index 0000000..c94350e
--- /dev/null
+++ b/kernel-headers/camera_isp.h
@@ -0,0 +1,909 @@
+#ifndef _MT_ISP_H
+#define _MT_ISP_H
+
+#include <linux/ioctl.h>
+
+
+/**
+    enforce kernel log enable
+*/
+//#define KERNEL_LOG  //enable debug log flag if defined
+#define ISR_LOG_ON  //turn on log print at isr if defined
+
+#define T_STAMP_2_0 //time stamp workaround method. (increase timestamp baseon fix fps, not read at each isr)
+
+#define SIG_ERESTARTSYS 512 //ERESTARTSYS
+/*******************************************************************************
+*
+********************************************************************************/
+#define ISP_DEV_MAJOR_NUMBER    251
+#define ISP_MAGIC               'k'
+/*******************************************************************************
+*
+********************************************************************************/
+//CAM_CTL_INT_P1_STATUS
+#define ISP_IRQ_P1_STATUS_VS1_INT_ST                ((unsigned int)1<<0)
+#define ISP_IRQ_P1_STATUS_TG1_INT1_ST               ((unsigned int)1<<1)
+#define ISP_IRQ_P1_STATUS_TG1_INT2_ST               ((unsigned int)1<<2)
+#define ISP_IRQ_P1_STATUS_EXPDON1_ST                ((unsigned int)1<<3)
+#define ISP_IRQ_P1_STATUS_TG1_ERR_ST                ((unsigned int)1<<4)
+#define ISP_IRQ_P1_STATUS_TG1_GBERR                 ((unsigned int)1<<5)
+#define ISP_IRQ_P1_STATUS_CQ0_ERR                   ((unsigned int)1<<6)
+#define ISP_IRQ_P1_STATUS_CQ0_VS_ERR_ST             ((unsigned int)1<<7)
+#define ISP_IRQ_P1_STATUS_IMGO_DROP_FRAME_ST        ((unsigned int)1<<8)
+#define ISP_IRQ_P1_STATUS_RRZO_DROP_FRAME_ST        ((unsigned int)1<<9)
+#define ISP_IRQ_P1_STATUS_PASS1_DON_ST              ((unsigned int)1<<10)
+#define ISP_IRQ_P1_STATUS_rsv_11                    ((unsigned int)1<<11)
+#define ISP_IRQ_P1_STATUS_SOF1_INT_ST               ((unsigned int)1<<12)
+#define ISP_IRQ_P1_STATUS_rsv_13                    ((unsigned int)1<<13)
+#define ISP_IRQ_P1_STATUS_PESUDO_P1_DON_ST          ((unsigned int)1<<15)
+#define ISP_IRQ_P1_STATUS_AF_DON_ST                 ((unsigned int)1<<16)
+#define ISP_IRQ_P1_STATUS_FLK_DON_ST                ((unsigned int)1<<17)
+#define ISP_IRQ_P1_STATUS_rsv_18                    ((unsigned int)1<<18)
+#define ISP_IRQ_P1_STATUS_IMGO_ERR_ST               ((unsigned int)1<<20)
+#define ISP_IRQ_P1_STATUS_AAO_ERR_ST                ((unsigned int)1<<21)
+#define ISP_IRQ_P1_STATUS_LCSO_ERR_ST               ((unsigned int)1<<22)
+#define ISP_IRQ_P1_STATUS_RRZO_ERR_ST               ((unsigned int)1<<23)
+#define ISP_IRQ_P1_STATUS_ESFKO_ERR_ST              ((unsigned int)1<<24)
+#define ISP_IRQ_P1_STATUS_FLK_ERR_ST                ((unsigned int)1<<25)
+#define ISP_IRQ_P1_STATUS_LSC_ERR_ST                ((unsigned int)1<<26)
+#define ISP_IRQ_P1_STATUS_FBC_RRZO_DON_ST           ((unsigned int)1<<27)
+#define ISP_IRQ_P1_STATUS_FBC_IMGO_DON_ST           ((unsigned int)1<<28)
+#define ISP_IRQ_P1_STATUS_rsv_29                    ((unsigned int)1<<29)
+#define ISP_IRQ_P1_STATUS_DMA_ERR_ST                ((unsigned int)1<<30)
+#define ISP_IRQ_P1_STATUS_rsv_31                    ((unsigned int)1<<31)
+//CAM_CTL_INT_P1_STATUS2
+#define ISP_IRQ_P1_STATUS2_IMGO_DONE_ST              ((unsigned int)1<<0)
+#define ISP_IRQ_P1_STATUS2_UFEO_DONE_ST              ((unsigned int)1<<1)
+#define ISP_IRQ_P1_STATUS2_RRZO_DONE_ST              ((unsigned int)1<<2)
+#define ISP_IRQ_P1_STATUS2_ESFKO_DONE_ST             ((unsigned int)1<<3)
+#define ISP_IRQ_P1_STATUS2_LCSO_DONE_ST              ((unsigned int)1<<4)
+#define ISP_IRQ_P1_STATUS2_AAO_DONE_ST               ((unsigned int)1<<5)
+#define ISP_IRQ_P1_STATUS2_BPCI_DONE_ST              ((unsigned int)1<<6)
+#define ISP_IRQ_P1_STATUS2_LSCI_DONE_ST              ((unsigned int)1<<7)
+#define ISP_IRQ_P1_STATUS2_AF_TAR_DONE_ST            ((unsigned int)1<<8)
+#define ISP_IRQ_P1_STATUS2_AF_FLO1_DONE_ST           ((unsigned int)1<<9)
+#define ISP_IRQ_P1_STATUS2_AF_FLO2_DONE_ST           ((unsigned int)1<<10)
+#define ISP_IRQ_P1_STATUS2_AF_FLO3_DONE_ST           ((unsigned int)1<<11)
+#define ISP_IRQ_P1_STATUS2_rsv_12                    ((unsigned int)1<<12)
+//CAM_CTL_INT_P1_STATUS_D
+#define ISP_IRQ_P1_STATUS_D_VS1_INT_ST                ((unsigned int)1<<0)
+#define ISP_IRQ_P1_STATUS_D_TG1_INT1_ST               ((unsigned int)1<<1)
+#define ISP_IRQ_P1_STATUS_D_TG1_INT2_ST               ((unsigned int)1<<2)
+#define ISP_IRQ_P1_STATUS_D_EXPDON1_ST                ((unsigned int)1<<3)
+#define ISP_IRQ_P1_STATUS_D_TG1_ERR_ST                ((unsigned int)1<<4)
+#define ISP_IRQ_P1_STATUS_D_TG1_GBERR                 ((unsigned int)1<<5)
+#define ISP_IRQ_P1_STATUS_D_CQ0_ERR                   ((unsigned int)1<<6)
+#define ISP_IRQ_P1_STATUS_D_CQ0_VS_ERR_ST             ((unsigned int)1<<7)
+#define ISP_IRQ_P1_STATUS_D_IMGO_DROP_FRAME_ST        ((unsigned int)1<<8)
+#define ISP_IRQ_P1_STATUS_D_RRZO_DROP_FRAME_ST        ((unsigned int)1<<9)
+#define ISP_IRQ_P1_STATUS_D_PASS1_DON_ST              ((unsigned int)1<<10)
+#define ISP_IRQ_P1_STATUS_D_rsv_11                    ((unsigned int)1<<11)
+#define ISP_IRQ_P1_STATUS_D_SOF1_INT_ST               ((unsigned int)1<<12)
+#define ISP_IRQ_P1_STATUS_D_rsv_13                    ((unsigned int)1<<13)
+#define ISP_IRQ_P1_STATUS_D_PESUDO_P1_DON_ST          ((unsigned int)1<<15)
+#define ISP_IRQ_P1_STATUS_D_AF_DON_ST                 ((unsigned int)1<<16)
+#define ISP_IRQ_P1_STATUS_D_rsv_17                    ((unsigned int)1<<17)
+#define ISP_IRQ_P1_STATUS_D_IMGO_ERR_ST               ((unsigned int)1<<20)
+#define ISP_IRQ_P1_STATUS_D_AAO_ERR_ST                ((unsigned int)1<<21)
+#define ISP_IRQ_P1_STATUS_D_LCSO_ERR_ST               ((unsigned int)1<<22)
+#define ISP_IRQ_P1_STATUS_D_RRZO_ERR_ST               ((unsigned int)1<<23)
+#define ISP_IRQ_P1_STATUS_D_AFO_ERR_ST                ((unsigned int)1<<24)
+#define ISP_IRQ_P1_STATUS_D_rsv_25                    ((unsigned int)1<<25)
+#define ISP_IRQ_P1_STATUS_D_LSC_ERR_ST                ((unsigned int)1<<26)
+#define ISP_IRQ_P1_STATUS_D_FBC_RRZO_DON_ST           ((unsigned int)1<<27)
+#define ISP_IRQ_P1_STATUS_D_FBC_IMGO_DON_ST           ((unsigned int)1<<28)
+#define ISP_IRQ_P1_STATUS_D_rsv_29                    ((unsigned int)1<<29)
+#define ISP_IRQ_P1_STATUS_D_DMA_ERR_ST                ((unsigned int)1<<30)
+#define ISP_IRQ_P1_STATUS_D_rsv_31                    ((unsigned int)1<<31)
+//CAM_CTL_INT_P1_STATUS2_D
+#define ISP_IRQ_P1_STATUS2_D_IMGO_D_DONE_ST            ((unsigned int)1<<0)
+#define ISP_IRQ_P1_STATUS2_D_rsv_1                     ((unsigned int)1<<1)
+#define ISP_IRQ_P1_STATUS2_D_RRZO_D_DONE_ST            ((unsigned int)1<<2)
+#define ISP_IRQ_P1_STATUS2_D_AFO_D_DONE_ST             ((unsigned int)1<<3)
+#define ISP_IRQ_P1_STATUS2_D_LCSO_D_DONE_ST            ((unsigned int)1<<4)
+#define ISP_IRQ_P1_STATUS2_D_AAO_D_DONE_ST             ((unsigned int)1<<5)
+#define ISP_IRQ_P1_STATUS2_D_BPCI_D_DONE_ST            ((unsigned int)1<<6)
+#define ISP_IRQ_P1_STATUS2_D_LSCI_D_DONE_ST            ((unsigned int)1<<7)
+#define ISP_IRQ_P1_STATUS2_D_AF_TAR_DONE_ST            ((unsigned int)1<<8)
+#define ISP_IRQ_P1_STATUS2_D_AF_FLO1_DONE_ST           ((unsigned int)1<<9)
+#define ISP_IRQ_P1_STATUS2_D_AF_FLO2_DONE_ST           ((unsigned int)1<<10)
+#define ISP_IRQ_P1_STATUS2_D_AF_FLO3_DONE_ST           ((unsigned int)1<<11)
+#define ISP_IRQ_P1_STATUS2_D_rsv_12                    ((unsigned int)1<<12)
+//CAM_CTL_SEL_P1
+#define ISP_CAM_CTL_SEL_P1_IMGO_SEL                    ((unsigned int)1<<6)
+//CAM_CTL_SEL_P1_D
+#define ISP_CAM_CTL_SEL_P1_D_IMGO_SEL                  ((unsigned int)1<<6)
+//CAM_CTL_INT_P2_STATUS
+#define ISP_IRQ_P2_STATUS_CQ_ERR_ST                 ((unsigned int)1<<0)
+#define ISP_IRQ_P2_STATUS_PASS2_DON_ST              ((unsigned int)1<<1)
+#define ISP_IRQ_P2_STATUS_TILE_DON_ST               ((unsigned int)1<<2)
+#define ISP_IRQ_P2_STATUS_CQ_DON_ST                 ((unsigned int)1<<3)
+#define ISP_IRQ_P2_STATUS_TDR_ERR_ST                ((unsigned int)1<<4)
+#define ISP_IRQ_P2_STATUS_PASS2A_DON_ST             ((unsigned int)1<<5)
+#define ISP_IRQ_P2_STATUS_PASS2B_DON_ST             ((unsigned int)1<<6)
+#define ISP_IRQ_P2_STATUS_PASS2C_DON_ST             ((unsigned int)1<<7)
+#define ISP_IRQ_P2_STATUS_CQ1_DONE_ST               ((unsigned int)1<<8)
+#define ISP_IRQ_P2_STATUS_CQ2_DONE_ST               ((unsigned int)1<<9)
+#define ISP_IRQ_P2_STATUS_CQ3_DONE_ST               ((unsigned int)1<<10)
+#define ISP_IRQ_P2_STATUS_PASS2A_ERR_TRIG_ST        ((unsigned int)1<<11)
+#define ISP_IRQ_P2_STATUS_PASS2B_ERR_TRIG_ST        ((unsigned int)1<<12)
+#define ISP_IRQ_P2_STATUS_PASS2C_ERR_TRIG_ST        ((unsigned int)1<<13)
+#define ISP_IRQ_P2_STATUS_IMGI_DONE_ST              ((unsigned int)1<<15)
+#define ISP_IRQ_P2_STATUS_UFDI_DONE_ST              ((unsigned int)1<<16)
+#define ISP_IRQ_P2_STATUS_VIPI_DONE_ST              ((unsigned int)1<<17)
+#define ISP_IRQ_P2_STATUS_VIP2I_DONE_ST             ((unsigned int)1<<18)
+#define ISP_IRQ_P2_STATUS_VIP3I_DONE_ST             ((unsigned int)1<<19)
+#define ISP_IRQ_P2_STATUS_LCEI_DONE_ST              ((unsigned int)1<<20)
+#define ISP_IRQ_P2_STATUS_MFBO_DONE_ST              ((unsigned int)1<<21)
+#define ISP_IRQ_P2_STATUS_IMG2O_DONE_ST             ((unsigned int)1<<22)
+#define ISP_IRQ_P2_STATUS_IMG3O_DONE_ST             ((unsigned int)1<<23)
+#define ISP_IRQ_P2_STATUS_IMG3BO_DONE_ST            ((unsigned int)1<<24)
+#define ISP_IRQ_P2_STATUS_IMG3CO_DONE_ST            ((unsigned int)1<<25)
+#define ISP_IRQ_P2_STATUS_FEO_DONE_ST               ((unsigned int)1<<26)
+#define ISP_IRQ_P2_STATUS_rsv_27                    ((unsigned int)1<<27)
+//CAM_CTL_INT_STATUSX //P1 AND P2
+#define ISP_IRQ_STATUSX_VS1_INT_ST                ((unsigned int)1<<0)
+#define ISP_IRQ_STATUSX_TG1_INT1_ST               ((unsigned int)1<<1)
+#define ISP_IRQ_STATUSX_TG1_INT2_ST               ((unsigned int)1<<2)
+#define ISP_IRQ_STATUSX_EXPDON1_ST                ((unsigned int)1<<3)
+#define ISP_IRQ_STATUSX_TG1_ERR_ST                ((unsigned int)1<<4)
+#define ISP_IRQ_STATUSX_TG1_GBERR                 ((unsigned int)1<<5)
+#define ISP_IRQ_STATUSX_CQ0_ERR                   ((unsigned int)1<<6)
+#define ISP_IRQ_STATUSX_CQ0_VS_ERR_ST             ((unsigned int)1<<7)
+#define ISP_IRQ_STATUSX_IMGO_DROP_FRAME_ST        ((unsigned int)1<<8)
+#define ISP_IRQ_STATUSX_RRZO_DROP_FRAME_ST        ((unsigned int)1<<9)
+#define ISP_IRQ_STATUSX_PASS1_DON_ST              ((unsigned int)1<<10)
+#define ISP_IRQ_STATUSX_rsv_11                    ((unsigned int)1<<11)
+#define ISP_IRQ_STATUSX_SOF1_INT_ST               ((unsigned int)1<<12)
+#define ISP_IRQ_STATUSX_CQ_ERR_ST                 ((unsigned int)1<<13)
+#define ISP_IRQ_STATUSX_PASS2_DON_ST              ((unsigned int)1<<14)
+#define ISP_IRQ_STATUSX_TILE_DON_ST               ((unsigned int)1<<15)
+#define ISP_IRQ_STATUSX_AF_DON_ST                 ((unsigned int)1<<16)
+#define ISP_IRQ_STATUSX_FLK_DON_ST                ((unsigned int)1<<17)
+#define ISP_IRQ_STATUSX_rsv_18					  ((unsigned int)1<<18)
+#define ISP_IRQ_STATUSX_CQ_DON_ST                 ((unsigned int)1<<19)
+#define ISP_IRQ_STATUSX_IMGO_ERR_ST               ((unsigned int)1<<20)
+#define ISP_IRQ_STATUSX_AAO_ERR_ST                ((unsigned int)1<<21)
+#define ISP_IRQ_STATUSX_LCSO_ERR_ST               ((unsigned int)1<<22)
+#define ISP_IRQ_STATUSX_RRZO_ERR_ST               ((unsigned int)1<<23)
+#define ISP_IRQ_STATUSX_ESFKO_ERR_ST              ((unsigned int)1<<24)
+#define ISP_IRQ_STATUSX_FLK_ERR_ST                ((unsigned int)1<<25)
+#define ISP_IRQ_STATUSX_LSC_ERR_ST                ((unsigned int)1<<26)
+#define ISP_IRQ_STATUSX_FBC_RRZO_DON_ST           ((unsigned int)1<<27)
+#define ISP_IRQ_STATUSX_FBC_IMGO_DON_ST           ((unsigned int)1<<28)
+#define ISP_IRQ_STATUSX_rsv_29                    ((unsigned int)1<<29)
+#define ISP_IRQ_STATUSX_DMA_ERR_ST                ((unsigned int)1<<30)
+#define ISP_IRQ_STATUSX_rsv_31                    ((unsigned int)1<<31)
+//CAM_CTL_INT_STATUS2X //P1_D
+#define ISP_IRQ_STATUS2X_VS1_INT_ST                ((unsigned int)1<<0)
+#define ISP_IRQ_STATUS2X_TG1_INT1_ST               ((unsigned int)1<<1)
+#define ISP_IRQ_STATUS2X_TG1_INT2_ST               ((unsigned int)1<<2)
+#define ISP_IRQ_STATUS2X_EXPDON1_ST                ((unsigned int)1<<3)
+#define ISP_IRQ_STATUS2X_TG1_ERR_ST                ((unsigned int)1<<4)
+#define ISP_IRQ_STATUS2X_TG1_GBERR                 ((unsigned int)1<<5)
+#define ISP_IRQ_STATUS2X_CQ0_ERR                   ((unsigned int)1<<6)
+#define ISP_IRQ_STATUS2X_CQ0_VS_ERR_ST             ((unsigned int)1<<7)
+#define ISP_IRQ_STATUS2X_IMGO_DROP_FRAME_ST        ((unsigned int)1<<8)
+#define ISP_IRQ_STATUS2X_RRZO_DROP_FRAME_ST        ((unsigned int)1<<9)
+#define ISP_IRQ_STATUS2X_PASS1_DON_ST              ((unsigned int)1<<10)
+#define ISP_IRQ_STATUS2X_rsv_11                    ((unsigned int)1<<11)
+#define ISP_IRQ_STATUS2X_SOF1_INT_ST               ((unsigned int)1<<12)
+#define ISP_IRQ_STATUS2X_rsv_13                    ((unsigned int)1<<13)
+#define ISP_IRQ_STATUS2X_rsv_14                    ((unsigned int)1<<14)
+#define ISP_IRQ_STATUS2X_rsv_15                    ((unsigned int)1<<15)
+#define ISP_IRQ_STATUS2X_AF_DON_ST                 ((unsigned int)1<<16)
+#define ISP_IRQ_STATUS2X_rsv_17                    ((unsigned int)1<<17)
+#define ISP_IRQ_STATUS2X_rsv_18					   ((unsigned int)1<<18)
+#define ISP_IRQ_STATUS2X_rsv_19                    ((unsigned int)1<<19)
+#define ISP_IRQ_STATUS2X_IMGO_ERR_ST               ((unsigned int)1<<20)
+#define ISP_IRQ_STATUS2X_AAO_ERR_ST                ((unsigned int)1<<21)
+#define ISP_IRQ_STATUS2X_LCSO_ERR_ST               ((unsigned int)1<<22)
+#define ISP_IRQ_STATUS2X_RRZO_ERR_ST               ((unsigned int)1<<23)
+#define ISP_IRQ_STATUS2X_AFO_ERR_ST                ((unsigned int)1<<24)
+#define ISP_IRQ_STATUS2X_rsv_25                    ((unsigned int)1<<25)
+#define ISP_IRQ_STATUS2X_LSC_ERR_ST                ((unsigned int)1<<26)
+#define ISP_IRQ_STATUS2X_FBC_RRZO_DON_ST           ((unsigned int)1<<27)
+#define ISP_IRQ_STATUS2X_FBC_IMGO_DON_ST           ((unsigned int)1<<28)
+#define ISP_IRQ_STATUS2X_rsv_29                    ((unsigned int)1<<29)
+#define ISP_IRQ_STATUS2X_DMA_ERR_ST                ((unsigned int)1<<30)
+#define ISP_IRQ_STATUS2X_rsv_31                    ((unsigned int)1<<31)
+//ISP_IRQ_STATUS3X //ALL DMA
+#define ISP_IRQ_STATUS3X_IMGO_DONE_ST              ((unsigned int)1<<0)
+#define ISP_IRQ_STATUS3X_UFEO_DONE_ST              ((unsigned int)1<<1)
+#define ISP_IRQ_STATUS3X_RRZO_DONE_ST              ((unsigned int)1<<2)
+#define ISP_IRQ_STATUS3X_ESFKO_DONE_ST             ((unsigned int)1<<3)
+#define ISP_IRQ_STATUS3X_LCSO_DONE_ST              ((unsigned int)1<<4)
+#define ISP_IRQ_STATUS3X_AAO_DONE_ST               ((unsigned int)1<<5)
+#define ISP_IRQ_STATUS3X_BPCI_DONE_ST              ((unsigned int)1<<6)
+#define ISP_IRQ_STATUS3X_LSCI_DONE_ST              ((unsigned int)1<<7)
+#define ISP_IRQ_STATUS3X_IMGO_D_DONE_ST            ((unsigned int)1<<8)
+#define ISP_IRQ_STATUS3X_RRZO_D_DONE_ST            ((unsigned int)1<<9)
+#define ISP_IRQ_STATUS3X_AFO_D_DONE_ST             ((unsigned int)1<<10)
+#define ISP_IRQ_STATUS3X_LCSO_D_DONE_ST            ((unsigned int)1<<11)
+#define ISP_IRQ_STATUS3X_AAO_D_DONE_ST             ((unsigned int)1<<12)
+#define ISP_IRQ_STATUS3X_BPCI_D_DONE_ST            ((unsigned int)1<<13)
+#define ISP_IRQ_STATUS3X_LCSI_D_DONE_ST            ((unsigned int)1<<14)
+#define ISP_IRQ_STATUS3X_IMGI_DONE_ST              ((unsigned int)1<<15)
+#define ISP_IRQ_STATUS3X_UFDI_DONE_ST              ((unsigned int)1<<16)
+#define ISP_IRQ_STATUS3X_VIPI_DONE_ST              ((unsigned int)1<<17)
+#define ISP_IRQ_STATUS3X_VIP2I_DONE_ST			   ((unsigned int)1<<18)
+#define ISP_IRQ_STATUS3X_VIP3I_DONE_ST             ((unsigned int)1<<19)
+#define ISP_IRQ_STATUS3X_LCEI_DONE_ST              ((unsigned int)1<<20)
+#define ISP_IRQ_STATUS3X_MFBO_DONE_ST              ((unsigned int)1<<21)
+#define ISP_IRQ_STATUS3X_IMG2O_DONE_ST             ((unsigned int)1<<22)
+#define ISP_IRQ_STATUS3X_IMG3O_DONE_ST             ((unsigned int)1<<23)
+#define ISP_IRQ_STATUS3X_IMG3BO_DONE_ST            ((unsigned int)1<<24)
+#define ISP_IRQ_STATUS3X_IMG3CO_DONE_ST            ((unsigned int)1<<25)
+#define ISP_IRQ_STATUS3X_FEO_DONE_ST               ((unsigned int)1<<26)
+#define ISP_IRQ_STATUS3X_rsv_27                    ((unsigned int)1<<27)
+#define ISP_IRQ_STATUS3X_rsv_28                    ((unsigned int)1<<28)
+#define ISP_IRQ_STATUS3X_rsv_29                    ((unsigned int)1<<29)
+#define ISP_IRQ_STATUS3X_rsv_30                    ((unsigned int)1<<30)
+#define ISP_IRQ_STATUS3X_rsv_31                    ((unsigned int)1<<31)
+//SENINF1_IRQ_INTSTA
+#define SENINF1_IRQ_OVERRUN_IRQ_STA					   ((unsigned int)1<<0)
+#define SENINF1_IRQ_CRCERR_IRQ_STA					   ((unsigned int)1<<1)
+#define SENINF1_IRQ_FSMERR_IRQ_STA					   ((unsigned int)1<<2)
+#define SENINF1_IRQ_VSIZEERR_IRQ_STA				   ((unsigned int)1<<3)
+#define SENINF1_IRQ_HSIZEERR_IRQ_STA				   ((unsigned int)1<<4)
+#define SENINF1_IRQ_SENSOR_VSIZEERR_IRQ_STA			   ((unsigned int)1<<5)
+#define SENINF1_IRQ_SENSOR_HSIZEERR_IRQ_STA			   ((unsigned int)1<<6)
+//SENINF2_IRQ_INTSTA
+#define SENINF2_IRQ_OVERRUN_IRQ_STA					   ((unsigned int)1<<0)
+#define SENINF2_IRQ_CRCERR_IRQ_STA					   ((unsigned int)1<<1)
+#define SENINF2_IRQ_FSMERR_IRQ_STA					   ((unsigned int)1<<2)
+#define SENINF2_IRQ_VSIZEERR_IRQ_STA				   ((unsigned int)1<<3)
+#define SENINF2_IRQ_HSIZEERR_IRQ_STA				   ((unsigned int)1<<4)
+#define SENINF2_IRQ_SENSOR_VSIZEERR_IRQ_STA			   ((unsigned int)1<<5)
+#define SENINF2_IRQ_SENSOR_HSIZEERR_IRQ_STA			   ((unsigned int)1<<6)
+//SENINF3_IRQ_INTSTA
+#define SENINF3_IRQ_OVERRUN_IRQ_STA					   ((unsigned int)1<<0)
+#define SENINF3_IRQ_CRCERR_IRQ_STA					   ((unsigned int)1<<1)
+#define SENINF3_IRQ_FSMERR_IRQ_STA					   ((unsigned int)1<<2)
+#define SENINF3_IRQ_VSIZEERR_IRQ_STA				   ((unsigned int)1<<3)
+#define SENINF3_IRQ_HSIZEERR_IRQ_STA				   ((unsigned int)1<<4)
+#define SENINF3_IRQ_SENSOR_VSIZEERR_IRQ_STA			   ((unsigned int)1<<5)
+#define SENINF3_IRQ_SENSOR_HSIZEERR_IRQ_STA			   ((unsigned int)1<<6)
+//SENINF4_IRQ_INTSTA
+#define SENINF4_IRQ_OVERRUN_IRQ_STA					   ((unsigned int)1<<0)
+#define SENINF4_IRQ_CRCERR_IRQ_STA					   ((unsigned int)1<<1)
+#define SENINF4_IRQ_FSMERR_IRQ_STA					   ((unsigned int)1<<2)
+#define SENINF4_IRQ_VSIZEERR_IRQ_STA				   ((unsigned int)1<<3)
+#define SENINF4_IRQ_HSIZEERR_IRQ_STA				   ((unsigned int)1<<4)
+#define SENINF4_IRQ_SENSOR_VSIZEERR_IRQ_STA			   ((unsigned int)1<<5)
+#define SENINF4_IRQ_SENSOR_HSIZEERR_IRQ_STA			   ((unsigned int)1<<6)
+//REG_CAMSV_INT_STATUS
+#define ISP_IRQ_CAMSV_STATUS_VS1_ST						((unsigned int)1<<0)
+#define ISP_IRQ_CAMSV_STATUS_TG_ST1						((unsigned int)1<<1)
+#define ISP_IRQ_CAMSV_STATUS_TG_ST2						((unsigned int)1<<2)
+#define ISP_IRQ_CAMSV_STATUS_EXPDON1_ST					((unsigned int)1<<3)
+#define ISP_IRQ_CAMSV_STATUS_TG_ERR_ST					((unsigned int)1<<4)
+#define ISP_IRQ_CAMSV_STATUS_TG_GBERR_ST				((unsigned int)1<<5)
+#define ISP_IRQ_CAMSV_STATUS_TG_DROP_ST					((unsigned int)1<<6)
+#define ISP_IRQ_CAMSV_STATUS_TG_SOF1_ST					((unsigned int)1<<7)
+#define ISP_IRQ_CAMSV_STATUS_rsv_8						((unsigned int)1<<8)
+#define ISP_IRQ_CAMSV_STATUS_rsv_9						((unsigned int)1<<9)
+#define ISP_IRQ_CAMSV_STATUS_PASS1_DON_ST				((unsigned int)1<<10)
+#define ISP_IRQ_CAMSV_STATUS_rsv_11						((unsigned int)1<<11)
+#define ISP_IRQ_CAMSV_STATUS_rsv_12						((unsigned int)1<<12)
+#define ISP_IRQ_CAMSV_STATUS_rsv_13						((unsigned int)1<<13)
+#define ISP_IRQ_CAMSV_STATUS_rsv_14						((unsigned int)1<<14)
+#define ISP_IRQ_CAMSV_STATUS_rsv_15						((unsigned int)1<<15)
+#define ISP_IRQ_CAMSV_STATUS_IMGO_ERR_ST				((unsigned int)1<<16)
+#define ISP_IRQ_CAMSV_STATUS_IMGO_OVERR_ST				((unsigned int)1<<17)
+#define ISP_IRQ_CAMSV_STATUS_rsv_18						((unsigned int)1<<18)
+#define ISP_IRQ_CAMSV_STATUS_IMGO_DROP_ST				((unsigned int)1<<19)
+//REG_ISP_IRQ_CAMSV2_STATUS
+#define ISP_IRQ_CAMSV2_STATUS_VS1_ST					((unsigned int)1<<0)
+#define ISP_IRQ_CAMSV2_STATUS_TG_ST1					((unsigned int)1<<1)
+#define ISP_IRQ_CAMSV2_STATUS_TG_ST2					((unsigned int)1<<2)
+#define ISP_IRQ_CAMSV2_STATUS_EXPDON1_ST				((unsigned int)1<<3)
+#define ISP_IRQ_CAMSV2_STATUS_TG_ERR_ST					((unsigned int)1<<4)
+#define ISP_IRQ_CAMSV2_STATUS_TG_GBERR_ST				((unsigned int)1<<5)
+#define ISP_IRQ_CAMSV2_STATUS_TG_DROP_ST				((unsigned int)1<<6)
+#define ISP_IRQ_CAMSV2_STATUS_TG_SOF1_ST				((unsigned int)1<<7)
+#define ISP_IRQ_CAMSV2_STATUS_rsv_8						((unsigned int)1<<8)
+#define ISP_IRQ_CAMSV2_STATUS_rsv_9						((unsigned int)1<<9)
+#define ISP_IRQ_CAMSV2_STATUS_PASS1_DON_ST				((unsigned int)1<<10)
+#define ISP_IRQ_CAMSV2_STATUS_rsv_11					((unsigned int)1<<11)
+#define ISP_IRQ_CAMSV2_STATUS_rsv_12					((unsigned int)1<<12)
+#define ISP_IRQ_CAMSV2_STATUS_rsv_13					((unsigned int)1<<13)
+#define ISP_IRQ_CAMSV2_STATUS_rsv_14					((unsigned int)1<<14)
+#define ISP_IRQ_CAMSV2_STATUS_rsv_15					((unsigned int)1<<15)
+#define ISP_IRQ_CAMSV2_STATUS_IMGO_ERR_ST				((unsigned int)1<<16)
+#define ISP_IRQ_CAMSV2_STATUS_IMGO_OVERR_ST				((unsigned int)1<<17)
+#define ISP_IRQ_CAMSV2_STATUS_rsv_18					((unsigned int)1<<18)
+#define ISP_IRQ_CAMSV2_STATUS_IMGO_DROP_ST				((unsigned int)1<<19)
+
+/*******************************************************************************
+*
+********************************************************************************/
+
+//defined if want to support multiple dequne and enque or camera 3.0
+/**
+    support multiple deque and enque if defined.
+    note: still en/de que 1 buffer each time only
+    e.g:
+        deque();
+        deque();
+        enque();
+        enque();
+*/
+#define _rtbc_buf_que_2_0_
+
+
+typedef enum
+{
+    ISP_IRQ_CLEAR_NONE,
+    ISP_IRQ_CLEAR_WAIT,
+    ISP_IRQ_CLEAR_STATUS,
+    ISP_IRQ_CLEAR_ALL
+}ISP_IRQ_CLEAR_ENUM;
+
+typedef enum
+{
+	ISP_IRQ_TYPE_INT_P1_ST,		//P1
+	ISP_IRQ_TYPE_INT_P1_ST2,	//P1_DMA
+	ISP_IRQ_TYPE_INT_P1_ST_D,	//P1_D
+	ISP_IRQ_TYPE_INT_P1_ST2_D,	//P1_DMA_D
+	ISP_IRQ_TYPE_INT_P2_ST,		//P2
+	ISP_IRQ_TYPE_INT_STATUSX,	//STATUSX, P1 AND P2
+	ISP_IRQ_TYPE_INT_STATUS2X,	//STATUS2X, P1_D
+	ISP_IRQ_TYPE_INT_STATUS3X,	//STATUS3X, ALL DMA
+	ISP_IRQ_TYPE_ISP_AMOUNT,
+	ISP_IRQ_TYPE_INT_SENINF1=ISP_IRQ_TYPE_ISP_AMOUNT,
+	ISP_IRQ_TYPE_INT_SENINF2,
+	ISP_IRQ_TYPE_INT_SENINF3,
+	ISP_IRQ_TYPE_INT_SENINF4,
+	ISP_IRQ_TYPE_SENINF_AMOUNT,
+	ISP_IRQ_TYPE_INT_CAMSV=ISP_IRQ_TYPE_SENINF_AMOUNT,
+	ISP_IRQ_TYPE_INT_CAMSV2,
+    ISP_IRQ_TYPE_AMOUNT
+}ISP_IRQ_TYPE_ENUM;
+
+
+typedef enum
+{
+    ISP_IRQ_USER_ISPDRV =   0,
+    ISP_IRQ_USER_MW     =   1,
+    ISP_IRQ_USER_3A     =   2,
+    ISP_IRQ_USER_HWSYNC =   3,
+    ISP_IRQ_USER_ACDK   =   4,
+    ISP_IRQ_USER_EIS    =   5,
+    ISP_IRQ_USER_VHDR   =   6,
+    ISP_IRQ_USER_MAX
+}ISP_IRQ_USER_ENUM;
+
+typedef struct
+{
+    ISP_IRQ_TYPE_ENUM   Type;
+    unsigned int        Status;
+    int                 UserKey;                     /* user key for doing interrupt operation */
+}ISP_IRQ_USER_STRUCT;
+
+typedef enum    //special user for specific operation
+{
+    ISP_IRQ_WAITIRQ_SPEUSER_NONE = 0,
+    ISP_IRQ_WAITIRQ_SPEUSER_EIS = 1,
+    ISP_IRQ_WAITIRQ_SPEUSER_NUM
+}ISP_IRQ_WAITIRQ_SPEUSER_ENUM;
+
+typedef struct
+{
+    unsigned int    tLastSig_sec;                       /* time stamp of the latest occuring signal*/
+    unsigned int    tLastSig_usec;                  /* time stamp of the latest occuring signal*/
+    unsigned int    tMark2WaitSig_sec;            /* time period from marking a signal to user try to wait and get the signal*/
+    unsigned int    tMark2WaitSig_usec;            /* time period from marking a signal to user try to wait and get the signal*/
+    unsigned int    tLastSig2GetSig_sec;         /* time period from latest occuring signal to user try to wait and get the signal*/
+    unsigned int    tLastSig2GetSig_usec;         /* time period from latest occuring signal to user try to wait and get the signal*/
+    int             passedbySigcnt;          /* the count for the signal passed by  */
+}ISP_IRQ_TIME_STRUCT;
+
+typedef struct
+{
+    unsigned int       tLastSOF2P1done_sec;                       /* time stamp of the last closest occuring sof signal for pass1 done*/
+    unsigned int       tLastSOF2P1done_usec;                  /* time stamp of the last closest occuring sof signal for pass1 done*/
+}ISP_EIS_META_STRUCT;
+
+
+typedef struct
+{
+    ISP_IRQ_CLEAR_ENUM  Clear;		//v1 & v3
+    ISP_IRQ_TYPE_ENUM   Type;           //v1 only
+    unsigned int        Status;                 //v1 only
+    int                 UserNumber;             //v1 only
+    unsigned int        Timeout;             //v1 & v3
+    char*			    UserName;       //no use
+    unsigned int        irq_TStamp;         //v1 & v3
+    unsigned int        bDumpReg;         //v1 & v3
+    ISP_IRQ_USER_STRUCT  UserInfo;  //v3 only
+    ISP_IRQ_TIME_STRUCT  TimeInfo;  //v3 only
+    ISP_EIS_META_STRUCT EisMeta;    //v1&v3
+    ISP_IRQ_WAITIRQ_SPEUSER_ENUM SpecUser;
+}ISP_WAIT_IRQ_STRUCT;
+
+typedef struct
+{
+    int  userKey;
+    char* userName;
+}ISP_REGISTER_USERKEY_STRUCT;
+
+typedef struct
+{
+    ISP_IRQ_TYPE_ENUM   Type;
+    ISP_IRQ_USER_ENUM   UserNumber;
+    unsigned int       Status;
+}ISP_READ_IRQ_STRUCT;
+
+typedef struct
+{
+    ISP_IRQ_TYPE_ENUM   Type;
+    ISP_IRQ_USER_ENUM   UserNumber;
+    unsigned int       Status;
+}ISP_CLEAR_IRQ_STRUCT;
+
+typedef enum
+{
+    ISP_HOLD_TIME_VD,
+    ISP_HOLD_TIME_EXPDONE
+}ISP_HOLD_TIME_ENUM;
+
+typedef struct
+{
+    unsigned int Addr;   // register's addr
+    unsigned int Val;    // register's value
+}ISP_REG_STRUCT;
+
+typedef struct
+{
+    //unsigned int Data;   // pointer to ISP_REG_STRUCT
+    ISP_REG_STRUCT* pData;   // pointer to ISP_REG_STRUCT
+    unsigned int Count;  // count
+}ISP_REG_IO_STRUCT;
+
+typedef void (*pIspCallback)(void);
+
+typedef enum
+{
+    //Work queue. It is interruptible, so there can be "Sleep" in work queue function.
+    ISP_CALLBACK_WORKQUEUE_VD,
+    ISP_CALLBACK_WORKQUEUE_EXPDONE,
+    //Tasklet. It is uninterrupted, so there can NOT be "Sleep" in tasklet function.
+    ISP_CALLBACK_TASKLET_VD,
+    ISP_CALLBACK_TASKLET_EXPDONE,
+    ISP_CALLBACK_AMOUNT
+}ISP_CALLBACK_ENUM;
+
+typedef struct
+{
+    ISP_CALLBACK_ENUM   Type;
+    pIspCallback        Func;
+}ISP_CALLBACK_STRUCT;
+
+//
+// length of the two memory areas
+#define P1_DEQUE_CNT    1
+#define RT_BUF_TBL_NPAGES 16
+#define ISP_RT_BUF_SIZE 16
+#define ISP_RT_CQ0C_BUF_SIZE (ISP_RT_BUF_SIZE)//(ISP_RT_BUF_SIZE>>1)
+//pass1 setting sync index
+#define ISP_REG_P1_CFG_IDX 0x4090
+//
+typedef enum
+{
+    _cam_tg_  = 0,
+    _cam_tg2_ ,     // 1
+    _camsv_tg_,     // 2
+    _camsv2_tg_,    // 3
+    _cam_tg_max_
+}_isp_tg_enum_;
+
+//
+typedef enum
+{
+    _imgi_  = 0,
+    _vipi_ ,    // 1
+    _vip2i_,    // 2
+    _vip3i_,    // 3
+    _imgo_,     // 4
+    _ufdi_,     // 5
+    _lcei_,     // 6
+    _ufeo_,     // 7
+    _rrzo_,     // 8
+    _imgo_d_,   // 9
+    _rrzo_d_,   // 10
+    _img2o_,    // 11
+    _img3o_,    // 12
+    _img3bo_,   // 13
+    _img3co_,   // 14
+    _camsv_imgo_,  // 15
+    _camsv2_imgo_,// 16
+    _mfbo_,     // 17
+    _feo_,      //18
+    _wrot_,    // 19
+    _wdma_,     // 20
+    _jpeg_,     // 21
+    _venc_stream_,     // 21
+    _rt_dma_max_
+}_isp_dma_enum_;
+//
+typedef struct {
+    unsigned int   w;       //tg size
+    unsigned int   h;
+    unsigned int   xsize;   //dmao xsize
+    unsigned int   stride;
+    unsigned int   fmt;
+    unsigned int   pxl_id;
+    unsigned int   wbn;
+    unsigned int   ob;
+    unsigned int   lsc;
+    unsigned int   rpg;
+    unsigned int   m_num_0;
+    unsigned int   frm_cnt;
+    unsigned int   bus_size;
+}ISP_RT_IMAGE_INFO_STRUCT;
+
+typedef struct {
+    unsigned int   srcX;    //crop window start point
+    unsigned int   srcY;
+    unsigned int   srcW;    //crop window size
+    unsigned int   srcH;
+    unsigned int   dstW;    //rrz out size
+    unsigned int   dstH;
+}ISP_RT_RRZ_INFO_STRUCT;
+
+typedef struct{
+    unsigned int x; //in pix
+    unsigned int y; //in pix
+    unsigned int w; //in byte
+    unsigned int h; //in byte
+}ISP_RT_DMAO_CROPPING_STRUCT;
+
+typedef struct {
+    unsigned int   memID;
+    unsigned int   size;
+    long long      base_vAddr;
+    unsigned int   base_pAddr;
+    unsigned int   timeStampS;
+    unsigned int   timeStampUs;
+    unsigned int   bFilled;
+    unsigned int   bProcessRaw;
+    ISP_RT_IMAGE_INFO_STRUCT image;
+    ISP_RT_RRZ_INFO_STRUCT rrzInfo;
+    ISP_RT_DMAO_CROPPING_STRUCT dmaoCrop;   //imgo
+    unsigned int          bDequeued;
+    signed int         bufIdx;//used for replace buffer
+}ISP_RT_BUF_INFO_STRUCT;
+//
+typedef struct  {
+    unsigned int           count;
+    unsigned int           sof_cnt;         //cnt for current sof
+    unsigned int           img_cnt;         //cnt for mapping to which sof
+    //rome support only deque 1 image at a time
+    //ISP_RT_BUF_INFO_STRUCT  data[ISP_RT_BUF_SIZE];
+    ISP_RT_BUF_INFO_STRUCT  data[P1_DEQUE_CNT];
+}ISP_DEQUE_BUF_INFO_STRUCT;
+//
+typedef struct  {
+    unsigned int           start;          //current DMA accessing buffer
+    unsigned int           total_count;    //total buffer number.Include Filled and empty
+    unsigned int           empty_count;    //total empty buffer number include current DMA accessing buffer
+    unsigned int           pre_empty_count;//previous total empty buffer number include current DMA accessing buffer
+    unsigned int           active;
+    unsigned int           read_idx;
+    unsigned int           img_cnt;         //cnt for mapping to which sof
+    ISP_RT_BUF_INFO_STRUCT  data[ISP_RT_BUF_SIZE];
+}ISP_RT_RING_BUF_INFO_STRUCT;
+//
+typedef enum
+{
+    ISP_RT_BUF_CTRL_ENQUE,      // 0
+#ifdef _rtbc_buf_que_2_0_
+    ISP_RT_BUF_CTRL_ENQUE_IMD,  // for directly enque
+#else
+    ISP_RT_BUF_CTRL_ENQUE_IMD = ISP_RT_BUF_CTRL_ENQUE,
+#endif
+    ISP_RT_BUF_CTRL_EXCHANGE_ENQUE, // 1
+    ISP_RT_BUF_CTRL_DEQUE,          // 2
+    ISP_RT_BUF_CTRL_IS_RDY,         // 3
+#ifdef _rtbc_buf_que_2_0_
+    ISP_RT_BUF_CTRL_DMA_EN,           // 4
+#endif
+    ISP_RT_BUF_CTRL_GET_SIZE,       // 5
+    ISP_RT_BUF_CTRL_CLEAR,          // 6
+    ISP_RT_BUF_CTRL_CUR_STATUS,     //7
+    ISP_RT_BUF_CTRL_MAX
+}ISP_RT_BUF_CTRL_ENUM;
+//
+typedef enum
+{
+    ISP_RTBC_STATE_INIT, // 0
+    ISP_RTBC_STATE_SOF,
+    ISP_RTBC_STATE_DONE,
+    ISP_RTBC_STATE_MAX
+}ISP_RTBC_STATE_ENUM;
+//
+typedef enum
+{
+    ISP_RTBC_BUF_EMPTY, // 0
+    ISP_RTBC_BUF_FILLED,// 1
+    ISP_RTBC_BUF_LOCKED,// 2
+}ISP_RTBC_BUF_STATE_ENUM;
+//
+typedef enum
+{
+    ISP_RROCESSED_RAW,// 0
+    ISP_PURE_RAW, // 1
+}ISP_RAW_TYPE_ENUM;
+//
+typedef struct  {
+    ISP_RTBC_STATE_ENUM state;
+    unsigned long dropCnt;
+    ISP_RT_RING_BUF_INFO_STRUCT  ring_buf[_rt_dma_max_];
+}ISP_RT_BUF_STRUCT;
+//
+typedef struct  {
+    ISP_RT_BUF_CTRL_ENUM    ctrl;
+    _isp_dma_enum_          buf_id;
+    //unsigned int            data_ptr;
+    //unsigned int            ex_data_ptr; //exchanged buffer
+    ISP_RT_BUF_INFO_STRUCT*  data_ptr;
+    ISP_RT_BUF_INFO_STRUCT*  ex_data_ptr; //exchanged buffer
+    unsigned char* pExtend;
+}ISP_BUFFER_CTRL_STRUCT;
+//
+//reference count
+#define _use_kernel_ref_cnt_
+//
+typedef enum
+{
+    ISP_REF_CNT_GET,    // 0
+    ISP_REF_CNT_INC,    // 1
+    ISP_REF_CNT_DEC,    // 2
+    ISP_REF_CNT_DEC_AND_RESET_P1_P2_IF_LAST_ONE,    // 3
+    ISP_REF_CNT_DEC_AND_RESET_P1_IF_LAST_ONE,    // 4
+    ISP_REF_CNT_DEC_AND_RESET_P2_IF_LAST_ONE,    // 5
+    ISP_REF_CNT_MAX
+}ISP_REF_CNT_CTRL_ENUM;
+//
+typedef enum
+{
+    ISP_REF_CNT_ID_IMEM,    // 0
+    ISP_REF_CNT_ID_ISP_FUNC,// 1
+    ISP_REF_CNT_ID_GLOBAL_PIPE, // 2
+    ISP_REF_CNT_ID_P1_PIPE,     // 3
+    ISP_REF_CNT_ID_P2_PIPE,     // 4
+    ISP_REF_CNT_ID_MAX,
+}ISP_REF_CNT_ID_ENUM;
+//
+typedef struct  {
+    ISP_REF_CNT_CTRL_ENUM   ctrl;
+    ISP_REF_CNT_ID_ENUM     id;
+    signed int*         data_ptr;
+}ISP_REF_CNT_CTRL_STRUCT;
+
+//struct for enqueue/dequeue control in ihalpipe wrapper
+typedef enum
+{
+    ISP_ED_BUFQUE_CTRL_ENQUE_FRAME=0,          // 0,signal that a specific buffer is enqueued
+    ISP_ED_BUFQUE_CTRL_WAIT_DEQUE,             // 1,a dequeue thread is waiting to do dequeue
+    ISP_ED_BUFQUE_CTRL_DEQUE_SUCCESS,          // 2,signal that a buffer is dequeued (success)
+    ISP_ED_BUFQUE_CTRL_DEQUE_FAIL,             // 3,signal that a buffer is dequeued (fail)
+    ISP_ED_BUFQUE_CTRL_WAIT_FRAME,             // 4,wait for a specific buffer
+    ISP_ED_BUFQUE_CTRL_WAKE_WAITFRAME,         // 5,wake all sleeped users to check buffer is dequeued or not
+    ISP_ED_BUFQUE_CTRL_CLAER_ALL,              // 6,free all recored dequeued buffer
+    ISP_ED_BUFQUE_CTRL_MAX
+}ISP_ED_BUFQUE_CTRL_ENUM;
+
+typedef struct
+{
+    ISP_ED_BUFQUE_CTRL_ENUM ctrl;
+    unsigned int            processID;
+    unsigned int            callerID;
+    int                     p2burstQIdx;
+    int                     p2dupCQIdx;
+    unsigned int            timeoutUs;
+}ISP_ED_BUFQUE_STRUCT;
+
+typedef enum
+{
+    ISP_ED_BUF_STATE_NONE  =-1,
+    ISP_ED_BUF_STATE_ENQUE=0,
+    ISP_ED_BUF_STATE_RUNNING,
+    ISP_ED_BUF_STATE_WAIT_DEQUE_FAIL,
+    ISP_ED_BUF_STATE_DEQUE_SUCCESS,
+    ISP_ED_BUF_STATE_DEQUE_FAIL
+}ISP_ED_BUF_STATE_ENUM;
+/********************************************************************************************
+ pass1 real time buffer control use cq0c
+********************************************************************************************/
+//
+#define _rtbc_use_cq0c_
+
+#define _MAGIC_NUM_ERR_HANDLING_
+
+
+#if defined(_rtbc_use_cq0c_)
+//
+typedef struct _cq_cmd_st_
+{
+    unsigned int inst;
+    unsigned int data_ptr_pa;
+}CQ_CMD_ST;
+/*
+typedef struct _cq_cmd_rtbc_st_
+{
+    CQ_CMD_ST imgo;
+    CQ_CMD_ST img2o;
+    CQ_CMD_ST cq0ci;
+    CQ_CMD_ST end;
+}CQ_CMD_RTBC_ST;
+*/
+typedef struct _cq_info_rtbc_st_
+{
+    CQ_CMD_ST imgo;
+    CQ_CMD_ST rrzo;
+    CQ_CMD_ST next_cq0ci;
+    CQ_CMD_ST end;
+    unsigned int imgo_base_pAddr;
+    unsigned int rrzo_base_pAddr;
+    signed int imgo_buf_idx; //used for replace buffer
+    signed int rrzo_buf_idx; //used for replace buffer
+}CQ_INFO_RTBC_ST;
+typedef struct _cq_ring_cmd_st_
+{
+    CQ_INFO_RTBC_ST cq_rtbc;
+    unsigned long next_pa;
+    struct _cq_ring_cmd_st_ *pNext;
+}CQ_RING_CMD_ST;
+typedef struct _cq_rtbc_ring_st_
+{
+    CQ_RING_CMD_ST rtbc_ring[ISP_RT_CQ0C_BUF_SIZE];
+    unsigned int   imgo_ring_size;
+    unsigned int   rrzo_ring_size;
+}CQ_RTBC_RING_ST;
+#endif
+
+//CQ0B for AE smoothing, set obc_gain0~3
+typedef struct _cq0b_info_rtbc_st_
+{
+    CQ_CMD_ST ob;
+    CQ_CMD_ST end;
+}CQ0B_INFO_RTBC_ST;
+
+typedef struct _cq0b_ring_cmd_st_
+{
+    CQ0B_INFO_RTBC_ST cq0b_rtbc;
+    unsigned long next_pa;
+    struct _cq0b_ring_cmd_st_ *pNext;
+}CQ0B_RING_CMD_ST;
+
+typedef struct _cq0b_rtbc_ring_st_
+{
+    CQ0B_RING_CMD_ST rtbc_ring;
+}CQ0B_RTBC_RING_ST;
+//
+typedef volatile union _CQ_RTBC_FBC_
+{
+    volatile struct
+    {
+        unsigned int FBC_CNT                   : 4;
+        unsigned int rsv_4                     : 7;
+        unsigned int RCNT_INC                  : 1;
+        unsigned int rsv_12                    : 2;
+        unsigned int FBC_EN                    : 1;
+        unsigned int LOCK_EN                   : 1;
+        unsigned int FB_NUM                    : 4;
+        unsigned int RCNT                      : 4;
+        unsigned int WCNT                      : 4;
+        unsigned int DROP_CNT                  : 4;
+    } Bits;
+    unsigned int Reg_val;
+}CQ_RTBC_FBC;
+
+//
+/********************************************************************************************
+
+********************************************************************************************/
+
+
+/*******************************************************************************
+*
+********************************************************************************/
+typedef enum
+{
+    ISP_CMD_RESET_CAM_P1,          //Reset
+    ISP_CMD_RESET_CAM_P2,
+    ISP_CMD_RESET_CAMSV,
+    ISP_CMD_RESET_CAMSV2,
+    ISP_CMD_RESET_BUF,
+    ISP_CMD_READ_REG,       //Read register from driver
+    ISP_CMD_WRITE_REG,      //Write register to driver
+    ISP_CMD_HOLD_TIME,
+    ISP_CMD_HOLD_REG,       //Hold reg write to hw, on/off
+    ISP_CMD_WAIT_IRQ,       //Wait IRQ
+    ISP_CMD_READ_IRQ,       //Read IRQ
+    ISP_CMD_CLEAR_IRQ,      //Clear IRQ
+    ISP_CMD_DUMP_REG,       //Dump ISP registers , for debug usage
+    ISP_CMD_SET_USER_PID,   //for signal
+    ISP_CMD_RT_BUF_CTRL,   //for pass buffer control
+    ISP_CMD_REF_CNT,        //get imem reference count
+    ISP_CMD_DEBUG_FLAG,      //Dump message level
+    ISP_CMD_REGISTER_IRQ,    //register for a specific irq
+    ISP_CMD_UNREGISTER_IRQ,  //unregister for a specific irq
+    ISP_CMD_ED_QUEBUF_CTRL,
+    ISP_CMD_UPDATE_REGSCEN,
+    ISP_CMD_QUERY_REGSCEN,
+    ISP_CMD_UPDATE_BURSTQNUM,
+    ISP_CMD_QUERY_BURSTQNUM,
+    ISP_CMD_DUMP_ISR_LOG,   //dump isr log
+    ISP_CMD_GET_CUR_SOF,
+    ISP_CMD_GET_DMA_ERR,
+    ISP_CMD_GET_INT_ERR,
+    ISP_CMD_GET_DROP_FRAME,         //dump current frame informaiton, 1 for drop frmae, 2 for last working frame
+#ifdef T_STAMP_2_0
+    ISP_CMD_SET_FPS,
+#endif
+    ISP_CMD_WAKELOCK_CTRL,
+    ISP_CMD_REGISTER_IRQ_USER_KEY,              /* register for a user key to do irq operation */
+    ISP_CMD_MARK_IRQ_REQUEST,                    /* mark for a specific register befor wait for the interrupt if needed */
+    ISP_CMD_GET_MARK2QUERY_TIME,             /* query time information between read and mark */
+    ISP_CMD_FLUSH_IRQ_REQUEST,                    /* flush signal */
+}ISP_CMD_ENUM;
+//
+#define ISP_RESET_CAM_P1    _IO  (ISP_MAGIC, ISP_CMD_RESET_CAM_P1)
+#define ISP_RESET_CAM_P2    _IO  (ISP_MAGIC, ISP_CMD_RESET_CAM_P2)
+#define ISP_RESET_CAMSV     _IO  (ISP_MAGIC, ISP_CMD_RESET_CAMSV)
+#define ISP_RESET_CAMSV2    _IO  (ISP_MAGIC, ISP_CMD_RESET_CAMSV2)
+#define ISP_RESET_BUF       _IO  (ISP_MAGIC, ISP_CMD_RESET_BUF)
+#define ISP_READ_REGISTER   _IOWR(ISP_MAGIC, ISP_CMD_READ_REG,      ISP_REG_IO_STRUCT)
+#define ISP_WRITE_REGISTER  _IOWR(ISP_MAGIC, ISP_CMD_WRITE_REG,     ISP_REG_IO_STRUCT)
+#define ISP_HOLD_REG_TIME   _IOW (ISP_MAGIC, ISP_CMD_HOLD_TIME,     ISP_HOLD_TIME_ENUM)
+#define ISP_HOLD_REG        _IOW (ISP_MAGIC, ISP_CMD_HOLD_REG,      bool)
+#define ISP_WAIT_IRQ        _IOW (ISP_MAGIC, ISP_CMD_WAIT_IRQ,      ISP_WAIT_IRQ_STRUCT)
+#define ISP_READ_IRQ        _IOR (ISP_MAGIC, ISP_CMD_READ_IRQ,      ISP_READ_IRQ_STRUCT)
+#define ISP_CLEAR_IRQ       _IOW (ISP_MAGIC, ISP_CMD_CLEAR_IRQ,     ISP_CLEAR_IRQ_STRUCT)
+#define ISP_DUMP_REG        _IO  (ISP_MAGIC, ISP_CMD_DUMP_REG)
+#define ISP_SET_USER_PID    _IOW (ISP_MAGIC, ISP_CMD_SET_USER_PID,    unsigned int)
+#define ISP_BUFFER_CTRL     _IOWR(ISP_MAGIC, ISP_CMD_RT_BUF_CTRL,    ISP_BUFFER_CTRL_STRUCT)
+#define ISP_REF_CNT_CTRL    _IOWR(ISP_MAGIC, ISP_CMD_REF_CNT,       ISP_REF_CNT_CTRL_STRUCT)
+#define ISP_DEBUG_FLAG      _IOW (ISP_MAGIC, ISP_CMD_DEBUG_FLAG,    unsigned char*)
+#define ISP_REGISTER_IRQ    _IOW (ISP_MAGIC, ISP_CMD_REGISTER_IRQ,  ISP_WAIT_IRQ_STRUCT)
+#define ISP_UNREGISTER_IRQ    _IOW (ISP_MAGIC, ISP_CMD_UNREGISTER_IRQ,  ISP_WAIT_IRQ_STRUCT)
+#define ISP_ED_QUEBUF_CTRL     _IOWR (ISP_MAGIC, ISP_CMD_ED_QUEBUF_CTRL, ISP_ED_BUFQUE_STRUCT)
+#define ISP_UPDATE_REGSCEN     _IOWR (ISP_MAGIC, ISP_CMD_UPDATE_REGSCEN, unsigned int)
+#define ISP_QUERY_REGSCEN     _IOR (ISP_MAGIC, ISP_CMD_QUERY_REGSCEN, unsigned int)
+#define ISP_UPDATE_BURSTQNUM _IOW(ISP_MAGIC,ISP_CMD_UPDATE_BURSTQNUM, int)
+#define ISP_QUERY_BURSTQNUM _IOR (ISP_MAGIC,ISP_CMD_QUERY_BURSTQNUM, int)
+#define ISP_DUMP_ISR_LOG    _IO  (ISP_MAGIC, ISP_CMD_DUMP_ISR_LOG)
+#define ISP_GET_CUR_SOF     _IOR (ISP_MAGIC, ISP_CMD_GET_CUR_SOF,      unsigned int)
+#define ISP_GET_DMA_ERR     _IOWR (ISP_MAGIC, ISP_CMD_GET_DMA_ERR,      unsigned char*)
+#define ISP_GET_INT_ERR     _IOR    (ISP_MAGIC, ISP_CMD_GET_INT_ERR,      unsigned char*)
+#define ISP_GET_DROP_FRAME  _IOWR    (ISP_MAGIC, ISP_CMD_GET_DROP_FRAME,      unsigned int)
+#ifdef T_STAMP_2_0
+    #define ISP_SET_FPS     _IOW (ISP_MAGIC, ISP_CMD_SET_FPS,    unsigned int)
+#endif
+#define ISP_REGISTER_IRQ_USER_KEY   _IOR(ISP_MAGIC,ISP_CMD_REGISTER_IRQ_USER_KEY,ISP_REGISTER_USERKEY_STRUCT)
+#define ISP_MARK_IRQ_REQUEST        _IOWR(ISP_MAGIC,ISP_CMD_MARK_IRQ_REQUEST,ISP_WAIT_IRQ_STRUCT)
+#define ISP_GET_MARK2QUERY_TIME     _IOWR(ISP_MAGIC,ISP_CMD_GET_MARK2QUERY_TIME,ISP_WAIT_IRQ_STRUCT)
+#define ISP_FLUSH_IRQ_REQUEST       _IOW(ISP_MAGIC,ISP_CMD_FLUSH_IRQ_REQUEST,ISP_WAIT_IRQ_STRUCT)
+
+#define ISP_WAKELOCK_CTRL     _IOWR (ISP_MAGIC, ISP_CMD_WAKELOCK_CTRL,      unsigned int)
+
+//
+bool ISP_RegCallback(ISP_CALLBACK_STRUCT* pCallback);
+bool ISP_UnregCallback(ISP_CALLBACK_ENUM   Type);
+int32_t ISP_MDPClockOnCallback(uint64_t engineFlag);
+int32_t ISP_MDPDumpCallback(uint64_t engineFlag,
+                            int level);
+int32_t ISP_MDPResetCallback(uint64_t engineFlag);
+
+int32_t ISP_MDPClockOffCallback(uint64_t engineFlag);
+
+int32_t ISP_BeginGCECallback(uint32_t taskID, uint32_t *regCount, uint32_t **regAddress);
+int32_t ISP_EndGCECallback(uint32_t taskID, uint32_t regCount, uint32_t *regValues);
+
+//
+#endif
+
diff --git a/kernel-headers/camera_isp_D2.h b/kernel-headers/camera_isp_D2.h
new file mode 100755
index 0000000..c2d3cc7
--- /dev/null
+++ b/kernel-headers/camera_isp_D2.h
@@ -0,0 +1,537 @@
+/*
+* Copyright (C) 2011-2014 MediaTek Inc.
+*
+* This program is free software: you can redistribute it and/or modify it under the terms of the
+* GNU General Public License version 2 as published by the Free Software Foundation.
+*
+* This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
+* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+* See the GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License along with this program.
+* If not, see <http://www.gnu.org/licenses/>.
+*/
+
+#ifndef _MT_ISP_H
+#define _MT_ISP_H
+
+#include <linux/ioctl.h>
+
+#ifdef CONFIG_COMPAT
+//64 bit
+#include <linux/fs.h>
+#include <linux/compat.h>
+#endif
+
+//89serial IC , for HW FBC
+#define _89SERIAL_
+
+/*******************************************************************************
+*
+********************************************************************************/
+#define ISP_DEV_MAJOR_NUMBER    251
+#define ISP_MAGIC               'k'
+/*******************************************************************************
+*
+********************************************************************************/
+//CAM_CTL_INT_STATUS
+#define ISP_IRQ_INT_STATUS_VS1_ST               ((unsigned int)1 << 0)
+#define ISP_IRQ_INT_STATUS_TG1_ST1              ((unsigned int)1 << 1)
+#define ISP_IRQ_INT_STATUS_TG1_ST2              ((unsigned int)1 << 2)
+#define ISP_IRQ_INT_STATUS_EXPDON1_ST           ((unsigned int)1 << 3)
+#define ISP_IRQ_INT_STATUS_TG1_ERR_ST           ((unsigned int)1 << 4)
+#define ISP_IRQ_INT_STATUS_PASS1_TG1_DON_ST     ((unsigned int)1 << 10)
+#define ISP_IRQ_INT_STATUS_SOF1_INT_ST          ((unsigned int)1 << 12)
+#define ISP_IRQ_INT_STATUS_CQ_ERR_ST            ((unsigned int)1 << 13)
+#define ISP_IRQ_INT_STATUS_PASS2_DON_ST         ((unsigned int)1 << 14)
+#define ISP_IRQ_INT_STATUS_TPIPE_DON_ST         ((unsigned int)1 << 15)
+#define ISP_IRQ_INT_STATUS_AF_DON_ST            ((unsigned int)1 << 16)
+#define ISP_IRQ_INT_STATUS_FLK_DON_ST           ((unsigned int)1 << 17)
+#define ISP_IRQ_INT_STATUS_CQ_DON_ST            ((unsigned int)1 << 19)
+#define ISP_IRQ_INT_STATUS_IMGO_ERR_ST          ((unsigned int)1 << 20)
+#define ISP_IRQ_INT_STATUS_AAO_ERR_ST           ((unsigned int)1 << 21)
+#define ISP_IRQ_INT_STATUS_IMG2O_ERR_ST         ((unsigned int)1 << 23)
+#define ISP_IRQ_INT_STATUS_ESFKO_ERR_ST         ((unsigned int)1 << 24)
+#define ISP_IRQ_INT_STATUS_FLK_ERR_ST           ((unsigned int)1 << 25)
+#define ISP_IRQ_INT_STATUS_LSC_ERR_ST           ((unsigned int)1 << 26)
+#define ISP_IRQ_INT_STATUS_FBC_IMGO_DONE_ST     ((unsigned int)1 << 28)
+#define ISP_IRQ_INT_STATUS_DMA_ERR_ST           ((unsigned int)1 << 30)
+//CAM_CTL_DMA_INT
+#define ISP_IRQ_DMA_INT_IMGO_DONE_ST            ((unsigned int)1 << 0)
+#define ISP_IRQ_DMA_INT_IMG2O_DONE_ST           ((unsigned int)1 << 1)
+#define ISP_IRQ_DMA_INT_AAO_DONE_ST             ((unsigned int)1 << 2)
+//#define ISP_IRQ_DMA_INT_LCSO_DONE_ST            ((unsigned int)1 << 3)
+#define ISP_IRQ_DMA_INT_ESFKO_DONE_ST           ((unsigned int)1 << 4)
+//#define ISP_IRQ_DMA_INT_DISPO_DONE_ST           ((unsigned int)1 << 5)
+//#define ISP_IRQ_DMA_INT_VIDO_DONE_ST            ((unsigned int)1 << 6)
+//#define ISP_IRQ_DMA_INT_VRZO_DONE_ST            ((unsigned int)1 << 7)
+#define ISP_IRQ_DMA_INT_CQ0_ERR_ST              ((unsigned int)1 << 8)
+#define ISP_IRQ_DMA_INT_CQ0_DONE_ST             ((unsigned int)1 << 9)
+//#define ISP_IRQ_DMA_INT_SOF2_INT_ST             ((unsigned int)1 << 10)
+//#define ISP_IRQ_DMA_INT_BUF_OVL_ST              ((unsigned int)1 << 11)
+#define ISP_IRQ_DMA_INT_TG1_GBERR_ST            ((unsigned int)1 << 12)
+//#define ISP_IRQ_DMA_INT_TG2_GBERR_ST            ((unsigned int)1 << 13)
+#define ISP_IRQ_DMA_INT_CQ0C_DONE_ST            ((unsigned int)1 << 14)
+#define ISP_IRQ_DMA_INT_CQ0B_DONE_ST            ((unsigned int)1 << 15)
+//CAM_CTL_INTB_STATUS
+#define ISP_IRQ_INTB_STATUS_CQ_ERR_ST           ((unsigned int)1 << 13)
+#define ISP_IRQ_INTB_STATUS_PASS2_DON_ST        ((unsigned int)1 << 14)
+#define ISP_IRQ_INTB_STATUS_TPIPE_DON_ST        ((unsigned int)1 << 15)
+#define ISP_IRQ_INTB_STATUS_CQ_DON_ST           ((unsigned int)1 << 19)
+#define ISP_IRQ_INTB_STATUS_IMGO_ERR_ST         ((unsigned int)1 << 20)
+#define ISP_IRQ_INTB_STATUS_LCSO_ERR_ST         ((unsigned int)1 << 22)
+#define ISP_IRQ_INTB_STATUS_IMG2O_ERR_ST        ((unsigned int)1 << 23)
+#define ISP_IRQ_INTB_STATUS_LSC_ERR_ST          ((unsigned int)1 << 26)
+#define ISP_IRQ_INTB_STATUS_BPC_ERR_ST          ((unsigned int)1 << 28)
+#define ISP_IRQ_INTB_STATUS_LCE_ERR_ST          ((unsigned int)1 << 29)
+#define ISP_IRQ_INTB_STATUS_DMA_ERR_ST          ((unsigned int)1 << 30)
+#define ISP_IRQ_INTB_STATUS_INT_WCLR_ST         ((unsigned int)1 << 31)
+
+//CAM_CTL_DMAB_INT
+#define ISP_IRQ_DMAB_INT_IMGO_DONE_ST           ((unsigned int)1 << 0)
+#define ISP_IRQ_DMAB_INT_IMG2O_DONE_ST          ((unsigned int)1 << 1)
+#define ISP_IRQ_DMAB_INT_AAO_DONE_ST            ((unsigned int)1 << 2)
+#define ISP_IRQ_DMAB_INT_LCSO_DONE_ST           ((unsigned int)1 << 3)
+#define ISP_IRQ_DMAB_INT_ESFKO_DONE_ST          ((unsigned int)1 << 4)
+#define ISP_IRQ_DMAB_INT_DISPO_DONE_ST          ((unsigned int)1 << 5)
+#define ISP_IRQ_DMAB_INT_VIDO_DONE_ST           ((unsigned int)1 << 6)
+//#define ISP_IRQ_DMAB_INT_VRZO_DONE_ST           ((unsigned int)1 << 7)
+//#define ISP_IRQ_DMAB_INT_NR3O_DONE_ST           ((unsigned int)1 << 8)
+//#define ISP_IRQ_DMAB_INT_NR3O_ERR_ST            ((unsigned int)1 << 9)
+//CAM_CTL_INTC_STATUS
+#define ISP_IRQ_INTC_STATUS_CQ_ERR_ST           ((unsigned int)1 << 13)
+#define ISP_IRQ_INTC_STATUS_PASS2_DON_ST        ((unsigned int)1 << 14)
+#define ISP_IRQ_INTC_STATUS_TPIPE_DON_ST        ((unsigned int)1 << 15)
+#define ISP_IRQ_INTC_STATUS_CQ_DON_ST           ((unsigned int)1 << 19)
+#define ISP_IRQ_INTC_STATUS_IMGO_ERR_ST         ((unsigned int)1 << 20)
+#define ISP_IRQ_INTC_STATUS_LCSO_ERR_ST         ((unsigned int)1 << 22)
+#define ISP_IRQ_INTC_STATUS_IMG2O_ERR_ST        ((unsigned int)1 << 23)
+#define ISP_IRQ_INTC_STATUS_LSC_ERR_ST          ((unsigned int)1 << 26)
+#define ISP_IRQ_INTC_STATUS_BPC_ERR_ST          ((unsigned int)1 << 28)
+#define ISP_IRQ_INTC_STATUS_LCE_ERR_ST          ((unsigned int)1 << 29)
+#define ISP_IRQ_INTC_STATUS_DMA_ERR_ST          ((unsigned int)1 << 30)
+//CAM_CTL_DMAC_INT
+#define ISP_IRQ_DMAC_INT_IMGO_DONE_ST           ((unsigned int)1 << 0)
+#define ISP_IRQ_DMAC_INT_IMG2O_DONE_ST          ((unsigned int)1 << 1)
+#define ISP_IRQ_DMAC_INT_AAO_DONE_ST            ((unsigned int)1 << 2)
+#define ISP_IRQ_DMAC_INT_LCSO_DONE_ST           ((unsigned int)1 << 3)
+#define ISP_IRQ_DMAC_INT_ESFKO_DONE_ST          ((unsigned int)1 << 4)
+#define ISP_IRQ_DMAC_INT_DISPO_DONE_ST          ((unsigned int)1 << 5)
+#define ISP_IRQ_DMAC_INT_VIDO_DONE_ST           ((unsigned int)1 << 6)
+//#define ISP_IRQ_DMAC_INT_VRZO_DONE_ST           ((unsigned int)1 << 7)
+//#define ISP_IRQ_DMAC_INT_NR3O_DONE_ST           ((unsigned int)1 << 8)
+//#define ISP_IRQ_DMAC_INT_NR3O_ERR_ST            ((unsigned int)1 << 9)
+//CAM_CTL_INT_STATUSX
+#define ISP_IRQ_INTX_STATUS_VS1_ST              ((unsigned int)1 << 0)
+#define ISP_IRQ_INTX_STATUS_TG1_ST1             ((unsigned int)1 << 1)
+#define ISP_IRQ_INTX_STATUS_TG1_ST2             ((unsigned int)1 << 2)
+#define ISP_IRQ_INTX_STATUS_EXPDON1_ST          ((unsigned int)1 << 3)
+#define ISP_IRQ_INTX_STATUS_TG1_ERR_ST          ((unsigned int)1 << 4)
+#define ISP_IRQ_INTX_STATUS_VS2_ST              ((unsigned int)1 << 5)
+#define ISP_IRQ_INTX_STATUS_TG2_ST1             ((unsigned int)1 << 6)
+#define ISP_IRQ_INTX_STATUS_TG2_ST2             ((unsigned int)1 << 7)
+#define ISP_IRQ_INTX_STATUS_EXPDON2_ST          ((unsigned int)1 << 8)
+#define ISP_IRQ_INTX_STATUS_TG2_ERR_ST          ((unsigned int)1 << 9)
+#define ISP_IRQ_INTX_STATUS_PASS1_TG1_DON_ST    ((unsigned int)1 << 10)
+#define ISP_IRQ_INTX_STATUS_PASS1_TG2_DON_ST    ((unsigned int)1 << 11)
+//#define ISP_IRQ_INTX_STATUS_VEC_DON_ST          ((unsigned int)1 << 12)
+#define ISP_IRQ_INTX_STATUS_CQ_ERR_ST           ((unsigned int)1 << 13)
+#define ISP_IRQ_INTX_STATUS_PASS2_DON_ST        ((unsigned int)1 << 14)
+#define ISP_IRQ_INTX_STATUS_TPIPE_DON_ST        ((unsigned int)1 << 15)
+#define ISP_IRQ_INTX_STATUS_AF_DON_ST           ((unsigned int)1 << 16)
+#define ISP_IRQ_INTX_STATUS_FLK_DON_ST          ((unsigned int)1 << 17)
+#define ISP_IRQ_INTX_STATUS_FMT_DON_ST          ((unsigned int)1 << 18)
+#define ISP_IRQ_INTX_STATUS_CQ_DON_ST           ((unsigned int)1 << 19)
+#define ISP_IRQ_INTX_STATUS_IMGO_ERR_ST         ((unsigned int)1 << 20)
+#define ISP_IRQ_INTX_STATUS_AAO_ERR_ST          ((unsigned int)1 << 21)
+#define ISP_IRQ_INTX_STATUS_LCSO_ERR_ST         ((unsigned int)1 << 22)
+#define ISP_IRQ_INTX_STATUS_IMG2O_ERR_ST        ((unsigned int)1 << 23)
+#define ISP_IRQ_INTX_STATUS_ESFKO_ERR_ST        ((unsigned int)1 << 24)
+#define ISP_IRQ_INTX_STATUS_FLK_ERR_ST          ((unsigned int)1 << 25)
+#define ISP_IRQ_INTX_STATUS_LSC_ERR_ST          ((unsigned int)1 << 26)
+//#define ISP_IRQ_INTX_STATUS_LSC2_ERR_ST         ((unsigned int)1 << 27)
+#define ISP_IRQ_INTX_STATUS_BPC_ERR_ST          ((unsigned int)1 << 28)
+#define ISP_IRQ_INTX_STATUS_LCE_ERR_ST          ((unsigned int)1 << 29)
+#define ISP_IRQ_INTX_STATUS_DMA_ERR_ST          ((unsigned int)1 << 30)
+//CAM_CTL_DMA_INTX
+#define ISP_IRQ_DMAX_INT_IMGO_DONE_ST           ((unsigned int)1 << 0)
+#define ISP_IRQ_DMAX_INT_IMG2O_DONE_ST          ((unsigned int)1 << 1)
+#define ISP_IRQ_DMAX_INT_AAO_DONE_ST            ((unsigned int)1 << 2)
+#define ISP_IRQ_DMAX_INT_LCSO_DONE_ST           ((unsigned int)1 << 3)
+#define ISP_IRQ_DMAX_INT_ESFKO_DONE_ST          ((unsigned int)1 << 4)
+#define ISP_IRQ_DMAX_INT_DISPO_DONE_ST          ((unsigned int)1 << 5)
+#define ISP_IRQ_DMAX_INT_VIDO_DONE_ST           ((unsigned int)1 << 6)
+#define ISP_IRQ_DMAX_INT_VRZO_DONE_ST           ((unsigned int)1 << 7)
+#define ISP_IRQ_DMAX_INT_NR3O_DONE_ST           ((unsigned int)1 << 8)
+#define ISP_IRQ_DMAX_INT_NR3O_ERR_ST            ((unsigned int)1 << 9)
+#define ISP_IRQ_DMAX_INT_CQ_ERR_ST              ((unsigned int)1 << 10)
+#define ISP_IRQ_DMAX_INT_BUF_OVL_ST             ((unsigned int)1 << 11)
+#define ISP_IRQ_DMAX_INT_TG1_GBERR_ST           ((unsigned int)1 << 12)
+#define ISP_IRQ_DMAX_INT_TG2_GBERR_ST           ((unsigned int)1 << 13)
+
+/*******************************************************************************
+*
+********************************************************************************/
+typedef enum
+{
+    ISP_IRQ_CLEAR_NONE,
+    ISP_IRQ_CLEAR_WAIT,
+    ISP_IRQ_CLEAR_ALL
+}ISP_IRQ_CLEAR_ENUM;
+
+typedef enum
+{
+    ISP_IRQ_TYPE_INT,
+    ISP_IRQ_TYPE_DMA,
+    ISP_IRQ_TYPE_INTB,
+    ISP_IRQ_TYPE_DMAB,
+    ISP_IRQ_TYPE_INTC,
+    ISP_IRQ_TYPE_DMAC,
+    ISP_IRQ_TYPE_INTX,
+    ISP_IRQ_TYPE_DMAX,
+    ISP_IRQ_TYPE_AMOUNT
+}ISP_IRQ_TYPE_ENUM;
+
+typedef struct
+{
+    ISP_IRQ_CLEAR_ENUM  Clear;
+    ISP_IRQ_TYPE_ENUM   Type;
+    unsigned int       Status;
+    unsigned int       Timeout;
+}ISP_WAIT_IRQ_STRUCT;
+
+typedef struct
+{
+    ISP_IRQ_TYPE_ENUM   Type;
+    unsigned int       Status;
+}ISP_READ_IRQ_STRUCT;
+
+typedef struct
+{
+    ISP_IRQ_TYPE_ENUM   Type;
+    unsigned int       Status;
+}ISP_CLEAR_IRQ_STRUCT;
+
+typedef enum
+{
+    ISP_HOLD_TIME_VD,
+    ISP_HOLD_TIME_EXPDONE
+}ISP_HOLD_TIME_ENUM;
+
+typedef struct
+{
+    unsigned int Addr;   // register's addr
+    unsigned int Val;    // register's value
+}ISP_REG_STRUCT;
+
+typedef struct
+{
+    //unsigned int Data;   // pointer to ISP_REG_STRUCT
+    ISP_REG_STRUCT *pData;  // pointer to ISP_REG_STRUCT
+    unsigned int Count;  // count
+}ISP_REG_IO_STRUCT;
+
+typedef void (*pIspCallback)(void);
+
+typedef enum
+{
+    //Work queue. It is interruptible, so there can be "Sleep" in work queue function.
+    ISP_CALLBACK_WORKQUEUE_VD,
+    ISP_CALLBACK_WORKQUEUE_EXPDONE,
+    ISP_CALLBACK_WORKQUEUE_SENINF,
+    //Tasklet. It is uninterrupted, so there can NOT be "Sleep" in tasklet function.
+    ISP_CALLBACK_TASKLET_VD,
+    ISP_CALLBACK_TASKLET_EXPDONE,
+    ISP_CALLBACK_TASKLET_SENINF,
+    ISP_CALLBACK_AMOUNT
+}ISP_CALLBACK_ENUM;
+
+typedef struct
+{
+    ISP_CALLBACK_ENUM   Type;
+    pIspCallback        Func;
+}ISP_CALLBACK_STRUCT;
+
+//
+// length of the two memory areas
+#define RT_BUF_TBL_NPAGES 16
+#define ISP_RT_BUF_SIZE 16
+//#define ISP_RT_CQ0C_BUF_SIZE (ISP_RT_BUF_SIZE>>2)
+#define ISP_RT_CQ0C_BUF_SIZE (6)    //special for 6582
+
+
+//
+typedef enum
+{
+    _imgi_  = 0,
+    _imgci_,    // 1
+    _vipi_ ,    // 2
+    _vip2i_,    // 3
+    _imgo_,     // 4
+    _img2o_,    // 5
+    _dispo_,    // 6
+    _vido_,     // 7
+    _fdo_,      // 8
+    _lsci_,     // 9
+    _lcei_,     // 10
+    _rt_dma_max_
+}_isp_dma_enum_;
+//
+typedef struct {
+    unsigned int   memID;
+    unsigned int   size;
+    long long      base_vAddr;
+    unsigned int   base_pAddr;
+    unsigned int   timeStampS;
+    unsigned int   timeStampUs;
+    unsigned int   bFilled;
+}ISP_RT_BUF_INFO_STRUCT;
+//
+typedef struct  {
+    unsigned int           count;
+    ISP_RT_BUF_INFO_STRUCT  data[ISP_RT_BUF_SIZE];
+}ISP_DEQUE_BUF_INFO_STRUCT;
+//
+typedef struct  {
+    unsigned int           start;          //current DMA accessing buffer
+    unsigned int           total_count;    //total buffer number.Include Filled and empty
+    unsigned int           empty_count;    //total empty buffer number include current DMA accessing buffer
+    unsigned int           pre_empty_count;//previous total empty buffer number include current DMA accessing buffer
+    unsigned int           active;
+    ISP_RT_BUF_INFO_STRUCT  data[ISP_RT_BUF_SIZE];
+}ISP_RT_RING_BUF_INFO_STRUCT;
+//
+typedef enum
+{
+    ISP_RT_BUF_CTRL_ENQUE,          // 0
+    ISP_RT_BUF_CTRL_EXCHANGE_ENQUE, // 1
+    ISP_RT_BUF_CTRL_DEQUE,          // 2
+    ISP_RT_BUF_CTRL_IS_RDY,         // 3
+    ISP_RT_BUF_CTRL_GET_SIZE,       // 4
+    ISP_RT_BUF_CTRL_CLEAR,          // 5
+    ISP_RT_BUF_CTRL_MAX
+}ISP_RT_BUF_CTRL_ENUM;
+//
+typedef enum
+{
+    ISP_RTBC_STATE_INIT, // 0
+    ISP_RTBC_STATE_SOF,
+    ISP_RTBC_STATE_DONE,
+    ISP_RTBC_STATE_MAX
+}ISP_RTBC_STATE_ENUM;
+//
+typedef enum
+{
+    ISP_RTBC_BUF_EMPTY, // 0
+    ISP_RTBC_BUF_FILLED,// 1
+    ISP_RTBC_BUF_LOCKED,// 2
+}ISP_RTBC_BUF_STATE_ENUM;
+//
+typedef struct  {
+    ISP_RTBC_STATE_ENUM state;
+    unsigned long dropCnt;
+    ISP_RT_RING_BUF_INFO_STRUCT  ring_buf[_rt_dma_max_];
+}ISP_RT_BUF_STRUCT;
+//
+typedef struct  {
+    ISP_RT_BUF_CTRL_ENUM    ctrl;
+    _isp_dma_enum_          buf_id;
+    //unsigned int            data_ptr;
+    //unsigned int            ex_data_ptr; //exchanged buffer
+    ISP_RT_BUF_INFO_STRUCT  *data_ptr;
+    ISP_RT_BUF_INFO_STRUCT  *ex_data_ptr; //exchanged buffer
+    unsigned char           *pExtend;
+}ISP_BUFFER_CTRL_STRUCT;
+//
+//reference count
+#define _use_kernel_ref_cnt_
+//
+typedef enum
+{
+    ISP_REF_CNT_GET,    // 0
+    ISP_REF_CNT_INC,    // 1
+    ISP_REF_CNT_DEC,    // 2
+    ISP_REF_CNT_DEC_AND_RESET_IF_LAST_ONE,    // 3
+    ISP_REF_CNT_DEC_AND_RESET_P1_IF_LAST_ONE,    // 4
+    ISP_REF_CNT_DEC_AND_RESET_P2_IF_LAST_ONE,    // 5
+    ISP_REF_CNT_MAX
+}ISP_REF_CNT_CTRL_ENUM;
+//
+typedef enum
+{
+    ISP_REF_CNT_ID_IMEM,        // 0
+    ISP_REF_CNT_ID_ISP_FUNC,    // 1
+    ISP_REF_CNT_ID_GLOBAL_PIPE, // 2
+    ISP_REF_CNT_ID_P1_PIPE,     // 3
+    ISP_REF_CNT_ID_P2_PIPE,     // 4
+    ISP_REF_CNT_ID_MAX,
+}ISP_REF_CNT_ID_ENUM;
+//
+typedef struct  {
+    ISP_REF_CNT_CTRL_ENUM   ctrl;
+    ISP_REF_CNT_ID_ENUM     id;
+    signed int*           data_ptr;
+}ISP_REF_CNT_CTRL_STRUCT;
+
+
+/********************************************************************************************
+ pass1 real time buffer control use cq0c
+********************************************************************************************/
+//
+#define _rtbc_use_cq0c_
+
+#if defined(_rtbc_use_cq0c_)
+//
+typedef volatile union _CQ_RTBC_FBC_
+{
+    volatile struct
+    {
+        unsigned long FBC_CNT                   : 4;
+        unsigned long DROP_INT_EN               : 1;
+        unsigned long rsv_5                     : 6;
+        unsigned long RCNT_INC                  : 1;
+        unsigned long rsv_12                    : 2;
+        unsigned long FBC_EN                    : 1;
+        unsigned long LOCK_EN                   : 1;
+        unsigned long FB_NUM                    : 4;
+        unsigned long RCNT                      : 4;
+        unsigned long WCNT                      : 4;
+        unsigned long DROP_CNT                  : 4;
+    } Bits;
+    unsigned long Reg_val;
+}CQ_RTBC_FBC;
+
+typedef struct _cq_cmd_st_
+{
+    unsigned int inst;
+    unsigned int data_ptr_pa;
+}CQ_CMD_ST;
+/*
+typedef struct _cq_cmd_rtbc_st_
+{
+    CQ_CMD_ST imgo;
+    CQ_CMD_ST img2o;
+    CQ_CMD_ST cq0ci;
+    CQ_CMD_ST end;
+}CQ_CMD_RTBC_ST;
+*/
+typedef struct _cq_info_rtbc_st_
+{
+    CQ_CMD_ST imgo;
+    CQ_CMD_ST img2o;
+    CQ_CMD_ST next_cq0ci;
+    CQ_CMD_ST end;
+    unsigned int imgo_base_pAddr;
+    unsigned int img2o_base_pAddr;
+}CQ_INFO_RTBC_ST;
+typedef struct _cq_ring_cmd_st_
+{
+    CQ_INFO_RTBC_ST cq_rtbc;
+    unsigned long next_pa;
+    struct _cq_ring_cmd_st_ *pNext;
+}CQ_RING_CMD_ST;
+typedef struct _cq_rtbc_ring_st_
+{
+    CQ_RING_CMD_ST rtbc_ring[ISP_RT_CQ0C_BUF_SIZE];
+    unsigned int   imgo_ring_size;
+    unsigned int   img2o_ring_size;
+}CQ_RTBC_RING_ST;
+#endif
+
+
+#ifdef CONFIG_COMPAT
+
+typedef struct
+{
+    compat_uptr_t pData;
+    unsigned int Count;  // count
+} compat_ISP_REG_IO_STRUCT;
+
+typedef struct  {
+    ISP_RT_BUF_CTRL_ENUM    ctrl;
+    _isp_dma_enum_          buf_id;
+    compat_uptr_t           data_ptr;
+    compat_uptr_t           ex_data_ptr; //exchanged buffer
+    compat_uptr_t           pExtend;
+} compat_ISP_BUFFER_CTRL_STRUCT;
+
+typedef struct  {
+    ISP_REF_CNT_CTRL_ENUM   ctrl;
+    ISP_REF_CNT_ID_ENUM     id;
+    compat_uptr_t         data_ptr;
+} compat_ISP_REF_CNT_CTRL_STRUCT;
+
+
+#endif
+//
+/********************************************************************************************
+
+********************************************************************************************/
+
+
+/*******************************************************************************
+*
+********************************************************************************/
+typedef enum
+{
+    ISP_CMD_RESET,          //Reset
+    ISP_CMD_RESET_BUF,
+    ISP_CMD_READ_REG,       //Read register from driver
+    ISP_CMD_WRITE_REG,      //Write register to driver
+    ISP_CMD_HOLD_TIME,
+    ISP_CMD_HOLD_REG,       //Hold reg write to hw, on/off
+    ISP_CMD_WAIT_IRQ,       //Wait IRQ
+    ISP_CMD_READ_IRQ,       //Read IRQ
+    ISP_CMD_CLEAR_IRQ,      //Clear IRQ
+    ISP_CMD_DUMP_REG,       //Dump ISP registers , for debug usage
+    ISP_CMD_SET_USER_PID,   //for signal
+    ISP_CMD_RT_BUF_CTRL,   //for pass buffer control
+    ISP_CMD_REF_CNT,        //get imem reference count
+    ISP_CMD_DEBUG_FLAG,      //Dump message level
+    ISP_CMD_WAKELOCK_CTRL,   //isp wakelock control
+    ISP_CMD_SENSOR_FREQ_CTRL      // sensor frequence control
+}ISP_CMD_ENUM;
+//
+#define ISP_RESET           _IO  (ISP_MAGIC, ISP_CMD_RESET)
+#define ISP_RESET_BUF       _IO  (ISP_MAGIC, ISP_CMD_RESET_BUF)
+#define ISP_READ_REGISTER   _IOWR(ISP_MAGIC, ISP_CMD_READ_REG,      ISP_REG_IO_STRUCT)
+#define ISP_WRITE_REGISTER  _IOWR(ISP_MAGIC, ISP_CMD_WRITE_REG,     ISP_REG_IO_STRUCT)
+#define ISP_HOLD_REG_TIME   _IOW (ISP_MAGIC, ISP_CMD_HOLD_TIME,     ISP_HOLD_TIME_ENUM)
+#define ISP_HOLD_REG        _IOW (ISP_MAGIC, ISP_CMD_HOLD_REG,      bool)
+#define ISP_WAIT_IRQ        _IOW (ISP_MAGIC, ISP_CMD_WAIT_IRQ,      ISP_WAIT_IRQ_STRUCT)
+#define ISP_READ_IRQ        _IOR (ISP_MAGIC, ISP_CMD_READ_IRQ,      ISP_READ_IRQ_STRUCT)
+#define ISP_CLEAR_IRQ       _IOW (ISP_MAGIC, ISP_CMD_CLEAR_IRQ,     ISP_CLEAR_IRQ_STRUCT)
+#define ISP_DUMP_REG        _IO  (ISP_MAGIC, ISP_CMD_DUMP_REG)
+#define ISP_SET_USER_PID    _IOW (ISP_MAGIC, ISP_CMD_SET_USER_PID,  unsigned long)
+#define ISP_BUFFER_CTRL     _IOWR(ISP_MAGIC, ISP_CMD_RT_BUF_CTRL,   ISP_BUFFER_CTRL_STRUCT)
+#define ISP_REF_CNT_CTRL    _IOWR(ISP_MAGIC, ISP_CMD_REF_CNT,       ISP_REF_CNT_CTRL_STRUCT)
+#define ISP_DEBUG_FLAG      _IOW (ISP_MAGIC, ISP_CMD_DEBUG_FLAG,    unsigned long)
+#define ISP_WAKELOCK_CTRL   _IOWR (ISP_MAGIC, ISP_CMD_WAKELOCK_CTRL,unsigned long)
+#define ISP_SENSOR_FREQ_CTRL  _IOW (ISP_MAGIC, ISP_CMD_SENSOR_FREQ_CTRL, unsigned long)
+
+#ifdef CONFIG_COMPAT
+#define COMPAT_ISP_READ_REGISTER    _IOWR(ISP_MAGIC, ISP_CMD_READ_REG,      compat_ISP_REG_IO_STRUCT)
+#define COMPAT_ISP_WRITE_REGISTER   _IOWR(ISP_MAGIC, ISP_CMD_WRITE_REG,     compat_ISP_REG_IO_STRUCT)
+#define COMPAT_ISP_BUFFER_CTRL      _IOWR(ISP_MAGIC, ISP_CMD_RT_BUF_CTRL,   compat_ISP_BUFFER_CTRL_STRUCT)
+#define COMPAT_ISP_REF_CNT_CTRL     _IOWR(ISP_MAGIC, ISP_CMD_REF_CNT,       compat_ISP_REF_CNT_CTRL_STRUCT)
+#define COMPAT_ISP_SET_USER_PID     _IOW (ISP_MAGIC, ISP_CMD_SET_USER_PID,  compat_uptr_t)
+#define COMPAT_ISP_DEBUG_FLAG       _IOW (ISP_MAGIC, ISP_CMD_DEBUG_FLAG,    compat_uptr_t)
+#define COMPAT_ISP_WAKELOCK_CTRL    _IOWR(ISP_MAGIC, ISP_CMD_WAKELOCK_CTRL, compat_uptr_t)
+#define COMPAT_ISP_SENSOR_FREQ_CTRL  _IOW(ISP_MAGIC, ISP_CMD_SENSOR_FREQ_CTRL, compat_uptr_t)
+#endif
+
+//
+bool ISP_RegCallback(ISP_CALLBACK_STRUCT* pCallback);
+bool ISP_UnregCallback(ISP_CALLBACK_ENUM   Type);
+
+bool ISP_ControlMdpClock(bool en);
+int32_t ISP_MDPClockOnCallback(uint64_t engineFlag);
+int32_t ISP_MDPDumpCallback(uint64_t engineFlag,
+                            int level);
+int32_t ISP_MDPResetCallback(uint64_t engineFlag);
+
+int32_t ISP_MDPClockOffCallback(uint64_t engineFlag);
+
+//
+#endif
+
diff --git a/kernel-headers/camera_isp_FrmB_D2.h b/kernel-headers/camera_isp_FrmB_D2.h
new file mode 100644
index 0000000..e0a6c3d
--- /dev/null
+++ b/kernel-headers/camera_isp_FrmB_D2.h
@@ -0,0 +1,573 @@
+/*
+* Copyright (C) 2014 The Android Open Source Project
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*      http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*/
+
+
+#ifndef _MT_ISP_FRMB_H
+#define _MT_ISP_FRMB_H
+
+#include "camera_isp_D2.h"
+
+//#define KERNEL_LOG  //enable debug log flag if defined
+#define ISR_LOG_ON  //turn on log print at isr if defined
+#define T_STAMP_2_0 //time stamp workaround method. (increase timestamp baseon fix fps, not read at each isr)
+
+#define _rtbc_buf_que_2_0_
+
+/*******************************************************************************
+*
+********************************************************************************/
+typedef enum
+{
+    ISP_IRQ_CLEAR_NONE_FRMB,
+    ISP_IRQ_CLEAR_WAIT_FRMB,
+    ISP_IRQ_CLEAR_STATUS_FRMB,
+    ISP_IRQ_CLEAR_ALL_FRMB
+}ISP_IRQ_CLEAR_ENUM_FRMB;
+
+
+typedef enum
+{
+    ISP_IRQ_TYPE_INT_FRMB,
+    ISP_IRQ_TYPE_DMA_FRMB,
+    ISP_IRQ_TYPE_INTB_FRMB,
+    ISP_IRQ_TYPE_DMAB_FRMB,
+    ISP_IRQ_TYPE_INTC_FRMB,
+    ISP_IRQ_TYPE_DMAC_FRMB,
+    ISP_IRQ_TYPE_INTX_FRMB,
+    ISP_IRQ_TYPE_DMAX_FRMB,
+    ISP_IRQ_TYPE_AMOUNT_FRMB
+}ISP_IRQ_TYPE_ENUM_FRMB;
+
+
+typedef enum    //special user for specific operation
+{
+    ISP_IRQ_WAITIRQ_SPEUSER_NONE = 0,
+    ISP_IRQ_WAITIRQ_SPEUSER_EIS = 1,
+    ISP_IRQ_WAITIRQ_SPEUSER_NUM
+}ISP_IRQ_WAITIRQ_SPEUSER_ENUM;
+typedef struct
+{
+    ISP_IRQ_TYPE_ENUM_FRMB   Type;
+    unsigned int                            Status;
+    int                                             UserKey;                     /* user key for doing interrupt operation */
+}ISP_IRQ_USER_STRUCT_FRMB;
+
+typedef struct
+{
+    unsigned int    tLastSig_sec;                       /* time stamp of the latest occuring signal*/
+    unsigned int    tLastSig_usec;                  /* time stamp of the latest occuring signal*/
+    unsigned int    tMark2WaitSig_sec;            /* time period from marking a signal to user try to wait and get the signal*/
+    unsigned int    tMark2WaitSig_usec;            /* time period from marking a signal to user try to wait and get the signal*/
+    unsigned int    tLastSig2GetSig_sec;         /* time period from latest occuring signal to user try to wait and get the signal*/
+    unsigned int    tLastSig2GetSig_usec;         /* time period from latest occuring signal to user try to wait and get the signal*/
+    int                        passedbySigcnt;          /* the count for the signal passed by  */
+}ISP_IRQ_TIME_STRUCT_FRMB;
+
+typedef struct
+{
+    unsigned int       tLastSOF2P1done_sec;                       /* time stamp of the last closest occuring sof signal for pass1 done*/
+    unsigned int       tLastSOF2P1done_usec;                  /* time stamp of the last closest occuring sof signal for pass1 done*/
+}ISP_EIS_META_STRUCT;
+
+typedef struct
+{
+    ISP_IRQ_CLEAR_ENUM_FRMB  Clear;
+    ISP_IRQ_USER_STRUCT_FRMB  UserInfo;
+    ISP_IRQ_TIME_STRUCT_FRMB  TimeInfo;
+    ISP_EIS_META_STRUCT EisMeta;
+    ISP_IRQ_WAITIRQ_SPEUSER_ENUM SpecUser;
+    unsigned int       Timeout;                     /* time out for waiting for a specific interrupt */
+    unsigned int       bDumpReg;
+}ISP_WAIT_IRQ_STRUCT_FRMB;
+
+typedef struct
+{
+    int  userKey;
+    char* userName;
+}ISP_REGISTER_USERKEY_STRUCT_FRMB;
+
+
+typedef struct
+{
+    ISP_IRQ_TYPE_ENUM   Type;
+    unsigned int       Status;
+}ISP_READ_IRQ_STRUCT_FRMB;
+
+typedef struct
+{
+    ISP_IRQ_TYPE_ENUM   Type;
+    unsigned int       Status;
+}ISP_CLEAR_IRQ_STRUCT_FRMB;
+
+typedef enum
+{
+    ISP_HOLD_TIME_VD_FRMB,
+    ISP_HOLD_TIME_EXPDONE_FRMB
+}ISP_HOLD_TIME_ENUM_FRMB;
+
+typedef struct
+{
+    unsigned int Addr_FrmB;   // register's addr
+    unsigned int Val_FrmB;    // register's value
+}ISP_REG_STRUCT_FRMB;
+
+typedef struct
+{
+    //unsigned int Data_FrmB;   // pointer to ISP_REG_STRUCT
+    ISP_REG_STRUCT_FRMB *pData_FrmB;
+    unsigned int Count_FrmB;  // count
+}ISP_REG_IO_STRUCT_FRMB;
+
+//typedef void (*pIspCallback)(void);
+
+typedef enum
+{
+    //Work queue. It is interruptible, so there can be "Sleep" in work queue function.
+    ISP_CALLBACK_WORKQUEUE_VD_FRMB,
+    ISP_CALLBACK_WORKQUEUE_EXPDONE_FRMB,
+    //Tasklet. It is uninterrupted, so there can NOT be "Sleep" in tasklet function.
+    ISP_CALLBACK_TASKLET_VD_FRMB,
+    ISP_CALLBACK_TASKLET_EXPDONE_FRMB,
+    ISP_CALLBACK_AMOUNT_FRMB
+}ISP_CALLBACK_ENUM_FRMB;
+
+typedef struct
+{
+    ISP_CALLBACK_ENUM   Type_FrmB;
+    pIspCallback        Func_FrmB;
+}ISP_CALLBACK_STRUCT_FRMB;
+
+//
+// length of the two memory areas
+#define P1_DEQUE_CNT    1
+////////////////////////////////////////
+//DEFINED IN CAMREA_ISP.H
+//#define RT_BUF_TBL_NPAGES 16
+//#define ISP_RT_BUF_SIZE 16
+//#define ISP_RT_CQ0C_BUF_SIZE (ISP_RT_BUF_SIZE)//(ISP_RT_BUF_SIZE>>1)
+///////////////////////////////////////
+//pass1 setting sync index
+#define ISP_REG_P1_CFG_IDX 0x4090
+
+
+//
+typedef enum
+{
+    _cam_tg_  = 0,
+    _cam_tg2_ ,     // 1
+    _camsv_tg_,     // 2
+    _camsv2_tg_,    // 3
+    _cam_tg_max_
+}_isp_tg_enum_;
+
+//
+typedef struct {
+    unsigned int   w;
+    unsigned int   h;
+    unsigned int   xsize;
+    unsigned int   stride;
+    unsigned int   fmt;
+    unsigned int   pxl_id;
+    unsigned int   wbn;
+    unsigned int   ob;
+    unsigned int   lsc;
+    unsigned int   rpg;
+    unsigned int   m_num_0;
+    unsigned int   frm_cnt;
+}ISP_RT_IMAGE_INFO_STRUCT;
+
+typedef struct {
+    unsigned int   srcX;    //crop window start point
+    unsigned int   srcY;
+    unsigned int   srcW;    //crop window size
+    unsigned int   srcH;
+    unsigned int   dstW;    //rrz out size
+    unsigned int   dstH;
+}ISP_RT_HRZ_INFO_STRUCT;
+
+typedef struct{
+    unsigned int x; //in pix
+    unsigned int y; //in pix
+    unsigned int w; //in byte
+    unsigned int h; //in byte
+}ISP_RT_DMAO_CROPPING_STRUCT;
+
+
+typedef struct {
+    unsigned int   memID;
+    unsigned int   size;
+    long long   base_vAddr;
+    unsigned int   base_pAddr;
+    unsigned int   timeStampS;
+    unsigned int   timeStampUs;
+    unsigned int   bFilled;
+    ISP_RT_IMAGE_INFO_STRUCT image;
+    ISP_RT_HRZ_INFO_STRUCT HrzInfo;
+    ISP_RT_DMAO_CROPPING_STRUCT dmaoCrop;   //imgo
+    unsigned int          bDequeued;
+    signed int         bufIdx;//used for replace buffer
+}ISP_RT_BUF_INFO_STRUCT_FRMB;
+
+//
+typedef struct  {
+    unsigned int           count;
+    unsigned int           sof_cnt;         //cnt for current sof
+    unsigned int           img_cnt;         //cnt for mapping to which sof
+    //rome support only deque 1 image at a time
+    //ISP_RT_BUF_INFO_STRUCT  data[ISP_RT_BUF_SIZE];
+    ISP_RT_BUF_INFO_STRUCT_FRMB  data[P1_DEQUE_CNT];
+}ISP_DEQUE_BUF_INFO_STRUCT_FRMB;
+
+//
+typedef struct  {
+    unsigned int           start;          //current DMA accessing buffer
+    unsigned int           total_count;    //total buffer number.Include Filled and empty
+    unsigned int           empty_count;    //total empty buffer number include current DMA accessing buffer
+    unsigned int           pre_empty_count;//previous total empty buffer number include current DMA accessing buffer
+    unsigned int           active;
+    unsigned int           read_idx;
+    unsigned int           img_cnt;         //cnt for mapping to which sof
+    ISP_RT_BUF_INFO_STRUCT_FRMB  data[ISP_RT_BUF_SIZE];
+}ISP_RT_RING_BUF_INFO_STRUCT_FRMB;
+
+//
+typedef enum
+{
+    ISP_RT_BUF_CTRL_ENQUE_FRMB,      // 0
+#ifdef _rtbc_buf_que_2_0_
+            ISP_RT_BUF_CTRL_ENQUE_IMD_FRMB,
+#else
+            ISP_RT_BUF_CTRL_ENQUE_IMD_FRMB = ISP_RT_BUF_CTRL_ENQUE_FRMB,
+#endif
+    ISP_RT_BUF_CTRL_EXCHANGE_ENQUE_FRMB, // 1
+    ISP_RT_BUF_CTRL_DEQUE_FRMB,          // 2
+    ISP_RT_BUF_CTRL_IS_RDY_FRMB,         // 3
+#ifdef _rtbc_buf_que_2_0_
+    ISP_RT_BUF_CTRL_DMA_EN_FRMB,           // 4
+#endif
+    ISP_RT_BUF_CTRL_GET_SIZE_FRMB,       // 5
+    ISP_RT_BUF_CTRL_CLEAR_FRMB,          // 6
+    ISP_RT_BUF_CTRL_CUR_STATUS_FRMB,     //7
+    ISP_RT_BUF_CTRL_MAX_FRMB
+}ISP_RT_BUF_CTRL_ENUM_FRMB;
+
+typedef struct  {
+    ISP_RTBC_STATE_ENUM state;
+    unsigned long dropCnt;
+    ISP_RT_RING_BUF_INFO_STRUCT_FRMB  ring_buf[_rt_dma_max_];
+}ISP_RT_BUF_STRUCT_FRMB;
+//
+typedef struct  {
+    ISP_RT_BUF_CTRL_ENUM_FRMB    ctrl;
+    _isp_dma_enum_          buf_id;
+    //unsigned int            data_ptr;
+    //unsigned int            ex_data_ptr; //exchanged buffer
+    ISP_RT_BUF_INFO_STRUCT_FRMB *data_ptr;
+    ISP_RT_BUF_INFO_STRUCT_FRMB *ex_data_ptr;
+    unsigned char *pExtend;
+}ISP_BUFFER_CTRL_STRUCT_FRMB;
+
+
+//
+//reference count
+#define _use_kernel_ref_cnt_
+
+//
+typedef enum
+{
+    ISP_REF_CNT_GET_FRMB,    // 0
+    ISP_REF_CNT_INC_FRMB,    // 1
+    ISP_REF_CNT_DEC_FRMB,    // 2
+    ISP_REF_CNT_DEC_AND_RESET_P1_P2_IF_LAST_ONE_FRMB,    // 3
+    ISP_REF_CNT_DEC_AND_RESET_P1_IF_LAST_ONE_FRMB,    // 4
+    ISP_REF_CNT_DEC_AND_RESET_P2_IF_LAST_ONE_FRMB,    // 5
+    ISP_REF_CNT_MAX_FRMB
+}ISP_REF_CNT_CTRL_ENUM_FRMB;
+
+//
+typedef enum
+{
+    ISP_REF_CNT_ID_IMEM_FRMB,    // 0
+    ISP_REF_CNT_ID_ISP_FUNC_FRMB,// 1
+    ISP_REF_CNT_ID_GLOBAL_PIPE_FRMB, // 2
+    ISP_REF_CNT_ID_P1_PIPE_FRMB,     // 3
+    ISP_REF_CNT_ID_P2_PIPE_FRMB,     // 4
+    ISP_REF_CNT_ID_MAX_FRMB,
+}ISP_REF_CNT_ID_ENUM_FRMB;
+
+typedef struct  {
+    ISP_REF_CNT_CTRL_ENUM_FRMB   ctrl;
+    ISP_REF_CNT_ID_ENUM_FRMB     id;
+    signed int*           data_ptr;
+}ISP_REF_CNT_CTRL_STRUCT_FRMB;
+
+
+//struct for enqueue/dequeue control in ihalpipe wrapper
+typedef enum
+{
+    ISP_ED_BUFQUE_CTRL_ENQUE_FRAME=0,          // 0,signal that a specific buffer is enqueued
+    ISP_ED_BUFQUE_CTRL_WAIT_DEQUE,             // 1,a dequeue thread is waiting to do dequeue
+    ISP_ED_BUFQUE_CTRL_DEQUE_SUCCESS,          // 2,signal that a buffer is dequeued (success)
+    ISP_ED_BUFQUE_CTRL_DEQUE_FAIL,             // 3,signal that a buffer is dequeued (fail)
+    ISP_ED_BUFQUE_CTRL_WAIT_FRAME,             // 4,wait for a specific buffer
+    ISP_ED_BUFQUE_CTRL_WAKE_WAITFRAME,         // 5,wake all sleeped users to check buffer is dequeued or not
+    ISP_ED_BUFQUE_CTRL_CLAER_ALL,              // 6,free all recored dequeued buffer
+    ISP_ED_BUFQUE_CTRL_MAX
+}ISP_ED_BUFQUE_CTRL_ENUM;
+
+typedef struct
+{
+    ISP_ED_BUFQUE_CTRL_ENUM ctrl;
+    unsigned int            processID;
+    unsigned int            callerID;
+    int                     p2burstQIdx;
+    int                     p2dupCQIdx;
+    unsigned int            timeoutUs;
+}ISP_ED_BUFQUE_STRUCT_FRMB;
+
+typedef enum
+{
+    ISP_ED_BUF_STATE_NONE  =-1,
+    ISP_ED_BUF_STATE_ENQUE=0,
+    ISP_ED_BUF_STATE_RUNNING,
+    ISP_ED_BUF_STATE_WAIT_DEQUE_FAIL,
+    ISP_ED_BUF_STATE_DEQUE_SUCCESS,
+    ISP_ED_BUF_STATE_DEQUE_FAIL
+}ISP_ED_BUF_STATE_ENUM;
+
+
+/********************************************************************************************
+ pass1 real time buffer control use cq0c
+********************************************************************************************/
+//
+//#define _rtbc_use_cq0c_ //defined in camera_isp.h
+
+#define _MAGIC_NUM_ERR_HANDLING_
+
+#if defined(_rtbc_use_cq0c_)
+//
+typedef struct _cq_info_rtbc_st_frmb_
+{
+    CQ_CMD_ST imgo_frmb;
+    CQ_CMD_ST img2o_frmb;//rrzo
+    CQ_CMD_ST next_cq0ci_frmb;
+    CQ_CMD_ST end_frmb;
+    unsigned long imgo_base_pAddr_frmb;
+    unsigned long img2o_base_pAddr_frmb;//rrzo
+    signed int imgo_buf_idx_frmb; //used for replace buffer
+    signed int img2o_buf_idx_frmb; //used for replace buffer//rrzo
+}CQ_INFO_RTBC_ST_FRMB;
+
+typedef struct _cq_ring_cmd_st_frmb_
+{
+    CQ_INFO_RTBC_ST_FRMB cq_rtbc_frmb;
+    unsigned long next_pa_frmb;
+    struct _cq_ring_cmd_st_frmb_ *pNext_frmb;
+}CQ_RING_CMD_ST_FRMB;
+
+typedef struct _cq_rtbc_ring_st_frmb_
+{
+    CQ_RING_CMD_ST_FRMB rtbc_ring_frmb[ISP_RT_CQ0C_BUF_SIZE];
+    unsigned long   imgo_ring_size_frmb;
+    unsigned long   img2o_ring_size_frmb;//rrzo
+}CQ_RTBC_RING_ST_FRMB;
+
+#endif
+
+//CQ0B for AE smoothing, set obc_gain0~3
+typedef struct _cq0b_info_rtbc_st_frmb_
+{
+    CQ_CMD_ST ob_frmb;
+    CQ_CMD_ST end_frmb;
+}CQ0B_INFO_RTBC_ST_FRMB;
+
+typedef struct _cq0b_ring_cmd_st_frmb_
+{
+    CQ0B_INFO_RTBC_ST_FRMB cq0b_rtbc_frmb;
+    unsigned long next_pa_frmb;
+    struct _cq0b_ring_cmd_st_frmb_ *pNext_frmb;
+}CQ0B_RING_CMD_ST_FRMB;
+
+typedef struct _cq0b_rtbc_ring_st_frmb_
+{
+    CQ0B_RING_CMD_ST_FRMB rtbc_ring_frmb;
+}CQ0B_RTBC_RING_ST_FRMB;
+
+
+#ifdef CONFIG_COMPAT
+typedef struct
+{
+    int  userKey;
+    compat_uptr_t userName;
+}compat_ISP_REGISTER_USERKEY_STRUCT_FRMB;
+
+typedef struct
+{
+    compat_uptr_t pData;
+    unsigned int Count;  // count
+} compat_ISP_REG_IO_STRUCT_FRMB;
+
+typedef struct  {
+    ISP_RT_BUF_CTRL_ENUM    ctrl;
+    _isp_dma_enum_          buf_id;
+    compat_uptr_t           data_ptr;
+    compat_uptr_t           ex_data_ptr; //exchanged buffer
+    compat_uptr_t           pExtend;
+} compat_ISP_BUFFER_CTRL_STRUCT_FRMB;
+
+typedef struct  {
+    ISP_REF_CNT_CTRL_ENUM   ctrl;
+    ISP_REF_CNT_ID_ENUM     id;
+    compat_uptr_t         data_ptr;
+} compat_ISP_REF_CNT_CTRL_STRUCT_FRMB;
+#endif
+
+//
+/********************************************************************************************
+
+********************************************************************************************/
+
+
+/*******************************************************************************
+*
+********************************************************************************/
+
+typedef enum
+{
+    //ISP_CMD_RESET,          //Reset
+    //ISP_CMD_RESET_BUF,
+    //ISP_CMD_READ_REG,       //Read register from driver
+    //ISP_CMD_WRITE_REG,      //Write register to driver
+    //ISP_CMD_HOLD_TIME,
+    //ISP_CMD_HOLD_REG,       //Hold reg write to hw, on/off
+    //ISP_CMD_WAIT_IRQ,       //Wait IRQ
+    ///ISP_CMD_READ_IRQ,       //Read IRQ
+    //ISP_CMD_CLEAR_IRQ,      //Clear IRQ
+    //ISP_CMD_DUMP_REG,       //Dump ISP registers , for debug usage
+    //ISP_CMD_SET_USER_PID,   //for signal
+    //ISP_CMD_RT_BUF_CTRL,   //for pass buffer control
+    //ISP_CMD_REF_CNT,        //get imem reference count
+    //ISP_CMD_DEBUG_FLAG,      //Dump message level
+    //ISP_CMD_SENSOR_FREQ_CTRL      // sensor frequence control
+
+    ISP_CMD_REGISTER_IRQ_FRMB = ISP_CMD_SENSOR_FREQ_CTRL+1 ,    //register for a specific irq
+    ISP_CMD_DEBUG_FLAG_FRMB,
+    ISP_CMD_UNREGISTER_IRQ_FRMB,  //unregister for a specific irq
+    ISP_CMD_WAIT_IRQ_FRMB,       //Wait IRQ
+    ISP_CMD_ED_QUEBUF_CTRL_FRMB,
+    ISP_CMD_UPDATE_REGSCEN_FRMB,
+    ISP_CMD_QUERY_REGSCEN_FRMB,
+    ISP_CMD_UPDATE_BURSTQNUM_FRMB,
+    ISP_CMD_QUERY_BURSTQNUM_FRMB,
+    ISP_CMD_DUMP_ISR_LOG_FRMB,   //dump isr log
+    ISP_CMD_GET_CUR_SOF_FRMB,
+    ISP_CMD_GET_DMA_ERR_FRMB,
+    ISP_CMD_GET_INT_ERR_FRMB,
+#ifdef T_STAMP_2_0
+    ISP_CMD_SET_FPS_FRMB,
+#endif
+    ISP_CMD_REGISTER_IRQ_USER_KEY,              /* register for a user key to do irq operation */
+    ISP_CMD_MARK_IRQ_REQUEST,                    /* mark for a specific register befor wait for the interrupt if needed */
+    ISP_CMD_GET_MARK2QUERY_TIME,             /* query time information between read and mark */
+    ISP_CMD_FLUSH_IRQ_REQUEST,                    /* flush signal */
+    ISP_CMD_SET_CAM_VERSION,                    /* set camera version */
+    ISP_CMD_GET_DROP_FRAME_FRMB,            //dump current frame informaiton, 1 for drop frmae, 2 for last working frame
+}ISP_CMD_ENUM_FRMB;
+//
+//#define ISP_RESET           _IO  (ISP_MAGIC, ISP_CMD_RESET)
+//#define ISP_RESET_BUF       _IO  (ISP_MAGIC, ISP_CMD_RESET_BUF)
+//#define ISP_READ_REGISTER   _IOWR(ISP_MAGIC, ISP_CMD_READ_REG,      ISP_REG_IO_STRUCT)
+//#define ISP_WRITE_REGISTER  _IOWR(ISP_MAGIC, ISP_CMD_WRITE_REG,     ISP_REG_IO_STRUCT)
+//#define ISP_HOLD_REG_TIME   _IOW (ISP_MAGIC, ISP_CMD_HOLD_TIME,     ISP_HOLD_TIME_ENUM)
+//#define ISP_HOLD_REG        _IOW (ISP_MAGIC, ISP_CMD_HOLD_REG,      bool)
+//#define ISP_WAIT_IRQ        _IOW (ISP_MAGIC, ISP_CMD_WAIT_IRQ,      ISP_WAIT_IRQ_STRUCT)
+//#define ISP_READ_IRQ        _IOR (ISP_MAGIC, ISP_CMD_READ_IRQ,      ISP_READ_IRQ_STRUCT)
+//#define ISP_CLEAR_IRQ       _IOW (ISP_MAGIC, ISP_CMD_CLEAR_IRQ,     ISP_CLEAR_IRQ_STRUCT)
+//#define ISP_DUMP_REG        _IO  (ISP_MAGIC, ISP_CMD_DUMP_REG)
+//#define ISP_SET_USER_PID    _IOW (ISP_MAGIC, ISP_CMD_SET_USER_PID,    unsigned long)
+//#define ISP_BUFFER_CTRL     _IOWR(ISP_MAGIC, ISP_CMD_RT_BUF_CTRL,    ISP_BUFFER_CTRL_STRUCT)
+//#define ISP_REF_CNT_CTRL    _IOWR(ISP_MAGIC, ISP_CMD_REF_CNT,       ISP_REF_CNT_CTRL_STRUCT)
+#define ISP_DEBUG_FLAG_FRMB         _IOW (ISP_MAGIC, ISP_CMD_DEBUG_FLAG_FRMB,    unsigned long)
+//#define ISP_SENSOR_FREQ_CTRL  _IOW (ISP_MAGIC, ISP_CMD_SENSOR_FREQ_CTRL,    unsigned long)
+#define ISP_REGISTER_IRQ_FRMB       _IOW (ISP_MAGIC, ISP_CMD_REGISTER_IRQ_FRMB,  ISP_WAIT_IRQ_STRUCT_FRMB)
+#define ISP_UNREGISTER_IRQ_FRMB     _IOW (ISP_MAGIC, ISP_CMD_UNREGISTER_IRQ_FRMB,  ISP_WAIT_IRQ_STRUCT_FRMB)
+#define ISP_WAIT_IRQ_FRMB           _IOW (ISP_MAGIC, ISP_CMD_WAIT_IRQ_FRMB,  ISP_WAIT_IRQ_STRUCT_FRMB)
+#define ISP_ED_QUEBUF_CTRL_FRMB     _IOWR (ISP_MAGIC, ISP_CMD_ED_QUEBUF_CTRL_FRMB, ISP_ED_BUFQUE_STRUCT_FRMB)
+#define ISP_UPDATE_REGSCEN_FRMB     _IOWR (ISP_MAGIC, ISP_CMD_UPDATE_REGSCEN_FRMB, unsigned int)
+#define ISP_QUERY_REGSCEN_FRMB      _IOR (ISP_MAGIC, ISP_CMD_QUERY_REGSCEN_FRMB, unsigned int)
+#define ISP_UPDATE_BURSTQNUM_FRMB   _IOW(ISP_MAGIC,ISP_CMD_UPDATE_BURSTQNUM_FRMB, int)
+#define ISP_QUERY_BURSTQNUM_FRMB    _IOR (ISP_MAGIC,ISP_CMD_QUERY_BURSTQNUM_FRMB, int)
+#define ISP_DUMP_ISR_LOG_FRMB       _IO  (ISP_MAGIC, ISP_CMD_DUMP_ISR_LOG_FRMB)
+#define ISP_GET_CUR_SOF_FRMB        _IOWR(ISP_MAGIC, ISP_CMD_GET_CUR_SOF_FRMB, unsigned long)
+#define ISP_GET_DMA_ERR_FRMB        _IOWR (ISP_MAGIC, ISP_CMD_GET_DMA_ERR_FRMB, unsigned int)
+#define ISP_GET_INT_ERR_FRMB        _IOR (ISP_MAGIC, ISP_CMD_GET_INT_ERR_FRMB, unsigned long)
+#ifdef T_STAMP_2_0
+    #define ISP_SET_FPS_FRMB        _IOW (ISP_MAGIC, ISP_CMD_SET_FPS_FRMB,    unsigned int)
+#endif
+#define ISP_GET_DROP_FRAME_FRMB     _IOWR(ISP_MAGIC, ISP_CMD_GET_DROP_FRAME_FRMB, unsigned int)
+#define ISP_REGISTER_IRQ_USER_KEY   _IOWR(ISP_MAGIC,ISP_CMD_REGISTER_IRQ_USER_KEY, ISP_REGISTER_USERKEY_STRUCT_FRMB)
+#define ISP_MARK_IRQ_REQUEST        _IOWR(ISP_MAGIC,ISP_CMD_MARK_IRQ_REQUEST,ISP_WAIT_IRQ_STRUCT_FRMB)
+#define ISP_GET_MARK2QUERY_TIME     _IOWR(ISP_MAGIC,ISP_CMD_GET_MARK2QUERY_TIME,ISP_WAIT_IRQ_STRUCT_FRMB)
+#define ISP_FLUSH_IRQ_REQUEST       _IOW(ISP_MAGIC,ISP_CMD_FLUSH_IRQ_REQUEST,ISP_WAIT_IRQ_STRUCT_FRMB)
+#define ISP_SET_CAM_VERSION         _IOW(ISP_MAGIC,ISP_CMD_SET_CAM_VERSION, bool)
+
+#ifdef CONFIG_COMPAT
+#define COMPAT_ISP_DEBUG_FLAG_FRMB      _IOW(ISP_MAGIC, ISP_CMD_DEBUG_FLAG_FRMB,    compat_uptr_t)
+#define COMPAT_ISP_REGISTER_IRQ_USER_KEY    _IOWR(ISP_MAGIC, ISP_CMD_REGISTER_IRQ_USER_KEY,    compat_ISP_REGISTER_USERKEY_STRUCT_FRMB)
+#define COMPAT_ISP_GET_DMA_ERR_FRMB     _IOWR(ISP_MAGIC, ISP_CMD_GET_DMA_ERR_FRMB,  compat_uptr_t)
+#define COMPAT_ISP_GET_INT_ERR_FRMB     _IOR(ISP_MAGIC, ISP_CMD_GET_INT_ERR_FRMB, compat_uptr_t)
+#define COMPAT_ISP_WAIT_IRQ             _IOW (ISP_MAGIC, ISP_CMD_WAIT_IRQ_FRMB,      compat_ISP_WAIT_IRQ_STRUCT_FRMB)
+#define COMPAT_ISP_MARK_IRQ_REQUEST     _IOWR(ISP_MAGIC,ISP_CMD_MARK_IRQ_REQUEST,compat_ISP_WAIT_IRQ_STRUCT_FRMB)
+#define COMPAT_ISP_GET_MARK2QUERY_TIME  _IOWR(ISP_MAGIC,ISP_CMD_GET_MARK2QUERY_TIME,compat_ISP_WAIT_IRQ_STRUCT_FRMB)
+#define COMPAT_ISP_FLUSH_IRQ_REQUEST    _IOW(ISP_MAGIC,ISP_CMD_FLUSH_IRQ_REQUEST,compat_ISP_WAIT_IRQ_STRUCT_FRMB)
+#define COMPAT_ISP_GET_CUR_SOF_FRMB     _IOWR(ISP_MAGIC, ISP_CMD_GET_CUR_SOF_FRMB, compat_uptr_t)
+#endif
+
+//
+
+
+//
+//int32_t ISP_MDPClockOnCallback(uint64_t engineFlag);
+//int32_t ISP_MDPDumpCallback(uint64_t engineFlag, int level);
+//int32_t ISP_MDPResetCallback(uint64_t engineFlag);
+//int32_t ISP_MDPClockOffCallback(uint64_t engineFlag);
+//int32_t ISP_BeginGCECallback(uint32_t taskID, uint32_t *regCount, uint32_t **regAddress);
+//int32_t ISP_EndGCECallback(uint32_t taskID, uint32_t regCount, uint32_t *regValues);
+//
+
+//basically , should separate into p1/p1_d/p2/camsv/camsv_d,
+//currently, only use camsv/camsv_d/others
+typedef enum _eISPIrq
+{
+    _IRQ            = 0,
+    _IRQ_D          = 1,
+    _CAMSV_IRQ      = 2,
+    _CAMSV_D_IRQ    = 3,
+    _IRQ_MAX        = 4,
+}eISPIrq;
+//
+
+//static int ISP_ED_BufQue_CTRL_FUNC(ISP_ED_BUFQUE_STRUCT param);
+//static int ISP_RTBC_ENQUE_FRMB(int dma,ISP_RT_BUF_INFO_STRUCT* prt_buf_info);
+//static int ISP_RTBC_DEQUE_FRMB(int dma,ISP_DEQUE_BUF_INFO_STRUCT*    pdeque_buf);
+//static long ISP_Buf_CTRL_FUNC_FRMB(unsigned int Param);
+//static int ISP_SOF_Buf_Get_FRMB(eISPIrq irqT,unsigned long long sec,unsigned long usec,bool bDrop);
+//static int ISP_DONE_Buf_Time_FrmB(eISPIrq irqT,unsigned long long sec,unsigned long usec);
+//static int ISP_WaitIrq_FrmB(ISP_WAIT_IRQ_STRUCT_FRMB* WaitIrq);
+//
+
+#endif
+
diff --git a/kernel-headers/camera_pipe_mgr_D2.h b/kernel-headers/camera_pipe_mgr_D2.h
new file mode 100644
index 0000000..67adb9d
--- /dev/null
+++ b/kernel-headers/camera_pipe_mgr_D2.h
@@ -0,0 +1,114 @@
+/*
+* Copyright (C) 2011-2014 MediaTek Inc.
+* 
+* This program is free software: you can redistribute it and/or modify it under the terms of the 
+* GNU General Public License version 2 as published by the Free Software Foundation.
+* 
+* This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; 
+* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+* See the GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License along with this program.
+* If not, see <http://www.gnu.org/licenses/>.
+*/
+
+//-----------------------------------------------------------------------------
+#ifndef CAMERA_PIPE_MGR_H
+#define CAMERA_PIPE_MGR_H
+//-----------------------------------------------------------------------------
+#define CAM_PIPE_MGR_DEV_NAME       "camera-pipemgr"
+#define CAM_PIPE_MGR_MAGIC_NO       'p'
+//-----------------------------------------------------------------------------
+#define CAM_PIPE_MGR_PIPE_MASK_CAM_IO       ((unsigned long)1 << 0)
+#define CAM_PIPE_MGR_PIPE_MASK_POST_PROC    ((unsigned long)1 << 1)
+#define CAM_PIPE_MGR_PIPE_MASK_XDP_CAM      ((unsigned long)1 << 2)
+//-----------------------------------------------------------------------------
+typedef enum
+{
+    CAM_PIPE_MGR_SCEN_SW_NONE,
+    CAM_PIPE_MGR_SCEN_SW_CAM_IDLE,
+    CAM_PIPE_MGR_SCEN_SW_CAM_PRV,
+    CAM_PIPE_MGR_SCEN_SW_CAM_CAP,
+    CAM_PIPE_MGR_SCEN_SW_VIDEO_PRV,
+    CAM_PIPE_MGR_SCEN_SW_VIDEO_REC,
+    CAM_PIPE_MGR_SCEN_SW_VIDEO_VSS,
+    CAM_PIPE_MGR_SCEN_SW_ZSD,
+    CAM_PIPE_MGR_SCEN_SW_N3D,
+}CAM_PIPE_MGR_SCEN_SW_ENUM;
+//
+typedef enum
+{
+    CAM_PIPE_MGR_SCEN_HW_NONE,
+    CAM_PIPE_MGR_SCEN_HW_IC,
+    CAM_PIPE_MGR_SCEN_HW_VR,
+    CAM_PIPE_MGR_SCEN_HW_ZSD,
+    CAM_PIPE_MGR_SCEN_HW_IP,
+    CAM_PIPE_MGR_SCEN_HW_N3D,
+    CAM_PIPE_MGR_SCEN_HW_VSS
+}CAM_PIPE_MGR_SCEN_HW_ENUM;
+//
+typedef enum
+{
+    CAM_PIPE_MGR_DEV_CAM,
+    CAM_PIPE_MGR_DEV_ATV,
+    CAM_PIPE_MGR_DEV_VT
+}CAM_PIPE_MGR_DEV_ENUM;
+//
+typedef struct
+{
+    unsigned int    PipeMask;
+    unsigned int    Timeout;
+}CAM_PIPE_MGR_LOCK_STRUCT;
+//
+typedef struct
+{
+    unsigned int    PipeMask;
+}CAM_PIPE_MGR_UNLOCK_STRUCT;
+//
+typedef struct
+{
+    CAM_PIPE_MGR_SCEN_SW_ENUM   ScenSw;
+    CAM_PIPE_MGR_SCEN_HW_ENUM   ScenHw;
+    CAM_PIPE_MGR_DEV_ENUM       Dev;
+}CAM_PIPE_MGR_MODE_STRUCT;
+//
+typedef struct
+{
+    unsigned int    PipeMask;
+}CAM_PIPE_MGR_ENABLE_STRUCT;
+//
+typedef struct
+{
+    unsigned int    PipeMask;
+}CAM_PIPE_MGR_DISABLE_STRUCT;
+//-----------------------------------------------------------------------------
+typedef enum
+{
+    CAM_PIPE_MGR_CMD_VECNPLL_CTRL_SET_HIGH,
+    CAM_PIPE_MGR_CMD_VECNPLL_CTRL_SET_LOW
+}CAM_PIPE_MGR_CMD_VECNPLL_CTRL_ENUM;
+//-----------------------------------------------------------------------------
+typedef enum
+{
+    CAM_PIPE_MGR_CMD_LOCK,
+    CAM_PIPE_MGR_CMD_UNLOCK,
+    CAM_PIPE_MGR_CMD_DUMP,
+    CAM_PIPE_MGR_CMD_SET_MODE,
+    CAM_PIPE_MGR_CMD_GET_MODE,
+    CAM_PIPE_MGR_CMD_ENABLE_PIPE,
+    CAM_PIPE_MGR_CMD_DISABLE_PIPE,
+    CAM_PIPE_MGR_CMD_VENC_PLL_CTRL
+}CAM_PIPE_MGR_CMD_ENUM;
+//-----------------------------------------------------------------------------
+#define CAM_PIPE_MGR_LOCK           _IOW(   CAM_PIPE_MGR_MAGIC_NO,  CAM_PIPE_MGR_CMD_LOCK,          CAM_PIPE_MGR_LOCK_STRUCT)
+#define CAM_PIPE_MGR_UNLOCK         _IOW(   CAM_PIPE_MGR_MAGIC_NO,  CAM_PIPE_MGR_CMD_UNLOCK,        CAM_PIPE_MGR_UNLOCK_STRUCT)
+#define CAM_PIPE_MGR_DUMP           _IO(    CAM_PIPE_MGR_MAGIC_NO,  CAM_PIPE_MGR_CMD_DUMP)
+#define CAM_PIPE_MGR_SET_MODE       _IOW(   CAM_PIPE_MGR_MAGIC_NO,  CAM_PIPE_MGR_CMD_SET_MODE,      CAM_PIPE_MGR_MODE_STRUCT)
+#define CAM_PIPE_MGR_GET_MODE       _IOW(   CAM_PIPE_MGR_MAGIC_NO,  CAM_PIPE_MGR_CMD_GET_MODE,      CAM_PIPE_MGR_MODE_STRUCT)
+#define CAM_PIPE_MGR_ENABLE_PIPE    _IOW(   CAM_PIPE_MGR_MAGIC_NO,  CAM_PIPE_MGR_CMD_ENABLE_PIPE,   CAM_PIPE_MGR_ENABLE_STRUCT)
+#define CAM_PIPE_MGR_DISABLE_PIPE   _IOW(   CAM_PIPE_MGR_MAGIC_NO,  CAM_PIPE_MGR_CMD_DISABLE_PIPE,  CAM_PIPE_MGR_DISABLE_STRUCT)
+#define CAM_PIPE_MGR_VENCPLL_CTRL   _IOW(   CAM_PIPE_MGR_MAGIC_NO,  CAM_PIPE_MGR_CMD_VENC_PLL_CTRL,  CAM_PIPE_MGR_CMD_VECNPLL_CTRL_ENUM)
+//-----------------------------------------------------------------------------
+#endif
+//-----------------------------------------------------------------------------
+
diff --git a/kernel-headers/camera_pipe_mgr_imp_D2.h b/kernel-headers/camera_pipe_mgr_imp_D2.h
new file mode 100644
index 0000000..4694b3b
--- /dev/null
+++ b/kernel-headers/camera_pipe_mgr_imp_D2.h
@@ -0,0 +1,113 @@
+/*
+* Copyright (C) 2011-2014 MediaTek Inc.
+* 
+* This program is free software: you can redistribute it and/or modify it under the terms of the 
+* GNU General Public License version 2 as published by the Free Software Foundation.
+* 
+* This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; 
+* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+* See the GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License along with this program.
+* If not, see <http://www.gnu.org/licenses/>.
+*/
+
+//-----------------------------------------------------------------------------
+#ifndef CAMERA_PIPE_MGR_IMP_H
+#define CAMERA_PIPE_MGR_IMP_H
+//-----------------------------------------------------------------------------
+typedef unsigned long long  MUINT64;
+typedef long long           MINT64;
+typedef unsigned long       MUINT32;
+typedef long                MINT32;
+typedef unsigned char       MUINT8;
+typedef char                MINT8;
+typedef bool                MBOOL;
+#define MTRUE               true
+#define MFALSE              false
+//-----------------------------------------------------------------------------
+#define LOG_TAG "CamPipeMgr"
+#define LOG_MSG(fmt, arg...)    pr_debug(LOG_TAG "[%s]"          fmt "\r\n", __FUNCTION__,           ##arg)
+#define LOG_WRN(fmt, arg...)    pr_warn (LOG_TAG "[%s]WRN(%5d):" fmt "\r\n", __FUNCTION__, __LINE__, ##arg)
+#define LOG_ERR(fmt, arg...)    pr_err  (LOG_TAG "[%s]ERR(%5d):" fmt "\r\n", __FUNCTION__, __LINE__, ##arg)
+#define LOG_DMP(fmt, arg...)    pr_err  (LOG_TAG ""              fmt,                                ##arg)
+//-----------------------------------------------------------------------------
+#define CAM_PIPE_MGR_DEV_NUM        (1)
+#define CAM_PIPE_MGR_DEV_MINOR_NUM  (1)
+#define CAM_PIPE_MGR_DEV_NO_MINOR   (0)
+#define CAM_PIPE_MGR_JIFFIES_MAX    (0xFFFFFFFF)
+#define CAM_PIPE_MGR_PROC_NAME      "Default"
+#define CAM_PIPE_MGR_SCEN_HW_AMOUNT (7)
+#define CAM_PIPE_MGR_TIMEOUT_MAX    (10*1000)
+//-----------------------------------------------------------------------------
+#define CAM_PIPE_MGR_PIPE_NAME_LEN          (10)
+#define CAM_PIPE_MGR_PIPE_NAME_CAM_IO       "CamIO"
+#define CAM_PIPE_MGR_PIPE_NAME_POST_PROC    "PostProc"
+#define CAM_PIPE_MGR_PIPE_NAME_XDP_CAM      "CamXDP"
+//-----------------------------------------------------------------------------
+typedef enum
+{
+    CAM_PIPE_MGR_PIPE_CAM_IO,
+    CAM_PIPE_MGR_PIPE_POST_PROC,
+    CAM_PIPE_MGR_PIPE_XDP_CAM,
+    CAM_PIPE_MGR_PIPE_AMOUNT
+}CAM_PIPE_MGR_PIPE_ENUM;
+//
+typedef enum
+{
+    CAM_PIPE_MGR_STATUS_OK,
+    CAM_PIPE_MGR_STATUS_FAIL,
+    CAM_PIPE_MGR_STATUS_TIMEOUT,
+    CAM_PIPE_MGR_STATUS_UNKNOW
+}CAM_PIPE_MGR_STATUS_ENUM;
+//
+#define CAM_PIPE_MGR_LOCK_TABLE_NONE    (   0)
+#define CAM_PIPE_MGR_LOCK_TABLE_IC      (   (1<<CAM_PIPE_MGR_PIPE_CAM_IO)| \
+                                            (1<<CAM_PIPE_MGR_PIPE_POST_PROC))
+#define CAM_PIPE_MGR_LOCK_TABLE_VR      (   (1<<CAM_PIPE_MGR_PIPE_CAM_IO)| \
+                                            (1<<CAM_PIPE_MGR_PIPE_XDP_CAM))
+#define CAM_PIPE_MGR_LOCK_TABLE_ZSD     (   (1<<CAM_PIPE_MGR_PIPE_CAM_IO)| \
+                                            (1<<CAM_PIPE_MGR_PIPE_XDP_CAM))
+#define CAM_PIPE_MGR_LOCK_TABLE_IP      (   (1<<CAM_PIPE_MGR_PIPE_POST_PROC))
+#define CAM_PIPE_MGR_LOCK_TABLE_N3D     (   (1<<CAM_PIPE_MGR_PIPE_CAM_IO)| \
+                                            (1<<CAM_PIPE_MGR_PIPE_POST_PROC))
+#define CAM_PIPE_MGR_LOCK_TABLE_VSS     (   (1<<CAM_PIPE_MGR_PIPE_CAM_IO)| \
+                                            (1<<CAM_PIPE_MGR_PIPE_POST_PROC))
+//-----------------------------------------------------------------------------
+typedef struct
+{
+    pid_t   Pid;
+    pid_t   Tgid;
+    char    ProcName[TASK_COMM_LEN];
+    MUINT32 PipeMask;
+    MUINT32 TimeS;
+    MUINT32 TimeUS;
+}CAM_PIPE_MGR_PROC_STRUCT;
+//
+typedef struct
+{
+    pid_t   Pid;
+    pid_t   Tgid;
+    char    ProcName[TASK_COMM_LEN];
+    MUINT32 TimeS;
+    MUINT32 TimeUS;
+}CAM_PIPE_MGR_PIPE_STRUCT;
+//
+typedef struct
+{
+    MUINT32                     PipeMask;
+    spinlock_t                  SpinLock;
+    dev_t                       DevNo;
+    struct cdev*                pCharDrv;
+    struct class*               pClass;
+    wait_queue_head_t           WaitQueueHead;
+    CAM_PIPE_MGR_MODE_STRUCT    Mode;
+    CAM_PIPE_MGR_PIPE_STRUCT    PipeInfo[CAM_PIPE_MGR_PIPE_AMOUNT];
+    char                        PipeName[CAM_PIPE_MGR_PIPE_AMOUNT][CAM_PIPE_MGR_PIPE_NAME_LEN];
+    MUINT32                     PipeLockTable[CAM_PIPE_MGR_SCEN_HW_AMOUNT];
+    MUINT32                     LogMask;
+}CAM_PIPE_MGR_STRUCT;
+//-----------------------------------------------------------------------------
+#endif
+//-----------------------------------------------------------------------------
+
diff --git a/kernel-headers/camera_sysram.h b/kernel-headers/camera_sysram.h
new file mode 100644
index 0000000..fca705d
--- /dev/null
+++ b/kernel-headers/camera_sysram.h
@@ -0,0 +1,37 @@
+#ifndef CAMERA_SYSRAM_H
+#define CAMERA_SYSRAM_H
+//-----------------------------------------------------------------------------
+#define SYSRAM_DEV_NAME     "camera-sysram"
+#define SYSRAM_MAGIC_NO     'p'
+//-----------------------------------------------------------------------------
+typedef enum
+{
+    SYSRAM_USER_VIDO,
+    SYSRAM_USER_GDMA,
+    SYSRAM_USER_SW_FD,
+    SYSRAM_USER_AMOUNT,
+    SYSRAM_USER_NONE
+}SYSRAM_USER_ENUM;
+//
+typedef struct
+{
+    unsigned long       Alignment;
+    unsigned long       Size;
+    SYSRAM_USER_ENUM    User;
+    unsigned long       Addr; // In/Out : address
+    unsigned long       TimeoutMS; // In : millisecond
+}SYSRAM_ALLOC_STRUCT;
+//
+typedef enum
+{
+    SYSRAM_CMD_ALLOC,
+    SYSRAM_CMD_FREE,
+    SYSRAM_CMD_DUMP
+}SYSRAM_CMD_ENUM;
+//-----------------------------------------------------------------------------
+#define SYSRAM_ALLOC    _IOWR(  SYSRAM_MAGIC_NO,    SYSRAM_CMD_ALLOC,   SYSRAM_ALLOC_STRUCT)
+#define SYSRAM_FREE     _IOWR(  SYSRAM_MAGIC_NO,    SYSRAM_CMD_FREE,    SYSRAM_USER_ENUM)
+#define SYSRAM_DUMP     _IO(    SYSRAM_MAGIC_NO,    SYSRAM_CMD_DUMP)
+//-----------------------------------------------------------------------------
+#endif
+
diff --git a/kernel-headers/camera_sysram_D2.h b/kernel-headers/camera_sysram_D2.h
new file mode 100644
index 0000000..9bec42a
--- /dev/null
+++ b/kernel-headers/camera_sysram_D2.h
@@ -0,0 +1,56 @@
+/*
+* Copyright (C) 2011-2014 MediaTek Inc.
+* 
+* This program is free software: you can redistribute it and/or modify it under the terms of the 
+* GNU General Public License version 2 as published by the Free Software Foundation.
+* 
+* This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; 
+* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+* See the GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License along with this program.
+* If not, see <http://www.gnu.org/licenses/>.
+*/
+
+#ifndef CAMERA_SYSRAM_H
+#define CAMERA_SYSRAM_H
+//-----------------------------------------------------------------------------
+#define SYSRAM_DEV_NAME     "camera-sysram"
+#define SYSRAM_MAGIC_NO     'p'
+//-----------------------------------------------------------------------------
+#ifdef CONFIG_COMPAT
+//64 bit
+#include <linux/fs.h>
+#include <linux/compat.h>
+#endif
+typedef enum
+{
+    SYSRAM_USER_VIDO,
+    SYSRAM_USER_GDMA,
+    SYSRAM_USER_SW_FD,
+    SYSRAM_USER_AMOUNT,
+    SYSRAM_USER_NONE
+}SYSRAM_USER_ENUM;
+//
+typedef struct
+{
+    unsigned int       Alignment;
+    unsigned int       Size;
+    SYSRAM_USER_ENUM    User;
+    unsigned int       Addr; // In/Out : address
+    unsigned int       TimeoutMS; // In : millisecond
+}SYSRAM_ALLOC_STRUCT;
+//
+typedef enum
+{
+    SYSRAM_CMD_ALLOC,
+    SYSRAM_CMD_FREE,
+    SYSRAM_CMD_DUMP
+}SYSRAM_CMD_ENUM;
+//-----------------------------------------------------------------------------
+#define SYSRAM_ALLOC    _IOWR(  SYSRAM_MAGIC_NO,    SYSRAM_CMD_ALLOC,   SYSRAM_ALLOC_STRUCT)
+#define SYSRAM_FREE     _IOWR(  SYSRAM_MAGIC_NO,    SYSRAM_CMD_FREE,    SYSRAM_USER_ENUM)
+#define SYSRAM_DUMP     _IO(    SYSRAM_MAGIC_NO,    SYSRAM_CMD_DUMP)
+//-----------------------------------------------------------------------------
+#endif
+
diff --git a/kernel-headers/camera_sysram_imp_D2.h b/kernel-headers/camera_sysram_imp_D2.h
new file mode 100644
index 0000000..73732f9
--- /dev/null
+++ b/kernel-headers/camera_sysram_imp_D2.h
@@ -0,0 +1,176 @@
+/*
+* Copyright (C) 2011-2014 MediaTek Inc.
+* 
+* This program is free software: you can redistribute it and/or modify it under the terms of the 
+* GNU General Public License version 2 as published by the Free Software Foundation.
+* 
+* This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; 
+* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+* See the GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License along with this program.
+* If not, see <http://www.gnu.org/licenses/>.
+*/
+
+#ifndef CAMERA_SYSRAM_IMP_H
+#define CAMERA_SYSRAM_IMP_H
+//-----------------------------------------------------------------------------
+typedef unsigned long long  MUINT64;
+typedef long long           MINT64;
+typedef unsigned long       MUINT32;
+typedef long                MINT32;
+typedef unsigned char       MUINT8;
+typedef char                MINT8;
+typedef bool                MBOOL;
+#define MTRUE               true
+#define MFALSE              false
+//-----------------------------------------------------------------------------
+#define LOG_TAG "SYSRAM"
+#define LOG_MSG(fmt, arg...)    pr_debug(LOG_TAG "[%s]"          fmt "\r\n", __FUNCTION__,           ##arg)
+#define LOG_WRN(fmt, arg...)    pr_warn (LOG_TAG "[%s]WRN(%5d):" fmt "\r\n", __FUNCTION__, __LINE__, ##arg)
+#define LOG_ERR(fmt, arg...)    pr_err  (LOG_TAG "[%s]ERR(%5d):" fmt "\r\n", __FUNCTION__, __LINE__, ##arg)
+#define LOG_DMP(fmt, arg...)    pr_err  (LOG_TAG ""              fmt,                                ##arg)
+//-----------------------------------------------------------------------------
+#define SYSRAM_DEBUG_DEFAULT    (0xFFFFFFFF)
+#define SYSRAM_JIFFIES_MAX      (0xFFFFFFFF)
+#define SYSRAM_PROC_NAME        "Default"
+//-----------------------------------------------------------------------------
+#define SYSRAM_BASE_PHY_ADDR    ((SYSRAM_BASE&0x0FFFFFFF)|0x10000000)
+#define SYSRAM_BASE_SIZE        (81920) //32K+48K
+#define SYSRAM_BASE_ADDR_BANK_0 (SYSRAM_BASE_PHY_ADDR)
+#define SYSRAM_BASE_SIZE_BANK_0 (SYSRAM_BASE_SIZE)
+//
+#define SYSRAM_USER_SIZE_VIDO   (SYSRAM_BASE_SIZE)//(78408)//(74496)    // Always allocate max SYSRAM size because there is no other user. //78408: Max size used when format is RGB565.
+#define SYSRAM_USER_SIZE_GDMA   (46080)
+#define SYSRAM_USER_SIZE_SW_FD  (0) //TBD
+//
+#define SYSRAM_MEM_NODE_AMOUNT_PER_POOL (SYSRAM_USER_AMOUNT*2 + 2)
+//-----------------------------------------------------------------------------
+typedef struct
+{
+    pid_t   pid;                    // thread id
+    pid_t   tgid;                   // process id
+    char    ProcName[TASK_COMM_LEN];    // executable name
+    MUINT64 Time64;
+    MUINT32 TimeS;
+    MUINT32 TimeUS;
+}SYSRAM_USER_STRUCT;
+//
+typedef struct
+{
+    spinlock_t              SpinLock;
+    MUINT32                 TotalUserCount;
+    MUINT32                 AllocatedTbl;
+    MUINT32                 AllocatedSize[SYSRAM_USER_AMOUNT];
+    SYSRAM_USER_STRUCT      UserInfo[SYSRAM_USER_AMOUNT];
+    wait_queue_head_t       WaitQueueHead;
+    MBOOL                   EnableClk;
+    MUINT32                 DebugFlag;
+    dev_t                   DevNo;
+    struct cdev*            pCharDrv;
+    struct class*           pClass;
+}SYSRAM_STRUCT;
+//
+typedef struct
+{
+    pid_t   Pid;
+    pid_t   Tgid;
+    char    ProcName[TASK_COMM_LEN];
+    MUINT32 Table;
+    MUINT64 Time64;
+    MUINT32 TimeS;
+    MUINT32 TimeUS;
+}SYSRAM_PROC_STRUCT;
+
+//
+typedef enum 
+{
+    SYSRAM_MEM_BANK_0,
+    SYSRAM_MEM_BANK_AMOUNT,
+    SYSRAM_MEM_BANK_BAD
+}SYSRAM_MEM_BANK_ENUM;
+//
+typedef struct SYSRAM_MEM_NODE
+{
+    SYSRAM_USER_ENUM        User;
+    MUINT32                 Offset;
+    MUINT32                 Length;
+    MUINT32                 Index;
+    struct SYSRAM_MEM_NODE* pNext;
+    struct SYSRAM_MEM_NODE* pPrev;
+}SYSRAM_MEM_NODE_STRUCT;
+//
+typedef struct
+{
+    SYSRAM_MEM_NODE_STRUCT* const   pMemNode;
+    MUINT32 const                   UserAmount;
+    MUINT32 const                   Addr;
+    MUINT32 const                   Size;
+    MUINT32                         IndexTbl;
+    MUINT32                         UserCount;
+}SYSRAM_MEM_POOL_STRUCT;
+//------------------------------------------------------------------------------
+static SYSRAM_MEM_NODE_STRUCT SysramMemNodeBank0Tbl[SYSRAM_MEM_NODE_AMOUNT_PER_POOL];
+static SYSRAM_MEM_POOL_STRUCT SysramMemPoolInfo[SYSRAM_MEM_BANK_AMOUNT] = 
+{
+    [SYSRAM_MEM_BANK_0] = 
+    {
+        .pMemNode   = &SysramMemNodeBank0Tbl[0], 
+        .UserAmount = SYSRAM_MEM_NODE_AMOUNT_PER_POOL, 
+        .Addr       = SYSRAM_BASE_ADDR_BANK_0, 
+        .Size       = SYSRAM_BASE_SIZE_BANK_0, 
+        .IndexTbl   = (~0x1), 
+        .UserCount  = 0, 
+    }
+};
+//
+static inline SYSRAM_MEM_POOL_STRUCT* SYSRAM_GetMemPoolInfo(SYSRAM_MEM_BANK_ENUM const MemBankNo)
+{
+    if(SYSRAM_MEM_BANK_AMOUNT > MemBankNo)
+    {
+        return &SysramMemPoolInfo[MemBankNo];
+    }
+    return  NULL;
+}
+//
+enum
+{
+    SysramMemBank0UserMask =
+         (1<<SYSRAM_USER_VIDO)
+        |(1<<SYSRAM_USER_GDMA)
+        |(1<<SYSRAM_USER_SW_FD)
+        , 
+    SysramLogUserMask =
+         (1<<SYSRAM_USER_VIDO)
+        |(1<<SYSRAM_USER_GDMA)
+        |(1<<SYSRAM_USER_SW_FD)
+};
+//
+static SYSRAM_MEM_BANK_ENUM SYSRAM_GetMemBankNo(SYSRAM_USER_ENUM const User)
+{
+    MUINT32 const UserMask = (1<<User);
+    //
+    if(UserMask & SysramMemBank0UserMask)
+    {
+        return  SYSRAM_MEM_BANK_0;
+    }
+    //
+    return  SYSRAM_MEM_BANK_BAD;
+}
+//
+static char const*const SysramUserName[SYSRAM_USER_AMOUNT] = 
+{
+    [SYSRAM_USER_VIDO]  = "VIDO", 
+    [SYSRAM_USER_GDMA]  = "GDMA",
+    [SYSRAM_USER_SW_FD] = "SW FD"
+};
+//
+static MUINT32 const SysramUserSize[SYSRAM_USER_AMOUNT] = 
+{
+    [SYSRAM_USER_VIDO]  = (3 + SYSRAM_USER_SIZE_VIDO) / 4 * 4,
+    [SYSRAM_USER_GDMA]  = (3 + SYSRAM_USER_SIZE_GDMA) / 4 * 4,
+    [SYSRAM_USER_SW_FD] = (3 + SYSRAM_USER_SIZE_SW_FD) / 4 * 4
+};
+//------------------------------------------------------------------------------
+#endif
+
diff --git a/kernel-headers/cmdq_engine.h b/kernel-headers/cmdq_engine.h
new file mode 100644
index 0000000..29b2ad1
--- /dev/null
+++ b/kernel-headers/cmdq_engine.h
@@ -0,0 +1,73 @@
+#ifndef __CMDQ_ENGINE_H__
+#define __CMDQ_ENGINE_H__
+
+typedef enum CMDQ_ENG_ENUM {
+	/* ISP */
+	CMDQ_ENG_ISP_IMGI = 0,
+	CMDQ_ENG_ISP_IMGO,	/* 1 */
+	CMDQ_ENG_ISP_IMG2O,	/* 2 */
+
+	/* MDP */
+	CMDQ_ENG_MDP_CAMIN,	/* 3 */
+	CMDQ_ENG_MDP_RDMA0,	/* 4 */
+	CMDQ_ENG_MDP_RSZ0,	/* 5 */
+	CMDQ_ENG_MDP_RSZ1,	/* 6 */
+	CMDQ_ENG_MDP_TDSHP0,	/* 7 */
+	CMDQ_ENG_MDP_WROT0,	/* 8 */
+	CMDQ_ENG_MDP_WDMA,	/* 9 */
+
+	/* JPEG & VENC */
+	CMDQ_ENG_JPEG_ENC,	/* 10 */
+	CMDQ_ENG_VIDEO_ENC,	/* 11 */
+	CMDQ_ENG_JPEG_DEC,	/* 12 */
+	CMDQ_ENG_JPEG_REMDC,	/* 13 */
+
+	/* DISP */
+	CMDQ_ENG_DISP_UFOE,	/* 14 */
+	CMDQ_ENG_DISP_AAL,	/* 15 */
+	CMDQ_ENG_DISP_COLOR0,	/* 16 */
+	CMDQ_ENG_DISP_RDMA0,	/* 17 */
+	CMDQ_ENG_DISP_RDMA1,	/* 18 */
+	CMDQ_ENG_DISP_WDMA0,	/* 19 */
+	CMDQ_ENG_DISP_WDMA1,	/* 20 */
+	CMDQ_ENG_DISP_OVL0,	/* 21 */
+	CMDQ_ENG_DISP_OVL1,	/* 22 */
+	CMDQ_ENG_DISP_GAMMA,	/* 23 */
+	CMDQ_ENG_DISP_DSI0_VDO,	/* 24 */
+	CMDQ_ENG_DISP_DSI0_CMD,	/* 25 */
+	CMDQ_ENG_DISP_DSI0,	/* 26 */
+	CMDQ_ENG_DISP_DPI,	/* 27 */
+
+	/* temp: CMDQ internal usage */
+	CMDQ_ENG_CMDQ,
+	CMDQ_ENG_DISP_MUTEX,
+	CMDQ_ENG_MMSYS_CONFIG,
+
+	/* Dummy Engine */
+	CMDQ_ENG_MDP_RDMA1,
+	CMDQ_ENG_MDP_RSZ2,
+	CMDQ_ENG_MDP_TDSHP1,
+	CMDQ_ENG_MDP_COLOR0,
+	CMDQ_ENG_MDP_MOUT0,
+	CMDQ_ENG_MDP_MOUT1,
+	CMDQ_ENG_MDP_WROT1,
+
+	CMDQ_ENG_DISP_COLOR1,
+	CMDQ_ENG_DISP_RDMA2,
+	CMDQ_ENG_DISP_OVL2,
+	CMDQ_ENG_DISP_2L_OVL0,
+	CMDQ_ENG_DISP_2L_OVL1,
+	CMDQ_ENG_DISP_2L_OVL2,
+	CMDQ_ENG_DISP_MERGE,
+	CMDQ_ENG_DISP_SPLIT0,
+	CMDQ_ENG_DISP_SPLIT1,
+	CMDQ_ENG_DISP_DSI1_VDO,
+	CMDQ_ENG_DISP_DSI1_CMD,
+	CMDQ_ENG_DISP_DSI1,
+
+	CMDQ_ENG_DPE,
+
+	CMDQ_MAX_ENGINE_COUNT	/* ALWAYS keep at the end */
+} CMDQ_ENG_ENUM;
+
+#endif				/* __CMDQ_ENGINE_H__ */
diff --git a/kernel-headers/cmdq_event.h b/kernel-headers/cmdq_event.h
new file mode 100644
index 0000000..442e096
--- /dev/null
+++ b/kernel-headers/cmdq_event.h
@@ -0,0 +1,145 @@
+/* MDP start frame */
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_MDP_RDMA0_SOF, 0)
+    DECLARE_CMDQ_EVENT(CMDQ_EVENT_MDP_RSZ0_SOF, 1)
+    DECLARE_CMDQ_EVENT(CMDQ_EVENT_MDP_RSZ1_SOF, 2)
+    DECLARE_CMDQ_EVENT(CMDQ_EVENT_DSI_TE, 3)
+    DECLARE_CMDQ_EVENT(CMDQ_EVENT_MDP_WDMA_SOF, 4)
+    DECLARE_CMDQ_EVENT(CMDQ_EVENT_MDP_WROT_SOF, 5)
+
+/* Display start frame */
+    DECLARE_CMDQ_EVENT(CMDQ_EVENT_DISP_OVL0_SOF, 6)
+    DECLARE_CMDQ_EVENT(CMDQ_EVENT_DISP_RDMA0_SOF, 7)
+    DECLARE_CMDQ_EVENT(CMDQ_EVENT_DISP_RDMA1_SOF, 8)
+    DECLARE_CMDQ_EVENT(CMDQ_EVENT_DISP_WDMA0_SOF, 9)
+    DECLARE_CMDQ_EVENT(CMDQ_EVENT_DISP_CCORR_SOF, 10)
+    DECLARE_CMDQ_EVENT(CMDQ_EVENT_DISP_COLOR_SOF, 11)
+    DECLARE_CMDQ_EVENT(CMDQ_EVENT_DISP_AAL_SOF, 12)
+    DECLARE_CMDQ_EVENT(CMDQ_EVENT_DISP_GAMMA_SOF, 13)
+    DECLARE_CMDQ_EVENT(CMDQ_EVENT_DISP_DITHER_SOF, 14)
+
+    DECLARE_CMDQ_EVENT(CMDQ_EVENT_DISP_PWM0_SOF, 16)
+    
+    DECLARE_CMDQ_EVENT(CMDQ_EVENT_DISP_OVL1_SOF, (-2))
+    DECLARE_CMDQ_EVENT(CMDQ_EVENT_DISP_UFOE_SOF, (-3))
+    DECLARE_CMDQ_EVENT(CMDQ_EVENT_DISP_WDMA1_SOF, (-4))
+    DECLARE_CMDQ_EVENT(CMDQ_EVENT_UFOD_RAMA0_L0_SOF, (-5))
+    DECLARE_CMDQ_EVENT(CMDQ_EVENT_UFOD_RAMA0_L1_SOF, (-6))
+    DECLARE_CMDQ_EVENT(CMDQ_EVENT_UFOD_RAMA0_L2_SOF, (-7))
+    DECLARE_CMDQ_EVENT(CMDQ_EVENT_UFOD_RAMA0_L3_SOF, (-8))
+    DECLARE_CMDQ_EVENT(CMDQ_EVENT_UFOD_RAMA1_L0_SOF, (-9))
+    DECLARE_CMDQ_EVENT(CMDQ_EVENT_UFOD_RAMA1_L1_SOF, (-10))
+    DECLARE_CMDQ_EVENT(CMDQ_EVENT_UFOD_RAMA1_L2_SOF, (-11))
+    DECLARE_CMDQ_EVENT(CMDQ_EVENT_UFOD_RAMA1_L3_SOF, (-12))
+
+/* MDP frame done */
+    DECLARE_CMDQ_EVENT(CMDQ_EVENT_MDP_RDMA0_EOF, 17)
+    DECLARE_CMDQ_EVENT(CMDQ_EVENT_MDP_RSZ0_EOF, 18)
+    DECLARE_CMDQ_EVENT(CMDQ_EVENT_MDP_RSZ1_EOF, 19)
+    DECLARE_CMDQ_EVENT(CMDQ_EVENT_MDP_TDSHP_EOF, 20)
+    DECLARE_CMDQ_EVENT(CMDQ_EVENT_MDP_WDMA_EOF, 21)
+    DECLARE_CMDQ_EVENT(CMDQ_EVENT_MDP_WROT_WRITE_EOF, 22)
+    DECLARE_CMDQ_EVENT(CMDQ_EVENT_MDP_WROT_READ_EOF, 23)
+
+/* Display frame done */
+    DECLARE_CMDQ_EVENT(CMDQ_EVENT_DISP_OVL0_EOF, 24)
+    DECLARE_CMDQ_EVENT(CMDQ_EVENT_DISP_RDMA0_EOF, 25)
+    DECLARE_CMDQ_EVENT(CMDQ_EVENT_DISP_RDMA1_EOF, 26)
+    DECLARE_CMDQ_EVENT(CMDQ_EVENT_DISP_WDMA0_EOF, 27)
+    DECLARE_CMDQ_EVENT(CMDQ_EVENT_DISP_CCORR_EOF, 28)
+    DECLARE_CMDQ_EVENT(CMDQ_EVENT_DISP_COLOR_EOF, 29)
+    DECLARE_CMDQ_EVENT(CMDQ_EVENT_DISP_AAL_EOF, 30)
+    DECLARE_CMDQ_EVENT(CMDQ_EVENT_DISP_GAMMA_EOF, 31)
+    DECLARE_CMDQ_EVENT(CMDQ_EVENT_DISP_DITHER_EOF, 32)
+
+    DECLARE_CMDQ_EVENT(CMDQ_EVENT_DISP_DPI0_EOF, 34)
+    
+    DECLARE_CMDQ_EVENT(CMDQ_EVENT_DISP_OVL1_EOF, (-13))
+    DECLARE_CMDQ_EVENT(CMDQ_EVENT_DISP_UFOE_EOF, (-14))
+    DECLARE_CMDQ_EVENT(CMDQ_EVENT_DISP_WDMA1_EOF, (-15))
+    DECLARE_CMDQ_EVENT(CMDQ_EVENT_UFOD_RAMA0_L0_EOF, (-16))
+    DECLARE_CMDQ_EVENT(CMDQ_EVENT_UFOD_RAMA0_L1_EOF, (-17))
+    DECLARE_CMDQ_EVENT(CMDQ_EVENT_UFOD_RAMA0_L2_EOF, (-18))
+    DECLARE_CMDQ_EVENT(CMDQ_EVENT_UFOD_RAMA0_L3_EOF, (-19))
+    DECLARE_CMDQ_EVENT(CMDQ_EVENT_UFOD_RAMA1_L0_EOF, (-20))
+    DECLARE_CMDQ_EVENT(CMDQ_EVENT_UFOD_RAMA1_L1_EOF, (-21))
+    DECLARE_CMDQ_EVENT(CMDQ_EVENT_UFOD_RAMA1_L2_EOF, (-22))
+    DECLARE_CMDQ_EVENT(CMDQ_EVENT_UFOD_RAMA1_L3_EOF, (-23))
+
+/* Mutex frame done */
+    DECLARE_CMDQ_EVENT(CMDQ_EVENT_MUTEX0_STREAM_EOF, 35)/* DISPSYS */
+    DECLARE_CMDQ_EVENT(CMDQ_EVENT_MUTEX1_STREAM_EOF, 36)/* DISPSYS */
+    DECLARE_CMDQ_EVENT(CMDQ_EVENT_MUTEX2_STREAM_EOF, 37)/* DISPSYS */
+    DECLARE_CMDQ_EVENT(CMDQ_EVENT_MUTEX3_STREAM_EOF, 38)/* DISPSYS */
+    DECLARE_CMDQ_EVENT(CMDQ_EVENT_MUTEX4_STREAM_EOF, 39)/* DISPSYS, please refer to disp_hal.h */
+    DECLARE_CMDQ_EVENT(CMDQ_EVENT_MUTEX5_STREAM_EOF, 40)/* DpFramework */
+    DECLARE_CMDQ_EVENT(CMDQ_EVENT_MUTEX6_STREAM_EOF, 41)/* DpFramework */
+    DECLARE_CMDQ_EVENT(CMDQ_EVENT_MUTEX7_STREAM_EOF, 42)/* DpFramework */
+    DECLARE_CMDQ_EVENT(CMDQ_EVENT_MUTEX8_STREAM_EOF, 43)/* DpFramework */
+    DECLARE_CMDQ_EVENT(CMDQ_EVENT_MUTEX9_STREAM_EOF, 44)/* DpFramework via CMDQ_IOCTL_LOCK_MUTEX */
+
+/* Display underrun */
+    DECLARE_CMDQ_EVENT(CMDQ_EVENT_DISP_RDMA0_UNDERRUN, 45)
+    DECLARE_CMDQ_EVENT(CMDQ_EVENT_DISP_RDMA1_UNDERRUN, 46)
+
+/* Display TE */
+    DECLARE_CMDQ_EVENT(CMDQ_EVENT_MDP_TDSHP_SOF, 47)
+
+/* ISP frame done */
+    DECLARE_CMDQ_EVENT(CMDQ_EVENT_ISP_PASS2_2_EOF, 65)
+    DECLARE_CMDQ_EVENT(CMDQ_EVENT_ISP_PASS2_1_EOF, 66)
+    DECLARE_CMDQ_EVENT(CMDQ_EVENT_ISP_PASS2_0_EOF, 67)
+    DECLARE_CMDQ_EVENT(CMDQ_EVENT_ISP_PASS1_1_EOF, 68)
+    DECLARE_CMDQ_EVENT(CMDQ_EVENT_ISP_PASS1_0_EOF, 69)
+
+/* ISP engine events */
+    DECLARE_CMDQ_EVENT(CMDQ_EVENT_ISP_CAMSV_2_PASS1_DONE, 70)
+    DECLARE_CMDQ_EVENT(CMDQ_EVENT_ISP_CAMSV_1_PASS1_DONE, 71)
+    DECLARE_CMDQ_EVENT(CMDQ_EVENT_ISP_SENINF_CAM1_2_3_FULL, 72)
+    DECLARE_CMDQ_EVENT(CMDQ_EVENT_ISP_SENINF_CAM0_FULL, 73)
+
+/* VENC frame done */
+    DECLARE_CMDQ_EVENT(CMDQ_EVENT_VENC_EOF, 129)
+
+/* JPEG frame done */
+    DECLARE_CMDQ_EVENT(CMDQ_EVENT_JPEG_ENC_EOF, 130)
+    DECLARE_CMDQ_EVENT(CMDQ_EVENT_JPEG_DEC_EOF, 131)
+
+/* VENC engine events */
+    DECLARE_CMDQ_EVENT(CMDQ_EVENT_VENC_MB_DONE, 132)
+    DECLARE_CMDQ_EVENT(CMDQ_EVENT_VENC_128BYTE_CNT_DONE, 133)
+
+/* Keep this at the end of HW events */
+    DECLARE_CMDQ_EVENT(CMDQ_MAX_HW_EVENT_COUNT, 270)
+
+/* SW Sync Tokens (Pre-defined) */
+    /* Config thread notify trigger thread */
+    DECLARE_CMDQ_EVENT(CMDQ_SYNC_TOKEN_CONFIG_DIRTY, 271)
+    /* Trigger thread notify config thread */
+    DECLARE_CMDQ_EVENT(CMDQ_SYNC_TOKEN_STREAM_EOF, 272)
+    /* Block Trigger thread until the ESD check finishes. */
+    DECLARE_CMDQ_EVENT(CMDQ_SYNC_TOKEN_ESD_EOF, 273)
+    /* check CABC setup finish */
+    DECLARE_CMDQ_EVENT(CMDQ_SYNC_TOKEN_CABC_EOF, 274)
+    /* Pass-2 notifies VENC frame is ready to be encoded */
+    DECLARE_CMDQ_EVENT(CMDQ_SYNC_TOKEN_VENC_INPUT_READY, 280)
+    /* VENC notifies Pass-2 encode done so next frame may start */
+    DECLARE_CMDQ_EVENT(CMDQ_SYNC_TOKEN_VENC_EOF, 281)
+
+/* SW Sync Tokens (User-defined) */
+    DECLARE_CMDQ_EVENT(CMDQ_SYNC_TOKEN_USER_0, 300)
+    DECLARE_CMDQ_EVENT(CMDQ_SYNC_TOKEN_USER_1, 301)
+
+/* GPR access tokens (for HW register backup) */
+/* There are 15 32-bit GPR, 3 GPR form a set (64-bit for address, 32-bit for value) */
+    DECLARE_CMDQ_EVENT(CMDQ_SYNC_TOKEN_GPR_SET_0, 400)
+    DECLARE_CMDQ_EVENT(CMDQ_SYNC_TOKEN_GPR_SET_1, 401)
+    DECLARE_CMDQ_EVENT(CMDQ_SYNC_TOKEN_GPR_SET_2, 402)
+    DECLARE_CMDQ_EVENT(CMDQ_SYNC_TOKEN_GPR_SET_3, 403)
+    DECLARE_CMDQ_EVENT(CMDQ_SYNC_TOKEN_GPR_SET_4, 404)
+
+/* Resource lock event to control resource in GCE thread */
+	DECLARE_CMDQ_EVENT(CMDQ_SYNC_RESOURCE_WROT0, 460)
+	
+    DECLARE_CMDQ_EVENT(CMDQ_SYNC_TOKEN_MAX, (0x1FF))	/* event id is 9 bit */
+    DECLARE_CMDQ_EVENT(CMDQ_SYNC_TOKEN_INVALID, (-1))
+
diff --git a/kernel-headers/cmdq_event_D1.h b/kernel-headers/cmdq_event_D1.h
new file mode 100644
index 0000000..3906077
--- /dev/null
+++ b/kernel-headers/cmdq_event_D1.h
@@ -0,0 +1,181 @@
+/* MDP start frame */
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_MDP_RDMA0_SOF, 0)
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_MDP_RSZ0_SOF, 1)
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_MDP_RSZ1_SOF, 2)
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_DSI_TE, 3)
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_MDP_WDMA_SOF, 4)
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_MDP_WROT_SOF, 5)
+
+/* Display start frame */
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_DISP_OVL0_SOF, 6)
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_DISP_RDMA0_SOF, 7)
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_DISP_RDMA1_SOF, 8)
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_DISP_WDMA0_SOF, 9)
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_DISP_CCORR_SOF, 10)
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_DISP_COLOR_SOF, 11)
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_DISP_AAL_SOF, 12)
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_DISP_GAMMA_SOF, 13)
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_DISP_DITHER_SOF, 14)
+
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_DISP_PWM0_SOF, 16)
+
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_DISP_OVL1_SOF, (-2))
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_DISP_UFOE_SOF, (-3))
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_DISP_WDMA1_SOF, (-4))
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_UFOD_RAMA0_L0_SOF, (-5))
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_UFOD_RAMA0_L1_SOF, (-6))
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_UFOD_RAMA0_L2_SOF, (-7))
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_UFOD_RAMA0_L3_SOF, (-8))
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_UFOD_RAMA1_L0_SOF, (-9))
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_UFOD_RAMA1_L1_SOF, (-10))
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_UFOD_RAMA1_L2_SOF, (-11))
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_UFOD_RAMA1_L3_SOF, (-12))
+
+
+/* MDP frame done */
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_MDP_RDMA0_EOF, 17)
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_MDP_RSZ0_EOF, 18)
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_MDP_RSZ1_EOF, 19)
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_MDP_TDSHP_EOF, 20)
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_MDP_WDMA_EOF, 21)
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_MDP_WROT_WRITE_EOF, 22)
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_MDP_WROT_READ_EOF, 23)
+
+/* Display frame done */
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_DISP_OVL0_EOF, 24)
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_DISP_RDMA0_EOF, 25)
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_DISP_RDMA1_EOF, 26)
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_DISP_WDMA0_EOF, 27)
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_DISP_CCORR_EOF, 28)
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_DISP_COLOR_EOF, 29)
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_DISP_AAL_EOF, 30)
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_DISP_GAMMA_EOF, 31)
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_DISP_DITHER_EOF, 32)
+
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_DISP_DPI0_EOF, 34)
+
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_DISP_OVL1_EOF, (-13))
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_DISP_UFOE_EOF, (-14))
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_DISP_WDMA1_EOF, (-15))
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_UFOD_RAMA0_L0_EOF, (-16))
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_UFOD_RAMA0_L1_EOF, (-17))
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_UFOD_RAMA0_L2_EOF, (-18))
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_UFOD_RAMA0_L3_EOF, (-19))
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_UFOD_RAMA1_L0_EOF, (-20))
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_UFOD_RAMA1_L1_EOF, (-21))
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_UFOD_RAMA1_L2_EOF, (-22))
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_UFOD_RAMA1_L3_EOF, (-23))
+
+/* Mutex frame done */
+/* DISPSYS */
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_MUTEX0_STREAM_EOF, 35)
+/* DISPSYS */
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_MUTEX1_STREAM_EOF, 36)
+/* DISPSYS */
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_MUTEX2_STREAM_EOF, 37)
+/* DISPSYS */
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_MUTEX3_STREAM_EOF, 38)
+/* DISPSYS, please refer to disp_hal.h */
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_MUTEX4_STREAM_EOF, 39)
+/* DpFramework */
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_MUTEX5_STREAM_EOF, 40)
+/* DpFramework */
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_MUTEX6_STREAM_EOF, 41)
+/* DpFramework */
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_MUTEX7_STREAM_EOF, 42)
+/* DpFramework */
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_MUTEX8_STREAM_EOF, 43)
+/* DpFramework via CMDQ_IOCTL_LOCK_MUTEX */
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_MUTEX9_STREAM_EOF, 44)
+
+/* Display underrun */
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_DISP_RDMA0_UNDERRUN, 45)
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_DISP_RDMA1_UNDERRUN, 46)
+
+/* Display TE */
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_MDP_TDSHP_SOF, 47)
+
+/* ISP frame done */
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_ISP_PASS2_2_EOF, 65)
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_ISP_PASS2_1_EOF, 66)
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_ISP_PASS2_0_EOF, 67)
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_ISP_PASS1_1_EOF, 68)
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_ISP_PASS1_0_EOF, 69)
+
+/* ISP engine events */
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_ISP_CAMSV_2_PASS1_DONE, 70)
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_ISP_CAMSV_1_PASS1_DONE, 71)
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_ISP_SENINF_CAM1_2_3_FULL, 72)
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_ISP_SENINF_CAM0_FULL, 73)
+
+/* VENC frame done */
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_VENC_EOF, 129)
+
+/* JPEG frame done */
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_JPEG_ENC_EOF, 130)
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_JPEG_DEC_EOF, 131)
+
+/* VENC engine events */
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_VENC_MB_DONE, 132)
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_VENC_128BYTE_CNT_DONE, 133)
+
+/* Keep this at the end of HW events */
+DECLARE_CMDQ_EVENT(CMDQ_MAX_HW_EVENT_COUNT, 400)
+
+/* SW Sync Tokens (Pre-defined) */
+/* Config thread notify trigger thread */
+DECLARE_CMDQ_EVENT(CMDQ_SYNC_TOKEN_CONFIG_DIRTY, 401)
+/* Trigger thread notify config thread */
+DECLARE_CMDQ_EVENT(CMDQ_SYNC_TOKEN_STREAM_EOF, 402)
+/* Block Trigger thread until the ESD check finishes. */
+DECLARE_CMDQ_EVENT(CMDQ_SYNC_TOKEN_ESD_EOF, 403)
+/* check CABC setup finish */
+DECLARE_CMDQ_EVENT(CMDQ_SYNC_TOKEN_CABC_EOF, 404)
+/* Block Trigger thread until the path freeze finishes */
+DECLARE_CMDQ_EVENT(CMDQ_SYNC_TOKEN_FREEZE_EOF, 405)
+/* Pass-2 notifies VENC frame is ready to be encoded */
+DECLARE_CMDQ_EVENT(CMDQ_SYNC_TOKEN_VENC_INPUT_READY, 406)
+/* VENC notifies Pass-2 encode done so next frame may start */
+DECLARE_CMDQ_EVENT(CMDQ_SYNC_TOKEN_VENC_EOF, 407)
+
+/* Notify normal CMDQ there are some secure task done */
+DECLARE_CMDQ_EVENT(CMDQ_SYNC_SECURE_THR_EOF, 408)
+
+/* SW Sync Tokens (User-defined) */
+DECLARE_CMDQ_EVENT(CMDQ_SYNC_TOKEN_USER_0, 410)
+DECLARE_CMDQ_EVENT(CMDQ_SYNC_TOKEN_USER_1, 411)
+DECLARE_CMDQ_EVENT(CMDQ_SYNC_TOKEN_POLL_MONITOR, 412)
+
+/* Event for CMDQ to block executing command when append command
+* Plz sync CMDQ_SYNC_TOKEN_APPEND_THR(id) in cmdq_core source file. */
+DECLARE_CMDQ_EVENT(CMDQ_SYNC_TOKEN_APPEND_THR0, 422)
+DECLARE_CMDQ_EVENT(CMDQ_SYNC_TOKEN_APPEND_THR1, 423)
+DECLARE_CMDQ_EVENT(CMDQ_SYNC_TOKEN_APPEND_THR2, 424)
+DECLARE_CMDQ_EVENT(CMDQ_SYNC_TOKEN_APPEND_THR3, 425)
+DECLARE_CMDQ_EVENT(CMDQ_SYNC_TOKEN_APPEND_THR4, 426)
+DECLARE_CMDQ_EVENT(CMDQ_SYNC_TOKEN_APPEND_THR5, 427)
+DECLARE_CMDQ_EVENT(CMDQ_SYNC_TOKEN_APPEND_THR6, 428)
+DECLARE_CMDQ_EVENT(CMDQ_SYNC_TOKEN_APPEND_THR7, 429)
+DECLARE_CMDQ_EVENT(CMDQ_SYNC_TOKEN_APPEND_THR8, 430)
+DECLARE_CMDQ_EVENT(CMDQ_SYNC_TOKEN_APPEND_THR9, 431)
+DECLARE_CMDQ_EVENT(CMDQ_SYNC_TOKEN_APPEND_THR10, 432)
+DECLARE_CMDQ_EVENT(CMDQ_SYNC_TOKEN_APPEND_THR11, 433)
+DECLARE_CMDQ_EVENT(CMDQ_SYNC_TOKEN_APPEND_THR12, 434)
+DECLARE_CMDQ_EVENT(CMDQ_SYNC_TOKEN_APPEND_THR13, 435)
+DECLARE_CMDQ_EVENT(CMDQ_SYNC_TOKEN_APPEND_THR14, 436)
+DECLARE_CMDQ_EVENT(CMDQ_SYNC_TOKEN_APPEND_THR15, 437)
+
+/* GPR access tokens (for HW register backup) */
+/* There are 15 32-bit GPR, 3 GPR form a set (64-bit for address, 32-bit for value) */
+DECLARE_CMDQ_EVENT(CMDQ_SYNC_TOKEN_GPR_SET_0, 450)
+DECLARE_CMDQ_EVENT(CMDQ_SYNC_TOKEN_GPR_SET_1, 451)
+DECLARE_CMDQ_EVENT(CMDQ_SYNC_TOKEN_GPR_SET_2, 452)
+DECLARE_CMDQ_EVENT(CMDQ_SYNC_TOKEN_GPR_SET_3, 453)
+DECLARE_CMDQ_EVENT(CMDQ_SYNC_TOKEN_GPR_SET_4, 454)
+
+/* Resource lock event to control resource in GCE thread */
+DECLARE_CMDQ_EVENT(CMDQ_SYNC_RESOURCE_WROT0, 460)
+
+/* event id is 9 bit */
+DECLARE_CMDQ_EVENT(CMDQ_SYNC_TOKEN_MAX, (0x1FF))
+DECLARE_CMDQ_EVENT(CMDQ_SYNC_TOKEN_INVALID, (-1))
diff --git a/kernel-headers/cmdq_event_D2.h b/kernel-headers/cmdq_event_D2.h
new file mode 100644
index 0000000..18d2d13
--- /dev/null
+++ b/kernel-headers/cmdq_event_D2.h
@@ -0,0 +1,182 @@
+/* MDP start frame */
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_MDP_RDMA0_SOF, 0)
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_MDP_RSZ0_SOF, 1)
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_MDP_RSZ1_SOF, 2)
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_MDP_TDSHP_SOF, 3)
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_MDP_WDMA_SOF, 4)
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_MDP_WROT_SOF, 5)
+
+/* Display start frame */
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_DISP_OVL0_SOF, 6)
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_DISP_RDMA0_SOF, 8)
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_DISP_RDMA1_SOF, 9)
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_DISP_WDMA0_SOF, 10)
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_DISP_CCORR_SOF, 11)
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_DISP_COLOR_SOF, 12)
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_DISP_AAL_SOF, 13)
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_DISP_GAMMA_SOF, 14)
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_DISP_DITHER_SOF, 15)
+
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_DISP_PWM0_SOF, 17)
+
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_DISP_OVL1_SOF, (-2))
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_DISP_UFOE_SOF, (-3))
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_DISP_WDMA1_SOF, (-4))
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_UFOD_RAMA0_L0_SOF, (-5))
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_UFOD_RAMA0_L1_SOF, (-6))
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_UFOD_RAMA0_L2_SOF, (-7))
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_UFOD_RAMA0_L3_SOF, (-8))
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_UFOD_RAMA1_L0_SOF, (-9))
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_UFOD_RAMA1_L1_SOF, (-10))
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_UFOD_RAMA1_L2_SOF, (-11))
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_UFOD_RAMA1_L3_SOF, (-12))
+
+
+/* MDP frame done */
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_MDP_RDMA0_EOF, 18)
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_MDP_RSZ0_EOF, 19)
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_MDP_RSZ1_EOF, 20)
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_MDP_TDSHP_EOF, 21)
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_MDP_WDMA_EOF, 22)
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_MDP_WROT_WRITE_EOF, 23)
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_MDP_WROT_READ_EOF, 24)
+
+/* Display frame done */
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_DISP_OVL0_EOF, 25)
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_DISP_RDMA0_EOF, 27)
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_DISP_RDMA1_EOF, 28)
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_DISP_WDMA0_EOF, 29)
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_DISP_CCORR_EOF, 30)
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_DISP_COLOR_EOF, 31)
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_DISP_AAL_EOF, 32)
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_DISP_GAMMA_EOF, 33)
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_DISP_DITHER_EOF, 34)
+
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_DISP_DPI0_EOF, 36)
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_DISP_DSI0_EOF, 37)
+
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_DISP_OVL1_EOF, (-13))
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_DISP_UFOE_EOF, (-14))
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_DISP_WDMA1_EOF, (-15))
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_UFOD_RAMA0_L0_EOF, (-16))
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_UFOD_RAMA0_L1_EOF, (-17))
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_UFOD_RAMA0_L2_EOF, (-18))
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_UFOD_RAMA0_L3_EOF, (-19))
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_UFOD_RAMA1_L0_EOF, (-20))
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_UFOD_RAMA1_L1_EOF, (-21))
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_UFOD_RAMA1_L2_EOF, (-22))
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_UFOD_RAMA1_L3_EOF, (-23))
+
+/* Mutex frame done */
+/* DISPSYS */
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_MUTEX0_STREAM_EOF, 38)
+/* DISPSYS */
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_MUTEX1_STREAM_EOF, 39)
+/* DISPSYS */
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_MUTEX2_STREAM_EOF, 40)
+/* DISPSYS */
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_MUTEX3_STREAM_EOF, 41)
+/* DISPSYS, please refer to disp_hal.h */
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_MUTEX4_STREAM_EOF, 42)
+/* DpFramework */
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_MUTEX5_STREAM_EOF, 43)
+/* DpFramework */
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_MUTEX6_STREAM_EOF, 44)
+/* DpFramework */
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_MUTEX7_STREAM_EOF, 45)
+/* DpFramework */
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_MUTEX8_STREAM_EOF, 46)
+/* DpFramework via CMDQ_IOCTL_LOCK_MUTEX */
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_MUTEX9_STREAM_EOF, 47)
+
+/* Display underrun */
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_DISP_RDMA0_UNDERRUN, 48)
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_DISP_RDMA1_UNDERRUN, 49)
+
+/* Display TE */
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_DSI_TE, 50)
+
+/* ISP frame done */
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_ISP_PASS2_2_EOF, -24)
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_ISP_PASS2_1_EOF, 66)
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_ISP_PASS2_0_EOF, 67)
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_ISP_PASS1_1_EOF, -25)
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_ISP_PASS1_0_EOF, -26)
+
+/* ISP engine events */
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_ISP_CAMSV_2_PASS1_DONE, -27)
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_ISP_CAMSV_1_PASS1_DONE, -28)
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_ISP_SENINF_CAM1_2_3_FULL, -29)
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_ISP_SENINF_CAM0_FULL, 73)
+
+/* VENC frame done */
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_VENC_EOF, -30)
+
+/* JPEG frame done */
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_JPEG_ENC_EOF, -31)
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_JPEG_DEC_EOF, -32)
+
+/* VENC engine events */
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_VENC_MB_DONE, -33)
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_VENC_128BYTE_CNT_DONE, -34)
+
+/* Keep this at the end of HW events */
+DECLARE_CMDQ_EVENT(CMDQ_MAX_HW_EVENT_COUNT, 400)
+
+/* SW Sync Tokens (Pre-defined) */
+/* Config thread notify trigger thread */
+DECLARE_CMDQ_EVENT(CMDQ_SYNC_TOKEN_CONFIG_DIRTY, 401)
+/* Trigger thread notify config thread */
+DECLARE_CMDQ_EVENT(CMDQ_SYNC_TOKEN_STREAM_EOF, 402)
+/* Block Trigger thread until the ESD check finishes. */
+DECLARE_CMDQ_EVENT(CMDQ_SYNC_TOKEN_ESD_EOF, 403)
+/* check CABC setup finish */
+DECLARE_CMDQ_EVENT(CMDQ_SYNC_TOKEN_CABC_EOF, 404)
+/* Block Trigger thread until the path freeze finishes */
+DECLARE_CMDQ_EVENT(CMDQ_SYNC_TOKEN_FREEZE_EOF, 405)
+/* Pass-2 notifies VENC frame is ready to be encoded */
+DECLARE_CMDQ_EVENT(CMDQ_SYNC_TOKEN_VENC_INPUT_READY, 406)
+/* VENC notifies Pass-2 encode done so next frame may start */
+DECLARE_CMDQ_EVENT(CMDQ_SYNC_TOKEN_VENC_EOF, 407)
+
+/* Notify normal CMDQ there are some secure task done */
+DECLARE_CMDQ_EVENT(CMDQ_SYNC_SECURE_THR_EOF, 408)
+
+/* SW Sync Tokens (User-defined) */
+DECLARE_CMDQ_EVENT(CMDQ_SYNC_TOKEN_USER_0, 410)
+DECLARE_CMDQ_EVENT(CMDQ_SYNC_TOKEN_USER_1, 411)
+DECLARE_CMDQ_EVENT(CMDQ_SYNC_TOKEN_POLL_MONITOR, 412)
+
+/* Event for CMDQ to block executing command when append command
+* Plz sync CMDQ_SYNC_TOKEN_APPEND_THR(id) in cmdq_core source file. */
+DECLARE_CMDQ_EVENT(CMDQ_SYNC_TOKEN_APPEND_THR0, 422)
+DECLARE_CMDQ_EVENT(CMDQ_SYNC_TOKEN_APPEND_THR1, 423)
+DECLARE_CMDQ_EVENT(CMDQ_SYNC_TOKEN_APPEND_THR2, 424)
+DECLARE_CMDQ_EVENT(CMDQ_SYNC_TOKEN_APPEND_THR3, 425)
+DECLARE_CMDQ_EVENT(CMDQ_SYNC_TOKEN_APPEND_THR4, 426)
+DECLARE_CMDQ_EVENT(CMDQ_SYNC_TOKEN_APPEND_THR5, 427)
+DECLARE_CMDQ_EVENT(CMDQ_SYNC_TOKEN_APPEND_THR6, 428)
+DECLARE_CMDQ_EVENT(CMDQ_SYNC_TOKEN_APPEND_THR7, 429)
+DECLARE_CMDQ_EVENT(CMDQ_SYNC_TOKEN_APPEND_THR8, 430)
+DECLARE_CMDQ_EVENT(CMDQ_SYNC_TOKEN_APPEND_THR9, 431)
+DECLARE_CMDQ_EVENT(CMDQ_SYNC_TOKEN_APPEND_THR10, 432)
+DECLARE_CMDQ_EVENT(CMDQ_SYNC_TOKEN_APPEND_THR11, 433)
+DECLARE_CMDQ_EVENT(CMDQ_SYNC_TOKEN_APPEND_THR12, 434)
+DECLARE_CMDQ_EVENT(CMDQ_SYNC_TOKEN_APPEND_THR13, 435)
+DECLARE_CMDQ_EVENT(CMDQ_SYNC_TOKEN_APPEND_THR14, 436)
+DECLARE_CMDQ_EVENT(CMDQ_SYNC_TOKEN_APPEND_THR15, 437)
+
+/* GPR access tokens (for HW register backup) */
+/* There are 15 32-bit GPR, 3 GPR form a set (64-bit for address, 32-bit for value) */
+DECLARE_CMDQ_EVENT(CMDQ_SYNC_TOKEN_GPR_SET_0, 450)
+DECLARE_CMDQ_EVENT(CMDQ_SYNC_TOKEN_GPR_SET_1, 451)
+DECLARE_CMDQ_EVENT(CMDQ_SYNC_TOKEN_GPR_SET_2, 452)
+DECLARE_CMDQ_EVENT(CMDQ_SYNC_TOKEN_GPR_SET_3, 453)
+DECLARE_CMDQ_EVENT(CMDQ_SYNC_TOKEN_GPR_SET_4, 454)
+
+/* Resource lock event to control resource in GCE thread */
+DECLARE_CMDQ_EVENT(CMDQ_SYNC_RESOURCE_WROT0, 460)
+
+/* event id is 9 bit */
+DECLARE_CMDQ_EVENT(CMDQ_SYNC_TOKEN_MAX, (0x1FF))
+DECLARE_CMDQ_EVENT(CMDQ_SYNC_TOKEN_INVALID, (-1))
diff --git a/kernel-headers/cmdq_event_D3.h b/kernel-headers/cmdq_event_D3.h
new file mode 100644
index 0000000..fdbbd87
--- /dev/null
+++ b/kernel-headers/cmdq_event_D3.h
@@ -0,0 +1,182 @@
+/* MDP start frame */
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_MDP_RDMA0_SOF, 0)
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_MDP_RSZ0_SOF, 1)
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_MDP_RSZ1_SOF, 2)
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_MDP_TDSHP_SOF, 3)
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_MDP_WDMA_SOF, 4)
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_MDP_WROT_SOF, 5)
+
+/* Display start frame */
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_DISP_OVL0_SOF, 6)
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_DISP_OVL1_SOF, 7)
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_DISP_RDMA0_SOF, 8)
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_DISP_RDMA1_SOF, 9)
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_DISP_WDMA0_SOF, 10)
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_DISP_CCORR_SOF, 11)
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_DISP_COLOR_SOF, 12)
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_DISP_AAL_SOF, 13)
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_DISP_GAMMA_SOF, 14)
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_DISP_DITHER_SOF, 15)
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_DISP_PWM0_SOF, 17)
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_DISP_OD_SOF, 18)
+
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_DISP_UFOE_SOF, (-3))
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_DISP_WDMA1_SOF, (-4))
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_UFOD_RAMA0_L0_SOF, (-5))
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_UFOD_RAMA0_L1_SOF, (-6))
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_UFOD_RAMA0_L2_SOF, (-7))
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_UFOD_RAMA0_L3_SOF, (-8))
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_UFOD_RAMA1_L0_SOF, (-9))
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_UFOD_RAMA1_L1_SOF, (-10))
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_UFOD_RAMA1_L2_SOF, (-11))
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_UFOD_RAMA1_L3_SOF, (-12))
+
+
+/* MDP frame done */
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_MDP_RDMA0_EOF, 19)
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_MDP_RSZ0_EOF, 20)
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_MDP_RSZ1_EOF, 21)
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_MDP_TDSHP_EOF, 22)
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_MDP_WDMA_EOF, 23)
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_MDP_WROT_WRITE_EOF, 24)
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_MDP_WROT_READ_EOF, 25)
+
+/* Display frame done */
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_DISP_OVL0_EOF, 26)
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_DISP_OVL1_EOF, 27)
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_DISP_RDMA0_EOF, 28)
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_DISP_RDMA1_EOF, 29)
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_DISP_WDMA0_EOF, 30)
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_DISP_CCORR_EOF, 31)
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_DISP_COLOR_EOF, 32)
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_DISP_AAL_EOF, 33)
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_DISP_GAMMA_EOF, 34)
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_DISP_DITHER_EOF, 35)
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_DISP_OD_EOF, 37)
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_DISP_DPI0_EOF, 38)
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_DISP_DSI0_EOF, 39)
+
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_DISP_UFOE_EOF, (-14))
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_DISP_WDMA1_EOF, (-15))
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_UFOD_RAMA0_L0_EOF, (-16))
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_UFOD_RAMA0_L1_EOF, (-17))
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_UFOD_RAMA0_L2_EOF, (-18))
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_UFOD_RAMA0_L3_EOF, (-19))
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_UFOD_RAMA1_L0_EOF, (-20))
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_UFOD_RAMA1_L1_EOF, (-21))
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_UFOD_RAMA1_L2_EOF, (-22))
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_UFOD_RAMA1_L3_EOF, (-23))
+
+/* Mutex frame done */
+/* DISPSYS */
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_MUTEX0_STREAM_EOF, 40)
+/* DISPSYS */
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_MUTEX1_STREAM_EOF, 41)
+/* DISPSYS */
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_MUTEX2_STREAM_EOF, 42)
+/* DISPSYS */
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_MUTEX3_STREAM_EOF, 43)
+/* DISPSYS, please refer to disp_hal.h */
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_MUTEX4_STREAM_EOF, 44)
+/* DpFramework */
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_MUTEX5_STREAM_EOF, 45)
+/* DpFramework */
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_MUTEX6_STREAM_EOF, 46)
+/* DpFramework */
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_MUTEX7_STREAM_EOF, 47)
+/* DpFramework */
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_MUTEX8_STREAM_EOF, 48)
+/* DpFramework via CMDQ_IOCTL_LOCK_MUTEX */
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_MUTEX9_STREAM_EOF, 49)
+
+/* Display underrun */
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_DISP_RDMA0_UNDERRUN, 50)
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_DISP_RDMA1_UNDERRUN, 51)
+
+/* Display TE */
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_DSI_TE, 52)
+
+/* ISP frame done */
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_ISP_PASS2_2_EOF, 65)
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_ISP_PASS2_1_EOF, 66)
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_ISP_PASS2_0_EOF, 67)
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_ISP_PASS1_1_EOF, 68)
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_ISP_PASS1_0_EOF, 69)
+
+/* ISP engine events */
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_ISP_CAMSV_2_PASS1_DONE, 70)
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_ISP_CAMSV_1_PASS1_DONE, 71)
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_ISP_SENINF_CAM1_2_3_FULL, 72)
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_ISP_SENINF_CAM0_FULL, 73)
+
+/* VENC frame done */
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_VENC_EOF, 129)
+
+/* JPEG frame done */
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_JPEG_ENC_EOF, 130)
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_JPEG_DEC_EOF, 131)
+
+/* VENC engine events */
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_VENC_MB_DONE, 132)
+DECLARE_CMDQ_EVENT(CMDQ_EVENT_VENC_128BYTE_CNT_DONE, 133)
+
+/* Keep this at the end of HW events */
+DECLARE_CMDQ_EVENT(CMDQ_MAX_HW_EVENT_COUNT, 400)
+
+/* SW Sync Tokens (Pre-defined) */
+/* Config thread notify trigger thread */
+DECLARE_CMDQ_EVENT(CMDQ_SYNC_TOKEN_CONFIG_DIRTY, 401)
+/* Trigger thread notify config thread */
+DECLARE_CMDQ_EVENT(CMDQ_SYNC_TOKEN_STREAM_EOF, 402)
+/* Block Trigger thread until the ESD check finishes. */
+DECLARE_CMDQ_EVENT(CMDQ_SYNC_TOKEN_ESD_EOF, 403)
+/* check CABC setup finish */
+DECLARE_CMDQ_EVENT(CMDQ_SYNC_TOKEN_CABC_EOF, 404)
+/* Block Trigger thread until the path freeze finishes */
+DECLARE_CMDQ_EVENT(CMDQ_SYNC_TOKEN_FREEZE_EOF, 405)
+/* Pass-2 notifies VENC frame is ready to be encoded */
+DECLARE_CMDQ_EVENT(CMDQ_SYNC_TOKEN_VENC_INPUT_READY, 406)
+/* VENC notifies Pass-2 encode done so next frame may start */
+DECLARE_CMDQ_EVENT(CMDQ_SYNC_TOKEN_VENC_EOF, 407)
+
+/* Notify normal CMDQ there are some secure task done */
+DECLARE_CMDQ_EVENT(CMDQ_SYNC_SECURE_THR_EOF, 408)
+
+/* SW Sync Tokens (User-defined) */
+DECLARE_CMDQ_EVENT(CMDQ_SYNC_TOKEN_USER_0, 410)
+DECLARE_CMDQ_EVENT(CMDQ_SYNC_TOKEN_USER_1, 411)
+DECLARE_CMDQ_EVENT(CMDQ_SYNC_TOKEN_POLL_MONITOR, 412)
+
+/* Event for CMDQ to block executing command when append command
+* Plz sync CMDQ_SYNC_TOKEN_APPEND_THR(id) in cmdq_core source file. */
+DECLARE_CMDQ_EVENT(CMDQ_SYNC_TOKEN_APPEND_THR0, 422)
+DECLARE_CMDQ_EVENT(CMDQ_SYNC_TOKEN_APPEND_THR1, 423)
+DECLARE_CMDQ_EVENT(CMDQ_SYNC_TOKEN_APPEND_THR2, 424)
+DECLARE_CMDQ_EVENT(CMDQ_SYNC_TOKEN_APPEND_THR3, 425)
+DECLARE_CMDQ_EVENT(CMDQ_SYNC_TOKEN_APPEND_THR4, 426)
+DECLARE_CMDQ_EVENT(CMDQ_SYNC_TOKEN_APPEND_THR5, 427)
+DECLARE_CMDQ_EVENT(CMDQ_SYNC_TOKEN_APPEND_THR6, 428)
+DECLARE_CMDQ_EVENT(CMDQ_SYNC_TOKEN_APPEND_THR7, 429)
+DECLARE_CMDQ_EVENT(CMDQ_SYNC_TOKEN_APPEND_THR8, 430)
+DECLARE_CMDQ_EVENT(CMDQ_SYNC_TOKEN_APPEND_THR9, 431)
+DECLARE_CMDQ_EVENT(CMDQ_SYNC_TOKEN_APPEND_THR10, 432)
+DECLARE_CMDQ_EVENT(CMDQ_SYNC_TOKEN_APPEND_THR11, 433)
+DECLARE_CMDQ_EVENT(CMDQ_SYNC_TOKEN_APPEND_THR12, 434)
+DECLARE_CMDQ_EVENT(CMDQ_SYNC_TOKEN_APPEND_THR13, 435)
+DECLARE_CMDQ_EVENT(CMDQ_SYNC_TOKEN_APPEND_THR14, 436)
+DECLARE_CMDQ_EVENT(CMDQ_SYNC_TOKEN_APPEND_THR15, 437)
+
+/* GPR access tokens (for HW register backup) */
+/* There are 15 32-bit GPR, 3 GPR form a set (64-bit for address, 32-bit for value) */
+DECLARE_CMDQ_EVENT(CMDQ_SYNC_TOKEN_GPR_SET_0, 450)
+DECLARE_CMDQ_EVENT(CMDQ_SYNC_TOKEN_GPR_SET_1, 451)
+DECLARE_CMDQ_EVENT(CMDQ_SYNC_TOKEN_GPR_SET_2, 452)
+DECLARE_CMDQ_EVENT(CMDQ_SYNC_TOKEN_GPR_SET_3, 453)
+DECLARE_CMDQ_EVENT(CMDQ_SYNC_TOKEN_GPR_SET_4, 454)
+
+/* Resource lock event to control resource in GCE thread */
+DECLARE_CMDQ_EVENT(CMDQ_SYNC_RESOURCE_WROT0, 460)
+
+/* event id is 9 bit */
+DECLARE_CMDQ_EVENT(CMDQ_SYNC_TOKEN_MAX, (0x1FF))
+DECLARE_CMDQ_EVENT(CMDQ_SYNC_TOKEN_INVALID, (-1))
diff --git a/kernel-headers/cmdq_subsys.h b/kernel-headers/cmdq_subsys.h
new file mode 100644
index 0000000..f7b3bf4
--- /dev/null
+++ b/kernel-headers/cmdq_subsys.h
@@ -0,0 +1,28 @@
+/* msb     id   group        reg-base-name */
+DECLARE_CMDQ_SUBSYS(0x1300, 0, MFG, G3D_CONFIG_BASE)
+DECLARE_CMDQ_SUBSYS(0x1400, 1, MMSYS, MMSYS_CONFIG_BASE)
+DECLARE_CMDQ_SUBSYS(0x1401, 2, MMSYS, DISP_DITHER_BASE)
+DECLARE_CMDQ_SUBSYS(0x1402, 3, MMSYS, NA)
+DECLARE_CMDQ_SUBSYS(0x1500, 4, CAM, IMGSYS_BASE)
+DECLARE_CMDQ_SUBSYS(0x1600, 5, VDEC, VDEC_GCON_BASE)
+DECLARE_CMDQ_SUBSYS(0x1700, 6, VENC, VENC_GCON_BASE)
+DECLARE_CMDQ_SUBSYS(0x1800, 7, PERISYS, CONN_PERIPHERALS)
+
+DECLARE_CMDQ_SUBSYS(0x1000, 8, TOP_AO_3, TOPCKGEN_BASE)
+DECLARE_CMDQ_SUBSYS(0x1001, 9, INFRA_AO, KP_BASE)
+DECLARE_CMDQ_SUBSYS(0x1002, 10, INFRA_AO, SCP_SRAM_BASE)
+DECLARE_CMDQ_SUBSYS(0x1003, 11, NA, NA)
+DECLARE_CMDQ_SUBSYS(0x1004, 12, NA, NA)
+DECLARE_CMDQ_SUBSYS(0x1005, 13, SCP, SCP)
+
+DECLARE_CMDQ_SUBSYS(0x1020, 14, INFRASYS, MCUCFG_BASE)
+DECLARE_CMDQ_SUBSYS(0x1021, 15, INFRASYS, GCPU_BASE)
+DECLARE_CMDQ_SUBSYS(0x1120, 16, PERISYS, USB0_BASE)
+DECLARE_CMDQ_SUBSYS(0x1121, 17, PERISYS, USB_SIF_BASE)
+DECLARE_CMDQ_SUBSYS(0x1122, 18, PERISYS, AUDIO_BASE)
+DECLARE_CMDQ_SUBSYS(0x1123, 19, PERISYS, MSDC0_BASE)
+DECLARE_CMDQ_SUBSYS(0x1124, 20, PERISYS, MSDC1_BASE)
+DECLARE_CMDQ_SUBSYS(0x1125, 21, PERISYS, MSDC2_BASE)
+DECLARE_CMDQ_SUBSYS(0x1126, 22, PERISYS, MSDC3_BASE)
+
+/*if id is over 99 check cmdq_platform.h: #define CMDQ_SPECIAL_SUBSYS_ADDR 99 */
diff --git a/kernel-headers/cmdq_subsys_common.h b/kernel-headers/cmdq_subsys_common.h
index 1872b80..1872b80 100644..100755
--- a/kernel-headers/cmdq_subsys_common.h
+++ b/kernel-headers/cmdq_subsys_common.h
diff --git a/kernel-headers/ddp_aal.h b/kernel-headers/ddp_aal.h
new file mode 100644
index 0000000..287bcbe
--- /dev/null
+++ b/kernel-headers/ddp_aal.h
@@ -0,0 +1,29 @@
+#ifndef __DDP_AAL_H__
+#define __DDP_AAL_H__
+
+#define AAL_HIST_BIN        33	/* [0..32] */
+#define AAL_DRE_POINT_NUM   29
+
+#define AAL_SERVICE_FORCE_UPDATE 0x1
+
+typedef struct {
+	/* DRE */
+	int dre_map_bypass;
+	/* CABC */
+	int cabc_gainlmt[33];
+} DISP_AAL_INITREG;
+
+typedef struct {
+	unsigned int serviceFlags;
+	int backlight;
+	unsigned int maxHist[AAL_HIST_BIN];
+} DISP_AAL_HIST;
+
+typedef struct {
+	int DREGainFltStatus[AAL_DRE_POINT_NUM];
+	int cabc_fltgain_force;	/* 10-bit ; [0,1023] */
+	int cabc_gainlmt[33];
+	int FinalBacklight;	/* 10-bit ; [0,1023] */
+} DISP_AAL_PARAM;
+
+#endif
diff --git a/kernel-headers/ddp_data_type.h b/kernel-headers/ddp_data_type.h
new file mode 100644
index 0000000..60486d1
--- /dev/null
+++ b/kernel-headers/ddp_data_type.h
@@ -0,0 +1,165 @@
+#ifndef __DP_DATA_TYPE_H__
+#define __DP_DATA_TYPE_H__
+
+#ifndef MAX
+    #define MAX(x, y)   ((x) >= (y))? (x): (y)
+#endif // MAX
+
+#ifndef MIN
+    #define MIN(x, y)   ((x) <= (y))? (x): (y)
+#endif  // MIN
+
+//FMT GROUP , 0-RGB , 1-YUV , 2-Bayer raw , 3-compressed format
+#define DP_COLORFMT_PACK(VIDEO, PLANE, COPLANE, HFACTOR, VFACTOR, BITS, GROUP ,SWAP_ENABLE, UNIQUEID)  \
+    ((VIDEO         << 27) |                                                             \
+     (PLANE         << 24) |                                                             \
+     (COPLANE       << 22) |                                                             \
+     (HFACTOR       << 20) |                                                             \
+     (VFACTOR       << 18) |                                                             \
+     (BITS          << 8)  |                                                             \
+     (GROUP         << 6)  |                                                             \
+     (SWAP_ENABLE   << 5)  |                                                             \
+     (UNIQUEID      << 0)) 
+
+#define DP_COLOR_GET_INTERLACED_MODE(color)     ((0x10000000 & color) >> 28)
+#define DP_COLOR_GET_BLOCK_MODE(color)          ((0x18000000 & color) >> 27)
+#define DP_COLOR_GET_PLANE_COUNT(color)         ((0x07000000 & color) >> 24)
+#define DP_COLOR_IS_UV_COPLANE(color)           ((0x00C00000 & color) >> 22)
+#define DP_COLOR_GET_H_SUBSAMPLE(color)         ((0x00300000 & color) >> 20)
+#define DP_COLOR_GET_V_SUBSAMPLE(color)         ((0x000C0000 & color) >> 18)
+#define DP_COLOR_BITS_PER_PIXEL(color)          ((0x0003FF00 & color) >>  8)
+#define DP_COLOR_GET_COLOR_GROUP(color)         ((0x000000C0 & color) >>  6)
+#define DP_COLOR_GET_SWAP_ENABLE(color)         ((0x00000020 & color) >>  5)
+#define DP_COLOR_GET_UNIQUE_ID(color)           ((0x0000001F & color) >>  0)
+#define DP_COLOR_GET_HW_FORMAT(color)           ((0x0000001F & color) >>  0)
+
+typedef enum DP_COLOR_ENUM
+{                                                       
+    DP_COLOR_BAYER8         = DP_COLORFMT_PACK(0,   1,  0, 0, 0,  8, 2,  0, 20),
+    DP_COLOR_BAYER10        = DP_COLORFMT_PACK(0,   1,  0, 0, 0, 10, 2,  0, 21),
+    DP_COLOR_BAYER12        = DP_COLORFMT_PACK(0,   1,  0, 0, 0, 12, 2,  0, 22),
+    DP_COLOR_RGB565         = DP_COLORFMT_PACK(0,   1,  0, 0, 0, 16, 0,  0, 0),
+    DP_COLOR_BGR565         = DP_COLORFMT_PACK(0,   1,  0, 0, 0, 16, 0,  1, 0),
+    DP_COLOR_RGB888         = DP_COLORFMT_PACK(0,   1,  0, 0, 0, 24, 0,  1, 1),
+    DP_COLOR_BGR888         = DP_COLORFMT_PACK(0,   1,  0, 0, 0, 24, 0,  0, 1),
+    DP_COLOR_RGBX8888       = DP_COLORFMT_PACK(0,   1,  0, 0, 0, 32, 0,  0, 23),
+    DP_COLOR_BGRX8888       = DP_COLORFMT_PACK(0,   1,  0, 0, 0, 32, 0,  1, 23),
+    DP_COLOR_RGBA8888       = DP_COLORFMT_PACK(0,   1,  0, 0, 0, 32, 0,  1, 2),
+    DP_COLOR_BGRA8888       = DP_COLORFMT_PACK(0,   1,  0, 0, 0, 32, 0,  0, 2),
+    DP_COLOR_XRGB8888       = DP_COLORFMT_PACK(0,   1,  0, 0, 0, 32, 0,  0, 24),
+    DP_COLOR_XBGR8888       = DP_COLORFMT_PACK(0,   1,  0, 0, 0, 32, 0,  1, 24),
+    DP_COLOR_ARGB8888       = DP_COLORFMT_PACK(0,   1,  0, 0, 0, 32, 0,  1, 3),
+    DP_COLOR_ABGR8888       = DP_COLORFMT_PACK(0,   1,  0, 0, 0, 32, 0,  0, 3),
+    DP_COLOR_I420           = DP_COLORFMT_PACK(0,   3,  0, 1, 1,  8, 1,  0, 8),
+    DP_COLOR_YV12           = DP_COLORFMT_PACK(0,   3,  0, 1, 1,  8, 1,  1, 8),
+    DP_COLOR_NV12           = DP_COLORFMT_PACK(0,   2,  1, 1, 1,  8, 1,  0, 12),
+    DP_COLOR_NV21           = DP_COLORFMT_PACK(0,   2,  1, 1, 1,  8, 1,  1, 12),
+    DP_COLOR_I422           = DP_COLORFMT_PACK(0,   3,  0, 1, 0,  8, 1,  0, 9),
+    DP_COLOR_YV16           = DP_COLORFMT_PACK(0,   3,  0, 1, 0,  8, 1,  1, 9),
+    DP_COLOR_NV16           = DP_COLORFMT_PACK(0,   2,  1, 1, 0,  8, 1,  0, 13),
+    DP_COLOR_NV61           = DP_COLORFMT_PACK(0,   2,  1, 1, 0,  8, 1,  1, 13),
+    DP_COLOR_YUYV           = DP_COLORFMT_PACK(0,   1,  0, 1, 0, 16, 1,  0, 5),
+    DP_COLOR_YVYU           = DP_COLORFMT_PACK(0,   1,  0, 1, 0, 16, 1,  1, 5),
+    DP_COLOR_UYVY           = DP_COLORFMT_PACK(0,   1,  0, 1, 0, 16, 1,  0, 4),
+    DP_COLOR_VYUY           = DP_COLORFMT_PACK(0,   1,  0, 1, 0, 16, 1,  1, 4),
+    DP_COLOR_I444           = DP_COLORFMT_PACK(0,   3,  0, 0, 0,  8, 1,  0, 10),
+    DP_COLOR_YV24           = DP_COLORFMT_PACK(0,   3,  0, 0, 0,  8, 1,  1, 10),
+    DP_COLOR_IYU2           = DP_COLORFMT_PACK(0,   1,  0, 0, 0, 24, 1,  0, 25),
+    DP_COLOR_NV24           = DP_COLORFMT_PACK(0,   2,  1, 0, 0,  8, 1,  0, 14),
+    DP_COLOR_NV42           = DP_COLORFMT_PACK(0,   2,  1, 0, 0,  8, 1,  1, 14),
+    DP_COLOR_GREY           = DP_COLORFMT_PACK(0,   1,  0, 0, 0,  8, 1,  0, 7),
+    
+
+    // Mediatek proprietary format
+    DP_COLOR_420_BLKP       = DP_COLORFMT_PACK(1,   2,  1, 1, 1, 256, 1, 0 , 12),//Field mode
+    DP_COLOR_420_BLKI       = DP_COLORFMT_PACK(3,   2,  1, 1, 1, 256, 1, 0 , 12),//Field mode + Video mode
+    DP_COLOR_422_BLKP       = DP_COLORFMT_PACK(1,   1,  0, 1, 0, 512, 1, 0 , 4),  //Field mode
+} DP_COLOR_ENUM;
+
+
+// Legacy for 6589 compatible
+typedef DP_COLOR_ENUM DpColorFormat;
+
+#define eYUV_420_3P             DP_COLOR_I420
+#define eYUV_420_2P_YUYV        DP_COLOR_YUYV
+#define eYUV_420_2P_UYVY        DP_COLOR_UYVY
+#define eYUV_420_2P_YVYU        DP_COLOR_YVYU
+#define eYUV_420_2P_VYUY        DP_COLOR_VYUY
+#define eYUV_420_2P_ISP_BLK     DP_COLOR_420_BLKP
+#define eYUV_420_2P_VDO_BLK     DP_COLOR_420_BLKI
+#define eYUV_422_3P             DP_COLOR_I422
+#define eYUV_422_2P             DP_COLOR_NV16
+#define eYUV_422_I              DP_COLOR_YUYV
+#define eYUV_422_I_BLK          DP_COLOR_422_BLKP
+#define eYUV_444_3P             DP_COLOR_I444
+#define eYUV_444_2P             DP_COLOR_NV24
+#define eYUV_444_1P             DP_COLOR_YUV444
+#define eBAYER8                 DP_COLOR_BAYER8
+#define eBAYER10                DP_COLOR_BAYER10
+#define eBAYER12                DP_COLOR_BAYER12
+#define eRGB565                 DP_COLOR_RGB565
+#define eBGR565                 DP_COLOR_BGR565
+#define eRGB888                 DP_COLOR_RGB888
+#define eBGR888                 DP_COLOR_BGR888
+#define eARGB8888               DP_COLOR_ARGB8888
+#define eABGR8888               DP_COLOR_ABGR8888
+#define eRGBA8888               DP_COLOR_RGBA8888
+#define eBGRA8888               DP_COLOR_BGRA8888
+#define eXRGB8888               DP_COLOR_XRGB8888
+#define eXBGR8888               DP_COLOR_XBGR8888
+#define eRGBX8888               DP_COLOR_RGBX8888
+#define eBGRX8888               DP_COLOR_BGRX8888
+#define ePARGB8888              DP_COLOR_PARGB8888
+#define eXARGB8888              DP_COLOR_XARGB8888
+#define ePABGR8888              DP_COLOR_PABGR8888
+#define eXABGR8888              DP_COLOR_XABGR8888
+#define eGREY                   DP_COLOR_GREY
+#define eI420                   DP_COLOR_I420
+#define eYV12                   DP_COLOR_YV12
+#define eIYU2                   DP_COLOR_IYU2   
+
+
+#define eYV21                   DP_COLOR_I420
+#define eNV12_BLK               DP_COLOR_420_BLKP
+#define eNV12_BLK_FCM           DP_COLOR_420_BLKI
+#define eYUV_420_3P_YVU         DP_COLOR_YV12
+
+#define eNV12_BP                DP_COLOR_420_BLKP
+#define eNV12_BI                DP_COLOR_420_BLKI
+#define eNV12                   DP_COLOR_NV12
+#define eNV21                   DP_COLOR_NV21
+#define eI422                   DP_COLOR_I422
+#define eYV16                   DP_COLOR_YV16
+#define eNV16                   DP_COLOR_NV16
+#define eNV61                   DP_COLOR_NV61
+#define eUYVY                   DP_COLOR_UYVY
+#define eVYUY                   DP_COLOR_VYUY
+#define eYUYV                   DP_COLOR_YUYV
+#define eYVYU                   DP_COLOR_YVYU
+#define eUYVY_BP                DP_COLOR_422_BLKP
+#define eI444                   DP_COLOR_I444
+#define eNV24                   DP_COLOR_NV24
+#define eNV42                   DP_COLOR_NV42
+#define eYUY2                   DP_COLOR_YUYV
+#define eY800                   DP_COLOR_GREY
+//#define eIYU2
+#define eMTKYUV                 DP_COLOR_422_BLKP
+
+#define eCompactRaw1            DP_COLOR_BAYER10
+
+
+enum DpInterlaceFormat
+{
+    eInterlace_None,
+    eTop_Field,
+    eBottom_Field
+};
+
+enum DpSecure
+{
+	DP_SECURE_NONE = 0,
+	DP_SECURE	   = 1
+};
+
+
+#endif  // __DP_DATA_TYPE_H__
diff --git a/kernel-headers/ddp_drv.h b/kernel-headers/ddp_drv.h
new file mode 100644
index 0000000..284658e
--- /dev/null
+++ b/kernel-headers/ddp_drv.h
@@ -0,0 +1,332 @@
+
+#ifndef __DDP_DRV_H__
+#define __DDP_DRV_H__
+#include <linux/ioctl.h>
+#include <sys/types.h>
+#include "ddp_hal.h"
+#include "ddp_aal.h"
+#include "ddp_gamma.h"
+#include "disp_event.h"
+
+typedef struct
+{
+    unsigned int reg;
+    unsigned int val;
+    unsigned int mask;
+} DISP_WRITE_REG;
+
+typedef struct
+{
+    unsigned int reg;
+    unsigned int val;
+    unsigned int mask;
+} DISP_READ_REG;
+
+#if 0
+typedef struct
+{
+    DISP_MODULE_ENUM module;
+    unsigned int timeout_ms;  //timeout, unit is ms
+} disp_wait_irq_struct;
+#endif
+
+typedef struct DISP_EXEC_COMMAND
+{
+    int taskID;
+    uint32_t scenario;
+    uint32_t priority;
+    uint32_t engineFlag;
+    uint32_t *pFrameBaseSW;
+    uint32_t *pTileBaseSW;
+    uint32_t blockSize;
+} DISP_EXEC_COMMAND;
+
+typedef struct
+{
+    int layer;
+
+    unsigned long addr;
+    unsigned int fmt;
+
+    int x;
+    int y;
+    int w;
+    int h;                  // clip region
+    int pitch;
+} DISP_OVL_INFO;
+
+//PQ
+#define COLOR_TUNING_INDEX 19
+#define THSHP_TUNING_INDEX 12
+#define THSHP_PARAM_MAX 83
+#define PARTIAL_Y_INDEX 10
+
+#define GLOBAL_SAT_SIZE 10
+#define CONTRAST_SIZE 10
+#define BRIGHTNESS_SIZE 10
+#define PARTIAL_Y_SIZE 28
+#define PQ_HUE_ADJ_PHASE_CNT 4
+#define PQ_SAT_ADJ_PHASE_CNT 4
+#define PQ_PARTIALS_CONTROL 5
+#define PURP_TONE_SIZE 3
+#define SKIN_TONE_SIZE 8 //(-6)
+#define GRASS_TONE_SIZE 6 //(-2)
+#define SKY_TONE_SIZE 3
+#define CCORR_COEF_CNT 4 /* ccorr feature */
+
+typedef struct {
+    unsigned int u4SHPGain;    // 0 : min , 9 : max.
+    unsigned int u4SatGain;    // 0 : min , 9 : max.
+    unsigned int u4PartialY;   /* 0 : min , 9 : max. */
+    unsigned int u4HueAdj[PQ_HUE_ADJ_PHASE_CNT];
+    unsigned int u4SatAdj[PQ_SAT_ADJ_PHASE_CNT];
+    unsigned int u4Contrast;   // 0 : min , 9 : max.
+    unsigned int u4Brightness; // 0 : min , 9 : max.
+    unsigned int u4Ccorr;      /* 0 : min , 3 : max. ccorr feature */
+} DISP_PQ_PARAM;
+
+typedef struct {
+    int split_en;
+    int start_x;
+    int start_y;
+    int end_x;
+    int end_y;
+} DISP_PQ_WIN_PARAM;
+
+typedef struct {
+    int image;
+    int video;
+    int camera;
+} DISP_PQ_MAPPING_PARAM;
+
+typedef struct {
+    unsigned int en;
+    unsigned int pos_x;
+    unsigned int pos_y;
+} MDP_COLOR_CAP;
+
+typedef struct {
+    unsigned int TDS_GAIN_MID;
+    unsigned int TDS_GAIN_HIGH;
+    unsigned int TDS_COR_GAIN;
+    unsigned int TDS_COR_THR;
+    unsigned int TDS_COR_ZERO;
+    unsigned int TDS_GAIN;
+    unsigned int TDS_COR_VALUE;
+} MDP_TDSHP_REG;
+
+typedef struct{
+
+    unsigned short GLOBAL_SAT  [GLOBAL_SAT_SIZE];
+    unsigned short CONTRAST    [CONTRAST_SIZE];
+    unsigned short BRIGHTNESS  [BRIGHTNESS_SIZE];
+    unsigned char PARTIAL_Y    [PARTIAL_Y_INDEX][PARTIAL_Y_SIZE];
+    unsigned char PURP_TONE_S  [COLOR_TUNING_INDEX][PQ_PARTIALS_CONTROL][PURP_TONE_SIZE];
+    unsigned char SKIN_TONE_S  [COLOR_TUNING_INDEX][PQ_PARTIALS_CONTROL][SKIN_TONE_SIZE];
+    unsigned char GRASS_TONE_S [COLOR_TUNING_INDEX][PQ_PARTIALS_CONTROL][GRASS_TONE_SIZE];
+    unsigned char SKY_TONE_S   [COLOR_TUNING_INDEX][PQ_PARTIALS_CONTROL][SKY_TONE_SIZE];
+    unsigned char PURP_TONE_H  [COLOR_TUNING_INDEX][PURP_TONE_SIZE];
+    unsigned char SKIN_TONE_H  [COLOR_TUNING_INDEX][SKIN_TONE_SIZE];
+    unsigned char GRASS_TONE_H [COLOR_TUNING_INDEX][GRASS_TONE_SIZE];
+    unsigned char SKY_TONE_H   [COLOR_TUNING_INDEX][SKY_TONE_SIZE];
+    unsigned int  CCORR_COEF   [CCORR_COEF_CNT][3][3];
+
+} DISPLAY_PQ_T;
+
+typedef struct{
+
+    unsigned int entry[THSHP_TUNING_INDEX][THSHP_PARAM_MAX];
+
+} DISPLAY_TDSHP_T;
+
+typedef enum {
+    DS_en = 0,
+    iUpSlope,
+    iUpThreshold,
+    iDownSlope,
+    iDownThreshold,
+    iISO_en,
+    iISO_thr1,
+    iISO_thr0,
+    iISO_thr3,
+    iISO_thr2,
+    iISO_IIR_alpha,
+    iCorZero_clip2,
+    iCorZero_clip1,
+    iCorZero_clip0,
+    iCorThr_clip2,
+    iCorThr_clip1,
+    iCorThr_clip0,
+    iCorGain_clip2,
+    iCorGain_clip1,
+    iCorGain_clip0,
+    iGain_clip2,
+    iGain_clip1,
+    iGain_clip0,
+    PQ_DS_INDEX_MAX
+} PQ_DS_index_t;
+
+
+typedef struct {
+
+    int param[PQ_DS_INDEX_MAX];
+
+} DISP_PQ_DS_PARAM;
+
+typedef enum {
+    BlackEffectEnable = 0,
+    WhiteEffectEnable,
+    StrongBlackEffect,
+    StrongWhiteEffect,
+    AdaptiveBlackEffect,
+    AdaptiveWhiteEffect,
+    ScenceChangeOnceEn,
+    ScenceChangeControlEn,
+    ScenceChangeControl,
+    ScenceChangeTh1,
+    ScenceChangeTh2,
+    ScenceChangeTh3,
+    ContentSmooth1,
+    ContentSmooth2,
+    ContentSmooth3,
+    MiddleRegionGain1,
+    MiddleRegionGain2,
+    BlackRegionGain1,
+    BlackRegionGain2,
+    BlackRegionRange,
+    BlackEffectLevel,
+    BlackEffectParam1,
+    BlackEffectParam2,
+    BlackEffectParam3,
+    BlackEffectParam4,
+    WhiteRegionGain1,
+    WhiteRegionGain2,
+    WhiteRegionRange,
+    WhiteEffectLevel,
+    WhiteEffectParam1,
+    WhiteEffectParam2,
+    WhiteEffectParam3,
+    WhiteEffectParam4,
+    ContrastAdjust1,
+    ContrastAdjust2,
+    DCChangeSpeedLevel,
+    ProtectRegionEffect,
+    DCChangeSpeedLevel2,
+    ProtectRegionWeight,
+    DCEnable
+} PQ_DC_index_t;
+
+typedef struct {
+
+    int param[40];
+
+} DISP_PQ_DC_PARAM;
+
+
+// OD
+typedef struct {
+    unsigned int size;
+    unsigned int type;
+    unsigned int ret;
+    unsigned int param0;
+    unsigned int param1;
+    unsigned int param2;
+    unsigned int param3;
+} DISP_OD_CMD;
+
+typedef enum
+{
+    DISP_INTERLACE_FORMAT_NONE,
+    DISP_INTERLACE_FORMAT_TOP_FIELD,
+    DISP_INTERLACE_FORMAT_BOTTOM_FIELD
+}DISP_INTERLACE_FORMAT;
+
+#define DISP_IOCTL_MAGIC        'x'
+
+#define DISP_IOCTL_WRITE_REG       _IOW     (DISP_IOCTL_MAGIC, 1, DISP_WRITE_REG)   // also defined in atci_pq_cmd.h
+#define DISP_IOCTL_READ_REG        _IOWR    (DISP_IOCTL_MAGIC, 2, DISP_READ_REG)    // also defined in atci_pq_cmd.h
+//#define DISP_IOCTL_WAIT_IRQ        _IOR     (DISP_IOCTL_MAGIC, 3, disp_wait_irq_struct)
+#define DISP_IOCTL_DUMP_REG        _IOR     (DISP_IOCTL_MAGIC, 4, int)
+#define DISP_IOCTL_LOCK_THREAD     _IOR     (DISP_IOCTL_MAGIC, 5, int)
+#define DISP_IOCTL_UNLOCK_THREAD   _IOR     (DISP_IOCTL_MAGIC, 6, int)
+#define DISP_IOCTL_MARK_CMQ        _IOR     (DISP_IOCTL_MAGIC, 7, int)
+#define DISP_IOCTL_WAIT_CMQ        _IOR     (DISP_IOCTL_MAGIC, 8, int)
+#define DISP_IOCTL_SYNC_REG        _IOR     (DISP_IOCTL_MAGIC, 9, int)
+
+#define DISP_IOCTL_LOCK_MUTEX      _IOW     (DISP_IOCTL_MAGIC, 20, int)
+#define DISP_IOCTL_UNLOCK_MUTEX    _IOR     (DISP_IOCTL_MAGIC, 21, int)
+
+#define DISP_IOCTL_LOCK_RESOURCE   _IOW     (DISP_IOCTL_MAGIC, 25, int)
+#define DISP_IOCTL_UNLOCK_RESOURCE _IOR     (DISP_IOCTL_MAGIC, 26, int)
+
+#define DISP_IOCTL_SET_INTR        _IOR     (DISP_IOCTL_MAGIC, 10, int)
+#define DISP_IOCTL_TEST_PATH       _IOR     (DISP_IOCTL_MAGIC, 11, int)
+
+#define DISP_IOCTL_CLOCK_ON        _IOR     (DISP_IOCTL_MAGIC, 12, int)
+#define DISP_IOCTL_CLOCK_OFF       _IOR     (DISP_IOCTL_MAGIC, 13, int)
+
+#define DISP_IOCTL_RUN_DPF         _IOW     (DISP_IOCTL_MAGIC, 30, int)
+#define DISP_IOCTL_CHECK_OVL       _IOR     (DISP_IOCTL_MAGIC, 31, int)
+#define DISP_IOCTL_GET_OVL         _IOWR    (DISP_IOCTL_MAGIC, 32, DISP_OVL_INFO)
+
+#define DISP_IOCTL_EXEC_COMMAND    _IOW     (DISP_IOCTL_MAGIC, 33, DISP_EXEC_COMMAND)
+#define DISP_IOCTL_RESOURCE_REQUIRE   _IOR     (DISP_IOCTL_MAGIC, 34, int)
+
+//Add for AAL control - S
+//0 : disable AAL event, 1 : enable AAL event
+#define DISP_IOCTL_AAL_EVENTCTL    _IOW    (DISP_IOCTL_MAGIC, 15 , int)
+//Get AAL statistics data.
+#define DISP_IOCTL_AAL_GET_HIST    _IOR    (DISP_IOCTL_MAGIC, 16 , DISP_AAL_HIST)
+//Update AAL setting
+#define DISP_IOCTL_AAL_SET_PARAM   _IOW    (DISP_IOCTL_MAGIC, 17 , DISP_AAL_PARAM)
+#define DISP_IOCTL_AAL_INIT_REG    _IOW    (DISP_IOCTL_MAGIC, 18 , DISP_AAL_INITREG)
+#define DISP_IOCTL_SET_GAMMALUT    _IOW    (DISP_IOCTL_MAGIC, 23 , DISP_GAMMA_LUT_T)
+#define DISP_IOCTL_SET_CCORR       _IOW    (DISP_IOCTL_MAGIC, 24 , DISP_CCORR_COEF_T)
+
+
+//Add for AAL control - E
+/*-----------------------------------------------------------------------------
+    DDP Kernel Mode API  (for Kernel Trap)
+  -----------------------------------------------------------------------------*/
+//DDPK Bitblit
+//#define DISP_IOCTL_G_WAIT_REQUEST  _IOR     (DISP_IOCTL_MAGIC , 40 , DDPIOCTL_DdpkBitbltConfig)
+//#define DISP_IOCTL_T_INFORM_DONE   _IOW     (DISP_IOCTL_MAGIC , 41 , DDPIOCTL_DdpkBitbltInformDone)
+
+#define DISP_IOCTL_SET_CLKON        _IOW    (DISP_IOCTL_MAGIC, 50 , DISP_MODULE_ENUM)
+#define DISP_IOCTL_SET_CLKOFF       _IOW    (DISP_IOCTL_MAGIC, 51 , DISP_MODULE_ENUM)
+
+#define DISP_IOCTL_MUTEX_CONTROL    _IOW    (DISP_IOCTL_MAGIC, 55 , int)    // also defined in atci_pq_cmd.h
+#define DISP_IOCTL_GET_LCMINDEX     _IOR    (DISP_IOCTL_MAGIC, 56 , int)
+
+// PQ setting
+#define DISP_IOCTL_SET_PQPARAM      _IOW    (DISP_IOCTL_MAGIC, 60 , DISP_PQ_PARAM)
+#define DISP_IOCTL_GET_PQPARAM      _IOR    (DISP_IOCTL_MAGIC, 61 , DISP_PQ_PARAM)
+#define DISP_IOCTL_GET_PQINDEX      _IOR    (DISP_IOCTL_MAGIC, 63,  DISPLAY_PQ_T)
+#define DISP_IOCTL_SET_PQINDEX      _IOW    (DISP_IOCTL_MAGIC, 64 , DISPLAY_PQ_T)
+#define DISP_IOCTL_SET_TDSHPINDEX   _IOW    (DISP_IOCTL_MAGIC, 65 , DISPLAY_TDSHP_T)
+#define DISP_IOCTL_GET_TDSHPINDEX   _IOR    (DISP_IOCTL_MAGIC, 66 , DISPLAY_TDSHP_T)
+#define DISP_IOCTL_SET_PQ_CAM_PARAM _IOW    (DISP_IOCTL_MAGIC, 67 , DISP_PQ_PARAM)
+#define DISP_IOCTL_GET_PQ_CAM_PARAM _IOR    (DISP_IOCTL_MAGIC, 68 , DISP_PQ_PARAM)
+#define DISP_IOCTL_SET_PQ_GAL_PARAM _IOW    (DISP_IOCTL_MAGIC, 69 , DISP_PQ_PARAM)
+#define DISP_IOCTL_GET_PQ_GAL_PARAM _IOR    (DISP_IOCTL_MAGIC, 70 , DISP_PQ_PARAM)
+
+#define DISP_IOCTL_PQ_SET_BYPASS_COLOR  _IOW    (DISP_IOCTL_MAGIC, 71 , int)
+#define DISP_IOCTL_PQ_SET_WINDOW    _IOW    (DISP_IOCTL_MAGIC, 72 , DISP_PQ_WIN_PARAM)
+#define DISP_IOCTL_PQ_GET_TDSHP_FLAG    _IOR    (DISP_IOCTL_MAGIC, 73 , int)
+#define DISP_IOCTL_PQ_SET_TDSHP_FLAG    _IOW    (DISP_IOCTL_MAGIC, 74 , int)
+#define DISP_IOCTL_PQ_GET_DC_PARAM  _IOR    (DISP_IOCTL_MAGIC, 75, DISP_PQ_DC_PARAM)
+#define DISP_IOCTL_PQ_SET_DC_PARAM  _IOW    (DISP_IOCTL_MAGIC, 76, DISP_PQ_DC_PARAM)
+#define DISP_IOCTL_WRITE_SW_REG     _IOW    (DISP_IOCTL_MAGIC, 77, DISP_WRITE_REG)   // also defined in atci_pq_cmd.h
+#define DISP_IOCTL_READ_SW_REG      _IOWR   (DISP_IOCTL_MAGIC, 78, DISP_READ_REG)    // also defined in atci_pq_cmd.h
+
+// OD
+#define DISP_IOCTL_OD_CTL           _IOWR    (DISP_IOCTL_MAGIC, 80 , DISP_OD_CMD)
+
+// OVL
+#define DISP_IOCTL_OVL_ENABLE_CASCADE  _IOW    (DISP_IOCTL_MAGIC, 90 , int)
+#define DISP_IOCTL_OVL_DISABLE_CASCADE  _IOW    (DISP_IOCTL_MAGIC, 91 , int)
+// PQ setting
+#define DISP_IOCTL_PQ_GET_DS_PARAM _IOR      (DISP_IOCTL_MAGIC, 100, DISP_PQ_DS_PARAM)
+#define DISP_IOCTL_PQ_GET_MDP_COLOR_CAP _IOR (DISP_IOCTL_MAGIC, 101, MDP_COLOR_CAP)
+#define DISP_IOCTL_PQ_GET_MDP_TDSHP_REG _IOR (DISP_IOCTL_MAGIC, 102, MDP_TDSHP_REG)
+#endif
diff --git a/kernel-headers/ddp_gamma.h b/kernel-headers/ddp_gamma.h
new file mode 100644
index 0000000..484bf27
--- /dev/null
+++ b/kernel-headers/ddp_gamma.h
@@ -0,0 +1,35 @@
+#ifndef __DDP_GAMMA_H__
+#define __DDP_GAMMA_H__
+
+//#include <asm/uaccess.h>
+
+
+typedef enum {
+    DISP_GAMMA0 = 0,
+    DISP_GAMMA_TOTAL
+} disp_gamma_id_t;
+
+
+typedef unsigned int gamma_entry;
+#define GAMMA_ENTRY(r10, g10, b10) (((r10) << 20) | ((g10) << 10) | (b10))
+
+#define DISP_GAMMA_LUT_SIZE 512
+
+typedef struct {
+    disp_gamma_id_t hw_id;
+    gamma_entry lut[DISP_GAMMA_LUT_SIZE];
+} DISP_GAMMA_LUT_T;
+
+
+typedef enum {
+    DISP_CCORR0 = 0,
+    DISP_CCORR_TOTAL
+} disp_ccorr_id_t;
+
+typedef struct {
+    disp_ccorr_id_t hw_id;
+    unsigned int coef[3][3];
+} DISP_CCORR_COEF_T;
+
+#endif
+
diff --git a/kernel-headers/ddp_hal.h b/kernel-headers/ddp_hal.h
new file mode 100644
index 0000000..ebb3ceb
--- /dev/null
+++ b/kernel-headers/ddp_hal.h
@@ -0,0 +1,125 @@
+#ifndef _H_DDP_HAL_
+#define _H_DDP_HAL_
+
+/* DISP Mutex */
+#define DISP_MUTEX_TOTAL      (10)
+#define DISP_MUTEX_DDP_FIRST  (0)
+#define DISP_MUTEX_DDP_LAST   (4)
+#define DISP_MUTEX_DDP_COUNT  (5)
+#define DISP_MUTEX_MDP_FIRST  (5)
+#define DISP_MUTEX_MDP_COUNT  (5)
+
+/* DISP MODULE */
+typedef enum
+{    
+    DISP_MODULE_OVL0  ,
+    DISP_MODULE_OVL1  ,
+    DISP_MODULE_RDMA0 ,
+    DISP_MODULE_RDMA1 ,
+    DISP_MODULE_WDMA0 ,
+    DISP_MODULE_COLOR0,
+    DISP_MODULE_CCORR ,
+    DISP_MODULE_AAL   ,
+    DISP_MODULE_GAMMA ,
+    DISP_MODULE_DITHER,
+    DISP_MODULE_UFOE  , //10
+    DISP_MODULE_PWM0   ,
+    DISP_MODULE_WDMA1 ,
+    DISP_MODULE_DSI0  ,
+    DISP_MODULE_DPI   ,
+    DISP_MODULE_SMI,
+    DISP_MODULE_CONFIG,
+    DISP_MODULE_CMDQ,
+    DISP_MODULE_MUTEX,	
+
+    DISP_MODULE_COLOR1,
+    DISP_MODULE_RDMA2,
+    DISP_MODULE_PWM1,
+    DISP_MODULE_OD,
+    DISP_MODULE_MERGE,
+    DISP_MODULE_SPLIT0,
+    DISP_MODULE_SPLIT1,
+    DISP_MODULE_DSI1,
+    DISP_MODULE_DSIDUAL,    
+
+	DISP_MODULE_SMI_LARB0 ,
+    DISP_MODULE_SMI_COMMON,
+    DISP_MODULE_UNKNOWN, //20
+    DISP_MODULE_NUM
+} DISP_MODULE_ENUM;
+
+typedef enum
+{
+    DISP_REG_OVL0   ,
+    DISP_REG_OVL1   ,
+    DISP_REG_RDMA0  ,
+    DISP_REG_RDMA1  ,
+    DISP_REG_WDMA0  ,
+    DISP_REG_COLOR  ,
+    DISP_REG_CCORR  ,
+    DISP_REG_AAL    ,
+    DISP_REG_GAMMA  ,
+    DISP_REG_DITHER ,
+    DISP_REG_UFOE   ,
+    DISP_REG_PWM    ,
+    DISP_REG_WDMA1  ,
+    DISP_REG_MUTEX  ,
+    DISP_REG_DSI0   ,
+    DISP_REG_DPI0   ,
+    DISP_REG_CONFIG ,
+    DISP_REG_SMI_LARB0 ,
+    DISP_REG_SMI_COMMON,
+    DISP_REG_MIPI   ,
+    DISP_REG_CONFIG2 ,
+    DISP_REG_CONFIG3 ,
+    DISP_REG_IO_DRIVING,
+    DISP_TVDPLL_CFG6,
+    DISP_TVDPLL_CON0,
+    DISP_TVDPLL_CON1,
+    DISP_REG_NUM
+} DISP_REG_ENUM;
+
+typedef enum {
+    SOF_SINGLE = 0,
+    SOF_DSI0,
+    SOF_DSI1,
+    SOF_DPI0,
+} MUTEX_SOF;  
+
+enum OVL_LAYER_SOURCE {
+    OVL_LAYER_SOURCE_MEM    = 0,
+    OVL_LAYER_SOURCE_RESERVED = 1,
+    OVL_LAYER_SOURCE_SCL     = 2,
+    OVL_LAYER_SOURCE_PQ     = 3,
+};
+
+enum OVL_LAYER_SECURE_MODE {
+    OVL_LAYER_NORMAL_BUFFER    = 0,
+    OVL_LAYER_SECURE_BUFFER    = 1,
+    OVL_LAYER_PROTECTED_BUFFER = 2
+};
+
+typedef enum
+{
+    CMDQ_DISABLE = 0,
+    CMDQ_ENABLE
+}CMDQ_SWITCH;
+
+typedef enum
+{
+    CMDQ_BEFORE_STREAM_SOF,
+    CMDQ_WAIT_STREAM_EOF_EVENT,
+    CMDQ_CHECK_IDLE_AFTER_STREAM_EOF,
+    CMDQ_AFTER_STREAM_EOF,
+    CMDQ_ESD_CHECK_READ,
+    CMDQ_ESD_CHECK_CMP,    
+    CMDQ_ESD_ALLC_SLOT,
+    CMDQ_ESD_FREE_SLOT,
+    CMDQ_STOP_VDO_MODE,
+    CMDQ_START_VDO_MODE,
+    CMDQ_DSI_RESET
+}CMDQ_STATE;
+
+
+
+#endif
diff --git a/kernel-headers/ddp_ovl.h b/kernel-headers/ddp_ovl.h
new file mode 100644
index 0000000..01f0f44
--- /dev/null
+++ b/kernel-headers/ddp_ovl.h
@@ -0,0 +1,17 @@
+#ifndef _DDP_OVL_H_
+#define _DDP_OVL_H_
+#include "ddp_hal.h"
+#include "ddp_data_type.h"
+
+#define OVL_CASCADE_SUPPORT
+#define OVL_MAX_WIDTH  (4095)
+#define OVL_MAX_HEIGHT (4095)
+#ifdef OVL_CASCADE_SUPPORT
+#define OVL_LAYER_NUM  (8)
+#else
+#define OVL_LAYER_NUM  (4)
+#endif
+
+#define OVL_LAYER_NUM_PER_OVL 4
+
+#endif
diff --git a/kernel-headers/disp_event.h b/kernel-headers/disp_event.h
new file mode 100644
index 0000000..e97ecf8
--- /dev/null
+++ b/kernel-headers/disp_event.h
@@ -0,0 +1,19 @@
+#ifndef __DISP_EVENT_H__
+#define __DISP_EVENT_H__
+
+typedef enum{
+	DISP_PATH_EVENT_FRAME_DONE = 0,
+	DISP_PATH_EVENT_FRAME_START,
+	DISP_PATH_EVENT_FRAME_REG_UPDATE,
+	DISP_PATH_EVENT_FRAME_TARGET_LINE,
+	DISP_PATH_EVENT_FRAME_COMPLETE,
+	DISP_PATH_EVENT_FRAME_STOP,
+	DISP_PATH_EVENT_IF_CMD_DONE,
+	DISP_PATH_EVENT_IF_VSYNC,
+	DISP_PATH_EVENT_TRIGGER,
+	DISP_PATH_EVENT_AAL_OUT_END_FRAME,
+	DISP_PATH_EVENT_NUM,
+	DISP_PATH_EVENT_NONE = 0xff,
+}DISP_PATH_EVENT;
+
+#endif
diff --git a/kernel-headers/errata.h b/kernel-headers/errata.h
new file mode 100644
index 0000000..61998a4
--- /dev/null
+++ b/kernel-headers/errata.h
@@ -0,0 +1,41 @@
+#ifndef ERRATA_H
+#define ERRATA_H
+
+#define SAFE_READ(x) \
+    __asm__ __volatile__( \
+    "nop\n" \
+    "nop\n" \
+    "nop\n" \
+    "nop\n" \
+    "nop\n" \
+    "nop\n" \
+    "nop\n" \
+    "nop\n" \
+    "nop\n" \
+    ); \
+    x; \
+    __asm__ __volatile__( \
+    "nop\n" \
+    );
+
+#define SAFE_HEAD \
+    { \
+    __asm__ __volatile__( \
+    "nop\n" \
+    "nop\n" \
+    "nop\n" \
+    "nop\n" \
+    "nop\n" \
+    "nop\n" \
+    "nop\n" \
+    "nop\n" \
+    "nop\n" \
+    ); \
+
+#define SAFE_TAIL \
+    __asm__ __volatile__( \
+    "nop\n" \
+    ); \
+    }
+
+#endif
diff --git a/kernel-headers/hevcd_if.h b/kernel-headers/hevcd_if.h
index 871e45a..871e45a 100644..100755
--- a/kernel-headers/hevcd_if.h
+++ b/kernel-headers/hevcd_if.h
diff --git a/kernel-headers/jpeg_drv.h b/kernel-headers/jpeg_drv.h
new file mode 100644
index 0000000..5699235
--- /dev/null
+++ b/kernel-headers/jpeg_drv.h
@@ -0,0 +1,677 @@
+#include <linux/ioctl.h>                                                                       
+                                                                                               
+#ifndef __JPEG_DRV_H__                                                                         
+#define __JPEG_DRV_H__                                                                         
+
+
+
+#define TO_CEIL(x,a) ( ((x) + ((a)-1)) & ~((a)-1) )
+#define TO_FLOOR(x,a) ( (x) & ~((a)-1) )
+#define TO_MASK(x,a) ( (x) & (a) )
+
+#define DUNUM_MAPPING(value) (((value)-1)&0x3)
+                                                                                                               
+                                                                                           
+                                                                                                               
+typedef struct                                                                                                 
+{                                                                                                              
+    long timeout;                                                                                              
+    unsigned int *result;                                                                                      
+                                                                                                               
+}JPEG_DEC_DRV_OUT;                                                                                             
+
+
+//===========================================================================================
+
+
+
+
+#define MAX_JPEG_COMPONENT	     4
+#define MAX_NUM_SCAN		        32
+
+#define D_MAX_JPEG_HW_COMP		   3
+//#define D_MAX_JPEG_HUFF_TBL		 4
+#define D_MAX_JPEG_QTBL			     4
+#define D_MAX_JPEG_HW_QTBL		   2
+#define D_MAX_JPEG_BLOCK_NUM		10
+#define D_HUFF_LOOKAHEAD_BITS	   6	   /* # of bits of lookahead */
+
+#define D_DCTSIZE				         8
+#define D_JPEG_DRAM_ALIGN_MASK	0xf
+#define D_JPEG_DRAM_ALIGN_SIZE	(D_JPEG_DRAM_ALIGN_MASK + 1)
+
+#define D_JPEG_BASELINE			0
+#define D_JPEG_DC_REFINE		1
+#define D_JPEG_AC_FIRST			2
+#define D_JPEG_AC_REFINE		3
+#define D_JPEG_DC_FIRST			4
+
+/* global data check flags */
+#define D_FLAG_NONE				(0)
+
+#define D_GLOB_PROGRESSIVE		(1 << 0)
+#define D_GLOB_NCOMP			(1 << 1)
+#define D_GLOB_BLK_W			(1 << 2)
+#define D_GLOB_BLK_H			(1 << 3)
+#define D_GLOB_PIC_W			(1 << 4)
+#define D_GLOB_PIC_H			(1 << 5)
+#define D_GLOB_DCHUFF			(1 << 6)	/* no need */
+#define D_GLOB_ACHUFF			(1 << 7)	/* no need */
+#define D_GLOB_NZBUFF			(1 << 8)	/* no need */
+#define D_GLOB_QTBL				(1 << 9)	/* no need */
+#define D_GLOB_RESTART			(1 << 10)
+/* scan data check flags */
+#define D_SCAN_DATASTART		(1 << 0)
+#define D_SCAN_NCOMP			(1 << 1)
+#define D_SCAN_COMPIN			(1 << 2)
+#define D_SCAN_COMPQ			(1 << 3)
+#define D_SCAN_BLKDC			(1 << 4)
+#define D_SCAN_BLKAC			(1 << 5)
+#define D_SCAN_ALAH				(1 << 6)
+#define D_SCAN_SESS				(1 << 7)
+#define D_SCAN_LAST				(1 << 8)
+#define D_SCAN_ROWSTART			(1 << 9)
+#define D_SCAN_ROWEND			(1 << 10)
+#define D_SCAN_DCHUFF			(1 << 11)
+#define D_SCAN_ACHUFF			(1 << 12)
+#define D_SCAN_QTBL				(1 << 13)
+#define D_SCAN_NZBUFF			(1 << 14)
+/* mcu row check flags */
+#define D_ROW_CURR				(1 << 0)
+#define D_ROW_OUTBUF			(1 << 1)
+#define D_ROW_OUTBUFSIZE		(1 << 2)
+/* mcu check flags */
+#define D_MCU_OUTADDR			(1 << 0)
+#define D_MCU_COEFADDR			(1 << 1)
+/* misc check flags */
+#define D_MISC_ADDR_X			(1 << 0)
+#define D_MISC_ADDR_Y			(1 << 1)
+
+
+#define M_JPEG_INTERFACE_START() \
+	int				i4Ret = (int)E_HWJPG_OK;
+
+#define M_JPEG_INTERFACE_END() \
+	return i4Ret
+
+
+#define HORI 0
+#define VERT 1
+
+#define JPEG_ENC_DST_ADDR_OFFSET_MASK (0x0f)
+
+
+
+
+
+typedef enum _ENUM_JPEG_RET_CODE_T
+{
+	E_JPG_OK,
+	E_JPG_ERR_NONFATAL,
+	E_JPG_ERR_FATAL,
+	E_JPG_ERR_PARAM,
+	E_JPG_ERR_NOT_INITED,
+	E_JPG_ERR_ALREADY, //5
+	/* markers */
+	E_JPG_ERR_NOT_JPEG_IMAGE,
+	E_JPG_ERR_NOT_A_MARKER,
+	E_JPG_ERR_PASS_END,
+	E_JPG_ERR_MULTI_SOI,
+	E_JPG_ERR_UNSUPPORT_SOF, //10
+	E_JPG_ERR_MULTI_SOF,
+	E_JPG_ERR_INVALID_SOF,
+	E_JPG_ERR_SOS_BEFORE_SOF,
+	E_JPG_ERR_INVALID_SOS,
+	E_JPG_ERR_INVALID_DHT, //15
+	E_JPG_ERR_INVALID_DRI,
+	E_JPG_ERR_MULTI_APP1,
+	E_JPG_ERR_INVALID_APP0,
+	E_JPG_ERR_INVALID_APP1,
+	E_JPG_ERR_PARSE_FAILED, //20
+	E_JPG_ERR_NOT_PARSED,
+	E_JPG_ERR_MULTI_EOI,
+	/* instances */
+	E_JPG_ERR_ALLOC_PARSER,
+	E_JPG_ERR_ALLOC_DECODER,
+	E_JPG_ERR_ALLOC_MEM, //25
+	E_JPG_ERR_ALLOC_FLOW,
+	/* general */
+	E_JPG_ERR_UNSUPPORT,
+	E_JPG_ERR_GENERAL,
+	E_JPG_ERR_LAST,
+	E_JPG_ERR_DISPLAY_ADDR, //30
+	E_JPG_ERR_INVALID_COMPONENT	//code sync
+} JpegDecRetCode;
+
+
+typedef enum 
+{
+	E_HWJPG_OK = 0,
+	E_HWJPG_BUSY,
+
+	E_HWJPG_ERR_FETCH_TIMEOIT = E_JPG_ERR_LAST + 1,
+	E_HWJPG_ERR_SET_BS,
+	E_HWJPG_ERR_LOAD_Q,
+	E_HWJPG_ERR_QTBL_INDEX,
+	E_HWJPG_ERR_QTBL_NUM,
+
+	E_HWJPG_ERR_PARAM,
+	E_HWJPG_ERR_TIMEOUT,
+
+	E_HWJPG_ERR_COMP_RANGE,
+	E_HWJPG_ERR_TBL_RANGE,
+	E_HWJPG_ERR_BLOCK,
+	E_HWJPG_ERR_SIZE,
+	E_HWJPG_ERR_OUTBUF,
+
+	E_HWJPG_ERR_NULL_SCAN,
+
+	E_HWJPG_ERR_GLOB_NOT_READY,
+	E_HWJPG_ERR_SCAN_NOT_READY,
+	E_HWJPG_ERR_ROW_NOT_READY,
+	E_HWJPG_ERR_MCU_NOT_READY,
+	E_HWJPG_ERR_MISC_NOT_READY,
+	E_HWJPG_ERR_HUFF_ADDR,
+	/* last */
+	E_HWJPG_ERR_GENERAL
+} JpegDrvDecRetCode;
+
+
+typedef enum
+{
+    JDEC_HAL_DEC_MODE_NONE,
+    JDEC_HAL_DEC_MODE_BASELINE_PIC,                        ///< Jpeg baseline picture, decode whole picture
+    JDEC_HAL_DEC_MODE_BASELINE_MCU,                        ///< Jpeg baseline picture, decode MCU row
+    JDEC_HAL_DEC_MODE_BASELINE_MCU_ROW,                    ///< Jpeg baseline picture, decode MCU
+    JDEC_HAL_DEC_MODE_BASELINE_VIDEO_OUTPUT,               
+    JDEC_HAL_DEC_MODE_PROGRESSIVE_MCU_MULTI_COLLECT,       ///< Jpeg progressive picture, decode MCU milti-collect
+    JDEC_HAL_DEC_MODE_PROGRESSIVE_MCU_ENHANCE,             ///< Jpeg progressive picture, decode MCU enhance decoding
+    JDEC_HAL_DEC_MODE_PROGRESSIVE_MCU_ROW_MULTI_COLLECT,   ///Jpeg progressive MCU-Row Mode
+    JDEC_HAL_DEC_MODE_PROGRESSIVE_MCU_ROW_ENHANCE,
+    JDEC_HAL_DEC_MODE_PROGRESSIVE_SCAN_MULTI_COLLECT,
+    JDEC_HAL_DEC_MODE_PROGRESSIVE_SCAN_ENHANCE
+} JpegDrvDecMode;
+
+/* jpeg format */
+typedef enum _JpegDecFormat
+{
+	E_JPG_UNKNOWN_FORMAT,
+	E_JPG_BASELINE,
+	E_JPG_EX_SEQ_HUFFMAN,
+	E_JPG_PROGRESSIVE_HUFFMAN,
+	E_JPG_EX_SEQ_ARITHMETIC,
+	E_JPG_PROGRESSIVE_ARITHMETIC,
+	E_JPG_LOSSLESS_HUFFMAN,
+	E_JPG_DIFFERENTIAL_SEQ_HUFFMAN,
+	E_JPG_DIFF_PROG_HUFFMAN,
+	E_JPG_DIFF_LLESS_HUFFMAN,
+	E_JPG_RESERVED_FOR_EXTENSIONS,
+	E_JPG_LOSSLESS_ARITHMETIC,
+	E_JPG_DIFF_SEQ_ARITHMETIC,
+	E_JPG_DIFF_PROG_ARITHMETIC,
+	E_JPG_UNSUPPORT_FORMAT
+} JpegDecFormat;
+
+
+/* component info in SOF marker */
+typedef struct _JpegDecSOFComp
+{
+	unsigned char		u1CompId;
+	unsigned char		u1HSampFactor;
+	unsigned char		u1VSampFactor;
+	unsigned char		u1QuantTblNo;
+} JpegDecSOFComp;
+
+typedef struct _JpegDecSOS
+{
+	unsigned int		 u4ScanPass;			/* scan pass */
+	unsigned char		 u1CompInScan;
+	unsigned char		 au1CompNoList[MAX_JPEG_COMPONENT];
+	unsigned char		 au1DcId[MAX_JPEG_COMPONENT];
+	unsigned char		 au1AcId[MAX_JPEG_COMPONENT];
+ 	unsigned char    u1Ss, u1Se, u1Ah, u1Al, u1AhAl;        /* OT: NO USE */
+	unsigned char*   pu1ScanTableStart;
+	unsigned char*   pu1ScanDataStart;
+} JpegDecSOS;
+
+
+/* raw de-huffman table */
+typedef struct
+{
+	unsigned char au1Bits[17];
+	unsigned char au1HuffVal[256];
+} JpegDecDhtHuffTbl;
+
+
+
+/* SOF data */
+typedef struct _JpegDecSOF
+{
+	int 					      fgSOF;	         /* indicate that already have an SOF marker */
+	JpegDecFormat   		eJpegFormat;
+	unsigned char			  u1DataPrecision;
+	unsigned short			u2ImageHeight;
+	unsigned short			u2ImageWidth;
+	unsigned char			  u1NumComponents;
+	unsigned char			  au1MapId2Index[256];
+	JpegDecSOFComp			arSofComp[MAX_JPEG_COMPONENT];
+} JpegDecSOF;
+
+
+
+/* DHT data */
+typedef struct 
+{
+	unsigned int			  u4NumDcTbl;
+	unsigned int			  u4NumAcTbl;
+	unsigned int			  fgDcTblLoaded;     /* bit mask for loaded dc table */
+	unsigned int			  fgAcTblLoaded;     /* bit mask for loaded ac table */
+	JpegDecDhtHuffTbl		arDcTbl[4];
+	JpegDecDhtHuffTbl		arAcTbl[4];
+} JpegDecDHT;
+
+/* DQT data */
+typedef struct
+{
+	/*
+	although we leave 2bytes * 64 space here,
+	if q table precision is 8bits, we use only
+	first half (1x64) of this table
+	*/
+	unsigned char		aau1Qtbl[4][128];
+	unsigned int		afgPrec[4];
+	unsigned char		u1NumQ;
+	unsigned int		fgDQT;
+} JpegDecDQT;
+
+
+/* new types for flw2 (wired) */
+typedef struct 
+{
+    void             *pvFreePoint;           /* OT: NO USE */
+    unsigned int     u4Width;                /* OT: NO USE */
+    unsigned int     u4Height;               /* OT: NO USE */
+    unsigned int     u4McuNumInRow;          /* OT: NO USE */
+    unsigned int     u4McuRows;              /* OT: NO USE */
+    unsigned int     u4TotalMcuNum;          /* OT: NO USE */
+    unsigned int     aau4SampleFactor[3][2]; /* OT: NO USE */
+    unsigned int     au4CompBlock[3];        /* OT: NO USE */
+    unsigned int     au4MaxFactor[2];        /* OT: NO USE */
+    unsigned int     outputBuffer0[3];
+    unsigned int     outputBuffer1[3];                         /* nouse in full frame mode, only use in PauseResume/DirectCouple mode */
+    unsigned int     au1CoffBuffer[3];       /* OT: NO USE */
+    int              fgProgScan;             /* OT: NO USE */
+	  /* temp buffers */
+	  unsigned int     apvNzBuffer[3];         /* OT: NO USE */
+	  
+} JpegDrvDecFlow;
+
+
+
+//// jpeg decode mode
+typedef enum _JpegDecMode
+{
+    JPEG_DEC_MODE_NONE,
+    JPEG_DEC_MODE_FRAME,                   ///< Jpeg baseline picture, decode whole picture
+    JPEG_DEC_MODE_DC_LINK,                 ///< Jpeg baseline picture, decode whole picture
+    JPEG_DEC_MODE_MCU_ROW                 ///< Jpeg baseline picture, decode MCU row
+} JpegDecMode;
+
+
+//// JPEG Decoder Structure
+typedef struct
+{
+
+    /* common */
+    unsigned int    decodeMode;        //OK 
+    unsigned int    reg_OpMode ;       //OK
+    unsigned int    regDecDumpEn;
+	  unsigned int    totalMCU ;         //OK
+	  unsigned int    comp0_DU ;
+
+    unsigned int    membershipList ;   //OK    /* { GRAY, gmcEn, DU9, DU8,..., DU1, DU0} */
+
+    /* for BRZ  (0): 1, (1): 1/2, (2): 1/4, (3): 1/8 */
+    unsigned char   lumaHorDecimate;   //OK 
+    unsigned char   lumaVerDecimate;   //OK
+    unsigned char   cbcrHorDecimate;   //OK
+    unsigned char   cbcrVerDecimate;   //OK
+	  
+    unsigned int    srcStreamAddrBase;     //OK
+    unsigned int    srcStreamSize;         //OK
+    unsigned int    srcStreamAddrWritePtr; //OK 
+                    
+    unsigned int    outputBuffer0[3];    //OK                                                                                                  
+    unsigned int    outputBuffer1[3];    //OK                     /* nouse in full frame mode, only use in PauseResume/DirectCouple mode */ 
+    
+
+    // JPEG component information  
+    unsigned int    componentNum;        //OK  
+    unsigned int    componentID[3];      //OK                 ///< Ci                                                             
+    unsigned int    hSamplingFactor[3];  //OK                 ///< Hi                                                             
+    unsigned int    vSamplingFactor[3];  //OK                 ///< Vi                                                             
+    unsigned int    qTableSelector[3];   //OK                 ///< Tqi   (OT: need this field?) 
+    
+    unsigned int    dma_McuInGroup;       //OK
+    unsigned int    dma_GroupNum ;        //OK
+    unsigned int    dma_LastMcuNum ;      //OK
+    unsigned int    gmcEn ;               //OK
+
+
+    //unsigned int totalMcuRows;         //OK                 ///< number of MCU column in the JPEG file                           
+
+	  unsigned int	  compImgStride[D_MAX_JPEG_HW_COMP];		   //OK           // hSamplingFactor[n] * 8 * mcuPerRow (byte pitch of a component)
+	  unsigned int	  compMemStride[D_MAX_JPEG_HW_COMP];       //OK
+	  unsigned int	  compTileBufStride[D_MAX_JPEG_HW_COMP];		         // hSamplingFactor[n] * 8 * mcuPerRow (byte pitch of a component)
+
+
+    
+    unsigned int    mcuPerRow;            //OK     //move to HAL ///< number of MCU row in the JPEG file                              
+    unsigned int    pauseRow_en;          //OK
+    unsigned int    pauseRowCnt;                   //move to HAL
+    unsigned int    pauseMCU;             //OK
+    unsigned int    tileBufRowNum ;               //move to HAL
+    unsigned int    buffer_Y_PA ;                  //move to HAL
+    unsigned int    buffer_Cb_PA;                  //move to HAL
+    unsigned int    buffer_Cr_PA;                  //move to HAL
+    unsigned int    buffer_Y_row_size ;            //move to HAL
+    unsigned int    buffer_C_row_size ;            //move to HAL
+
+                                                                                                                    
+    //unsigned int compDU[3];           //OK                 ///< (required by HW decoder) number of DU for each component        
+    //unsigned int duPerMCURow[3];       //OK                 ///< (required by HW decoder) DU per MCU row for each component      (MT6589_NOUSE)
+    //unsigned int dummyDU[3];           //OK                 ///< (required by HW decoder) number of dummy DU for each component  (MT6589_NOUSE) 
+    //unsigned int samplingFormat;       //OK                 /// how many format?     
+                                                                           
+
+
+
+}JPEG_DEC_DRV_IN;
+
+
+
+
+
+typedef struct 
+{
+    unsigned int    decRowBuf[3];    //OK
+    unsigned int    pauseMCU;             //OK
+
+
+}JPEG_DEC_CONFIG_ROW; 
+
+
+
+typedef struct 
+{
+    unsigned int    goNum; 
+    unsigned int    pauseMCUidx[64]; 
+    unsigned int    decRowBuf0[64]; 
+    unsigned int    decRowBuf1[64]; 
+    unsigned int    decRowBuf2[64]; 
+
+
+}JPEG_DEC_CONFIG_CMDQ; 
+
+
+
+
+typedef struct 
+{
+    // from mt6575 
+    unsigned int srcStreamAddrBase;                                                                                
+    unsigned int srcStreamSize;    
+    unsigned int srcStreamAddrWritePtr;                                                                            
+    
+    unsigned int outputBuffer0[3];
+    unsigned int outputBuffer1[3];                         /* nouse in full frame mode, only use in PauseResume/DirectCouple mode */    
+                                                                                                               
+    unsigned int mcuPerRow;                  ///< number of MCU row in the JPEG file                              
+    unsigned int totalMcuRows;               ///< number of MCU column in the JPEG file                           
+                                                                                                               
+    unsigned int compDU[3];              ///< (required by HW decoder) number of DU for each component        
+    unsigned int duPerMCURow[3];          ///< (required by HW decoder) DU per MCU row for each component      (MT6589_NOUSE)
+    unsigned int dummyDU[3];              ///< (required by HW decoder) number of dummy DU for each component  (MT6589_NOUSE)
+                                                                                                               
+    unsigned int samplingFormat;          /// how many format?                                                                      
+                                                                                                               
+    // JPEG component information                                                                              
+    unsigned int  componentNum;                                                                                
+    unsigned int  componentID[3];          ///< Ci                                                             
+    unsigned int  hSamplingFactor[3];      ///< Hi                                                             
+    unsigned int  vSamplingFactor[3];      ///< Vi                                                             
+    unsigned int  qTableSelector[3];       ///< Tqi   (OT: need this field?) 
+
+/*********************************************************************************/
+
+    /* common */
+	  unsigned int    totalMCU ;
+	  unsigned char	  blkNumInMCU;          //total drv no use
+
+	  unsigned char   u1MaxHorSample, u1MaxVerSample;			        // widest, highest
+	  unsigned int	  u4PicWidth, u4PicHeight;				            // picture width and height
+	  unsigned int	  compImgStride[D_MAX_JPEG_HW_COMP];		      // hSamplingFactor[n] * 8 * mcuPerRow (byte pitch of a component)
+	  unsigned int	  compTileBufStride[D_MAX_JPEG_HW_COMP];		      // hSamplingFactor[n] * 8 * mcuPerRow (byte pitch of a component)
+    unsigned int    au4PicWidthInBuf[D_MAX_JPEG_HW_COMP];    
+    
+
+	  // use only in look ahead table
+	  unsigned char	  au1MemberShip[D_MAX_JPEG_BLOCK_NUM];		// DU mapping to components
+	  unsigned char	  aau1Qtbl[D_MAX_JPEG_QTBL][128];				// q tables in stream
+	  unsigned int	  u4RestartInterval;
+	  
+	  /* current scan */
+	  unsigned char   u1NumCompsInCurrScan;					            // number of components in current scan
+	  int             afgCompInScan[D_MAX_JPEG_HW_COMP + 1];
+	  //unsigned char   qTableSelector[D_MAX_JPEG_HW_COMP];
+	  unsigned char   au1BlkDc[D_MAX_JPEG_BLOCK_NUM];
+	  unsigned char   au1BlkAc[D_MAX_JPEG_BLOCK_NUM];
+    unsigned char   u1Se;                          /* OT: NO USE */
+    unsigned char   u1Ss;                          /* OT: NO USE */
+    
+	  /* current mcu row */
+	  unsigned int	  u4CurrMcuRow;
+    unsigned int    u4ModTotalRows;
+    
+	  
+	  /* for single component in p scan */
+	  unsigned char	  u1FirstCompInScan;   
+	  
+    /* for BRZ */
+    unsigned char   lumaHorDecimate;      //(0): 1, (1): 1/2, (2): 1/4, (3): 1/8
+    unsigned char   lumaVerDecimate;
+    unsigned char   cbcrHorDecimate;
+    unsigned char   cbcrVerDecimate;
+    unsigned int    srcColorFormat;
+    unsigned int    dstColorFormat;
+    unsigned int    u4isColorConv;
+    unsigned int    u4ds_width[3] ;
+    unsigned int    u4ds_height[3] ;
+    
+    unsigned int    decodeMode;
+    unsigned int    gdmaBypassEn;
+    unsigned int    regDecDumpEn;
+
+    unsigned int    pauseRow_en;
+    unsigned int    pauseRowCnt;
+    unsigned int    tileBufRowNum ;
+    unsigned int    buffer_Y_PA ;
+    unsigned int    buffer_Cb_PA;
+    unsigned int    buffer_Cr_PA;
+    unsigned int    buffer_Y_row_size ;
+    unsigned int    buffer_C_row_size ;
+  
+} JpegDrvDecConfig;
+
+typedef struct
+{
+    unsigned int *pChksum;  
+} JpegDrvDecResult;
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+//==========================================================================================
+
+
+// JPEG Encoder Structure 
+typedef struct 
+{
+
+    unsigned int dstBufferAddr; 
+    unsigned int dstBufferSize; 
+
+    unsigned int encWidth;    //HW directly fill to header
+    unsigned int encHeight;   //HW directly fill to header
+
+    unsigned char enableEXIF;
+    unsigned char allocBuffer;
+    //unsigned char enableSyncReset;   //not use in mt6589
+
+    unsigned int encQuality; 
+    unsigned int encFormat;
+        
+    //extend in mt6589
+    unsigned int disableGMC;     //TBD: not support
+    unsigned int restartInterval;      
+    unsigned int srcBufferAddr;   // YUV420: Luma 
+    unsigned int srcChromaAddr;    
+    unsigned int imgStride ;
+    unsigned int memStride ;
+    unsigned int totalEncDU ;
+    unsigned int dstBufAddrOffset; 
+    unsigned int dstBufAddrOffsetMask; 
+    
+}JPEG_ENC_DRV_IN; 
+
+
+
+
+
+typedef struct                                                                                                 
+{                                                                                                              
+    long timeout;                                                                                              
+    unsigned int *fileSize;                                                                                    
+    unsigned int *result;
+    unsigned int *cycleCount;                                                                                      
+                                                                                                               
+}JPEG_ENC_DRV_OUT;                                                                                             
+                                                                                                               
+typedef struct {                                                                                               
+    unsigned long startAddr;//In :                                                                             
+    unsigned long size;                                                                                        
+    unsigned long result;// 0 : out of pmem range, 1 : inside pmem range, 2 : partially overlap with pmem range
+} JPEG_PMEM_RANGE;                                                                                             
+
+//====================================================================================
+
+
+typedef struct
+{
+    long timeout;
+    unsigned int *pFileSize;  
+    unsigned int *pResult;
+    unsigned int *pCycleCount;
+    
+} JpegDrvEncResult;
+
+
+
+
+
+
+//typedef struct
+//{
+//    unsigned int srcBufferAddr; // YUV420: Luma 
+//    unsigned int srcChromaAddr;
+//    unsigned int dstBufferAddr;
+//    unsigned int dstBufferSize;
+//    
+//    unsigned int srcWidth;
+//    unsigned int srcHeight;
+//
+//    unsigned char enableEXIF;
+//    unsigned char disableGMC;  //not support
+//
+//    unsigned int restartInterval;    
+//    unsigned int quality;
+//    unsigned int yuvFormat; 
+//
+//} JpegDrvEncParam;
+
+
+
+//======================================================================================
+
+
+
+
+
+
+                                                                                                               
+#define JPEG_IOCTL_MAGIC        'x'                                                                            
+
+#if 0                                                                                                               
+  #define JPEG_DEC_IOCTL_INIT     _IO  (JPEG_IOCTL_MAGIC, 1)                                                     
+  //#define JPEG_DEC_IOCTL_CONFIG   _IOW (JPEG_IOCTL_MAGIC, 2, JPEG_DEC_DRV_IN)                                    
+  #define JPEG_DEC_IOCTL_START    _IO  (JPEG_IOCTL_MAGIC, 3)                                                     
+  #define JPEG_DEC_IOCTL_WAIT     _IOWR(JPEG_IOCTL_MAGIC, 6, JPEG_DEC_DRV_OUT)                                   
+  #define JPEG_DEC_IOCTL_DEINIT   _IO  (JPEG_IOCTL_MAGIC, 8)                                                     
+  //#define JPEG_DEC_IOCTL_RESUME   _IOW(JPEG_IOCTL_MAGIC, 4, JPEG_DEC_RESUME_IN)                                
+  //#define JPEG_DEC_IOCTL_RANGE    _IOWR(JPEG_IOCTL_MAGIC, 5, JPEG_DEC_RANGE_IN)                                
+  //#define JPEG_DEC_IOCTL_COPY     _IOWR(JPEG_IOCTL_MAGIC, 7, int)                                              
+#endif
+
+///////////////////// JPEG DEC IOCTL /////////////////////////////////////
+#define JPEG_DEC_IOCTL_INIT     _IO    (JPEG_IOCTL_MAGIC,  1)
+#define JPEG_DEC_IOCTL_CONFIG   _IOW   (JPEG_IOCTL_MAGIC,  2, JPEG_DEC_DRV_IN)
+#define JPEG_DEC_IOCTL_FLOW     _IOW   (JPEG_IOCTL_MAGIC,  3, JpegDrvDecFlow)
+#define JPEG_DEC_IOCTL_START    _IO    (JPEG_IOCTL_MAGIC,  4)
+#define JPEG_DEC_IOCTL_WAIT     _IOWR  (JPEG_IOCTL_MAGIC,  5, JPEG_DEC_DRV_OUT)
+#define JPEG_DEC_IOCTL_DEINIT   _IO    (JPEG_IOCTL_MAGIC,  6)
+
+#define JPEG_DEC_IOCTL_RESET    _IO    (JPEG_IOCTL_MAGIC,  7)
+#define JPEG_DEC_IOCTL_CHKSUM   _IOWR  (JPEG_IOCTL_MAGIC,  8, JpegDrvDecResult)
+#define JPEG_DEC_IOCTL_BREAK    _IO    (JPEG_IOCTL_MAGIC,  9)
+#define JPEG_DEC_IOCTL_RW_REG   _IO    (JPEG_IOCTL_MAGIC, 10)
+#define JPEG_DEC_IOCTL_RESUME   _IOW   (JPEG_IOCTL_MAGIC, 11, JPEG_DEC_CONFIG_ROW)
+
+#define JPEG_DEC_IOCTL_FLUSH_CMDQ   _IOW   (JPEG_IOCTL_MAGIC, 17, JPEG_DEC_CONFIG_CMDQ)
+
+#define JPEG_DEC_IOCTL_DUMP_REG _IO  (JPEG_IOCTL_MAGIC, 30)
+//#define JPEG_DEC_IOCTL_MAN_GDMA _IOW (JPEG_IOCTL_MAGIC, 31, unsigned char)
+
+
+
+///////////////////// JPEG ENC IOCTL /////////////////////////////////////
+
+                                                                                                               
+#define JPEG_ENC_IOCTL_INIT     _IO  (JPEG_IOCTL_MAGIC, 11)                                                    
+#define JPEG_ENC_IOCTL_CONFIG   _IOW (JPEG_IOCTL_MAGIC, 12, JPEG_ENC_DRV_IN)                                   
+#define JPEG_ENC_IOCTL_WAIT     _IOWR(JPEG_IOCTL_MAGIC, 13, JPEG_ENC_DRV_OUT)                                  
+#define JPEG_ENC_IOCTL_DEINIT   _IO  (JPEG_IOCTL_MAGIC, 14)                                                    
+#define JPEG_ENC_IOCTL_START    _IO  (JPEG_IOCTL_MAGIC, 15)                                                    
+
+
+#define JPEG_ENC_IOCTL_WARM_RESET   _IO(JPEG_IOCTL_MAGIC, 20)
+#define JPEG_ENC_IOCTL_DUMP_REG     _IO(JPEG_IOCTL_MAGIC, 21)
+#define JPEG_ENC_IOCTL_RW_REG       _IO(JPEG_IOCTL_MAGIC, 22)
+
+                                                                                                               
+#endif                                                                                                         
+                                                                                                               
diff --git a/kernel-headers/kd_imgsensor.h b/kernel-headers/kd_imgsensor.h
index 98ace23..722c2d3 100644
--- a/kernel-headers/kd_imgsensor.h
+++ b/kernel-headers/kd_imgsensor.h
@@ -98,15 +98,16 @@ NSFeature :  : RAWSensorInfo < _id >  :  : getFlickerPara \
 ********************************************************************************/
 /* SENSOR CHIP VERSION */
 /*IMX*/
+#define IMX377_SENSOR_ID                        0x0377
+#define IMX278_SENSOR_ID                        0x0278
+#define IMX258_SENSOR_ID                        0x0258
+#define IMX230_SENSOR_ID                        0x0230
 #define IMX220_SENSOR_ID                        0x0220
-#define IMX145_SENSOR_ID                        0x0145
 #define IMX219_SENSOR_ID                        0x0219
 #define IMX215_SENSOR_ID                        0x0215
 #define IMX214_SENSOR_ID                        0x0214
 #define IMX179_SENSOR_ID                        0x0179
-#define IMX175_SENSOR_ID                        0x0175
 #define IMX178_SENSOR_ID                        0x0178
-#define IMX164_SENSOR_ID                        0x0164
 #define IMX135_SENSOR_ID                        0x0135
 #define IMX132MIPI_SENSOR_ID                    0x0132
 #define IMX119_SENSOR_ID                        0x0119
@@ -114,29 +115,23 @@ NSFeature :  : RAWSensorInfo < _id >  :  : getFlickerPara \
 #define IMX091_SENSOR_ID                        0x0091
 #define IMX073_SENSOR_ID                        0x0046
 #define IMX058_SENSOR_ID                        0x0058
-#define IMX166_SENSOR_ID                        0x0152
 /*OV*/
 #define OV23850_SENSOR_ID                       0x023850
 #define OV16825MIPI_SENSOR_ID                   0x016820
 #define OV13850_SENSOR_ID                       0xD850
 #define OV12830_SENSOR_ID                       0xC830
 #define OV9760MIPI_SENSOR_ID                    0x9760
-#define OV9762MIPI_SENSOR_ID                    0x9762
-#define OV9762SUBMIPI_SENSOR_ID                 0x9763
 #define OV9740MIPI_SENSOR_ID                    0x9740
 #define OV9726_SENSOR_ID                        0x9726
 #define OV9726MIPI_SENSOR_ID                    0x9726
 #define OV8865_SENSOR_ID                        0x8865
 #define OV8858_SENSOR_ID                        0x8858
 #define OV8858S_SENSOR_ID                      (0x8858+1)
-#define OV8858TRULY_SENSOR_ID                   0x885a
-#define OV8858SUNNY_SENSOR_ID                   0x8859
 #define OV8830_SENSOR_ID                        0x8830
 #define OV8825_SENSOR_ID                        0x8825
 #define OV7675_SENSOR_ID                        0x7673
 #define OV5693_SENSOR_ID                        0x5690
 #define OV5670MIPI_SENSOR_ID                    0x5670
-#define OV5670SUBMIPI_SENSOR_ID                 0x5672
 #define OV5671MIPI_SENSOR_ID                    0x5671
 #define OV5650_SENSOR_ID                        0x5651
 #define OV5650MIPI_SENSOR_ID                    0x5651
@@ -157,12 +152,16 @@ NSFeature :  : RAWSensorInfo < _id >  :  : getFlickerPara \
 #define OV2650_SENSOR_ID_1                      0x2651
 #define OV2650_SENSOR_ID_2                      0x2652
 #define OV2650_SENSOR_ID_3                      0x2655
+#define OV8856_SENSOR_ID                        0x8856
+#define OV8856_SENSOR_ID_SUNWIN                 (0x8856+1)
 /*S5K*/
 #define S5K2X8_SENSOR_ID                        0x2188
 #define S5K2P8_SENSOR_ID                        0x2108
 #define S5K3M2_SENSOR_ID                        0x30D2
-#define S5K3M2TRULY_SENSOR_ID                   0x30D4
-#define S5K3M2SUNNY_SENSOR_ID                   0x30D3
+#define S5K3M2_SENSOR_ID_YD                     (0x30D2+1)
+#define S5K3M2_SENSOR_ID_SUNWIN                 (0x30D2+2)
+#define S5K3M2_SENSOR_ID_SEASONS                (0x30D2+2)
+#define S5K3M2_SENSOR_ID_QT                     (0x30D2+3)
 #define S5K3AAEA_SENSOR_ID                      0x07AC
 #define S5K3BAFB_SENSOR_ID                      0x7070
 #define S5K3H7Y_SENSOR_ID                       0x3087
@@ -175,18 +174,15 @@ NSFeature :  : RAWSensorInfo < _id >  :  : getFlickerPara \
 #define S5K53BEX_SENSOR_ID                      0x45A8
 #define S5K53BEB_SENSOR_ID                      0x87A8
 #define S5K5BAFX_SENSOR_ID                      0x05BA
-#define S5K4E2GX_SENSOR_ID                      0x4e20
 #define S5K5E2YA_SENSOR_ID                      0x5e20
-#define S5K5E2YASUB_SENSOR_ID                   0x5e21
 #define S5K4H5YX_2LANE_SENSOR_ID                0x485B
-#define S5K4H5YC_SENSOR_ID                      0x485B
-#define S5K4H5YC_2LANE_SENSOR_ID                0x485b
+#define S5K4H5YC_SENSOR_ID                      0x485C
 #define S5K83AFX_SENSOR_ID                      0x01C4
 #define S5K5CAGX_SENSOR_ID                      0x05ca
 #define S5K8AAYX_MIPI_SENSOR_ID                 0x08aa
 #define S5K8AAYX_SENSOR_ID                      0x08aa
-#define S5K3L2_SENSOR_ID                        0x30c2
-#define S5K3H5XA_SENSOR_ID                      0x3085
+#define S5K3L2_SENSOR_ID			0x30C2
+#define S5K4H8_SENSOR_ID				0x4089
 /*HI*/
 #define HI841_SENSOR_ID                         0x0841
 #define HI707_SENSOR_ID                         0x00b8
@@ -200,6 +196,7 @@ NSFeature :  : RAWSensorInfo < _id >  :  : getFlickerPara \
 #define HI251_SENSOR_ID                         0x0084
 #define HI191MIPI_SENSOR_ID                     0x0191
 #define HIVICF_SENSOR_ID                        0x0081
+#define HI843B_SENSOR_ID                        0x0843
 /*MT*/
 #define MT9D011_SENSOR_ID                       0x1511
 #define MT9D111_SENSOR_ID                       0x1511
@@ -226,44 +223,25 @@ NSFeature :  : RAWSensorInfo < _id >  :  : getFlickerPara \
 #define MT9P017MIPI_SENSOR_ID                   0x4800
 #define MT9T113MIPI_SENSOR_ID                   0x4680
 /*GC*/
-#define GC2755_SENSOR_ID                        0x2655
 #define GC2355_SENSOR_ID                        0x2355
-#define GC2365_SENSOR_ID                        0x2365
-#define GC2355SUB_SENSOR_ID                        0x2356
 #define GC2235_SENSOR_ID                        0x2235
-
-#define GC2235MIPI_SENSOR_ID                        0x2235
-
 #define GC2035_SENSOR_ID                        0x2035
 #define GC2145_SENSOR_ID                        0x2145
 #define GC0330_SENSOR_ID                        0xC1
 #define GC0329_SENSOR_ID                        0xC0
 #define GC0310_SENSOR_ID                        0xa310
-#define GC0310MAIN_SENSOR_ID                    0xa311
-#define GC2155MIPI_SENSOR_ID                    0x2155
 #define GC0313MIPI_YUV_SENSOR_ID                0xD0
-#define GC0409_SENSOR_ID                        0x0409
-#define GC5004MIPI_SENSOR_ID                    0x5004
-#define GC5005MIPI_SENSOR_ID                    0x5005
-#define GC5005SUBMIPI_SENSOR_ID                 0x5006
-#define GC5024MIPI_SENSOR_ID                    0x5024
-#define GC8024MIPI_SENSOR_ID                    0x8024
-#define GC8003MIPI_SENSOR_ID                    0x8003
+#define GC0312_SENSOR_ID                        0xb310
+#define GC2755MIPI_SENSOR_ID                        0x2655
 /*SP*/
 #define SP0A19_YUV_SENSOR_ID                    0xA6
-#define SP0A20_SENSOR_ID                        0x2b
-#define SP2508_SENSOR_ID                        0x2508
-#define SP2509MIPI_SENSOR_ID                    0x2509
 #define SP2518_YUV_SENSOR_ID                    0x53
-#define SP5409MIPI_SENSOR_ID                    0x5409
-#define SP5409SUBMIPI_SENSOR_ID                    0x540a
-#define SP8408MIPI_SENSOR_ID                    0x1490
+#define SP2509MIPI_SENSOR_ID                    0x2509
 /*A*/
 #define A5141MIPI_SENSOR_ID                     0x4800
 #define A5142MIPI_SENSOR_ID                     0x4800
 /*HM*/
 #define HM3451_SENSOR_ID                        0x345
-#define HM5040_SENSOR_ID                        0x3bb
 /*AR*/
 #define AR0833_SENSOR_ID                        0x4B03
 /*SIV*/
@@ -291,48 +269,44 @@ NSFeature :  : RAWSensorInfo < _id >  :  : getFlickerPara \
 #define SHARP3D_SENSOR_ID                       0x003d
 #define T8EV5_SENSOR_ID                         0x1011
 
+#define S5K4H5YC_DL_SENSOR_ID                      0x485B
 /* CAMERA DRIVER NAME */
 #define CAMERA_HW_DEVNAME                       "kd_camera_hw"
 /* SENSOR DEVICE DRIVER NAME */
 /*IMX*/
+#define SENSOR_DRVNAME_IMX377_MIPI_RAW          "imx377mipiraw"
+#define SENSOR_DRVNAME_IMX278_MIPI_RAW          "imx278mipiraw"
+#define SENSOR_DRVNAME_IMX258_MIPI_RAW          "imx258mipiraw"
+#define SENSOR_DRVNAME_IMX230_MIPI_RAW          "imx230mipiraw"
 #define SENSOR_DRVNAME_IMX220_MIPI_RAW          "imx220mipiraw"
-#define SENSOR_DRVNAME_IMX145_MIPI_RAW          "imx145mipiraw"
 #define SENSOR_DRVNAME_IMX219_MIPI_RAW          "imx219mipiraw"
 #define SENSOR_DRVNAME_IMX215_MIPI_RAW          "imx215mipiraw"
 #define SENSOR_DRVNAME_IMX214_MIPI_RAW          "imx214mipiraw"
 #define SENSOR_DRVNAME_IMX179_MIPI_RAW          "imx179mipiraw"
-#define SENSOR_DRVNAME_IMX179_MIPI_RAW_4LANE     "imx179mipiraw4lane"
-#define SENSOR_DRVNAME_IMX175_MIPI_RAW          "imx175mipiraw"
 #define SENSOR_DRVNAME_IMX178_MIPI_RAW          "imx178mipiraw"
-#define SENSOR_DRVNAME_IMX164_MIPI_RAW          "imx164mipiraw"
 #define SENSOR_DRVNAME_IMX135_MIPI_RAW          "imx135mipiraw"
 #define SENSOR_DRVNAME_IMX132_MIPI_RAW          "imx132mipiraw"
 #define SENSOR_DRVNAME_IMX119_MIPI_RAW          "imx119mipiraw"
 #define SENSOR_DRVNAME_IMX105_MIPI_RAW          "imx105mipiraw"
 #define SENSOR_DRVNAME_IMX091_MIPI_RAW          "imx091mipiraw"
 #define SENSOR_DRVNAME_IMX073_MIPI_RAW          "imx073mipiraw"
-#define SENSOR_DRVNAME_IMX166_MIPI_RAW          "imx166mipiraw"
 /*OV*/
+#define SENSOR_DRVNAME_OV23850_MIPI_RAW         "ov23850mipiraw"
 #define SENSOR_DRVNAME_OV16825_MIPI_RAW         "ov16825mipiraw"
 #define SENSOR_DRVNAME_OV13850_MIPI_RAW         "ov13850mipiraw"
 #define SENSOR_DRVNAME_OV12830_MIPI_RAW         "ov12830mipiraw"
 #define SENSOR_DRVNAME_OV9760_MIPI_RAW          "ov9760mipiraw"
-#define SENSOR_DRVNAME_OV9762_MIPI_RAW          "ov9762mipiraw"
-#define SENSOR_DRVNAME_OV9762SUB_MIPI_RAW       "ov9762submipiraw"
 #define SENSOR_DRVNAME_OV9740_MIPI_YUV          "ov9740mipiyuv"
 #define SENSOR_DRVNAME_0V9726_RAW               "ov9726raw"
 #define SENSOR_DRVNAME_OV9726_MIPI_RAW          "ov9726mipiraw"
 #define SENSOR_DRVNAME_OV8865_MIPI_RAW          "ov8865mipiraw"
 #define SENSOR_DRVNAME_OV8858_MIPI_RAW          "ov8858mipiraw"
 #define SENSOR_DRVNAME_OV8858S_MIPI_RAW         "ov8858smipiraw"
-#define SENSOR_DRVNAME_OV8858TRULY_MIPI_RAW     "ov8858trulymipiraw"
-#define SENSOR_DRVNAME_OV8858SUNNY_MIPI_RAW     "ov8858sunnymipiraw"
 #define SENSOR_DRVNAME_OV8830_RAW               "ov8830"
 #define SENSOR_DRVNAME_OV8825_MIPI_RAW          "ov8825mipiraw"
 #define SENSOR_DRVNAME_OV7675_YUV               "ov7675yuv"
 #define SENSOR_DRVNAME_OV5693_MIPI_RAW          "ov5693mipi"
 #define SENSOR_DRVNAME_OV5670_MIPI_RAW          "ov5670mipiraw"
-#define SENSOR_DRVNAME_OV5670SUB_MIPI_RAW       "ov5670submipiraw"
 #define SENSOR_DRVNAME_OV5671_MIPI_RAW          "ov5671mipiraw"
 #define SENSOR_DRVNAME_OV5647MIPI_RAW           "ov5647mipiraw"
 #define SENSOR_DRVNAME_OV5645_MIPI_YUV          "ov5645_mipi_yuv"
@@ -349,16 +323,23 @@ NSFeature :  : RAWSensorInfo < _id >  :  : getFlickerPara \
 #define SENSOR_DRVNAME_OV4688_MIPI_RAW          "ov4688mipiraw"
 #define SENSOR_DRVNAME_OV3640_RAW               "ov3640"
 #define SENSOR_DRVNAME_OV3640_YUV               "ov3640yuv"
+#define SENSOR_DRVNAME_OV2724_MIPI_RAW          "ov2724mipiraw"
 #define SENSOR_DRVNAME_OV2722_MIPI_RAW          "ov2722mipiraw"
 #define SENSOR_DRVNAME_OV2680_MIPI_RAW          "ov2680mipiraw"
 #define SENSOR_DRVNAME_OV2659_YUV               "ov2659yuv"
 #define SENSOR_DRVNAME_OV2655_YUV               "ov2655yuv"
 #define SENSOR_DRVNAME_OV2650_RAW               "ov265x"
+#define SENSOR_DRVNAME_OV8856_MIPI_RAW          "ov8856mipiraw"
+#define SENSOR_DRVNAME_OV8856_MIPI_RAW_SUNWIN   "ov8856mipirawsunwin"
 /*S5K*/
+#define SENSOR_DRVNAME_S5K2X8_MIPI_RAW          "s5k2x8mipiraw"
 #define SENSOR_DRVNAME_S5K2P8_MIPI_RAW          "s5k2p8mipiraw"
+#define SENSOR_DRVNAME_S5K3L2_MIPI_RAW         "s5k3l2mipiraw"
 #define SENSOR_DRVNAME_S5K3M2_MIPI_RAW          "s5k3m2mipiraw"
-#define SENSOR_DRVNAME_S5K3M2TRULY_MIPI_RAW          "s5k3m2trulymipiraw"
-#define SENSOR_DRVNAME_S5K3M2SUNNY_MIPI_RAW          "s5k3m2sunnymipiraw"
+#define SENSOR_DRVNAME_S5K3M2_MIPI_RAW_YD       "s5k3m2mipirawyd"
+#define SENSOR_DRVNAME_S5K3M2_MIPI_RAW_SUNWIN   "s5k3m2mipirawsunwin"
+#define SENSOR_DRVNAME_S5K3M2_MIPI_RAW_SEASONS  "s5k3m2mipirawseasons"
+#define SENSOR_DRVNAME_S5K3M2_MIPI_RAW_QT       "s5k3m2mipirawqt"
 #define SENSOR_DRVNAME_S5K3H2YX_MIPI_RAW        "s5k3h2yxmipiraw"
 #define SENSOR_DRVNAME_S5K3H7Y_MIPI_RAW         "s5k3h7ymipiraw"
 #define SENSOR_DRVNAME_S5K4H5YC_MIPI_RAW        "s5k4h5ycmipiraw"
@@ -366,14 +347,10 @@ NSFeature :  : RAWSensorInfo < _id >  :  : getFlickerPara \
 #define SENSOR_DRVNAME_S5K4ECGX_MIPI_YUV        "s5k4ecgxmipiyuv"
 #define SENSOR_DRVNAME_S5K5CAGX_YUV             "s5k5cagxyuv"
 #define SENSOR_DRVNAME_S5K4H5YX_2LANE_MIPI_RAW  "s5k4h5yx2lanemipiraw"
-#define SENSOR_DRVNAME_S5K4E2GX_MIPI_RAW   "s5k4e2gxmipiraw"
 #define SENSOR_DRVNAME_S5K5E2YA_MIPI_RAW        "s5k5e2yamipiraw"
-#define SENSOR_DRVNAME_S5K5E2YASUB_MIPI_RAW     "s5k5e2yasubmipiraw"
 #define SENSOR_DRVNAME_S5K8AAYX_MIPI_YUV        "s5k8aayxmipiyuv"
 #define SENSOR_DRVNAME_S5K8AAYX_YUV             "s5k8aayxyuv"
-#define SENSOR_DRVNAME_S5K3L2_MIPI_RAW          "s5k3l2mipiraw"
-#define SENSOR_DRVNAME_S5K3H5XA_MIPI_RAW        "s5k3h5xamipiraw"
-#define SENSOR_DRVNAME_S5K4H5YC_MIPI_RAW_2LANE "s5k4h5ycmipiraw2lane"
+#define SENSOR_DRVNAME_S5K4H8_MIPI_RAW          "s5k4h8mipiraw"
 /*HI*/
 #define SENSOR_DRVNAME_HI841_MIPI_RAW           "hi841mipiraw"
 #define SENSOR_DRVNAME_HI707_YUV                "hi707yuv"
@@ -385,6 +362,7 @@ NSFeature :  : RAWSensorInfo < _id >  :  : getFlickerPara \
 #define SENSOR_DRVNAME_HI544_MIPI_RAW           "hi544mipiraw"
 #define SENSOR_DRVNAME_HI253_YUV                "hi253yuv"
 #define SENSOR_DRVNAME_HI191_MIPI_RAW           "hi191mipiraw"
+#define SENSOR_DRVNAME_HI843B_MIPI_RAW          "hi843bmipiraw"
 /*MT*/
 #define SENSOR_DRVNAME_MT9P012_RAW              "mt9p012"
 #define SENSOR_DRVNAME_MT9P015_RAW              "mt9p015"
@@ -399,41 +377,24 @@ NSFeature :  : RAWSensorInfo < _id >  :  : getFlickerPara \
 /*GC*/
 #define SENSOR_DRVNAME_GC2035_YUV               "gc2035_yuv"
 #define SENSOR_DRVNAME_GC2235_RAW               "gc2235_raw"
-#define SENSOR_DRVNAME_GC2235_MIPI_RAW   	"gc2235mipiraw"
-#define SENSOR_DRVNAME_GC2755_MIPI_RAW          "gc2755mipiraw"
 #define SENSOR_DRVNAME_GC2355_MIPI_RAW          "gc2355mipiraw"
-#define SENSOR_DRVNAME_GC2365_MIPI_RAW          "gc2365mipiraw"
-#define SENSOR_DRVNAME_GC2355SUB_MIPI_RAW          "gc2356submipiraw"
 #define SENSOR_DRVNAME_GC0330_YUV               "gc0330_yuv"
 #define SENSOR_DRVNAME_GC0329_YUV               "gc0329yuv"
 #define SENSOR_DRVNAME_GC2145_MIPI_YUV          "gc2145mipiyuv"
 #define SENSOR_DRVNAME_GC0310_MIPI_YUV          "gc0310mipiyuv"
-#define SENSOR_DRVNAME_GC0310MAIN_MIPI_YUV      "gc0310mainmipiyuv"
 #define SENSOR_DRVNAME_GC0310_YUV               "gc0310yuv"
-#define SENSOR_DRVNAME_GC2155_MIPI_YUV          "gc2155mipiyuv"
+#define SENSOR_DRVNAME_GC0312_YUV               "gc0312yuv"
 #define SENSOR_DRVNAME_GC0313MIPI_YUV           "gc0313mipiyuv"
-#define SENSOR_DRVNAME_GC0409MIPI_RAW           "gc0409mipiraw"
-#define SENSOR_DRVNAME_GC5004_MIPI_RAW          "gc5004mipiraw"
-#define SENSOR_DRVNAME_GC5005_MIPI_RAW          "gc5005mipiraw"
-#define SENSOR_DRVNAME_GC5005SUB_MIPI_RAW       "gc5005submipiraw"
-#define SENSOR_DRVNAME_GC5024_MIPI_RAW          "gc5024mipiraw"
-#define SENSOR_DRVNAME_GC8024_MIPI_RAW          "gc8024mipiraw"
-#define SENSOR_DRVNAME_GC8003_MIPI_RAW          "gc8003mipiraw"
+#define SENSOR_DRVNAME_GC2755_MIPI_RAW          "gc2755mipiraw"
 /*SP*/
 #define SENSOR_DRVNAME_SP0A19_YUV               "sp0a19yuv"
-#define SENSOR_DRVNAME_SP0A20_YUV               "sp0a20yuv"
-#define SENSOR_DRVNAME_SP2508_MIPI_RAW          "sp2508mipiraw"
-#define SENSOR_DRVNAME_SP2509_MIPI_RAW          "sp2509mipiraw"
 #define SENSOR_DRVNAME_SP2518_YUV               "sp2518yuv"
-#define SENSOR_DRVNAME_SP5409_MIPI_RAW          "sp5409_mipi_raw"
-#define SENSOR_DRVNAME_SP5409SUB_MIPI_RAW          "sp5409sub_mipi_raw"
-#define SENSOR_DRVNAME_SP8408_MIPI_RAW          "sp8408_mipi_raw"
+#define SENSOR_DRVNAME_SP2509_MIPI_RAW          "sp2509mipiraw"
 /*A*/
 #define SENSOR_DRVNAME_A5141_MIPI_RAW           "a5141mipiraw"
 #define SENSOR_DRVNAME_A5142_MIPI_RAW           "a5142mipiraw"
 /*HM*/
 #define SENSOR_DRVNAME_HM3451_RAW               "hm3451raw"
-#define SENSOR_DRVNAME_HM5040_MIPI_RAW          "hm5040mipiraw"
 /*AR*/
 #define SENSOR_DRVNAME_AR0833_MIPI_RAW          "ar0833mipiraw"
 /*SIV*/
@@ -450,7 +411,7 @@ NSFeature :  : RAWSensorInfo < _id >  :  : getFlickerPara \
 #define SENSOR_DRVNAME_T8EV5_YUV                "t8ev5_yuv"
 /*Test*/
 #define SENSOR_DRVNAME_IMX135_MIPI_RAW_5MP      "imx135mipiraw5mp"
-
+#define SENSOR_DRVNAME_S5K4H5YC_MIPI_RAW_DL        "s5k4h5ycmipiraw_dl"
 /*******************************************************************************
 *
 ********************************************************************************/
diff --git a/kernel-headers/kd_imgsensor_define.h b/kernel-headers/kd_imgsensor_define.h
index 8eab108..08ae053 100644
--- a/kernel-headers/kd_imgsensor_define.h
+++ b/kernel-headers/kd_imgsensor_define.h
@@ -713,6 +713,7 @@ typedef struct {
 	MUINT32 i4SubBlkH;      /* sub block height */
 	MUINT32 i4PosL[16][2];  /* left pd pixel position in one block*/
 	MUINT32 i4PosR[16][2];  /* right pd pixel position in one block*/
+	MUINT32 iMirrorFlip;    /* 0:IMAGE_NORMAL,1:IMAGE_H_MIRROR,2:IMAGE_V_MIRROR,3:IMAGE_HV_MIRROR*/
 } SET_PD_BLOCK_INFO_T, *PSET_PD_BLOCK_INFO_T;
 
 
diff --git a/kernel-headers/linux/hwmsensor.h b/kernel-headers/linux/hwmsensor.h
index c14611d..c14611d 100644..100755
--- a/kernel-headers/linux/hwmsensor.h
+++ b/kernel-headers/linux/hwmsensor.h
diff --git a/kernel-headers/mt_smi.h b/kernel-headers/mt_smi.h
new file mode 100644
index 0000000..83fc921
--- /dev/null
+++ b/kernel-headers/mt_smi.h
@@ -0,0 +1,190 @@
+#ifndef _MTK_SMI_H_
+#define _MTK_SMI_H_
+
+#define MTK_SMI_MAJOR_NUMBER 190
+
+#define MTK_IOW(num, dtype)     _IOW('O', num, dtype)
+#define MTK_IOR(num, dtype)     _IOR('O', num, dtype)
+#define MTK_IOWR(num, dtype)    _IOWR('O', num, dtype)
+#define MTK_IO(num)             _IO('O', num)
+
+/* -------------------------------------------------------------------------- */
+#define MTK_CONFIG_MM_MAU       MTK_IOW(10, unsigned long)
+
+
+typedef struct {
+	int larb;		/* 0~4: the larb you want to monitor */
+	int entry;		/* 0~2: the mau entry to use */
+	unsigned int port_msk;	/* port mask to be monitored */
+	int virt;		/* 1: monitor va (this port is using m4u);  */
+					/* 0: monitor pa (this port is not using m4u) */
+	int monitor_read;	/* monitor read transaction 1-enable, 0-disable */
+	int monitor_write;	/* monitor write transaction 1-enable, 0-disable */
+	unsigned int start;	/* start address to monitor */
+	unsigned int end;	/* end address to monitor */
+} MTK_MAU_CONFIG;
+
+
+int mau_config(MTK_MAU_CONFIG* pMauConf);
+int mau_dump_status(int larb);
+
+
+/* --------------------------------------------------------------------------- */
+typedef enum {
+	SMI_BWC_SCEN_NORMAL,
+	SMI_BWC_SCEN_VR,
+	SMI_BWC_SCEN_SWDEC_VP,
+	SMI_BWC_SCEN_VP,
+	SMI_BWC_SCEN_VR_SLOW,
+	SMI_BWC_SCEN_MM_GPU,
+	SMI_BWC_SCEN_WFD,
+	SMI_BWC_SCEN_VENC,
+	SMI_BWC_SCEN_ICFP,
+	SMI_BWC_SCEN_UI_IDLE,
+	SMI_BWC_SCEN_VSS,
+	SMI_BWC_SCEN_FORCE_MMDVFS,
+	SMI_BWC_SCEN_CNT
+} MTK_SMI_BWC_SCEN;
+
+/* MMDVFS */
+typedef enum {
+	MMDVFS_VOLTAGE_DEFAULT,
+	MMDVFS_VOLTAGE_0 = MMDVFS_VOLTAGE_DEFAULT,
+	MMDVFS_VOLTAGE_LOW = MMDVFS_VOLTAGE_0,
+	MMDVFS_VOLTAGE_1,
+	MMDVFS_VOLTAGE_HIGH = MMDVFS_VOLTAGE_1,
+	MMDVFS_VOLTAGE_DEFAULT_STEP,
+	MMDVFS_VOLTAGE_COUNT
+} mmdvfs_voltage_enum;
+
+typedef struct {
+	int scenario;
+	int b_on_off;		/* 0 : exit this scenario , 1 : enter this scenario */
+} MTK_SMI_BWC_CONFIG;
+
+typedef struct
+{
+	unsigned int*       hwc_max_pixel; //0 : exit this scenario , 1 : enter this scenario 
+} MTK_SMI_BWC_STATE;
+
+typedef struct {
+	unsigned int address;
+	unsigned int value;
+} MTK_SMI_BWC_REGISTER_SET;
+
+typedef struct {
+	unsigned int address;
+	unsigned int *return_address;
+} MTK_SMI_BWC_REGISTER_GET;
+
+#define MMDVFS_CAMERA_MODE_FLAG_DEFAULT	1
+#define MMDVFS_CAMERA_MODE_FLAG_PIP (1 << 1)
+#define MMDVFS_CAMERA_MODE_FLAG_VFB (1 << 2)
+#define MMDVFS_CAMERA_MODE_FLAG_EIS_2_0 (1 << 3)
+#define MMDVFS_CAMERA_MODE_FLAG_IVHDR (1 << 4)
+#define MMDVFS_CAMERA_MODE_FLAG_STEREO  (1 << 5)
+
+typedef struct {
+	unsigned int type;
+	MTK_SMI_BWC_SCEN scen;
+
+	unsigned int sensor_size;
+	unsigned int sensor_fps;
+	unsigned int camera_mode;
+
+	unsigned int venc_size;
+
+	unsigned int ret;
+} MTK_MMDVFS_CMD;
+
+#define MTK_MMDVFS_CMD_TYPE_SET		0
+#define MTK_MMDVFS_CMD_TYPE_QUERY	1
+
+typedef enum {
+	SMI_BWC_INFO_CON_PROFILE = 0,
+	SMI_BWC_INFO_SENSOR_SIZE,
+	SMI_BWC_INFO_VIDEO_RECORD_SIZE,
+	SMI_BWC_INFO_DISP_SIZE,
+	SMI_BWC_INFO_TV_OUT_SIZE,
+	SMI_BWC_INFO_FPS,
+	SMI_BWC_INFO_VIDEO_ENCODE_CODEC,
+	SMI_BWC_INFO_VIDEO_DECODE_CODEC,
+	SMI_BWC_INFO_HW_OVL_LIMIT,
+	SMI_BWC_INFO_CNT
+} MTK_SMI_BWC_INFO_ID;
+
+typedef struct {
+	int       property;
+	int       value1;
+	int       value2;
+} MTK_SMI_BWC_INFO_SET;
+
+
+typedef struct {
+	unsigned int flag;	/* Reserved */
+	int concurrent_profile;
+	int sensor_size[2];
+	int video_record_size[2];
+	int display_size[2];
+	int tv_out_size[2];
+	int fps;
+	int video_encode_codec;
+	int video_decode_codec;
+	int hw_ovl_limit;
+} MTK_SMI_BWC_MM_INFO;
+
+
+#define MTK_IOC_SPC_CONFIG          MTK_IOW(20, unsigned long)
+#define MTK_IOC_SPC_DUMP_REG        MTK_IOW(21, unsigned long)
+#define MTK_IOC_SPC_DUMP_STA        MTK_IOW(22, unsigned long)
+#define MTK_IOC_SPC_CMD             MTK_IOW(23, unsigned long)
+#define MTK_IOC_SMI_BWC_CONFIG      MTK_IOW(24, MTK_SMI_BWC_CONFIG)
+#define MTK_IOC_SMI_BWC_STATE       MTK_IOWR(25, MTK_SMI_BWC_STATE)
+#define MTK_IOC_SMI_BWC_REGISTER_SET    MTK_IOWR(26, MTK_SMI_BWC_REGISTER_SET)
+#define MTK_IOC_SMI_BWC_REGISTER_GET    MTK_IOWR(27, MTK_SMI_BWC_REGISTER_GET)
+
+/* For BWC.MM property setting */
+#define MTK_IOC_SMI_BWC_INFO_SET    MTK_IOWR(28, MTK_SMI_BWC_INFO_SET)
+/* For BWC.MM property get */
+#define MTK_IOC_SMI_BWC_INFO_GET    MTK_IOWR(29, MTK_SMI_BWC_MM_INFO)
+
+/* GMP end */
+
+#define MTK_IOC_SMI_DUMP_LARB       MTK_IOWR(66, unsigned int)
+#define MTK_IOC_SMI_DUMP_COMMON     MTK_IOWR(67, unsigned int)
+#define MTK_IOC_MMDVFS_CMD			MTK_IOW(88, MTK_MMDVFS_CMD)
+
+
+typedef enum {
+	SPC_PROT_NO_PROT = 0,
+	SPC_PROT_SEC_RW_ONLY,
+	SPC_PROT_SEC_RW_NONSEC_R,
+	SPC_PROT_NO_ACCESS,
+
+}SPC_PROT_T;
+
+
+typedef struct {
+	SPC_PROT_T domain_0_prot;
+	SPC_PROT_T domain_1_prot;
+	SPC_PROT_T domain_2_prot;
+	SPC_PROT_T domain_3_prot;
+	unsigned int start;	/* start address to monitor */
+	unsigned int end;	/* end address to monitor */
+} MTK_SPC_CONFIG;
+
+void spc_config(MTK_SPC_CONFIG* pCfg);
+unsigned int spc_status_check(void);
+unsigned int spc_dump_reg(void);
+unsigned int spc_register_isr(void* dev);
+unsigned int spc_clear_irq(void);
+int spc_test(int code);
+int MTK_SPC_Init(void* dev);
+
+#define MMDVFS_ENABLE_DEFAULT_STEP_QUERY
+#define MMDVFS_MMCLOCK_NOTIFICATION
+/* MMDVFS kernel API */
+extern int mmdvfs_set_step(MTK_SMI_BWC_SCEN scenario, mmdvfs_voltage_enum step);
+extern int mmdvfs_is_default_step_need_perf(void);
+extern void mmdvfs_mm_clock_switch_notify(int is_before, int is_to_high);
+#endif
diff --git a/kernel-headers/val_api_private.h b/kernel-headers/val_api_private.h
index 4e41082..4e41082 100644..100755
--- a/kernel-headers/val_api_private.h
+++ b/kernel-headers/val_api_private.h
diff --git a/kernel-headers/val_api_public.h b/kernel-headers/val_api_public.h
index 9af8887..9af8887 100644..100755
--- a/kernel-headers/val_api_public.h
+++ b/kernel-headers/val_api_public.h
diff --git a/kernel-headers/val_oal.h b/kernel-headers/val_oal.h
index 56f7711..56f7711 100644..100755
--- a/kernel-headers/val_oal.h
+++ b/kernel-headers/val_oal.h
diff --git a/kernel-headers/val_types_private.h b/kernel-headers/val_types_private.h
index 0675703..0675703 100644..100755
--- a/kernel-headers/val_types_private.h
+++ b/kernel-headers/val_types_private.h
diff --git a/kernel-headers/val_types_public.h b/kernel-headers/val_types_public.h
index ed407ac..d84acfd 100644
--- a/kernel-headers/val_types_public.h
+++ b/kernel-headers/val_types_public.h
@@ -152,6 +152,7 @@ typedef enum _VAL_DRIVER_TYPE_T {
 	VAL_DRIVER_TYPE_HEVC_ENC,                   /* /< HEVC encoder */
 	VAL_DRIVER_TYPE_HEVC_DEC,                   /* /< HEVC decoder */
 	VAL_DRIVER_TYPE_H264_ENC_LIVEPHOTO,         /* LivePhoto type */
+	VAL_DRIVER_TYPE_MMDVFS,                     /* /< MMDVFS */
 	VAL_DRIVER_TYPE_MAX = 0xFFFFFFFF            /* /< Max driver type */
 } VAL_DRIVER_TYPE_T;
 
diff --git a/kernel-headers/vcodec_OAL_v2.h b/kernel-headers/vcodec_OAL_v2.h
index fa4ef40..fa4ef40 100644..100755
--- a/kernel-headers/vcodec_OAL_v2.h
+++ b/kernel-headers/vcodec_OAL_v2.h
diff --git a/kernel-headers/vcodec_if_v2.h b/kernel-headers/vcodec_if_v2.h
index 72f1bcd..72f1bcd 100644..100755
--- a/kernel-headers/vcodec_if_v2.h
+++ b/kernel-headers/vcodec_if_v2.h
diff --git a/kernel-headers/vcodec_log.h b/kernel-headers/vcodec_log.h
index ac4abf1..ac4abf1 100644..100755
--- a/kernel-headers/vcodec_log.h
+++ b/kernel-headers/vcodec_log.h
diff --git a/kernel-headers/vdec_drv_if_private.h b/kernel-headers/vdec_drv_if_private.h
index 4e27516..4e27516 100644..100755
--- a/kernel-headers/vdec_drv_if_private.h
+++ b/kernel-headers/vdec_drv_if_private.h
diff --git a/kernel-headers/vdec_drv_if_public.h b/kernel-headers/vdec_drv_if_public.h
index 8a141a3..8a141a3 100644..100755
--- a/kernel-headers/vdec_drv_if_public.h
+++ b/kernel-headers/vdec_drv_if_public.h
diff --git a/kernel-headers/venc_drv_base.h b/kernel-headers/venc_drv_base.h
index ff02e7b..ff02e7b 100644..100755
--- a/kernel-headers/venc_drv_base.h
+++ b/kernel-headers/venc_drv_base.h
diff --git a/kernel-headers/venc_drv_if_private.h b/kernel-headers/venc_drv_if_private.h
index 4cff833..7ca9481 100644..100755
--- a/kernel-headers/venc_drv_if_private.h
+++ b/kernel-headers/venc_drv_if_private.h
@@ -106,6 +106,7 @@ typedef struct __VENC_HYB_ENCSETTING {
 	VAL_BOOL_T      fgUseMCI;
 	VAL_UINT32_T    u4VEncThreadNum;
         VAL_UINT32_T    u4LivePhoto;
+        VAL_UINT32_T    u4ViLTE;
 } VENC_HYBRID_ENCSETTING;
 
 
diff --git a/kernel-headers/venc_drv_if_public.h b/kernel-headers/venc_drv_if_public.h
index 7035dde..f99d109 100644
--- a/kernel-headers/venc_drv_if_public.h
+++ b/kernel-headers/venc_drv_if_public.h
@@ -343,6 +343,7 @@ typedef enum __VENC_DRV_SET_TYPE_T {
 	VENC_DRV_SET_TYPE_SLOW_MOTION_UNLOCK_HW,    /* /< Set to Slow Motion Video Recording for UnLock HW */
 	VENC_DRV_SET_TYPE_NONREFP,              /* /< Set Enable/Disable Non reference P frame */
 	VENC_DRV_SET_TYPE_CONFIG_QP,            /* /< Set init QP */
+        VENC_DRV_SET_TYPE_RFS_ON,
 	VENC_DRV_SET_TYPE_MAX = 0xFFFFFFFF      /* /< Max VENC_DRV_SET_TYPE_T value */
 } VENC_DRV_SET_TYPE_T;
 
@@ -397,6 +398,7 @@ typedef enum __VENC_DRV_SCENARIO_T {
 	VENC_DRV_SCENARIO_LIVEPHOTO_EFFECT      = (1 << 2), /* /< LivePhoto effect transcoding */
 	VENC_DRV_SCENARIO_CAMERA_REC_SLOW_MOTION = (1 << 3), /* /< Camera recording with slow motion */
 	VENC_DRV_SCENARIO_SCREEN_REC            = (1 << 4), /* /< Screen recording */
+        VENC_DRV_SCENARIO_VILTE_REC            = (1 << 5), /* /< VILTE recording */
 } VENC_DRV_SCENARIO_T;
 
 
diff --git a/kernel-headers/videocodec_kernel_driver.h b/kernel-headers/videocodec_kernel_driver.h
new file mode 100644
index 0000000..7eec0db
--- /dev/null
+++ b/kernel-headers/videocodec_kernel_driver.h
@@ -0,0 +1,47 @@
+#ifndef __MT6589_VCODEC_H__
+#define __MT6589_VCODEC_H__
+
+#define MFV_IOC_MAGIC    'M'
+
+//below is control message
+#define MFV_TEST_CMD                            _IO(MFV_IOC_MAGIC,  0x00)
+#define MFV_INIT_CMD                            _IO(MFV_IOC_MAGIC, 0x01)
+#define MFV_DEINIT_CMD                          _IO(MFV_IOC_MAGIC, 0x02)
+#define MFV_SET_CMD_CMD                         _IOW(MFV_IOC_MAGIC, 0x03, unsigned int) //P_MFV_DRV_CMD_QUEUE_T
+#define MFV_SET_PWR_CMD                         _IOW(MFV_IOC_MAGIC, 0x04, unsigned int) //HAL_POWER_T *
+#define MFV_SET_ISR_CMD                         _IOW(MFV_IOC_MAGIC, 0x05, unsigned int) //HAL_ISR_T *
+#define MFV_ALLOC_MEM_CMD                       _IOW(MFV_IOC_MAGIC, 0x06, unsigned int)
+#define MFV_FREE_MEM_CMD                        _IOW(MFV_IOC_MAGIC, 0x07, unsigned int)
+#define MFV_MAKE_PMEM_TO_NONCACHED              _IOW(MFV_IOC_MAGIC, 0x08, unsigned int) //unsigned int*
+#define MFV_ALLOC_INT_MEM_CMD                   _IOW(MFV_IOC_MAGIC, 0x09, unsigned int) //VAL_INTMEM_T*
+#define MFV_FREE_INT_MEM_CMD                    _IOW(MFV_IOC_MAGIC, 0x0a, unsigned int)//VAL_INTMEM_T*
+#define VCODEC_WAITISR                          _IOW(MFV_IOC_MAGIC, 0x0b, unsigned int)//HAL_POWER_T *
+#define VCODEC_LOCKHW                           _IOW(MFV_IOC_MAGIC, 0x0d, unsigned int)//VAL_HW_LOCK_T *
+#define VCODEC_PMEM_FLUSH                       _IOW(MFV_IOC_MAGIC, 0x10, unsigned int)//HAL_POWER_T *
+#define VCODEC_PMEM_CLEAN                       _IOW(MFV_IOC_MAGIC, 0x11, unsigned int)//HAL_POWER_T *
+#define VCODEC_INC_SYSRAM_USER                  _IOW(MFV_IOC_MAGIC, 0x13, unsigned int)//VAL_UINT32_T *
+#define VCODEC_DEC_SYSRAM_USER                  _IOW(MFV_IOC_MAGIC, 0x14, unsigned int)//VAL_UINT32_T *
+#define VCODEC_INC_ENC_EMI_USER                 _IOW(MFV_IOC_MAGIC, 0x15, unsigned int)//VAL_UINT32_T *
+#define VCODEC_DEC_ENC_EMI_USER                 _IOW(MFV_IOC_MAGIC, 0x16, unsigned int)//VAL_UINT32_T *
+#define VCODEC_INC_DEC_EMI_USER                 _IOW(MFV_IOC_MAGIC, 0x17, unsigned int)//VAL_UINT32_T *
+#define VCODEC_DEC_DEC_EMI_USER                 _IOW(MFV_IOC_MAGIC, 0x18, unsigned int)//VAL_UINT32_T *
+#define VCODEC_INITHWLOCK                       _IOW(MFV_IOC_MAGIC, 0x20, unsigned int)//VAL_VCODEC_OAL_HW_REGISTER_T *
+#define VCODEC_DEINITHWLOCK                     _IOW(MFV_IOC_MAGIC, 0x21, unsigned int)//VAL_VCODEC_OAL_HW_REGISTER_T *
+#define VCODEC_ALLOC_NON_CACHE_BUFFER           _IOW(MFV_IOC_MAGIC, 0x22, unsigned int)//VAL_MEMORY_T *
+#define VCODEC_FREE_NON_CACHE_BUFFER            _IOW(MFV_IOC_MAGIC, 0x23, unsigned int)//VAL_MEMORY_T *
+#define VCODEC_SET_THREAD_ID                    _IOW(MFV_IOC_MAGIC, 0x24, unsigned int)//VAL_VCODEC_THREAD_ID_T *
+#define VCODEC_SET_SYSRAM_INFO                  _IOW(MFV_IOC_MAGIC, 0x25, unsigned int)//VAL_INTMEM_T *
+#define VCODEC_GET_SYSRAM_INFO                  _IOW(MFV_IOC_MAGIC, 0x26, unsigned int)//VAL_INTMEM_T *
+#define VCODEC_INC_PWR_USER                     _IOW(MFV_IOC_MAGIC, 0x27, unsigned int)//HAL_POWER_T *
+#define VCODEC_DEC_PWR_USER                     _IOW(MFV_IOC_MAGIC, 0x28, unsigned int)//HAL_POWER_T *
+#define VCODEC_GET_CPU_LOADING_INFO             _IOW(MFV_IOC_MAGIC, 0x29, unsigned int)//VAL_VCODEC_CPU_LOADING_INFO_T *
+#define VCODEC_GET_CORE_LOADING                 _IOW(MFV_IOC_MAGIC, 0x30, unsigned int)//VAL_VCODEC_CORE_LOADING_T *
+#define VCODEC_GET_CORE_NUMBER                  _IOW(MFV_IOC_MAGIC, 0x31, unsigned int)//int *
+#define VCODEC_SET_CPU_OPP_LIMIT                _IOW(MFV_IOC_MAGIC, 0x32, unsigned int)//VAL_VCODEC_CPU_OPP_LIMIT_T *
+#define VCODEC_UNLOCKHW                         _IOW(MFV_IOC_MAGIC, 0x33, unsigned int)//VAL_HW_LOCK_T *
+#define VCODEC_MB                               _IOW(MFV_IOC_MAGIC, 0x34, unsigned int)//VAL_UINT32_T *
+
+
+//#define MFV_GET_CACHECTRLADDR_CMD  _IOR(MFV_IOC_MAGIC, 0x06, int)
+
+#endif //__MT6589_MFLEXVIDEO_H__