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#define REG_DEV_IDL_TX (TX_PAGE_L0 | 0x0002)
#define REG_DEV_IDH_TX (TX_PAGE_L0 | 0x0003)
#define REG_DEV_REV (TX_PAGE_L0 | 0x0004)
#define REG_SYS_CTRL1 (TX_PAGE_L0 | 0x0008)
#define REG_SYS_STAT (TX_PAGE_L0 | 0x0009)
#define REG_VID_CTRL (TX_PAGE_L0 | 0x0048)
#define REG_VID_ACEN (TX_PAGE_L0 | 0x0049)
#define DOWN_SAMPLE (BIT0)
#define RANGE_COMPRESS (BIT1)
#define RGB2YCbCr (BIT2)
#define RANGE_CLIP (BIT3)
#define CLIP_INPUTS_YC (BIT4)
#define PUF_RANGE_CLIP (BIT5)
#define PUF_DITHER (BIT7)
#define REG_VID_MODE (TX_PAGE_L0 | 0x004A)
#define UP_SAMPLE (BIT2)
#define YCbCr2RGB (BIT3)
#define RANGE_EXPAND (BIT4)
#define DITHER (BIT5)
#define REG_INTR_STATE (TX_PAGE_L0 | 0x0070)
#define REG_INTR1 (TX_PAGE_L0 | 0x0071)
#define REG_INTR1_MASK (TX_PAGE_L0 | 0x0075)
#define REG_INTR2 (TX_PAGE_L0 | 0x0072)
#define REG_INTR2_MASK (TX_PAGE_L0 | 0x0076)
#define REG_TMDS_CCTRL (TX_PAGE_L0 | 0x0080)
#define TMDS_OE (BIT4)
#define REG_USB_CHARGE_PUMP_MHL (TX_PAGE_L0 | 0x00F7)
#define REG_USB_CHARGE_PUMP (TX_PAGE_L0 | 0x00F8)
#define REG_LM_DDC (TX_PAGE_L0 | 0x00C7)
#define DDC_REQUEST (BIT0)
#define DDC_GRANT (BIT1)
#define DDC_ACCESS (BIT2)
#define VID_MUTE (BIT5)
#define REG_AUDP_TXCTRL (TX_PAGE_L1 | 0x2F)
#define REG_POWER_EN (TX_PAGE_L1 | 0x003D)
#define REG_SRST (TX_PAGE_3 | 0x0000)
#define REG_DISC_CTRL1 (TX_PAGE_3 | 0x0010)
#define REG_DISC_CTRL2 (TX_PAGE_3 | 0x0011)
#define REG_DISC_CTRL3 (TX_PAGE_3 | 0x0012)
#define REG_DISC_CTRL4 (TX_PAGE_3 | 0x0013)
#define REG_DISC_CTRL5 (TX_PAGE_3 | 0x0014)
#define REG_DISC_CTRL6 (TX_PAGE_3 | 0x0015)
#define REG_DISC_CTRL7 (TX_PAGE_3 | 0x0016)
#define REG_DISC_CTRL8 (TX_PAGE_3 | 0x0017)
#define REG_DISC_CTRL9 (TX_PAGE_3 | 0x0018)
#define REG_DISC_CTRL10 (TX_PAGE_3 | 0x0019)
#define REG_DISC_CTRL11 (TX_PAGE_3 | 0x001A)
#define REG_DISC_STAT (TX_PAGE_3 | 0x001B)
#define REG_DISC_STAT2 (TX_PAGE_3 | 0x001C)
#define REG_INT_CTRL (TX_PAGE_3 | 0x0020)
#define REG_INTR4 (TX_PAGE_3 | 0x0021)
#define REG_INTR4_MASK (TX_PAGE_3 | 0x0022)
#define REG_INTR5 (TX_PAGE_3 | 0x0023)
#define REG_INTR5_MASK (TX_PAGE_3 | 0x0024)
#define REG_MHLTX_CTL1 (TX_PAGE_3 | 0x0030)
#define REG_MHLTX_CTL2 (TX_PAGE_3 | 0x0031)
#define REG_MHLTX_CTL3 (TX_PAGE_3 | 0x0032)
#define REG_MHLTX_CTL4 (TX_PAGE_3 | 0x0033)
#define REG_MHLTX_CTL5 (TX_PAGE_3 | 0x0034)
#define REG_MHLTX_CTL6 (TX_PAGE_3 | 0x0035)
#define REG_MHLTX_CTL7 (TX_PAGE_3 | 0x0036)
#define REG_MHLTX_CTL8 (TX_PAGE_3 | 0x0037)
#define REG_CBUS_CFG (TX_PAGE_CBUS | 0x0007)
#define REG_CBUS_INTR_STATUS (TX_PAGE_CBUS | 0x0008)
#define BIT_DDC_ABORT (BIT2)
#define BIT_MSC_MSG_RCV (BIT3)
#define BIT_MSC_XFR_DONE (BIT4)
#define BIT_MSC_XFR_ABORT (BIT5)
#define BIT_MSC_ABORT (BIT6)
#define REG_CBUS_INTR_ENABLE (TX_PAGE_CBUS | 0x0009)
#define REG_CBUS_BUS_STATUS (TX_PAGE_CBUS | 0x000A)
#define BIT_BUS_CONNECTED 0x01
#define BIT_LA_VAL_CHG 0x02
#define REG_DDC_ABORT_REASON (TX_PAGE_CBUS | 0x000B)
#define REG_MSC_REQ_ABORT_REASON (TX_PAGE_CBUS | 0x000D)
#define REG_MSC_RES_ABORT_REASON (TX_PAGE_CBUS | 0x000E)
#define CBUSABORT_BIT_REQ_MAXFAIL (0x01 << 0)
#define CBUSABORT_BIT_PROTOCOL_ERROR (0x01 << 1)
#define CBUSABORT_BIT_REQ_TIMEOUT (0x01 << 2)
#define CBUSABORT_BIT_UNDEFINED_OPCODE (0x01 << 3)
#define CBUSABORT_BIT_UNDEFINED_OFFSET (0x01 << 4)
#define CBUSABORT_BIT_PEER_BUSY (0x01 << 5)
#define CBUSABORT_BIT_PEER_ABORTED (0x01 << 7)
#define REG_MSC_COMMAND_START (TX_PAGE_CBUS | 0x0012)
#define BIT_TRANSFER_PVT_CMD 0x01
#define BIT_SEND_MSC_MSG 0x02
#define MSC_START_BIT_MSC_CMD (0x01 << 0)
#define MSC_START_BIT_VS_CMD (0x01 << 1)
#define MSC_START_BIT_READ_REG (0x01 << 2)
#define MSC_START_BIT_WRITE_REG (0x01 << 3)
#define MSC_START_BIT_WRITE_BURST (0x01 << 4)
#define REG_MSC_CMD_OR_OFFSET (TX_PAGE_CBUS | 0x0013)
#define REG_CBUS_PRI_WR_DATA_1ST (TX_PAGE_CBUS | 0x0014)
#define REG_CBUS_PRI_WR_DATA_2ND (TX_PAGE_CBUS | 0x0015)
#define REG_CBUS_PRI_RD_DATA_1ST (TX_PAGE_CBUS | 0x0016)
#define REG_CBUS_PRI_RD_DATA_2ND (TX_PAGE_CBUS | 0x0017)
#define REG_CBUS_PRI_VS_CMD (TX_PAGE_CBUS | 0x0018)
#define REG_CBUS_PRI_VS_DATA (TX_PAGE_CBUS | 0x0019)
#define MSC_REQUESTOR_DONE_NACK (0x01 << 6)
#define REG_CBUS_MSC_RETRY_INTERVAL (TX_PAGE_CBUS | 0x001A)
#define REG_CBUS_DDC_FAIL_LIMIT (TX_PAGE_CBUS | 0x001C)
#define REG_CBUS_MSC_FAIL_LIMIT (TX_PAGE_CBUS | 0x001D)
#define REG_CBUS_MSC_INT2_STATUS (TX_PAGE_CBUS | 0x001E)
#define REG_CBUS_MSC_INT2_ENABLE (TX_PAGE_CBUS | 0x001F)
#define MSC_INT2_REQ_WRITE_MSC (0x01 << 0)
#define MSC_INT2_HEARTBEAT_MAXFAIL (0x01 << 1)
#define REG_MSC_WRITE_BURST_LEN (TX_PAGE_CBUS | 0x0020)
#define REG_MSC_HEARTBEAT_CONTROL (TX_PAGE_CBUS | 0x0021)
#define MSC_HEARTBEAT_PERIOD_MASK 0x0F
#define MSC_HEARTBEAT_FAIL_LIMIT_MASK 0x70
#define MSC_HEARTBEAT_ENABLE 0x80
#define REG_MSC_TIMEOUT_LIMIT (TX_PAGE_CBUS | 0x0022)
#define MSC_TIMEOUT_LIMIT_MSB_MASK (0x0F)
#define MSC_LEGACY_BIT (0x01 << 7)
#define REG_MSC_COMP_CTRL (TX_PAGE_CBUS | 0x002E)
#define REG_CBUS_CTRL1 (TX_PAGE_CBUS | 0x0030)
#define REG_CBUS_CTRL2 (TX_PAGE_CBUS | 0x0031)
#define REG_CBUS_CTRL3 (TX_PAGE_CBUS | 0x0032)
#define REG_CBUS_CTRL4 (TX_PAGE_CBUS | 0x0033)
#define REG_CBUS_CTRL5 (TX_PAGE_CBUS | 0x0034)
#define REG_CBUS_CTRL6 (TX_PAGE_CBUS | 0x0035)
#define REG_CBUS_CTRL7 (TX_PAGE_CBUS | 0x0036)
#define REG_CBUS_STAT1 (TX_PAGE_CBUS | 0x0037)
#define REG_CBUS_STAT2 (TX_PAGE_CBUS | 0x0038)
#define REG_CBUS_CTRL8 (TX_PAGE_CBUS | 0x0039)
#define REG_CBUS_CTRL9 (TX_PAGE_CBUS | 0x003A)
#define REG_CBUS_CTRL10 (TX_PAGE_CBUS | 0x003B)
#define REG_CBUS_CTRL11 (TX_PAGE_CBUS | 0x003C)
#define REG_CBUS_CTRL12 (TX_PAGE_CBUS | 0x003D)
#define REG_CBUS_DRV_STR0 (TX_PAGE_CBUS | 0x0040)
#define REG_CBUS_DRV_STR1 (TX_PAGE_CBUS | 0x0041)
#define REG_CBUS_ACK_CONTROL (TX_PAGE_CBUS | 0x0042)
#define REG_CBUS_CAL_CONTROL (TX_PAGE_CBUS | 0x0043)
#define REG_CBUS_DEVICE_CAP_0 (TX_PAGE_CBUS | 0x0080)
#define REG_CBUS_DEVICE_CAP_1 (TX_PAGE_CBUS | 0x0081)
#define REG_CBUS_DEVICE_CAP_2 (TX_PAGE_CBUS | 0x0082)
#define REG_CBUS_DEVICE_CAP_3 (TX_PAGE_CBUS | 0x0083)
#define REG_CBUS_DEVICE_CAP_4 (TX_PAGE_CBUS | 0x0084)
#define REG_CBUS_DEVICE_CAP_5 (TX_PAGE_CBUS | 0x0085)
#define REG_CBUS_DEVICE_CAP_6 (TX_PAGE_CBUS | 0x0086)
#define REG_CBUS_DEVICE_CAP_7 (TX_PAGE_CBUS | 0x0087)
#define REG_CBUS_DEVICE_CAP_8 (TX_PAGE_CBUS | 0x0088)
#define REG_CBUS_DEVICE_CAP_9 (TX_PAGE_CBUS | 0x0089)
#define REG_CBUS_DEVICE_CAP_A (TX_PAGE_CBUS | 0x008A)
#define REG_CBUS_DEVICE_CAP_B (TX_PAGE_CBUS | 0x008B)
#define REG_CBUS_DEVICE_CAP_C (TX_PAGE_CBUS | 0x008C)
#define REG_CBUS_DEVICE_CAP_D (TX_PAGE_CBUS | 0x008D)
#define REG_CBUS_DEVICE_CAP_E (TX_PAGE_CBUS | 0x008E)
#define REG_CBUS_DEVICE_CAP_F (TX_PAGE_CBUS | 0x008F)
#define REG_CBUS_SET_INT_0 (TX_PAGE_CBUS | 0x00A0)
#define REG_CBUS_SET_INT_1 (TX_PAGE_CBUS | 0x00A1)
#define REG_CBUS_SET_INT_2 (TX_PAGE_CBUS | 0x00A2)
#define REG_CBUS_SET_INT_3 (TX_PAGE_CBUS | 0x00A3)
#define REG_CBUS_WRITE_STAT_0 (TX_PAGE_CBUS | 0x00B0)
#define REG_CBUS_WRITE_STAT_1 (TX_PAGE_CBUS | 0x00B1)
#define REG_CBUS_WRITE_STAT_2 (TX_PAGE_CBUS | 0x00B2)
#define REG_CBUS_WRITE_STAT_3 (TX_PAGE_CBUS | 0x00B3)
#define REG_CBUS_SCRATCHPAD_0 (TX_PAGE_CBUS | 0x00C0)
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