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* arm64: dts: add DT entry to mount /system early during bootfire8552017-12-273-0/+51
| | | | | | BaCkPoRtEd To 3.10 By ThE BigGeSt MidGeT iN tHe GaMe Signed-off-by: Mister Oyster <oysterized@gmail.com>
* defconfig: regen and disable MTK_PASSPOINT_R1_SUPPORTMister Oyster2017-12-271-2/+1
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* UPSTREAM: arm64: jump labels: NOP out NOP -> NOP replacementMark Rutland2017-12-251-14/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the arm64 arch_static_branch implementation we place an A64 NOP into the instruction stream and log relevant details to a jump_entry in a __jump_table section. Later this may be replaced with an immediate branch without link to the code for the unlikely case. At init time, the core calls arch_jump_label_transform_static to initialise the NOPs. On x86 this involves inserting the optimal NOP for a given microarchitecture, but on arm64 we only use the architectural NOP, and hence replace each NOP with the exact same NOP. This is somewhat pointless. Additionally, at module load time we don't call jump_label_apply_nops to patch the optimal NOPs in, unlike other architectures, but get away with this because we only use the architectural NOP anyway. A later notifier will patch NOPs with branches as required. Similarly to x86 commit 11570da1c5b1dee1 (x86/jump-label: Do not bother updating NOPs if they are correct), we can avoid patching NOPs with identical NOPs. Given that we only use a single NOP encoding, this means we can NOP-out the body of arch_jump_label_transform_static entirely. As the default __weak arch_jump_label_transform_static implementation performs a patch, we must use an empty function to achieve this. Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Jiang Liu <liuj97@gmail.com> Cc: Laura Abbott <lauraa@codeaurora.org> Acked-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> (cherry picked from commit 6ddae4186886a81e22ad78ad7c6936ed36bc8225) Signed-off-by: Tomasz Figa <tfiga@chromium.org> Bug: 24475017 Change-Id: I9ef07c3a5a7f91418b30006850fcc0c421e147e2 Signed-off-by: Kees Cook <keescook@google.com> Signed-off-by: franciscofranco <franciscofranco.1990@gmail.com> Signed-off-by: Joe Maples <joe@frap129.org>
* arm64: use the new *_relaxed macros for lower power usagefranciscofranco2017-12-255-9/+9
| | | | | | Signed-off-by: franciscofranco <franciscofranco.1990@gmail.com> Signed-off-by: Joe Maples <joe@frap129.org> Signed-off-by: Mister Oyster <oysterized@gmail.com>
* defconfig: remove VMEMMister Oyster2017-12-242-2/+0
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* defconfig: remove android_pmem config (and delete recovery_defconfig, never ↵Mister Oyster2017-12-243-3316/+0
| | | | used)
* ARM64: Wire up getrandom.Josh Gao2017-12-232-1/+3
| | | | | Bug: http://b/29621447 Change-Id: I2e7623ae13318b91589d17d779391c4baa292421
* Finally eradicate CONFIG_HOTPLUGStephen Rothwell2017-12-2215-26/+8
| | | | | | | | | | | | | | | | | | | Ever since commit 45f035ab9b8f ("CONFIG_HOTPLUG should be always on"), it has been basically impossible to build a kernel with CONFIG_HOTPLUG turned off. Remove all the remaining references to it. Cc: Russell King <linux@arm.linux.org.uk> Cc: Doug Thompson <dougthompson@xmission.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Steven Whitehouse <swhiteho@redhat.com> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Pavel Machek <pavel@ucw.cz> Cc: "Rafael J. Wysocki" <rjw@sisk.pl> Cc: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au> Acked-by: Mauro Carvalho Chehab <mchehab@redhat.com> Acked-by: Hans Verkuil <hans.verkuil@cisco.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* cflags: cleanup Makefile & arm64 Makefile (-ftree-vectorize is enabled when ↵Moyster2017-12-221-1/+1
| | | | building with O3, let's keep it clean)
* defconfig: raise frame_warm to 2048Moyster2017-12-221-1/+1
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* Revert "arch/arm64: skip randomization within stack"Mister Oyster2017-12-221-0/+2
| | | | This reverts commit 76848d1b0190a973e54cde8b7dab8af87b34f6f5.
* defconfig: support NFSMister Oyster2017-12-221-1/+25
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* defconfig: disable selinux bootparamMister Oyster2017-12-221-2/+1
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* defconfig: don't build old deprecated OSS sound stuffMister Oyster2017-12-221-8/+5
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* defconfig: update mmap_rnd_* to max valueMister Oyster2017-12-211-2/+2
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* defconfig: turnoff deprecated configMister Oyster2017-12-211-1/+1
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* defconfig: support LZMA/XZ/LZ4 compressed ramdiskMister Oyster2017-12-211-5/+15
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* defconfig: enable chacha20_neonMister Oyster2017-12-211-0/+1
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* backport: crypto: arm64/chacha20 - implement NEON version based on SSE3 codeArd Biesheuvel2017-12-214-0/+596
| | | | | | | | | | | | | | This is a straight port to arm64/NEON of the x86 SSE3 implementation of the ChaCha20 stream cipher. It uses the new skcipher walksize attribute to process the input in strides of 4x the block size. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au> backported to 3.10 the same way arm chacha20 SNEON3 imp. for 3.18 was done : https://android-review.googlesource.com/c/kernel/common/+/551349 Signed-off-by: Mister Oyster <oysterized@gmail.com>
* arm64/crypto: issue aese/aesmc instructions in pairsArd Biesheuvel2017-12-212-13/+9
| | | | | | | | | | | | | | | | | | | This changes the AES core transform implementations to issue aese/aesmc (and aesd/aesimc) in pairs. This enables a micro-architectural optimization in recent Cortex-A5x cores that improves performance by 50-90%. Measured performance in cycles per byte (Cortex-A57): CBC enc CBC dec CTR before 3.64 1.34 1.32 after 1.95 0.85 0.93 Note that this results in a ~5% performance decrease for older cores. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Will Deacon <will.deacon@arm.com> (cherry picked from commit 4a97abd44329bf7b9c57f020224da5f823c9c9ea) Change-Id: I9d6b28b9bd9263bb273607590704111529323ca9
* arm64: crypto: increase AES interleave to 4xArd Biesheuvel2017-12-211-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch increases the interleave factor for parallel AES modes to 4x. This improves performance on Cortex-A57 by ~35%. This is due to the 3-cycle latency of AES instructions on the A57's relatively deep pipeline (compared to Cortex-A53 where the AES instruction latency is only 2 cycles). At the same time, disable inline expansion of the core AES functions, as the performance benefit of this feature is negligible. Measured on AMD Seattle (using tcrypt.ko mode=500 sec=1): Baseline (2x interleave, inline expansion) ------------------------------------------ testing speed of async cbc(aes) (cbc-aes-ce) decryption test 4 (128 bit key, 8192 byte blocks): 95545 operations in 1 seconds test 14 (256 bit key, 8192 byte blocks): 68496 operations in 1 seconds This patch (4x interleave, no inline expansion) ----------------------------------------------- testing speed of async cbc(aes) (cbc-aes-ce) decryption test 4 (128 bit key, 8192 byte blocks): 124735 operations in 1 seconds test 14 (256 bit key, 8192 byte blocks): 92328 operations in 1 seconds Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> (cherry picked from commit 0eee0fbd41c7b57d01136df2519c92ec1506e333) Change-Id: I0fb82b0cc7f685a13c3d15c919be435917e17429
* arm64/crypto: use crypto instructions to generate AES key scheduleArd Biesheuvel2017-12-215-11/+133
| | | | | | | | | | | | | | This patch implements the AES key schedule generation using ARMv8 Crypto Instructions. It replaces the table based C implementation in aes_generic.ko, which means we can drop the dependency on that module. Tested-by: Steve Capper <steve.capper@linaro.org> Acked-by: Steve Capper <steve.capper@linaro.org> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Will Deacon <will.deacon@arm.com> (cherry picked from commit 12ac3efe74f888a13cb4df88b38bb01e8034dea8) Change-Id: I48488f43e280c4de8256365eb0be40d7be26d418
* crypto: arm64/aes-blk - honour iv_out requirement in CBC and CTR modesArd Biesheuvel2017-12-211-46/+42
| | | | | | | | | | | | | Update the ARMv8 Crypto Extensions and the plain NEON AES implementations in CBC and CTR modes to return the next IV back to the skcipher API client. This is necessary for chaining to work correctly. Note that for CTR, this is only done if the request is a round multiple of the block size, since otherwise, chaining is impossible anyway. Cc: <stable@vger.kernel.org> # v3.16+ Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* defconfig: enable all optimized crypto algos (chacha20_neon impl. is for ↵Mister Oyster2017-12-211-7/+7
| | | | arm, missing arm64 commit)
* arm64: crypto: reduce priority of core AES cipherArd Biesheuvel2017-12-211-1/+1
| | | | | | | | | | | | | | | The asynchronous, merged implementations of AES in CBC, CTR and XTS modes are preferred when available (i.e., when instantiating ablkciphers explicitly). However, the synchronous core AES cipher combined with the generic CBC mode implementation will produce a 'cbc(aes)' blkcipher that is callable asynchronously as well. To prevent this implementation from being used when the accelerated asynchronous implemenation is also available, lower its priority to 250 (i.e., below the asynchronous module's priority of 300). Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: franciscofranco <franciscofranco.1990@gmail.com>
* crypto: arm64/crc32 - bring in line with generic CRC32Ard Biesheuvel2017-12-211-3/+19
| | | | | | | | | The arm64 CRC32 (not CRC32c) implementation was not quite doing the same thing as the generic one. Fix that. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Acked-by: Steve Capper <steve.capper@linaro.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: crc32 - Add ARM64 CRC32 hw accelerated moduleYazen Ghannam2017-12-213-0/+282
| | | | | | | | | | | | | | | | This module registers a crc32 algorithm and a crc32c algorithm that use the optional CRC32 and CRC32C instructions in ARMv8. Tested on AMD Seattle. Improvement compared to crc32c-generic algorithm: TCRYPT CRC32C speed test shows ~450% speedup. Simple dd write tests to btrfs filesystem show ~30% speedup. Signed-off-by: Yazen Ghannam <yazen.ghannam@linaro.org> Acked-by: Steve Capper <steve.capper@linaro.org> Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* defconfig: regenMister Oyster2017-12-191-4/+3
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* defconfig: enable CGROUP_FREEZERMister Oyster2017-12-191-1/+1
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* log: Initial dmesg pruningNathan Chancellor2017-12-183-3/+3
| | | | | | | | | These are all of the annoying messages on just the stock kernel... More to follow in future patches! Signed-off-by: Nathan Chancellor <natechancellor@gmail.com> Signed-off-by: Mister Oyster <oysterized@gmail.com>
* BACKPORT: arm64: cpuinfo: Missing NULL terminator in compat_hwcap_strJulien Grall2017-12-181-1/+2
| | | | | | | | | | | | | | | | | | | | | | | The loop that browses the array compat_hwcap_str will stop when a NULL is encountered, however NULL is missing at the end of array. This will lead to overrun until a NULL is found somewhere in the following memory. In reality, this works out because the compat_hwcap2_str array tends to follow immediately in memory, and that *is* terminated correctly. Furthermore, the unsigned int compat_elf_hwcap is checked before printing each capability, so we end up doing the right thing because the size of the two arrays is less than 32. Still, this is an obvious mistake and should be fixed. Note for backporting: commit 12d11817eaafa414 ("arm64: Move /proc/cpuinfo handling code") moved this code in v4.4. Prior to that commit, the same change should be made in arch/arm64/kernel/setup.c. Bug: 37430238 Fixes: 44b82b7700d0 "arm64: Fix up /proc/cpuinfo" Cc: <stable@vger.kernel.org> # v3.19+ (but see note above prior to v4.4) Signed-off-by: Julien Grall <julien.grall@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: David Lin <dtwlin@google.com>
* arch/arm64: skip randomization within stackYi-wei Zhao2017-12-181-2/+0
| | | | | | | | | | | | | | It's a WA to make 32-bit dhrystone generate consistent scores during "sustained peformance mode" cts test. Change-Id: Ib146224ff0701899640cbaba649227aba85534a0 Signed-off-by: Yi-wei Zhao <gbjc64@motorola.com> Reviewed-on: https://gerrit.mot.com/902751 SME-Granted: SME Approvals Granted SLTApproved: Slta Waiver <sltawvr@motorola.com> Tested-by: Jira Key <jirakey@motorola.com> Reviewed-by: Igor Kovalenko <igork@motorola.com> Submit-Approved: Jira Key <jirakey@motorola.com>
* UPSTREAM: arm64: compat: Remove leftover variable declarationKevin Brodsky2017-12-141-2/+0
| | | | | | | | | | | | | | | | | | (cherry picked from commit 82d24d114f249d919b918ff8eefde4117db8f088) Commit a1d5ebaf8ccd ("arm64: big-endian: don't treat code as data when copying sigret code") moved the 32-bit sigreturn trampoline code from the aarch32_sigret_code array to kuser32.S. The commit removed the array definition from signal32.c, but not its declaration in signal32.h. Remove the leftover declaration. Signed-off-by: Kevin Brodsky <kevin.brodsky@arm.com> Signed-off-by: Mark Salyzyn <salyzyn@android.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Bug: 20045882 Bug: 63737556 Change-Id: Ic8a5f0e367f0ecd5c5ddd9e3885d0285f91cf89e Signed-off-by: Mister Oyster <oysterized@gmail.com>
* arm64: big-endian: don't treat code as data when copying sigret codeMatthew Leach2017-12-144-30/+45
| | | | | | | | | | | | | | | Currently the sigreturn compat code is copied to an offset in the vectors table. When using a BE kernel this data will be stored in the wrong endianess so when returning from a signal on a 32-bit BE system, arbitrary code will be executed. Instead of declaring the code inside a struct and copying that, use the assembler's .byte directives to store the code in the correct endianess regardless of platform endianess. Acked-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Matthew Leach <matthew.leach@arm.com> Signed-off-by: Mister Oyster <oysterized@gmail.com>
* FROMLIST: arm64: Avoid aligning normal memory pointers in __memcpy_{to,from}ioMark Salyzyn2017-12-141-7/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | (cherry picked from arm64/for-next/core commit 9ca255bf041ddc7698b6906dbd846c0ba64b1fe1) __memcpy_{to,from}io fall back to byte-at-a-time copying if both the source and destination pointers are not 8-byte aligned. Since one of the pointers always points at normal memory, this is unnecessary and detrimental to performance, so only do byte copying until we hit an 8-byte boundary for the device pointer. This change was motivated by performance issues in the pstore driver. On a test platform, measuring probe time for pstore, console buffer size of 1/4MB and pmsg of 1/2MB, was in the 90-107ms region. Change managed to reduce it to 10-25ms, an improvement in boot time. Cc: Kees Cook <keescook@chromium.org> Cc: Anton Vorontsov <anton@enomsg.org> Cc: Tony Luck <tony.luck@intel.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will.deacon@arm.com> Cc: Anton Vorontsov <anton@enomsg.org> Cc: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Mark Salyzyn <salyzyn@android.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Bug: 63716230 Change-Id: I245545e8243a54b44d30fbb0d0c71a9b8a77ef63
* UPSTREAM: arm64: optimize memcpy_{from,to}io() and memset_io()Joonwoo Park2017-12-141-10/+56
| | | | | | | | | | | | | | | | | | (cherry picked from commit 70ddb63a88bfd45eb6abe36e2bf4f8f351a447d7) Optimize memcpy_{from,to}io() and memset_io() by transferring in 64 bit as much as possible with minimized barrier usage. This simplest optimization brings faster throughput compare to current byte-by-byte read and write with barrier in the loop. Code's skeleton is taken from the powerpc. Link: http://lkml.kernel.org/p/20141020133304.GH23751@e104818-lin.cambridge.arm.com Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Reviewed-by: Trilok Soni <tsoni@codeaurora.org> Signed-off-by: Joonwoo Park <joonwoop@codeaurora.org> Signed-off-by: Will Deacon <will.deacon@arm.com> Bug: 63716230 Change-Id: I27a3ecfcdb8d1e80ceac5eb5f71609283e0c901b
* UPSTREAM: arm64: vdso: fix clock_getres for 4GiB-aligned resMark Rutland2017-12-141-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | (cherry pick from commit c80ed088a519da53f27b798a69748eaabc66aadf) The vdso tries to check for a NULL res pointer in __kernel_clock_getres, but only checks the lower 32 bits as is uses CBZ on the W register the res pointer is held in. Thus, if the res pointer happened to be aligned to a 4GiB boundary, we'd spuriously skip storing the timespec to it, while returning a zero error code to the caller. Prevent this by checking the whole pointer, using CBZ on the X register the res pointer is held in. Fixes: 9031fefde6f2ac1d ("arm64: VDSO support") Signed-off-by: Mark Rutland <mark.rutland@arm.com> Reported-by: Andrew Pinski <apinski@cavium.com> Reported-by: Mark Salyzyn <salyzyn@android.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will.deacon@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Bug: 20045882 Bug: 63737556 Change-Id: Iab5449d8515f9d655e792e3d7ce43a8f016fa2a0
* UPSTREAM: arm64: vdso: minor ABI fix for clock_getresNathan Lynch2017-12-141-1/+1
| | | | | | | | | | | | | | | | | | | | | | (cherry picked from commit e1b6b6ce55a0a25c8aa8af019095253b2133a41a) The vdso implementation of clock_getres currently returns 0 (success) whenever a null timespec is provided by the caller, regardless of the clock id supplied. This behavior is incorrect. It should fall back to syscall when an unrecognized clock id is passed, even when the timespec argument is null. This ensures that clock_getres always returns an error for invalid clock ids. Signed-off-by: Nathan Lynch <nathan_lynch@mentor.com> Acked-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Bug: 20045882 Bug: 63737556 Bug: 69626243 Change-Id: I93caac645d807403cab85245a33faf6439c6f3c1 Signed-off-by: Mister Oyster <oysterized@gmail.com>
* arm: don't force DMA_API_DEBUG on arm/arm64Mister Oyster2017-12-142-2/+0
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* arm: don't force IRQ_DOMAIN_DEBUG on mt67xx archMister Oyster2017-12-143-12/+2
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* defconfig: add chacha20_neonMister Oyster2017-12-141-0/+1
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* UPSTREAM: crypto: arm/chacha20 - implement NEON version based on SSE3 codeArd Biesheuvel2017-12-143-0/+661
| | | | | | | | | | | | This is a straight port to ARM/NEON of the x86 SSE3 implementation of the ChaCha20 stream cipher. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au> (cherry picked from commit 8096667273477e735b0072b11a6d617ccee45e5f, fixed merge conflicts in Kconfig and Makefile) Change-Id: Id5d32a41a3ec036b9cffe0b739321eede4c92d0a Signed-off-by: Eric Biggers <ebiggers@google.com>
* defconfig: enable chacha20 algoMister Oyster2017-12-141-0/+1
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* Fix arch/arm/crypto/sha256_glue.cSami Tolvanen2017-12-141-1/+1
| | | | | | | | MODULE_ALIAS_CRYPTO is not defined, use MODULE_ALIAS. Signed-off-by: Sami Tolvanen <samitolvanen@google.com> Change-Id: I24803dbbbf7ac7889bc027f69af371b594eca835 (cherry picked from 5eb3cca16fcf9c62753058aaf73bb12b71acba79)
* arm64: Remove nr parameter from secure_computingbillchen1977@gmail.com2017-12-051-1/+1
| | | | Change-Id: I2afff0e5ea7fe12843ef2e48a5d7eba3216fd8ce
* seccomp,x86,arm,mips,s390: Remove nr parameter from secure_computingAndy Lutomirski2017-12-054-4/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The secure_computing function took a syscall number parameter, but it only paid any attention to that parameter if seccomp mode 1 was enabled. Rather than coming up with a kludge to get the parameter to work in mode 2, just remove the parameter. To avoid churn in arches that don't have seccomp filters (and may not even support syscall_get_nr right now), this leaves the parameter in secure_computing_strict, which is now a real function. For ARM, this is a bit ugly due to the fact that ARM conditionally supports seccomp filters. Fixing that would probably only be a couple of lines of code, but it should be coordinated with the audit maintainers. This will be a slight slowdown on some arches. The right fix is to pass in all of seccomp_data instead of trying to make just the syscall nr part be fast. This is a prerequisite for making two-phase seccomp work cleanly. Cc: Russell King <linux@arm.linux.org.uk> Cc: linux-arm-kernel@lists.infradead.org Cc: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org Cc: Martin Schwidefsky <schwidefsky@de.ibm.com> Cc: Heiko Carstens <heiko.carstens@de.ibm.com> Cc: linux-s390@vger.kernel.org Cc: x86@kernel.org Cc: Kees Cook <keescook@chromium.org> Signed-off-by: Andy Lutomirski <luto@amacapital.net> Signed-off-by: Kees Cook <keescook@chromium.org>
* arm64/ptrace: Preserve previous registers for short regset writeDave Martin2017-12-051-1/+2
| | | | | | | | | | | | Ensure that if userspace supplies insufficient data to PTRACE_SETREGSET to fill all the registers, the thread's old registers are preserved. Cc: <stable@vger.kernel.org> # 3.19.x- Fixes: 766a85d7bc5d ("arm64: ptrace: add NT_ARM_SYSTEM_CALL regset") Signed-off-by: Dave Martin <Dave.Martin@arm.com> Acked-by: Will Deacon <Will.Deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
* format-security: move static strings to constKees Cook2017-12-053-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | While examining output from trial builds with -Wformat-security enabled, many strings were found that should be defined as "const", or as a char array instead of char pointer. This makes some static analysis easier, by producing fewer false positives. As these are all trivial changes, it seemed best to put them all in a single patch rather than chopping them up per maintainer. Link: http://lkml.kernel.org/r/20170405214711.GA5711@beast Signed-off-by: Kees Cook <keescook@chromium.org> Acked-by: Jes Sorensen <jes@trained-monkey.org> [runner.c] Cc: Tony Lindgren <tony@atomide.com> Cc: Russell King <linux@armlinux.org.uk> Cc: "Maciej W. Rozycki" <macro@linux-mips.org> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: "Rafael J. Wysocki" <rjw@rjwysocki.net> Cc: Viresh Kumar <viresh.kumar@linaro.org> Cc: Daniel Vetter <daniel.vetter@intel.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Sean Paul <seanpaul@chromium.org> Cc: David Airlie <airlied@linux.ie> Cc: Yisen Zhuang <yisen.zhuang@huawei.com> Cc: Salil Mehta <salil.mehta@huawei.com> Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Cc: Jiri Slaby <jslaby@suse.com> Cc: Patrice Chotard <patrice.chotard@st.com> Cc: "David S. Miller" <davem@davemloft.net> Cc: James Hogan <james.hogan@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Matt Redfearn <matt.redfearn@imgtec.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Ingo Molnar <mingo@kernel.org> Cc: Rasmus Villemoes <linux@rasmusvillemoes.dk> Cc: Mugunthan V N <mugunthanvnm@ti.com> Cc: Felipe Balbi <felipe.balbi@linux.intel.com> Cc: Jarod Wilson <jarod@redhat.com> Cc: Florian Westphal <fw@strlen.de> Cc: Antonio Quartulli <a@unstable.cc> Cc: Dmitry Torokhov <dmitry.torokhov@gmail.com> Cc: Kejian Yan <yankejian@huawei.com> Cc: Daode Huang <huangdaode@hisilicon.com> Cc: Qianqian Xie <xieqianqian@huawei.com> Cc: Philippe Reynes <tremyfr@gmail.com> Cc: Colin Ian King <colin.king@canonical.com> Cc: Eric Dumazet <edumazet@google.com> Cc: Christian Gromm <christian.gromm@microchip.com> Cc: Andrey Shvetsov <andrey.shvetsov@k2l.de> Cc: Jason Litzinger <jlitzingerdev@gmail.com> Cc: WANG Cong <xiyou.wangcong@gmail.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
* Revert "power: make sync on suspend optional"Moyster2017-12-013-3/+0
| | | | | | seems like gueste kanged franciscofranco, sorry for that :D This reverts commit e68ce258c35d28b497cdb11e1e5e9949f660d1ed.
* defconfig: enable the same ipv4 & ipv6 netfilter configsMoyster2017-12-011-1/+1
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