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* crypto: arm64/aes-blk - honour iv_out requirement in CBC and CTR modesArd Biesheuvel2017-12-211-46/+42
| | | | | | | | | | | | | Update the ARMv8 Crypto Extensions and the plain NEON AES implementations in CBC and CTR modes to return the next IV back to the skcipher API client. This is necessary for chaining to work correctly. Note that for CTR, this is only done if the request is a round multiple of the block size, since otherwise, chaining is impossible anyway. Cc: <stable@vger.kernel.org> # v3.16+ Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* defconfig: enable all optimized crypto algos (chacha20_neon impl. is for ↵Mister Oyster2017-12-211-7/+7
| | | | arm, missing arm64 commit)
* arm64: crypto: reduce priority of core AES cipherArd Biesheuvel2017-12-211-1/+1
| | | | | | | | | | | | | | | The asynchronous, merged implementations of AES in CBC, CTR and XTS modes are preferred when available (i.e., when instantiating ablkciphers explicitly). However, the synchronous core AES cipher combined with the generic CBC mode implementation will produce a 'cbc(aes)' blkcipher that is callable asynchronously as well. To prevent this implementation from being used when the accelerated asynchronous implemenation is also available, lower its priority to 250 (i.e., below the asynchronous module's priority of 300). Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: franciscofranco <franciscofranco.1990@gmail.com>
* crypto: arm64/crc32 - bring in line with generic CRC32Ard Biesheuvel2017-12-211-3/+19
| | | | | | | | | The arm64 CRC32 (not CRC32c) implementation was not quite doing the same thing as the generic one. Fix that. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Acked-by: Steve Capper <steve.capper@linaro.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: crc32 - Add ARM64 CRC32 hw accelerated moduleYazen Ghannam2017-12-213-0/+282
| | | | | | | | | | | | | | | | This module registers a crc32 algorithm and a crc32c algorithm that use the optional CRC32 and CRC32C instructions in ARMv8. Tested on AMD Seattle. Improvement compared to crc32c-generic algorithm: TCRYPT CRC32C speed test shows ~450% speedup. Simple dd write tests to btrfs filesystem show ~30% speedup. Signed-off-by: Yazen Ghannam <yazen.ghannam@linaro.org> Acked-by: Steve Capper <steve.capper@linaro.org> Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* defconfig: regenMister Oyster2017-12-191-4/+3
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* defconfig: enable CGROUP_FREEZERMister Oyster2017-12-191-1/+1
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* log: Initial dmesg pruningNathan Chancellor2017-12-182-2/+2
| | | | | | | | | These are all of the annoying messages on just the stock kernel... More to follow in future patches! Signed-off-by: Nathan Chancellor <natechancellor@gmail.com> Signed-off-by: Mister Oyster <oysterized@gmail.com>
* BACKPORT: arm64: cpuinfo: Missing NULL terminator in compat_hwcap_strJulien Grall2017-12-181-1/+2
| | | | | | | | | | | | | | | | | | | | | | | The loop that browses the array compat_hwcap_str will stop when a NULL is encountered, however NULL is missing at the end of array. This will lead to overrun until a NULL is found somewhere in the following memory. In reality, this works out because the compat_hwcap2_str array tends to follow immediately in memory, and that *is* terminated correctly. Furthermore, the unsigned int compat_elf_hwcap is checked before printing each capability, so we end up doing the right thing because the size of the two arrays is less than 32. Still, this is an obvious mistake and should be fixed. Note for backporting: commit 12d11817eaafa414 ("arm64: Move /proc/cpuinfo handling code") moved this code in v4.4. Prior to that commit, the same change should be made in arch/arm64/kernel/setup.c. Bug: 37430238 Fixes: 44b82b7700d0 "arm64: Fix up /proc/cpuinfo" Cc: <stable@vger.kernel.org> # v3.19+ (but see note above prior to v4.4) Signed-off-by: Julien Grall <julien.grall@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: David Lin <dtwlin@google.com>
* arch/arm64: skip randomization within stackYi-wei Zhao2017-12-181-2/+0
| | | | | | | | | | | | | | It's a WA to make 32-bit dhrystone generate consistent scores during "sustained peformance mode" cts test. Change-Id: Ib146224ff0701899640cbaba649227aba85534a0 Signed-off-by: Yi-wei Zhao <gbjc64@motorola.com> Reviewed-on: https://gerrit.mot.com/902751 SME-Granted: SME Approvals Granted SLTApproved: Slta Waiver <sltawvr@motorola.com> Tested-by: Jira Key <jirakey@motorola.com> Reviewed-by: Igor Kovalenko <igork@motorola.com> Submit-Approved: Jira Key <jirakey@motorola.com>
* UPSTREAM: arm64: compat: Remove leftover variable declarationKevin Brodsky2017-12-141-2/+0
| | | | | | | | | | | | | | | | | | (cherry picked from commit 82d24d114f249d919b918ff8eefde4117db8f088) Commit a1d5ebaf8ccd ("arm64: big-endian: don't treat code as data when copying sigret code") moved the 32-bit sigreturn trampoline code from the aarch32_sigret_code array to kuser32.S. The commit removed the array definition from signal32.c, but not its declaration in signal32.h. Remove the leftover declaration. Signed-off-by: Kevin Brodsky <kevin.brodsky@arm.com> Signed-off-by: Mark Salyzyn <salyzyn@android.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Bug: 20045882 Bug: 63737556 Change-Id: Ic8a5f0e367f0ecd5c5ddd9e3885d0285f91cf89e Signed-off-by: Mister Oyster <oysterized@gmail.com>
* arm64: big-endian: don't treat code as data when copying sigret codeMatthew Leach2017-12-144-30/+45
| | | | | | | | | | | | | | | Currently the sigreturn compat code is copied to an offset in the vectors table. When using a BE kernel this data will be stored in the wrong endianess so when returning from a signal on a 32-bit BE system, arbitrary code will be executed. Instead of declaring the code inside a struct and copying that, use the assembler's .byte directives to store the code in the correct endianess regardless of platform endianess. Acked-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Matthew Leach <matthew.leach@arm.com> Signed-off-by: Mister Oyster <oysterized@gmail.com>
* FROMLIST: arm64: Avoid aligning normal memory pointers in __memcpy_{to,from}ioMark Salyzyn2017-12-141-7/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | (cherry picked from arm64/for-next/core commit 9ca255bf041ddc7698b6906dbd846c0ba64b1fe1) __memcpy_{to,from}io fall back to byte-at-a-time copying if both the source and destination pointers are not 8-byte aligned. Since one of the pointers always points at normal memory, this is unnecessary and detrimental to performance, so only do byte copying until we hit an 8-byte boundary for the device pointer. This change was motivated by performance issues in the pstore driver. On a test platform, measuring probe time for pstore, console buffer size of 1/4MB and pmsg of 1/2MB, was in the 90-107ms region. Change managed to reduce it to 10-25ms, an improvement in boot time. Cc: Kees Cook <keescook@chromium.org> Cc: Anton Vorontsov <anton@enomsg.org> Cc: Tony Luck <tony.luck@intel.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will.deacon@arm.com> Cc: Anton Vorontsov <anton@enomsg.org> Cc: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Mark Salyzyn <salyzyn@android.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Bug: 63716230 Change-Id: I245545e8243a54b44d30fbb0d0c71a9b8a77ef63
* UPSTREAM: arm64: optimize memcpy_{from,to}io() and memset_io()Joonwoo Park2017-12-141-10/+56
| | | | | | | | | | | | | | | | | | (cherry picked from commit 70ddb63a88bfd45eb6abe36e2bf4f8f351a447d7) Optimize memcpy_{from,to}io() and memset_io() by transferring in 64 bit as much as possible with minimized barrier usage. This simplest optimization brings faster throughput compare to current byte-by-byte read and write with barrier in the loop. Code's skeleton is taken from the powerpc. Link: http://lkml.kernel.org/p/20141020133304.GH23751@e104818-lin.cambridge.arm.com Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Reviewed-by: Trilok Soni <tsoni@codeaurora.org> Signed-off-by: Joonwoo Park <joonwoop@codeaurora.org> Signed-off-by: Will Deacon <will.deacon@arm.com> Bug: 63716230 Change-Id: I27a3ecfcdb8d1e80ceac5eb5f71609283e0c901b
* UPSTREAM: arm64: vdso: fix clock_getres for 4GiB-aligned resMark Rutland2017-12-141-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | (cherry pick from commit c80ed088a519da53f27b798a69748eaabc66aadf) The vdso tries to check for a NULL res pointer in __kernel_clock_getres, but only checks the lower 32 bits as is uses CBZ on the W register the res pointer is held in. Thus, if the res pointer happened to be aligned to a 4GiB boundary, we'd spuriously skip storing the timespec to it, while returning a zero error code to the caller. Prevent this by checking the whole pointer, using CBZ on the X register the res pointer is held in. Fixes: 9031fefde6f2ac1d ("arm64: VDSO support") Signed-off-by: Mark Rutland <mark.rutland@arm.com> Reported-by: Andrew Pinski <apinski@cavium.com> Reported-by: Mark Salyzyn <salyzyn@android.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will.deacon@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Bug: 20045882 Bug: 63737556 Change-Id: Iab5449d8515f9d655e792e3d7ce43a8f016fa2a0
* UPSTREAM: arm64: vdso: minor ABI fix for clock_getresNathan Lynch2017-12-141-1/+1
| | | | | | | | | | | | | | | | | | | | | | (cherry picked from commit e1b6b6ce55a0a25c8aa8af019095253b2133a41a) The vdso implementation of clock_getres currently returns 0 (success) whenever a null timespec is provided by the caller, regardless of the clock id supplied. This behavior is incorrect. It should fall back to syscall when an unrecognized clock id is passed, even when the timespec argument is null. This ensures that clock_getres always returns an error for invalid clock ids. Signed-off-by: Nathan Lynch <nathan_lynch@mentor.com> Acked-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Bug: 20045882 Bug: 63737556 Bug: 69626243 Change-Id: I93caac645d807403cab85245a33faf6439c6f3c1 Signed-off-by: Mister Oyster <oysterized@gmail.com>
* arm: don't force DMA_API_DEBUG on arm/arm64Mister Oyster2017-12-141-1/+0
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* arm: don't force IRQ_DOMAIN_DEBUG on mt67xx archMister Oyster2017-12-142-7/+2
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* defconfig: add chacha20_neonMister Oyster2017-12-141-0/+1
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* defconfig: enable chacha20 algoMister Oyster2017-12-141-0/+1
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* arm64: Remove nr parameter from secure_computingbillchen1977@gmail.com2017-12-051-1/+1
| | | | Change-Id: I2afff0e5ea7fe12843ef2e48a5d7eba3216fd8ce
* arm64/ptrace: Preserve previous registers for short regset writeDave Martin2017-12-051-1/+2
| | | | | | | | | | | | Ensure that if userspace supplies insufficient data to PTRACE_SETREGSET to fill all the registers, the thread's old registers are preserved. Cc: <stable@vger.kernel.org> # 3.19.x- Fixes: 766a85d7bc5d ("arm64: ptrace: add NT_ARM_SYSTEM_CALL regset") Signed-off-by: Dave Martin <Dave.Martin@arm.com> Acked-by: Will Deacon <Will.Deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
* Revert "power: make sync on suspend optional"Moyster2017-12-013-3/+0
| | | | | | seems like gueste kanged franciscofranco, sorry for that :D This reverts commit e68ce258c35d28b497cdb11e1e5e9949f660d1ed.
* defconfig: enable the same ipv4 & ipv6 netfilter configsMoyster2017-12-011-1/+1
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* defconfig: regenMoyster2017-11-061-1/+1
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* arm64/configs: Enable BALANCE_ANON_FILE_RECLAIMThierry Strudel2017-10-211-0/+1
| | | | | | | | | | | BALANCE_ANON_FILE_RECLAIM helps in improving headroom by swapping anon memory earlier. This helps saving more memory and helps overall system performance when ZRAM is enabled. Enable this config on 64 bit targets for performance reasons. Change-Id: Ib72a25457749077853582414bb504adfface3da9 Signed-off-by: Veena Sambasivan <veenas@codeaurora.org> Signed-off-by: Mister Oyster <oysterized@gmail.com>
* arm64: zero the leading stack canary byteDaniel Micay2017-10-141-0/+3
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* defconfig: hardened configMister Oyster2017-10-141-12/+12
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* defconfig: ntfs drivers don't have full rw support, use fuseMoyster2017-09-271-2/+1
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* lz4k: Remove lz4k modulealexlartsev192017-09-261-1/+0
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* defconfig: use crypto lz4Mister Oyster2017-09-251-3/+3
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* arm64: Remove TIF_POLLING_NRFLAGPeter Zijlstra2017-09-201-2/+0
| | | | | | | | | | | | | | | | The only idle method for arm64 is WFI and it therefore unconditionally requires the reschedule interrupt when idle. Suggested-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Peter Zijlstra <peterz@infradead.org> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Link: http://lkml.kernel.org/r/20140509170649.GG13658@twins.programming.kicks-ass.net Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Ingo Molnar <mingo@kernel.org> Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git Git-commit: 842514849a616e9b61acad65771c7afe01e651f9 [joonwoop@codeaurora.org: fixed trivial merge conflict.] Signed-off-by: Joonwoo Park <joonwoop@codeaurora.org>
* arm64: process management: Add TIF_MM_RELEASEDAbhimanyu Kapur2017-09-201-0/+2
| | | | | | | | | | Add a new task info flag to represent a task whose mm struct has been freed. This is used by the android low memory killer to track tasks whose mm struct has been freed. Change-Id: Id72e67e31fb52e07f01fb6e234b102f63b400aa5 Signed-off-by: Abhimanyu Kapur <abhimany@codeaurora.org>
* defconfig: regenMister Oyster2017-09-161-0/+1
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* lib: vsprintf: whitelist stack tracesDave Weinstein2017-09-141-2/+2
| | | | | | | | | Use the %pP functionality to explicitly allow kernel pointers to be logged for stack traces BUG: 30368199 Change-Id: I495915465565293e9e4da5aa28fbd1d14538d99b Signed-off-by: Dave Weinstein <olorin@google.com>
* defconfig: disable config_have_xlog_featureMister Oyster2017-09-051-1/+1
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* defconfig: disable CONFIG_MTK_COMBO_DISABLE_5G_FOR_P2PMister Oyster2017-09-051-1/+1
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* defconfig: enable rumble/leds on xbox360 controllers & regen defconfigMoyster2017-09-051-4/+26
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* defconfig: Enable usb host driver for joystick/gamepadHemant Kumar2017-09-051-0/+2
| | | | | | | | | | Current kernel configuration does not support joystick/gamepads. Controllers like Logitech F710 requires this driver to work. CRs-Fixed: 758193 Change-Id: Id2e75e019eff3855b5fa2cc778093af68aef1511 Signed-off-by: Hemant Kumar <hemantk@codeaurora.org> Signed-off-by: Moyster <oysterized@gmail.com>
* crypto: xts - fix compile errorsStephan Mueller2017-08-311-0/+1
| | | | | | | | Commit 28856a9e52c7 missed the addition of the crypto/xts.h include file for different architecture-specific AES implementations. Signed-off-by: Stephan Mueller <smueller@chronox.de> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: xts - consolidate sanity check for keysStephan Mueller2017-08-311-0/+4
| | | | | | | | | | | | | | | The patch centralizes the XTS key check logic into the service function xts_check_key which is invoked from the different XTS implementations. With this, the XTS implementations in ARM, ARM64, PPC and S390 have now a sanity check for the XTS keys similar to the other arches. In addition, this service function received a check to ensure that the key != the tweak key which is mandated by FIPS 140-2 IG A.9. As the check is not present in the standards defining XTS, it is only enforced in FIPS mode of the kernel. Signed-off-by: Stephan Mueller <smueller@chronox.de> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* crypto: arm64/aes-ctr - fix NULL dereference in tail processingArd Biesheuvel2017-08-311-1/+1
| | | | | | | | | | | | | | | | | | | | | The AES-CTR glue code avoids calling into the blkcipher API for the tail portion of the walk, by comparing the remainder of walk.nbytes modulo AES_BLOCK_SIZE with the residual nbytes, and jumping straight into the tail processing block if they are equal. This tail processing block checks whether nbytes != 0, and does nothing otherwise. However, in case of an allocation failure in the blkcipher layer, we may enter this code with walk.nbytes == 0, while nbytes > 0. In this case, we should not dereference the source and destination pointers, since they may be NULL. So instead of checking for nbytes != 0, check for (walk.nbytes % AES_BLOCK_SIZE) != 0, which implies the former in non-error conditions. Fixes: 49788fe2a128 ("arm64/crypto: AES-ECB/CBC/CTR/XTS using ARMv8 NEON and Crypto Extensions") Cc: stable@vger.kernel.org Reported-by: xiakaixu <xiakaixu@huawei.com> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* arm64: crypto: assure that ECB modes don't require an IVJeremy Linton2017-08-311-2/+2
| | | | | | | | | ECB modes don't use an initialization vector. The kernel /proc/crypto interface doesn't reflect this properly. Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Jeremy Linton <jeremy.linton@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
* arm64/crypto: remove redundant update of dataColin Ian King2017-08-311-1/+0
| | | | | | | | | | | | | | | Originally found by cppcheck: [arch/arm64/crypto/sha2-ce-glue.c:153]: (warning) Assignment of function parameter has no effect outside the function. Did you forget dereferencing it? Updating data by blocks * SHA256_BLOCK_SIZE at the end of sha2_finup is redundant code and can be removed. Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
* arm64: mm: fix show_pte KERN_CONT falloutMark Rutland2017-08-311-3/+4
| | | | | | | | | | | | | | | | | | | | Recent changes made KERN_CONT mandatory for continued lines. In the absence of KERN_CONT, a newline may be implicit inserted by the core printk code. In show_pte, we (erroneously) use printk without KERN_CONT for continued prints, resulting in output being split across a number of lines, and not matching the intended output, e.g. [ff000000000000] *pgd=00000009f511b003 , *pud=00000009f4a80003 , *pmd=0000000000000000 Fix this by using pr_cont() for all the continuations. Acked-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
* defconfig enable ntfs driversMister Oyster2017-08-311-1/+3
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* defconfig: enable exfat driversMister Oyster2017-08-311-0/+7
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* arm64: kernel: add missing __init section marker to cpu_suspend_initLorenzo Pieralisi2017-07-111-1/+1
| | | | | | | | | | | | | | | | Suspend init function must be marked as __init, since it is not needed after the kernel has booted. This patch moves the cpu_suspend_init() function to the __init section. Change-Id: I380b7013eb68ecf7bc0abe11dc5442142310f1b1 Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Git-commit: 18ab7db6b749ac27aac08d572afbbd2f4d937934 Git-repo: https://git.kernel.org/scm/linux/kernel/git/stable/linux-stable.git Signed-off-by: Mahesh Sivasubramanian <msivasub@codeaurora.org> Signed-off-by: Archana Sathyakumar <asathyak@codeaurora.org> Signed-off-by: Murali Nalajala <mnalajal@codeaurora.org> Signed-off-by: Maulik Shah <mkshah@codeaurora.org>
* defconfig: regen .107Mister Oyster2017-07-041-1/+1
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* defconfig: enable hwbinder domainMister Oyster2017-06-181-0/+1
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