diff options
Diffstat (limited to 'include/linux/mu3d')
| -rw-r--r-- | include/linux/mu3d/hal/mu3d_hal_comm.h | 172 | ||||
| -rw-r--r-- | include/linux/mu3d/hal/mu3d_hal_hw.h | 286 | ||||
| -rw-r--r-- | include/linux/mu3d/hal/mu3d_hal_osal.h | 76 | ||||
| -rw-r--r-- | include/linux/mu3d/hal/mu3d_hal_phy.h | 28 | ||||
| -rw-r--r-- | include/linux/mu3d/hal/mu3d_hal_qmu_drv.h | 277 | ||||
| -rw-r--r-- | include/linux/mu3d/hal/mu3d_hal_usb_drv.h | 188 | ||||
| -rw-r--r-- | include/linux/mu3d/hal/ssusb_dev_c_header.h | 3727 | ||||
| -rw-r--r-- | include/linux/mu3d/hal/ssusb_epctl_csr_c_header.h | 187 | ||||
| -rw-r--r-- | include/linux/mu3d/hal/ssusb_sifslv_ippc_c_header.h | 728 | ||||
| -rw-r--r-- | include/linux/mu3d/hal/ssusb_usb2_csr_c_header.h | 294 | ||||
| -rw-r--r-- | include/linux/mu3d/hal/ssusb_usb3_mac_csr_c_header.h | 423 | ||||
| -rw-r--r-- | include/linux/mu3d/hal/ssusb_usb3_sys_csr_c_header.h | 318 | ||||
| -rw-r--r-- | include/linux/mu3d/test_drv/mu3d_test_qmu_drv.h | 52 | ||||
| -rw-r--r-- | include/linux/mu3d/test_drv/mu3d_test_test.h | 5 | ||||
| -rw-r--r-- | include/linux/mu3d/test_drv/mu3d_test_unified.h | 37 | ||||
| -rw-r--r-- | include/linux/mu3d/test_drv/mu3d_test_usb_drv.h | 336 |
16 files changed, 7134 insertions, 0 deletions
diff --git a/include/linux/mu3d/hal/mu3d_hal_comm.h b/include/linux/mu3d/hal/mu3d_hal_comm.h new file mode 100644 index 000000000..efc8851d7 --- /dev/null +++ b/include/linux/mu3d/hal/mu3d_hal_comm.h @@ -0,0 +1,172 @@ +#ifndef _DRV_COMM_H +#define _DRV_COMM_H +#include <linux/mu3d/hal/mu3d_hal_hw.h> +#include <linux/io.h> + +#undef EXTERN + +#ifdef _DRV_COMM_H +#define EXTERN +#else +#define EXTERN extern +#endif + + +/* CONSTANTS */ + +#ifndef FALSE + #define FALSE 0 +#endif + +#ifndef TRUE + #define TRUE 1 +#endif + +/* TYPES */ + +typedef unsigned int DEV_UINT32; +typedef int DEV_INT32; +typedef unsigned short DEV_UINT16; +typedef short DEV_INT16; +typedef unsigned char DEV_UINT8; +typedef char DEV_INT8; + +typedef enum { + RET_SUCCESS = 0, + RET_FAIL, +} USB_RESULT; + +#ifdef NEVER +#define os_writeb(addr,data) {\ + (*((volatile DEV_UINT8 *)(addr)) = (DEV_UINT8)data);\ + if(0) printk("****** os_writeb [0x%08x] = 0x%08x (%s#%d)\n", (unsigned int)addr, data, __func__, __LINE__);\ + } + +#define os_writew(addr,data) {\ + (*((volatile DEV_UINT16 *)(addr)) = (DEV_UINT16)data);\ + if(0) printk("****** os_writew [0x%08x] = 0x%08x (%s#%d)\n", (unsigned int)addr, data, __func__, __LINE__);\ + } + +#define os_writel(addr,data) {\ + (*((volatile DEV_UINT32 *)(addr)) = (DEV_UINT32)data);\ + if(0) printk("****** os_writel [0x%08x] = 0x%08x (%s#%d)\n", (unsigned int)addr, data, __func__, __LINE__);\ + } + +#define os_readl(addr) *((volatile DEV_UINT32 *)(addr)) +#define os_writelmsk(addr, data, msk) \ + { os_writel(addr, ((os_readl(addr) & ~(msk)) | ((data) & (msk)))); \ + } +#define os_setmsk(addr, msk) \ + { os_writel(addr, os_readl(addr) | msk); \ + } +#define os_clrmsk(addr, msk) \ + { os_writel(addr, os_readl(addr) &~ msk); \ + } +/*msk the data first, then umsk with the umsk.*/ +#define os_writelmskumsk(addr, data, msk, umsk) \ +{\ + os_writel(addr, ((os_readl(addr) & ~(msk)) | ((data) & (msk))) & (umsk));\ +} + +#define USB_END_OFFSET(_bEnd, _bOffset) ((0x10*(_bEnd-1)) + _bOffset) +#define USB_ReadCsr32(_bOffset, _bEnd) \ + os_readl(USB_END_OFFSET(_bEnd, _bOffset)) +#define USB_WriteCsr32( _bOffset, _bEnd, _bData) \ + os_writel( USB_END_OFFSET(_bEnd, _bOffset), _bData) +#else +static inline void os_writeb( void __iomem *addr, unsigned char data) +{ + writeb(data, (void __iomem *)addr); + if(0) printk("%s writeb [%p] = 0x%08x\n", __func__, (void *)addr, data); +} + +static inline void os_writew( void __iomem *addr, unsigned short data) +{ + writew(data, (void __iomem *)addr); + if(0) printk("%s writew [%p] = 0x%08x\n", __func__, (void *)addr, data); +} + +static inline void os_writel( void __iomem *addr, unsigned int data) +{ + writel(data, (void __iomem *)addr); + if(0) printk("%s writel [%p] = 0x%08x\n", __func__, (void *)addr, data); +} + +#define os_readl(addr) readl((void __iomem *)((unsigned long)addr)) + +static inline void os_writelmsk( void __iomem *addr, unsigned int data, unsigned int msk) +{ + unsigned int tmp = readl((void __iomem *)addr); + mb(); + writel(((tmp & ~(msk)) | ((data) & (msk))), (void __iomem *)addr); +} + +static inline void os_setmsk( void __iomem *addr, unsigned int msk) +{ + unsigned int tmp = readl((void __iomem *)addr); + if(0) printk("%s setmsk [%p] = 0x%08x\n", __func__, (void *)addr, tmp); + mb(); + writel((tmp | msk), (void __iomem *)addr); + if(0) printk("%s setmsk [%p] = 0x%08x\n", __func__, (void *)addr, readl((void __iomem *)addr)); +} + +static inline void os_clrmsk( void __iomem *addr, unsigned int msk) +{ + unsigned int tmp = readl((void __iomem *)addr); + if(0) printk("%s clrmsk [%p] = 0x%08x\n", __func__, (void *)addr, tmp); + mb(); + writel((tmp & ~(msk)), (void __iomem *)addr); + if(0) printk("%s clrmsk [%p] = 0x%08x\n", __func__, (void *)addr, readl((void __iomem *)addr)); +} + +/*msk the data first, then umsk with the umsk.*/ +static inline void os_writelmskumsk( void __iomem *addr, unsigned int data, + unsigned int msk, unsigned int umsk) +{ + unsigned int tmp = readl((void __iomem *)addr); + mb(); + writel(((tmp & ~(msk)) | ((data) & (msk))) & (umsk), (void __iomem *)addr); +} + +static inline int wait_for_value( void __iomem *addr, unsigned int msk, + unsigned int value, unsigned int ms_intvl, unsigned int count) +{ + u32 i; + for (i = 0; i < count; i++) { + if ((os_readl(addr) & msk) == value) + return RET_SUCCESS; + mb(); + mdelay(ms_intvl); + } + return RET_FAIL; +} + +static inline int wait_for_value_us( void __iomem *addr, unsigned int msk, + unsigned int value, unsigned int us_intvl, unsigned int count) +{ + u32 i; + for (i = 0; i < count; i++) { + if ((os_readl(addr) & msk) == value) + return RET_SUCCESS; + mb(); + udelay(us_intvl); + } + return RET_FAIL; +} + +#define USB_END_OFFSET(_bEnd, _bOffset) ((0x10*(_bEnd-1)) + _bOffset) + +#define USB_ReadCsr32(_bOffset, _bEnd) \ + readl((void __iomem *)(uintptr_t)(USB_END_OFFSET(_bEnd, _bOffset))) + +#define USB_WriteCsr32( _bOffset, _bEnd, _bData) \ + do{\ + writel( _bData, (void __iomem *)(uintptr_t)(USB_END_OFFSET(_bEnd, _bOffset)));\ + mb();\ + }while(0) + +#endif + +#define div_and_rnd_up(x, y) (((x) + (y) - 1) / (y)) + +#endif /*_DRV_COMM_H*/ diff --git a/include/linux/mu3d/hal/mu3d_hal_hw.h b/include/linux/mu3d/hal/mu3d_hal_hw.h new file mode 100644 index 000000000..b95505bdd --- /dev/null +++ b/include/linux/mu3d/hal/mu3d_hal_hw.h @@ -0,0 +1,286 @@ +#ifndef USB_HW_H +#define USB_HW_H + +#include <linux/types.h> + +#define SW_VERSION "20130627" + +/* U3D configuration */ + +/*This define for DVT OTG testing*/ +#ifdef CONFIG_USBIF_COMPLIANCE +#define SUPPORT_OTG +#endif +//This should be defined if superspeed is supported +#define SUPPORT_U3 +#ifdef SUPPORT_U3 + +#define U3D_DFT_SPEED SSUSB_SPEED_SUPER +#define U2_U3_SWITCH +//#define U2_U3_SWITCH_AUTO +#else +#define U3D_DFT_SPEED SSUSB_SPEED_HIGH +#endif + +#ifndef CONFIG_USB_MU3D_DRV +#define POWER_SAVING_MODE +#endif + +/* clock setting + this setting is applied ONLY for DR FPGA + please check integrator for your platform setting + */ +//OSC 125MHz/2 = 62.5MHz, ceil(62.5) = 63 +#define U3D_MAC_SYS_CK 63 +//OSC 20Mhz/2 = 10MHz +//#define U3D_MAC_REF_CK 10 +#define U3D_MAC_REF_CK 26 +//U3D_PHY_REF_CK = U3D_MAC_REF_CK on ASIC +//On FPGA, these two clocks are separated +#define U3D_PHY_REF_CK 26 + + +#define PIO_MODE 1 +#define DMA_MODE 2 +#define QMU_MODE 3 +#define BUS_MODE PIO_MODE + +#ifdef CONFIG_USBIF_COMPLIANCE +#define EP0_BUS_MODE DMA_MODE +#else +#define EP0_BUS_MODE PIO_MODE +#endif + + +#define AUTOSET +#define AUTOCLEAR +#define BOUNDARY_4K +#define DIS_ZLP_CHECK_CRC32 //disable check crc32 in zlp + +#define CS_12B 1 +#define CS_16B 2 +#define CHECKSUM_TYPE CS_16B +#define U3D_COMMAND_TIMER 10 + +#if (CHECKSUM_TYPE==CS_16B) + #define CHECKSUM_LENGTH 16 +#else + #define CHECKSUM_LENGTH 12 +#endif + +#define NO_ZLP 0 +#define HW_MODE 1 +#define GPD_MODE 2 + +#ifdef _USB_NORMAL_ +#define TXZLP NO_ZLP +#else +#define TXZLP GPD_MODE +#endif + +#define ISO_UPDATE_TEST 0 +#define ISO_UPDATE_MODE 1 + +#define LPM_STRESS 0 + +// USBIF , uevent +//#define USBIF_OTG_EVENT_DEV_CONN_TMOUT "DEV_CONN_TMOUT" +//#define USBIF_OTG_EVENT_NO_RESP_FOR_HNP_ENABLE "NO_RESP_FOR_HNP_ENABLE" +//#define USBIF_OTG_EVENT_HUB_NOT_SUPPORTED "HUB_NOT_SUPPORTED" +//#define USBIF_OTG_EVENT_DEV_NOT_SUPPORTED "DEV_NOT_SUPPORTED" +#define USBIF_OTG_EVENT_HNP_FAILED "HNP_FAILED" +#define USBIF_OTG_EVENT_NO_RESP_FOR_SRP "NO_RESP_FOR_SRP" + +/*EP number is hard code, not read from U3D_CAP_EPINFO*/ +#define HARDCODE_EP + +extern void __iomem *u3_base; +extern void __iomem *u3_sif_base; +extern void __iomem *u3_sif2_base; + +#ifdef CONFIG_MTK_FPGA +extern void __iomem *i2c1_base; +#endif + +/** + * @U3D register map + */ + +/* + * 0x1127_0000 for MAC register + */ +//4K for each, offset may differ from project to project. Please check integrator +#define SSUSB_DEV_BASE (u3_base+0x1000) +#define SSUSB_EPCTL_CSR_BASE (u3_base+0x1800) +#define SSUSB_USB3_MAC_CSR_BASE (u3_base+0x2400) +#define SSUSB_USB3_SYS_CSR_BASE (u3_base+0x2400) +#define SSUSB_USB2_CSR_BASE (u3_base+0x3400) + +/* + * 0x1128_0000 for sifslv register in Infra + */ +#define SSUSB_SIFSLV_SPLLC_BASE (u3_sif_base+0x000) +#define SSUSB_SIFSLV_IPPC_BASE (u3_sif_base+0x700) +#define SSUSB_SIFSLV_U2PHY_COM_BASE (u3_sif_base+0x800) +#define SSUSB_SIFSLV_U3PHYD_BASE (u3_sif_base+0x900) + +#ifdef CONFIG_PROJECT_PHY +/* + * 0x1129_0000 for sifslv register in top_ao + */ +#define SSUSB_SIFSLV_U2PHY_COM_SIV_B_BASE (u3_sif2_base+0x800) +#define SSUSB_USB30_PHYA_SIV_B_BASE (u3_sif2_base+0xB00) +#define SSUSB_SIFSLV_U3PHYA_DA_BASE (u3_sif2_base+0xC00) +#endif + +#include <linux/mu3d/hal/ssusb_dev_c_header.h> +#include <linux/mu3d/hal/ssusb_epctl_csr_c_header.h> +//usb3_mac / usb3_sys do not exist in U2 ONLY IP +#include <linux/mu3d/hal/ssusb_usb3_mac_csr_c_header.h> +#include <linux/mu3d/hal/ssusb_usb3_sys_csr_c_header.h> +#include <linux/mu3d/hal/ssusb_usb2_csr_c_header.h> +#include <linux/mu3d/hal/ssusb_sifslv_ippc_c_header.h> +#include <linux/mu3phy/mtk-phy.h> + +#ifdef EXT_VBUS_DET +#define FPGA_REG 0xf0008098 +#define VBUS_RISE_BIT (1<<11) //W1C +#define VBUS_FALL_BIT (1<<12) //W1C +#define VBUS_MSK (VBUS_RISE_BIT | VBUS_FALL_BIT) +#define VBUS_RISE_IRQ 13 +#define VBUS_FALL_IRQ 14 +#endif +#define USB_IRQ 146 + + +#define RISC_SIZE_1B 0x0 +#define RISC_SIZE_2B 0x1 +#define RISC_SIZE_4B 0x2 + + +#define USB_FIFO(ep_num) (U3D_FIFO0+ep_num*0x10) + +#define USB_FIFOSZ_SIZE_8 (0x03) +#define USB_FIFOSZ_SIZE_16 (0x04) +#define USB_FIFOSZ_SIZE_32 (0x05) +#define USB_FIFOSZ_SIZE_64 (0x06) +#define USB_FIFOSZ_SIZE_128 (0x07) +#define USB_FIFOSZ_SIZE_256 (0x08) +#define USB_FIFOSZ_SIZE_512 (0x09) +#define USB_FIFOSZ_SIZE_1024 (0x0A) +#define USB_FIFOSZ_SIZE_2048 (0x0B) +#define USB_FIFOSZ_SIZE_4096 (0x0C) +#define USB_FIFOSZ_SIZE_8192 (0x0D) +#define USB_FIFOSZ_SIZE_16384 (0x0E) +#define USB_FIFOSZ_SIZE_32768 (0x0F) + + +//U3D_EP0CSR +#define CSR0_SETUPEND (0x00200000) ///removed, use SETUPENDISR +#define CSR0_FLUSHFIFO (0x01000000) ///removed +#define CSR0_SERVICESETUPEND (0x08000000) ///removed, W1C SETUPENDISR +#define EP0_W1C_BITS (~(EP0_RXPKTRDY | EP0_SETUPPKTRDY | EP0_SENTSTALL)) +//U3D_TX1CSR0 +#define USB_TXCSR_FLUSHFIFO (0x00100000) //removed +#define TX_W1C_BITS (~(TX_SENTSTALL)) +/* USB_RXCSR */ +#define USB_RXCSR_FLUSHFIFO (0x00100000) //removed +#define RX_W1C_BITS (~(RX_SENTSTALL|RX_RXPKTRDY)) + + +#define BIT0 (1<<0) +#define BIT16 (1<<16) + +#define TYPE_BULK (0x00) +#define TYPE_INT (0x10) +#define TYPE_ISO (0x20) +#define TYPE_MASK (0x30) + + +/* QMU macros */ +#define USB_QMU_RQCSR(n) (U3D_RXQCSR1+0x0010*((n)-1)) +#define USB_QMU_RQSAR(n) (U3D_RXQSAR1+0x0010*((n)-1)) +#define USB_QMU_RQCPR(n) (U3D_RXQCPR1+0x0010*((n)-1)) +#define USB_QMU_RQLDPR(n) (U3D_RXQLDPR1+0x0010*((n)-1)) +#define USB_QMU_TQCSR(n) (U3D_TXQCSR1+0x0010*((n)-1)) +#define USB_QMU_TQSAR(n) (U3D_TXQSAR1+0x0010*((n)-1)) +#define USB_QMU_TQCPR(n) (U3D_TXQCPR1+0x0010*((n)-1)) + +#define QMU_Q_START (0x00000001) +#define QMU_Q_RESUME (0x00000002) +#define QMU_Q_STOP (0x00000004) +#define QMU_Q_ACTIVE (0x00008000) + +#define QMU_TX_EN(n) (BIT0<<(n)) +#define QMU_RX_EN(n) (BIT16<<(n)) +#define QMU_TX_CS_EN(n) (BIT0<<(n)) +#define QMU_RX_CS_EN(n) (BIT16<<(n)) +#define QMU_TX_ZLP(n) (BIT0<<(n)) +#define QMU_RX_MULTIPLE(n) (BIT16<<((n)-1)) +#define QMU_RX_ZLP(n) (BIT0<<(n)) +#define QMU_RX_COZ(n) (BIT16<<(n)) + +#define QMU_RX_EMPTY(n) (BIT16<<(n)) +#define QMU_TX_EMPTY(n) (BIT0<<(n)) +#define QMU_RX_DONE(n) (BIT16<<(n)) +#define QMU_TX_DONE(n) (BIT0<<(n)) + +#define QMU_RX_ZLP_ERR(n) (BIT16<<(n)) +#define QMU_RX_EP_ERR(n) (BIT0<<(n)) +#define QMU_RX_LEN_ERR(n) (BIT16<<(n)) +#define QMU_RX_CS_ERR(n) (BIT0<<(n)) + +#define QMU_TX_LEN_ERR(n) (BIT16<<(n)) +#define QMU_TX_CS_ERR(n) (BIT0<<(n)) + +/** + * @MAC value Definition + */ + +/* U3D_LINK_STATE_MACHINE */ +#define STATE_RESET (0) +#define STATE_DISABLE (1) +#define STATE_DISABLE_EXIT (2) +#define STATE_SS_INACTIVE_QUITE (3) +#define STATE_SS_INACTIVE_DISC_DETECT (4) +#define STATE_RX_DETECT_RESET (5) +#define STATE_RX_DETECT_ACTIVE (6) +#define STATE_RX_DETECT_QUITE (7) +#define STATE_POLLING_LFPS (8) +#define STATE_POLLING_RXEQ (9) +#define STATE_POLLING_ACTIVE (10) +#define STATE_POLLING_CONFIGURATION (11) +#define STATE_POLLING_IDLE (12) +#define STATE_U0_STATE (13) +#define STATE_U1_STATE (14) +#define STATE_U1_TX_PING (15) +#define STATE_U1_EXIT (16) +#define STATE_U2_STATE (17) +#define STATE_U2_DETECT (18) +#define STATE_U2_EXIT (19) +#define STATE_U3_STATE (20) +#define STATE_U3_DETECT (21) +#define STATE_U3_EXIT (22) +#define STATE_COMPLIANCE (23) +#define STATE_RECOVERY_ACTIVE (24) +#define STATE_RECOVERY_CONFIGURATION (25) +#define STATE_RECOVERY_IDLE (26) +#define STATE_LOOPBACK_ACTIVE_MASTER (27) +#define STATE_LOOPBACK_ACTIVE_SLAVE (28) + +//TODO: remove these definitions +#if 1 +/* DEVICE_CONTROL */ +#define USB_DEVCTL_SESSION (0x1) +#define USB_DEVCTL_HOSTREQUEST (0x2) +#define USB_DEVCTL_HOSTMODE (0x4) +#define USB_DEVCTL_LS_DEV (0x5) +#define USB_DEVCTL_FS_DEV (0x6) +#define USB_DEVCTL_BDEVICE (0x80) +#define USB_DEVCTL_VBUSMASK (0x18) +#define USB_DEVCTL_VBUSVALID (0x18) +#define USB_DEVCTL_VBUS_OFFSET (0x3) +#endif + +#endif /* USB_HW_H */ + diff --git a/include/linux/mu3d/hal/mu3d_hal_osal.h b/include/linux/mu3d/hal/mu3d_hal_osal.h new file mode 100644 index 000000000..c885667ec --- /dev/null +++ b/include/linux/mu3d/hal/mu3d_hal_osal.h @@ -0,0 +1,76 @@ +#ifndef _USB_OSAI_H_ +#define _USB_OSAI_H_ +#include <linux/delay.h> +#include <linux/spinlock_types.h> +#include <linux/spinlock.h> +#include <linux/types.h> +#include <linux/interrupt.h> +#include <linux/dma-mapping.h> +#include <linux/random.h> +#include <linux/slab.h> +#include <linux/mu3d/hal/mu3d_hal_comm.h> +#include <linux/mu3d/hal/mu3d_hal_hw.h> + +#undef EXTERN + +#ifdef _USB_OSAI_EXT_ +#define EXTERN +#else +#define EXTERN extern +#endif + +#define K_EMERG (1<<7) +#define K_QMU (1<<7) +#define K_ALET (1<<6) +#define K_CRIT (1<<5) +#define K_ERR (1<<4) +#define K_WARNIN (1<<3) +#define K_NOTICE (1<<2) +#define K_INFO (1<<1) +#define K_DEBUG (1<<0) + +/*Set the debug level at musb_core.c*/ +extern u32 debug_level; + +#ifdef USE_SSUSB_QMU +#define qmu_printk(level, fmt, args...) do { \ + if ( debug_level & (level|K_QMU) ) { \ + printk("[U3D][Q]" fmt, ## args); \ + } \ + } while (0) +#endif + +#define os_printk(level, fmt, args...) do { \ + if ( debug_level & level ) { \ + printk("[U3D]" fmt, ## args); \ + } \ + } while (0) + +#define OS_R_OK ((DEV_INT32) 0) + +EXTERN spinlock_t _lock; +EXTERN DEV_INT32 os_reg_isr(DEV_UINT32 irq,irq_handler_t handler,void *isrbuffer); +// USBIF +EXTERN void os_free_isr(DEV_UINT32 irq,void *isrbuffer); +EXTERN void os_ms_delay (DEV_UINT32 ui4_delay); +EXTERN void os_us_delay (DEV_UINT32 ui4_delay); +EXTERN void os_ms_sleep (DEV_UINT32 ui4_sleep); + +void os_memcpy(DEV_INT8 *pv_to, DEV_INT8 *pv_from, size_t z_l); +EXTERN void *os_memset(void *pv_to, DEV_UINT8 ui1_c, size_t z_l); +EXTERN void *os_mem_alloc(size_t z_size); + +EXTERN void *os_phys_to_virt(void *paddr); + +EXTERN void os_mem_free(void *pv_mem); +EXTERN void os_disableIrq(DEV_UINT32 irq); +EXTERN void os_disableIrq(DEV_UINT32 irq); +EXTERN void os_enableIrq(DEV_UINT32 irq); +EXTERN void os_clearIrq(DEV_UINT32 irq); +EXTERN void os_get_random_bytes(void *buf,DEV_INT32 nbytes); +EXTERN void os_disableDcache(void); +EXTERN void os_flushinvalidateDcache(void); + +#undef EXTERN + +#endif diff --git a/include/linux/mu3d/hal/mu3d_hal_phy.h b/include/linux/mu3d/hal/mu3d_hal_phy.h new file mode 100644 index 000000000..073aa57c6 --- /dev/null +++ b/include/linux/mu3d/hal/mu3d_hal_phy.h @@ -0,0 +1,28 @@ +#ifndef MTK_PHY_H +#define MTK_PHY_H + +#include <linux/mu3d/hal/mu3d_hal_comm.h> +#include <linux/mu3phy/mtk-phy.h> + +#undef EXTERN + +#define ENTER_U0_TH 10 +#define MAX_PHASE_RANGE 31 +#define MAX_TIMEOUT_COUNT 100 + +#ifdef _MTK_PHY_EXT_ +#define EXTERN +#else +#define EXTERN extern +#endif + +#define U3_PHY_I2C_PCLK_DRV_REG 0x0A +#define U3_PHY_I2C_PCLK_PHASE_REG 0x0B + +EXTERN DEV_INT32 mu3d_hal_phy_scan(DEV_INT32 latch_val, DEV_UINT8 driving); +EXTERN PHY_INT32 _U3Read_Reg(PHY_INT32 address); +EXTERN PHY_INT32 _U3Write_Reg(PHY_INT32 address, PHY_INT32 value); + +#undef EXTERN + +#endif diff --git a/include/linux/mu3d/hal/mu3d_hal_qmu_drv.h b/include/linux/mu3d/hal/mu3d_hal_qmu_drv.h new file mode 100644 index 000000000..af4692883 --- /dev/null +++ b/include/linux/mu3d/hal/mu3d_hal_qmu_drv.h @@ -0,0 +1,277 @@ +#ifndef MTK_QMU_H +#define MTK_QMU_H + +#include <linux/mu3d/hal/mu3d_hal_osal.h> +#include <linux/mu3d/hal/mu3d_hal_hw.h> +#include <linux/mu3d/hal/mu3d_hal_comm.h> +#include <linux/mu3d/hal/mu3d_hal_usb_drv.h> +#include <linux/platform_device.h> + +typedef struct _TGPD { + DEV_UINT8 flag; + DEV_UINT8 chksum; + DEV_UINT16 DataBufferLen; /*Rx Allow Length*/ +#ifdef CONFIG_ARM64 + DEV_UINT32 pNext; + DEV_UINT32 pBuf; +#else + struct _TGPD* pNext; + DEV_UINT8* pBuf; +#endif + DEV_UINT16 bufLen; + DEV_UINT8 ExtLength; + DEV_UINT8 ZTepFlag; +} __attribute__((packed, aligned(4))) TGPD, *PGPD; + +typedef struct _TBD { + DEV_UINT8 flag; + DEV_UINT8 chksum; + DEV_UINT16 DataBufferLen; /*Rx Allow Length*/ +#ifdef CONFIG_ARM64 + DEV_UINT32 pNext; + DEV_UINT32 pBuf; +#else + struct _TBD *pNext; + DEV_UINT8 *pBuf; +#endif + DEV_UINT16 bufLen; + DEV_UINT8 extLen; + DEV_UINT8 reserved; +} __attribute__((packed, aligned(4))) TBD, *PBD; + +typedef struct _GPD_RANGE { + PGPD pNext; + PGPD pStart; + PGPD pEnd; +}GPD_R, *RGPD; + +typedef struct _BD_RANGE { + PBD pNext; + PBD pStart; + PBD pEnd; +}BD_R, *RBD; + +struct qmu_desc_map { + void *p_desc; + dma_addr_t p_desc_dma; +}; + +/* + * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0464d/BABCFDAH.html + * CA7 , CA15 + * The L1 data memory system has the following features: + * data side cache line length of 64-bytes + */ +#define CACHE_LINE_SIZE 64 +#ifdef CACHE_LINE_SIZE +/* + * The min size of GPD must align cache line size. + * So using GPD_EXT_LEN as the dummy space. +*/ +#define AT_GPD_EXT_LEN (CACHE_LINE_SIZE-16) +#else +#define AT_GPD_EXT_LEN 0 +#endif +#define AT_BD_EXT_LEN 0 +#define MAX_GPD_NUM 32 +#define MAX_BD_NUM 0 +//DVT+ +#define STRESS_IOC_TH 8 +#define STRESS_GPD_TH 24 +#define RANDOM_STOP_DELAY 80 +#ifdef CONFIG_USBIF_COMPLIANCE +#define STRESS_DATA_LENGTH 1024 +#else +#define STRESS_DATA_LENGTH 1024*64//1024*16 +#endif +//DVT- +#define GPD_BUF_SIZE 65532 +#define BD_BUF_SIZE 32768 //set to half of 64K of max size + +#define IS_BDP 1 + +#define MAX_QMU_EP MAX_EP_NUM /*The better way is to read U3D_CAP_EPINFO*/ + +#define TGPD_FLAGS_HWO 0x01 +#define TGPD_IS_FLAGS_HWO(_pd) (((TGPD *)_pd)->flag & TGPD_FLAGS_HWO) +#define TGPD_SET_FLAGS_HWO(_pd) (((TGPD *)_pd)->flag |= TGPD_FLAGS_HWO) +#define TGPD_CLR_FLAGS_HWO(_pd) (((TGPD *)_pd)->flag &= (~TGPD_FLAGS_HWO)) +#define TGPD_FORMAT_BDP 0x02 +#define TGPD_IS_FORMAT_BDP(_pd) (((TGPD *)_pd)->flag & TGPD_FORMAT_BDP) +#define TGPD_SET_FORMAT_BDP(_pd) (((TGPD *)_pd)->flag |= TGPD_FORMAT_BDP) +#define TGPD_CLR_FORMAT_BDP(_pd) (((TGPD *)_pd)->flag &= (~TGPD_FORMAT_BDP)) +#define TGPD_FORMAT_BPS 0x04 +#define TGPD_IS_FORMAT_BPS(_pd) (((TGPD *)_pd)->flag & TGPD_FORMAT_BPS) +#define TGPD_SET_FORMAT_BPS(_pd) (((TGPD *)_pd)->flag |= TGPD_FORMAT_BPS) +#define TGPD_CLR_FORMAT_BPS(_pd) (((TGPD *)_pd)->flag &= (~TGPD_FORMAT_BPS)) +#define TGPD_SET_FLAG(_pd, _flag) ((TGPD *)_pd)->flag = (((TGPD *)_pd)->flag&(~TGPD_FLAGS_HWO))|(_flag) +#define TGPD_GET_FLAG(_pd) (((TGPD *)_pd)->flag & TGPD_FLAGS_HWO) +#define TGPD_SET_CHKSUM(_pd, _n) ((TGPD *)_pd)->chksum = mu3d_hal_cal_checksum((DEV_UINT8 *)_pd, _n)-1 +#define TGPD_SET_CHKSUM_HWO(_pd, _n) ((TGPD *)_pd)->chksum = mu3d_hal_cal_checksum((DEV_UINT8 *)_pd, _n)-1 +#define TGPD_GET_CHKSUM(_pd) ((TGPD *)_pd)->chksum +#define TGPD_SET_FORMAT(_pd, _fmt) ((TGPD *)_pd)->flag = (((TGPD *)_pd)->flag&(~TGPD_FORMAT_BDP))|(_fmt) +#define TGPD_GET_FORMAT(_pd) ((((TGPD *)_pd)->flag & TGPD_FORMAT_BDP)>>1) +#define TGPD_SET_DataBUF_LEN(_pd, _len) ((TGPD *)_pd)->DataBufferLen = _len +#define TGPD_ADD_DataBUF_LEN(_pd, _len) ((TGPD *)_pd)->DataBufferLen += _len +#define TGPD_GET_DataBUF_LEN(_pd) ((TGPD *)_pd)->DataBufferLen + +#ifdef CONFIG_ARM64 + +#define TGPD_SET_NEXT(_pd, _next) ((TGPD *)_pd)->pNext = (u32)_next; +#define TGPD_GET_NEXT(_pd) (TGPD *)(uintptr_t)((TGPD *)_pd)->pNext + +#define TGPD_SET_TBD(_pd, _tbd) ((TGPD *)_pd)->pBuf = (u32)_tbd;\ + TGPD_SET_FORMAT_BDP(_pd) +#define TGPD_GET_TBD(_pd) (TBD *)(uintptr_t)((TGPD *)_pd)->pBuf + +#define TGPD_SET_DATA(_pd, _data) ((TGPD *)_pd)->pBuf = (u32)_data +#define TGPD_GET_DATA(_pd) (DEV_UINT8*)(uintptr_t)((TGPD *)_pd)->pBuf + +#else + +#define TGPD_SET_NEXT(_pd, _next) ((TGPD *)_pd)->pNext = (TGPD *)_next; +#define TGPD_GET_NEXT(_pd) (TGPD *)((TGPD *)_pd)->pNext + +#define TGPD_SET_TBD(_pd, _tbd) ((TGPD *)_pd)->pBuf = (DEV_UINT8 *)_tbd;\ + TGPD_SET_FORMAT_BDP(_pd) +#define TGPD_GET_TBD(_pd) (TBD *)((TGPD *)_pd)->pBuf + +#define TGPD_SET_DATA(_pd, _data) ((TGPD *)_pd)->pBuf = (DEV_UINT8 *)_data +#define TGPD_GET_DATA(_pd) (DEV_UINT8*)((TGPD *)_pd)->pBuf + +#endif + +#define TGPD_SET_BUF_LEN(_pd, _len) ((TGPD *)_pd)->bufLen = _len +#define TGPD_ADD_BUF_LEN(_pd, _len) ((TGPD *)_pd)->bufLen += _len +#define TGPD_GET_BUF_LEN(_pd) ((TGPD *)_pd)->bufLen +#define TGPD_SET_EXT_LEN(_pd, _len) ((TGPD *)_pd)->ExtLength = _len +#define TGPD_GET_EXT_LEN(_pd) ((TGPD *)_pd)->ExtLength +#define TGPD_SET_EPaddr(_pd, _EP) ((TGPD *)_pd)->ZTepFlag =(((TGPD *)_pd)->ZTepFlag&0xF0)|(_EP) +#define TGPD_GET_EPaddr(_pd) ((TGPD *)_pd)->ZTepFlag & 0x0F +#define TGPD_FORMAT_TGL 0x10 +#define TGPD_IS_FORMAT_TGL(_pd) (((TGPD *)_pd)->ZTepFlag & TGPD_FORMAT_TGL) +#define TGPD_SET_FORMAT_TGL(_pd) (((TGPD *)_pd)->ZTepFlag |=TGPD_FORMAT_TGL) +#define TGPD_CLR_FORMAT_TGL(_pd) (((TGPD *)_pd)->ZTepFlag &= (~TGPD_FORMAT_TGL)) +#define TGPD_FORMAT_ZLP 0x20 +#define TGPD_IS_FORMAT_ZLP(_pd) (((TGPD *)_pd)->ZTepFlag & TGPD_FORMAT_ZLP) +#define TGPD_SET_FORMAT_ZLP(_pd) (((TGPD *)_pd)->ZTepFlag |=TGPD_FORMAT_ZLP) +#define TGPD_CLR_FORMAT_ZLP(_pd) (((TGPD *)_pd)->ZTepFlag &= (~TGPD_FORMAT_ZLP)) +#define TGPD_FORMAT_IOC 0x80 +#define TGPD_IS_FORMAT_IOC(_pd) (((TGPD *)_pd)->flag & TGPD_FORMAT_IOC) +#define TGPD_SET_FORMAT_IOC(_pd) (((TGPD *)_pd)->flag |=TGPD_FORMAT_IOC) +#define TGPD_CLR_FORMAT_IOC(_pd) (((TGPD *)_pd)->flag &= (~TGPD_FORMAT_IOC)) +#define TGPD_SET_TGL(_pd, _TGL) ((TGPD *)_pd)->ZTepFlag |=(( _TGL) ? 0x10: 0x00) +#define TGPD_GET_TGL(_pd) ((TGPD *)_pd)->ZTepFlag & 0x10 ? 1:0 +#define TGPD_SET_ZLP(_pd, _ZLP) ((TGPD *)_pd)->ZTepFlag |= ((_ZLP) ? 0x20: 0x00) +#define TGPD_GET_ZLP(_pd) ((TGPD *)_pd)->ZTepFlag & 0x20 ? 1:0 +#define TGPD_GET_EXT(_pd) ((DEV_UINT8 *)_pd + sizeof(TGPD)) + + +#define TBD_FLAGS_EOL 0x01 +#define TBD_IS_FLAGS_EOL(_bd) (((TBD *)_bd)->flag & TBD_FLAGS_EOL) +#define TBD_SET_FLAGS_EOL(_bd) (((TBD *)_bd)->flag |= TBD_FLAGS_EOL) +#define TBD_CLR_FLAGS_EOL(_bd) (((TBD *)_bd)->flag &= (~TBD_FLAGS_EOL)) +#define TBD_SET_FLAG(_bd, _flag) ((TBD *)_bd)->flag = (DEV_UINT8)_flag +#define TBD_GET_FLAG(_bd) ((TBD *)_bd)->flag +#define TBD_SET_CHKSUM(_pd, _n) ((TBD *)_pd)->chksum = mu3d_hal_cal_checksum((DEV_UINT8 *)_pd, _n) +#define TBD_GET_CHKSUM(_pd) ((TBD *)_pd)->chksum +#define TBD_SET_DataBUF_LEN(_pd, _len) ((TBD *)_pd)->DataBufferLen = _len +#define TBD_GET_DataBUF_LEN(_pd) ((TBD *)_pd)->DataBufferLen + +#ifdef CONFIG_ARM64 + +#define TBD_SET_NEXT(_bd, _next) ((TBD *)_bd)->pNext = (u32)_next +#define TBD_GET_NEXT(_bd) (TBD *)(uintptr_t)((TBD *)_bd)->pNext +#define TBD_SET_DATA(_bd, _data) ((TBD *)_bd)->pBuf = (u32)_data +#define TBD_GET_DATA(_bd) (DEV_UINT8*)(uintptr_t)((TBD *)_bd)->pBuf + +#else + +#define TBD_SET_NEXT(_bd, _next) ((TBD *)_bd)->pNext = (TBD *)_next +#define TBD_GET_NEXT(_bd) (TBD *)((TBD *)_bd)->pNext +#define TBD_SET_DATA(_bd, _data) ((TBD *)_bd)->pBuf = (DEV_UINT8 *)_data +#define TBD_GET_DATA(_bd) (DEV_UINT8*)((TBD *)_bd)->pBuf + +#endif + +#define TBD_SET_BUF_LEN(_bd, _len) ((TBD *)_bd)->bufLen = _len +#define TBD_ADD_BUF_LEN(_bd, _len) ((TBD *)_bd)->bufLen += _len +#define TBD_GET_BUF_LEN(_bd) ((TBD *)_bd)->bufLen +#define TBD_SET_EXT_LEN(_bd, _len) ((TBD *)_bd)->extLen = _len +#define TBD_ADD_EXT_LEN(_bd, _len) ((TBD *)_bd)->extLen += _len +#define TBD_GET_EXT_LEN(_bd) ((TBD *)_bd)->extLen +#define TBD_GET_EXT(_bd) ((DEV_UINT8 *)_bd + sizeof(TBD)) + + + +#undef EXTERN + +#ifdef _MTK_QMU_DRV_EXT_ +#define EXTERN +#else +#define EXTERN extern +#endif + + +EXTERN DEV_UINT8 is_bdp; +//DVT+ +EXTERN DEV_UINT32 gpd_buf_size; +EXTERN DEV_UINT16 bd_buf_size; +EXTERN DEV_UINT8 bBD_Extension; +EXTERN DEV_UINT8 bGPD_Extension; +EXTERN DEV_UINT32 g_dma_buffer_size; +//DVT+ +EXTERN PGPD Rx_gpd_head[15]; +EXTERN PGPD Tx_gpd_head[15]; +EXTERN PGPD Rx_gpd_end[15]; +EXTERN PGPD Tx_gpd_end[15]; +EXTERN PGPD Rx_gpd_last[15]; +EXTERN PGPD Tx_gpd_last[15]; +EXTERN GPD_R Rx_gpd_List[15]; +EXTERN GPD_R Tx_gpd_List[15]; +EXTERN BD_R Rx_bd_List[15]; +EXTERN BD_R Tx_bd_List[15]; +EXTERN struct qmu_desc_map rx_gpd_map[15]; +EXTERN struct qmu_desc_map tx_gpd_map[15]; +EXTERN struct qmu_desc_map rx_bd_map[15]; +EXTERN struct qmu_desc_map tx_bd_map[15]; + + +EXTERN void mu3d_hal_resume_qmu(DEV_INT32 Q_num, USB_DIR dir); +EXTERN void mu3d_hal_stop_qmu(DEV_INT32 Q_num, USB_DIR dir); +EXTERN TGPD* _ex_mu3d_hal_prepare_tx_gpd(TGPD* gpd, dma_addr_t pBuf, DEV_UINT32 data_length, DEV_UINT8 ep_num, DEV_UINT8 _is_bdp, DEV_UINT8 isHWO,DEV_UINT8 ioc, DEV_UINT8 bps,DEV_UINT8 zlp); +EXTERN TGPD* mu3d_hal_prepare_tx_gpd(TGPD* gpd, dma_addr_t pBuf, DEV_UINT32 data_length, DEV_UINT8 ep_num, DEV_UINT8 _is_bdp, DEV_UINT8 isHWO,DEV_UINT8 ioc, DEV_UINT8 bps,DEV_UINT8 zlp); +EXTERN TGPD* _ex_mu3d_hal_prepare_rx_gpd(TGPD*gpd, dma_addr_t pBuf, DEV_UINT32 data_len, DEV_UINT8 ep_num, DEV_UINT8 _is_bdp, DEV_UINT8 isHWO, DEV_UINT8 ioc, DEV_UINT8 bps,DEV_UINT32 cMaxPacketSize); +EXTERN TGPD* mu3d_hal_prepare_rx_gpd(TGPD*gpd, dma_addr_t pBuf, DEV_UINT32 data_len, DEV_UINT8 ep_num, DEV_UINT8 _is_bdp, DEV_UINT8 isHWO, DEV_UINT8 ioc, DEV_UINT8 bps,DEV_UINT32 cMaxPacketSize); +EXTERN void _ex_mu3d_hal_insert_transfer_gpd(DEV_INT32 ep_num,USB_DIR dir, dma_addr_t buf, DEV_UINT32 count, DEV_UINT8 isHWO, DEV_UINT8 ioc, DEV_UINT8 bps,DEV_UINT8 zlp, DEV_UINT32 cMaxPacketSize ); +EXTERN void mu3d_hal_insert_transfer_gpd(DEV_INT32 ep_num,USB_DIR dir, dma_addr_t buf, DEV_UINT32 count, DEV_UINT8 isHWO, DEV_UINT8 ioc, DEV_UINT8 bps,DEV_UINT8 zlp, DEV_UINT32 cMaxPacketSize ); +EXTERN void _ex_mu3d_hal_alloc_qmu_mem(struct device *dev); +EXTERN void _ex_mu3d_hal_free_qmu_mem(struct device *dev); +EXTERN void mu3d_hal_alloc_qmu_mem(void); +EXTERN void mu3d_hal_free_qmu_mem(void); +EXTERN void _ex_mu3d_hal_init_qmu(void); +EXTERN void mu3d_hal_init_qmu(void); +EXTERN void mu3d_hal_start_qmu(DEV_INT32 Q_num, USB_DIR dir); +EXTERN void _ex_mu3d_hal_flush_qmu(DEV_INT32 Q_num, USB_DIR dir); +EXTERN void mu3d_hal_flush_qmu(DEV_INT32 Q_num, USB_DIR dir); +EXTERN void mu3d_hal_restart_qmu(DEV_INT32 Q_num, USB_DIR dir); +EXTERN void mu3d_hal_send_stall(DEV_INT32 Q_num, USB_DIR dir); +EXTERN DEV_UINT8 mu3d_hal_cal_checksum(DEV_UINT8 *data, DEV_INT32 len); + +EXTERN dma_addr_t _ex_mu3d_hal_gpd_virt_to_phys(void *vaddr,USB_DIR dir,DEV_UINT32 num); +EXTERN dma_addr_t mu3d_hal_gpd_virt_to_phys(void *vaddr,USB_DIR dir,DEV_UINT32 num); + +EXTERN PBD _ex_get_bd(USB_DIR dir,DEV_UINT32 num); +EXTERN PBD get_bd(USB_DIR dir,DEV_UINT32 num); + +EXTERN dma_addr_t bd_virt_to_phys(void *vaddr,USB_DIR dir,DEV_UINT32 num); +EXTERN void *bd_phys_to_virt(void *paddr,USB_DIR dir,DEV_UINT32 num); + +EXTERN PGPD get_gpd(USB_DIR dir,DEV_UINT32 num); + +EXTERN void *gpd_phys_to_virt(void *paddr,USB_DIR dir,DEV_UINT32 num); +EXTERN void gpd_ptr_align(USB_DIR dir,DEV_UINT32 num,PGPD ptr); + +#undef EXTERN + +#endif diff --git a/include/linux/mu3d/hal/mu3d_hal_usb_drv.h b/include/linux/mu3d/hal/mu3d_hal_usb_drv.h new file mode 100644 index 000000000..7d1724e7e --- /dev/null +++ b/include/linux/mu3d/hal/mu3d_hal_usb_drv.h @@ -0,0 +1,188 @@ + +#ifndef MTK_USB_DRV_H +#define MTK_USB_DRV_H + +#include <linux/mu3d/hal/mu3d_hal_hw.h> +#undef EXTERN + +#ifdef _MTK_USB_DRV_EXT_ +#define EXTERN +#else +#define EXTERN extern +#endif + + + +#define MAX_EP_NUM 8 /* 4 Tx and 4 Rx */ +#define USB_BUF_SIZE 65536 +#define MAX_SLOT (2-1) + +/*EP0, TX, RX has separate SRAMs*/ +#define USB_TX_FIFO_START_ADDRESS 0 +#define USB_RX_FIFO_START_ADDRESS 0 + +#ifndef IRQ_USB_MC_NINT_CODE +#define IRQ_USB_MC_NINT_CODE 8 +#endif +#ifndef IRQ_USB_DMA_NINT_CODE +#define IRQ_USB_DMA_NINT_CODE 9 +#endif + +/* IN, OUT pipe index for ep_number */ +typedef enum { + USB_TX = 0, + USB_RX +} USB_DIR; + +/* CTRL, BULK, INTR, ISO endpoint */ +typedef enum { + USB_CTRL = 0, + USB_BULK = 2, + USB_INTR = 3, + USB_ISO = 1 +} TRANSFER_TYPE; + +typedef enum { + SSUSB_SPEED_INACTIVE = 0, + SSUSB_SPEED_FULL = 1, + SSUSB_SPEED_HIGH = 3, + SSUSB_SPEED_SUPER = 4, +} USB_SPEED; + +typedef enum { + EP0_IDLE = 0, + EP0_TX, + EP0_RX, +} EP0_STATE; + +struct USB_EP_SETTING { + TRANSFER_TYPE transfer_type; + DEV_UINT32 fifoaddr; + DEV_UINT32 fifosz; + DEV_UINT32 maxp; + USB_DIR dir; + DEV_UINT8 enabled; +}; + +struct USB_REQ { + DEV_UINT8* buf; + //DEV_UINT8* dma_adr; + dma_addr_t dma_adr; + DEV_UINT32 actual; + DEV_UINT32 count; + DEV_UINT32 currentCount; + DEV_UINT32 complete; + DEV_UINT32 needZLP; + DEV_UINT32 transferCount; +}; + +struct USB_TEST_SETTING { + USB_SPEED speed; + struct USB_EP_SETTING ep_setting[2 * MAX_EP_NUM + 1]; +}; + +/*============================================= +* +* USB 3 test +* +*=============================================*/ + +//#define NUM_TXENDPS 4 +//#define NUM_RXENDPS 4 +//#define NUM_EPS (NUM_TXENDPS + NUM_RXENDPS + 1) + +//#define MGC_END0_FIFOSIZE 64 +//#define MGC_RX_DMA_ENABLE_LEVEL 32 + +//#define IsDbf 0x00000001 +//#define IsTx 0x00000002 +//#define IsHalt 0x00000004 +//#define IsEnabled 0x80000000 + +//#define REQUEST_START_TX 0x1 +//#define REQUEST_START_RX 0x2 + + + /* + * USB directions + * + * This bit flag is used in endpoint descriptors' bEndpointAddress field. + * It's also one of three fields in control requests bRequestType. + */ +#define USB_DIR_OUT 0 /* to device */ +#define USB_DIR_IN 0x80 /* to host */ +#define USB_DIR_MASK 0x80 /* to host */ + + /* + * USB request types + */ + +#define USB_TYPE_MASK (0x03 << 5) +#define USB_TYPE_STANDARD (0x00 << 5) +#define USB_TYPE_CLASS (0x01 << 5) +#define USB_TYPE_VENDOR (0x02 << 5) +#define USB_TYPE_RESERVED (0x03 << 5) + + + /* + * Standard requests + */ +#define USB_REQ_GET_STATUS 0x00 +#define USB_REQ_CLEAR_FEATURE 0x01 +#define USB_REQ_SET_FEATURE 0x03 +#define USB_REQ_SET_ADDRESS 0x05 +#define USB_REQ_GET_DESCRIPTOR 0x06 +#define USB_REQ_SET_DESCRIPTOR 0x07 +#define USB_REQ_GET_CONFIGURATION 0x08 +#define USB_REQ_SET_CONFIGURATION 0x09 +#define USB_REQ_GET_INTERFACE 0x0A +#define USB_REQ_SET_INTERFACE 0x0B +#define USB_REQ_SYNCH_FRAME 0x0C +#define USB_REQ_EP0_IN_STALL 0xFD +#define USB_REQ_EP0_OUT_STALL 0xFE +#define USB_REQ_EP0_STALL 0xFF + + + + +EXTERN struct USB_REQ g_u3d_req[2 * MAX_EP_NUM + 1]; +EXTERN struct USB_TEST_SETTING g_u3d_setting; +EXTERN DEV_UINT32 g_TxFIFOadd; +EXTERN DEV_UINT32 g_RxFIFOadd; + + +EXTERN struct USB_REQ *mu3d_hal_get_req(DEV_INT32 ep_num, USB_DIR dir); +EXTERN void mu3d_hal_pdn_dis(void); +EXTERN void mu3d_hal_ssusb_en(void); +EXTERN void _ex_mu3d_hal_ssusb_en(void); +EXTERN void mu3d_hal_rst_dev(void); +EXTERN DEV_INT32 mu3d_hal_check_clk_sts(void); +EXTERN DEV_INT32 mu3d_hal_link_up(DEV_INT32 latch_val); +EXTERN void mu3d_hal_initr_dis(void); +EXTERN void mu3d_hal_clear_intr(void); +EXTERN void mu3d_hal_system_intr_en(void); +EXTERN void _ex_mu3d_hal_system_intr_en(void); +EXTERN DEV_INT32 mu3d_hal_read_fifo_burst(DEV_INT32 ep_num,DEV_UINT8 *buf); +EXTERN DEV_INT32 mu3d_hal_read_fifo(DEV_INT32 ep_num,DEV_UINT8 *buf); +EXTERN DEV_INT32 mu3d_hal_write_fifo_burst(DEV_INT32 ep_num,DEV_INT32 length,DEV_UINT8 *buf,DEV_INT32 maxp); +EXTERN DEV_INT32 mu3d_hal_write_fifo(DEV_INT32 ep_num,DEV_INT32 length,DEV_UINT8 *buf,DEV_INT32 maxp); +EXTERN void _ex_mu3d_hal_ep_enable(DEV_UINT8 ep_num, USB_DIR dir, TRANSFER_TYPE type, DEV_INT32 maxp, DEV_INT8 interval, DEV_INT8 slot,DEV_INT8 burst, DEV_INT8 mult); +EXTERN void mu3d_hal_ep_enable(DEV_UINT8 ep_num, USB_DIR dir, TRANSFER_TYPE type, DEV_INT32 maxp, DEV_INT8 interval, DEV_INT8 slot,DEV_INT8 burst, DEV_INT8 mult); +EXTERN void mu3d_hal_resume(void); +EXTERN void mu3d_hal_u2dev_connect(void); +EXTERN void mu3d_hal_u2dev_disconn(void); +EXTERN void mu3d_hal_u3dev_en(void); +EXTERN void mu3d_hal_u3dev_dis(void); +EXTERN void mu3d_hal_unfigured_ep(void); +EXTERN void mu3d_hal_unfigured_ep_num(DEV_UINT8 ep_num, USB_DIR dir); +EXTERN void mu3d_hal_set_speed(USB_SPEED usb_speed); +EXTERN void mu3d_hal_det_speed(USB_SPEED speed, DEV_UINT8 det_speed); +EXTERN void mu3d_hal_pdn_cg_en(void); +EXTERN void mu3d_hal_pdn_ip_port(DEV_UINT8 on, DEV_UINT8 touch_dis, DEV_UINT8 u3, DEV_UINT8 u2); +EXTERN void mu3d_hal_dft_reg(void); + +#undef EXTERN + + +#endif //USB_DRV_H + diff --git a/include/linux/mu3d/hal/ssusb_dev_c_header.h b/include/linux/mu3d/hal/ssusb_dev_c_header.h new file mode 100644 index 000000000..d994ef2a9 --- /dev/null +++ b/include/linux/mu3d/hal/ssusb_dev_c_header.h @@ -0,0 +1,3727 @@ +/* SSUSB_DEV REGISTER DEFINITION */ + +#define U3D_LV1ISR (SSUSB_DEV_BASE+0x0000) +#define U3D_LV1IER (SSUSB_DEV_BASE+0x0004) +#define U3D_LV1IESR (SSUSB_DEV_BASE+0x0008) +#define U3D_LV1IECR (SSUSB_DEV_BASE+0x000C) +#define U3D_AXI_WR_DMA_CFG (SSUSB_DEV_BASE+0x0020) +#define U3D_AXI_RD_DMA_CFG (SSUSB_DEV_BASE+0x0024) +#define U3D_MAC_U1_EN_CTRL (SSUSB_DEV_BASE+0x0030) +#define U3D_MAC_U2_EN_CTRL (SSUSB_DEV_BASE+0x0034) +#define U3D_SRAM_DBG_CTRL (SSUSB_DEV_BASE+0x0040) +#define U3D_SRAM_DBG_CTRL_1 (SSUSB_DEV_BASE+0x0044) +#define U3D_RISC_SIZE (SSUSB_DEV_BASE+0x0050) +#define U3D_WRBUF_ERR_STS (SSUSB_DEV_BASE+0x0070) +#define U3D_BUF_ERR_EN (SSUSB_DEV_BASE+0x0074) +#define U3D_EPISR (SSUSB_DEV_BASE+0x0080) +#define U3D_EPIER (SSUSB_DEV_BASE+0x0084) +#define U3D_EPIESR (SSUSB_DEV_BASE+0x0088) +#define U3D_EPIECR (SSUSB_DEV_BASE+0x008C) +#define U3D_DMAISR (SSUSB_DEV_BASE+0x0090) +#define U3D_DMAIER (SSUSB_DEV_BASE+0x0094) +#define U3D_DMAIESR (SSUSB_DEV_BASE+0x0098) +#define U3D_DMAIECR (SSUSB_DEV_BASE+0x009C) +#define U3D_EP0DMACTRL (SSUSB_DEV_BASE+0x00C0) +#define U3D_EP0DMASTRADDR (SSUSB_DEV_BASE+0x00C4) +#define U3D_EP0DMATFRCOUNT (SSUSB_DEV_BASE+0x00C8) +#define U3D_EP0DMARLCOUNT (SSUSB_DEV_BASE+0x00CC) +#define U3D_TXDMACTRL (SSUSB_DEV_BASE+0x00D0) +#define U3D_TXDMASTRADDR (SSUSB_DEV_BASE+0x00D4) +#define U3D_TXDMATRDCNT (SSUSB_DEV_BASE+0x00D8) +#define U3D_TXDMARLCOUNT (SSUSB_DEV_BASE+0x00DC) +#define U3D_RXDMACTRL (SSUSB_DEV_BASE+0x00E0) +#define U3D_RXDMASTRADDR (SSUSB_DEV_BASE+0x00E4) +#define U3D_RXDMATRDCNT (SSUSB_DEV_BASE+0x00E8) +#define U3D_RXDMARLCOUNT (SSUSB_DEV_BASE+0x00EC) +#define U3D_EP0CSR (SSUSB_DEV_BASE+0x0100) +#define U3D_RXCOUNT0 (SSUSB_DEV_BASE+0x0108) +#define U3D_RESERVED (SSUSB_DEV_BASE+0x010C) +#define U3D_TX1CSR0 (SSUSB_DEV_BASE+0x0110) +#define U3D_TX1CSR1 (SSUSB_DEV_BASE+0x0114) +#define U3D_TX1CSR2 (SSUSB_DEV_BASE+0x0118) +#define U3D_TX2CSR0 (SSUSB_DEV_BASE+0x0120) +#define U3D_TX2CSR1 (SSUSB_DEV_BASE+0x0124) +#define U3D_TX2CSR2 (SSUSB_DEV_BASE+0x0128) +#define U3D_TX3CSR0 (SSUSB_DEV_BASE+0x0130) +#define U3D_TX3CSR1 (SSUSB_DEV_BASE+0x0134) +#define U3D_TX3CSR2 (SSUSB_DEV_BASE+0x0138) +#define U3D_TX4CSR0 (SSUSB_DEV_BASE+0x0140) +#define U3D_TX4CSR1 (SSUSB_DEV_BASE+0x0144) +#define U3D_TX4CSR2 (SSUSB_DEV_BASE+0x0148) +#define U3D_TX5CSR0 (SSUSB_DEV_BASE+0x0150) +#define U3D_TX5CSR1 (SSUSB_DEV_BASE+0x0154) +#define U3D_TX5CSR2 (SSUSB_DEV_BASE+0x0158) +#define U3D_TX6CSR0 (SSUSB_DEV_BASE+0x0160) +#define U3D_TX6CSR1 (SSUSB_DEV_BASE+0x0164) +#define U3D_TX6CSR2 (SSUSB_DEV_BASE+0x0168) +#define U3D_TX7CSR0 (SSUSB_DEV_BASE+0x0170) +#define U3D_TX7CSR1 (SSUSB_DEV_BASE+0x0174) +#define U3D_TX7CSR2 (SSUSB_DEV_BASE+0x0178) +#define U3D_TX8CSR0 (SSUSB_DEV_BASE+0x0180) +#define U3D_TX8CSR1 (SSUSB_DEV_BASE+0x0184) +#define U3D_TX8CSR2 (SSUSB_DEV_BASE+0x0188) +#define U3D_TX9CSR0 (SSUSB_DEV_BASE+0x0190) +#define U3D_TX9CSR1 (SSUSB_DEV_BASE+0x0194) +#define U3D_TX9CSR2 (SSUSB_DEV_BASE+0x0198) +#define U3D_TX10CSR0 (SSUSB_DEV_BASE+0x01A0) +#define U3D_TX10CSR1 (SSUSB_DEV_BASE+0x01A4) +#define U3D_TX10CSR2 (SSUSB_DEV_BASE+0x01A8) +#define U3D_TX11CSR0 (SSUSB_DEV_BASE+0x01B0) +#define U3D_TX11CSR1 (SSUSB_DEV_BASE+0x01B4) +#define U3D_TX11CSR2 (SSUSB_DEV_BASE+0x01B8) +#define U3D_TX12CSR0 (SSUSB_DEV_BASE+0x01C0) +#define U3D_TX12CSR1 (SSUSB_DEV_BASE+0x01C4) +#define U3D_TX12CSR2 (SSUSB_DEV_BASE+0x01C8) +#define U3D_TX13CSR0 (SSUSB_DEV_BASE+0x01D0) +#define U3D_TX13CSR1 (SSUSB_DEV_BASE+0x01D4) +#define U3D_TX13CSR2 (SSUSB_DEV_BASE+0x01D8) +#define U3D_TX14CSR0 (SSUSB_DEV_BASE+0x01E0) +#define U3D_TX14CSR1 (SSUSB_DEV_BASE+0x01E4) +#define U3D_TX14CSR2 (SSUSB_DEV_BASE+0x01E8) +#define U3D_TX15CSR0 (SSUSB_DEV_BASE+0x01F0) +#define U3D_TX15CSR1 (SSUSB_DEV_BASE+0x01F4) +#define U3D_TX15CSR2 (SSUSB_DEV_BASE+0x01F8) +#define U3D_RX1CSR0 (SSUSB_DEV_BASE+0x0210) +#define U3D_RX1CSR1 (SSUSB_DEV_BASE+0x0214) +#define U3D_RX1CSR2 (SSUSB_DEV_BASE+0x0218) +#define U3D_RX1CSR3 (SSUSB_DEV_BASE+0x021C) +#define U3D_RX2CSR0 (SSUSB_DEV_BASE+0x0220) +#define U3D_RX2CSR1 (SSUSB_DEV_BASE+0x0224) +#define U3D_RX2CSR2 (SSUSB_DEV_BASE+0x0228) +#define U3D_RX2CSR3 (SSUSB_DEV_BASE+0x022C) +#define U3D_RX3CSR0 (SSUSB_DEV_BASE+0x0230) +#define U3D_RX3CSR1 (SSUSB_DEV_BASE+0x0234) +#define U3D_RX3CSR2 (SSUSB_DEV_BASE+0x0238) +#define U3D_RX3CSR3 (SSUSB_DEV_BASE+0x023C) +#define U3D_RX4CSR0 (SSUSB_DEV_BASE+0x0240) +#define U3D_RX4CSR1 (SSUSB_DEV_BASE+0x0244) +#define U3D_RX4CSR2 (SSUSB_DEV_BASE+0x0248) +#define U3D_RX4CSR3 (SSUSB_DEV_BASE+0x024C) +#define U3D_RX5CSR0 (SSUSB_DEV_BASE+0x0250) +#define U3D_RX5CSR1 (SSUSB_DEV_BASE+0x0254) +#define U3D_RX5CSR2 (SSUSB_DEV_BASE+0x0258) +#define U3D_RX5CSR3 (SSUSB_DEV_BASE+0x025C) +#define U3D_RX6CSR0 (SSUSB_DEV_BASE+0x0260) +#define U3D_RX6CSR1 (SSUSB_DEV_BASE+0x0264) +#define U3D_RX6CSR2 (SSUSB_DEV_BASE+0x0268) +#define U3D_RX6CSR3 (SSUSB_DEV_BASE+0x026C) +#define U3D_RX7CSR0 (SSUSB_DEV_BASE+0x0270) +#define U3D_RX7CSR1 (SSUSB_DEV_BASE+0x0274) +#define U3D_RX7CSR2 (SSUSB_DEV_BASE+0x0278) +#define U3D_RX7CSR3 (SSUSB_DEV_BASE+0x027C) +#define U3D_RX8CSR0 (SSUSB_DEV_BASE+0x0280) +#define U3D_RX8CSR1 (SSUSB_DEV_BASE+0x0284) +#define U3D_RX8CSR2 (SSUSB_DEV_BASE+0x0288) +#define U3D_RX8CSR3 (SSUSB_DEV_BASE+0x028C) +#define U3D_RX9CSR0 (SSUSB_DEV_BASE+0x0290) +#define U3D_RX9CSR1 (SSUSB_DEV_BASE+0x0294) +#define U3D_RX9CSR2 (SSUSB_DEV_BASE+0x0298) +#define U3D_RX9CSR3 (SSUSB_DEV_BASE+0x029C) +#define U3D_RX10CSR0 (SSUSB_DEV_BASE+0x02A0) +#define U3D_RX10CSR1 (SSUSB_DEV_BASE+0x02A4) +#define U3D_RX10CSR2 (SSUSB_DEV_BASE+0x02A8) +#define U3D_RX10CSR3 (SSUSB_DEV_BASE+0x02AC) +#define U3D_RX11CSR0 (SSUSB_DEV_BASE+0x02B0) +#define U3D_RX11CSR1 (SSUSB_DEV_BASE+0x02B4) +#define U3D_RX11CSR2 (SSUSB_DEV_BASE+0x02B8) +#define U3D_RX11CSR3 (SSUSB_DEV_BASE+0x02BC) +#define U3D_RX12CSR0 (SSUSB_DEV_BASE+0x02C0) +#define U3D_RX12CSR1 (SSUSB_DEV_BASE+0x02C4) +#define U3D_RX12CSR2 (SSUSB_DEV_BASE+0x02C8) +#define U3D_RX12CSR3 (SSUSB_DEV_BASE+0x02CC) +#define U3D_RX13CSR0 (SSUSB_DEV_BASE+0x02D0) +#define U3D_RX13CSR1 (SSUSB_DEV_BASE+0x02D4) +#define U3D_RX13CSR2 (SSUSB_DEV_BASE+0x02D8) +#define U3D_RX13CSR3 (SSUSB_DEV_BASE+0x02DC) +#define U3D_RX14CSR0 (SSUSB_DEV_BASE+0x02E0) +#define U3D_RX14CSR1 (SSUSB_DEV_BASE+0x02E4) +#define U3D_RX14CSR2 (SSUSB_DEV_BASE+0x02E8) +#define U3D_RX14CSR3 (SSUSB_DEV_BASE+0x02EC) +#define U3D_RX15CSR0 (SSUSB_DEV_BASE+0x02F0) +#define U3D_RX15CSR1 (SSUSB_DEV_BASE+0x02F4) +#define U3D_RX15CSR2 (SSUSB_DEV_BASE+0x02F8) +#define U3D_RX15CSR3 (SSUSB_DEV_BASE+0x02FC) +#define U3D_FIFO0 (SSUSB_DEV_BASE+0x0300) +#define U3D_FIFO1 (SSUSB_DEV_BASE+0x0310) +#define U3D_FIFO2 (SSUSB_DEV_BASE+0x0320) +#define U3D_FIFO3 (SSUSB_DEV_BASE+0x0330) +#define U3D_FIFO4 (SSUSB_DEV_BASE+0x0340) +#define U3D_FIFO5 (SSUSB_DEV_BASE+0x0350) +#define U3D_FIFO6 (SSUSB_DEV_BASE+0x0360) +#define U3D_FIFO7 (SSUSB_DEV_BASE+0x0370) +#define U3D_FIFO8 (SSUSB_DEV_BASE+0x0380) +#define U3D_FIFO9 (SSUSB_DEV_BASE+0x0390) +#define U3D_FIFO10 (SSUSB_DEV_BASE+0x03A0) +#define U3D_FIFO11 (SSUSB_DEV_BASE+0x03B0) +#define U3D_FIFO12 (SSUSB_DEV_BASE+0x03C0) +#define U3D_FIFO13 (SSUSB_DEV_BASE+0x03D0) +#define U3D_FIFO14 (SSUSB_DEV_BASE+0x03E0) +#define U3D_FIFO15 (SSUSB_DEV_BASE+0x03F0) +#define U3D_QCR0 (SSUSB_DEV_BASE+0x0400) +#define U3D_QCR1 (SSUSB_DEV_BASE+0x0404) +#define U3D_QCR2 (SSUSB_DEV_BASE+0x0408) +#define U3D_QCR3 (SSUSB_DEV_BASE+0x040C) +#define U3D_QGCSR (SSUSB_DEV_BASE+0x0410) +#define U3D_TXQCSR1 (SSUSB_DEV_BASE+0x0510) +#define U3D_TXQSAR1 (SSUSB_DEV_BASE+0x0514) +#define U3D_TXQCPR1 (SSUSB_DEV_BASE+0x0518) +#define U3D_TXQCSR2 (SSUSB_DEV_BASE+0x0520) +#define U3D_TXQSAR2 (SSUSB_DEV_BASE+0x0524) +#define U3D_TXQCPR2 (SSUSB_DEV_BASE+0x0528) +#define U3D_TXQCSR3 (SSUSB_DEV_BASE+0x0530) +#define U3D_TXQSAR3 (SSUSB_DEV_BASE+0x0534) +#define U3D_TXQCPR3 (SSUSB_DEV_BASE+0x0538) +#define U3D_TXQCSR4 (SSUSB_DEV_BASE+0x0540) +#define U3D_TXQSAR4 (SSUSB_DEV_BASE+0x0544) +#define U3D_TXQCPR4 (SSUSB_DEV_BASE+0x0548) +#define U3D_TXQCSR5 (SSUSB_DEV_BASE+0x0550) +#define U3D_TXQSAR5 (SSUSB_DEV_BASE+0x0554) +#define U3D_TXQCPR5 (SSUSB_DEV_BASE+0x0558) +#define U3D_TXQCSR6 (SSUSB_DEV_BASE+0x0560) +#define U3D_TXQSAR6 (SSUSB_DEV_BASE+0x0564) +#define U3D_TXQCPR6 (SSUSB_DEV_BASE+0x0568) +#define U3D_TXQCSR7 (SSUSB_DEV_BASE+0x0570) +#define U3D_TXQSAR7 (SSUSB_DEV_BASE+0x0574) +#define U3D_TXQCPR7 (SSUSB_DEV_BASE+0x0578) +#define U3D_TXQCSR8 (SSUSB_DEV_BASE+0x0580) +#define U3D_TXQSAR8 (SSUSB_DEV_BASE+0x0584) +#define U3D_TXQCPR8 (SSUSB_DEV_BASE+0x0588) +#define U3D_TXQCSR9 (SSUSB_DEV_BASE+0x0590) +#define U3D_TXQSAR9 (SSUSB_DEV_BASE+0x0594) +#define U3D_TXQCPR9 (SSUSB_DEV_BASE+0x0598) +#define U3D_TXQCSR10 (SSUSB_DEV_BASE+0x05A0) +#define U3D_TXQSAR10 (SSUSB_DEV_BASE+0x05A4) +#define U3D_TXQCPR10 (SSUSB_DEV_BASE+0x05A8) +#define U3D_TXQCSR11 (SSUSB_DEV_BASE+0x05B0) +#define U3D_TXQSAR11 (SSUSB_DEV_BASE+0x05B4) +#define U3D_TXQCPR11 (SSUSB_DEV_BASE+0x05B8) +#define U3D_TXQCSR12 (SSUSB_DEV_BASE+0x05C0) +#define U3D_TXQSAR12 (SSUSB_DEV_BASE+0x05C4) +#define U3D_TXQCPR12 (SSUSB_DEV_BASE+0x05C8) +#define U3D_TXQCSR13 (SSUSB_DEV_BASE+0x05D0) +#define U3D_TXQSAR13 (SSUSB_DEV_BASE+0x05D4) +#define U3D_TXQCPR13 (SSUSB_DEV_BASE+0x05D8) +#define U3D_TXQCSR14 (SSUSB_DEV_BASE+0x05E0) +#define U3D_TXQSAR14 (SSUSB_DEV_BASE+0x05E4) +#define U3D_TXQCPR14 (SSUSB_DEV_BASE+0x05E8) +#define U3D_TXQCSR15 (SSUSB_DEV_BASE+0x05F0) +#define U3D_TXQSAR15 (SSUSB_DEV_BASE+0x05F4) +#define U3D_TXQCPR15 (SSUSB_DEV_BASE+0x05F8) +#define U3D_RXQCSR1 (SSUSB_DEV_BASE+0x0610) +#define U3D_RXQSAR1 (SSUSB_DEV_BASE+0x0614) +#define U3D_RXQCPR1 (SSUSB_DEV_BASE+0x0618) +#define U3D_RXQLDPR1 (SSUSB_DEV_BASE+0x061C) +#define U3D_RXQCSR2 (SSUSB_DEV_BASE+0x0620) +#define U3D_RXQSAR2 (SSUSB_DEV_BASE+0x0624) +#define U3D_RXQCPR2 (SSUSB_DEV_BASE+0x0628) +#define U3D_RXQLDPR2 (SSUSB_DEV_BASE+0x062C) +#define U3D_RXQCSR3 (SSUSB_DEV_BASE+0x0630) +#define U3D_RXQSAR3 (SSUSB_DEV_BASE+0x0634) +#define U3D_RXQCPR3 (SSUSB_DEV_BASE+0x0638) +#define U3D_RXQLDPR3 (SSUSB_DEV_BASE+0x063C) +#define U3D_RXQCSR4 (SSUSB_DEV_BASE+0x0640) +#define U3D_RXQSAR4 (SSUSB_DEV_BASE+0x0644) +#define U3D_RXQCPR4 (SSUSB_DEV_BASE+0x0648) +#define U3D_RXQLDPR4 (SSUSB_DEV_BASE+0x064C) +#define U3D_RXQCSR5 (SSUSB_DEV_BASE+0x0650) +#define U3D_RXQSAR5 (SSUSB_DEV_BASE+0x0654) +#define U3D_RXQCPR5 (SSUSB_DEV_BASE+0x0658) +#define U3D_RXQLDPR5 (SSUSB_DEV_BASE+0x065C) +#define U3D_RXQCSR6 (SSUSB_DEV_BASE+0x0660) +#define U3D_RXQSAR6 (SSUSB_DEV_BASE+0x0664) +#define U3D_RXQCPR6 (SSUSB_DEV_BASE+0x0668) +#define U3D_RXQLDPR6 (SSUSB_DEV_BASE+0x066C) +#define U3D_RXQCSR7 (SSUSB_DEV_BASE+0x0670) +#define U3D_RXQSAR7 (SSUSB_DEV_BASE+0x0674) +#define U3D_RXQCPR7 (SSUSB_DEV_BASE+0x0678) +#define U3D_RXQLDPR7 (SSUSB_DEV_BASE+0x067C) +#define U3D_RXQCSR8 (SSUSB_DEV_BASE+0x0680) +#define U3D_RXQSAR8 (SSUSB_DEV_BASE+0x0684) +#define U3D_RXQCPR8 (SSUSB_DEV_BASE+0x0688) +#define U3D_RXQLDPR8 (SSUSB_DEV_BASE+0x068C) +#define U3D_RXQCSR9 (SSUSB_DEV_BASE+0x0690) +#define U3D_RXQSAR9 (SSUSB_DEV_BASE+0x0694) +#define U3D_RXQCPR9 (SSUSB_DEV_BASE+0x0698) +#define U3D_RXQLDPR9 (SSUSB_DEV_BASE+0x069C) +#define U3D_RXQCSR10 (SSUSB_DEV_BASE+0x06A0) +#define U3D_RXQSAR10 (SSUSB_DEV_BASE+0x06A4) +#define U3D_RXQCPR10 (SSUSB_DEV_BASE+0x06A8) +#define U3D_RXQLDPR10 (SSUSB_DEV_BASE+0x06AC) +#define U3D_RXQCSR11 (SSUSB_DEV_BASE+0x06B0) +#define U3D_RXQSAR11 (SSUSB_DEV_BASE+0x06B4) +#define U3D_RXQCPR11 (SSUSB_DEV_BASE+0x06B8) +#define U3D_RXQLDPR11 (SSUSB_DEV_BASE+0x06BC) +#define U3D_RXQCSR12 (SSUSB_DEV_BASE+0x06C0) +#define U3D_RXQSAR12 (SSUSB_DEV_BASE+0x06C4) +#define U3D_RXQCPR12 (SSUSB_DEV_BASE+0x06C8) +#define U3D_RXQLDPR12 (SSUSB_DEV_BASE+0x06CC) +#define U3D_RXQCSR13 (SSUSB_DEV_BASE+0x06D0) +#define U3D_RXQSAR13 (SSUSB_DEV_BASE+0x06D4) +#define U3D_RXQCPR13 (SSUSB_DEV_BASE+0x06D8) +#define U3D_RXQLDPR13 (SSUSB_DEV_BASE+0x06DC) +#define U3D_RXQCSR14 (SSUSB_DEV_BASE+0x06E0) +#define U3D_RXQSAR14 (SSUSB_DEV_BASE+0x06E4) +#define U3D_RXQCPR14 (SSUSB_DEV_BASE+0x06E8) +#define U3D_RXQLDPR14 (SSUSB_DEV_BASE+0x06EC) +#define U3D_RXQCSR15 (SSUSB_DEV_BASE+0x06F0) +#define U3D_RXQSAR15 (SSUSB_DEV_BASE+0x06F4) +#define U3D_RXQCPR15 (SSUSB_DEV_BASE+0x06F8) +#define U3D_RXQLDPR15 (SSUSB_DEV_BASE+0x06FC) +#define U3D_QISAR0 (SSUSB_DEV_BASE+0x0700) +#define U3D_QIER0 (SSUSB_DEV_BASE+0x0704) +#define U3D_QIESR0 (SSUSB_DEV_BASE+0x0708) +#define U3D_QIECR0 (SSUSB_DEV_BASE+0x070C) +#define U3D_QISAR1 (SSUSB_DEV_BASE+0x0710) +#define U3D_QIER1 (SSUSB_DEV_BASE+0x0714) +#define U3D_QIESR1 (SSUSB_DEV_BASE+0x0718) +#define U3D_QIECR1 (SSUSB_DEV_BASE+0x071C) +#define U3D_QEMIR (SSUSB_DEV_BASE+0x0740) +#define U3D_QEMIER (SSUSB_DEV_BASE+0x0744) +#define U3D_QEMIESR (SSUSB_DEV_BASE+0x0748) +#define U3D_QEMIECR (SSUSB_DEV_BASE+0x074C) +#define U3D_TQERRIR0 (SSUSB_DEV_BASE+0x0780) +#define U3D_TQERRIER0 (SSUSB_DEV_BASE+0x0784) +#define U3D_TQERRIESR0 (SSUSB_DEV_BASE+0x0788) +#define U3D_TQERRIECR0 (SSUSB_DEV_BASE+0x078C) +#define U3D_RQERRIR0 (SSUSB_DEV_BASE+0x07C0) +#define U3D_RQERRIER0 (SSUSB_DEV_BASE+0x07C4) +#define U3D_RQERRIESR0 (SSUSB_DEV_BASE+0x07C8) +#define U3D_RQERRIECR0 (SSUSB_DEV_BASE+0x07CC) +#define U3D_RQERRIR1 (SSUSB_DEV_BASE+0x07D0) +#define U3D_RQERRIER1 (SSUSB_DEV_BASE+0x07D4) +#define U3D_RQERRIESR1 (SSUSB_DEV_BASE+0x07D8) +#define U3D_RQERRIECR1 (SSUSB_DEV_BASE+0x07DC) +#define U3D_CAP_EP0FFSZ (SSUSB_DEV_BASE+0x0C04) +#define U3D_CAP_EPNTXFFSZ (SSUSB_DEV_BASE+0x0C08) +#define U3D_CAP_EPNRXFFSZ (SSUSB_DEV_BASE+0x0C0C) +#define U3D_CAP_EPINFO (SSUSB_DEV_BASE+0x0C10) +#define U3D_CAP_TX_SLOT1 (SSUSB_DEV_BASE+0x0C20) +#define U3D_CAP_TX_SLOT2 (SSUSB_DEV_BASE+0x0C24) +#define U3D_CAP_TX_SLOT3 (SSUSB_DEV_BASE+0x0C28) +#define U3D_CAP_TX_SLOT4 (SSUSB_DEV_BASE+0x0C2C) +#define U3D_CAP_RX_SLOT1 (SSUSB_DEV_BASE+0x0C30) +#define U3D_CAP_RX_SLOT2 (SSUSB_DEV_BASE+0x0C34) +#define U3D_CAP_RX_SLOT3 (SSUSB_DEV_BASE+0x0C38) +#define U3D_CAP_RX_SLOT4 (SSUSB_DEV_BASE+0x0C3C) +#define U3D_MISC_CTRL (SSUSB_DEV_BASE+0x0C84) + +/* SSUSB_DEV FIELD DEFINITION */ + +//U3D_LV1ISR +#define EP_CTRL_INTR (0x1<<5) //5:5 +#define MAC2_INTR (0x1<<4) //4:4 +#define DMA_INTR (0x1<<3) //3:3 +#define MAC3_INTR (0x1<<2) //2:2 +#define QMU_INTR (0x1<<1) //1:1 +#define BMU_INTR (0x1<<0) //0:0 + +//U3D_LV1IER +#define LV1IER (0xffffffff<<0) //31:0 + +//U3D_LV1IESR +#define LV1IESR (0xffffffff<<0) //31:0 + +//U3D_LV1IECR +#define LV1IECR (0xffffffff<<0) //31:0 + +//U3D_AXI_WR_DMA_CFG +#define AXI_WR_ULTRA_NUM (0xff<<24) //31:24 +#define AXI_WR_PRE_ULTRA_NUM (0xff<<16) //23:16 +#define AXI_WR_ULTRA_EN (0x1<<0) //0:0 + +//U3D_AXI_RD_DMA_CFG +#define AXI_RD_ULTRA_NUM (0xff<<24) //31:24 +#define AXI_RD_PRE_ULTRA_NUM (0xff<<16) //23:16 +#define AXI_RD_ULTRA_EN (0x1<<0) //0:0 + +//U3D_MAC_U1_EN_CTRL +#define EXIT_BY_ERDY_DIS (0x1<<31) //31:31 +#define ACCEPT_BMU_RX_EMPTY_CHK (0x1<<20) //20:20 +#define ACCEPT_BMU_TX_EMPTY_CHK (0x1<<19) //19:19 +#define ACCEPT_RXQ_INACTIVE_CHK (0x1<<18) //18:18 +#define ACCEPT_TXQ_INACTIVE_CHK (0x1<<17) //17:17 +#define ACCEPT_EP0_INACTIVE_CHK (0x1<<16) //16:16 +#define REQUEST_BMU_RX_EMPTY_CHK (0x1<<4) //4:4 +#define REQUEST_BMU_TX_EMPTY_CHK (0x1<<3) //3:3 +#define REQUEST_RXQ_INACTIVE_CHK (0x1<<2) //2:2 +#define REQUEST_TXQ_INACTIVE_CHK (0x1<<1) //1:1 +#define REQUEST_EP0_INACTIVE_CHK (0x1<<0) //0:0 + +//U3D_MAC_U2_EN_CTRL +#define EXIT_BY_ERDY_DIS (0x1<<31) //31:31 +#define ACCEPT_BMU_RX_EMPTY_CHK (0x1<<20) //20:20 +#define ACCEPT_BMU_TX_EMPTY_CHK (0x1<<19) //19:19 +#define ACCEPT_RXQ_INACTIVE_CHK (0x1<<18) //18:18 +#define ACCEPT_TXQ_INACTIVE_CHK (0x1<<17) //17:17 +#define ACCEPT_EP0_INACTIVE_CHK (0x1<<16) //16:16 +#define REQUEST_BMU_RX_EMPTY_CHK (0x1<<4) //4:4 +#define REQUEST_BMU_TX_EMPTY_CHK (0x1<<3) //3:3 +#define REQUEST_RXQ_INACTIVE_CHK (0x1<<2) //2:2 +#define REQUEST_TXQ_INACTIVE_CHK (0x1<<1) //1:1 +#define REQUEST_EP0_INACTIVE_CHK (0x1<<0) //0:0 + +//U3D_SRAM_DBG_CTRL +#define EPNRX_SRAM_DEBUG_MODE (0x1<<2) //2:2 +#define EPNTX_SRAM_DEBUG_MODE (0x1<<1) //1:1 +#define EP0_SRAM_DEBUG_MODE (0x1<<0) //0:0 + +//U3D_SRAM_DBG_CTRL_1 +#define SRAM_DEBUG_FIFOSEGSIZE (0xf<<24) //27:24 +#define SRAM_DEBUG_SLOT (0x3f<<16) //21:16 +#define SRAM_DEBUG_DP_COUNT (0x7ff<<0) //10:0 + +//U3D_RISC_SIZE +#define RISC_SIZE (0x3<<0) //1:0 + +//U3D_WRBUF_ERR_STS +#define RX_RDBUF_ERR_STS (0x7fff<<17) //31:17 +#define TX_WRBUF_ERR_STS (0x7fff<<1) //15:1 + +//U3D_BUF_ERR_EN +#define RX_RDBUF_ERR_EN (0x7fff<<17) //31:17 +#define TX_WRBUF_ERR_EN (0x7fff<<1) //15:1 + +//U3D_EPISR +#define EPRISR (0x7fff<<17) //31:17 +#define SETUPENDISR (0x1<<16) //16:16 +#define EPTISR (0x7fff<<1) //15:1 +#define EP0ISR (0x1<<0) //0:0 + +//U3D_EPIER +#define EPRIER (0x7fff<<17) //31:17 +#define SETUPENDIER (0x1<<16) //16:16 +#define EPTIER (0x7fff<<1) //15:1 +#define EP0IER (0x1<<0) //0:0 + +//U3D_EPIESR +#define EPRIESR (0x7fff<<17) //31:17 +#define SETUPENDIESR (0x1<<16) //16:16 +#define EPTIESR (0x7fff<<1) //15:1 +#define EP0IESR (0x1<<0) //0:0 + +//U3D_EPIECR +#define EPRISR (0x7fff<<17) //31:17 +#define SETUPENDIECR (0x1<<16) //16:16 +#define EPTIECR (0x7fff<<1) //15:1 +#define EP0IECR (0x1<<0) //0:0 + +//U3D_DMAISR +#define RXDMAISR (0x1<<2) //2:2 +#define TXDMAISR (0x1<<1) //1:1 +#define EP0DMAISR (0x1<<0) //0:0 + +//U3D_DMAIER +#define RXDMAIER (0x1<<2) //2:2 +#define TXDMAIER (0x1<<1) //1:1 +#define EP0DMAER (0x1<<0) //0:0 + +//U3D_DMAIESR +#define RXDMAIESR (0x1<<2) //2:2 +#define TXDMAIESR (0x1<<1) //1:1 +#define EP0DMAIESR (0x1<<0) //0:0 + +//U3D_DMAIECR +#define RXDMAIECR (0x1<<2) //2:2 +#define TXDMAIECR (0x1<<1) //1:1 +#define EP0DMAIECR (0x1<<0) //0:0 + +//U3D_EP0DMACTRL +#define FFSTRADDR0 (0xffff<<16) //31:16 +#define ENDPNT (0xf<<4) //7:4 +#define INTEN (0x1<<3) //3:3 +#define DMA_DIR (0x1<<1) //1:1 +#define DMA_EN (0x1<<0) //0:0 + +//U3D_EP0DMASTRADDR +#define DMASTRADDR0 (0xffffffff<<0) //31:0 + +//U3D_EP0DMATFRCOUNT +#define DMATFRCNT0 (0x7ff<<0) //10:0 + +//U3D_EP0DMARLCOUNT +#define EP0_DMALIMITER (0x7<<28) //30:28 +#define DMA_FAKE (0x1<<27) //27:27 +#define DMA_BURST (0x3<<24) //25:24 +#define AXI_DMA_OUTSTAND_NUM (0xf<<20) //23:20 +#define AXI_DMA_COHERENCE (0x1<<19) //19:19 +#define AXI_DMA_IOMMU (0x1<<18) //18:18 +#define AXI_DMA_CACHEABLE (0x1<<17) //17:17 +#define AXI_DMA_ULTRA_EN (0x1<<16) //16:16 +#define AXI_DMA_ULTRA_NUM (0xff<<8) //15:8 +#define AXI_DMA_PRE_ULTRA_NUM (0xff<<0) //7:0 + +//U3D_TXDMACTRL +#define FFSTRADDR (0xffff<<16) //31:16 +#define ENDPNT (0xf<<4) //7:4 +#define INTEN (0x1<<3) //3:3 +#define DMA_DIR (0x1<<1) //1:1 +#define DMA_EN (0x1<<0) //0:0 + +//U3D_TXDMASTRADDR +#define DMASTRADDR (0xffffffff<<0) //31:0 + +//U3D_TXDMATRDCNT +#define DMATFRCNT (0x7ff<<0) //10:0 + +//U3D_TXDMARLCOUNT +#define DMALIMITER (0x7<<28) //30:28 +#define DMA_FAKE (0x1<<27) //27:27 +#define DMA_BURST (0x3<<24) //25:24 +#define AXI_DMA_OUTSTAND_NUM (0xf<<20) //23:20 +#define AXI_DMA_COHERENCE (0x1<<19) //19:19 +#define AXI_DMA_IOMMU (0x1<<18) //18:18 +#define AXI_DMA_CACHEABLE (0x1<<17) //17:17 +#define AXI_DMA_ULTRA_EN (0x1<<16) //16:16 +#define AXI_DMA_ULTRA_NUM (0xff<<8) //15:8 +#define AXI_DMA_PRE_ULTRA_NUM (0xff<<0) //7:0 + +//U3D_RXDMACTRL +#define FFSTRADDR (0xffff<<16) //31:16 +#define ENDPNT (0xf<<4) //7:4 +#define INTEN (0x1<<3) //3:3 +#define DMA_DIR (0x1<<1) //1:1 +#define DMA_EN (0x1<<0) //0:0 + +//U3D_RXDMASTRADDR +#define DMASTRADDR (0xffffffff<<0) //31:0 + +//U3D_RXDMATRDCNT +#define DMATFRCNT (0x7ff<<0) //10:0 + +//U3D_RXDMARLCOUNT +#define DMA_NON_BUF (0x1<<31) //31:31 +#define DMALIMITER (0x7<<28) //30:28 +#define DMA_FAKE (0x1<<27) //27:27 +#define DMA_BURST (0x3<<24) //25:24 +#define AXI_DMA_OUTSTAND_NUM (0xf<<20) //23:20 +#define AXI_DMA_COHERENCE (0x1<<19) //19:19 +#define AXI_DMA_IOMMU (0x1<<18) //18:18 +#define AXI_DMA_CACHEABLE (0x1<<17) //17:17 +#define AXI_DMA_ULTRA_EN (0x1<<16) //16:16 +#define AXI_DMA_ULTRA_NUM (0xff<<8) //15:8 +#define AXI_DMA_PRE_ULTRA_NUM (0xff<<0) //7:0 + +//U3D_EP0CSR +#define EP0_EP_RESET (0x1<<31) //31:31 +#define EP0_AUTOCLEAR (0x1<<30) //30:30 +#define EP0_AUTOSET (0x1<<29) //29:29 +#define EP0_DMAREQEN (0x1<<28) //28:28 +#define EP0_SENDSTALL (0x1<<25) //25:25 +#define EP0_FIFOFULL (0x1<<23) //23:23 +#define EP0_SENTSTALL (0x1<<22) //22:22 +#define EP0_DPHTX (0x1<<20) //20:20 +#define EP0_DATAEND (0x1<<19) //19:19 +#define EP0_TXPKTRDY (0x1<<18) //18:18 +#define EP0_SETUPPKTRDY (0x1<<17) //17:17 +#define EP0_RXPKTRDY (0x1<<16) //16:16 +#define EP0_MAXPKTSZ0 (0x3ff<<0) //9:0 + +//U3D_RXCOUNT0 +#define EP0_RX_COUNT (0x3ff<<0) //9:0 + +//U3D_RESERVED + +//U3D_TX1CSR0 +#define TX_EP_RESET (0x1<<31) //31:31 +#define TX_AUTOSET (0x1<<30) //30:30 +#define TX_DMAREQEN (0x1<<29) //29:29 +#define TX_FIFOFULL (0x1<<25) //25:25 +#define TX_FIFOEMPTY (0x1<<24) //24:24 +#define TX_SENTSTALL (0x1<<22) //22:22 +#define TX_SENDSTALL (0x1<<21) //21:21 +#define TX_TXPKTRDY (0x1<<16) //16:16 +#define TX_TXMAXPKTSZ (0x7ff<<0) //10:0 + +//U3D_TX1CSR1 +#define TX_MULT (0x3<<22) //23:22 +#define TX_MAX_PKT (0x3f<<16) //21:16 +#define TX_SLOT (0x3f<<8) //13:8 +#define TXTYPE (0x3<<4) //5:4 +#define SS_TX_BURST (0xf<<0) //3:0 + +//U3D_TX1CSR2 +#define TXBINTERVAL (0xff<<24) //31:24 +#define TXFIFOSEGSIZE (0xf<<16) //19:16 +#define TXFIFOADDR (0x1fff<<0) //12:0 + +//U3D_TX2CSR0 +#define TX_EP_RESET (0x1<<31) //31:31 +#define TX_AUTOSET (0x1<<30) //30:30 +#define TX_DMAREQEN (0x1<<29) //29:29 +#define TX_FIFOFULL (0x1<<25) //25:25 +#define TX_FIFOEMPTY (0x1<<24) //24:24 +#define TX_SENTSTALL (0x1<<22) //22:22 +#define TX_SENDSTALL (0x1<<21) //21:21 +#define TX_TXPKTRDY (0x1<<16) //16:16 +#define TX_TXMAXPKTSZ (0x7ff<<0) //10:0 + +//U3D_TX2CSR1 +#define TX_MULT (0x3<<22) //23:22 +#define TX_MAX_PKT (0x3f<<16) //21:16 +#define TX_SLOT (0x3f<<8) //13:8 +#define TXTYPE (0x3<<4) //5:4 +#define SS_TX_BURST (0xf<<0) //3:0 + +//U3D_TX2CSR2 +#define TXBINTERVAL (0xff<<24) //31:24 +#define TXFIFOSEGSIZE (0xf<<16) //19:16 +#define TXFIFOADDR (0x1fff<<0) //12:0 + +//U3D_TX3CSR0 +#define TX_EP_RESET (0x1<<31) //31:31 +#define TX_AUTOSET (0x1<<30) //30:30 +#define TX_DMAREQEN (0x1<<29) //29:29 +#define TX_FIFOFULL (0x1<<25) //25:25 +#define TX_FIFOEMPTY (0x1<<24) //24:24 +#define TX_SENTSTALL (0x1<<22) //22:22 +#define TX_SENDSTALL (0x1<<21) //21:21 +#define TX_TXPKTRDY (0x1<<16) //16:16 +#define TX_TXMAXPKTSZ (0x7ff<<0) //10:0 + +//U3D_TX3CSR1 +#define TX_MULT (0x3<<22) //23:22 +#define TX_MAX_PKT (0x3f<<16) //21:16 +#define TX_SLOT (0x3f<<8) //13:8 +#define TXTYPE (0x3<<4) //5:4 +#define SS_TX_BURST (0xf<<0) //3:0 + +//U3D_TX3CSR2 +#define TXBINTERVAL (0xff<<24) //31:24 +#define TXFIFOSEGSIZE (0xf<<16) //19:16 +#define TXFIFOADDR (0x1fff<<0) //12:0 + +//U3D_TX4CSR0 +#define TX_EP_RESET (0x1<<31) //31:31 +#define TX_AUTOSET (0x1<<30) //30:30 +#define TX_DMAREQEN (0x1<<29) //29:29 +#define TX_FIFOFULL (0x1<<25) //25:25 +#define TX_FIFOEMPTY (0x1<<24) //24:24 +#define TX_SENTSTALL (0x1<<22) //22:22 +#define TX_SENDSTALL (0x1<<21) //21:21 +#define TX_TXPKTRDY (0x1<<16) //16:16 +#define TX_TXMAXPKTSZ (0x7ff<<0) //10:0 + +//U3D_TX4CSR1 +#define TX_MULT (0x3<<22) //23:22 +#define TX_MAX_PKT (0x3f<<16) //21:16 +#define TX_SLOT (0x3f<<8) //13:8 +#define TXTYPE (0x3<<4) //5:4 +#define SS_TX_BURST (0xf<<0) //3:0 + +//U3D_TX4CSR2 +#define TXBINTERVAL (0xff<<24) //31:24 +#define TXFIFOSEGSIZE (0xf<<16) //19:16 +#define TXFIFOADDR (0x1fff<<0) //12:0 + +//U3D_TX5CSR0 +#define TX_EP_RESET (0x1<<31) //31:31 +#define TX_AUTOSET (0x1<<30) //30:30 +#define TX_DMAREQEN (0x1<<29) //29:29 +#define TX_FIFOFULL (0x1<<25) //25:25 +#define TX_FIFOEMPTY (0x1<<24) //24:24 +#define TX_SENTSTALL (0x1<<22) //22:22 +#define TX_SENDSTALL (0x1<<21) //21:21 +#define TX_TXPKTRDY (0x1<<16) //16:16 +#define TX_TXMAXPKTSZ (0x7ff<<0) //10:0 + +//U3D_TX5CSR1 +#define TX_MULT (0x3<<22) //23:22 +#define TX_MAX_PKT (0x3f<<16) //21:16 +#define TX_SLOT (0x3f<<8) //13:8 +#define TXTYPE (0x3<<4) //5:4 +#define SS_TX_BURST (0xf<<0) //3:0 + +//U3D_TX5CSR2 +#define TXBINTERVAL (0xff<<24) //31:24 +#define TXFIFOSEGSIZE (0xf<<16) //19:16 +#define TXFIFOADDR (0x1fff<<0) //12:0 + +//U3D_TX6CSR0 +#define TX_EP_RESET (0x1<<31) //31:31 +#define TX_AUTOSET (0x1<<30) //30:30 +#define TX_DMAREQEN (0x1<<29) //29:29 +#define TX_FIFOFULL (0x1<<25) //25:25 +#define TX_FIFOEMPTY (0x1<<24) //24:24 +#define TX_SENTSTALL (0x1<<22) //22:22 +#define TX_SENDSTALL (0x1<<21) //21:21 +#define TX_TXPKTRDY (0x1<<16) //16:16 +#define TX_TXMAXPKTSZ (0x7ff<<0) //10:0 + +//U3D_TX6CSR1 +#define TX_MULT (0x3<<22) //23:22 +#define TX_MAX_PKT (0x3f<<16) //21:16 +#define TX_SLOT (0x3f<<8) //13:8 +#define TXTYPE (0x3<<4) //5:4 +#define SS_TX_BURST (0xf<<0) //3:0 + +//U3D_TX6CSR2 +#define TXBINTERVAL (0xff<<24) //31:24 +#define TXFIFOSEGSIZE (0xf<<16) //19:16 +#define TXFIFOADDR (0x1fff<<0) //12:0 + +//U3D_TX7CSR0 +#define TX_EP_RESET (0x1<<31) //31:31 +#define TX_AUTOSET (0x1<<30) //30:30 +#define TX_DMAREQEN (0x1<<29) //29:29 +#define TX_FIFOFULL (0x1<<25) //25:25 +#define TX_FIFOEMPTY (0x1<<24) //24:24 +#define TX_SENTSTALL (0x1<<22) //22:22 +#define TX_SENDSTALL (0x1<<21) //21:21 +#define TX_TXPKTRDY (0x1<<16) //16:16 +#define TX_TXMAXPKTSZ (0x7ff<<0) //10:0 + +//U3D_TX7CSR1 +#define TX_MULT (0x3<<22) //23:22 +#define TX_MAX_PKT (0x3f<<16) //21:16 +#define TX_SLOT (0x3f<<8) //13:8 +#define TXTYPE (0x3<<4) //5:4 +#define SS_TX_BURST (0xf<<0) //3:0 + +//U3D_TX7CSR2 +#define TXBINTERVAL (0xff<<24) //31:24 +#define TXFIFOSEGSIZE (0xf<<16) //19:16 +#define TXFIFOADDR (0x1fff<<0) //12:0 + +//U3D_TX8CSR0 +#define TX_EP_RESET (0x1<<31) //31:31 +#define TX_AUTOSET (0x1<<30) //30:30 +#define TX_DMAREQEN (0x1<<29) //29:29 +#define TX_FIFOFULL (0x1<<25) //25:25 +#define TX_FIFOEMPTY (0x1<<24) //24:24 +#define TX_SENTSTALL (0x1<<22) //22:22 +#define TX_SENDSTALL (0x1<<21) //21:21 +#define TX_TXPKTRDY (0x1<<16) //16:16 +#define TX_TXMAXPKTSZ (0x7ff<<0) //10:0 + +//U3D_TX8CSR1 +#define TX_MULT (0x3<<22) //23:22 +#define TX_MAX_PKT (0x3f<<16) //21:16 +#define TX_SLOT (0x3f<<8) //13:8 +#define TXTYPE (0x3<<4) //5:4 +#define SS_TX_BURST (0xf<<0) //3:0 + +//U3D_TX8CSR2 +#define TXBINTERVAL (0xff<<24) //31:24 +#define TXFIFOSEGSIZE (0xf<<16) //19:16 +#define TXFIFOADDR (0x1fff<<0) //12:0 + +//U3D_TX9CSR0 +#define TX_EP_RESET (0x1<<31) //31:31 +#define TX_AUTOSET (0x1<<30) //30:30 +#define TX_DMAREQEN (0x1<<29) //29:29 +#define TX_FIFOFULL (0x1<<25) //25:25 +#define TX_FIFOEMPTY (0x1<<24) //24:24 +#define TX_SENTSTALL (0x1<<22) //22:22 +#define TX_SENDSTALL (0x1<<21) //21:21 +#define TX_TXPKTRDY (0x1<<16) //16:16 +#define TX_TXMAXPKTSZ (0x7ff<<0) //10:0 + +//U3D_TX9CSR1 +#define TX_MULT (0x3<<22) //23:22 +#define TX_MAX_PKT (0x3f<<16) //21:16 +#define TX_SLOT (0x3f<<8) //13:8 +#define TXTYPE (0x3<<4) //5:4 +#define SS_TX_BURST (0xf<<0) //3:0 + +//U3D_TX9CSR2 +#define TXBINTERVAL (0xff<<24) //31:24 +#define TXFIFOSEGSIZE (0xf<<16) //19:16 +#define TXFIFOADDR (0x1fff<<0) //12:0 + +//U3D_TX10CSR0 +#define TX_EP_RESET (0x1<<31) //31:31 +#define TX_AUTOSET (0x1<<30) //30:30 +#define TX_DMAREQEN (0x1<<29) //29:29 +#define TX_FIFOFULL (0x1<<25) //25:25 +#define TX_FIFOEMPTY (0x1<<24) //24:24 +#define TX_SENTSTALL (0x1<<22) //22:22 +#define TX_SENDSTALL (0x1<<21) //21:21 +#define TX_TXPKTRDY (0x1<<16) //16:16 +#define TX_TXMAXPKTSZ (0x7ff<<0) //10:0 + +//U3D_TX10CSR1 +#define TX_MULT (0x3<<22) //23:22 +#define TX_MAX_PKT (0x3f<<16) //21:16 +#define TX_SLOT (0x3f<<8) //13:8 +#define TXTYPE (0x3<<4) //5:4 +#define SS_TX_BURST (0xf<<0) //3:0 + +//U3D_TX10CSR2 +#define TXBINTERVAL (0xff<<24) //31:24 +#define TXFIFOSEGSIZE (0xf<<16) //19:16 +#define TXFIFOADDR (0x1fff<<0) //12:0 + +//U3D_TX11CSR0 +#define TX_EP_RESET (0x1<<31) //31:31 +#define TX_AUTOSET (0x1<<30) //30:30 +#define TX_DMAREQEN (0x1<<29) //29:29 +#define TX_FIFOFULL (0x1<<25) //25:25 +#define TX_FIFOEMPTY (0x1<<24) //24:24 +#define TX_SENTSTALL (0x1<<22) //22:22 +#define TX_SENDSTALL (0x1<<21) //21:21 +#define TX_TXPKTRDY (0x1<<16) //16:16 +#define TX_TXMAXPKTSZ (0x7ff<<0) //10:0 + +//U3D_TX11CSR1 +#define TX_MULT (0x3<<22) //23:22 +#define TX_MAX_PKT (0x3f<<16) //21:16 +#define TX_SLOT (0x3f<<8) //13:8 +#define TXTYPE (0x3<<4) //5:4 +#define SS_TX_BURST (0xf<<0) //3:0 + +//U3D_TX11CSR2 +#define TXBINTERVAL (0xff<<24) //31:24 +#define TXFIFOSEGSIZE (0xf<<16) //19:16 +#define TXFIFOADDR (0x1fff<<0) //12:0 + +//U3D_TX12CSR0 +#define TX_EP_RESET (0x1<<31) //31:31 +#define TX_AUTOSET (0x1<<30) //30:30 +#define TX_DMAREQEN (0x1<<29) //29:29 +#define TX_FIFOFULL (0x1<<25) //25:25 +#define TX_FIFOEMPTY (0x1<<24) //24:24 +#define TX_SENTSTALL (0x1<<22) //22:22 +#define TX_SENDSTALL (0x1<<21) //21:21 +#define TX_TXPKTRDY (0x1<<16) //16:16 +#define TX_TXMAXPKTSZ (0x7ff<<0) //10:0 + +//U3D_TX12CSR1 +#define TX_MULT (0x3<<22) //23:22 +#define TX_MAX_PKT (0x3f<<16) //21:16 +#define TX_SLOT (0x3f<<8) //13:8 +#define TXTYPE (0x3<<4) //5:4 +#define SS_TX_BURST (0xf<<0) //3:0 + +//U3D_TX12CSR2 +#define TXBINTERVAL (0xff<<24) //31:24 +#define TXFIFOSEGSIZE (0xf<<16) //19:16 +#define TXFIFOADDR (0x1fff<<0) //12:0 + +//U3D_TX13CSR0 +#define TX_EP_RESET (0x1<<31) //31:31 +#define TX_AUTOSET (0x1<<30) //30:30 +#define TX_DMAREQEN (0x1<<29) //29:29 +#define TX_FIFOFULL (0x1<<25) //25:25 +#define TX_FIFOEMPTY (0x1<<24) //24:24 +#define TX_SENTSTALL (0x1<<22) //22:22 +#define TX_SENDSTALL (0x1<<21) //21:21 +#define TX_TXPKTRDY (0x1<<16) //16:16 +#define TX_TXMAXPKTSZ (0x7ff<<0) //10:0 + +//U3D_TX13CSR1 +#define TX_MULT (0x3<<22) //23:22 +#define TX_MAX_PKT (0x3f<<16) //21:16 +#define TX_SLOT (0x3f<<8) //13:8 +#define TXTYPE (0x3<<4) //5:4 +#define SS_TX_BURST (0xf<<0) //3:0 + +//U3D_TX13CSR2 +#define TXBINTERVAL (0xff<<24) //31:24 +#define TXFIFOSEGSIZE (0xf<<16) //19:16 +#define TXFIFOADDR (0x1fff<<0) //12:0 + +//U3D_TX14CSR0 +#define TX_EP_RESET (0x1<<31) //31:31 +#define TX_AUTOSET (0x1<<30) //30:30 +#define TX_DMAREQEN (0x1<<29) //29:29 +#define TX_FIFOFULL (0x1<<25) //25:25 +#define TX_FIFOEMPTY (0x1<<24) //24:24 +#define TX_SENTSTALL (0x1<<22) //22:22 +#define TX_SENDSTALL (0x1<<21) //21:21 +#define TX_TXPKTRDY (0x1<<16) //16:16 +#define TX_TXMAXPKTSZ (0x7ff<<0) //10:0 + +//U3D_TX14CSR1 +#define TX_MULT (0x3<<22) //23:22 +#define TX_MAX_PKT (0x3f<<16) //21:16 +#define TX_SLOT (0x3f<<8) //13:8 +#define TXTYPE (0x3<<4) //5:4 +#define SS_TX_BURST (0xf<<0) //3:0 + +//U3D_TX14CSR2 +#define TXBINTERVAL (0xff<<24) //31:24 +#define TXFIFOSEGSIZE (0xf<<16) //19:16 +#define TXFIFOADDR (0x1fff<<0) //12:0 + +//U3D_TX15CSR0 +#define TX_EP_RESET (0x1<<31) //31:31 +#define TX_AUTOSET (0x1<<30) //30:30 +#define TX_DMAREQEN (0x1<<29) //29:29 +#define TX_FIFOFULL (0x1<<25) //25:25 +#define TX_FIFOEMPTY (0x1<<24) //24:24 +#define TX_SENTSTALL (0x1<<22) //22:22 +#define TX_SENDSTALL (0x1<<21) //21:21 +#define TX_TXPKTRDY (0x1<<16) //16:16 +#define TX_TXMAXPKTSZ (0x7ff<<0) //10:0 + +//U3D_TX15CSR1 +#define TX_MULT (0x3<<22) //23:22 +#define TX_MAX_PKT (0x3f<<16) //21:16 +#define TX_SLOT (0x3f<<8) //13:8 +#define TXTYPE (0x3<<4) //5:4 +#define SS_TX_BURST (0xf<<0) //3:0 + +//U3D_TX15CSR2 +#define TXBINTERVAL (0xff<<24) //31:24 +#define TXFIFOSEGSIZE (0xf<<16) //19:16 +#define TXFIFOADDR (0x1fff<<0) //12:0 + +//U3D_RX1CSR0 +#define RX_EP_RESET (0x1<<31) //31:31 +#define RX_AUTOCLEAR (0x1<<30) //30:30 +#define RX_DMAREQEN (0x1<<29) //29:29 +#define RX_SENTSTALL (0x1<<22) //22:22 +#define RX_SENDSTALL (0x1<<21) //21:21 +#define RX_FIFOFULL (0x1<<18) //18:18 +#define RX_FIFOEMPTY (0x1<<17) //17:17 +#define RX_RXPKTRDY (0x1<<16) //16:16 +#define RX_RXMAXPKTSZ (0x7ff<<0) //10:0 + +//U3D_RX1CSR1 +#define RX_MULT (0x3<<22) //23:22 +#define RX_MAX_PKT (0x3f<<16) //21:16 +#define RX_SLOT (0x3f<<8) //13:8 +#define RX_TYPE (0x3<<4) //5:4 +#define SS_RX_BURST (0xf<<0) //3:0 + +//U3D_RX1CSR2 +#define RXBINTERVAL (0xff<<24) //31:24 +#define RXFIFOSEGSIZE (0xf<<16) //19:16 +#define RXFIFOADDR (0x1fff<<0) //12:0 + +//U3D_RX1CSR3 +#define EP_RX_COUNT (0x7ff<<16) //26:16 + +//U3D_RX2CSR0 +#define RX_EP_RESET (0x1<<31) //31:31 +#define RX_AUTOCLEAR (0x1<<30) //30:30 +#define RX_DMAREQEN (0x1<<29) //29:29 +#define RX_SENTSTALL (0x1<<22) //22:22 +#define RX_SENDSTALL (0x1<<21) //21:21 +#define RX_FIFOFULL (0x1<<18) //18:18 +#define RX_FIFOEMPTY (0x1<<17) //17:17 +#define RX_RXPKTRDY (0x1<<16) //16:16 +#define RX_RXMAXPKTSZ (0x7ff<<0) //10:0 + +//U3D_RX2CSR1 +#define RX_MULT (0x3<<22) //23:22 +#define RX_MAX_PKT (0x3f<<16) //21:16 +#define RX_SLOT (0x3f<<8) //13:8 +#define RX_TYPE (0x3<<4) //5:4 +#define SS_RX_BURST (0xf<<0) //3:0 + +//U3D_RX2CSR2 +#define RXBINTERVAL (0xff<<24) //31:24 +#define RXFIFOSEGSIZE (0xf<<16) //19:16 +#define RXFIFOADDR (0x1fff<<0) //12:0 + +//U3D_RX2CSR3 +#define EP_RX_COUNT (0x7ff<<16) //26:16 + +//U3D_RX3CSR0 +#define RX_EP_RESET (0x1<<31) //31:31 +#define RX_AUTOCLEAR (0x1<<30) //30:30 +#define RX_DMAREQEN (0x1<<29) //29:29 +#define RX_SENTSTALL (0x1<<22) //22:22 +#define RX_SENDSTALL (0x1<<21) //21:21 +#define RX_FIFOFULL (0x1<<18) //18:18 +#define RX_FIFOEMPTY (0x1<<17) //17:17 +#define RX_RXPKTRDY (0x1<<16) //16:16 +#define RX_RXMAXPKTSZ (0x7ff<<0) //10:0 + +//U3D_RX3CSR1 +#define RX_MULT (0x3<<22) //23:22 +#define RX_MAX_PKT (0x3f<<16) //21:16 +#define RX_SLOT (0x3f<<8) //13:8 +#define RX_TYPE (0x3<<4) //5:4 +#define SS_RX_BURST (0xf<<0) //3:0 + +//U3D_RX3CSR2 +#define RXBINTERVAL (0xff<<24) //31:24 +#define RXFIFOSEGSIZE (0xf<<16) //19:16 +#define RXFIFOADDR (0x1fff<<0) //12:0 + +//U3D_RX3CSR3 +#define EP_RX_COUNT (0x7ff<<16) //26:16 + +//U3D_RX4CSR0 +#define RX_EP_RESET (0x1<<31) //31:31 +#define RX_AUTOCLEAR (0x1<<30) //30:30 +#define RX_DMAREQEN (0x1<<29) //29:29 +#define RX_SENTSTALL (0x1<<22) //22:22 +#define RX_SENDSTALL (0x1<<21) //21:21 +#define RX_FIFOFULL (0x1<<18) //18:18 +#define RX_FIFOEMPTY (0x1<<17) //17:17 +#define RX_RXPKTRDY (0x1<<16) //16:16 +#define RX_RXMAXPKTSZ (0x7ff<<0) //10:0 + +//U3D_RX4CSR1 +#define RX_MULT (0x3<<22) //23:22 +#define RX_MAX_PKT (0x3f<<16) //21:16 +#define RX_SLOT (0x3f<<8) //13:8 +#define RX_TYPE (0x3<<4) //5:4 +#define SS_RX_BURST (0xf<<0) //3:0 + +//U3D_RX4CSR2 +#define RXBINTERVAL (0xff<<24) //31:24 +#define RXFIFOSEGSIZE (0xf<<16) //19:16 +#define RXFIFOADDR (0x1fff<<0) //12:0 + +//U3D_RX4CSR3 +#define EP_RX_COUNT (0x7ff<<16) //26:16 + +//U3D_RX5CSR0 +#define RX_EP_RESET (0x1<<31) //31:31 +#define RX_AUTOCLEAR (0x1<<30) //30:30 +#define RX_DMAREQEN (0x1<<29) //29:29 +#define RX_SENTSTALL (0x1<<22) //22:22 +#define RX_SENDSTALL (0x1<<21) //21:21 +#define RX_FIFOFULL (0x1<<18) //18:18 +#define RX_FIFOEMPTY (0x1<<17) //17:17 +#define RX_RXPKTRDY (0x1<<16) //16:16 +#define RX_RXMAXPKTSZ (0x7ff<<0) //10:0 + +//U3D_RX5CSR1 +#define RX_MULT (0x3<<22) //23:22 +#define RX_MAX_PKT (0x3f<<16) //21:16 +#define RX_SLOT (0x3f<<8) //13:8 +#define RX_TYPE (0x3<<4) //5:4 +#define SS_RX_BURST (0xf<<0) //3:0 + +//U3D_RX5CSR2 +#define RXBINTERVAL (0xff<<24) //31:24 +#define RXFIFOSEGSIZE (0xf<<16) //19:16 +#define RXFIFOADDR (0x1fff<<0) //12:0 + +//U3D_RX5CSR3 +#define EP_RX_COUNT (0x7ff<<16) //26:16 + +//U3D_RX6CSR0 +#define RX_EP_RESET (0x1<<31) //31:31 +#define RX_AUTOCLEAR (0x1<<30) //30:30 +#define RX_DMAREQEN (0x1<<29) //29:29 +#define RX_SENTSTALL (0x1<<22) //22:22 +#define RX_SENDSTALL (0x1<<21) //21:21 +#define RX_FIFOFULL (0x1<<18) //18:18 +#define RX_FIFOEMPTY (0x1<<17) //17:17 +#define RX_RXPKTRDY (0x1<<16) //16:16 +#define RX_RXMAXPKTSZ (0x7ff<<0) //10:0 + +//U3D_RX6CSR1 +#define RX_MULT (0x3<<22) //23:22 +#define RX_MAX_PKT (0x3f<<16) //21:16 +#define RX_SLOT (0x3f<<8) //13:8 +#define RX_TYPE (0x3<<4) //5:4 +#define SS_RX_BURST (0xf<<0) //3:0 + +//U3D_RX6CSR2 +#define RXBINTERVAL (0xff<<24) //31:24 +#define RXFIFOSEGSIZE (0xf<<16) //19:16 +#define RXFIFOADDR (0x1fff<<0) //12:0 + +//U3D_RX6CSR3 +#define EP_RX_COUNT (0x7ff<<16) //26:16 + +//U3D_RX7CSR0 +#define RX_EP_RESET (0x1<<31) //31:31 +#define RX_AUTOCLEAR (0x1<<30) //30:30 +#define RX_DMAREQEN (0x1<<29) //29:29 +#define RX_SENTSTALL (0x1<<22) //22:22 +#define RX_SENDSTALL (0x1<<21) //21:21 +#define RX_FIFOFULL (0x1<<18) //18:18 +#define RX_FIFOEMPTY (0x1<<17) //17:17 +#define RX_RXPKTRDY (0x1<<16) //16:16 +#define RX_RXMAXPKTSZ (0x7ff<<0) //10:0 + +//U3D_RX7CSR1 +#define RX_MULT (0x3<<22) //23:22 +#define RX_MAX_PKT (0x3f<<16) //21:16 +#define RX_SLOT (0x3f<<8) //13:8 +#define RX_TYPE (0x3<<4) //5:4 +#define SS_RX_BURST (0xf<<0) //3:0 + +//U3D_RX7CSR2 +#define RXBINTERVAL (0xff<<24) //31:24 +#define RXFIFOSEGSIZE (0xf<<16) //19:16 +#define RXFIFOADDR (0x1fff<<0) //12:0 + +//U3D_RX7CSR3 +#define EP_RX_COUNT (0x7ff<<16) //26:16 + +//U3D_RX8CSR0 +#define RX_EP_RESET (0x1<<31) //31:31 +#define RX_AUTOCLEAR (0x1<<30) //30:30 +#define RX_DMAREQEN (0x1<<29) //29:29 +#define RX_SENTSTALL (0x1<<22) //22:22 +#define RX_SENDSTALL (0x1<<21) //21:21 +#define RX_FIFOFULL (0x1<<18) //18:18 +#define RX_FIFOEMPTY (0x1<<17) //17:17 +#define RX_RXPKTRDY (0x1<<16) //16:16 +#define RX_RXMAXPKTSZ (0x7ff<<0) //10:0 + +//U3D_RX8CSR1 +#define RX_MULT (0x3<<22) //23:22 +#define RX_MAX_PKT (0x3f<<16) //21:16 +#define RX_SLOT (0x3f<<8) //13:8 +#define RX_TYPE (0x3<<4) //5:4 +#define SS_RX_BURST (0xf<<0) //3:0 + +//U3D_RX8CSR2 +#define RXBINTERVAL (0xff<<24) //31:24 +#define RXFIFOSEGSIZE (0xf<<16) //19:16 +#define RXFIFOADDR (0x1fff<<0) //12:0 + +//U3D_RX8CSR3 +#define EP_RX_COUNT (0x7ff<<16) //26:16 + +//U3D_RX9CSR0 +#define RX_EP_RESET (0x1<<31) //31:31 +#define RX_AUTOCLEAR (0x1<<30) //30:30 +#define RX_DMAREQEN (0x1<<29) //29:29 +#define RX_SENTSTALL (0x1<<22) //22:22 +#define RX_SENDSTALL (0x1<<21) //21:21 +#define RX_FIFOFULL (0x1<<18) //18:18 +#define RX_FIFOEMPTY (0x1<<17) //17:17 +#define RX_RXPKTRDY (0x1<<16) //16:16 +#define RX_RXMAXPKTSZ (0x7ff<<0) //10:0 + +//U3D_RX9CSR1 +#define RX_MULT (0x3<<22) //23:22 +#define RX_MAX_PKT (0x3f<<16) //21:16 +#define RX_SLOT (0x3f<<8) //13:8 +#define RX_TYPE (0x3<<4) //5:4 +#define SS_RX_BURST (0xf<<0) //3:0 + +//U3D_RX9CSR2 +#define RXBINTERVAL (0xff<<24) //31:24 +#define RXFIFOSEGSIZE (0xf<<16) //19:16 +#define RXFIFOADDR (0x1fff<<0) //12:0 + +//U3D_RX9CSR3 +#define EP_RX_COUNT (0x7ff<<16) //26:16 + +//U3D_RX10CSR0 +#define RX_EP_RESET (0x1<<31) //31:31 +#define RX_AUTOCLEAR (0x1<<30) //30:30 +#define RX_DMAREQEN (0x1<<29) //29:29 +#define RX_SENTSTALL (0x1<<22) //22:22 +#define RX_SENDSTALL (0x1<<21) //21:21 +#define RX_FIFOFULL (0x1<<18) //18:18 +#define RX_FIFOEMPTY (0x1<<17) //17:17 +#define RX_RXPKTRDY (0x1<<16) //16:16 +#define RX_RXMAXPKTSZ (0x7ff<<0) //10:0 + +//U3D_RX10CSR1 +#define RX_MULT (0x3<<22) //23:22 +#define RX_MAX_PKT (0x3f<<16) //21:16 +#define RX_SLOT (0x3f<<8) //13:8 +#define RX_TYPE (0x3<<4) //5:4 +#define SS_RX_BURST (0xf<<0) //3:0 + +//U3D_RX10CSR2 +#define RXBINTERVAL (0xff<<24) //31:24 +#define RXFIFOSEGSIZE (0xf<<16) //19:16 +#define RXFIFOADDR (0x1fff<<0) //12:0 + +//U3D_RX10CSR3 +#define EP_RX_COUNT (0x7ff<<16) //26:16 + +//U3D_RX11CSR0 +#define RX_EP_RESET (0x1<<31) //31:31 +#define RX_AUTOCLEAR (0x1<<30) //30:30 +#define RX_DMAREQEN (0x1<<29) //29:29 +#define RX_SENTSTALL (0x1<<22) //22:22 +#define RX_SENDSTALL (0x1<<21) //21:21 +#define RX_FIFOFULL (0x1<<18) //18:18 +#define RX_FIFOEMPTY (0x1<<17) //17:17 +#define RX_RXPKTRDY (0x1<<16) //16:16 +#define RX_RXMAXPKTSZ (0x7ff<<0) //10:0 + +//U3D_RX11CSR1 +#define RX_MULT (0x3<<22) //23:22 +#define RX_MAX_PKT (0x3f<<16) //21:16 +#define RX_SLOT (0x3f<<8) //13:8 +#define RX_TYPE (0x3<<4) //5:4 +#define SS_RX_BURST (0xf<<0) //3:0 + +//U3D_RX11CSR2 +#define RXBINTERVAL (0xff<<24) //31:24 +#define RXFIFOSEGSIZE (0xf<<16) //19:16 +#define RXFIFOADDR (0x1fff<<0) //12:0 + +//U3D_RX11CSR3 +#define EP_RX_COUNT (0x7ff<<16) //26:16 + +//U3D_RX12CSR0 +#define RX_EP_RESET (0x1<<31) //31:31 +#define RX_AUTOCLEAR (0x1<<30) //30:30 +#define RX_DMAREQEN (0x1<<29) //29:29 +#define RX_SENTSTALL (0x1<<22) //22:22 +#define RX_SENDSTALL (0x1<<21) //21:21 +#define RX_FIFOFULL (0x1<<18) //18:18 +#define RX_FIFOEMPTY (0x1<<17) //17:17 +#define RX_RXPKTRDY (0x1<<16) //16:16 +#define RX_RXMAXPKTSZ (0x7ff<<0) //10:0 + +//U3D_RX12CSR1 +#define RX_MULT (0x3<<22) //23:22 +#define RX_MAX_PKT (0x3f<<16) //21:16 +#define RX_SLOT (0x3f<<8) //13:8 +#define RX_TYPE (0x3<<4) //5:4 +#define SS_RX_BURST (0xf<<0) //3:0 + +//U3D_RX12CSR2 +#define RXBINTERVAL (0xff<<24) //31:24 +#define RXFIFOSEGSIZE (0xf<<16) //19:16 +#define RXFIFOADDR (0x1fff<<0) //12:0 + +//U3D_RX12CSR3 +#define EP_RX_COUNT (0x7ff<<16) //26:16 + +//U3D_RX13CSR0 +#define RX_EP_RESET (0x1<<31) //31:31 +#define RX_AUTOCLEAR (0x1<<30) //30:30 +#define RX_DMAREQEN (0x1<<29) //29:29 +#define RX_SENTSTALL (0x1<<22) //22:22 +#define RX_SENDSTALL (0x1<<21) //21:21 +#define RX_FIFOFULL (0x1<<18) //18:18 +#define RX_FIFOEMPTY (0x1<<17) //17:17 +#define RX_RXPKTRDY (0x1<<16) //16:16 +#define RX_RXMAXPKTSZ (0x7ff<<0) //10:0 + +//U3D_RX13CSR1 +#define RX_MULT (0x3<<22) //23:22 +#define RX_MAX_PKT (0x3f<<16) //21:16 +#define RX_SLOT (0x3f<<8) //13:8 +#define RX_TYPE (0x3<<4) //5:4 +#define SS_RX_BURST (0xf<<0) //3:0 + +//U3D_RX13CSR2 +#define RXBINTERVAL (0xff<<24) //31:24 +#define RXFIFOSEGSIZE (0xf<<16) //19:16 +#define RXFIFOADDR (0x1fff<<0) //12:0 + +//U3D_RX13CSR3 +#define EP_RX_COUNT (0x7ff<<16) //26:16 + +//U3D_RX14CSR0 +#define RX_EP_RESET (0x1<<31) //31:31 +#define RX_AUTOCLEAR (0x1<<30) //30:30 +#define RX_DMAREQEN (0x1<<29) //29:29 +#define RX_SENTSTALL (0x1<<22) //22:22 +#define RX_SENDSTALL (0x1<<21) //21:21 +#define RX_FIFOFULL (0x1<<18) //18:18 +#define RX_FIFOEMPTY (0x1<<17) //17:17 +#define RX_RXPKTRDY (0x1<<16) //16:16 +#define RX_RXMAXPKTSZ (0x7ff<<0) //10:0 + +//U3D_RX14CSR1 +#define RX_MULT (0x3<<22) //23:22 +#define RX_MAX_PKT (0x3f<<16) //21:16 +#define RX_SLOT (0x3f<<8) //13:8 +#define RX_TYPE (0x3<<4) //5:4 +#define SS_RX_BURST (0xf<<0) //3:0 + +//U3D_RX14CSR2 +#define RXBINTERVAL (0xff<<24) //31:24 +#define RXFIFOSEGSIZE (0xf<<16) //19:16 +#define RXFIFOADDR (0x1fff<<0) //12:0 + +//U3D_RX14CSR3 +#define EP_RX_COUNT (0x7ff<<16) //26:16 + +//U3D_RX15CSR0 +#define RX_EP_RESET (0x1<<31) //31:31 +#define RX_AUTOCLEAR (0x1<<30) //30:30 +#define RX_DMAREQEN (0x1<<29) //29:29 +#define RX_SENTSTALL (0x1<<22) //22:22 +#define RX_SENDSTALL (0x1<<21) //21:21 +#define RX_FIFOFULL (0x1<<18) //18:18 +#define RX_FIFOEMPTY (0x1<<17) //17:17 +#define RX_RXPKTRDY (0x1<<16) //16:16 +#define RX_RXMAXPKTSZ (0x7ff<<0) //10:0 + +//U3D_RX15CSR1 +#define RX_MULT (0x3<<22) //23:22 +#define RX_MAX_PKT (0x3f<<16) //21:16 +#define RX_SLOT (0x3f<<8) //13:8 +#define RX_TYPE (0x3<<4) //5:4 +#define SS_RX_BURST (0xf<<0) //3:0 + +//U3D_RX15CSR2 +#define RXBINTERVAL (0xff<<24) //31:24 +#define RXFIFOSEGSIZE (0xf<<16) //19:16 +#define RXFIFOADDR (0x1fff<<0) //12:0 + +//U3D_RX15CSR3 +#define EP_RX_COUNT (0x7ff<<16) //26:16 + +//U3D_FIFO0 +#define BYTE3 (0xff<<24) //31:24 +#define BYTE2 (0xff<<16) //23:16 +#define BYTE1 (0xff<<8) //15:8 +#define BYTE0 (0xff<<0) //7:0 + +//U3D_FIFO1 +#define BYTE3 (0xff<<24) //31:24 +#define BYTE2 (0xff<<16) //23:16 +#define BYTE1 (0xff<<8) //15:8 +#define BYTE0 (0xff<<0) //7:0 + +//U3D_FIFO2 +#define BYTE3 (0xff<<24) //31:24 +#define BYTE2 (0xff<<16) //23:16 +#define BYTE1 (0xff<<8) //15:8 +#define BYTE0 (0xff<<0) //7:0 + +//U3D_FIFO3 +#define BYTE3 (0xff<<24) //31:24 +#define BYTE2 (0xff<<16) //23:16 +#define BYTE1 (0xff<<8) //15:8 +#define BYTE0 (0xff<<0) //7:0 + +//U3D_FIFO4 +#define BYTE3 (0xff<<24) //31:24 +#define BYTE2 (0xff<<16) //23:16 +#define BYTE1 (0xff<<8) //15:8 +#define BYTE0 (0xff<<0) //7:0 + +//U3D_FIFO5 +#define BYTE3 (0xff<<24) //31:24 +#define BYTE2 (0xff<<16) //23:16 +#define BYTE1 (0xff<<8) //15:8 +#define BYTE0 (0xff<<0) //7:0 + +//U3D_FIFO6 +#define BYTE3 (0xff<<24) //31:24 +#define BYTE2 (0xff<<16) //23:16 +#define BYTE1 (0xff<<8) //15:8 +#define BYTE0 (0xff<<0) //7:0 + +//U3D_FIFO7 +#define BYTE3 (0xff<<24) //31:24 +#define BYTE2 (0xff<<16) //23:16 +#define BYTE1 (0xff<<8) //15:8 +#define BYTE0 (0xff<<0) //7:0 + +//U3D_FIFO8 +#define BYTE3 (0xff<<24) //31:24 +#define BYTE2 (0xff<<16) //23:16 +#define BYTE1 (0xff<<8) //15:8 +#define BYTE0 (0xff<<0) //7:0 + +//U3D_FIFO9 +#define BYTE3 (0xff<<24) //31:24 +#define BYTE2 (0xff<<16) //23:16 +#define BYTE1 (0xff<<8) //15:8 +#define BYTE0 (0xff<<0) //7:0 + +//U3D_FIFO10 +#define BYTE3 (0xff<<24) //31:24 +#define BYTE2 (0xff<<16) //23:16 +#define BYTE1 (0xff<<8) //15:8 +#define BYTE0 (0xff<<0) //7:0 + +//U3D_FIFO11 +#define BYTE3 (0xff<<24) //31:24 +#define BYTE2 (0xff<<16) //23:16 +#define BYTE1 (0xff<<8) //15:8 +#define BYTE0 (0xff<<0) //7:0 + +//U3D_FIFO12 +#define BYTE3 (0xff<<24) //31:24 +#define BYTE2 (0xff<<16) //23:16 +#define BYTE1 (0xff<<8) //15:8 +#define BYTE0 (0xff<<0) //7:0 + +//U3D_FIFO13 +#define BYTE3 (0xff<<24) //31:24 +#define BYTE2 (0xff<<16) //23:16 +#define BYTE1 (0xff<<8) //15:8 +#define BYTE0 (0xff<<0) //7:0 + +//U3D_FIFO14 +#define BYTE3 (0xff<<24) //31:24 +#define BYTE2 (0xff<<16) //23:16 +#define BYTE1 (0xff<<8) //15:8 +#define BYTE0 (0xff<<0) //7:0 + +//U3D_FIFO15 +#define BYTE3 (0xff<<24) //31:24 +#define BYTE2 (0xff<<16) //23:16 +#define BYTE1 (0xff<<8) //15:8 +#define BYTE0 (0xff<<0) //7:0 + +//U3D_QCR0 +#define RXQ_CS_EN (0x7fff<<17) //31:17 +#define TXQ_CS_EN (0x7fff<<1) //15:1 +#define CS16B_EN (0x1<<0) //0:0 + +//U3D_QCR1 +#define CFG_TX_ZLP_GPD (0x7fff<<1) //15:1 + +//U3D_QCR2 +#define CFG_TX_ZLP (0x7fff<<1) //15:1 + +//U3D_QCR3 +#define CFG_RX_COZ (0x7fff<<17) //31:17 +#define CFG_RX_ZLP (0x7fff<<1) //15:1 + +//U3D_QGCSR +#define RXQ_EN (0x7fff<<17) //31:17 +#define TXQ_EN (0x7fff<<1) //15:1 + +//U3D_TXQCSR1 +#define TXQ_DMGR_DMSM_CS (0xf<<16) //19:16 +#define TXQ_ACTIVE (0x1<<15) //15:15 +#define TXQ_EPQ_STATE (0xf<<8) //11:8 +#define TXQ_STOP (0x1<<2) //2:2 +#define TXQ_RESUME (0x1<<1) //1:1 +#define TXQ_START (0x1<<0) //0:0 + +//U3D_TXQSAR1 +#define TXQ_START_ADDR (0x3fffffff<<2) //31:2 + +//U3D_TXQCPR1 +#define TXQ_CUR_GPD_ADDR (0x3fffffff<<2) //31:2 + +//U3D_TXQCSR2 +#define TXQ_DMGR_DMSM_CS (0xf<<16) //19:16 +#define TXQ_ACTIVE (0x1<<15) //15:15 +#define TXQ_EPQ_STATE (0xf<<8) //11:8 +#define TXQ_STOP (0x1<<2) //2:2 +#define TXQ_RESUME (0x1<<1) //1:1 +#define TXQ_START (0x1<<0) //0:0 + +//U3D_TXQSAR2 +#define TXQ_START_ADDR (0x3fffffff<<2) //31:2 + +//U3D_TXQCPR2 +#define TXQ_CUR_GPD_ADDR (0x3fffffff<<2) //31:2 + +//U3D_TXQCSR3 +#define TXQ_DMGR_DMSM_CS (0xf<<16) //19:16 +#define TXQ_ACTIVE (0x1<<15) //15:15 +#define TXQ_EPQ_STATE (0xf<<8) //11:8 +#define TXQ_STOP (0x1<<2) //2:2 +#define TXQ_RESUME (0x1<<1) //1:1 +#define TXQ_START (0x1<<0) //0:0 + +//U3D_TXQSAR3 +#define TXQ_START_ADDR (0x3fffffff<<2) //31:2 + +//U3D_TXQCPR3 +#define TXQ_CUR_GPD_ADDR (0x3fffffff<<2) //31:2 + +//U3D_TXQCSR4 +#define TXQ_DMGR_DMSM_CS (0xf<<16) //19:16 +#define TXQ_ACTIVE (0x1<<15) //15:15 +#define TXQ_EPQ_STATE (0xf<<8) //11:8 +#define TXQ_STOP (0x1<<2) //2:2 +#define TXQ_RESUME (0x1<<1) //1:1 +#define TXQ_START (0x1<<0) //0:0 + +//U3D_TXQSAR4 +#define TXQ_START_ADDR (0x3fffffff<<2) //31:2 + +//U3D_TXQCPR4 +#define TXQ_CUR_GPD_ADDR (0x3fffffff<<2) //31:2 + +//U3D_TXQCSR5 +#define TXQ_DMGR_DMSM_CS (0xf<<16) //19:16 +#define TXQ_ACTIVE (0x1<<15) //15:15 +#define TXQ_EPQ_STATE (0xf<<8) //11:8 +#define TXQ_STOP (0x1<<2) //2:2 +#define TXQ_RESUME (0x1<<1) //1:1 +#define TXQ_START (0x1<<0) //0:0 + +//U3D_TXQSAR5 +#define TXQ_START_ADDR (0x3fffffff<<2) //31:2 + +//U3D_TXQCPR5 +#define TXQ_CUR_GPD_ADDR (0x3fffffff<<2) //31:2 + +//U3D_TXQCSR6 +#define TXQ_DMGR_DMSM_CS (0xf<<16) //19:16 +#define TXQ_ACTIVE (0x1<<15) //15:15 +#define TXQ_EPQ_STATE (0xf<<8) //11:8 +#define TXQ_STOP (0x1<<2) //2:2 +#define TXQ_RESUME (0x1<<1) //1:1 +#define TXQ_START (0x1<<0) //0:0 + +//U3D_TXQSAR6 +#define TXQ_START_ADDR (0x3fffffff<<2) //31:2 + +//U3D_TXQCPR6 +#define TXQ_CUR_GPD_ADDR (0x3fffffff<<2) //31:2 + +//U3D_TXQCSR7 +#define TXQ_DMGR_DMSM_CS (0xf<<16) //19:16 +#define TXQ_ACTIVE (0x1<<15) //15:15 +#define TXQ_EPQ_STATE (0xf<<8) //11:8 +#define TXQ_STOP (0x1<<2) //2:2 +#define TXQ_RESUME (0x1<<1) //1:1 +#define TXQ_START (0x1<<0) //0:0 + +//U3D_TXQSAR7 +#define TXQ_START_ADDR (0x3fffffff<<2) //31:2 + +//U3D_TXQCPR7 +#define TXQ_CUR_GPD_ADDR (0x3fffffff<<2) //31:2 + +//U3D_TXQCSR8 +#define TXQ_DMGR_DMSM_CS (0xf<<16) //19:16 +#define TXQ_ACTIVE (0x1<<15) //15:15 +#define TXQ_EPQ_STATE (0xf<<8) //11:8 +#define TXQ_STOP (0x1<<2) //2:2 +#define TXQ_RESUME (0x1<<1) //1:1 +#define TXQ_START (0x1<<0) //0:0 + +//U3D_TXQSAR8 +#define TXQ_START_ADDR (0x3fffffff<<2) //31:2 + +//U3D_TXQCPR8 +#define TXQ_CUR_GPD_ADDR (0x3fffffff<<2) //31:2 + +//U3D_TXQCSR9 +#define TXQ_DMGR_DMSM_CS (0xf<<16) //19:16 +#define TXQ_ACTIVE (0x1<<15) //15:15 +#define TXQ_EPQ_STATE (0xf<<8) //11:8 +#define TXQ_STOP (0x1<<2) //2:2 +#define TXQ_RESUME (0x1<<1) //1:1 +#define TXQ_START (0x1<<0) //0:0 + +//U3D_TXQSAR9 +#define TXQ_START_ADDR (0x3fffffff<<2) //31:2 + +//U3D_TXQCPR9 +#define TXQ_CUR_GPD_ADDR (0x3fffffff<<2) //31:2 + +//U3D_TXQCSR10 +#define TXQ_DMGR_DMSM_CS (0xf<<16) //19:16 +#define TXQ_ACTIVE (0x1<<15) //15:15 +#define TXQ_EPQ_STATE (0xf<<8) //11:8 +#define TXQ_STOP (0x1<<2) //2:2 +#define TXQ_RESUME (0x1<<1) //1:1 +#define TXQ_START (0x1<<0) //0:0 + +//U3D_TXQSAR10 +#define TXQ_START_ADDR (0x3fffffff<<2) //31:2 + +//U3D_TXQCPR10 +#define TXQ_CUR_GPD_ADDR (0x3fffffff<<2) //31:2 + +//U3D_TXQCSR11 +#define TXQ_DMGR_DMSM_CS (0xf<<16) //19:16 +#define TXQ_ACTIVE (0x1<<15) //15:15 +#define TXQ_EPQ_STATE (0xf<<8) //11:8 +#define TXQ_STOP (0x1<<2) //2:2 +#define TXQ_RESUME (0x1<<1) //1:1 +#define TXQ_START (0x1<<0) //0:0 + +//U3D_TXQSAR11 +#define TXQ_START_ADDR (0x3fffffff<<2) //31:2 + +//U3D_TXQCPR11 +#define TXQ_CUR_GPD_ADDR (0x3fffffff<<2) //31:2 + +//U3D_TXQCSR12 +#define TXQ_DMGR_DMSM_CS (0xf<<16) //19:16 +#define TXQ_ACTIVE (0x1<<15) //15:15 +#define TXQ_EPQ_STATE (0xf<<8) //11:8 +#define TXQ_STOP (0x1<<2) //2:2 +#define TXQ_RESUME (0x1<<1) //1:1 +#define TXQ_START (0x1<<0) //0:0 + +//U3D_TXQSAR12 +#define TXQ_START_ADDR (0x3fffffff<<2) //31:2 + +//U3D_TXQCPR12 +#define TXQ_CUR_GPD_ADDR (0x3fffffff<<2) //31:2 + +//U3D_TXQCSR13 +#define TXQ_DMGR_DMSM_CS (0xf<<16) //19:16 +#define TXQ_ACTIVE (0x1<<15) //15:15 +#define TXQ_EPQ_STATE (0xf<<8) //11:8 +#define TXQ_STOP (0x1<<2) //2:2 +#define TXQ_RESUME (0x1<<1) //1:1 +#define TXQ_START (0x1<<0) //0:0 + +//U3D_TXQSAR13 +#define TXQ_START_ADDR (0x3fffffff<<2) //31:2 + +//U3D_TXQCPR13 +#define TXQ_CUR_GPD_ADDR (0x3fffffff<<2) //31:2 + +//U3D_TXQCSR14 +#define TXQ_DMGR_DMSM_CS (0xf<<16) //19:16 +#define TXQ_ACTIVE (0x1<<15) //15:15 +#define TXQ_EPQ_STATE (0xf<<8) //11:8 +#define TXQ_STOP (0x1<<2) //2:2 +#define TXQ_RESUME (0x1<<1) //1:1 +#define TXQ_START (0x1<<0) //0:0 + +//U3D_TXQSAR14 +#define TXQ_START_ADDR (0x3fffffff<<2) //31:2 + +//U3D_TXQCPR14 +#define TXQ_CUR_GPD_ADDR (0x3fffffff<<2) //31:2 + +//U3D_TXQCSR15 +#define TXQ_DMGR_DMSM_CS (0xf<<16) //19:16 +#define TXQ_ACTIVE (0x1<<15) //15:15 +#define TXQ_EPQ_STATE (0xf<<8) //11:8 +#define TXQ_STOP (0x1<<2) //2:2 +#define TXQ_RESUME (0x1<<1) //1:1 +#define TXQ_START (0x1<<0) //0:0 + +//U3D_TXQSAR15 +#define TXQ_START_ADDR (0x3fffffff<<2) //31:2 + +//U3D_TXQCPR15 +#define TXQ_CUR_GPD_ADDR (0x3fffffff<<2) //31:2 + +//U3D_RXQCSR1 +#define RXQ_DMGR_DMSM_CS (0xf<<16) //19:16 +#define RXQ_ACTIVE (0x1<<15) //15:15 +#define RXQ_EPQ_STATE (0x1f<<8) //12:8 +#define RXQ_STOP (0x1<<2) //2:2 +#define RXQ_RESUME (0x1<<1) //1:1 +#define RXQ_START (0x1<<0) //0:0 + +//U3D_RXQSAR1 +#define RXQ_START_ADDR (0x3fffffff<<2) //31:2 + +//U3D_RXQCPR1 +#define RXQ_CUR_GPD_ADDR (0x3fffffff<<2) //31:2 + +//U3D_RXQLDPR1 +#define RXQ_LAST_DONE_PTR (0x3fffffff<<2) //31:2 + +//U3D_RXQCSR2 +#define RXQ_DMGR_DMSM_CS (0xf<<16) //19:16 +#define RXQ_ACTIVE (0x1<<15) //15:15 +#define RXQ_EPQ_STATE (0x1f<<8) //12:8 +#define RXQ_STOP (0x1<<2) //2:2 +#define RXQ_RESUME (0x1<<1) //1:1 +#define RXQ_START (0x1<<0) //0:0 + +//U3D_RXQSAR2 +#define RXQ_START_ADDR (0x3fffffff<<2) //31:2 + +//U3D_RXQCPR2 +#define RXQ_CUR_GPD_ADDR (0x3fffffff<<2) //31:2 + +//U3D_RXQLDPR2 +#define RXQ_LAST_DONE_PTR (0x3fffffff<<2) //31:2 + +//U3D_RXQCSR3 +#define RXQ_DMGR_DMSM_CS (0xf<<16) //19:16 +#define RXQ_ACTIVE (0x1<<15) //15:15 +#define RXQ_EPQ_STATE (0x1f<<8) //12:8 +#define RXQ_STOP (0x1<<2) //2:2 +#define RXQ_RESUME (0x1<<1) //1:1 +#define RXQ_START (0x1<<0) //0:0 + +//U3D_RXQSAR3 +#define RXQ_START_ADDR (0x3fffffff<<2) //31:2 + +//U3D_RXQCPR3 +#define RXQ_CUR_GPD_ADDR (0x3fffffff<<2) //31:2 + +//U3D_RXQLDPR3 +#define RXQ_LAST_DONE_PTR (0x3fffffff<<2) //31:2 + +//U3D_RXQCSR4 +#define RXQ_DMGR_DMSM_CS (0xf<<16) //19:16 +#define RXQ_ACTIVE (0x1<<15) //15:15 +#define RXQ_EPQ_STATE (0x1f<<8) //12:8 +#define RXQ_STOP (0x1<<2) //2:2 +#define RXQ_RESUME (0x1<<1) //1:1 +#define RXQ_START (0x1<<0) //0:0 + +//U3D_RXQSAR4 +#define RXQ_START_ADDR (0x3fffffff<<2) //31:2 + +//U3D_RXQCPR4 +#define RXQ_CUR_GPD_ADDR (0x3fffffff<<2) //31:2 + +//U3D_RXQLDPR4 +#define RXQ_LAST_DONE_PTR (0x3fffffff<<2) //31:2 + +//U3D_RXQCSR5 +#define RXQ_DMGR_DMSM_CS (0xf<<16) //19:16 +#define RXQ_ACTIVE (0x1<<15) //15:15 +#define RXQ_EPQ_STATE (0x1f<<8) //12:8 +#define RXQ_STOP (0x1<<2) //2:2 +#define RXQ_RESUME (0x1<<1) //1:1 +#define RXQ_START (0x1<<0) //0:0 + +//U3D_RXQSAR5 +#define RXQ_START_ADDR (0x3fffffff<<2) //31:2 + +//U3D_RXQCPR5 +#define RXQ_CUR_GPD_ADDR (0x3fffffff<<2) //31:2 + +//U3D_RXQLDPR5 +#define RXQ_LAST_DONE_PTR (0x3fffffff<<2) //31:2 + +//U3D_RXQCSR6 +#define RXQ_DMGR_DMSM_CS (0xf<<16) //19:16 +#define RXQ_ACTIVE (0x1<<15) //15:15 +#define RXQ_EPQ_STATE (0x1f<<8) //12:8 +#define RXQ_STOP (0x1<<2) //2:2 +#define RXQ_RESUME (0x1<<1) //1:1 +#define RXQ_START (0x1<<0) //0:0 + +//U3D_RXQSAR6 +#define RXQ_START_ADDR (0x3fffffff<<2) //31:2 + +//U3D_RXQCPR6 +#define RXQ_CUR_GPD_ADDR (0x3fffffff<<2) //31:2 + +//U3D_RXQLDPR6 +#define RXQ_LAST_DONE_PTR (0x3fffffff<<2) //31:2 + +//U3D_RXQCSR7 +#define RXQ_DMGR_DMSM_CS (0xf<<16) //19:16 +#define RXQ_ACTIVE (0x1<<15) //15:15 +#define RXQ_EPQ_STATE (0x1f<<8) //12:8 +#define RXQ_STOP (0x1<<2) //2:2 +#define RXQ_RESUME (0x1<<1) //1:1 +#define RXQ_START (0x1<<0) //0:0 + +//U3D_RXQSAR7 +#define RXQ_START_ADDR (0x3fffffff<<2) //31:2 + +//U3D_RXQCPR7 +#define RXQ_CUR_GPD_ADDR (0x3fffffff<<2) //31:2 + +//U3D_RXQLDPR7 +#define RXQ_LAST_DONE_PTR (0x3fffffff<<2) //31:2 + +//U3D_RXQCSR8 +#define RXQ_DMGR_DMSM_CS (0xf<<16) //19:16 +#define RXQ_ACTIVE (0x1<<15) //15:15 +#define RXQ_EPQ_STATE (0x1f<<8) //12:8 +#define RXQ_STOP (0x1<<2) //2:2 +#define RXQ_RESUME (0x1<<1) //1:1 +#define RXQ_START (0x1<<0) //0:0 + +//U3D_RXQSAR8 +#define RXQ_START_ADDR (0x3fffffff<<2) //31:2 + +//U3D_RXQCPR8 +#define RXQ_CUR_GPD_ADDR (0x3fffffff<<2) //31:2 + +//U3D_RXQLDPR8 +#define RXQ_LAST_DONE_PTR (0x3fffffff<<2) //31:2 + +//U3D_RXQCSR9 +#define RXQ_DMGR_DMSM_CS (0xf<<16) //19:16 +#define RXQ_ACTIVE (0x1<<15) //15:15 +#define RXQ_EPQ_STATE (0x1f<<8) //12:8 +#define RXQ_STOP (0x1<<2) //2:2 +#define RXQ_RESUME (0x1<<1) //1:1 +#define RXQ_START (0x1<<0) //0:0 + +//U3D_RXQSAR9 +#define RXQ_START_ADDR (0x3fffffff<<2) //31:2 + +//U3D_RXQCPR9 +#define RXQ_CUR_GPD_ADDR (0x3fffffff<<2) //31:2 + +//U3D_RXQLDPR9 +#define RXQ_LAST_DONE_PTR (0x3fffffff<<2) //31:2 + +//U3D_RXQCSR10 +#define RXQ_DMGR_DMSM_CS (0xf<<16) //19:16 +#define RXQ_ACTIVE (0x1<<15) //15:15 +#define RXQ_EPQ_STATE (0x1f<<8) //12:8 +#define RXQ_STOP (0x1<<2) //2:2 +#define RXQ_RESUME (0x1<<1) //1:1 +#define RXQ_START (0x1<<0) //0:0 + +//U3D_RXQSAR10 +#define RXQ_START_ADDR (0x3fffffff<<2) //31:2 + +//U3D_RXQCPR10 +#define RXQ_CUR_GPD_ADDR (0x3fffffff<<2) //31:2 + +//U3D_RXQLDPR10 +#define RXQ_LAST_DONE_PTR (0x3fffffff<<2) //31:2 + +//U3D_RXQCSR11 +#define RXQ_DMGR_DMSM_CS (0xf<<16) //19:16 +#define RXQ_ACTIVE (0x1<<15) //15:15 +#define RXQ_EPQ_STATE (0x1f<<8) //12:8 +#define RXQ_STOP (0x1<<2) //2:2 +#define RXQ_RESUME (0x1<<1) //1:1 +#define RXQ_START (0x1<<0) //0:0 + +//U3D_RXQSAR11 +#define RXQ_START_ADDR (0x3fffffff<<2) //31:2 + +//U3D_RXQCPR11 +#define RXQ_CUR_GPD_ADDR (0x3fffffff<<2) //31:2 + +//U3D_RXQLDPR11 +#define RXQ_LAST_DONE_PTR (0x3fffffff<<2) //31:2 + +//U3D_RXQCSR12 +#define RXQ_DMGR_DMSM_CS (0xf<<16) //19:16 +#define RXQ_ACTIVE (0x1<<15) //15:15 +#define RXQ_EPQ_STATE (0x1f<<8) //12:8 +#define RXQ_STOP (0x1<<2) //2:2 +#define RXQ_RESUME (0x1<<1) //1:1 +#define RXQ_START (0x1<<0) //0:0 + +//U3D_RXQSAR12 +#define RXQ_START_ADDR (0x3fffffff<<2) //31:2 + +//U3D_RXQCPR12 +#define RXQ_CUR_GPD_ADDR (0x3fffffff<<2) //31:2 + +//U3D_RXQLDPR12 +#define RXQ_LAST_DONE_PTR (0x3fffffff<<2) //31:2 + +//U3D_RXQCSR13 +#define RXQ_DMGR_DMSM_CS (0xf<<16) //19:16 +#define RXQ_ACTIVE (0x1<<15) //15:15 +#define RXQ_EPQ_STATE (0x1f<<8) //12:8 +#define RXQ_STOP (0x1<<2) //2:2 +#define RXQ_RESUME (0x1<<1) //1:1 +#define RXQ_START (0x1<<0) //0:0 + +//U3D_RXQSAR13 +#define RXQ_START_ADDR (0x3fffffff<<2) //31:2 + +//U3D_RXQCPR13 +#define RXQ_CUR_GPD_ADDR (0x3fffffff<<2) //31:2 + +//U3D_RXQLDPR13 +#define RXQ_LAST_DONE_PTR (0x3fffffff<<2) //31:2 + +//U3D_RXQCSR14 +#define RXQ_DMGR_DMSM_CS (0xf<<16) //19:16 +#define RXQ_ACTIVE (0x1<<15) //15:15 +#define RXQ_EPQ_STATE (0x1f<<8) //12:8 +#define RXQ_STOP (0x1<<2) //2:2 +#define RXQ_RESUME (0x1<<1) //1:1 +#define RXQ_START (0x1<<0) //0:0 + +//U3D_RXQSAR14 +#define RXQ_START_ADDR (0x3fffffff<<2) //31:2 + +//U3D_RXQCPR14 +#define RXQ_CUR_GPD_ADDR (0x3fffffff<<2) //31:2 + +//U3D_RXQLDPR14 +#define RXQ_LAST_DONE_PTR (0x3fffffff<<2) //31:2 + +//U3D_RXQCSR15 +#define RXQ_DMGR_DMSM_CS (0xf<<16) //19:16 +#define RXQ_ACTIVE (0x1<<15) //15:15 +#define RXQ_EPQ_STATE (0x1f<<8) //12:8 +#define RXQ_STOP (0x1<<2) //2:2 +#define RXQ_RESUME (0x1<<1) //1:1 +#define RXQ_START (0x1<<0) //0:0 + +//U3D_RXQSAR15 +#define RXQ_START_ADDR (0x3fffffff<<2) //31:2 + +//U3D_RXQCPR15 +#define RXQ_CUR_GPD_ADDR (0x3fffffff<<2) //31:2 + +//U3D_RXQLDPR15 +#define RXQ_LAST_DONE_PTR (0x3fffffff<<2) //31:2 + +//U3D_QISAR0 +#define RXQ_DONE_INT (0x7fff<<17) //31:17 +#define TXQ_DONE_INT (0x7fff<<1) //15:1 + +//U3D_QIER0 +#define RXQ_DONE_IER (0x7fff<<17) //31:17 +#define TXQ_DONE_IER (0x7fff<<1) //15:1 + +//U3D_QIESR0 +#define RXQ_DONE_IESR (0x7fff<<17) //31:17 +#define TXQ_DONE_IESR (0x7fff<<1) //15:1 + +//U3D_QIECR0 +#define RXQ_DONE_IECR (0x7fff<<17) //31:17 +#define TXQ_DONE_IECR (0x7fff<<1) //15:1 + +//U3D_QISAR1 +#define RXQ_ZLPERR_INT (0x1<<20) //20:20 +#define RXQ_LENERR_INT (0x1<<18) //18:18 +#define RXQ_CSERR_INT (0x1<<17) //17:17 +#define RXQ_EMPTY_INT (0x1<<16) //16:16 +#define TXQ_LENERR_INT (0x1<<2) //2:2 +#define TXQ_CSERR_INT (0x1<<1) //1:1 +#define TXQ_EMPTY_INT (0x1<<0) //0:0 + +//U3D_QIER1 +#define RXQ_ZLPERR_IER (0x1<<20) //20:20 +#define RXQ_LENERR_IER (0x1<<18) //18:18 +#define RXQ_CSERR_IER (0x1<<17) //17:17 +#define RXQ_EMPTY_IER (0x1<<16) //16:16 +#define TXQ_LENERR_IER (0x1<<2) //2:2 +#define TXQ_CSERR_IER (0x1<<1) //1:1 +#define TXQ_EMPTY_IER (0x1<<0) //0:0 + +//U3D_QIESR1 +#define RXQ_ZLPERR_IESR (0x1<<20) //20:20 +#define RXQ_LENERR_IESR (0x1<<18) //18:18 +#define RXQ_CSERR_IESR (0x1<<17) //17:17 +#define RXQ_EMPTY_IESR (0x1<<16) //16:16 +#define TXQ_LENERR_IESR (0x1<<2) //2:2 +#define TXQ_CSERR_IESR (0x1<<1) //1:1 +#define TXQ_EMPTY_IESR (0x1<<0) //0:0 + +//U3D_QIECR1 +#define RXQ_ZLPERR_IECR (0x1<<20) //20:20 +#define RXQ_LENERR_IECR (0x1<<18) //18:18 +#define RXQ_CSERR_IECR (0x1<<17) //17:17 +#define RXQ_EMPTY_IECR (0x1<<16) //16:16 +#define TXQ_LENERR_IECR (0x1<<2) //2:2 +#define TXQ_CSERR_IECR (0x1<<1) //1:1 +#define TXQ_EMPTY_IECR (0x1<<0) //0:0 + +//U3D_QEMIR +#define RXQ_EMPTY_MASK (0x7fff<<17) //31:17 +#define TXQ_EMPTY_MASK (0x7fff<<1) //15:1 + +//U3D_QEMIER +#define RXQ_EMPTY_IER_MASK (0x7fff<<17) //31:17 +#define TXQ_EMPTY_IER_MASK (0x7fff<<1) //15:1 + +//U3D_QEMIESR +#define RXQ_EMPTY_IESR_MASK (0x7fff<<17) //31:17 +#define TXQ_EMPTY_IESR_MASK (0x7fff<<1) //15:1 + +//U3D_QEMIECR +#define RXQ_EMPTY_IECR_MASK (0x7fff<<17) //31:17 +#define TXQ_EMPTY_IECR_MASK (0x7fff<<1) //15:1 + +//U3D_TQERRIR0 +#define TXQ_LENERR_MASK (0x7fff<<17) //31:17 +#define TXQ_CSERR_MASK (0x7fff<<1) //15:1 + +//U3D_TQERRIER0 +#define TXQ_LENERR_IER_MASK (0x7fff<<17) //31:17 +#define TXQ_CSERR_IER_MASK (0x7fff<<1) //15:1 + +//U3D_TQERRIESR0 +#define TXQ_LENERR_IESR_MASK (0x7fff<<17) //31:17 +#define TXQ_CSERR_IESR_MASK (0x7fff<<1) //15:1 + +//U3D_TQERRIECR0 +#define TXQ_LENERR_IECR_MASK (0x7fff<<17) //31:17 +#define TXQ_CSERR_IECR_MASK (0x7fff<<1) //15:1 + +//U3D_RQERRIR0 +#define RXQ_LENERR_MASK (0x7fff<<17) //31:17 +#define RXQ_CSERR_MASK (0x7fff<<1) //15:1 + +//U3D_RQERRIER0 +#define RXQ_LENERR_IER_MASK (0x7fff<<17) //31:17 +#define RXQ_CSERR_IER_MASK (0x7fff<<1) //15:1 + +//U3D_RQERRIESR0 +#define RXQ_LENERR_IESR_MASK (0x7fff<<17) //31:17 +#define RXQ_CSERR_IESR_MASK (0x7fff<<1) //15:1 + +//U3D_RQERRIECR0 +#define RXQ_LENERR_IECR_MASK (0x7fff<<17) //31:17 +#define RXQ_CSERR_IECR_MASK (0x7fff<<1) //15:1 + +//U3D_RQERRIR1 +#define RXQ_ZLPERR_MASK (0x7fff<<17) //31:17 + +//U3D_RQERRIER1 +#define RXQ_ZLPERR_IER_MASK (0x7fff<<17) //31:17 + +//U3D_RQERRIESR1 +#define RXQ_ZLPERR_IESR_MASK (0x7fff<<17) //31:17 + +//U3D_RQERRIECR1 +#define RXQ_ZLPERR_IECR_MASK (0x7fff<<17) //31:17 + +//U3D_CAP_EP0FFSZ +#define CAP_EP0FFSZ (0xffffffff<<0) //31:0 + +//U3D_CAP_EPNTXFFSZ +#define CAP_EPNTXFFSZ (0xffffffff<<0) //31:0 + +//U3D_CAP_EPNRXFFSZ +#define CAP_EPNRXFFSZ (0xffffffff<<0) //31:0 + +//U3D_CAP_EPINFO +#define CAP_RX_EP_NUM (0x1f<<8) //12:8 +#define CAP_TX_EP_NUM (0x1f<<0) //4:0 + +//U3D_CAP_TX_SLOT1 +#define CAP_TX_SLOT3 (0x3f<<24) //29:24 +#define CAP_TX_SLOT2 (0x3f<<16) //21:16 +#define CAP_TX_SLOT1 (0x3f<<8) //13:8 +#define RSV (0x3f<<0) //5:0 + +//U3D_CAP_TX_SLOT2 +#define CAP_TX_SLOT7 (0x3f<<24) //29:24 +#define CAP_TX_SLOT6 (0x3f<<16) //21:16 +#define CAP_TX_SLOT5 (0x3f<<8) //13:8 +#define CAP_TX_SLOT4 (0x3f<<0) //5:0 + +//U3D_CAP_TX_SLOT3 +#define CAP_TX_SLOT11 (0x3f<<24) //29:24 +#define CAP_TX_SLOT10 (0x3f<<16) //21:16 +#define CAP_TX_SLOT9 (0x3f<<8) //13:8 +#define CAP_TX_SLOT8 (0x3f<<0) //5:0 + +//U3D_CAP_TX_SLOT4 +#define CAP_TX_SLOT15 (0x3f<<24) //29:24 +#define CAP_TX_SLOT14 (0x3f<<16) //21:16 +#define CAP_TX_SLOT13 (0x3f<<8) //13:8 +#define CAP_TX_SLOT12 (0x3f<<0) //5:0 + +//U3D_CAP_RX_SLOT1 +#define CAP_RX_SLOT3 (0x3f<<24) //29:24 +#define CAP_RX_SLOT2 (0x3f<<16) //21:16 +#define CAP_RX_SLOT1 (0x3f<<8) //13:8 +#define RSV (0x3f<<0) //5:0 + +//U3D_CAP_RX_SLOT2 +#define CAP_RX_SLOT7 (0x3f<<24) //29:24 +#define CAP_RX_SLOT6 (0x3f<<16) //21:16 +#define CAP_RX_SLOT5 (0x3f<<8) //13:8 +#define CAP_RX_SLOT4 (0x3f<<0) //5:0 + +//U3D_CAP_RX_SLOT3 +#define CAP_RX_SLOT11 (0x3f<<24) //29:24 +#define CAP_RX_SLOT10 (0x3f<<16) //21:16 +#define CAP_RX_SLOT9 (0x3f<<8) //13:8 +#define CAP_RX_SLOT8 (0x3f<<0) //5:0 + +//U3D_CAP_RX_SLOT4 +#define CAP_RX_SLOT15 (0x3f<<24) //29:24 +#define CAP_RX_SLOT14 (0x3f<<16) //21:16 +#define CAP_RX_SLOT13 (0x3f<<8) //13:8 +#define CAP_RX_SLOT12 (0x3f<<0) //5:0 + +//U3D_MISC_CTRL +#define DMA_BUS_CK_GATE_DIS (0x1<<2) //2:2 +#define VBUS_ON (0x1<<1) //1:1 +#define VBUS_FRC_EN (0x1<<0) //0:0 + + +/* SSUSB_DEV FIELD OFFSET DEFINITION */ + +//U3D_LV1ISR +#define EP_CTRL_INTR_OFST (5) +#define MAC2_INTR_OFST (4) +#define DMA_INTR_OFST (3) +#define MAC3_INTR_OFST (2) +#define QMU_INTR_OFST (1) +#define BMU_INTR_OFST (0) + +//U3D_LV1IER +#define LV1IER_OFST (0) + +//U3D_LV1IESR +#define LV1IESR_OFST (0) + +//U3D_LV1IECR +#define LV1IECR_OFST (0) + +//U3D_AXI_WR_DMA_CFG +#define AXI_WR_ULTRA_NUM_OFST (24) +#define AXI_WR_PRE_ULTRA_NUM_OFST (16) +#define AXI_WR_ULTRA_EN_OFST (0) + +//U3D_AXI_RD_DMA_CFG +#define AXI_RD_ULTRA_NUM_OFST (24) +#define AXI_RD_PRE_ULTRA_NUM_OFST (16) +#define AXI_RD_ULTRA_EN_OFST (0) + +//U3D_MAC_U1_EN_CTRL +#define EXIT_BY_ERDY_DIS_OFST (31) +#define ACCEPT_BMU_RX_EMPTY_CHK_OFST (20) +#define ACCEPT_BMU_TX_EMPTY_CHK_OFST (19) +#define ACCEPT_RXQ_INACTIVE_CHK_OFST (18) +#define ACCEPT_TXQ_INACTIVE_CHK_OFST (17) +#define ACCEPT_EP0_INACTIVE_CHK_OFST (16) +#define REQUEST_BMU_RX_EMPTY_CHK_OFST (4) +#define REQUEST_BMU_TX_EMPTY_CHK_OFST (3) +#define REQUEST_RXQ_INACTIVE_CHK_OFST (2) +#define REQUEST_TXQ_INACTIVE_CHK_OFST (1) +#define REQUEST_EP0_INACTIVE_CHK_OFST (0) + +//U3D_MAC_U2_EN_CTRL +#define EXIT_BY_ERDY_DIS_OFST (31) +#define ACCEPT_BMU_RX_EMPTY_CHK_OFST (20) +#define ACCEPT_BMU_TX_EMPTY_CHK_OFST (19) +#define ACCEPT_RXQ_INACTIVE_CHK_OFST (18) +#define ACCEPT_TXQ_INACTIVE_CHK_OFST (17) +#define ACCEPT_EP0_INACTIVE_CHK_OFST (16) +#define REQUEST_BMU_RX_EMPTY_CHK_OFST (4) +#define REQUEST_BMU_TX_EMPTY_CHK_OFST (3) +#define REQUEST_RXQ_INACTIVE_CHK_OFST (2) +#define REQUEST_TXQ_INACTIVE_CHK_OFST (1) +#define REQUEST_EP0_INACTIVE_CHK_OFST (0) + +//U3D_SRAM_DBG_CTRL +#define EPNRX_SRAM_DEBUG_MODE_OFST (2) +#define EPNTX_SRAM_DEBUG_MODE_OFST (1) +#define EP0_SRAM_DEBUG_MODE_OFST (0) + +//U3D_SRAM_DBG_CTRL_1 +#define SRAM_DEBUG_FIFOSEGSIZE_OFST (24) +#define SRAM_DEBUG_SLOT_OFST (16) +#define SRAM_DEBUG_DP_COUNT_OFST (0) + +//U3D_RISC_SIZE +#define RISC_SIZE_OFST (0) + +//U3D_WRBUF_ERR_STS +#define RX_RDBUF_ERR_STS_OFST (17) +#define TX_WRBUF_ERR_STS_OFST (1) + +//U3D_BUF_ERR_EN +#define RX_RDBUF_ERR_EN_OFST (17) +#define TX_WRBUF_ERR_EN_OFST (1) + +//U3D_EPISR +#define EPRISR_OFST (17) +#define SETUPENDISR_OFST (16) +#define EPTISR_OFST (1) +#define EP0ISR_OFST (0) + +//U3D_EPIER +#define EPRIER_OFST (17) +#define SETUPENDIER_OFST (16) +#define EPTIER_OFST (1) +#define EP0IER_OFST (0) + +//U3D_EPIESR +#define EPRIESR_OFST (17) +#define SETUPENDIESR_OFST (16) +#define EPTIESR_OFST (1) +#define EP0IESR_OFST (0) + +//U3D_EPIECR +#define EPRISR_OFST (17) +#define SETUPENDIECR_OFST (16) +#define EPTIECR_OFST (1) +#define EP0IECR_OFST (0) + +//U3D_DMAISR +#define RXDMAISR_OFST (2) +#define TXDMAISR_OFST (1) +#define EP0DMAISR_OFST (0) + +//U3D_DMAIER +#define RXDMAIER_OFST (2) +#define TXDMAIER_OFST (1) +#define EP0DMAER_OFST (0) + +//U3D_DMAIESR +#define RXDMAIESR_OFST (2) +#define TXDMAIESR_OFST (1) +#define EP0DMAIESR_OFST (0) + +//U3D_DMAIECR +#define RXDMAIECR_OFST (2) +#define TXDMAIECR_OFST (1) +#define EP0DMAIECR_OFST (0) + +//U3D_EP0DMACTRL +#define FFSTRADDR0_OFST (16) +#define ENDPNT_OFST (4) +#define INTEN_OFST (3) +#define DMA_DIR_OFST (1) +#define DMA_EN_OFST (0) + +//U3D_EP0DMASTRADDR +#define DMASTRADDR0_OFST (0) + +//U3D_EP0DMATFRCOUNT +#define DMATFRCNT0_OFST (0) + +//U3D_EP0DMARLCOUNT +#define EP0_DMALIMITER_OFST (28) +#define DMA_FAKE_OFST (27) +#define DMA_BURST_OFST (24) +#define AXI_DMA_OUTSTAND_NUM_OFST (20) +#define AXI_DMA_COHERENCE_OFST (19) +#define AXI_DMA_IOMMU_OFST (18) +#define AXI_DMA_CACHEABLE_OFST (17) +#define AXI_DMA_ULTRA_EN_OFST (16) +#define AXI_DMA_ULTRA_NUM_OFST (8) +#define AXI_DMA_PRE_ULTRA_NUM_OFST (0) + +//U3D_TXDMACTRL +#define FFSTRADDR_OFST (16) +#define ENDPNT_OFST (4) +#define INTEN_OFST (3) +#define DMA_DIR_OFST (1) +#define DMA_EN_OFST (0) + +//U3D_TXDMASTRADDR +#define DMASTRADDR_OFST (0) + +//U3D_TXDMATRDCNT +#define DMATFRCNT_OFST (0) + +//U3D_TXDMARLCOUNT +#define DMALIMITER_OFST (28) +#define DMA_FAKE_OFST (27) +#define DMA_BURST_OFST (24) +#define AXI_DMA_OUTSTAND_NUM_OFST (20) +#define AXI_DMA_COHERENCE_OFST (19) +#define AXI_DMA_IOMMU_OFST (18) +#define AXI_DMA_CACHEABLE_OFST (17) +#define AXI_DMA_ULTRA_EN_OFST (16) +#define AXI_DMA_ULTRA_NUM_OFST (8) +#define AXI_DMA_PRE_ULTRA_NUM_OFST (0) + +//U3D_RXDMACTRL +#define FFSTRADDR_OFST (16) +#define ENDPNT_OFST (4) +#define INTEN_OFST (3) +#define DMA_DIR_OFST (1) +#define DMA_EN_OFST (0) + +//U3D_RXDMASTRADDR +#define DMASTRADDR_OFST (0) + +//U3D_RXDMATRDCNT +#define DMATFRCNT_OFST (0) + +//U3D_RXDMARLCOUNT +#define DMA_NON_BUF_OFST (31) +#define DMALIMITER_OFST (28) +#define DMA_FAKE_OFST (27) +#define DMA_BURST_OFST (24) +#define AXI_DMA_OUTSTAND_NUM_OFST (20) +#define AXI_DMA_COHERENCE_OFST (19) +#define AXI_DMA_IOMMU_OFST (18) +#define AXI_DMA_CACHEABLE_OFST (17) +#define AXI_DMA_ULTRA_EN_OFST (16) +#define AXI_DMA_ULTRA_NUM_OFST (8) +#define AXI_DMA_PRE_ULTRA_NUM_OFST (0) + +//U3D_EP0CSR +#define EP0_EP_RESET_OFST (31) +#define EP0_AUTOCLEAR_OFST (30) +#define EP0_AUTOSET_OFST (29) +#define EP0_DMAREQEN_OFST (28) +#define EP0_SENDSTALL_OFST (25) +#define EP0_FIFOFULL_OFST (23) +#define EP0_SENTSTALL_OFST (22) +#define EP0_DPHTX_OFST (20) +#define EP0_DATAEND_OFST (19) +#define EP0_TXPKTRDY_OFST (18) +#define EP0_SETUPPKTRDY_OFST (17) +#define EP0_RXPKTRDY_OFST (16) +#define EP0_MAXPKTSZ0_OFST (0) + +//U3D_RXCOUNT0 +#define EP0_RX_COUNT_OFST (0) + +//U3D_RESERVED + +//U3D_TX1CSR0 +#define TX_EP_RESET_OFST (31) +#define TX_AUTOSET_OFST (30) +#define TX_DMAREQEN_OFST (29) +#define TX_FIFOFULL_OFST (25) +#define TX_FIFOEMPTY_OFST (24) +#define TX_SENTSTALL_OFST (22) +#define TX_SENDSTALL_OFST (21) +#define TX_TXPKTRDY_OFST (16) +#define TX_TXMAXPKTSZ_OFST (0) + +//U3D_TX1CSR1 +#define TX_MULT_OFST (22) +#define TX_MAX_PKT_OFST (16) +#define TX_SLOT_OFST (8) +#define TXTYPE_OFST (4) +#define SS_TX_BURST_OFST (0) + +//U3D_TX1CSR2 +#define TXBINTERVAL_OFST (24) +#define TXFIFOSEGSIZE_OFST (16) +#define TXFIFOADDR_OFST (0) + +//U3D_TX2CSR0 +#define TX_EP_RESET_OFST (31) +#define TX_AUTOSET_OFST (30) +#define TX_DMAREQEN_OFST (29) +#define TX_FIFOFULL_OFST (25) +#define TX_FIFOEMPTY_OFST (24) +#define TX_SENTSTALL_OFST (22) +#define TX_SENDSTALL_OFST (21) +#define TX_TXPKTRDY_OFST (16) +#define TX_TXMAXPKTSZ_OFST (0) + +//U3D_TX2CSR1 +#define TX_MULT_OFST (22) +#define TX_MAX_PKT_OFST (16) +#define TX_SLOT_OFST (8) +#define TXTYPE_OFST (4) +#define SS_TX_BURST_OFST (0) + +//U3D_TX2CSR2 +#define TXBINTERVAL_OFST (24) +#define TXFIFOSEGSIZE_OFST (16) +#define TXFIFOADDR_OFST (0) + +//U3D_TX3CSR0 +#define TX_EP_RESET_OFST (31) +#define TX_AUTOSET_OFST (30) +#define TX_DMAREQEN_OFST (29) +#define TX_FIFOFULL_OFST (25) +#define TX_FIFOEMPTY_OFST (24) +#define TX_SENTSTALL_OFST (22) +#define TX_SENDSTALL_OFST (21) +#define TX_TXPKTRDY_OFST (16) +#define TX_TXMAXPKTSZ_OFST (0) + +//U3D_TX3CSR1 +#define TX_MULT_OFST (22) +#define TX_MAX_PKT_OFST (16) +#define TX_SLOT_OFST (8) +#define TXTYPE_OFST (4) +#define SS_TX_BURST_OFST (0) + +//U3D_TX3CSR2 +#define TXBINTERVAL_OFST (24) +#define TXFIFOSEGSIZE_OFST (16) +#define TXFIFOADDR_OFST (0) + +//U3D_TX4CSR0 +#define TX_EP_RESET_OFST (31) +#define TX_AUTOSET_OFST (30) +#define TX_DMAREQEN_OFST (29) +#define TX_FIFOFULL_OFST (25) +#define TX_FIFOEMPTY_OFST (24) +#define TX_SENTSTALL_OFST (22) +#define TX_SENDSTALL_OFST (21) +#define TX_TXPKTRDY_OFST (16) +#define TX_TXMAXPKTSZ_OFST (0) + +//U3D_TX4CSR1 +#define TX_MULT_OFST (22) +#define TX_MAX_PKT_OFST (16) +#define TX_SLOT_OFST (8) +#define TXTYPE_OFST (4) +#define SS_TX_BURST_OFST (0) + +//U3D_TX4CSR2 +#define TXBINTERVAL_OFST (24) +#define TXFIFOSEGSIZE_OFST (16) +#define TXFIFOADDR_OFST (0) + +//U3D_TX5CSR0 +#define TX_EP_RESET_OFST (31) +#define TX_AUTOSET_OFST (30) +#define TX_DMAREQEN_OFST (29) +#define TX_FIFOFULL_OFST (25) +#define TX_FIFOEMPTY_OFST (24) +#define TX_SENTSTALL_OFST (22) +#define TX_SENDSTALL_OFST (21) +#define TX_TXPKTRDY_OFST (16) +#define TX_TXMAXPKTSZ_OFST (0) + +//U3D_TX5CSR1 +#define TX_MULT_OFST (22) +#define TX_MAX_PKT_OFST (16) +#define TX_SLOT_OFST (8) +#define TXTYPE_OFST (4) +#define SS_TX_BURST_OFST (0) + +//U3D_TX5CSR2 +#define TXBINTERVAL_OFST (24) +#define TXFIFOSEGSIZE_OFST (16) +#define TXFIFOADDR_OFST (0) + +//U3D_TX6CSR0 +#define TX_EP_RESET_OFST (31) +#define TX_AUTOSET_OFST (30) +#define TX_DMAREQEN_OFST (29) +#define TX_FIFOFULL_OFST (25) +#define TX_FIFOEMPTY_OFST (24) +#define TX_SENTSTALL_OFST (22) +#define TX_SENDSTALL_OFST (21) +#define TX_TXPKTRDY_OFST (16) +#define TX_TXMAXPKTSZ_OFST (0) + +//U3D_TX6CSR1 +#define TX_MULT_OFST (22) +#define TX_MAX_PKT_OFST (16) +#define TX_SLOT_OFST (8) +#define TXTYPE_OFST (4) +#define SS_TX_BURST_OFST (0) + +//U3D_TX6CSR2 +#define TXBINTERVAL_OFST (24) +#define TXFIFOSEGSIZE_OFST (16) +#define TXFIFOADDR_OFST (0) + +//U3D_TX7CSR0 +#define TX_EP_RESET_OFST (31) +#define TX_AUTOSET_OFST (30) +#define TX_DMAREQEN_OFST (29) +#define TX_FIFOFULL_OFST (25) +#define TX_FIFOEMPTY_OFST (24) +#define TX_SENTSTALL_OFST (22) +#define TX_SENDSTALL_OFST (21) +#define TX_TXPKTRDY_OFST (16) +#define TX_TXMAXPKTSZ_OFST (0) + +//U3D_TX7CSR1 +#define TX_MULT_OFST (22) +#define TX_MAX_PKT_OFST (16) +#define TX_SLOT_OFST (8) +#define TXTYPE_OFST (4) +#define SS_TX_BURST_OFST (0) + +//U3D_TX7CSR2 +#define TXBINTERVAL_OFST (24) +#define TXFIFOSEGSIZE_OFST (16) +#define TXFIFOADDR_OFST (0) + +//U3D_TX8CSR0 +#define TX_EP_RESET_OFST (31) +#define TX_AUTOSET_OFST (30) +#define TX_DMAREQEN_OFST (29) +#define TX_FIFOFULL_OFST (25) +#define TX_FIFOEMPTY_OFST (24) +#define TX_SENTSTALL_OFST (22) +#define TX_SENDSTALL_OFST (21) +#define TX_TXPKTRDY_OFST (16) +#define TX_TXMAXPKTSZ_OFST (0) + +//U3D_TX8CSR1 +#define TX_MULT_OFST (22) +#define TX_MAX_PKT_OFST (16) +#define TX_SLOT_OFST (8) +#define TXTYPE_OFST (4) +#define SS_TX_BURST_OFST (0) + +//U3D_TX8CSR2 +#define TXBINTERVAL_OFST (24) +#define TXFIFOSEGSIZE_OFST (16) +#define TXFIFOADDR_OFST (0) + +//U3D_TX9CSR0 +#define TX_EP_RESET_OFST (31) +#define TX_AUTOSET_OFST (30) +#define TX_DMAREQEN_OFST (29) +#define TX_FIFOFULL_OFST (25) +#define TX_FIFOEMPTY_OFST (24) +#define TX_SENTSTALL_OFST (22) +#define TX_SENDSTALL_OFST (21) +#define TX_TXPKTRDY_OFST (16) +#define TX_TXMAXPKTSZ_OFST (0) + +//U3D_TX9CSR1 +#define TX_MULT_OFST (22) +#define TX_MAX_PKT_OFST (16) +#define TX_SLOT_OFST (8) +#define TXTYPE_OFST (4) +#define SS_TX_BURST_OFST (0) + +//U3D_TX9CSR2 +#define TXBINTERVAL_OFST (24) +#define TXFIFOSEGSIZE_OFST (16) +#define TXFIFOADDR_OFST (0) + +//U3D_TX10CSR0 +#define TX_EP_RESET_OFST (31) +#define TX_AUTOSET_OFST (30) +#define TX_DMAREQEN_OFST (29) +#define TX_FIFOFULL_OFST (25) +#define TX_FIFOEMPTY_OFST (24) +#define TX_SENTSTALL_OFST (22) +#define TX_SENDSTALL_OFST (21) +#define TX_TXPKTRDY_OFST (16) +#define TX_TXMAXPKTSZ_OFST (0) + +//U3D_TX10CSR1 +#define TX_MULT_OFST (22) +#define TX_MAX_PKT_OFST (16) +#define TX_SLOT_OFST (8) +#define TXTYPE_OFST (4) +#define SS_TX_BURST_OFST (0) + +//U3D_TX10CSR2 +#define TXBINTERVAL_OFST (24) +#define TXFIFOSEGSIZE_OFST (16) +#define TXFIFOADDR_OFST (0) + +//U3D_TX11CSR0 +#define TX_EP_RESET_OFST (31) +#define TX_AUTOSET_OFST (30) +#define TX_DMAREQEN_OFST (29) +#define TX_FIFOFULL_OFST (25) +#define TX_FIFOEMPTY_OFST (24) +#define TX_SENTSTALL_OFST (22) +#define TX_SENDSTALL_OFST (21) +#define TX_TXPKTRDY_OFST (16) +#define TX_TXMAXPKTSZ_OFST (0) + +//U3D_TX11CSR1 +#define TX_MULT_OFST (22) +#define TX_MAX_PKT_OFST (16) +#define TX_SLOT_OFST (8) +#define TXTYPE_OFST (4) +#define SS_TX_BURST_OFST (0) + +//U3D_TX11CSR2 +#define TXBINTERVAL_OFST (24) +#define TXFIFOSEGSIZE_OFST (16) +#define TXFIFOADDR_OFST (0) + +//U3D_TX12CSR0 +#define TX_EP_RESET_OFST (31) +#define TX_AUTOSET_OFST (30) +#define TX_DMAREQEN_OFST (29) +#define TX_FIFOFULL_OFST (25) +#define TX_FIFOEMPTY_OFST (24) +#define TX_SENTSTALL_OFST (22) +#define TX_SENDSTALL_OFST (21) +#define TX_TXPKTRDY_OFST (16) +#define TX_TXMAXPKTSZ_OFST (0) + +//U3D_TX12CSR1 +#define TX_MULT_OFST (22) +#define TX_MAX_PKT_OFST (16) +#define TX_SLOT_OFST (8) +#define TXTYPE_OFST (4) +#define SS_TX_BURST_OFST (0) + +//U3D_TX12CSR2 +#define TXBINTERVAL_OFST (24) +#define TXFIFOSEGSIZE_OFST (16) +#define TXFIFOADDR_OFST (0) + +//U3D_TX13CSR0 +#define TX_EP_RESET_OFST (31) +#define TX_AUTOSET_OFST (30) +#define TX_DMAREQEN_OFST (29) +#define TX_FIFOFULL_OFST (25) +#define TX_FIFOEMPTY_OFST (24) +#define TX_SENTSTALL_OFST (22) +#define TX_SENDSTALL_OFST (21) +#define TX_TXPKTRDY_OFST (16) +#define TX_TXMAXPKTSZ_OFST (0) + +//U3D_TX13CSR1 +#define TX_MULT_OFST (22) +#define TX_MAX_PKT_OFST (16) +#define TX_SLOT_OFST (8) +#define TXTYPE_OFST (4) +#define SS_TX_BURST_OFST (0) + +//U3D_TX13CSR2 +#define TXBINTERVAL_OFST (24) +#define TXFIFOSEGSIZE_OFST (16) +#define TXFIFOADDR_OFST (0) + +//U3D_TX14CSR0 +#define TX_EP_RESET_OFST (31) +#define TX_AUTOSET_OFST (30) +#define TX_DMAREQEN_OFST (29) +#define TX_FIFOFULL_OFST (25) +#define TX_FIFOEMPTY_OFST (24) +#define TX_SENTSTALL_OFST (22) +#define TX_SENDSTALL_OFST (21) +#define TX_TXPKTRDY_OFST (16) +#define TX_TXMAXPKTSZ_OFST (0) + +//U3D_TX14CSR1 +#define TX_MULT_OFST (22) +#define TX_MAX_PKT_OFST (16) +#define TX_SLOT_OFST (8) +#define TXTYPE_OFST (4) +#define SS_TX_BURST_OFST (0) + +//U3D_TX14CSR2 +#define TXBINTERVAL_OFST (24) +#define TXFIFOSEGSIZE_OFST (16) +#define TXFIFOADDR_OFST (0) + +//U3D_TX15CSR0 +#define TX_EP_RESET_OFST (31) +#define TX_AUTOSET_OFST (30) +#define TX_DMAREQEN_OFST (29) +#define TX_FIFOFULL_OFST (25) +#define TX_FIFOEMPTY_OFST (24) +#define TX_SENTSTALL_OFST (22) +#define TX_SENDSTALL_OFST (21) +#define TX_TXPKTRDY_OFST (16) +#define TX_TXMAXPKTSZ_OFST (0) + +//U3D_TX15CSR1 +#define TX_MULT_OFST (22) +#define TX_MAX_PKT_OFST (16) +#define TX_SLOT_OFST (8) +#define TXTYPE_OFST (4) +#define SS_TX_BURST_OFST (0) + +//U3D_TX15CSR2 +#define TXBINTERVAL_OFST (24) +#define TXFIFOSEGSIZE_OFST (16) +#define TXFIFOADDR_OFST (0) + +//U3D_RX1CSR0 +#define RX_EP_RESET_OFST (31) +#define RX_AUTOCLEAR_OFST (30) +#define RX_DMAREQEN_OFST (29) +#define RX_SENTSTALL_OFST (22) +#define RX_SENDSTALL_OFST (21) +#define RX_FIFOFULL_OFST (18) +#define RX_FIFOEMPTY_OFST (17) +#define RX_RXPKTRDY_OFST (16) +#define RX_RXMAXPKTSZ_OFST (0) + +//U3D_RX1CSR1 +#define RX_MULT_OFST (22) +#define RX_MAX_PKT_OFST (16) +#define RX_SLOT_OFST (8) +#define RX_TYPE_OFST (4) +#define SS_RX_BURST_OFST (0) + +//U3D_RX1CSR2 +#define RXBINTERVAL_OFST (24) +#define RXFIFOSEGSIZE_OFST (16) +#define RXFIFOADDR_OFST (0) + +//U3D_RX1CSR3 +#define EP_RX_COUNT_OFST (16) + +//U3D_RX2CSR0 +#define RX_EP_RESET_OFST (31) +#define RX_AUTOCLEAR_OFST (30) +#define RX_DMAREQEN_OFST (29) +#define RX_SENTSTALL_OFST (22) +#define RX_SENDSTALL_OFST (21) +#define RX_FIFOFULL_OFST (18) +#define RX_FIFOEMPTY_OFST (17) +#define RX_RXPKTRDY_OFST (16) +#define RX_RXMAXPKTSZ_OFST (0) + +//U3D_RX2CSR1 +#define RX_MULT_OFST (22) +#define RX_MAX_PKT_OFST (16) +#define RX_SLOT_OFST (8) +#define RX_TYPE_OFST (4) +#define SS_RX_BURST_OFST (0) + +//U3D_RX2CSR2 +#define RXBINTERVAL_OFST (24) +#define RXFIFOSEGSIZE_OFST (16) +#define RXFIFOADDR_OFST (0) + +//U3D_RX2CSR3 +#define EP_RX_COUNT_OFST (16) + +//U3D_RX3CSR0 +#define RX_EP_RESET_OFST (31) +#define RX_AUTOCLEAR_OFST (30) +#define RX_DMAREQEN_OFST (29) +#define RX_SENTSTALL_OFST (22) +#define RX_SENDSTALL_OFST (21) +#define RX_FIFOFULL_OFST (18) +#define RX_FIFOEMPTY_OFST (17) +#define RX_RXPKTRDY_OFST (16) +#define RX_RXMAXPKTSZ_OFST (0) + +//U3D_RX3CSR1 +#define RX_MULT_OFST (22) +#define RX_MAX_PKT_OFST (16) +#define RX_SLOT_OFST (8) +#define RX_TYPE_OFST (4) +#define SS_RX_BURST_OFST (0) + +//U3D_RX3CSR2 +#define RXBINTERVAL_OFST (24) +#define RXFIFOSEGSIZE_OFST (16) +#define RXFIFOADDR_OFST (0) + +//U3D_RX3CSR3 +#define EP_RX_COUNT_OFST (16) + +//U3D_RX4CSR0 +#define RX_EP_RESET_OFST (31) +#define RX_AUTOCLEAR_OFST (30) +#define RX_DMAREQEN_OFST (29) +#define RX_SENTSTALL_OFST (22) +#define RX_SENDSTALL_OFST (21) +#define RX_FIFOFULL_OFST (18) +#define RX_FIFOEMPTY_OFST (17) +#define RX_RXPKTRDY_OFST (16) +#define RX_RXMAXPKTSZ_OFST (0) + +//U3D_RX4CSR1 +#define RX_MULT_OFST (22) +#define RX_MAX_PKT_OFST (16) +#define RX_SLOT_OFST (8) +#define RX_TYPE_OFST (4) +#define SS_RX_BURST_OFST (0) + +//U3D_RX4CSR2 +#define RXBINTERVAL_OFST (24) +#define RXFIFOSEGSIZE_OFST (16) +#define RXFIFOADDR_OFST (0) + +//U3D_RX4CSR3 +#define EP_RX_COUNT_OFST (16) + +//U3D_RX5CSR0 +#define RX_EP_RESET_OFST (31) +#define RX_AUTOCLEAR_OFST (30) +#define RX_DMAREQEN_OFST (29) +#define RX_SENTSTALL_OFST (22) +#define RX_SENDSTALL_OFST (21) +#define RX_FIFOFULL_OFST (18) +#define RX_FIFOEMPTY_OFST (17) +#define RX_RXPKTRDY_OFST (16) +#define RX_RXMAXPKTSZ_OFST (0) + +//U3D_RX5CSR1 +#define RX_MULT_OFST (22) +#define RX_MAX_PKT_OFST (16) +#define RX_SLOT_OFST (8) +#define RX_TYPE_OFST (4) +#define SS_RX_BURST_OFST (0) + +//U3D_RX5CSR2 +#define RXBINTERVAL_OFST (24) +#define RXFIFOSEGSIZE_OFST (16) +#define RXFIFOADDR_OFST (0) + +//U3D_RX5CSR3 +#define EP_RX_COUNT_OFST (16) + +//U3D_RX6CSR0 +#define RX_EP_RESET_OFST (31) +#define RX_AUTOCLEAR_OFST (30) +#define RX_DMAREQEN_OFST (29) +#define RX_SENTSTALL_OFST (22) +#define RX_SENDSTALL_OFST (21) +#define RX_FIFOFULL_OFST (18) +#define RX_FIFOEMPTY_OFST (17) +#define RX_RXPKTRDY_OFST (16) +#define RX_RXMAXPKTSZ_OFST (0) + +//U3D_RX6CSR1 +#define RX_MULT_OFST (22) +#define RX_MAX_PKT_OFST (16) +#define RX_SLOT_OFST (8) +#define RX_TYPE_OFST (4) +#define SS_RX_BURST_OFST (0) + +//U3D_RX6CSR2 +#define RXBINTERVAL_OFST (24) +#define RXFIFOSEGSIZE_OFST (16) +#define RXFIFOADDR_OFST (0) + +//U3D_RX6CSR3 +#define EP_RX_COUNT_OFST (16) + +//U3D_RX7CSR0 +#define RX_EP_RESET_OFST (31) +#define RX_AUTOCLEAR_OFST (30) +#define RX_DMAREQEN_OFST (29) +#define RX_SENTSTALL_OFST (22) +#define RX_SENDSTALL_OFST (21) +#define RX_FIFOFULL_OFST (18) +#define RX_FIFOEMPTY_OFST (17) +#define RX_RXPKTRDY_OFST (16) +#define RX_RXMAXPKTSZ_OFST (0) + +//U3D_RX7CSR1 +#define RX_MULT_OFST (22) +#define RX_MAX_PKT_OFST (16) +#define RX_SLOT_OFST (8) +#define RX_TYPE_OFST (4) +#define SS_RX_BURST_OFST (0) + +//U3D_RX7CSR2 +#define RXBINTERVAL_OFST (24) +#define RXFIFOSEGSIZE_OFST (16) +#define RXFIFOADDR_OFST (0) + +//U3D_RX7CSR3 +#define EP_RX_COUNT_OFST (16) + +//U3D_RX8CSR0 +#define RX_EP_RESET_OFST (31) +#define RX_AUTOCLEAR_OFST (30) +#define RX_DMAREQEN_OFST (29) +#define RX_SENTSTALL_OFST (22) +#define RX_SENDSTALL_OFST (21) +#define RX_FIFOFULL_OFST (18) +#define RX_FIFOEMPTY_OFST (17) +#define RX_RXPKTRDY_OFST (16) +#define RX_RXMAXPKTSZ_OFST (0) + +//U3D_RX8CSR1 +#define RX_MULT_OFST (22) +#define RX_MAX_PKT_OFST (16) +#define RX_SLOT_OFST (8) +#define RX_TYPE_OFST (4) +#define SS_RX_BURST_OFST (0) + +//U3D_RX8CSR2 +#define RXBINTERVAL_OFST (24) +#define RXFIFOSEGSIZE_OFST (16) +#define RXFIFOADDR_OFST (0) + +//U3D_RX8CSR3 +#define EP_RX_COUNT_OFST (16) + +//U3D_RX9CSR0 +#define RX_EP_RESET_OFST (31) +#define RX_AUTOCLEAR_OFST (30) +#define RX_DMAREQEN_OFST (29) +#define RX_SENTSTALL_OFST (22) +#define RX_SENDSTALL_OFST (21) +#define RX_FIFOFULL_OFST (18) +#define RX_FIFOEMPTY_OFST (17) +#define RX_RXPKTRDY_OFST (16) +#define RX_RXMAXPKTSZ_OFST (0) + +//U3D_RX9CSR1 +#define RX_MULT_OFST (22) +#define RX_MAX_PKT_OFST (16) +#define RX_SLOT_OFST (8) +#define RX_TYPE_OFST (4) +#define SS_RX_BURST_OFST (0) + +//U3D_RX9CSR2 +#define RXBINTERVAL_OFST (24) +#define RXFIFOSEGSIZE_OFST (16) +#define RXFIFOADDR_OFST (0) + +//U3D_RX9CSR3 +#define EP_RX_COUNT_OFST (16) + +//U3D_RX10CSR0 +#define RX_EP_RESET_OFST (31) +#define RX_AUTOCLEAR_OFST (30) +#define RX_DMAREQEN_OFST (29) +#define RX_SENTSTALL_OFST (22) +#define RX_SENDSTALL_OFST (21) +#define RX_FIFOFULL_OFST (18) +#define RX_FIFOEMPTY_OFST (17) +#define RX_RXPKTRDY_OFST (16) +#define RX_RXMAXPKTSZ_OFST (0) + +//U3D_RX10CSR1 +#define RX_MULT_OFST (22) +#define RX_MAX_PKT_OFST (16) +#define RX_SLOT_OFST (8) +#define RX_TYPE_OFST (4) +#define SS_RX_BURST_OFST (0) + +//U3D_RX10CSR2 +#define RXBINTERVAL_OFST (24) +#define RXFIFOSEGSIZE_OFST (16) +#define RXFIFOADDR_OFST (0) + +//U3D_RX10CSR3 +#define EP_RX_COUNT_OFST (16) + +//U3D_RX11CSR0 +#define RX_EP_RESET_OFST (31) +#define RX_AUTOCLEAR_OFST (30) +#define RX_DMAREQEN_OFST (29) +#define RX_SENTSTALL_OFST (22) +#define RX_SENDSTALL_OFST (21) +#define RX_FIFOFULL_OFST (18) +#define RX_FIFOEMPTY_OFST (17) +#define RX_RXPKTRDY_OFST (16) +#define RX_RXMAXPKTSZ_OFST (0) + +//U3D_RX11CSR1 +#define RX_MULT_OFST (22) +#define RX_MAX_PKT_OFST (16) +#define RX_SLOT_OFST (8) +#define RX_TYPE_OFST (4) +#define SS_RX_BURST_OFST (0) + +//U3D_RX11CSR2 +#define RXBINTERVAL_OFST (24) +#define RXFIFOSEGSIZE_OFST (16) +#define RXFIFOADDR_OFST (0) + +//U3D_RX11CSR3 +#define EP_RX_COUNT_OFST (16) + +//U3D_RX12CSR0 +#define RX_EP_RESET_OFST (31) +#define RX_AUTOCLEAR_OFST (30) +#define RX_DMAREQEN_OFST (29) +#define RX_SENTSTALL_OFST (22) +#define RX_SENDSTALL_OFST (21) +#define RX_FIFOFULL_OFST (18) +#define RX_FIFOEMPTY_OFST (17) +#define RX_RXPKTRDY_OFST (16) +#define RX_RXMAXPKTSZ_OFST (0) + +//U3D_RX12CSR1 +#define RX_MULT_OFST (22) +#define RX_MAX_PKT_OFST (16) +#define RX_SLOT_OFST (8) +#define RX_TYPE_OFST (4) +#define SS_RX_BURST_OFST (0) + +//U3D_RX12CSR2 +#define RXBINTERVAL_OFST (24) +#define RXFIFOSEGSIZE_OFST (16) +#define RXFIFOADDR_OFST (0) + +//U3D_RX12CSR3 +#define EP_RX_COUNT_OFST (16) + +//U3D_RX13CSR0 +#define RX_EP_RESET_OFST (31) +#define RX_AUTOCLEAR_OFST (30) +#define RX_DMAREQEN_OFST (29) +#define RX_SENTSTALL_OFST (22) +#define RX_SENDSTALL_OFST (21) +#define RX_FIFOFULL_OFST (18) +#define RX_FIFOEMPTY_OFST (17) +#define RX_RXPKTRDY_OFST (16) +#define RX_RXMAXPKTSZ_OFST (0) + +//U3D_RX13CSR1 +#define RX_MULT_OFST (22) +#define RX_MAX_PKT_OFST (16) +#define RX_SLOT_OFST (8) +#define RX_TYPE_OFST (4) +#define SS_RX_BURST_OFST (0) + +//U3D_RX13CSR2 +#define RXBINTERVAL_OFST (24) +#define RXFIFOSEGSIZE_OFST (16) +#define RXFIFOADDR_OFST (0) + +//U3D_RX13CSR3 +#define EP_RX_COUNT_OFST (16) + +//U3D_RX14CSR0 +#define RX_EP_RESET_OFST (31) +#define RX_AUTOCLEAR_OFST (30) +#define RX_DMAREQEN_OFST (29) +#define RX_SENTSTALL_OFST (22) +#define RX_SENDSTALL_OFST (21) +#define RX_FIFOFULL_OFST (18) +#define RX_FIFOEMPTY_OFST (17) +#define RX_RXPKTRDY_OFST (16) +#define RX_RXMAXPKTSZ_OFST (0) + +//U3D_RX14CSR1 +#define RX_MULT_OFST (22) +#define RX_MAX_PKT_OFST (16) +#define RX_SLOT_OFST (8) +#define RX_TYPE_OFST (4) +#define SS_RX_BURST_OFST (0) + +//U3D_RX14CSR2 +#define RXBINTERVAL_OFST (24) +#define RXFIFOSEGSIZE_OFST (16) +#define RXFIFOADDR_OFST (0) + +//U3D_RX14CSR3 +#define EP_RX_COUNT_OFST (16) + +//U3D_RX15CSR0 +#define RX_EP_RESET_OFST (31) +#define RX_AUTOCLEAR_OFST (30) +#define RX_DMAREQEN_OFST (29) +#define RX_SENTSTALL_OFST (22) +#define RX_SENDSTALL_OFST (21) +#define RX_FIFOFULL_OFST (18) +#define RX_FIFOEMPTY_OFST (17) +#define RX_RXPKTRDY_OFST (16) +#define RX_RXMAXPKTSZ_OFST (0) + +//U3D_RX15CSR1 +#define RX_MULT_OFST (22) +#define RX_MAX_PKT_OFST (16) +#define RX_SLOT_OFST (8) +#define RX_TYPE_OFST (4) +#define SS_RX_BURST_OFST (0) + +//U3D_RX15CSR2 +#define RXBINTERVAL_OFST (24) +#define RXFIFOSEGSIZE_OFST (16) +#define RXFIFOADDR_OFST (0) + +//U3D_RX15CSR3 +#define EP_RX_COUNT_OFST (16) + +//U3D_FIFO0 +#define BYTE3_OFST (24) +#define BYTE2_OFST (16) +#define BYTE1_OFST (8) +#define BYTE0_OFST (0) + +//U3D_FIFO1 +#define BYTE3_OFST (24) +#define BYTE2_OFST (16) +#define BYTE1_OFST (8) +#define BYTE0_OFST (0) + +//U3D_FIFO2 +#define BYTE3_OFST (24) +#define BYTE2_OFST (16) +#define BYTE1_OFST (8) +#define BYTE0_OFST (0) + +//U3D_FIFO3 +#define BYTE3_OFST (24) +#define BYTE2_OFST (16) +#define BYTE1_OFST (8) +#define BYTE0_OFST (0) + +//U3D_FIFO4 +#define BYTE3_OFST (24) +#define BYTE2_OFST (16) +#define BYTE1_OFST (8) +#define BYTE0_OFST (0) + +//U3D_FIFO5 +#define BYTE3_OFST (24) +#define BYTE2_OFST (16) +#define BYTE1_OFST (8) +#define BYTE0_OFST (0) + +//U3D_FIFO6 +#define BYTE3_OFST (24) +#define BYTE2_OFST (16) +#define BYTE1_OFST (8) +#define BYTE0_OFST (0) + +//U3D_FIFO7 +#define BYTE3_OFST (24) +#define BYTE2_OFST (16) +#define BYTE1_OFST (8) +#define BYTE0_OFST (0) + +//U3D_FIFO8 +#define BYTE3_OFST (24) +#define BYTE2_OFST (16) +#define BYTE1_OFST (8) +#define BYTE0_OFST (0) + +//U3D_FIFO9 +#define BYTE3_OFST (24) +#define BYTE2_OFST (16) +#define BYTE1_OFST (8) +#define BYTE0_OFST (0) + +//U3D_FIFO10 +#define BYTE3_OFST (24) +#define BYTE2_OFST (16) +#define BYTE1_OFST (8) +#define BYTE0_OFST (0) + +//U3D_FIFO11 +#define BYTE3_OFST (24) +#define BYTE2_OFST (16) +#define BYTE1_OFST (8) +#define BYTE0_OFST (0) + +//U3D_FIFO12 +#define BYTE3_OFST (24) +#define BYTE2_OFST (16) +#define BYTE1_OFST (8) +#define BYTE0_OFST (0) + +//U3D_FIFO13 +#define BYTE3_OFST (24) +#define BYTE2_OFST (16) +#define BYTE1_OFST (8) +#define BYTE0_OFST (0) + +//U3D_FIFO14 +#define BYTE3_OFST (24) +#define BYTE2_OFST (16) +#define BYTE1_OFST (8) +#define BYTE0_OFST (0) + +//U3D_FIFO15 +#define BYTE3_OFST (24) +#define BYTE2_OFST (16) +#define BYTE1_OFST (8) +#define BYTE0_OFST (0) + +//U3D_QCR0 +#define RXQ_CS_EN_OFST (17) +#define TXQ_CS_EN_OFST (1) +#define CS16B_EN_OFST (0) + +//U3D_QCR1 +#define CFG_TX_ZLP_GPD_OFST (1) + +//U3D_QCR2 +#define CFG_TX_ZLP_OFST (1) + +//U3D_QCR3 +#define CFG_RX_COZ_OFST (17) +#define CFG_RX_ZLP_OFST (1) + +//U3D_QGCSR +#define RXQ_EN_OFST (17) +#define TXQ_EN_OFST (1) + +//U3D_TXQCSR1 +#define TXQ_DMGR_DMSM_CS_OFST (16) +#define TXQ_ACTIVE_OFST (15) +#define TXQ_EPQ_STATE_OFST (8) +#define TXQ_STOP_OFST (2) +#define TXQ_RESUME_OFST (1) +#define TXQ_START_OFST (0) + +//U3D_TXQSAR1 +#define TXQ_START_ADDR_OFST (2) + +//U3D_TXQCPR1 +#define TXQ_CUR_GPD_ADDR_OFST (2) + +//U3D_TXQCSR2 +#define TXQ_DMGR_DMSM_CS_OFST (16) +#define TXQ_ACTIVE_OFST (15) +#define TXQ_EPQ_STATE_OFST (8) +#define TXQ_STOP_OFST (2) +#define TXQ_RESUME_OFST (1) +#define TXQ_START_OFST (0) + +//U3D_TXQSAR2 +#define TXQ_START_ADDR_OFST (2) + +//U3D_TXQCPR2 +#define TXQ_CUR_GPD_ADDR_OFST (2) + +//U3D_TXQCSR3 +#define TXQ_DMGR_DMSM_CS_OFST (16) +#define TXQ_ACTIVE_OFST (15) +#define TXQ_EPQ_STATE_OFST (8) +#define TXQ_STOP_OFST (2) +#define TXQ_RESUME_OFST (1) +#define TXQ_START_OFST (0) + +//U3D_TXQSAR3 +#define TXQ_START_ADDR_OFST (2) + +//U3D_TXQCPR3 +#define TXQ_CUR_GPD_ADDR_OFST (2) + +//U3D_TXQCSR4 +#define TXQ_DMGR_DMSM_CS_OFST (16) +#define TXQ_ACTIVE_OFST (15) +#define TXQ_EPQ_STATE_OFST (8) +#define TXQ_STOP_OFST (2) +#define TXQ_RESUME_OFST (1) +#define TXQ_START_OFST (0) + +//U3D_TXQSAR4 +#define TXQ_START_ADDR_OFST (2) + +//U3D_TXQCPR4 +#define TXQ_CUR_GPD_ADDR_OFST (2) + +//U3D_TXQCSR5 +#define TXQ_DMGR_DMSM_CS_OFST (16) +#define TXQ_ACTIVE_OFST (15) +#define TXQ_EPQ_STATE_OFST (8) +#define TXQ_STOP_OFST (2) +#define TXQ_RESUME_OFST (1) +#define TXQ_START_OFST (0) + +//U3D_TXQSAR5 +#define TXQ_START_ADDR_OFST (2) + +//U3D_TXQCPR5 +#define TXQ_CUR_GPD_ADDR_OFST (2) + +//U3D_TXQCSR6 +#define TXQ_DMGR_DMSM_CS_OFST (16) +#define TXQ_ACTIVE_OFST (15) +#define TXQ_EPQ_STATE_OFST (8) +#define TXQ_STOP_OFST (2) +#define TXQ_RESUME_OFST (1) +#define TXQ_START_OFST (0) + +//U3D_TXQSAR6 +#define TXQ_START_ADDR_OFST (2) + +//U3D_TXQCPR6 +#define TXQ_CUR_GPD_ADDR_OFST (2) + +//U3D_TXQCSR7 +#define TXQ_DMGR_DMSM_CS_OFST (16) +#define TXQ_ACTIVE_OFST (15) +#define TXQ_EPQ_STATE_OFST (8) +#define TXQ_STOP_OFST (2) +#define TXQ_RESUME_OFST (1) +#define TXQ_START_OFST (0) + +//U3D_TXQSAR7 +#define TXQ_START_ADDR_OFST (2) + +//U3D_TXQCPR7 +#define TXQ_CUR_GPD_ADDR_OFST (2) + +//U3D_TXQCSR8 +#define TXQ_DMGR_DMSM_CS_OFST (16) +#define TXQ_ACTIVE_OFST (15) +#define TXQ_EPQ_STATE_OFST (8) +#define TXQ_STOP_OFST (2) +#define TXQ_RESUME_OFST (1) +#define TXQ_START_OFST (0) + +//U3D_TXQSAR8 +#define TXQ_START_ADDR_OFST (2) + +//U3D_TXQCPR8 +#define TXQ_CUR_GPD_ADDR_OFST (2) + +//U3D_TXQCSR9 +#define TXQ_DMGR_DMSM_CS_OFST (16) +#define TXQ_ACTIVE_OFST (15) +#define TXQ_EPQ_STATE_OFST (8) +#define TXQ_STOP_OFST (2) +#define TXQ_RESUME_OFST (1) +#define TXQ_START_OFST (0) + +//U3D_TXQSAR9 +#define TXQ_START_ADDR_OFST (2) + +//U3D_TXQCPR9 +#define TXQ_CUR_GPD_ADDR_OFST (2) + +//U3D_TXQCSR10 +#define TXQ_DMGR_DMSM_CS_OFST (16) +#define TXQ_ACTIVE_OFST (15) +#define TXQ_EPQ_STATE_OFST (8) +#define TXQ_STOP_OFST (2) +#define TXQ_RESUME_OFST (1) +#define TXQ_START_OFST (0) + +//U3D_TXQSAR10 +#define TXQ_START_ADDR_OFST (2) + +//U3D_TXQCPR10 +#define TXQ_CUR_GPD_ADDR_OFST (2) + +//U3D_TXQCSR11 +#define TXQ_DMGR_DMSM_CS_OFST (16) +#define TXQ_ACTIVE_OFST (15) +#define TXQ_EPQ_STATE_OFST (8) +#define TXQ_STOP_OFST (2) +#define TXQ_RESUME_OFST (1) +#define TXQ_START_OFST (0) + +//U3D_TXQSAR11 +#define TXQ_START_ADDR_OFST (2) + +//U3D_TXQCPR11 +#define TXQ_CUR_GPD_ADDR_OFST (2) + +//U3D_TXQCSR12 +#define TXQ_DMGR_DMSM_CS_OFST (16) +#define TXQ_ACTIVE_OFST (15) +#define TXQ_EPQ_STATE_OFST (8) +#define TXQ_STOP_OFST (2) +#define TXQ_RESUME_OFST (1) +#define TXQ_START_OFST (0) + +//U3D_TXQSAR12 +#define TXQ_START_ADDR_OFST (2) + +//U3D_TXQCPR12 +#define TXQ_CUR_GPD_ADDR_OFST (2) + +//U3D_TXQCSR13 +#define TXQ_DMGR_DMSM_CS_OFST (16) +#define TXQ_ACTIVE_OFST (15) +#define TXQ_EPQ_STATE_OFST (8) +#define TXQ_STOP_OFST (2) +#define TXQ_RESUME_OFST (1) +#define TXQ_START_OFST (0) + +//U3D_TXQSAR13 +#define TXQ_START_ADDR_OFST (2) + +//U3D_TXQCPR13 +#define TXQ_CUR_GPD_ADDR_OFST (2) + +//U3D_TXQCSR14 +#define TXQ_DMGR_DMSM_CS_OFST (16) +#define TXQ_ACTIVE_OFST (15) +#define TXQ_EPQ_STATE_OFST (8) +#define TXQ_STOP_OFST (2) +#define TXQ_RESUME_OFST (1) +#define TXQ_START_OFST (0) + +//U3D_TXQSAR14 +#define TXQ_START_ADDR_OFST (2) + +//U3D_TXQCPR14 +#define TXQ_CUR_GPD_ADDR_OFST (2) + +//U3D_TXQCSR15 +#define TXQ_DMGR_DMSM_CS_OFST (16) +#define TXQ_ACTIVE_OFST (15) +#define TXQ_EPQ_STATE_OFST (8) +#define TXQ_STOP_OFST (2) +#define TXQ_RESUME_OFST (1) +#define TXQ_START_OFST (0) + +//U3D_TXQSAR15 +#define TXQ_START_ADDR_OFST (2) + +//U3D_TXQCPR15 +#define TXQ_CUR_GPD_ADDR_OFST (2) + +//U3D_RXQCSR1 +#define RXQ_DMGR_DMSM_CS_OFST (16) +#define RXQ_ACTIVE_OFST (15) +#define RXQ_EPQ_STATE_OFST (8) +#define RXQ_STOP_OFST (2) +#define RXQ_RESUME_OFST (1) +#define RXQ_START_OFST (0) + +//U3D_RXQSAR1 +#define RXQ_START_ADDR_OFST (2) + +//U3D_RXQCPR1 +#define RXQ_CUR_GPD_ADDR_OFST (2) + +//U3D_RXQLDPR1 +#define RXQ_LAST_DONE_PTR_OFST (2) + +//U3D_RXQCSR2 +#define RXQ_DMGR_DMSM_CS_OFST (16) +#define RXQ_ACTIVE_OFST (15) +#define RXQ_EPQ_STATE_OFST (8) +#define RXQ_STOP_OFST (2) +#define RXQ_RESUME_OFST (1) +#define RXQ_START_OFST (0) + +//U3D_RXQSAR2 +#define RXQ_START_ADDR_OFST (2) + +//U3D_RXQCPR2 +#define RXQ_CUR_GPD_ADDR_OFST (2) + +//U3D_RXQLDPR2 +#define RXQ_LAST_DONE_PTR_OFST (2) + +//U3D_RXQCSR3 +#define RXQ_DMGR_DMSM_CS_OFST (16) +#define RXQ_ACTIVE_OFST (15) +#define RXQ_EPQ_STATE_OFST (8) +#define RXQ_STOP_OFST (2) +#define RXQ_RESUME_OFST (1) +#define RXQ_START_OFST (0) + +//U3D_RXQSAR3 +#define RXQ_START_ADDR_OFST (2) + +//U3D_RXQCPR3 +#define RXQ_CUR_GPD_ADDR_OFST (2) + +//U3D_RXQLDPR3 +#define RXQ_LAST_DONE_PTR_OFST (2) + +//U3D_RXQCSR4 +#define RXQ_DMGR_DMSM_CS_OFST (16) +#define RXQ_ACTIVE_OFST (15) +#define RXQ_EPQ_STATE_OFST (8) +#define RXQ_STOP_OFST (2) +#define RXQ_RESUME_OFST (1) +#define RXQ_START_OFST (0) + +//U3D_RXQSAR4 +#define RXQ_START_ADDR_OFST (2) + +//U3D_RXQCPR4 +#define RXQ_CUR_GPD_ADDR_OFST (2) + +//U3D_RXQLDPR4 +#define RXQ_LAST_DONE_PTR_OFST (2) + +//U3D_RXQCSR5 +#define RXQ_DMGR_DMSM_CS_OFST (16) +#define RXQ_ACTIVE_OFST (15) +#define RXQ_EPQ_STATE_OFST (8) +#define RXQ_STOP_OFST (2) +#define RXQ_RESUME_OFST (1) +#define RXQ_START_OFST (0) + +//U3D_RXQSAR5 +#define RXQ_START_ADDR_OFST (2) + +//U3D_RXQCPR5 +#define RXQ_CUR_GPD_ADDR_OFST (2) + +//U3D_RXQLDPR5 +#define RXQ_LAST_DONE_PTR_OFST (2) + +//U3D_RXQCSR6 +#define RXQ_DMGR_DMSM_CS_OFST (16) +#define RXQ_ACTIVE_OFST (15) +#define RXQ_EPQ_STATE_OFST (8) +#define RXQ_STOP_OFST (2) +#define RXQ_RESUME_OFST (1) +#define RXQ_START_OFST (0) + +//U3D_RXQSAR6 +#define RXQ_START_ADDR_OFST (2) + +//U3D_RXQCPR6 +#define RXQ_CUR_GPD_ADDR_OFST (2) + +//U3D_RXQLDPR6 +#define RXQ_LAST_DONE_PTR_OFST (2) + +//U3D_RXQCSR7 +#define RXQ_DMGR_DMSM_CS_OFST (16) +#define RXQ_ACTIVE_OFST (15) +#define RXQ_EPQ_STATE_OFST (8) +#define RXQ_STOP_OFST (2) +#define RXQ_RESUME_OFST (1) +#define RXQ_START_OFST (0) + +//U3D_RXQSAR7 +#define RXQ_START_ADDR_OFST (2) + +//U3D_RXQCPR7 +#define RXQ_CUR_GPD_ADDR_OFST (2) + +//U3D_RXQLDPR7 +#define RXQ_LAST_DONE_PTR_OFST (2) + +//U3D_RXQCSR8 +#define RXQ_DMGR_DMSM_CS_OFST (16) +#define RXQ_ACTIVE_OFST (15) +#define RXQ_EPQ_STATE_OFST (8) +#define RXQ_STOP_OFST (2) +#define RXQ_RESUME_OFST (1) +#define RXQ_START_OFST (0) + +//U3D_RXQSAR8 +#define RXQ_START_ADDR_OFST (2) + +//U3D_RXQCPR8 +#define RXQ_CUR_GPD_ADDR_OFST (2) + +//U3D_RXQLDPR8 +#define RXQ_LAST_DONE_PTR_OFST (2) + +//U3D_RXQCSR9 +#define RXQ_DMGR_DMSM_CS_OFST (16) +#define RXQ_ACTIVE_OFST (15) +#define RXQ_EPQ_STATE_OFST (8) +#define RXQ_STOP_OFST (2) +#define RXQ_RESUME_OFST (1) +#define RXQ_START_OFST (0) + +//U3D_RXQSAR9 +#define RXQ_START_ADDR_OFST (2) + +//U3D_RXQCPR9 +#define RXQ_CUR_GPD_ADDR_OFST (2) + +//U3D_RXQLDPR9 +#define RXQ_LAST_DONE_PTR_OFST (2) + +//U3D_RXQCSR10 +#define RXQ_DMGR_DMSM_CS_OFST (16) +#define RXQ_ACTIVE_OFST (15) +#define RXQ_EPQ_STATE_OFST (8) +#define RXQ_STOP_OFST (2) +#define RXQ_RESUME_OFST (1) +#define RXQ_START_OFST (0) + +//U3D_RXQSAR10 +#define RXQ_START_ADDR_OFST (2) + +//U3D_RXQCPR10 +#define RXQ_CUR_GPD_ADDR_OFST (2) + +//U3D_RXQLDPR10 +#define RXQ_LAST_DONE_PTR_OFST (2) + +//U3D_RXQCSR11 +#define RXQ_DMGR_DMSM_CS_OFST (16) +#define RXQ_ACTIVE_OFST (15) +#define RXQ_EPQ_STATE_OFST (8) +#define RXQ_STOP_OFST (2) +#define RXQ_RESUME_OFST (1) +#define RXQ_START_OFST (0) + +//U3D_RXQSAR11 +#define RXQ_START_ADDR_OFST (2) + +//U3D_RXQCPR11 +#define RXQ_CUR_GPD_ADDR_OFST (2) + +//U3D_RXQLDPR11 +#define RXQ_LAST_DONE_PTR_OFST (2) + +//U3D_RXQCSR12 +#define RXQ_DMGR_DMSM_CS_OFST (16) +#define RXQ_ACTIVE_OFST (15) +#define RXQ_EPQ_STATE_OFST (8) +#define RXQ_STOP_OFST (2) +#define RXQ_RESUME_OFST (1) +#define RXQ_START_OFST (0) + +//U3D_RXQSAR12 +#define RXQ_START_ADDR_OFST (2) + +//U3D_RXQCPR12 +#define RXQ_CUR_GPD_ADDR_OFST (2) + +//U3D_RXQLDPR12 +#define RXQ_LAST_DONE_PTR_OFST (2) + +//U3D_RXQCSR13 +#define RXQ_DMGR_DMSM_CS_OFST (16) +#define RXQ_ACTIVE_OFST (15) +#define RXQ_EPQ_STATE_OFST (8) +#define RXQ_STOP_OFST (2) +#define RXQ_RESUME_OFST (1) +#define RXQ_START_OFST (0) + +//U3D_RXQSAR13 +#define RXQ_START_ADDR_OFST (2) + +//U3D_RXQCPR13 +#define RXQ_CUR_GPD_ADDR_OFST (2) + +//U3D_RXQLDPR13 +#define RXQ_LAST_DONE_PTR_OFST (2) + +//U3D_RXQCSR14 +#define RXQ_DMGR_DMSM_CS_OFST (16) +#define RXQ_ACTIVE_OFST (15) +#define RXQ_EPQ_STATE_OFST (8) +#define RXQ_STOP_OFST (2) +#define RXQ_RESUME_OFST (1) +#define RXQ_START_OFST (0) + +//U3D_RXQSAR14 +#define RXQ_START_ADDR_OFST (2) + +//U3D_RXQCPR14 +#define RXQ_CUR_GPD_ADDR_OFST (2) + +//U3D_RXQLDPR14 +#define RXQ_LAST_DONE_PTR_OFST (2) + +//U3D_RXQCSR15 +#define RXQ_DMGR_DMSM_CS_OFST (16) +#define RXQ_ACTIVE_OFST (15) +#define RXQ_EPQ_STATE_OFST (8) +#define RXQ_STOP_OFST (2) +#define RXQ_RESUME_OFST (1) +#define RXQ_START_OFST (0) + +//U3D_RXQSAR15 +#define RXQ_START_ADDR_OFST (2) + +//U3D_RXQCPR15 +#define RXQ_CUR_GPD_ADDR_OFST (2) + +//U3D_RXQLDPR15 +#define RXQ_LAST_DONE_PTR_OFST (2) + +//U3D_QISAR0 +#define RXQ_DONE_INT_OFST (17) +#define TXQ_DONE_INT_OFST (1) + +//U3D_QIER0 +#define RXQ_DONE_IER_OFST (17) +#define TXQ_DONE_IER_OFST (1) + +//U3D_QIESR0 +#define RXQ_DONE_IESR_OFST (17) +#define TXQ_DONE_IESR_OFST (1) + +//U3D_QIECR0 +#define RXQ_DONE_IECR_OFST (17) +#define TXQ_DONE_IECR_OFST (1) + +//U3D_QISAR1 +#define RXQ_ZLPERR_INT_OFST (20) +#define RXQ_LENERR_INT_OFST (18) +#define RXQ_CSERR_INT_OFST (17) +#define RXQ_EMPTY_INT_OFST (16) +#define TXQ_LENERR_INT_OFST (2) +#define TXQ_CSERR_INT_OFST (1) +#define TXQ_EMPTY_INT_OFST (0) + +//U3D_QIER1 +#define RXQ_ZLPERR_IER_OFST (20) +#define RXQ_LENERR_IER_OFST (18) +#define RXQ_CSERR_IER_OFST (17) +#define RXQ_EMPTY_IER_OFST (16) +#define TXQ_LENERR_IER_OFST (2) +#define TXQ_CSERR_IER_OFST (1) +#define TXQ_EMPTY_IER_OFST (0) + +//U3D_QIESR1 +#define RXQ_ZLPERR_IESR_OFST (20) +#define RXQ_LENERR_IESR_OFST (18) +#define RXQ_CSERR_IESR_OFST (17) +#define RXQ_EMPTY_IESR_OFST (16) +#define TXQ_LENERR_IESR_OFST (2) +#define TXQ_CSERR_IESR_OFST (1) +#define TXQ_EMPTY_IESR_OFST (0) + +//U3D_QIECR1 +#define RXQ_ZLPERR_IECR_OFST (20) +#define RXQ_LENERR_IECR_OFST (18) +#define RXQ_CSERR_IECR_OFST (17) +#define RXQ_EMPTY_IECR_OFST (16) +#define TXQ_LENERR_IECR_OFST (2) +#define TXQ_CSERR_IECR_OFST (1) +#define TXQ_EMPTY_IECR_OFST (0) + +//U3D_QEMIR +#define RXQ_EMPTY_MASK_OFST (17) +#define TXQ_EMPTY_MASK_OFST (1) + +//U3D_QEMIER +#define RXQ_EMPTY_IER_MASK_OFST (17) +#define TXQ_EMPTY_IER_MASK_OFST (1) + +//U3D_QEMIESR +#define RXQ_EMPTY_IESR_MASK_OFST (17) +#define TXQ_EMPTY_IESR_MASK_OFST (1) + +//U3D_QEMIECR +#define RXQ_EMPTY_IECR_MASK_OFST (17) +#define TXQ_EMPTY_IECR_MASK_OFST (1) + +//U3D_TQERRIR0 +#define TXQ_LENERR_MASK_OFST (17) +#define TXQ_CSERR_MASK_OFST (1) + +//U3D_TQERRIER0 +#define TXQ_LENERR_IER_MASK_OFST (17) +#define TXQ_CSERR_IER_MASK_OFST (1) + +//U3D_TQERRIESR0 +#define TXQ_LENERR_IESR_MASK_OFST (17) +#define TXQ_CSERR_IESR_MASK_OFST (1) + +//U3D_TQERRIECR0 +#define TXQ_LENERR_IECR_MASK_OFST (17) +#define TXQ_CSERR_IECR_MASK_OFST (1) + +//U3D_RQERRIR0 +#define RXQ_LENERR_MASK_OFST (17) +#define RXQ_CSERR_MASK_OFST (1) + +//U3D_RQERRIER0 +#define RXQ_LENERR_IER_MASK_OFST (17) +#define RXQ_CSERR_IER_MASK_OFST (1) + +//U3D_RQERRIESR0 +#define RXQ_LENERR_IESR_MASK_OFST (17) +#define RXQ_CSERR_IESR_MASK_OFST (1) + +//U3D_RQERRIECR0 +#define RXQ_LENERR_IECR_MASK_OFST (17) +#define RXQ_CSERR_IECR_MASK_OFST (1) + +//U3D_RQERRIR1 +#define RXQ_ZLPERR_MASK_OFST (17) + +//U3D_RQERRIER1 +#define RXQ_ZLPERR_IER_MASK_OFST (17) + +//U3D_RQERRIESR1 +#define RXQ_ZLPERR_IESR_MASK_OFST (17) + +//U3D_RQERRIECR1 +#define RXQ_ZLPERR_IECR_MASK_OFST (17) + +//U3D_CAP_EP0FFSZ +#define CAP_EP0FFSZ_OFST (0) + +//U3D_CAP_EPNTXFFSZ +#define CAP_EPNTXFFSZ_OFST (0) + +//U3D_CAP_EPNRXFFSZ +#define CAP_EPNRXFFSZ_OFST (0) + +//U3D_CAP_EPINFO +#define CAP_RX_EP_NUM_OFST (8) +#define CAP_TX_EP_NUM_OFST (0) + +//U3D_CAP_TX_SLOT1 +#define CAP_TX_SLOT3_OFST (24) +#define CAP_TX_SLOT2_OFST (16) +#define CAP_TX_SLOT1_OFST (8) +#define RSV_OFST (0) + +//U3D_CAP_TX_SLOT2 +#define CAP_TX_SLOT7_OFST (24) +#define CAP_TX_SLOT6_OFST (16) +#define CAP_TX_SLOT5_OFST (8) +#define CAP_TX_SLOT4_OFST (0) + +//U3D_CAP_TX_SLOT3 +#define CAP_TX_SLOT11_OFST (24) +#define CAP_TX_SLOT10_OFST (16) +#define CAP_TX_SLOT9_OFST (8) +#define CAP_TX_SLOT8_OFST (0) + +//U3D_CAP_TX_SLOT4 +#define CAP_TX_SLOT15_OFST (24) +#define CAP_TX_SLOT14_OFST (16) +#define CAP_TX_SLOT13_OFST (8) +#define CAP_TX_SLOT12_OFST (0) + +//U3D_CAP_RX_SLOT1 +#define CAP_RX_SLOT3_OFST (24) +#define CAP_RX_SLOT2_OFST (16) +#define CAP_RX_SLOT1_OFST (8) +#define RSV_OFST (0) + +//U3D_CAP_RX_SLOT2 +#define CAP_RX_SLOT7_OFST (24) +#define CAP_RX_SLOT6_OFST (16) +#define CAP_RX_SLOT5_OFST (8) +#define CAP_RX_SLOT4_OFST (0) + +//U3D_CAP_RX_SLOT3 +#define CAP_RX_SLOT11_OFST (24) +#define CAP_RX_SLOT10_OFST (16) +#define CAP_RX_SLOT9_OFST (8) +#define CAP_RX_SLOT8_OFST (0) + +//U3D_CAP_RX_SLOT4 +#define CAP_RX_SLOT15_OFST (24) +#define CAP_RX_SLOT14_OFST (16) +#define CAP_RX_SLOT13_OFST (8) +#define CAP_RX_SLOT12_OFST (0) + +//U3D_MISC_CTRL +#define DMA_BUS_CK_GATE_DIS_OFST (2) +#define VBUS_ON_OFST (1) +#define VBUS_FRC_EN_OFST (0) + +////////////////////////////////////////////////////////////////////// diff --git a/include/linux/mu3d/hal/ssusb_epctl_csr_c_header.h b/include/linux/mu3d/hal/ssusb_epctl_csr_c_header.h new file mode 100644 index 000000000..c5741c24e --- /dev/null +++ b/include/linux/mu3d/hal/ssusb_epctl_csr_c_header.h @@ -0,0 +1,187 @@ +/* SSUSB_EPCTL_CSR REGISTER DEFINITION */ + +#define U3D_DEVICE_CONF (SSUSB_EPCTL_CSR_BASE+0x0000) +#define U3D_EP_RST (SSUSB_EPCTL_CSR_BASE+0x0004) +#define U3D_USB3_ERDY_TIMING_PARAMETER (SSUSB_EPCTL_CSR_BASE+0x0008) +#define U3D_USB3_EPCTRL_CAP (SSUSB_EPCTL_CSR_BASE+0x000C) +#define U3D_USB2_ISOINEP_INCOMP_INTR (SSUSB_EPCTL_CSR_BASE+0x0010) +#define U3D_USB2_ISOOUTEP_INCOMP_ERR (SSUSB_EPCTL_CSR_BASE+0x0014) +#define U3D_ISO_UNDERRUN_INTR (SSUSB_EPCTL_CSR_BASE+0x0018) +#define U3D_ISO_OVERRUN_INTR (SSUSB_EPCTL_CSR_BASE+0x001C) +#define U3D_USB2_RX_EP_DATAERR_INTR (SSUSB_EPCTL_CSR_BASE+0x0020) +#define U3D_USB2_EPCTRL_CAP (SSUSB_EPCTL_CSR_BASE+0x0024) +#define U3D_USB2_EPCTL_LPM (SSUSB_EPCTL_CSR_BASE+0x0028) +#define U3D_USB3_SW_ERDY (SSUSB_EPCTL_CSR_BASE+0x0030) +#define U3D_EP_FLOW_CTRL (SSUSB_EPCTL_CSR_BASE+0x0040) +#define U3D_USB3_EP_ACT (SSUSB_EPCTL_CSR_BASE+0x0044) +#define U3D_USB3_EP_PACKET_PENDING (SSUSB_EPCTL_CSR_BASE+0x0048) +#define U3D_DEV_LINK_INTR_ENABLE (SSUSB_EPCTL_CSR_BASE+0x0050) +#define U3D_DEV_LINK_INTR (SSUSB_EPCTL_CSR_BASE+0x0054) +#define U3D_USB2_EPCTL_LPM_FC_CHK (SSUSB_EPCTL_CSR_BASE+0x0060) +#define U3D_DEVICE_MONITOR (SSUSB_EPCTL_CSR_BASE+0x0064) + +/* SSUSB_EPCTL_CSR FIELD DEFINITION */ + +//U3D_DEVICE_CONF +#define DEV_ADDR (0x7f<<24) //30:24 +#define HW_USB2_3_SEL (0x1<<18) //18:18 +#define SW_USB2_3_SEL_EN (0x1<<17) //17:17 +#define SW_USB2_3_SEL (0x1<<16) //16:16 +#define SSUSB_DEV_SPEED (0x7<<0) //2:0 + +//U3D_EP_RST +#define EP_IN_RST (0x7fff<<17) //31:17 +#define EP_OUT_RST (0x7fff<<1) //15:1 +#define EP0_RST (0x1<<0) //0:0 + +//U3D_USB3_ERDY_TIMING_PARAMETER +#define ERDY_TIMEOUT_VALUE (0x3ff<<0) //9:0 + +//U3D_USB3_EPCTRL_CAP +#define TX_NUMP_0_EN (0x1<<4) //4:4 +#define SEND_STALL_CLR_PP_EN (0x1<<3) //3:3 +#define USB3_ISO_CRC_CHK_DIS (0x1<<2) //2:2 +#define SET_EOB_EN (0x1<<1) //1:1 +#define TX_BURST_EN (0x1<<0) //0:0 + +//U3D_USB2_ISOINEP_INCOMP_INTR +#define USB2_ISOINEP_INCOMP_INTR_EN (0x7fff<<17) //31:17 +#define USB2_ISOINEP_INCOMP_INTR (0x7fff<<1) //15:1 + +//U3D_USB2_ISOOUTEP_INCOMP_ERR +#define USB2_ISOOUTEP_INCOMP_INTR_EN (0x7fff<<17) //31:17 +#define USB2_ISOOUTEP_INCOMP_INTR (0x7fff<<1) //15:1 + +//U3D_ISO_UNDERRUN_INTR +#define ISOIN_UNDERRUN_INTR_EN (0x7fff<<17) //31:17 +#define ISOIN_UNDERRUN_INTR (0x7fff<<1) //15:1 + +//U3D_ISO_OVERRUN_INTR +#define ISOOUT_OVERRUN_INTR_EN (0x7fff<<17) //31:17 +#define ISOOUT_OVERRUN_INTR (0x7fff<<1) //15:1 + +//U3D_USB2_RX_EP_DATAERR_INTR +#define USB2_RX_EP_DATAERR_INTR_EN (0xffff<<16) //31:16 +#define USB2_RX_EP_DATAERR_INTR (0xffff<<0) //15:0 + +//U3D_USB2_EPCTRL_CAP +#define USB2_ISO_CRC_CHK_DIS (0x1<<0) //0:0 + +//U3D_USB2_EPCTL_LPM +#define L1_EXIT_EP_OUT_CHK (0x7fff<<17) //31:17 +#define L1_EXIT_EP_IN_CHK (0x7fff<<1) //15:1 +#define L1_EXIT_EP0_CHK (0x1<<0) //0:0 + +//U3D_USB3_SW_ERDY +#define SW_ERDY_EP_NUM (0xf<<2) //5:2 +#define SW_ERDY_EP_DIR (0x1<<1) //1:1 +#define SW_SEND_ERDY (0x1<<0) //0:0 + +//U3D_EP_FLOW_CTRL +#define EP_OUT_FC (0xffff<<16) //31:16 +#define EP_IN_FC (0xffff<<0) //15:0 + +//U3D_USB3_EP_ACT +#define EP_IN_ACT (0xffff<<0) //15:0 + +//U3D_USB3_EP_PACKET_PENDING +#define EP_OUT_PP (0xffff<<16) //31:16 +#define EP_IN_PP (0xffff<<0) //15:0 + +//U3D_DEV_LINK_INTR_ENABLE +#define SSUSB_DEV_SPEED_CHG_INTR_EN (0x1<<0) //0:0 + +//U3D_DEV_LINK_INTR +#define SSUSB_DEV_SPEED_CHG_INTR (0x1<<0) //0:0 + +//U3D_USB2_EPCTL_LPM_FC_CHK +#define L1_EXIT_EP_OUT_FC_CHK (0x7fff<<17) //31:17 +#define L1_EXIT_EP_IN_FC_CHK (0x7fff<<1) //15:1 +#define L1_EXIT_EP0_FC_CHK (0x1<<0) //0:0 + +//U3D_DEVICE_MONITOR +#define CUR_DEV_ADDR (0x7f<<0) //6:0 + + +/* SSUSB_EPCTL_CSR FIELD OFFSET DEFINITION */ + +//U3D_DEVICE_CONF +#define DEV_ADDR_OFST (24) +#define HW_USB2_3_SEL_OFST (18) +#define SW_USB2_3_SEL_EN_OFST (17) +#define SW_USB2_3_SEL_OFST (16) +#define SSUSB_DEV_SPEED_OFST (0) + +//U3D_EP_RST +#define EP_IN_RST_OFST (17) +#define EP_OUT_RST_OFST (1) +#define EP0_RST_OFST (0) + +//U3D_USB3_ERDY_TIMING_PARAMETER +#define ERDY_TIMEOUT_VALUE_OFST (0) + +//U3D_USB3_EPCTRL_CAP +#define SEND_STALL_CLR_PP_EN_OFST (3) +#define USB3_ISO_CRC_CHK_DIS_OFST (2) +#define SET_EOB_EN_OFST (1) +#define TX_BURST_EN_OFST (0) + +//U3D_USB2_ISOINEP_INCOMP_INTR +#define USB2_ISOINEP_INCOMP_INTR_EN_OFST (17) +#define USB2_ISOINEP_INCOMP_INTR_OFST (1) + +//U3D_USB2_ISOOUTEP_INCOMP_ERR +#define USB2_ISOOUTEP_INCOMP_INTR_EN_OFST (17) +#define USB2_ISOOUTEP_INCOMP_INTR_OFST (1) + +//U3D_ISO_UNDERRUN_INTR +#define ISOIN_UNDERRUN_INTR_EN_OFST (17) +#define ISOIN_UNDERRUN_INTR_OFST (1) + +//U3D_ISO_OVERRUN_INTR +#define ISOOUT_OVERRUN_INTR_EN_OFST (17) +#define ISOOUT_OVERRUN_INTR_OFST (1) + +//U3D_USB2_RX_EP_DATAERR_INTR +#define USB2_RX_EP_DATAERR_INTR_EN_OFST (16) +#define USB2_RX_EP_DATAERR_INTR_OFST (0) + +//U3D_USB2_EPCTRL_CAP +#define USB2_ISO_CRC_CHK_DIS_OFST (0) + +//U3D_USB2_EPCTL_LPM +#define L1_EXIT_EP_OUT_CHK_OFST (17) +#define L1_EXIT_EP_IN_CHK_OFST (1) +#define L1_EXIT_EP0_CHK_OFST (0) + +//U3D_USB3_SW_ERDY +#define SW_ERDY_EP_NUM_OFST (2) +#define SW_ERDY_EP_DIR_OFST (1) +#define SW_SEND_ERDY_OFST (0) + +//U3D_EP_FLOW_CTRL +#define EP_OUT_FC_OFST (16) +#define EP_IN_FC_OFST (0) + +//U3D_USB3_EP_ACT +#define EP_IN_ACT_OFST (0) + +//U3D_USB3_EP_PACKET_PENDING +#define EP_OUT_PP_OFST (16) +#define EP_IN_PP_OFST (0) + +//U3D_DEV_LINK_INTR_ENABLE +#define SSUSB_DEV_SPEED_CHG_INTR_EN_OFST (0) + +//U3D_DEV_LINK_INTR +#define SSUSB_DEV_SPEED_CHG_INTR_OFST (0) + +//U3D_USB2_EPCTL_LPM_FC_CHK +#define L1_EXIT_EP_OUT_FC_CHK_OFST (17) +#define L1_EXIT_EP_IN_FC_CHK_OFST (1) +#define L1_EXIT_EP0_FC_CHK_OFST (0) + +//U3D_DEVICE_MONITOR +#define CUR_DEV_ADDR_OFST (0) + +////////////////////////////////////////////////////////////////////// diff --git a/include/linux/mu3d/hal/ssusb_sifslv_ippc_c_header.h b/include/linux/mu3d/hal/ssusb_sifslv_ippc_c_header.h new file mode 100644 index 000000000..cf1438f59 --- /dev/null +++ b/include/linux/mu3d/hal/ssusb_sifslv_ippc_c_header.h @@ -0,0 +1,728 @@ +/* SSUSB_SIFSLV_IPPC REGISTER DEFINITION */ + +#define U3D_SSUSB_IP_PW_CTRL0 (SSUSB_SIFSLV_IPPC_BASE+0x0000) +#define U3D_SSUSB_IP_PW_CTRL1 (SSUSB_SIFSLV_IPPC_BASE+0x0004) +#define U3D_SSUSB_IP_PW_CTRL2 (SSUSB_SIFSLV_IPPC_BASE+0x0008) +#define U3D_SSUSB_IP_PW_CTRL3 (SSUSB_SIFSLV_IPPC_BASE+0x000C) +#define U3D_SSUSB_IP_PW_STS1 (SSUSB_SIFSLV_IPPC_BASE+0x0010) +#define U3D_SSUSB_IP_PW_STS2 (SSUSB_SIFSLV_IPPC_BASE+0x0014) +#define U3D_SSUSB_OTG_STS (SSUSB_SIFSLV_IPPC_BASE+0x0018) +#define U3D_SSUSB_OTG_STS_CLR (SSUSB_SIFSLV_IPPC_BASE+0x001C) +#define U3D_SSUSB_IP_MAC_CAP (SSUSB_SIFSLV_IPPC_BASE+0x0020) +#define U3D_SSUSB_IP_XHCI_CAP (SSUSB_SIFSLV_IPPC_BASE+0x0024) +#define U3D_SSUSB_IP_DEV_CAP (SSUSB_SIFSLV_IPPC_BASE+0x0028) +#define U3D_SSUSB_OTG_INT_EN (SSUSB_SIFSLV_IPPC_BASE+0x002C) + +#if (defined(SUPPORT_U3) || defined(CONFIG_MTK_FPGA)) +#define U3D_SSUSB_U3_CTRL_0P (SSUSB_SIFSLV_IPPC_BASE+0x0030) +#define U3D_SSUSB_U3_CTRL_1P (SSUSB_SIFSLV_IPPC_BASE+0x0038) +#define U3D_SSUSB_U3_CTRL_2P (SSUSB_SIFSLV_IPPC_BASE+0x0040) +#define U3D_SSUSB_U3_CTRL_3P (SSUSB_SIFSLV_IPPC_BASE+0x0048) +#endif +#define U3D_SSUSB_U2_CTRL_0P (SSUSB_SIFSLV_IPPC_BASE+0x0050) +#ifdef SUPPORT_U3 +#define U3D_SSUSB_U2_CTRL_1P (SSUSB_SIFSLV_IPPC_BASE+0x0058) +#define U3D_SSUSB_U2_CTRL_2P (SSUSB_SIFSLV_IPPC_BASE+0x0060) +#define U3D_SSUSB_U2_CTRL_3P (SSUSB_SIFSLV_IPPC_BASE+0x0068) +#define U3D_SSUSB_U2_CTRL_4P (SSUSB_SIFSLV_IPPC_BASE+0x0070) +#define U3D_SSUSB_U2_CTRL_5P (SSUSB_SIFSLV_IPPC_BASE+0x0078) +#endif +#define U3D_SSUSB_U2_PHY_PLL (SSUSB_SIFSLV_IPPC_BASE+0x007C) +#define U3D_SSUSB_DMA_CTRL (SSUSB_SIFSLV_IPPC_BASE+0x0080) +#define U3D_SSUSB_MAC_CK_CTRL (SSUSB_SIFSLV_IPPC_BASE+0x0084) +#define U3D_SSUSB_CSR_CK_CTRL (SSUSB_SIFSLV_IPPC_BASE+0x0088) +#define U3D_SSUSB_REF_CK_CTRL (SSUSB_SIFSLV_IPPC_BASE+0x008C) +#define U3D_SSUSB_XHCI_CK_CTRL (SSUSB_SIFSLV_IPPC_BASE+0x0090) +#define U3D_SSUSB_XHCI_RST_CTRL (SSUSB_SIFSLV_IPPC_BASE+0x0094) +#define U3D_SSUSB_DEV_RST_CTRL (SSUSB_SIFSLV_IPPC_BASE+0x0098) +#define U3D_SSUSB_SYS_CK_CTRL (SSUSB_SIFSLV_IPPC_BASE+0x009C) +#define U3D_SSUSB_HW_ID (SSUSB_SIFSLV_IPPC_BASE+0x00A0) +#define U3D_SSUSB_HW_SUB_ID (SSUSB_SIFSLV_IPPC_BASE+0x00A4) +#define U3D_SSUSB_PRB_CTRL0 (SSUSB_SIFSLV_IPPC_BASE+0x00B0) +#define U3D_SSUSB_PRB_CTRL1 (SSUSB_SIFSLV_IPPC_BASE+0x00B4) +#define U3D_SSUSB_PRB_CTRL2 (SSUSB_SIFSLV_IPPC_BASE+0x00B8) +#define U3D_SSUSB_PRB_CTRL3 (SSUSB_SIFSLV_IPPC_BASE+0x00BC) +#define U3D_SSUSB_PRB_CTRL4 (SSUSB_SIFSLV_IPPC_BASE+0x00C0) +#define U3D_SSUSB_PRB_CTRL5 (SSUSB_SIFSLV_IPPC_BASE+0x00C4) +#define U3D_SSUSB_IP_SPARE0 (SSUSB_SIFSLV_IPPC_BASE+0x00C8) +#define U3D_SSUSB_IP_SPARE1 (SSUSB_SIFSLV_IPPC_BASE+0x00CC) +#define U3D_SSUSB_FPGA_I2C_OUT_0P (SSUSB_SIFSLV_IPPC_BASE+0x00D0) +#define U3D_SSUSB_FPGA_I2C_IN_0P (SSUSB_SIFSLV_IPPC_BASE+0x00D4) +#define U3D_SSUSB_FPGA_I2C_OUT_1P (SSUSB_SIFSLV_IPPC_BASE+0x00D8) +#define U3D_SSUSB_FPGA_I2C_IN_1P (SSUSB_SIFSLV_IPPC_BASE+0x00DC) +#define U3D_SSUSB_FPGA_I2C_OUT_2P (SSUSB_SIFSLV_IPPC_BASE+0x00E0) +#define U3D_SSUSB_FPGA_I2C_IN_2P (SSUSB_SIFSLV_IPPC_BASE+0x00E4) +#define U3D_SSUSB_FPGA_I2C_OUT_3P (SSUSB_SIFSLV_IPPC_BASE+0x00E8) +#define U3D_SSUSB_FPGA_I2C_IN_3P (SSUSB_SIFSLV_IPPC_BASE+0x00EC) +#define U3D_SSUSB_FPGA_I2C_OUT_4P (SSUSB_SIFSLV_IPPC_BASE+0x00F0) +#define U3D_SSUSB_FPGA_I2C_IN_4P (SSUSB_SIFSLV_IPPC_BASE+0x00F4) +#define U3D_SSUSB_IP_SLV_TMOUT (SSUSB_SIFSLV_IPPC_BASE+0x00F8) + +/* SSUSB_SIFSLV_IPPC FIELD DEFINITION */ + +//U3D_SSUSB_IP_PW_CTRL0 +#define SSUSB_AHB_SLV_AUTO_RSP (0x1<<17) //17:17 +#define SSUSB_IP_SW_RST_CK_GATE_EN (0x1<<16) //16:16 +#define SSUSB_IP_U2_ENTER_SLEEP_CNT (0xff<<8) //15:8 +#define SSUSB_IP_SW_RST (0x1<<0) //0:0 + +//U3D_SSUSB_IP_PW_CTRL1 +#define SSUSB_IP_HOST_PDN (0x1<<0) //0:0 + +//U3D_SSUSB_IP_PW_CTRL2 +#define SSUSB_IP_DEV_PDN (0x1<<0) //0:0 + +//U3D_SSUSB_IP_PW_CTRL3 +#define SSUSB_IP_PCIE_PDN (0x1<<0) //0:0 + +//U3D_SSUSB_IP_PW_STS1 +#define SSUSB_IP_REF_CK_DIS_STS (0x1<<31) //31:31 +#define SSUSB_IP_SLEEP_STS (0x1<<30) //30:30 +#define SSUSB_U2_MAC_RST_B_STS_5P (0x1<<29) //29:29 +#define SSUSB_U2_MAC_RST_B_STS_4P (0x1<<28) //28:28 +#define SSUSB_U2_MAC_RST_B_STS_3P (0x1<<27) //27:27 +#define SSUSB_U2_MAC_RST_B_STS_2P (0x1<<26) //26:26 +#define SSUSB_U2_MAC_RST_B_STS_1P (0x1<<25) //25:25 +#define SSUSB_U2_MAC_RST_B_STS (0x1<<24) //24:24 +#define SSUSB_U3_MAC_RST_B_STS_3P (0x1<<19) //19:19 +#define SSUSB_U3_MAC_RST_B_STS_2P (0x1<<18) //18:18 +#define SSUSB_U3_MAC_RST_B_STS_1P (0x1<<17) //17:17 +#define SSUSB_U3_MAC_RST_B_STS (0x1<<16) //16:16 +#define SSUSB_DEV_DRAM_RST_B_STS (0x1<<13) //13:13 +#define SSUSB_XHCI_DRAM_RST_B_STS (0x1<<12) //12:12 +#define SSUSB_XHCI_RST_B_STS (0x1<<11) //11:11 +#define SSUSB_SYS125_RST_B_STS (0x1<<10) //10:10 +#define SSUSB_SYS60_RST_B_STS (0x1<<9) //9:9 +#define SSUSB_REF_RST_B_STS (0x1<<8) //8:8 +#define SSUSB_DEV_RST_B_STS (0x1<<3) //3:3 +#define SSUSB_DEV_BMU_RST_B_STS (0x1<<2) //2:2 +#define SSUSB_DEV_QMU_RST_B_STS (0x1<<1) //1:1 +#define SSUSB_SYSPLL_STABLE (0x1<<0) //0:0 + +//U3D_SSUSB_IP_PW_STS2 +#define SSUSB_U2_MAC_SYS_RST_B_STS_5P (0x1<<5) //5:5 +#define SSUSB_U2_MAC_SYS_RST_B_STS_4P (0x1<<4) //4:4 +#define SSUSB_U2_MAC_SYS_RST_B_STS_3P (0x1<<3) //3:3 +#define SSUSB_U2_MAC_SYS_RST_B_STS_2P (0x1<<2) //2:2 +#define SSUSB_U2_MAC_SYS_RST_B_STS_1P (0x1<<1) //1:1 +#define SSUSB_U2_MAC_SYS_RST_B_STS (0x1<<0) //0:0 + +//U3D_SSUSB_OTG_STS +#define SSUSB_XHCI_MAS_DMA_REQ (0x1<<14) //14:14 +#define SSUSB_DEV_DMA_REQ (0x1<<13) //13:13 +#define SSUSB_AVALID_STS (0x1<<12) //12:12 +#define SSUSB_SRP_REQ_INTR (0x1<<11) //11:11 +#define SSUSB_IDDIG (0x1<<10) //10:10 +#define SSUSB_VBUS_VALID (0x1<<9) //9:9 +#define SSUSB_HOST_DEV_MODE (0x1<<8) //8:8 +#define SSUSB_DEV_USBRST_INTR (0x1<<7) //7:7 +#define VBUS_CHG_INTR (0x1<<6) //6:6 +#define SSUSB_CHG_B_ROLE_B (0x1<<5) //5:5 +#define SSUSB_CHG_A_ROLE_B (0x1<<4) //4:4 +#define SSUSB_ATTACH_B_ROLE (0x1<<3) //3:3 +#define SSUSB_CHG_B_ROLE_A (0x1<<2) //2:2 +#define SSUSB_CHG_A_ROLE_A (0x1<<1) //1:1 +#define SSUSB_ATTACH_A_ROLE (0x1<<0) //0:0 + +//U3D_SSUSB_OTG_STS_CLR +#define SSUSB_SRP_REQ_INTR_CLR (0x1<<11) //11:11 +#define SSUSB_DEV_USBRST_INTR_CLR (0x1<<7) //7:7 +#define SSUSB_VBUS_INTR_CLR (0x1<<6) //6:6 +#define SSUSB_CHG_B_ROLE_B_CLR (0x1<<5) //5:5 +#define SSUSB_CHG_A_ROLE_B_CLR (0x1<<4) //4:4 +#define SSUSB_ATTACH_B_ROLE_CLR (0x1<<3) //3:3 +#define SSUSB_CHG_B_ROLE_A_CLR (0x1<<2) //2:2 +#define SSUSB_CHG_A_ROLE_A_CLR (0x1<<1) //1:1 +#define SSUSB_ATTACH_A_ROLE_CLR (0x1<<0) //0:0 + +//U3D_SSUSB_IP_MAC_CAP +#define SSUSB_IP_MAC_U2_PORT_NO (0xff<<8) //15:8 +#define SSUSB_IP_MAC_U3_PORT_NO (0xff<<0) //7:0 + +//U3D_SSUSB_IP_XHCI_CAP +#define SSUSB_IP_XHCI_U2_PORT_NO (0xff<<8) //15:8 +#define SSUSB_IP_XHCI_U3_PORT_NO (0xff<<0) //7:0 + +//U3D_SSUSB_IP_DEV_CAP +#define SSUSB_IP_DEV_U2_PORT_NO (0xff<<8) //15:8 +#define SSUSB_IP_DEV_U3_PORT_NO (0xff<<0) //7:0 + +//U3D_SSUSB_OTG_INT_EN +#define SSUSB_DEV_USBRST_INT_EN (0x1<<8) //8:8 +#define SSUSB_VBUS_CHG_INT_A_EN (0x1<<7) //7:7 +#define SSUSB_VBUS_CHG_INT_B_EN (0x1<<6) //6:6 +#define SSUSB_CHG_B_ROLE_B_INT_EN (0x1<<5) //5:5 +#define SSUSB_CHG_A_ROLE_B_INT_EN (0x1<<4) //4:4 +#define SSUSB_ATTACH_B_ROLE_INT_EN (0x1<<3) //3:3 +#define SSUSB_CHG_B_ROLE_A_INT_EN (0x1<<2) //2:2 +#define SSUSB_CHG_A_ROLE_A_INT_EN (0x1<<1) //1:1 +#define SSUSB_ATTACH_A_ROLE_INT_EN (0x1<<0) //0:0 + +//U3D_SSUSB_U3_CTRL_0P +#define SSUSB_U3_PORT_PHYD_RST (0x1<<5) //5:5 +#define SSUSB_U3_PORT_MAC_RST (0x1<<4) //4:4 +#define SSUSB_U3_PORT_U2_CG_EN (0x1<<3) //3:3 +#define SSUSB_U3_PORT_HOST_SEL (0x1<<2) //2:2 +#define SSUSB_U3_PORT_PDN (0x1<<1) //1:1 +#define SSUSB_U3_PORT_DIS (0x1<<0) //0:0 + +//U3D_SSUSB_U3_CTRL_1P +#define SSUSB_U3_PORT_PHYD_RST_1P (0x1<<5) //5:5 +#define SSUSB_U3_PORT_MAC_RST_1P (0x1<<4) //4:4 +#define SSUSB_U3_PORT_U2_CG_EN_1P (0x1<<3) //3:3 +#define SSUSB_U3_PORT_HOST_SEL_1P (0x1<<2) //2:2 +#define SSUSB_U3_PORT_PDN_1P (0x1<<1) //1:1 +#define SSUSB_U3_PORT_DIS_1P (0x1<<0) //0:0 + +//U3D_SSUSB_U3_CTRL_2P +#define SSUSB_U3_PORT_PHYD_RST_2P (0x1<<5) //5:5 +#define SSUSB_U3_PORT_MAC_RST_2P (0x1<<4) //4:4 +#define SSUSB_U3_PORT_U2_CG_EN_2P (0x1<<3) //3:3 +#define SSUSB_U3_PORT_HOST_SEL_2P (0x1<<2) //2:2 +#define SSUSB_U3_PORT_PDN_2P (0x1<<1) //1:1 +#define SSUSB_U3_PORT_DIS_2P (0x1<<0) //0:0 + +//U3D_SSUSB_U3_CTRL_3P +#define SSUSB_U3_PORT_PHYD_RST_3P (0x1<<5) //5:5 +#define SSUSB_U3_PORT_MAC_RST_3P (0x1<<4) //4:4 +#define SSUSB_U3_PORT_U2_CG_EN_3P (0x1<<3) //3:3 +#define SSUSB_U3_PORT_HOST_SEL_3P (0x1<<2) //2:2 +#define SSUSB_U3_PORT_PDN_3P (0x1<<1) //1:1 +#define SSUSB_U3_PORT_DIS_3P (0x1<<0) //0:0 + +//U3D_SSUSB_U2_CTRL_0P +#define SSUSB_U2_PORT_OTG_HOST_VBUSVALID_SEL (0x1<<9) //9:9 +#define SSUSB_U2_PORT_OTG_MAC_AUTO_SEL (0x1<<8) //8:8 +#define SSUSB_U2_PORT_OTG_SEL (0x1<<7) //7:7 +#define SSUSB_U2_PORT_PLL_STABLE_SEL (0x1<<6) //6:6 +#define SSUSB_U2_PORT_PHYD_RST (0x1<<5) //5:5 +#define SSUSB_U2_PORT_MAC_RST (0x1<<4) //4:4 +#define SSUSB_U2_PORT_U2_CG_EN (0x1<<3) //3:3 +#define SSUSB_U2_PORT_HOST_SEL (0x1<<2) //2:2 +#define SSUSB_U2_PORT_PDN (0x1<<1) //1:1 +#define SSUSB_U2_PORT_DIS (0x1<<0) //0:0 + +//U3D_SSUSB_U2_CTRL_1P +#define SSUSB_U2_PORT_PLL_STABLE_SEL_1P (0x1<<6) //6:6 +#define SSUSB_U2_PORT_PHYD_RST_1P (0x1<<5) //5:5 +#define SSUSB_U2_PORT_MAC_RST_1P (0x1<<4) //4:4 +#define SSUSB_U2_PORT_U2_CG_EN_1P (0x1<<3) //3:3 +#define SSUSB_U2_PORT_HOST_SEL_1P (0x1<<2) //2:2 +#define SSUSB_U2_PORT_PDN_1P (0x1<<1) //1:1 +#define SSUSB_U2_PORT_DIS_1P (0x1<<0) //0:0 + +//U3D_SSUSB_U2_CTRL_2P +#define SSUSB_U2_PORT_PLL_STABLE_SEL_2P (0x1<<6) //6:6 +#define SSUSB_U2_PORT_PHYD_RST_2P (0x1<<5) //5:5 +#define SSUSB_U2_PORT_MAC_RST_2P (0x1<<4) //4:4 +#define SSUSB_U2_PORT_U2_CG_EN_2P (0x1<<3) //3:3 +#define SSUSB_U2_PORT_HOST_SEL_2P (0x1<<2) //2:2 +#define SSUSB_U2_PORT_PDN_2P (0x1<<1) //1:1 +#define SSUSB_U2_PORT_DIS_2P (0x1<<0) //0:0 + +//U3D_SSUSB_U2_CTRL_3P +#define SSUSB_U2_PORT_PLL_STABLE_SEL_3P (0x1<<6) //6:6 +#define SSUSB_U2_PORT_PHYD_RST_3P (0x1<<5) //5:5 +#define SSUSB_U2_PORT_MAC_RST_3P (0x1<<4) //4:4 +#define SSUSB_U2_PORT_U2_CG_EN_3P (0x1<<3) //3:3 +#define SSUSB_U2_PORT_HOST_SEL_3P (0x1<<2) //2:2 +#define SSUSB_U2_PORT_PDN_3P (0x1<<1) //1:1 +#define SSUSB_U2_PORT_DIS_3P (0x1<<0) //0:0 + +//U3D_SSUSB_U2_CTRL_4P +#define SSUSB_U2_PORT_PLL_STABLE_SEL_4P (0x1<<6) //6:6 +#define SSUSB_U2_PORT_PHYD_RST_4P (0x1<<5) //5:5 +#define SSUSB_U2_PORT_MAC_RST_4P (0x1<<4) //4:4 +#define SSUSB_U2_PORT_U2_CG_EN_4P (0x1<<3) //3:3 +#define SSUSB_U2_PORT_HOST_SEL_4P (0x1<<2) //2:2 +#define SSUSB_U2_PORT_PDN_4P (0x1<<1) //1:1 +#define SSUSB_U2_PORT_DIS_4P (0x1<<0) //0:0 + +//U3D_SSUSB_U2_CTRL_5P +#define SSUSB_U2_PORT_PLL_STABLE_SEL_5P (0x1<<6) //6:6 +#define SSUSB_U2_PORT_PHYD_RST_5P (0x1<<5) //5:5 +#define SSUSB_U2_PORT_MAC_RST_5P (0x1<<4) //4:4 +#define SSUSB_U2_PORT_U2_CG_EN_5P (0x1<<3) //3:3 +#define SSUSB_U2_PORT_HOST_SEL_5P (0x1<<2) //2:2 +#define SSUSB_U2_PORT_PDN_5P (0x1<<1) //1:1 +#define SSUSB_U2_PORT_DIS_5P (0x1<<0) //0:0 + +//U3D_SSUSB_U2_PHY_PLL +#define SSUSB_SYSPLL_USE (0x1<<30) //30:30 +#define RG_SSUSB_U2_PLL_STB (0x1<<29) //29:29 +#define SSUSB_U2_FORCE_PLL_STB (0x1<<28) //28:28 +#define SSUSB_U2_PORT_PHY_CK_DEB_TIMER (0xf<<24) //27:24 +#define SSUSB_U2_PORT_LPM_PLL_STABLE_TIMER (0xff<<16) //23:16 +#define SSUSB_U2_PORT_PLL_STABLE_TIMER (0xff<<8) //15:8 +#define SSUSB_U2_PORT_1US_TIMER (0xff<<0) //7:0 + +//U3D_SSUSB_DMA_CTRL +#define SSUSB_IP_DMA_BUS_CK_GATE_DIS (0x1<<0) //0:0 + +//U3D_SSUSB_MAC_CK_CTRL +#define SSUSB_MAC3_SYS_CK_GATE_MASK_TIME (0xff<<16) //23:16 +#define SSUSB_MAC2_SYS_CK_GATE_MASK_TIME (0xff<<8) //15:8 +#define SSUSB_PHY_REF_CK_DIV2 (0x1<<4) //4:4 +#define SSUSB_MAC3_SYS_CK_GATE_MODE (0x3<<2) //3:2 +#define SSUSB_MAC2_SYS_CK_GATE_MODE (0x3<<0) //1:0 + +//U3D_SSUSB_CSR_CK_CTRL +#define SSUSB_SIFSLV_MCU_BUS_CK_GATE_EN (0x1<<1) //1:1 +#define SSUSB_CSR_MCU_BUS_CK_GATE_EN (0x1<<0) //0:0 + +//U3D_SSUSB_REF_CK_CTRL +#define SSUSB_REF_MAC2_CK_GATE_EN (0x1<<4) //4:4 +#define SSUSB_REF_MAC3_CK_GATE_EN (0x1<<3) //3:3 +#define SSUSB_REF_CK_GATE_EN (0x1<<2) //2:2 +#define SSUSB_REF_PHY_CK_GATE_EN (0x1<<1) //1:1 +#define SSUSB_REF_MAC_CK_GATE_EN (0x1<<0) //0:0 + +//U3D_SSUSB_XHCI_CK_CTRL +#define SSUSB_XACT3_XHCI_CK_GATE_MASK_TIME (0xff<<8) //15:8 +#define SSUSB_XACT3_XHCI_CK_GATE_MODE (0x3<<4) //5:4 +#define SSUSB_XHCI_CK_DIV2_EN (0x1<<0) //0:0 + +//U3D_SSUSB_XHCI_RST_CTRL +#define SSUSB_XHCI_SW_DRAM_RST (0x1<<4) //4:4 +#define SSUSB_XHCI_SW_SYS60_RST (0x1<<3) //3:3 +#define SSUSB_XHCI_SW_SYS125_RST (0x1<<2) //2:2 +#define SSUSB_XHCI_SW_XHCI_RST (0x1<<1) //1:1 +#define SSUSB_XHCI_SW_RST (0x1<<0) //0:0 + +//U3D_SSUSB_DEV_RST_CTRL +#define SSUSB_DEV_SW_DRAM_RST (0x1<<3) //3:3 +#define SSUSB_DEV_SW_QMU_RST (0x1<<2) //2:2 +#define SSUSB_DEV_SW_BMU_RST (0x1<<1) //1:1 +#define SSUSB_DEV_SW_RST (0x1<<0) //0:0 + +//U3D_SSUSB_SYS_CK_CTRL +#define SSUSB_SYS60_CK_EXT_SEL (0x1<<2) //2:2 +#define SSUSB_SYS_CK_EXT_SEL (0x1<<1) //1:1 +#define SSUSB_SYS_CK_DIV2_EN (0x1<<0) //0:0 + +//U3D_SSUSB_HW_ID +#define SSUSB_HW_ID (0xffffffff<<0) //31:0 + +//U3D_SSUSB_HW_SUB_ID +#define SSUSB_HW_SUB_ID (0xffffffff<<0) //31:0 + +//U3D_SSUSB_PRB_CTRL0 +#define PRB_BYTE3_EN (0x1<<3) //3:3 +#define PRB_BYTE2_EN (0x1<<2) //2:2 +#define PRB_BYTE1_EN (0x1<<1) //1:1 +#define PRB_BYTE0_EN (0x1<<0) //0:0 + +//U3D_SSUSB_PRB_CTRL1 +#define PRB_BYTE1_SEL (0xffff<<16) //31:16 +#define PRB_BYTE0_SEL (0xffff<<0) //15:0 + +//U3D_SSUSB_PRB_CTRL2 +#define PRB_BYTE3_SEL (0xffff<<16) //31:16 +#define PRB_BYTE2_SEL (0xffff<<0) //15:0 + +//U3D_SSUSB_PRB_CTRL3 +#define PRB_BYTE3_MODULE_SEL (0xff<<24) //31:24 +#define PRB_BYTE2_MODULE_SEL (0xff<<16) //23:16 +#define PRB_BYTE1_MODULE_SEL (0xff<<8) //15:8 +#define PRB_BYTE0_MODULE_SEL (0xff<<0) //7:0 + +//U3D_SSUSB_PRB_CTRL4 +#define SW_PRB_OUT (0xffffffff<<0) //31:0 + +//U3D_SSUSB_PRB_CTRL5 +#define PRB_RD_DATA (0xffffffff<<0) //31:0 + +//U3D_SSUSB_IP_SPARE0 +#define SSUSB_IP_SPARE0 (0xffffffff<<0) //31:0 + +//U3D_SSUSB_IP_SPARE1 +#define SSUSB_IP_SPARE1 (0xffffffff<<0) //31:0 + +//U3D_SSUSB_FPGA_I2C_OUT_0P +#define SSUSB_FPGA_I2C_SCL_OEN_0P (0x1<<3) //3:3 +#define SSUSB_FPGA_I2C_SCL_OUT_0P (0x1<<2) //2:2 +#define SSUSB_FPGA_I2C_SDA_OEN_0P (0x1<<1) //1:1 +#define SSUSB_FPGA_I2C_SDA_OUT_0P (0x1<<0) //0:0 + +//U3D_SSUSB_FPGA_I2C_IN_0P +#define SSUSB_FPGA_I2C_SCL_IN_0P (0x1<<1) //1:1 +#define SSUSB_FPGA_I2C_SDA_IN_0P (0x1<<0) //0:0 + +//U3D_SSUSB_FPGA_I2C_OUT_1P +#define SSUSB_FPGA_I2C_SCL_OEN_1P (0x1<<3) //3:3 +#define SSUSB_FPGA_I2C_SCL_OUT_1P (0x1<<2) //2:2 +#define SSUSB_FPGA_I2C_SDA_OEN_1P (0x1<<1) //1:1 +#define SSUSB_FPGA_I2C_SDA_OUT_1P (0x1<<0) //0:0 + +//U3D_SSUSB_FPGA_I2C_IN_1P +#define SSUSB_FPGA_I2C_SCL_IN_1P (0x1<<1) //1:1 +#define SSUSB_FPGA_I2C_SDA_IN_1P (0x1<<0) //0:0 + +//U3D_SSUSB_FPGA_I2C_OUT_2P +#define SSUSB_FPGA_I2C_SCL_OEN_2P (0x1<<3) //3:3 +#define SSUSB_FPGA_I2C_SCL_OUT_2P (0x1<<2) //2:2 +#define SSUSB_FPGA_I2C_SDA_OEN_2P (0x1<<1) //1:1 +#define SSUSB_FPGA_I2C_SDA_OUT_2P (0x1<<0) //0:0 + +//U3D_SSUSB_FPGA_I2C_IN_2P +#define SSUSB_FPGA_I2C_SCL_IN_2P (0x1<<1) //1:1 +#define SSUSB_FPGA_I2C_SDA_IN_2P (0x1<<0) //0:0 + +//U3D_SSUSB_FPGA_I2C_OUT_3P +#define SSUSB_FPGA_I2C_SCL_OEN_3P (0x1<<3) //3:3 +#define SSUSB_FPGA_I2C_SCL_OUT_3P (0x1<<2) //2:2 +#define SSUSB_FPGA_I2C_SDA_OEN_3P (0x1<<1) //1:1 +#define SSUSB_FPGA_I2C_SDA_OUT_3P (0x1<<0) //0:0 + +//U3D_SSUSB_FPGA_I2C_IN_3P +#define SSUSB_FPGA_I2C_SCL_IN_3P (0x1<<1) //1:1 +#define SSUSB_FPGA_I2C_SDA_IN_3P (0x1<<0) //0:0 + +//U3D_SSUSB_FPGA_I2C_OUT_4P +#define SSUSB_FPGA_I2C_SCL_OEN_4P (0x1<<3) //3:3 +#define SSUSB_FPGA_I2C_SCL_OUT_4P (0x1<<2) //2:2 +#define SSUSB_FPGA_I2C_SDA_OEN_4P (0x1<<1) //1:1 +#define SSUSB_FPGA_I2C_SDA_OUT_4P (0x1<<0) //0:0 + +//U3D_SSUSB_FPGA_I2C_IN_4P +#define SSUSB_FPGA_I2C_SCL_IN_4P (0x1<<1) //1:1 +#define SSUSB_FPGA_I2C_SDA_IN_4P (0x1<<0) //0:0 + +//U3D_SSUSB_IP_SLV_TMOUT +#define SSUSB_IP_SLV_TMOUT (0xffffffff<<0) //31:0 + + +/* SSUSB_SIFSLV_IPPC FIELD OFFSET DEFINITION */ + +//U3D_SSUSB_IP_PW_CTRL0 +#define SSUSB_AHB_SLV_AUTO_RSP_OFST (17) +#define SSUSB_IP_SW_RST_CK_GATE_EN_OFST (16) +#define SSUSB_IP_U2_ENTER_SLEEP_CNT_OFST (8) +#define SSUSB_IP_SW_RST_OFST (0) + +//U3D_SSUSB_IP_PW_CTRL1 +#define SSUSB_IP_HOST_PDN_OFST (0) + +//U3D_SSUSB_IP_PW_CTRL2 +#define SSUSB_IP_DEV_PDN_OFST (0) + +//U3D_SSUSB_IP_PW_CTRL3 +#define SSUSB_IP_PCIE_PDN_OFST (0) + +//U3D_SSUSB_IP_PW_STS1 +#define SSUSB_IP_REF_CK_DIS_STS_OFST (31) +#define SSUSB_IP_SLEEP_STS_OFST (30) +#define SSUSB_U2_MAC_RST_B_STS_5P_OFST (29) +#define SSUSB_U2_MAC_RST_B_STS_4P_OFST (28) +#define SSUSB_U2_MAC_RST_B_STS_3P_OFST (27) +#define SSUSB_U2_MAC_RST_B_STS_2P_OFST (26) +#define SSUSB_U2_MAC_RST_B_STS_1P_OFST (25) +#define SSUSB_U2_MAC_RST_B_STS_OFST (24) +#define SSUSB_U3_MAC_RST_B_STS_3P_OFST (19) +#define SSUSB_U3_MAC_RST_B_STS_2P_OFST (18) +#define SSUSB_U3_MAC_RST_B_STS_1P_OFST (17) +#define SSUSB_U3_MAC_RST_B_STS_OFST (16) +#define SSUSB_DEV_DRAM_RST_B_STS_OFST (13) +#define SSUSB_XHCI_DRAM_RST_B_STS_OFST (12) +#define SSUSB_XHCI_RST_B_STS_OFST (11) +#define SSUSB_SYS125_RST_B_STS_OFST (10) +#define SSUSB_SYS60_RST_B_STS_OFST (9) +#define SSUSB_REF_RST_B_STS_OFST (8) +#define SSUSB_DEV_RST_B_STS_OFST (3) +#define SSUSB_DEV_BMU_RST_B_STS_OFST (2) +#define SSUSB_DEV_QMU_RST_B_STS_OFST (1) +#define SSUSB_SYSPLL_STABLE_OFST (0) + +//U3D_SSUSB_IP_PW_STS2 +#define SSUSB_U2_MAC_SYS_RST_B_STS_5P_OFST (5) +#define SSUSB_U2_MAC_SYS_RST_B_STS_4P_OFST (4) +#define SSUSB_U2_MAC_SYS_RST_B_STS_3P_OFST (3) +#define SSUSB_U2_MAC_SYS_RST_B_STS_2P_OFST (2) +#define SSUSB_U2_MAC_SYS_RST_B_STS_1P_OFST (1) +#define SSUSB_U2_MAC_SYS_RST_B_STS_OFST (0) + +//U3D_SSUSB_OTG_STS +#define SSUSB_XHCI_MAS_DMA_REQ_OFST (14) +#define SSUSB_DEV_DMA_REQ_OFST (13) +#define SSUSB_AVALID_STS_OFST (12) +#define SSUSB_SRP_REQ_INTR_OFST (11) +#define SSUSB_IDDIG_OFST (10) +#define SSUSB_VBUS_VALID_OFST (9) +#define SSUSB_HOST_DEV_MODE_OFST (8) +#define SSUSB_DEV_USBRST_INTR_OFST (7) +#define VBUS_CHG_INTR_OFST (6) +#define SSUSB_CHG_B_ROLE_B_OFST (5) +#define SSUSB_CHG_A_ROLE_B_OFST (4) +#define SSUSB_ATTACH_B_ROLE_OFST (3) +#define SSUSB_CHG_B_ROLE_A_OFST (2) +#define SSUSB_CHG_A_ROLE_A_OFST (1) +#define SSUSB_ATTACH_A_ROLE_OFST (0) + +//U3D_SSUSB_OTG_STS_CLR +#define SSUSB_SRP_REQ_INTR_CLR_OFST (11) +#define SSUSB_DEV_USBRST_INTR_CLR_OFST (7) +#define SSUSB_VBUS_INTR_CLR_OFST (6) +#define SSUSB_CHG_B_ROLE_B_CLR_OFST (5) +#define SSUSB_CHG_A_ROLE_B_CLR_OFST (4) +#define SSUSB_ATTACH_B_ROLE_CLR_OFST (3) +#define SSUSB_CHG_B_ROLE_A_CLR_OFST (2) +#define SSUSB_CHG_A_ROLE_A_CLR_OFST (1) +#define SSUSB_ATTACH_A_ROLE_CLR_OFST (0) + +//U3D_SSUSB_IP_MAC_CAP +#define SSUSB_IP_MAC_U2_PORT_NO_OFST (8) +#define SSUSB_IP_MAC_U3_PORT_NO_OFST (0) + +//U3D_SSUSB_IP_XHCI_CAP +#define SSUSB_IP_XHCI_U2_PORT_NO_OFST (8) +#define SSUSB_IP_XHCI_U3_PORT_NO_OFST (0) + +//U3D_SSUSB_IP_DEV_CAP +#define SSUSB_IP_DEV_U2_PORT_NO_OFST (8) +#define SSUSB_IP_DEV_U3_PORT_NO_OFST (0) + +//U3D_SSUSB_OTG_INT_EN +#define SSUSB_DEV_USBRST_INT_EN_OFST (8) +#define SSUSB_VBUS_CHG_INT_A_EN_OFST (7) +#define SSUSB_VBUS_CHG_INT_B_EN_OFST (6) +#define SSUSB_CHG_B_ROLE_B_INT_EN_OFST (5) +#define SSUSB_CHG_A_ROLE_B_INT_EN_OFST (4) +#define SSUSB_ATTACH_B_ROLE_INT_EN_OFST (3) +#define SSUSB_CHG_B_ROLE_A_INT_EN_OFST (2) +#define SSUSB_CHG_A_ROLE_A_INT_EN_OFST (1) +#define SSUSB_ATTACH_A_ROLE_INT_EN_OFST (0) + +//U3D_SSUSB_U3_CTRL_0P +#define SSUSB_U3_PORT_PHYD_RST_OFST (5) +#define SSUSB_U3_PORT_MAC_RST_OFST (4) +#define SSUSB_U3_PORT_U2_CG_EN_OFST (3) +#define SSUSB_U3_PORT_HOST_SEL_OFST (2) +#define SSUSB_U3_PORT_PDN_OFST (1) +#define SSUSB_U3_PORT_DIS_OFST (0) + +//U3D_SSUSB_U3_CTRL_1P +#define SSUSB_U3_PORT_PHYD_RST_1P_OFST (5) +#define SSUSB_U3_PORT_MAC_RST_1P_OFST (4) +#define SSUSB_U3_PORT_U2_CG_EN_1P_OFST (3) +#define SSUSB_U3_PORT_HOST_SEL_1P_OFST (2) +#define SSUSB_U3_PORT_PDN_1P_OFST (1) +#define SSUSB_U3_PORT_DIS_1P_OFST (0) + +//U3D_SSUSB_U3_CTRL_2P +#define SSUSB_U3_PORT_PHYD_RST_2P_OFST (5) +#define SSUSB_U3_PORT_MAC_RST_2P_OFST (4) +#define SSUSB_U3_PORT_U2_CG_EN_2P_OFST (3) +#define SSUSB_U3_PORT_HOST_SEL_2P_OFST (2) +#define SSUSB_U3_PORT_PDN_2P_OFST (1) +#define SSUSB_U3_PORT_DIS_2P_OFST (0) + +//U3D_SSUSB_U3_CTRL_3P +#define SSUSB_U3_PORT_PHYD_RST_3P_OFST (5) +#define SSUSB_U3_PORT_MAC_RST_3P_OFST (4) +#define SSUSB_U3_PORT_U2_CG_EN_3P_OFST (3) +#define SSUSB_U3_PORT_HOST_SEL_3P_OFST (2) +#define SSUSB_U3_PORT_PDN_3P_OFST (1) +#define SSUSB_U3_PORT_DIS_3P_OFST (0) + +//U3D_SSUSB_U2_CTRL_0P +#define SSUSB_U2_PORT_OTG_HOST_VBUSVALID_SEL_OFST (9) +#define SSUSB_U2_PORT_OTG_MAC_AUTO_SEL_OFST (8) +#define SSUSB_U2_PORT_OTG_SEL_OFST (7) +#define SSUSB_U2_PORT_PLL_STABLE_SEL_OFST (6) +#define SSUSB_U2_PORT_PHYD_RST_OFST (5) +#define SSUSB_U2_PORT_MAC_RST_OFST (4) +#define SSUSB_U2_PORT_U2_CG_EN_OFST (3) +#define SSUSB_U2_PORT_HOST_SEL_OFST (2) +#define SSUSB_U2_PORT_PDN_OFST (1) +#define SSUSB_U2_PORT_DIS_OFST (0) + +//U3D_SSUSB_U2_CTRL_1P +#define SSUSB_U2_PORT_PLL_STABLE_SEL_1P_OFST (6) +#define SSUSB_U2_PORT_PHYD_RST_1P_OFST (5) +#define SSUSB_U2_PORT_MAC_RST_1P_OFST (4) +#define SSUSB_U2_PORT_U2_CG_EN_1P_OFST (3) +#define SSUSB_U2_PORT_HOST_SEL_1P_OFST (2) +#define SSUSB_U2_PORT_PDN_1P_OFST (1) +#define SSUSB_U2_PORT_DIS_1P_OFST (0) + +//U3D_SSUSB_U2_CTRL_2P +#define SSUSB_U2_PORT_PLL_STABLE_SEL_2P_OFST (6) +#define SSUSB_U2_PORT_PHYD_RST_2P_OFST (5) +#define SSUSB_U2_PORT_MAC_RST_2P_OFST (4) +#define SSUSB_U2_PORT_U2_CG_EN_2P_OFST (3) +#define SSUSB_U2_PORT_HOST_SEL_2P_OFST (2) +#define SSUSB_U2_PORT_PDN_2P_OFST (1) +#define SSUSB_U2_PORT_DIS_2P_OFST (0) + +//U3D_SSUSB_U2_CTRL_3P +#define SSUSB_U2_PORT_PLL_STABLE_SEL_3P_OFST (6) +#define SSUSB_U2_PORT_PHYD_RST_3P_OFST (5) +#define SSUSB_U2_PORT_MAC_RST_3P_OFST (4) +#define SSUSB_U2_PORT_U2_CG_EN_3P_OFST (3) +#define SSUSB_U2_PORT_HOST_SEL_3P_OFST (2) +#define SSUSB_U2_PORT_PDN_3P_OFST (1) +#define SSUSB_U2_PORT_DIS_3P_OFST (0) + +//U3D_SSUSB_U2_CTRL_4P +#define SSUSB_U2_PORT_PLL_STABLE_SEL_4P_OFST (6) +#define SSUSB_U2_PORT_PHYD_RST_4P_OFST (5) +#define SSUSB_U2_PORT_MAC_RST_4P_OFST (4) +#define SSUSB_U2_PORT_U2_CG_EN_4P_OFST (3) +#define SSUSB_U2_PORT_HOST_SEL_4P_OFST (2) +#define SSUSB_U2_PORT_PDN_4P_OFST (1) +#define SSUSB_U2_PORT_DIS_4P_OFST (0) + +//U3D_SSUSB_U2_CTRL_5P +#define SSUSB_U2_PORT_PLL_STABLE_SEL_5P_OFST (6) +#define SSUSB_U2_PORT_PHYD_RST_5P_OFST (5) +#define SSUSB_U2_PORT_MAC_RST_5P_OFST (4) +#define SSUSB_U2_PORT_U2_CG_EN_5P_OFST (3) +#define SSUSB_U2_PORT_HOST_SEL_5P_OFST (2) +#define SSUSB_U2_PORT_PDN_5P_OFST (1) +#define SSUSB_U2_PORT_DIS_5P_OFST (0) + +//U3D_SSUSB_U2_PHY_PLL +#define SSUSB_SYSPLL_USE_OFST (30) +#define RG_SSUSB_U2_PLL_STB_OFST (29) +#define SSUSB_U2_FORCE_PLL_STB_OFST (28) +#define SSUSB_U2_PORT_PHY_CK_DEB_TIMER_OFST (24) +#define SSUSB_U2_PORT_LPM_PLL_STABLE_TIMER_OFST (16) +#define SSUSB_U2_PORT_PLL_STABLE_TIMER_OFST (8) +#define SSUSB_U2_PORT_1US_TIMER_OFST (0) + +//U3D_SSUSB_DMA_CTRL +#define SSUSB_IP_DMA_BUS_CK_GATE_DIS_OFST (0) + +//U3D_SSUSB_MAC_CK_CTRL +#define SSUSB_MAC3_SYS_CK_GATE_MASK_TIME_OFST (16) +#define SSUSB_MAC2_SYS_CK_GATE_MASK_TIME_OFST (8) +#define SSUSB_PHY_REF_CK_DIV2_OFST (4) +#define SSUSB_MAC3_SYS_CK_GATE_MODE_OFST (2) +#define SSUSB_MAC2_SYS_CK_GATE_MODE_OFST (0) + +//U3D_SSUSB_CSR_CK_CTRL +#define SSUSB_SIFSLV_MCU_BUS_CK_GATE_EN_OFST (1) +#define SSUSB_CSR_MCU_BUS_CK_GATE_EN_OFST (0) + +//U3D_SSUSB_REF_CK_CTRL +#define SSUSB_REF_MAC2_CK_GATE_EN_OFST (4) +#define SSUSB_REF_MAC3_CK_GATE_EN_OFST (3) +#define SSUSB_REF_CK_GATE_EN_OFST (2) +#define SSUSB_REF_PHY_CK_GATE_EN_OFST (1) +#define SSUSB_REF_MAC_CK_GATE_EN_OFST (0) + +//U3D_SSUSB_XHCI_CK_CTRL +#define SSUSB_XACT3_XHCI_CK_GATE_MASK_TIME_OFST (8) +#define SSUSB_XACT3_XHCI_CK_GATE_MODE_OFST (4) +#define SSUSB_XHCI_CK_DIV2_EN_OFST (0) + +//U3D_SSUSB_XHCI_RST_CTRL +#define SSUSB_XHCI_SW_DRAM_RST_OFST (4) +#define SSUSB_XHCI_SW_SYS60_RST_OFST (3) +#define SSUSB_XHCI_SW_SYS125_RST_OFST (2) +#define SSUSB_XHCI_SW_XHCI_RST_OFST (1) +#define SSUSB_XHCI_SW_RST_OFST (0) + +//U3D_SSUSB_DEV_RST_CTRL +#define SSUSB_DEV_SW_DRAM_RST_OFST (3) +#define SSUSB_DEV_SW_QMU_RST_OFST (2) +#define SSUSB_DEV_SW_BMU_RST_OFST (1) +#define SSUSB_DEV_SW_RST_OFST (0) + +//U3D_SSUSB_SYS_CK_CTRL +#define SSUSB_SYS60_CK_EXT_SEL_OFST (2) +#define SSUSB_SYS_CK_EXT_SEL_OFST (1) +#define SSUSB_SYS_CK_DIV2_EN_OFST (0) + +//U3D_SSUSB_HW_ID +#define SSUSB_HW_ID_OFST (0) + +//U3D_SSUSB_HW_SUB_ID +#define SSUSB_HW_SUB_ID_OFST (0) + +//U3D_SSUSB_PRB_CTRL0 +#define PRB_BYTE3_EN_OFST (3) +#define PRB_BYTE2_EN_OFST (2) +#define PRB_BYTE1_EN_OFST (1) +#define PRB_BYTE0_EN_OFST (0) + +//U3D_SSUSB_PRB_CTRL1 +#define PRB_BYTE1_SEL_OFST (16) +#define PRB_BYTE0_SEL_OFST (0) + +//U3D_SSUSB_PRB_CTRL2 +#define PRB_BYTE3_SEL_OFST (16) +#define PRB_BYTE2_SEL_OFST (0) + +//U3D_SSUSB_PRB_CTRL3 +#define PRB_BYTE3_MODULE_SEL_OFST (24) +#define PRB_BYTE2_MODULE_SEL_OFST (16) +#define PRB_BYTE1_MODULE_SEL_OFST (8) +#define PRB_BYTE0_MODULE_SEL_OFST (0) + +//U3D_SSUSB_PRB_CTRL4 +#define SW_PRB_OUT_OFST (0) + +//U3D_SSUSB_PRB_CTRL5 +#define PRB_RD_DATA_OFST (0) + +//U3D_SSUSB_IP_SPARE0 +#define SSUSB_IP_SPARE0_OFST (0) + +//U3D_SSUSB_IP_SPARE1 +#define SSUSB_IP_SPARE1_OFST (0) + +//U3D_SSUSB_FPGA_I2C_OUT_0P +#define SSUSB_FPGA_I2C_SCL_OEN_0P_OFST (3) +#define SSUSB_FPGA_I2C_SCL_OUT_0P_OFST (2) +#define SSUSB_FPGA_I2C_SDA_OEN_0P_OFST (1) +#define SSUSB_FPGA_I2C_SDA_OUT_0P_OFST (0) + +//U3D_SSUSB_FPGA_I2C_IN_0P +#define SSUSB_FPGA_I2C_SCL_IN_0P_OFST (1) +#define SSUSB_FPGA_I2C_SDA_IN_0P_OFST (0) + +//U3D_SSUSB_FPGA_I2C_OUT_1P +#define SSUSB_FPGA_I2C_SCL_OEN_1P_OFST (3) +#define SSUSB_FPGA_I2C_SCL_OUT_1P_OFST (2) +#define SSUSB_FPGA_I2C_SDA_OEN_1P_OFST (1) +#define SSUSB_FPGA_I2C_SDA_OUT_1P_OFST (0) + +//U3D_SSUSB_FPGA_I2C_IN_1P +#define SSUSB_FPGA_I2C_SCL_IN_1P_OFST (1) +#define SSUSB_FPGA_I2C_SDA_IN_1P_OFST (0) + +//U3D_SSUSB_FPGA_I2C_OUT_2P +#define SSUSB_FPGA_I2C_SCL_OEN_2P_OFST (3) +#define SSUSB_FPGA_I2C_SCL_OUT_2P_OFST (2) +#define SSUSB_FPGA_I2C_SDA_OEN_2P_OFST (1) +#define SSUSB_FPGA_I2C_SDA_OUT_2P_OFST (0) + +//U3D_SSUSB_FPGA_I2C_IN_2P +#define SSUSB_FPGA_I2C_SCL_IN_2P_OFST (1) +#define SSUSB_FPGA_I2C_SDA_IN_2P_OFST (0) + +//U3D_SSUSB_FPGA_I2C_OUT_3P +#define SSUSB_FPGA_I2C_SCL_OEN_3P_OFST (3) +#define SSUSB_FPGA_I2C_SCL_OUT_3P_OFST (2) +#define SSUSB_FPGA_I2C_SDA_OEN_3P_OFST (1) +#define SSUSB_FPGA_I2C_SDA_OUT_3P_OFST (0) + +//U3D_SSUSB_FPGA_I2C_IN_3P +#define SSUSB_FPGA_I2C_SCL_IN_3P_OFST (1) +#define SSUSB_FPGA_I2C_SDA_IN_3P_OFST (0) + +//U3D_SSUSB_FPGA_I2C_OUT_4P +#define SSUSB_FPGA_I2C_SCL_OEN_4P_OFST (3) +#define SSUSB_FPGA_I2C_SCL_OUT_4P_OFST (2) +#define SSUSB_FPGA_I2C_SDA_OEN_4P_OFST (1) +#define SSUSB_FPGA_I2C_SDA_OUT_4P_OFST (0) + +//U3D_SSUSB_FPGA_I2C_IN_4P +#define SSUSB_FPGA_I2C_SCL_IN_4P_OFST (1) +#define SSUSB_FPGA_I2C_SDA_IN_4P_OFST (0) + +//U3D_SSUSB_IP_SLV_TMOUT +#define SSUSB_IP_SLV_TMOUT_OFST (0) + +////////////////////////////////////////////////////////////////////// diff --git a/include/linux/mu3d/hal/ssusb_usb2_csr_c_header.h b/include/linux/mu3d/hal/ssusb_usb2_csr_c_header.h new file mode 100644 index 000000000..084eead09 --- /dev/null +++ b/include/linux/mu3d/hal/ssusb_usb2_csr_c_header.h @@ -0,0 +1,294 @@ +/* SSUSB_USB2_CSR REGISTER DEFINITION */ + +#define U3D_XHCI_PORT_CTRL (SSUSB_USB2_CSR_BASE+0x0000) +#define U3D_POWER_MANAGEMENT (SSUSB_USB2_CSR_BASE+0x0004) +#define U3D_TIMING_TEST_MODE (SSUSB_USB2_CSR_BASE+0x0008) +#define U3D_DEVICE_CONTROL (SSUSB_USB2_CSR_BASE+0x000C) +#define U3D_POWER_UP_COUNTER (SSUSB_USB2_CSR_BASE+0x0010) +#define U3D_USB2_TEST_MODE (SSUSB_USB2_CSR_BASE+0x0014) +#define U3D_COMMON_USB_INTR_ENABLE (SSUSB_USB2_CSR_BASE+0x0018) +#define U3D_COMMON_USB_INTR (SSUSB_USB2_CSR_BASE+0x001C) +#define U3D_USB_BUS_PERFORMANCE (SSUSB_USB2_CSR_BASE+0x0020) +#define U3D_LINK_RESET_INFO (SSUSB_USB2_CSR_BASE+0x0024) +#define U3D_RESET_RESUME_TIME_VALUE (SSUSB_USB2_CSR_BASE+0x0034) +#define U3D_UTMI_SIGNAL_SEL (SSUSB_USB2_CSR_BASE+0x0038) +#define U3D_USB20_FRAME_NUM (SSUSB_USB2_CSR_BASE+0x003C) +#define U3D_USB20_TIMING_PARAMETER (SSUSB_USB2_CSR_BASE+0x0040) +#define U3D_USB20_LPM_PARAMETER (SSUSB_USB2_CSR_BASE+0x0044) +#define U3D_USB20_LPM_ENTRY_COUNT (SSUSB_USB2_CSR_BASE+0x0048) +#define U3D_USB20_MISC_CONTROL (SSUSB_USB2_CSR_BASE+0x004C) +#define U3D_USB20_LPM_TIMING_PARAM (SSUSB_USB2_CSR_BASE+0x0050) +#define U3D_USB20_OPSTATE (SSUSB_USB2_CSR_BASE+0x0060) + +/* SSUSB_USB2_CSR FIELD DEFINITION */ + +//U3D_XHCI_PORT_CTRL +#define GO_POLLING (0x1<<7) //7:7 + +//U3D_POWER_MANAGEMENT +#define LPM_BESL_STALL (0x1<<14) //14:14 +#define LPM_BESLD_STALL (0x1<<13) //13:13 +#define BC12_EN (0x1<<12) //12:12 +#define LPM_RWP (0x1<<11) //11:11 +#define LPM_HRWE (0x1<<10) //10:10 +#define LPM_MODE (0x3<<8) //9:8 +#define ISO_UPDATE (0x1<<7) //7:7 +#define SOFT_CONN (0x1<<6) //6:6 +#define HS_ENABLE (0x1<<5) //5:5 +#define HS_MODE (0x1<<4) //4:4 +#define BUS_RESET (0x1<<3) //3:3 +#define RESUME (0x1<<2) //2:2 +#define SUSPEND (0x1<<1) //1:1 +#define SUSPENDM_ENABLE (0x1<<0) //0:0 + +//U3D_TIMING_TEST_MODE +#define FS_DIS_SEL (0xf<<4) //7:4 +#define PHY_CLK_VALID (0x1<<3) //3:3 +#define FS_DIS_NE (0x1<<2) //2:2 +#define TM1 (0x1<<0) //0:0 + +//U3D_DEVICE_CONTROL +#define HW_AUTO_SENDRST_EN (0x1<<8) //8:8 +#define B_DEV (0x1<<7) //7:7 +#define FS_DEV (0x1<<6) //6:6 +#define LS_DEV (0x1<<5) //5:5 +#define VBUS (0x3<<3) //4:3 +#define HOSTMODE (0x1<<2) //2:2 +#define HOSTREQ (0x1<<1) //1:1 +#define SESSION (0x1<<0) //0:0 + +//U3D_POWER_UP_COUNTER +#define LPM_HUBDRVRMP_TIME (0xffff<<8) //23:8 +#define PWR_UP_CNT_LMT (0xf<<0) //3:0 + +//U3D_USB2_TEST_MODE +#define U2U3_AUTO_SWITCH (0x1<<10) //10:10 +#define HOST_FORCE_EN (0x1<<9) //9:9 +#define LPM_FORCE_STALL (0x1<<8) //8:8 +#define FORCE_HOST (0x1<<7) //7:7 +#define FIFO_ACCESS (0x1<<6) //6:6 +#define FORCE_FS (0x1<<5) //5:5 +#define FORCE_HS (0x1<<4) //4:4 +#define TEST_PACKET_MODE (0x1<<3) //3:3 +#define TEST_K_MODE (0x1<<2) //2:2 +#define TEST_J_MODE (0x1<<1) //1:1 +#define TEST_SE0_NAK_MODE (0x1<<0) //0:0 + +//U3D_COMMON_USB_INTR_ENABLE +#define LPM_RESUME_INTR_EN (0x1<<9) //9:9 +#define LPM_INTR_EN (0x1<<8) //8:8 +#define VBUSERR_INTR_EN (0x1<<7) //7:7 +#define SESSION_REQ_INTR_EN (0x1<<6) //6:6 +#define DISCONN_INTR_EN (0x1<<5) //5:5 +#define CONN_INTR_EN (0x1<<4) //4:4 +#define SOF_INTR_EN (0x1<<3) //3:3 +#define RESET_INTR_EN (0x1<<2) //2:2 +#define RESUME_INTR_EN (0x1<<1) //1:1 +#define SUSPEND_INTR_EN (0x1<<0) //0:0 + +//U3D_COMMON_USB_INTR +#define LPM_RESUME_INTR (0x1<<9) //9:9 +#define LPM_INTR (0x1<<8) //8:8 +#define VBUSERR_INTR (0x1<<7) //7:7 +#define SESSION_REQ_INTR (0x1<<6) //6:6 +#define DISCONN_INTR (0x1<<5) //5:5 +#define CONN_INTR (0x1<<4) //4:4 +#define SOF_INTR (0x1<<3) //3:3 +#define RESET_INTR (0x1<<2) //2:2 +#define RESUME_INTR (0x1<<1) //1:1 +#define SUSPEND_INTR (0x1<<0) //0:0 + +//U3D_USB_BUS_PERFORMANCE +#define XFER_START_FROM_SOF (0x1<<24) //24:24 +#define VBUSERR_MODE (0x1<<23) //23:23 +#define TX_FLUSH_EN (0x1<<22) //22:22 +#define NOISE_STILL_SOF (0x1<<21) //21:21 +#define UNDO_SRP_FIX (0x1<<19) //19:19 +#define OTG_DEGLITCH_DISABLE (0x1<<18) //18:18 +#define SWRST (0x1<<17) //17:17 +#define DIS_USB_RESET (0x1<<16) //16:16 +#define SOFT_DEBOUCE (0x1<<0) //0:0 + +//U3D_LINK_RESET_INFO +#define WTWRSM (0xf<<28) //31:28 +#define WTRSMK (0xf<<24) //27:24 +#define WRFSSE0 (0xf<<20) //23:20 +#define WTCHRP (0xf<<16) //19:16 +#define VPLEN (0xff<<8) //15:8 +#define WTCON (0xf<<4) //7:4 +#define WTID (0xf<<0) //3:0 + +//U3D_RESET_RESUME_TIME_VALUE +#define USB20_RESET_TIME_VALUE (0xffff<<0) //15:0 + +//U3D_UTMI_SIGNAL_SEL +#define TX_SIGNAL_SEL (0x3<<2) //3:2 +#define RX_SIGNAL_SEL (0x3<<0) //1:0 + +//U3D_USB20_FRAME_NUM +#define FRAME_NUMBER (0x7ff<<0) //10:0 + +//U3D_USB20_TIMING_PARAMETER +#define CHOPPER_DELAY_TIME (0xff<<16) //23:16 +#define SOFTCON_DELAY_TIME (0xff<<8) //15:8 +#define TIME_VALUE_1US (0xff<<0) //7:0 + +//U3D_USB20_LPM_PARAMETER +#define BESLCK_U3 (0xf<<12) //15:12 +#define BESLCK (0xf<<8) //11:8 +#define BESLDCK (0xf<<4) //7:4 +#define BESL (0xf<<0) //3:0 + +//U3D_USB20_LPM_ENTRY_COUNT +#define LPM_EXIT_COUNT (0xff<<16) //23:16 +#define LPM_EXIT_COUNT_RESET (0x1<<9) //9:9 +#define LPM_ENTRY_COUNT_RESET (0x1<<8) //8:8 +#define LPM_ENTRY_COUNT (0xff<<0) //7:0 + +//U3D_USB20_MISC_CONTROL +#define LPM_U3_ACK_EN (0x1<<0) //0:0 + +//U3D_USB20_LPM_TIMING_PARAM +#define LPM_L1_TOKENRETRY (0x1ff<<16) //24:16 +#define LPM_L1_RESIDENCY (0xfff<<0) //11:0 + +//U3D_USB20_OPSTATE +#define OPSTATE_SYS (0x3f<<0) //5:0 + + +/* SSUSB_USB2_CSR FIELD OFFSET DEFINITION */ + +//U3D_XHCI_PORT_CTRL +#define GO_POLLING_OFST (7) + +//U3D_POWER_MANAGEMENT +#define LPM_BESL_STALL_OFST (14) +#define LPM_BESLD_STALL_OFST (13) +#define BC12_EN_OFST (12) +#define LPM_RWP_OFST (11) +#define LPM_HRWE_OFST (10) +#define LPM_MODE_OFST (8) +#define ISO_UPDATE_OFST (7) +#define SOFT_CONN_OFST (6) +#define HS_ENABLE_OFST (5) +#define HS_MODE_OFST (4) +#define BUS_RESET_OFST (3) +#define RESUME_OFST (2) +#define SUSPEND_OFST (1) +#define SUSPENDM_ENABLE_OFST (0) + +//U3D_TIMING_TEST_MODE +#define FS_DIS_SEL_OFST (4) +#define PHY_CLK_VALID_OFST (3) +#define FS_DIS_NE_OFST (2) +#define TM1_OFST (0) + +//U3D_DEVICE_CONTROL +#define HW_AUTO_SENDRST_EN_OFST (8) +#define B_DEV_OFST (7) +#define FS_DEV_OFST (6) +#define LS_DEV_OFST (5) +#define VBUS_OFST (3) +#define HOSTMODE_OFST (2) +#define HOSTREQ_OFST (1) +#define SESSION_OFST (0) + +//U3D_POWER_UP_COUNTER +#define LPM_HUBDRVRMP_TIME_OFST (8) +#define PWR_UP_CNT_LMT_OFST (0) + +//U3D_USB2_TEST_MODE +#define U2U3_AUTO_SWITCH_OFST (10) +#define HOST_FORCE_EN_OFST (9) +#define LPM_FORCE_STALL_OFST (8) +#define FORCE_HOST_OFST (7) +#define FIFO_ACCESS_OFST (6) +#define FORCE_FS_OFST (5) +#define FORCE_HS_OFST (4) +#define TEST_PACKET_MODE_OFST (3) +#define TEST_K_MODE_OFST (2) +#define TEST_J_MODE_OFST (1) +#define TEST_SE0_NAK_MODE_OFST (0) + +//U3D_COMMON_USB_INTR_ENABLE +#define LPM_RESUME_INTR_EN_OFST (9) +#define LPM_INTR_EN_OFST (8) +#define VBUSERR_INTR_EN_OFST (7) +#define SESSION_REQ_INTR_EN_OFST (6) +#define DISCONN_INTR_EN_OFST (5) +#define CONN_INTR_EN_OFST (4) +#define SOF_INTR_EN_OFST (3) +#define RESET_INTR_EN_OFST (2) +#define RESUME_INTR_EN_OFST (1) +#define SUSPEND_INTR_EN_OFST (0) + +//U3D_COMMON_USB_INTR +#define LPM_RESUME_INTR_OFST (9) +#define LPM_INTR_OFST (8) +#define VBUSERR_INTR_OFST (7) +#define SESSION_REQ_INTR_OFST (6) +#define DISCONN_INTR_OFST (5) +#define CONN_INTR_OFST (4) +#define SOF_INTR_OFST (3) +#define RESET_INTR_OFST (2) +#define RESUME_INTR_OFST (1) +#define SUSPEND_INTR_OFST (0) + +//U3D_USB_BUS_PERFORMANCE +#define XFER_START_FROM_SOF_OFST (24) +#define VBUSERR_MODE_OFST (23) +#define TX_FLUSH_EN_OFST (22) +#define NOISE_STILL_SOF_OFST (21) +#define UNDO_SRP_FIX_OFST (19) +#define OTG_DEGLITCH_DISABLE_OFST (18) +#define SWRST_OFST (17) +#define DIS_USB_RESET_OFST (16) +#define SOFT_DEBOUCE_OFST (0) + +//U3D_LINK_RESET_INFO +#define WTWRSM_OFST (28) +#define WTRSMK_OFST (24) +#define WRFSSE0_OFST (20) +#define WTCHRP_OFST (16) +#define VPLEN_OFST (8) +#define WTCON_OFST (4) +#define WTID_OFST (0) + +//U3D_RESET_RESUME_TIME_VALUE +#define USB20_RESET_TIME_VALUE_OFST (0) + +//U3D_UTMI_SIGNAL_SEL +#define TX_SIGNAL_SEL_OFST (2) +#define RX_SIGNAL_SEL_OFST (0) + +//U3D_USB20_FRAME_NUM +#define FRAME_NUMBER_OFST (0) + +//U3D_USB20_TIMING_PARAMETER +#define CHOPPER_DELAY_TIME_OFST (16) +#define SOFTCON_DELAY_TIME_OFST (8) +#define TIME_VALUE_1US_OFST (0) + +//U3D_USB20_LPM_PARAMETER +#define BESLCK_U3_OFST (12) +#define BESLCK_OFST (8) +#define BESLDCK_OFST (4) +#define BESL_OFST (0) + +//U3D_USB20_LPM_ENTRY_COUNT +#define LPM_EXIT_COUNT_OFST (16) +#define LPM_EXIT_COUNT_RESET_OFST (9) +#define LPM_ENTRY_COUNT_RESET_OFST (8) +#define LPM_ENTRY_COUNT_OFST (0) + +//U3D_USB20_MISC_CONTROL +#define LPM_U3_ACK_EN_OFST (0) + +//U3D_USB20_LPM_TIMING_PARAM +#define LPM_L1_TOKENRETRY_OFST (16) +#define LPM_L1_RESIDENCY_OFST (0) + +//U3D_USB20_OPSTATE +#define OPSTATE_SYS_OFST (0) + +////////////////////////////////////////////////////////////////////// diff --git a/include/linux/mu3d/hal/ssusb_usb3_mac_csr_c_header.h b/include/linux/mu3d/hal/ssusb_usb3_mac_csr_c_header.h new file mode 100644 index 000000000..ad7dcd187 --- /dev/null +++ b/include/linux/mu3d/hal/ssusb_usb3_mac_csr_c_header.h @@ -0,0 +1,423 @@ +/* SSUSB_USB3_MAC_CSR REGISTER DEFINITION */ + +#define U3D_TS_CONFIG (SSUSB_USB3_MAC_CSR_BASE+0x0000) +#define U3D_PIPE (SSUSB_USB3_MAC_CSR_BASE+0x0004) +#define U3D_LTSSM_PARAMETER (SSUSB_USB3_MAC_CSR_BASE+0x000C) +#define U3D_LTSSM_CTRL (SSUSB_USB3_MAC_CSR_BASE+0x0010) +#define U3D_LTSSM_INFO (SSUSB_USB3_MAC_CSR_BASE+0x0014) +#define U3D_USB3_CONFIG (SSUSB_USB3_MAC_CSR_BASE+0x001C) +#define U3D_USB3_U1_STATE_INFO (SSUSB_USB3_MAC_CSR_BASE+0x0050) +#define U3D_USB3_U2_STATE_INFO (SSUSB_USB3_MAC_CSR_BASE+0x0054) +#define U3D_UX_LFPS_TIMING_PARAMETER (SSUSB_USB3_MAC_CSR_BASE+0x007C) +#define U3D_U1_LFPS_TIMING_PARAMETER_2 (SSUSB_USB3_MAC_CSR_BASE+0x0080) +#define U3D_U2_LB_LFPS_TIMING_PARAMETER_1 (SSUSB_USB3_MAC_CSR_BASE+0x0084) +#define U3D_U2_LB_LFPS_TIMING_PARAMETER_2 (SSUSB_USB3_MAC_CSR_BASE+0x0088) +#define U3D_U3_LFPS_TIMING_PARAMETER_1 (SSUSB_USB3_MAC_CSR_BASE+0x008C) +#define U3D_U3_LFPS_TIMING_PARAMETER_2 (SSUSB_USB3_MAC_CSR_BASE+0x0090) +#define U3D_PING_LFPS_TIMING_PARAMETER (SSUSB_USB3_MAC_CSR_BASE+0x0094) +#define U3D_POLLING_LFPS_TIMING_PARAMETER_1 (SSUSB_USB3_MAC_CSR_BASE+0x0098) +#define U3D_POLLING_LFPS_TIMING_PARAMETER_2 (SSUSB_USB3_MAC_CSR_BASE+0x009C) +#define U3D_UX_EXIT_LFPS_TIMING_PARAMETER (SSUSB_USB3_MAC_CSR_BASE+0x00A0) +#define U3D_P3_TIMING_PARAMETER (SSUSB_USB3_MAC_CSR_BASE+0x00A4) +#define U3D_WARM_RESET_TIMING_PARAMETER (SSUSB_USB3_MAC_CSR_BASE+0x00A8) +#define U3D_UX_EXIT_TIMING_PARAMETER (SSUSB_USB3_MAC_CSR_BASE+0x00AC) +#define U3D_REF_CK_PARAMETER (SSUSB_USB3_MAC_CSR_BASE+0x00B0) +#define U3D_LTSSM_TIMING_PARAMETER_1 (SSUSB_USB3_MAC_CSR_BASE+0x010C) +#define U3D_LTSSM_TIMING_PARAMETER_2 (SSUSB_USB3_MAC_CSR_BASE+0x0110) +#define U3D_LTSSM_TIMING_PARAMETER_3 (SSUSB_USB3_MAC_CSR_BASE+0x0114) +#define U3D_LTSSM_TIMING_PARAMETER_4 (SSUSB_USB3_MAC_CSR_BASE+0x0118) +#define U3D_LTSSM_TIMING_PARAMETER_5 (SSUSB_USB3_MAC_CSR_BASE+0x011C) +#define U3D_LTSSM_RXDETECT_CTRL (SSUSB_USB3_MAC_CSR_BASE+0x0120) +#define U3D_PIPE_RXDATA_ERR_INTR_ENABLE (SSUSB_USB3_MAC_CSR_BASE+0x0128) +#define U3D_PIPE_RXDATA_ERR_INTR (SSUSB_USB3_MAC_CSR_BASE+0x012C) +#define U3D_PIPE_LATCH_SELECT (SSUSB_USB3_MAC_CSR_BASE+0x0130) +#define U3D_LINK_STATE_MACHINE (SSUSB_USB3_MAC_CSR_BASE+0x0134) +#define U3D_MAC_FAST_SIMULATION (SSUSB_USB3_MAC_CSR_BASE+0x0138) +#define U3D_LTSSM_INTR_ENABLE (SSUSB_USB3_MAC_CSR_BASE+0x013C) +#define U3D_LTSSM_INTR (SSUSB_USB3_MAC_CSR_BASE+0x0140) +#define U3D_SKP_CNT (SSUSB_USB3_MAC_CSR_BASE+0x0148) + +/* SSUSB_USB3_MAC_CSR FIELD DEFINITION */ + +//U3D_TS_CONFIG +#define TS_CONFIG_DISABLE_SCRAMBLING (0x1<<0) //0:0 + +//U3D_PIPE +#define CP_TXDEEMPH_WITHOUT (0x3<<6) //7:6 +#define CP_TXDEEMPH_WITH (0x3<<4) //5:4 +#define CP_TXDEEMPH (0x3<<2) //3:2 +#define PIPE_TXDEEMPH (0x3<<0) //1:0 + +//U3D_LTSSM_PARAMETER +#define DISABLE_NUM (0xf<<24) //27:24 +#define RXDETECT_NUM (0x1f<<16) //20:16 +#define TX_TSEQ_NUM (0xffff<<0) //15:0 + +//U3D_LTSSM_CTRL +#define FORCE_POLLING_FAIL (0x1<<4) //4:4 +#define FORCE_RXDETECT_FAIL (0x1<<3) //3:3 +#define SOFT_U3_EXIT_EN (0x1<<2) //2:2 +#define COMPLIANCE_EN (0x1<<1) //1:1 +#define U1_GO_U2_EN (0x1<<0) //0:0 + +//U3D_LTSSM_INFO +#define CLR_PWR_CHG_TMOUT_FLAG (0x1<<26) //26:26 +#define CLR_DISABLE_CNT (0x1<<25) //25:25 +#define CLR_RXDETECT_CNT (0x1<<24) //24:24 +#define PWR_CHG_TMOUT_FLAG (0x1<<16) //16:16 +#define DISABLE_CNT (0xf<<8) //11:8 +#define RXDETECT_CNT (0x1f<<0) //4:0 + +//U3D_USB3_CONFIG +#define USB3_EN (0x1<<0) //0:0 + +//U3D_USB3_U1_STATE_INFO +#define CLR_USB3_U1_CNT (0x1<<16) //16:16 +#define USB3_U1_CNT (0xffff<<0) //15:0 + +//U3D_USB3_U2_STATE_INFO +#define CLR_USB3_U2_CNT (0x1<<16) //16:16 +#define USB3_U2_CNT (0xffff<<0) //15:0 + +//U3D_UX_LFPS_TIMING_PARAMETER +#define UX_EXIT_T12_T11_MINUS_300NS (0xff<<0) //7:0 + +//U3D_U1_LFPS_TIMING_PARAMETER_2 +#define U1_EXIT_NO_LFPS_TMOUT (0xfff<<16) //27:16 +#define U1_EXIT_T13_T11 (0xff<<8) //15:8 +#define U1_EXIT_T12_T10 (0xff<<0) //7:0 + +//U3D_U2_LB_LFPS_TIMING_PARAMETER_1 +#define U2_LB_EXIT_T13_T11 (0xfff<<16) //27:16 +#define U2_LB_EXIT_T12_T10 (0xfff<<0) //11:0 + +//U3D_U2_LB_LFPS_TIMING_PARAMETER_2 +#define U2_LB_EXIT_NO_LFPS_TMOUT (0xfff<<0) //11:0 + +//U3D_U3_LFPS_TIMING_PARAMETER_1 +#define U3_EXIT_T13_T11 (0x3fff<<16) //29:16 +#define U3_EXIT_T12_T10 (0x3fff<<0) //13:0 + +//U3D_U3_LFPS_TIMING_PARAMETER_2 +#define SEND_U3_EXIT_LFPS_WAIT_CYCLE (0xff<<16) //23:16 +#define U3_EXIT_NO_LFPS_TMOUT (0x3fff<<0) //13:0 + +//U3D_PING_LFPS_TIMING_PARAMETER +#define TX_PING_LFPS_TBURST (0x3f<<16) //21:16 +#define RX_PING_LFPS_TBURST_MAX (0x3f<<8) //13:8 +#define RX_PING_LFPS_TBURST_MIN (0xf<<0) //3:0 + +//U3D_POLLING_LFPS_TIMING_PARAMETER_1 +#define RX_POLLING_LFPS_TBURST_MAX (0xff<<8) //15:8 +#define RX_POLLING_LFPS_TBURST_MIN (0x7f<<0) //6:0 + +//U3D_POLLING_LFPS_TIMING_PARAMETER_2 +#define TX_POLLING_LFPS_NUM (0x1f<<16) //20:16 +#define TX_POLLING_LFPS_TREPEAT (0xf<<8) //11:8 +#define TX_POLLING_LFPS_TBURST (0xff<<0) //7:0 + +//U3D_UX_EXIT_LFPS_TIMING_PARAMETER +#define RX_UX_EXIT_LFPS_REF (0xff<<8) //15:8 +#define RX_UX_EXIT_LFPS_PIPE (0xff<<0) //7:0 + +//U3D_P3_TIMING_PARAMETER +#define P3_ENTER_CYCLE (0xf<<20) //23:20 +#define P3_EXIT_CYCLE (0xf<<16) //19:16 + +//U3D_WARM_RESET_TIMING_PARAMETER +#define TRESET_TBURST (0xff<<8) //15:8 +#define TRESETDELAY (0x3f<<0) //5:0 + +//U3D_UX_EXIT_TIMING_PARAMETER +#define UX_EXIT_TIMER (0xfffff<<0) //19:0 + +//U3D_REF_CK_PARAMETER +#define REF_1000NS (0xff<<0) //7:0 + +//U3D_LTSSM_TIMING_PARAMETER_1 +#define MAC_6MS (0xf<<16) //19:16 +#define MAC_2MS (0xff<<0) //7:0 + +//U3D_LTSSM_TIMING_PARAMETER_2 +#define MAC_100MS (0xff<<16) //23:16 +#define MAC_12MS (0x1f<<0) //4:0 + +//U3D_LTSSM_TIMING_PARAMETER_3 +#define MAC_360MS (0x3ff<<16) //25:16 +#define MAC_300MS (0x3ff<<0) //9:0 + +//U3D_LTSSM_TIMING_PARAMETER_4 +#define MAC_200MS (0xff<<0) //7:0 + +//U3D_LTSSM_TIMING_PARAMETER_5 +#define POWER_CHANGE_TIMEOUT_VALUE (0x3ff<<16) //25:16 +#define RXDETECT_TIMEOUT_VALUE (0x3ff<<0) //9:0 + +//U3D_LTSSM_RXDETECT_CTRL +#define RXDETECT_WAIT_TIME (0xff<<8) //15:8 +#define RXDETECT_WAIT_EN (0x1<<0) //0:0 + +//U3D_PIPE_RXDATA_ERR_INTR_ENABLE +#define DEC_8B10B_ERR_INTR_EN (0x1<<2) //2:2 +#define DISPARITY_ERR_INTR_EN (0x1<<1) //1:1 +#define EBUF_ERR_INTR_EN (0x1<<0) //0:0 + +//U3D_PIPE_RXDATA_ERR_INTR +#define DEC_8B10B_ERR_INTR (0x1<<2) //2:2 +#define DISPARITY_ERR_INTR (0x1<<1) //1:1 +#define EBUF_ERR_INTR (0x1<<0) //0:0 + +//U3D_PIPE_LATCH_SELECT +#define TX_SIGNAL_SEL (0x3<<2) //3:2 +#define RX_SIGNAL_SEL (0x3<<0) //1:0 + +//U3D_LINK_STATE_MACHINE +#define VBUS_DBC_CYCLE (0xffff<<16) //31:16 +#define VBUS_VALID (0x1<<8) //8:8 +#define LTSSM (0x1f<<0) //4:0 + +//U3D_MAC_FAST_SIMULATION +#define FORCE_U0_TO_U3 (0x1<<5) //5:5 +#define FORCE_U0_TO_U2 (0x1<<4) //4:4 +#define FORCE_U0_TO_U1 (0x1<<3) //3:3 +#define MAC_SPEED_MS_TO_US (0x1<<2) //2:2 +#define BYPASS_WARM_RESET (0x1<<1) //1:1 + +//U3D_LTSSM_INTR_ENABLE +#define U3_RESUME_INTR_EN (0x1<<18) //18:18 +#define U3_LFPS_TMOUT_INTR_EN (0x1<<17) //17:17 +#define VBUS_FALL_INTR_EN (0x1<<16) //16:16 +#define VBUS_RISE_INTR_EN (0x1<<15) //15:15 +#define RXDET_SUCCESS_INTR_EN (0x1<<14) //14:14 +#define EXIT_U3_INTR_EN (0x1<<13) //13:13 +#define EXIT_U2_INTR_EN (0x1<<12) //12:12 +#define EXIT_U1_INTR_EN (0x1<<11) //11:11 +#define ENTER_U3_INTR_EN (0x1<<10) //10:10 +#define ENTER_U2_INTR_EN (0x1<<9) //9:9 +#define ENTER_U1_INTR_EN (0x1<<8) //8:8 +#define ENTER_U0_INTR_EN (0x1<<7) //7:7 +#define RECOVERY_INTR_EN (0x1<<6) //6:6 +#define WARM_RST_INTR_EN (0x1<<5) //5:5 +#define HOT_RST_INTR_EN (0x1<<4) //4:4 +#define LOOPBACK_INTR_EN (0x1<<3) //3:3 +#define COMPLIANCE_INTR_EN (0x1<<2) //2:2 +#define SS_DISABLE_INTR_EN (0x1<<1) //1:1 +#define SS_INACTIVE_INTR_EN (0x1<<0) //0:0 + +//U3D_LTSSM_INTR +#define U3_RESUME_INTR (0x1<<18) //18:18 +#define U3_LFPS_TMOUT_INTR (0x1<<17) //17:17 +#define VBUS_FALL_INTR (0x1<<16) //16:16 +#define VBUS_RISE_INTR (0x1<<15) //15:15 +#define RXDET_SUCCESS_INTR (0x1<<14) //14:14 +#define EXIT_U3_INTR (0x1<<13) //13:13 +#define EXIT_U2_INTR (0x1<<12) //12:12 +#define EXIT_U1_INTR (0x1<<11) //11:11 +#define ENTER_U3_INTR (0x1<<10) //10:10 +#define ENTER_U2_INTR (0x1<<9) //9:9 +#define ENTER_U1_INTR (0x1<<8) //8:8 +#define ENTER_U0_INTR (0x1<<7) //7:7 +#define RECOVERY_INTR (0x1<<6) //6:6 +#define WARM_RST_INTR (0x1<<5) //5:5 +#define HOT_RST_INTR (0x1<<4) //4:4 +#define LOOPBACK_INTR (0x1<<3) //3:3 +#define COMPLIANCE_INTR (0x1<<2) //2:2 +#define SS_DISABLE_INTR (0x1<<1) //1:1 +#define SS_INACTIVE_INTR (0x1<<0) //0:0 + +//U3D_SKP_CNT +#define SKP_SYMBOL_NUM (0x7f<<0) //6:0 + + +/* SSUSB_USB3_MAC_CSR FIELD OFFSET DEFINITION */ + +//U3D_TS_CONFIG +#define TS_CONFIG_DISABLE_SCRAMBLING_OFST (0) + +//U3D_PIPE +#define CP_TXDEEMPH_WITHOUT_OFST (6) +#define CP_TXDEEMPH_WITH_OFST (4) +#define CP_TXDEEMPH_OFST (2) +#define PIPE_TXDEEMPH_OFST (0) + +//U3D_LTSSM_PARAMETER +#define DISABLE_NUM_OFST (24) +#define RXDETECT_NUM_OFST (16) +#define TX_TSEQ_NUM_OFST (0) + +//U3D_LTSSM_CTRL +#define FORCE_POLLING_FAIL_OFST (4) +#define FORCE_RXDETECT_FAIL_OFST (3) +#define SOFT_U3_EXIT_EN_OFST (2) +#define COMPLIANCE_EN_OFST (1) +#define U1_GO_U2_EN_OFST (0) + +//U3D_LTSSM_INFO +#define CLR_PWR_CHG_TMOUT_FLAG_OFST (26) +#define CLR_DISABLE_CNT_OFST (25) +#define CLR_RXDETECT_CNT_OFST (24) +#define PWR_CHG_TMOUT_FLAG_OFST (16) +#define DISABLE_CNT_OFST (8) +#define RXDETECT_CNT_OFST (0) + +//U3D_USB3_CONFIG +#define USB3_EN_OFST (0) + +//U3D_USB3_U1_STATE_INFO +#define CLR_USB3_U1_CNT_OFST (16) +#define USB3_U1_CNT_OFST (0) + +//U3D_USB3_U2_STATE_INFO +#define CLR_USB3_U2_CNT_OFST (16) +#define USB3_U2_CNT_OFST (0) + +//U3D_UX_LFPS_TIMING_PARAMETER +#define UX_EXIT_T12_T11_MINUS_300NS_OFST (0) + +//U3D_U1_LFPS_TIMING_PARAMETER_2 +#define U1_EXIT_NO_LFPS_TMOUT_OFST (16) +#define U1_EXIT_T13_T11_OFST (8) +#define U1_EXIT_T12_T10_OFST (0) + +//U3D_U2_LB_LFPS_TIMING_PARAMETER_1 +#define U2_LB_EXIT_T13_T11_OFST (16) +#define U2_LB_EXIT_T12_T10_OFST (0) + +//U3D_U2_LB_LFPS_TIMING_PARAMETER_2 +#define U2_LB_EXIT_NO_LFPS_TMOUT_OFST (0) + +//U3D_U3_LFPS_TIMING_PARAMETER_1 +#define U3_EXIT_T13_T11_OFST (16) +#define U3_EXIT_T12_T10_OFST (0) + +//U3D_U3_LFPS_TIMING_PARAMETER_2 +#define SEND_U3_EXIT_LFPS_WAIT_CYCLE_OFST (16) +#define U3_EXIT_NO_LFPS_TMOUT_OFST (0) + +//U3D_PING_LFPS_TIMING_PARAMETER +#define TX_PING_LFPS_TBURST_OFST (16) +#define RX_PING_LFPS_TBURST_MAX_OFST (8) +#define RX_PING_LFPS_TBURST_MIN_OFST (0) + +//U3D_POLLING_LFPS_TIMING_PARAMETER_1 +#define RX_POLLING_LFPS_TBURST_MAX_OFST (8) +#define RX_POLLING_LFPS_TBURST_MIN_OFST (0) + +//U3D_POLLING_LFPS_TIMING_PARAMETER_2 +#define TX_POLLING_LFPS_NUM_OFST (16) +#define TX_POLLING_LFPS_TREPEAT_OFST (8) +#define TX_POLLING_LFPS_TBURST_OFST (0) + +//U3D_UX_EXIT_LFPS_TIMING_PARAMETER +#define RX_UX_EXIT_LFPS_REF_OFST (8) +#define RX_UX_EXIT_LFPS_PIPE_OFST (0) + +//U3D_P3_TIMING_PARAMETER +#define P3_ENTER_CYCLE_OFST (20) +#define P3_EXIT_CYCLE_OFST (16) + +//U3D_WARM_RESET_TIMING_PARAMETER +#define TRESET_TBURST_OFST (8) +#define TRESETDELAY_OFST (0) + +//U3D_UX_EXIT_TIMING_PARAMETER +#define UX_EXIT_TIMER_OFST (0) + +//U3D_REF_CK_PARAMETER +#define REF_1000NS_OFST (0) + +//U3D_LTSSM_TIMING_PARAMETER_1 +#define MAC_6MS_OFST (16) +#define MAC_2MS_OFST (0) + +//U3D_LTSSM_TIMING_PARAMETER_2 +#define MAC_100MS_OFST (16) +#define MAC_12MS_OFST (0) + +//U3D_LTSSM_TIMING_PARAMETER_3 +#define MAC_360MS_OFST (16) +#define MAC_300MS_OFST (0) + +//U3D_LTSSM_TIMING_PARAMETER_4 +#define MAC_200MS_OFST (0) + +//U3D_LTSSM_TIMING_PARAMETER_5 +#define POWER_CHANGE_TIMEOUT_VALUE_OFST (16) +#define RXDETECT_TIMEOUT_VALUE_OFST (0) + +//U3D_LTSSM_RXDETECT_CTRL +#define RXDETECT_WAIT_TIME_OFST (8) +#define RXDETECT_WAIT_EN_OFST (0) + +//U3D_PIPE_RXDATA_ERR_INTR_ENABLE +#define DEC_8B10B_ERR_INTR_EN_OFST (2) +#define DISPARITY_ERR_INTR_EN_OFST (1) +#define EBUF_ERR_INTR_EN_OFST (0) + +//U3D_PIPE_RXDATA_ERR_INTR +#define DEC_8B10B_ERR_INTR_OFST (2) +#define DISPARITY_ERR_INTR_OFST (1) +#define EBUF_ERR_INTR_OFST (0) + +//U3D_PIPE_LATCH_SELECT +#define TX_SIGNAL_SEL_OFST (2) +#define RX_SIGNAL_SEL_OFST (0) + +//U3D_LINK_STATE_MACHINE +#define VBUS_DBC_CYCLE_OFST (16) +#define VBUS_VALID_OFST (8) +#define LTSSM_OFST (0) + +//U3D_MAC_FAST_SIMULATION +#define FORCE_U0_TO_U3_OFST (5) +#define FORCE_U0_TO_U2_OFST (4) +#define FORCE_U0_TO_U1_OFST (3) +#define MAC_SPEED_MS_TO_US_OFST (2) +#define BYPASS_WARM_RESET_OFST (1) + +//U3D_LTSSM_INTR_ENABLE +#define U3_RESUME_INTR_EN_OFST (18) +#define U3_LFPS_TMOUT_INTR_EN_OFST (17) +#define VBUS_FALL_INTR_EN_OFST (16) +#define VBUS_RISE_INTR_EN_OFST (15) +#define RXDET_SUCCESS_INTR_EN_OFST (14) +#define EXIT_U3_INTR_EN_OFST (13) +#define EXIT_U2_INTR_EN_OFST (12) +#define EXIT_U1_INTR_EN_OFST (11) +#define ENTER_U3_INTR_EN_OFST (10) +#define ENTER_U2_INTR_EN_OFST (9) +#define ENTER_U1_INTR_EN_OFST (8) +#define ENTER_U0_INTR_EN_OFST (7) +#define RECOVERY_INTR_EN_OFST (6) +#define WARM_RST_INTR_EN_OFST (5) +#define HOT_RST_INTR_EN_OFST (4) +#define LOOPBACK_INTR_EN_OFST (3) +#define COMPLIANCE_INTR_EN_OFST (2) +#define SS_DISABLE_INTR_EN_OFST (1) +#define SS_INACTIVE_INTR_EN_OFST (0) + +//U3D_LTSSM_INTR +#define U3_RESUME_INTR_OFST (18) +#define U3_LFPS_TMOUT_INTR_OFST (17) +#define VBUS_FALL_INTR_OFST (16) +#define VBUS_RISE_INTR_OFST (15) +#define RXDET_SUCCESS_INTR_OFST (14) +#define EXIT_U3_INTR_OFST (13) +#define EXIT_U2_INTR_OFST (12) +#define EXIT_U1_INTR_OFST (11) +#define ENTER_U3_INTR_OFST (10) +#define ENTER_U2_INTR_OFST (9) +#define ENTER_U1_INTR_OFST (8) +#define ENTER_U0_INTR_OFST (7) +#define RECOVERY_INTR_OFST (6) +#define WARM_RST_INTR_OFST (5) +#define HOT_RST_INTR_OFST (4) +#define LOOPBACK_INTR_OFST (3) +#define COMPLIANCE_INTR_OFST (2) +#define SS_DISABLE_INTR_OFST (1) +#define SS_INACTIVE_INTR_OFST (0) + +//U3D_SKP_CNT +#define SKP_SYMBOL_NUM_OFST (0) + +////////////////////////////////////////////////////////////////////// diff --git a/include/linux/mu3d/hal/ssusb_usb3_sys_csr_c_header.h b/include/linux/mu3d/hal/ssusb_usb3_sys_csr_c_header.h new file mode 100644 index 000000000..0f57e6c5a --- /dev/null +++ b/include/linux/mu3d/hal/ssusb_usb3_sys_csr_c_header.h @@ -0,0 +1,318 @@ +/* SSUSB_USB3_SYS_CSR REGISTER DEFINITION */ + +#define U3D_LINK_HP_TIMER (SSUSB_USB3_SYS_CSR_BASE+0x0200) +#define U3D_LINK_CMD_TIMER (SSUSB_USB3_SYS_CSR_BASE+0x0204) +#define U3D_LINK_PM_TIMER (SSUSB_USB3_SYS_CSR_BASE+0x0208) +#define U3D_LINK_UX_INACT_TIMER (SSUSB_USB3_SYS_CSR_BASE+0x020C) +#define U3D_LINK_POWER_CONTROL (SSUSB_USB3_SYS_CSR_BASE+0x0210) +#define U3D_LINK_ERR_COUNT (SSUSB_USB3_SYS_CSR_BASE+0x0214) +#define U3D_LTSSM_TRANSITION (SSUSB_USB3_SYS_CSR_BASE+0x0218) +#define U3D_LINK_RETRY_CTRL (SSUSB_USB3_SYS_CSR_BASE+0x0220) +#define U3D_SYS_FAST_SIMULATIION (SSUSB_USB3_SYS_CSR_BASE+0x0224) +#define U3D_LINK_CAPABILITY_CTRL (SSUSB_USB3_SYS_CSR_BASE+0x0228) +#define U3D_LINK_DEBUG_INFO (SSUSB_USB3_SYS_CSR_BASE+0x022C) +#define U3D_USB3_U1_REJECT (SSUSB_USB3_SYS_CSR_BASE+0x0240) +#define U3D_USB3_U2_REJECT (SSUSB_USB3_SYS_CSR_BASE+0x0244) +#define U3D_DEV_NOTIF_0 (SSUSB_USB3_SYS_CSR_BASE+0x0290) +#define U3D_DEV_NOTIF_1 (SSUSB_USB3_SYS_CSR_BASE+0x0294) +#define U3D_VENDOR_DEV_TEST (SSUSB_USB3_SYS_CSR_BASE+0x0298) +#define U3D_VENDOR_DEF_DATA_LOW (SSUSB_USB3_SYS_CSR_BASE+0x029C) +#define U3D_VENDOR_DEF_DATA_HIGH (SSUSB_USB3_SYS_CSR_BASE+0x02A0) +#define U3D_HOST_SET_PORT_CTRL (SSUSB_USB3_SYS_CSR_BASE+0x02A4) +#define U3D_LINK_CAP_CONTROL (SSUSB_USB3_SYS_CSR_BASE+0x02AC) +#define U3D_PORT_CONF_TIMEOUT (SSUSB_USB3_SYS_CSR_BASE+0x02B0) +#define U3D_TIMING_PULSE_CTRL (SSUSB_USB3_SYS_CSR_BASE+0x02B4) +#define U3D_ISO_TIMESTAMP (SSUSB_USB3_SYS_CSR_BASE+0x02B8) +#define U3D_RECEIVE_PKT_INTR_EN (SSUSB_USB3_SYS_CSR_BASE+0x02C0) +#define U3D_RECEIVE_PKT_INTR (SSUSB_USB3_SYS_CSR_BASE+0x02C4) +#define U3D_CRC_ERR_INTR_EN (SSUSB_USB3_SYS_CSR_BASE+0x02C8) +#define U3D_CRC_ERR_INTR (SSUSB_USB3_SYS_CSR_BASE+0x02CC) +#define U3D_PORT_STATUS_INTR_EN (SSUSB_USB3_SYS_CSR_BASE+0x02D0) +#define U3D_PORT_STATUS_INTR (SSUSB_USB3_SYS_CSR_BASE+0x02D4) +#define U3D_RECOVERY_COUNT (SSUSB_USB3_SYS_CSR_BASE+0x02D8) +#define U3D_T2R_LOOPBACK_TEST (SSUSB_USB3_SYS_CSR_BASE+0x02DC) + +/* SSUSB_USB3_SYS_CSR FIELD DEFINITION */ + +//U3D_LINK_HP_TIMER +#define CHP_TIMEOUT_VALUE (0x7f<<8) //14:8 +#define PHP_TIMEOUT_VALUE (0xf<<0) //3:0 + +//U3D_LINK_CMD_TIMER +#define NO_LC_TIMEOUT_VALUE (0xf<<8) //11:8 +#define LDN_TIMEOUT_VALUE (0xf<<4) //7:4 +#define LUP_TIMEOUT_VALUE (0xf<<0) //3:0 + +//U3D_LINK_PM_TIMER +#define LPMA_SENT_CNT_VALUE (0xf<<16) //19:16 +#define PM_ENTRY_TIMEOUT_VALUE (0xf<<8) //11:8 +#define PM_LC_TIMEOUT_VALUE (0xf<<0) //3:0 + +//U3D_LINK_UX_INACT_TIMER +#define DEV_U2_INACT_TIMEOUT_VALUE (0xff<<16) //23:16 +#define U2_INACT_TIMEOUT_VALUE (0xff<<8) //15:8 +#define U1_INACT_TIMEOUT_VALUE (0xff<<0) //7:0 + +//U3D_LINK_POWER_CONTROL +#define SW_U2_ACCEPT_ENABLE (0x1<<9) //9:9 +#define SW_U1_ACCEPT_ENABLE (0x1<<8) //8:8 +#define UX_EXIT (0x1<<5) //5:5 +#define LGO_U3 (0x1<<4) //4:4 +#define LGO_U2 (0x1<<3) //3:3 +#define LGO_U1 (0x1<<2) //2:2 +#define SW_U2_REQUEST_ENABLE (0x1<<1) //1:1 +#define SW_U1_REQUEST_ENABLE (0x1<<0) //0:0 + +//U3D_LINK_ERR_COUNT +#define CLR_LINK_ERR_CNT (0x1<<16) //16:16 +#define LINK_ERROR_COUNT (0xffff<<0) //15:0 + +//U3D_LTSSM_TRANSITION +#define GO_HOT_RESET (0x1<<3) //3:3 +#define GO_WARM_RESET (0x1<<2) //2:2 +#define GO_RXDETECT (0x1<<1) //1:1 +#define GO_SS_DISABLE (0x1<<0) //0:0 + +//U3D_LINK_RETRY_CTRL +#define TX_LRTY_DPP_EN (0x1<<0) //0:0 + +//U3D_SYS_FAST_SIMULATIION +#define SYS_SPEED_MS_TO_US (0x1<<0) //0:0 + +//U3D_LINK_CAPABILITY_CTRL +#define INSERT_CRC32_ERR_DP_NUM (0xff<<16) //23:16 +#define INSERT_CRC32_ERR_EN (0x1<<8) //8:8 +#define ZLP_CRC32_CHK_DIS (0x1<<0) //0:0 + +//U3D_LINK_DEBUG_INFO +#define CLR_TX_DATALEN_OVER_1024 (0x1<<1) //1:1 +#define TX_DATALEN_OVER_1024 (0x1<<0) //0:0 + +//U3D_USB3_U1_REJECT +#define CLR_USB3_U1_REJECT_CNT (0x1<<16) //16:16 +#define USB3_U1_REJECT_CNT (0xffff<<0) //15:0 + +//U3D_USB3_U2_REJECT +#define CLR_USB3_U2_REJECT_CNT (0x1<<16) //16:16 +#define USB3_U2_REJECT_CNT (0xffff<<0) //15:0 + +//U3D_DEV_NOTIF_0 +#define DEV_NOTIF_TYPE_SPECIFIC_LOW (0xffffff<<8) //31:8 +#define DEV_NOTIF_TYPE (0xf<<4) //7:4 +#define SEND_DEV_NOTIF (0x1<<0) //0:0 + +//U3D_DEV_NOTIF_1 +#define DEV_NOTIF_TYPE_SPECIFIC_HIGH (0xffffffff<<0) //31:0 + +//U3D_VENDOR_DEV_TEST +#define VENDOR_DEV_TEST_VALUE (0xff<<16) //23:16 +#define SEND_VENDOR_DEV_TEST (0x1<<0) //0:0 + +//U3D_VENDOR_DEF_DATA_LOW +#define VENDOR_DEF_DATA_LOW (0xffffffff<<0) //31:0 + +//U3D_VENDOR_DEF_DATA_HIGH +#define VENDOR_DEF_DATA_HIGH (0xffffffff<<0) //31:0 + +//U3D_HOST_SET_PORT_CTRL +#define SEND_U2_INACT_TIMEOUT (0x1<<2) //2:2 +#define FORCE_LINK_PM_ACPT (0x1<<1) //1:1 +#define SEND_SET_LINK_FUNC (0x1<<0) //0:0 + +//U3D_LINK_CAP_CONTROL +#define TIEBREAKER (0xf<<16) //19:16 +#define NUM_HP_BUF (0xff<<8) //15:8 +#define LINK_SPEED (0xff<<0) //7:0 + +//U3D_PORT_CONF_TIMEOUT +#define TPORT_CONF_TIMEOUT_VALUE (0x1f<<0) //4:0 + +//U3D_TIMING_PULSE_CTRL +#define CNT_1MS_VALUE (0xf<<28) //31:28 +#define CNT_100US_VALUE (0xf<<24) //27:24 +#define CNT_10US_VALUE (0xf<<20) //23:20 +#define CNT_1US_VALUE (0xff<<0) //7:0 + +//U3D_ISO_TIMESTAMP +#define ISO_TIMESTAMP (0x7ffffff<<0) //26:0 + +//U3D_RECEIVE_PKT_INTR_EN +#define RECV_SET_LINK_FUNC_INTR_EN (0x1<<2) //2:2 +#define RECV_U2_INACT_INTR_EN (0x1<<1) //1:1 +#define RECV_ITP_INTR_EN (0x1<<0) //0:0 + +//U3D_RECEIVE_PKT_INTR +#define RECV_SET_LINK_FUNC_INTR (0x1<<2) //2:2 +#define RECV_U2_INACT_INTR (0x1<<1) //1:1 +#define RECV_ITP_INTR (0x1<<0) //0:0 + +//U3D_CRC_ERR_INTR_EN +#define CRC16_ERR_INTR_EN (0x1<<2) //2:2 +#define CRC5_ERR_INTR_EN (0x1<<1) //1:1 +#define CRC32_ERR_INTR_EN (0x1<<0) //0:0 + +//U3D_CRC_ERR_INTR +#define CRC16_ERR_INTR (0x1<<2) //2:2 +#define CRC5_ERR_INTR (0x1<<1) //1:1 +#define CRC32_ERR_INTR (0x1<<0) //0:0 + +//U3D_PORT_STATUS_INTR_EN +#define LMP_ADV_ERR_INTR_EN (0x1<<2) //2:2 +#define LMP_ADV_DONE_INTR_EN (0x1<<1) //1:1 +#define LINK_ADV_DONE_INTR_EN (0x1<<0) //0:0 + +//U3D_PORT_STATUS_INTR +#define LMP_ADV_ERR_INTR (0x1<<2) //2:2 +#define LMP_ADV_DONE_INTR (0x1<<1) //1:1 +#define LINK_ADV_DONE_INTR (0x1<<0) //0:0 + +//U3D_RECOVERY_COUNT +#define CLR_RECOV_CNT (0x1<<16) //16:16 +#define RECOV_CNT (0xffff<<0) //15:0 + +//U3D_T2R_LOOPBACK_TEST +#define T2R_LOOPBACK (0x1<<0) //0:0 + + +/* SSUSB_USB3_SYS_CSR FIELD OFFSET DEFINITION */ + +//U3D_LINK_HP_TIMER +#define CHP_TIMEOUT_VALUE_OFST (8) +#define PHP_TIMEOUT_VALUE_OFST (0) + +//U3D_LINK_CMD_TIMER +#define NO_LC_TIMEOUT_VALUE_OFST (8) +#define LDN_TIMEOUT_VALUE_OFST (4) +#define LUP_TIMEOUT_VALUE_OFST (0) + +//U3D_LINK_PM_TIMER +#define LPMA_SENT_CNT_VALUE_OFST (16) +#define PM_ENTRY_TIMEOUT_VALUE_OFST (8) +#define PM_LC_TIMEOUT_VALUE_OFST (0) + +//U3D_LINK_UX_INACT_TIMER +#define DEV_U2_INACT_TIMEOUT_VALUE_OFST (16) +#define U2_INACT_TIMEOUT_VALUE_OFST (8) +#define U1_INACT_TIMEOUT_VALUE_OFST (0) + +//U3D_LINK_POWER_CONTROL +#define SW_U2_ACCEPT_ENABLE_OFST (9) +#define SW_U1_ACCEPT_ENABLE_OFST (8) +#define UX_EXIT_OFST (5) +#define LGO_U3_OFST (4) +#define LGO_U2_OFST (3) +#define LGO_U1_OFST (2) +#define SW_U2_REQUEST_ENABLE_OFST (1) +#define SW_U1_REQUEST_ENABLE_OFST (0) + +//U3D_LINK_ERR_COUNT +#define CLR_LINK_ERR_CNT_OFST (16) +#define LINK_ERROR_COUNT_OFST (0) + +//U3D_LTSSM_TRANSITION +#define GO_HOT_RESET_OFST (3) +#define GO_WARM_RESET_OFST (2) +#define GO_RXDETECT_OFST (1) +#define GO_SS_DISABLE_OFST (0) + +//U3D_LINK_RETRY_CTRL +#define TX_LRTY_DPP_EN_OFST (0) + +//U3D_SYS_FAST_SIMULATIION +#define SYS_SPEED_MS_TO_US_OFST (0) + +//U3D_LINK_CAPABILITY_CTRL +#define INSERT_CRC32_ERR_DP_NUM_OFST (16) +#define INSERT_CRC32_ERR_EN_OFST (8) +#define ZLP_CRC32_CHK_DIS_OFST (0) + +//U3D_LINK_DEBUG_INFO +#define CLR_TX_DATALEN_OVER_1024_OFST (1) +#define TX_DATALEN_OVER_1024_OFST (0) + +//U3D_USB3_U1_REJECT +#define CLR_USB3_U1_REJECT_CNT_OFST (16) +#define USB3_U1_REJECT_CNT_OFST (0) + +//U3D_USB3_U2_REJECT +#define CLR_USB3_U2_REJECT_CNT_OFST (16) +#define USB3_U2_REJECT_CNT_OFST (0) + +//U3D_DEV_NOTIF_0 +#define DEV_NOTIF_TYPE_SPECIFIC_LOW_OFST (8) +#define DEV_NOTIF_TYPE_OFST (4) +#define SEND_DEV_NOTIF_OFST (0) + +//U3D_DEV_NOTIF_1 +#define DEV_NOTIF_TYPE_SPECIFIC_HIGH_OFST (0) + +//U3D_VENDOR_DEV_TEST +#define VENDOR_DEV_TEST_VALUE_OFST (16) +#define SEND_VENDOR_DEV_TEST_OFST (0) + +//U3D_VENDOR_DEF_DATA_LOW +#define VENDOR_DEF_DATA_LOW_OFST (0) + +//U3D_VENDOR_DEF_DATA_HIGH +#define VENDOR_DEF_DATA_HIGH_OFST (0) + +//U3D_HOST_SET_PORT_CTRL +#define SEND_U2_INACT_TIMEOUT_OFST (2) +#define FORCE_LINK_PM_ACPT_OFST (1) +#define SEND_SET_LINK_FUNC_OFST (0) + +//U3D_LINK_CAP_CONTROL +#define TIEBREAKER_OFST (16) +#define NUM_HP_BUF_OFST (8) +#define LINK_SPEED_OFST (0) + +//U3D_PORT_CONF_TIMEOUT +#define TPORT_CONF_TIMEOUT_VALUE_OFST (0) + +//U3D_TIMING_PULSE_CTRL +#define CNT_1MS_VALUE_OFST (28) +#define CNT_100US_VALUE_OFST (24) +#define CNT_10US_VALUE_OFST (20) +#define CNT_1US_VALUE_OFST (0) + +//U3D_ISO_TIMESTAMP +#define ISO_TIMESTAMP_OFST (0) + +//U3D_RECEIVE_PKT_INTR_EN +#define RECV_SET_LINK_FUNC_INTR_EN_OFST (2) +#define RECV_U2_INACT_INTR_EN_OFST (1) +#define RECV_ITP_INTR_EN_OFST (0) + +//U3D_RECEIVE_PKT_INTR +#define RECV_SET_LINK_FUNC_INTR_OFST (2) +#define RECV_U2_INACT_INTR_OFST (1) +#define RECV_ITP_INTR_OFST (0) + +//U3D_CRC_ERR_INTR_EN +#define CRC16_ERR_INTR_EN_OFST (2) +#define CRC5_ERR_INTR_EN_OFST (1) +#define CRC32_ERR_INTR_EN_OFST (0) + +//U3D_CRC_ERR_INTR +#define CRC16_ERR_INTR_OFST (2) +#define CRC5_ERR_INTR_OFST (1) +#define CRC32_ERR_INTR_OFST (0) + +//U3D_PORT_STATUS_INTR_EN +#define LMP_ADV_ERR_INTR_EN_OFST (2) +#define LMP_ADV_DONE_INTR_EN_OFST (1) +#define LINK_ADV_DONE_INTR_EN_OFST (0) + +//U3D_PORT_STATUS_INTR +#define LMP_ADV_ERR_INTR_OFST (2) +#define LMP_ADV_DONE_INTR_OFST (1) +#define LINK_ADV_DONE_INTR_OFST (0) + +//U3D_RECOVERY_COUNT +#define CLR_RECOV_CNT_OFST (16) +#define RECOV_CNT_OFST (0) + +//U3D_T2R_LOOPBACK_TEST +#define T2R_LOOPBACK_OFST (0) + +////////////////////////////////////////////////////////////////////// diff --git a/include/linux/mu3d/test_drv/mu3d_test_qmu_drv.h b/include/linux/mu3d/test_drv/mu3d_test_qmu_drv.h new file mode 100644 index 000000000..66549b549 --- /dev/null +++ b/include/linux/mu3d/test_drv/mu3d_test_qmu_drv.h @@ -0,0 +1,52 @@ +#ifndef DDR_QMU_H +#define DDR_QMU_H + +#include <linux/mu3d/test_drv/mu3d_test_usb_drv.h> +#include <linux/mu3d/hal/mu3d_hal_osal.h> +#include <linux/mu3d/hal/mu3d_hal_hw.h> + + +#undef EXTERN + +#ifdef _QMU_DRV_EXT_ +#define EXTERN +#else +#define EXTERN extern +#endif + +EXTERN DEV_INT8 cfg_rx_zlp_en; +EXTERN DEV_INT8 cfg_rx_coz_en; +EXTERN DEV_INT8 g_run_stress; +EXTERN DEV_INT8 g_insert_hwo; +EXTERN DEV_UINT32 rx_done_count; +EXTERN DEV_UINT32 rx_IOC_count; + + + +EXTERN void mu3d_hal_alloc_qmu_mem(void); +EXTERN void mu3d_hal_init_qmu(void); +EXTERN void dev_QMURX(DEV_INT32 ep_rx); +EXTERN DEV_UINT8 dev_ep_reset(void); +EXTERN void dev_set_dma_busrt_limiter(DEV_INT8 busrt,DEV_INT8 limiter); +EXTERN void dev_tx_rx(DEV_INT32 ep_rx,DEV_INT32 ep_tx); +EXTERN void dev_qmu_loopback(DEV_INT32 ep_rx,DEV_INT32 ep_tx); +EXTERN void dev_qmu_loopback_ext(DEV_INT32 ep_rx,DEV_INT32 ep_tx); +EXTERN void dev_notification(DEV_INT8 type,DEV_INT32 valuel,DEV_INT32 valueh); +EXTERN irqreturn_t u3d_vbus_rise_handler(int irq, void *dev_id); +EXTERN irqreturn_t u3d_vbus_fall_handler(int irq, void *dev_id); +EXTERN irqreturn_t u3d_inter_handler(int irq, void *dev_id); +EXTERN void dev_start_stress(USB_DIR dir,DEV_INT32 ep_num); +EXTERN void dev_prepare_gpd(DEV_INT32 num,USB_DIR dir,DEV_INT32 ep_num,DEV_UINT8* buf); +EXTERN void dev_prepare_gpd_short(DEV_INT32 num,USB_DIR dir,DEV_INT32 ep_num,DEV_UINT8* buf); +EXTERN void dev_prepare_stress_gpd(DEV_INT32 num,USB_DIR dir,DEV_INT32 ep_num,DEV_UINT8* buf); +EXTERN void mu3d_hal_restart_qmu_no_flush(DEV_INT32 Q_num, USB_DIR dir, DEV_INT8 method); +EXTERN void dev_qmu_rx(DEV_INT32 ep_rx); +EXTERN void insert_stress_gpd(DEV_INT32 ep_num,USB_DIR dir, dma_addr_t buf, DEV_UINT32 count, DEV_UINT8 isHWO, DEV_UINT8 IOC); +EXTERN void dev_insert_stress_gpd_hwo(USB_DIR dir,DEV_INT32 ep_num); +EXTERN void dev_lpm_config(LPM_INFO *lpm_info); +EXTERN void dev_otg(DEV_UINT8 mode); + +#undef EXTERN + + +#endif diff --git a/include/linux/mu3d/test_drv/mu3d_test_test.h b/include/linux/mu3d/test_drv/mu3d_test_test.h new file mode 100644 index 000000000..65fabf00b --- /dev/null +++ b/include/linux/mu3d/test_drv/mu3d_test_test.h @@ -0,0 +1,5 @@ + +#define MU3D_MTK_TEST_MAJOR 234 +#define DEVICE_NAME "cli" + + diff --git a/include/linux/mu3d/test_drv/mu3d_test_unified.h b/include/linux/mu3d/test_drv/mu3d_test_unified.h new file mode 100644 index 000000000..c3e4b842c --- /dev/null +++ b/include/linux/mu3d/test_drv/mu3d_test_unified.h @@ -0,0 +1,37 @@ + +#ifndef _USB_UNIFIED_H_ +#define _USB_UNIFIED_H_ + +#include <linux/types.h> +#include <linux/mu3d/hal/mu3d_hal_comm.h> + + +#undef EXTERN + +#ifdef _USB_UNIFIED_H_ +#define EXTERN +#else +#define EXTERN extern +#endif + + +EXTERN DEV_INT32 TS_AUTO_TEST(DEV_INT32 argc, DEV_INT8** argv); +EXTERN DEV_INT32 TS_AUTO_TEST_STOP(DEV_INT32 argc, DEV_INT8** argv); +EXTERN DEV_INT32 u3init(int argc, char**argv); +EXTERN DEV_INT32 u3r(DEV_INT32 argc, DEV_INT8**argv); +EXTERN DEV_INT32 u3w(DEV_INT32 argc, DEV_INT8**argv); +EXTERN DEV_INT32 U3D_Phy_Cfg_Cmd(DEV_INT32 argc, DEV_INT8 **argv); +EXTERN DEV_INT32 u3d_linkup(DEV_INT32 argc, DEV_INT8 **argv); +EXTERN DEV_INT32 dbg_phy_eyeinit(int argc, char** argv); +EXTERN DEV_INT32 dbg_phy_eyescan(int argc, char** argv); + +EXTERN void sram_write(DEV_UINT32 mode, DEV_UINT32 addr, DEV_UINT32 data); +EXTERN DEV_UINT32 sram_read(DEV_UINT32 mode, DEV_UINT32 addr); +EXTERN void sram_dbg(void); + +EXTERN DEV_INT32 otg_top(int argc, char** argv); + + +#undef EXTERN + +#endif diff --git a/include/linux/mu3d/test_drv/mu3d_test_usb_drv.h b/include/linux/mu3d/test_drv/mu3d_test_usb_drv.h new file mode 100644 index 000000000..f198355ba --- /dev/null +++ b/include/linux/mu3d/test_drv/mu3d_test_usb_drv.h @@ -0,0 +1,336 @@ + +#ifndef DEV_USB_DRV_H +#define DEV_USB_DRV_H + +#include <linux/mu3d/hal/mu3d_hal_hw.h> +#include <linux/mu3d/hal/mu3d_hal_usb_drv.h> +#include <linux/mu3phy/mtk-phy.h> + + + +#undef EXTERN + +#ifdef _DEV_USB_DRV_EXT_ +#define EXTERN +#else +#define EXTERN extern +#endif + + + + + /* + * USB recipients + */ + +#define USB_RECIP_MASK 0x03 +#define USB_RECIP_DEVICE 0x00 +#define USB_RECIP_INTERFACE 0x01 +#define USB_RECIP_ENDPOINT 0x02 +#define USB_RECIP_OTHER 0x03 + + +struct USB_TRANSFER { + DEV_UINT8 type; + DEV_UINT8 speed; + DEV_UINT32 length; + DEV_UINT16 maxp; + DEV_UINT8 state; + DEV_UINT8 status; +}; + + +#define ENDPOINT_HALT 0x00 + +#define AT_CMD_ACK_DATA_LENGTH 8 +#define AT_CMD_SET_BUFFER_OFFSET 6 +#define AT_PW_STS_CHK_DATA_LENGTH 8 +#define USB_STATUS_SIZE 2 + +typedef enum { + READY = 0, + BUSY, + ERROR +} Req_Status; + +typedef struct USB_AT_REQ { + DEV_UINT32 bmRequestType; + DEV_UINT32 bRequest; + DEV_UINT32 wValue; + DEV_UINT32 wIndex; + DEV_UINT32 wLength; + DEV_UINT8 bValid; + DEV_UINT32 bCommand; + void *buffer; + +} DEV_REQ; + +typedef struct USB_AT_DATA { + DEV_UINT16 header; + DEV_UINT16 length; + DEV_UINT16 tsfun; + void *buffer; +} DEV_AT_CMD; + +typedef struct USB_EP_DATA { + DEV_UINT8 ep_num; + DEV_UINT8 dir; + DEV_UINT8 type; + DEV_UINT8 interval; + DEV_UINT16 ep_size; + DEV_UINT8 slot; + DEV_UINT8 burst; + DEV_UINT8 mult; +} EP_INFO; + +typedef struct USB_LB_DATA { + DEV_UINT32 transfer_length; + DEV_UINT32 gpd_buf_size; + DEV_UINT16 bd_buf_size; + DEV_UINT8 bdp; + DEV_UINT8 dram_offset; + DEV_UINT8 extension; + DEV_UINT8 dma_burst; + DEV_UINT8 dma_limiter; + +} LOOPBACK_INFO; + +typedef struct USB_RS_DATA { + DEV_UINT32 transfer_length; + DEV_UINT32 gpd_buf_size; + DEV_UINT16 bd_buf_size; + DEV_UINT8 dir_1; + DEV_UINT8 dir_2; + DEV_UINT32 stop_count_1; + DEV_UINT32 stop_count_2; + +} RANDOM_STOP_INFO; + +typedef struct USB_SQ_DATA { + DEV_UINT32 transfer_length; + DEV_UINT32 gpd_buf_size; + DEV_UINT16 bd_buf_size; + DEV_UINT8 tx_method; + +} STOP_QMU_INFO; + +typedef struct USB_PW_DATA { + DEV_UINT32 mode; + DEV_UINT8 u1_value; + DEV_UINT8 u2_value; + DEV_UINT8 en_u1; + DEV_UINT8 en_u2; + +} POWER_INFO; + +typedef struct USB_U1U2_DATA { + DEV_UINT8 type; + DEV_UINT8 u_num; + DEV_UINT8 opt; + DEV_UINT8 cond; + DEV_UINT8 u1_value; + DEV_UINT8 u2_value; + +} U1U2_INFO; + +typedef struct USB_LPM_DATA { + DEV_UINT8 lpm_mode; + DEV_UINT8 wakeup; + DEV_UINT8 beslck; + DEV_UINT8 beslck_u3; + DEV_UINT8 besldck; + DEV_UINT8 cond; + DEV_UINT8 cond_en; +} LPM_INFO; + +typedef struct USB_STALL_DATA { + DEV_UINT32 transfer_length; + DEV_UINT32 gpd_buf_size; + DEV_UINT16 bd_buf_size; + DEV_UINT8 bdp; + +} STALL_INFO; + +typedef struct USB_SINGLE_DATA { + DEV_UINT32 transfer_length; + DEV_UINT32 gpd_buf_size; + DEV_UINT16 bd_buf_size; + DEV_UINT8 dir; + DEV_UINT8 num; + DEV_UINT8 dual; + +} SINGLE_INFO; + +typedef struct USB_ST_DATA { + DEV_UINT32 transfer_length; + DEV_UINT32 gpd_buf_size; + DEV_UINT16 bd_buf_size; + DEV_UINT8 bdp; + DEV_UINT8 num; + +}STRESS_INFO; + +typedef struct USB_CZ_DATA { + DEV_UINT32 transfer_length; + DEV_UINT32 gpd_buf_size; + DEV_UINT16 bd_buf_size; + DEV_UINT8 zlp_en; + DEV_UINT8 coz_en; + +}RX_ZLP_INFO; + +typedef struct USB_NOTIF_DATA { + DEV_UINT32 valuel; + DEV_UINT32 valueh; + DEV_UINT8 type; + +}DEV_NOTIF_INFO; + +typedef struct USB_RESET_DATA { + DEV_UINT8 speed; +}REST_INFO; + +typedef struct USB_REMOTE_WAKE_DATA { + DEV_UINT16 delay; +}REMOTE_WAKE_INFO; + +typedef struct USB_CTRL_MODE_DATA { + DEV_UINT8 mode; +}CTRL_MODE_INFO; + +typedef struct USB_OTG_MODE_DATA { + DEV_UINT8 mode; +}OTG_MODE_INFO; + +typedef enum { + RESET_STATE, + CONFIG_EP_STATE, + LOOPBACK_STATE, + LOOPBACK_EXT_STATE, + REMOTE_WAKEUP, + STRESS, + EP_RESET_STATE, + WARM_RESET, + STALL, + RANDOM_STOP_STATE, + RX_ZLP_STATE, + DEV_NOTIFICATION_STATE, + STOP_QMU_STATE, + SINGLE, + POWER_STATE, + U1U2_STATE, + LPM_STATE, + STOP_DEV_STATE, + CTRL_MODE_STATE, + OTG_MODE_STATE +} USB3_TEST_CASE; + +typedef enum { + AT_CMD_SET, + AT_CMD_ACK, + AT_CTRL_TEST, + AT_PW_STS_CHK +} USB_AT_CMD; + +typedef enum { + RESERVED=0, + FUNCTION_WAKE, + LATENCY_TOLERANCE_MESSAGE, + BUS_INTERVAL_ADJUSTMENT_MESSAGE, + HOST_ROLE_REQUEST +} DEV_NOTIFICATION; + +struct USB_TEST_STATUS{ + USB_SPEED speed; + DEV_INT32 reset_received; + DEV_INT32 suspend; + DEV_INT32 enterU0; + DEV_INT32 vbus_valid; + DEV_INT32 addressed; +} ; + +EXTERN struct USB_TEST_STATUS g_usb_status; +EXTERN DEV_UINT8* g_loopback_buffer[2 * MAX_EP_NUM + 1]; +EXTERN DEV_UINT8 g_device_halt; +EXTERN DEV_UINT8 g_sw_rw; +EXTERN DEV_UINT8 g_hw_rw; +EXTERN DEV_UINT8 g_usb_irq; +EXTERN DEV_UINT8 g_u3d_status; +EXTERN DEV_UINT8 g_ep0_mode; +EXTERN DEV_UINT8 g_run; +EXTERN DEV_UINT16 g_hot_rst_cnt; +EXTERN DEV_UINT16 g_warm_rst_cnt; +EXTERN DEV_UINT16 g_rx_len_err_cnt; +EXTERN DEV_REQ *Request; +EXTERN DEV_AT_CMD *AT_CMD; +EXTERN DEV_UINT32 TransferLength; +EXTERN DEV_UINT8 bDramOffset; +EXTERN DEV_UINT8 bdma_burst; +EXTERN DEV_UINT8 bdma_limiter; + +EXTERN volatile DEV_UINT32 g_usb_phy_clk_on; +#ifdef SUPPORT_OTG +EXTERN volatile DEV_UINT32 g_otg_exec; +EXTERN volatile DEV_UINT32 g_otg_td_5_9; + +EXTERN volatile DEV_UINT32 g_otg_config; +EXTERN volatile DEV_UINT32 g_otg_srp_reqd; +EXTERN volatile DEV_UINT32 g_otg_hnp_reqd; +EXTERN volatile DEV_UINT32 g_otg_b_hnp_enable; + +EXTERN volatile DEV_UINT32 g_otg_vbus_chg; +EXTERN volatile DEV_UINT32 g_otg_reset; +EXTERN volatile DEV_UINT32 g_otg_suspend; +EXTERN volatile DEV_UINT32 g_otg_resume; +EXTERN volatile DEV_UINT32 g_otg_connect; +EXTERN volatile DEV_UINT32 g_otg_disconnect; +EXTERN volatile DEV_UINT32 g_otg_chg_a_role_b; +EXTERN volatile DEV_UINT32 g_otg_chg_b_role_b; +EXTERN volatile DEV_UINT32 g_otg_attach_b_role; + +EXTERN spinlock_t g_otg_lock; +#endif + +EXTERN void u3d_sync_with_bat(int usb_state); + +EXTERN void u3d_init_ctrl(void); +EXTERN void u3d_irq_en(void); +EXTERN void u3d_ep0_handler(void); +EXTERN void u3d_epx_handler(DEV_INT32 ep_num, USB_DIR dir); +EXTERN void u3d_dma_handler(DEV_INT32 chan_num); +EXTERN DEV_UINT8 req_complete(DEV_INT32 ep_num, USB_DIR dir); +EXTERN DEV_UINT8 u3d_command(void); +EXTERN void *u3d_req_buffer(void); +EXTERN DEV_UINT8 u3d_req_valid(void); +EXTERN void u3d_rst_request(void); +EXTERN void u3d_alloc_req(void); +EXTERN void u3d_init(void); +// USBIF +EXTERN void u3d_init_mem(void); +EXTERN void u3d_deinit(void); + +EXTERN void u3d_allocate_ep0_buffer(void); +EXTERN void u3d_dev_loopback(DEV_INT32 ep_rx,DEV_INT32 ep_tx); +EXTERN DEV_UINT8 u3d_device_halt(void); +EXTERN DEV_UINT8 u3d_transfer_complete(DEV_INT32 ep_num, USB_DIR dir); +EXTERN DEV_INT32 u3d_dev_suspend(void); +EXTERN void u3d_ep0en(void); +EXTERN void u3d_initialize_drv(void); +EXTERN void u3d_set_address(DEV_INT32 addr); +EXTERN void u3d_ep_start_transfer(DEV_INT32 ep_num, USB_DIR dir); +EXTERN void u3d_rxep_dis(DEV_INT32 ep_num); +EXTERN void dev_power_mode(DEV_INT32 mode, DEV_INT8 u1_value, DEV_INT8 u2_value, DEV_INT8 en_u1, DEV_INT8 en_u2); +EXTERN void dev_send_one_packet(DEV_INT32 ep_tx); +EXTERN void dev_send_erdy(DEV_INT8 opt,DEV_INT32 ep_rx , DEV_INT32 ep_tx); +EXTERN void dev_receive_ep0_test_packet(DEV_INT8 opt); +EXTERN void dev_u1u2_en_cond(DEV_INT8 opt,DEV_INT8 cond,DEV_INT32 ep_rx , DEV_INT32 ep_tx); +EXTERN void dev_u1u2_en_ctrl(DEV_INT8 type,DEV_INT8 u_num,DEV_INT8 opt,DEV_INT8 cond,DEV_INT8 u1_value, DEV_INT8 u2_value); +EXTERN DEV_INT8 dev_stschk(DEV_INT8 type, DEV_INT8 change); +EXTERN void reset_dev(USB_SPEED speed, DEV_UINT8 det_speed, DEV_UINT8 sw_rst); +EXTERN void dev_lpm_config_dev(LPM_INFO *lpm_info); + +#undef EXTERN + + +#endif //USB_DRV_H + |