diff options
| author | Meizu OpenSource <patchwork@meizu.com> | 2016-08-15 10:19:42 +0800 |
|---|---|---|
| committer | Meizu OpenSource <patchwork@meizu.com> | 2016-08-15 10:19:42 +0800 |
| commit | d2e1446d81725c351dc73a03b397ce043fb18452 (patch) | |
| tree | 4dbc616b7f92aea39cd697a9084205ddb805e344 /include/linux/rtc | |
first commit
Diffstat (limited to 'include/linux/rtc')
| -rw-r--r-- | include/linux/rtc/ds1307.h | 22 | ||||
| -rw-r--r-- | include/linux/rtc/m48t59.h | 64 | ||||
| -rw-r--r-- | include/linux/rtc/sirfsoc_rtciobrg.h | 18 |
3 files changed, 104 insertions, 0 deletions
diff --git a/include/linux/rtc/ds1307.h b/include/linux/rtc/ds1307.h new file mode 100644 index 000000000..291b1c490 --- /dev/null +++ b/include/linux/rtc/ds1307.h @@ -0,0 +1,22 @@ +/* + * ds1307.h - platform_data for the ds1307 (and variants) rtc driver + * (C) Copyright 2012 by Wolfram Sang, Pengutronix e.K. + * same license as the driver + */ + +#ifndef _LINUX_DS1307_H +#define _LINUX_DS1307_H + +#include <linux/types.h> + +#define DS1307_TRICKLE_CHARGER_250_OHM 0x01 +#define DS1307_TRICKLE_CHARGER_2K_OHM 0x02 +#define DS1307_TRICKLE_CHARGER_4K_OHM 0x03 +#define DS1307_TRICKLE_CHARGER_NO_DIODE 0x04 +#define DS1307_TRICKLE_CHARGER_DIODE 0x08 + +struct ds1307_platform_data { + u8 trickle_charger_setup; +}; + +#endif /* _LINUX_DS1307_H */ diff --git a/include/linux/rtc/m48t59.h b/include/linux/rtc/m48t59.h new file mode 100644 index 000000000..6fc961459 --- /dev/null +++ b/include/linux/rtc/m48t59.h @@ -0,0 +1,64 @@ +/* + * include/linux/rtc/m48t59.h + * + * Definitions for the platform data of m48t59 RTC chip driver. + * + * Copyright (c) 2007 Wind River Systems, Inc. + * + * Mark Zhan <rongkai.zhan@windriver.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef _LINUX_RTC_M48T59_H_ +#define _LINUX_RTC_M48T59_H_ + +/* + * M48T59 Register Offset + */ +#define M48T59_YEAR 0xf +#define M48T59_MONTH 0xe +#define M48T59_MDAY 0xd /* Day of Month */ +#define M48T59_WDAY 0xc /* Day of Week */ +#define M48T59_WDAY_CB 0x20 /* Century Bit */ +#define M48T59_WDAY_CEB 0x10 /* Century Enable Bit */ +#define M48T59_HOUR 0xb +#define M48T59_MIN 0xa +#define M48T59_SEC 0x9 +#define M48T59_CNTL 0x8 +#define M48T59_CNTL_READ 0x40 +#define M48T59_CNTL_WRITE 0x80 +#define M48T59_WATCHDOG 0x7 +#define M48T59_INTR 0x6 +#define M48T59_INTR_AFE 0x80 /* Alarm Interrupt Enable */ +#define M48T59_INTR_ABE 0x20 +#define M48T59_ALARM_DATE 0x5 +#define M48T59_ALARM_HOUR 0x4 +#define M48T59_ALARM_MIN 0x3 +#define M48T59_ALARM_SEC 0x2 +#define M48T59_UNUSED 0x1 +#define M48T59_FLAGS 0x0 +#define M48T59_FLAGS_WDT 0x80 /* watchdog timer expired */ +#define M48T59_FLAGS_AF 0x40 /* alarm */ +#define M48T59_FLAGS_BF 0x10 /* low battery */ + +#define M48T59RTC_TYPE_M48T59 0 /* to keep compatibility */ +#define M48T59RTC_TYPE_M48T02 1 +#define M48T59RTC_TYPE_M48T08 2 + +struct m48t59_plat_data { + /* The method to access M48T59 registers */ + void (*write_byte)(struct device *dev, u32 ofs, u8 val); + unsigned char (*read_byte)(struct device *dev, u32 ofs); + + int type; /* RTC model */ + + /* ioaddr mapped externally */ + void __iomem *ioaddr; + /* offset to RTC registers, automatically set according to the type */ + unsigned int offset; +}; + +#endif /* _LINUX_RTC_M48T59_H_ */ diff --git a/include/linux/rtc/sirfsoc_rtciobrg.h b/include/linux/rtc/sirfsoc_rtciobrg.h new file mode 100644 index 000000000..2c92e1c8e --- /dev/null +++ b/include/linux/rtc/sirfsoc_rtciobrg.h @@ -0,0 +1,18 @@ +/* + * RTC I/O Bridge interfaces for CSR SiRFprimaII + * ARM access the registers of SYSRTC, GPSRTC and PWRC through this module + * + * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. + * + * Licensed under GPLv2 or later. + */ +#ifndef _SIRFSOC_RTC_IOBRG_H_ +#define _SIRFSOC_RTC_IOBRG_H_ + +extern void sirfsoc_rtc_iobrg_besyncing(void); + +extern u32 sirfsoc_rtc_iobrg_readl(u32 addr); + +extern void sirfsoc_rtc_iobrg_writel(u32 val, u32 addr); + +#endif |
