misc: fix a bunch of 'warning: backslash and newline separated by space'

3 files changed, 41 insertions, 41 deletions

diff --git a/drivers/misc/mediatek/dispsys/mt6735/ddp_dsi.c b/drivers/misc/mediatek/dispsys/mt6735/ddp_dsi.c
index 4df98d76a..8fb64d1aa 100644
--- a/drivers/misc/mediatek/dispsys/mt6735/ddp_dsi.c
+++ b/drivers/misc/mediatek/dispsys/mt6735/ddp_dsi.c
@@ -42,7 +42,7 @@ extern bool is_ipoh_bootup;
 #define DSI_POLLREG32(cmdq, addr,mask,value) DISP_REG_CMDQ_POLLING(cmdq, addr,value,mask)
 
 #define BIT_TO_VALUE(TYPE,bit)  \
-	do { \   
+	do { \
 		TYPE r;\
 		*(unsigned long*)(&r) = ((unsigned int)0x00000000);	  \
 		r.bit = ~(r.bit);\
@@ -93,10 +93,10 @@ extern bool is_ipoh_bootup;
 	else printk("MIPI write fail\n");		\
 }
 
-#define MIPITX_INREG32(addr)								\		
+#define MIPITX_INREG32(addr)								\
   	({														\
   		unsigned int val = 0;										\
-		if(0) val = INREG32(addr);								\	
+		if(0) val = INREG32(addr);								\
 		if(dsi_reg_op_debug) 								\
 		{													\
 			printk("[mipitx/inreg]%p=0x%08x\n", (void*)addr, val);	\
@@ -123,10 +123,10 @@ extern bool is_ipoh_bootup;
 	
 #define MIPITX_MASKREG32(x, y, z)  MIPITX_OUTREG32(x, (MIPITX_INREG32(x)&~(y))|(z))
 #else
-#define MIPITX_INREG32(addr)								\		
+#define MIPITX_INREG32(addr)								\
   	({														\
   		unsigned int val = 0;										\
-		val = INREG32(addr);								\	
+		val = INREG32(addr);								\
 		if(dsi_reg_op_debug) 								\
 		{													\
 			printk("[mipitx/inreg]%p=0x%08x\n", (void*)addr, val);	\
diff --git a/drivers/misc/mediatek/mach/mt6735/include/mach/mt_spm_cpu.h b/drivers/misc/mediatek/mach/mt6735/include/mach/mt_spm_cpu.h
index cb14a0623..f852ee72a 100644
--- a/drivers/misc/mediatek/mach/mt6735/include/mach/mt_spm_cpu.h
+++ b/drivers/misc/mediatek/mach/mt6735/include/mach/mt_spm_cpu.h
@@ -305,40 +305,40 @@ extern u32 spm_irq_7;
 	SPM_WAKE_SRC(31, APSRC_SLEEP)	\
 }
 #else
-#define SPM_WAKE_SRC_LIST	{	\                                   
-	SPM_WAKE_SRC(0, SPM_MERGE),	/* PCM timer, TWAM or CPU */	\   
-	SPM_WAKE_SRC(1, MD32_WDT),	\                                 
-	SPM_WAKE_SRC(2, KP),		\                                     
-	SPM_WAKE_SRC(3, WDT),		\                                     
-	SPM_WAKE_SRC(4, GPT),		\                                     
-	SPM_WAKE_SRC(5, CONN2AP),	\                                   
-	SPM_WAKE_SRC(6, EINT),		\                                   
-	SPM_WAKE_SRC(7, CONN_WDT),	\                                 
-	SPM_WAKE_SRC(8, CCIF0_MD),	\                                 
-	SPM_WAKE_SRC(9, LOW_BAT),	\                                   
-	SPM_WAKE_SRC(10, MD32_SPM),	\                                 
-	SPM_WAKE_SRC(11, F26M_WAKE),	\                               
-	SPM_WAKE_SRC(12, F26M_SLEEP),	\                               
-	SPM_WAKE_SRC(13, PCM_WDT),	\                                 
-	SPM_WAKE_SRC(14, USB_CD),	\                                   
-	SPM_WAKE_SRC(15, USB_PDN),	\                                 
-	SPM_WAKE_SRC(16, LTE_WAKE),	\                                 
-	SPM_WAKE_SRC(17, LTE_SLEEP),	\                               
-	SPM_WAKE_SRC(18, CCIF1_MD),	\                                 
-	SPM_WAKE_SRC(19, UART0),	\                                   
-	SPM_WAKE_SRC(20, AFE),		\                                   
-	SPM_WAKE_SRC(21, THERM),	\                                   
-	SPM_WAKE_SRC(22, CIRQ),		\                                   
-	SPM_WAKE_SRC(23, MD2_WDT),	\                                 
-	SPM_WAKE_SRC(24, SYSPWREQ),	\                                 
-	SPM_WAKE_SRC(25, MD_WDT),	\                                   
-	SPM_WAKE_SRC(26, CLDMA_MD),	\                                 
-	SPM_WAKE_SRC(27, SEJ),		\                                   
-	SPM_WAKE_SRC(28, ALL_MD32),	\                                 
-	SPM_WAKE_SRC(29, CPU_IRQ),	\                                 
-	SPM_WAKE_SRC(30, APSRC_WAKE),	\                               
-	SPM_WAKE_SRC(31, APSRC_SLEEP)	\                               
-}                                                               
+#define SPM_WAKE_SRC_LIST	{	\
+	SPM_WAKE_SRC(0, SPM_MERGE),	/* PCM timer, TWAM or CPU */	\
+	SPM_WAKE_SRC(1, MD32_WDT),	\
+	SPM_WAKE_SRC(2, KP),		\
+	SPM_WAKE_SRC(3, WDT),		\
+	SPM_WAKE_SRC(4, GPT),		\
+	SPM_WAKE_SRC(5, CONN2AP),	\
+	SPM_WAKE_SRC(6, EINT),		\
+	SPM_WAKE_SRC(7, CONN_WDT),	\
+	SPM_WAKE_SRC(8, CCIF0_MD),	\
+	SPM_WAKE_SRC(9, LOW_BAT),	\
+	SPM_WAKE_SRC(10, MD32_SPM),	\
+	SPM_WAKE_SRC(11, F26M_WAKE),	\
+	SPM_WAKE_SRC(12, F26M_SLEEP),	\
+	SPM_WAKE_SRC(13, PCM_WDT),	\
+	SPM_WAKE_SRC(14, USB_CD),	\
+	SPM_WAKE_SRC(15, USB_PDN),	\
+	SPM_WAKE_SRC(16, LTE_WAKE),	\
+	SPM_WAKE_SRC(17, LTE_SLEEP),	\
+	SPM_WAKE_SRC(18, CCIF1_MD),	\
+	SPM_WAKE_SRC(19, UART0),	\
+	SPM_WAKE_SRC(20, AFE),		\
+	SPM_WAKE_SRC(21, THERM),	\
+	SPM_WAKE_SRC(22, CIRQ),		\
+	SPM_WAKE_SRC(23, MD2_WDT),	\
+	SPM_WAKE_SRC(24, SYSPWREQ),	\
+	SPM_WAKE_SRC(25, MD_WDT),	\
+	SPM_WAKE_SRC(26, CLDMA_MD),	\
+	SPM_WAKE_SRC(27, SEJ),		\
+	SPM_WAKE_SRC(28, ALL_MD32),	\
+	SPM_WAKE_SRC(29, CPU_IRQ),	\
+	SPM_WAKE_SRC(30, APSRC_WAKE),	\
+	SPM_WAKE_SRC(31, APSRC_SLEEP)	\
+} 
 #endif
 /* define WAKE_SRC_XXX */
 #undef SPM_WAKE_SRC
diff --git a/drivers/misc/mediatek/ssw/ssw_single_v2/sim_switch.c b/drivers/misc/mediatek/ssw/ssw_single_v2/sim_switch.c
index 62657a2c0..83f9bad32 100644
--- a/drivers/misc/mediatek/ssw/ssw_single_v2/sim_switch.c
+++ b/drivers/misc/mediatek/ssw/ssw_single_v2/sim_switch.c
@@ -178,11 +178,11 @@ static int set_sim_gpio(unsigned int mode)
             return SSW_INVALID_PARA;
     }
 #if (defined(GPIO_SIM1_HOT_PLUG) && defined(GPIO_SIM2_HOT_PLUG))
-    SSW_DBG("mode(%d),SIM1(eint=%d, sclk=%d, srst=%d , sio=%d) SIM2(eint=%d,sclk=%d, srst=%d , sio=%d)\n", mode,\        
+    SSW_DBG("mode(%d),SIM1(eint=%d, sclk=%d, srst=%d , sio=%d) SIM2(eint=%d,sclk=%d, srst=%d , sio=%d)\n", mode,\
         mt_get_gpio_mode(GPIO_SIM1_HOT_PLUG),mt_get_gpio_mode(GPIO_SIM1_SCLK),mt_get_gpio_mode(GPIO_SIM1_SRST),mt_get_gpio_mode(GPIO_SIM1_SIO), \
         mt_get_gpio_mode(GPIO_SIM2_HOT_PLUG),mt_get_gpio_mode(GPIO_SIM2_SCLK),mt_get_gpio_mode(GPIO_SIM2_SRST),mt_get_gpio_mode(GPIO_SIM2_SIO));
 #else
-    SSW_DBG("mode(%d),SIM1(sclk=%d, srst=%d , sio=%d) SIM2(sclk=%d, srst=%d , sio=%d)\n", mode,\        
+    SSW_DBG("mode(%d),SIM1(sclk=%d, srst=%d , sio=%d) SIM2(sclk=%d, srst=%d , sio=%d)\n", mode,\
         mt_get_gpio_mode(GPIO_SIM1_SCLK),mt_get_gpio_mode(GPIO_SIM1_SRST),mt_get_gpio_mode(GPIO_SIM1_SIO), \
         mt_get_gpio_mode(GPIO_SIM2_SCLK),mt_get_gpio_mode(GPIO_SIM2_SRST),mt_get_gpio_mode(GPIO_SIM2_SIO));