373 lines
8.5 KiB
C
373 lines
8.5 KiB
C
/*
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* Simulator of microcontrollers (stypes.h)
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*
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* Copyright (C) 1997,16 Drotos Daniel, Talker Bt.
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*
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* To contact author send email to drdani@mazsola.iit.uni-miskolc.hu
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*
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*/
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/* This file is part of microcontroller simulator: ucsim.
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UCSIM is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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UCSIM is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with UCSIM; see the file COPYING. If not, write to the Free
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Software Foundation, 59 Temple Place - Suite 330, Boston, MA
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02111-1307, USA. */
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/*@1@*/
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#ifndef STYPES_HEADER
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#define STYPES_HEADER
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#include "ddconfig.h"
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//typedef int8_t TYPE_BYTE;
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//typedef uint8_t TYPE_UBYTE;
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//typedef int16_t TYPE_WORD;
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//typedef uint16_t TYPE_UWORD;
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//typedef int32_t TYPE_DWORD;
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//typedef uint32_t TYPE_UDWORD;
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typedef unsigned char uchar;
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typedef unsigned int uint;
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typedef unsigned long ulong;
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typedef signed TYPE_BYTE i8_t;
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typedef unsigned TYPE_BYTE u8_t;
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typedef signed TYPE_WORD i16_t;
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typedef unsigned TYPE_WORD u16_t;
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typedef signed TYPE_DWORD i32_t;
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typedef unsigned TYPE_DWORD u32_t;
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typedef signed TYPE_QWORD i64_t;
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typedef unsigned TYPE_QWORD u64_t;
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typedef i64_t t_addr; /* 64 bit max */
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typedef u32_t t_mem; /* 32 bit max */
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typedef i32_t t_smem; /* signed 32 bit memory */
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#define SPECA SPEC_QWORD
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#define SPECM SPEC_DWORD
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#define AI(addr) ((int)(addr))
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#define AU(addr) ((unsigned int)(addr))
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#define AI8(addr) (AI((addr)&0xff))
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#define AU8(addr) (AU((addr)&0xff))
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#define AI16(addr) (AI((addr)&0xffff))
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#define AU16(addr) (AU((addr)&0xffff))
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#define AI32(addr) (AI((addr)&0xffffffff))
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#define AU32(addr) (AU((addr)&0xffffffff))
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#define MI(v) ((int)(v))
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#define MU(v) ((unsigned int)(v))
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#define MI8(v) (MI((v)&0xff))
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#define MU8(v) (MU((v)&0xff))
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#define MI32(v) (MI((v)&0xffffffff))
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#define MU32(v) (MU((v)&0xffffffff))
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enum {
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max_mem_size= 0x40000000 /* 1 GB */
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};
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struct id_element
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{
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int id;
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const char *id_string;
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};
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enum error_type {
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err_unknown = 0x01,
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err_error = 0x02,
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err_warning = 0x04
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};
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// table of dissassembled instructions
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struct dis_entry
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{
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/*uint64_t*/long long code, mask; // max 8 byte of code
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char branch;
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uchar length;
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const char *mnemonic;
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bool is_call;
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};
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// table entry of SFR and BIT names
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struct name_entry
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{
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int cpu_type;
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t_addr addr;
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const char *name;
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};
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enum cpu_type {
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CPU_NONE = 0,
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CPU_51 = 0x0001,
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CPU_31 = 0x0002,
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CPU_52 = 0x0004,
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CPU_32 = 0x0008,
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CPU_51R = 0x0010,
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CPU_89C51R = 0x0020,
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CPU_251 = 0x0040,
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CPU_DS320 = 0x0080,
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CPU_DS390 = 0x0100,
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CPU_DS390F = 0x0200,
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CPU_C521 = 0x0400,
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CPU_517 = 0x0800,
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CPU_F380 = 0x1000,
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CPU_XC88X = 0x2000,
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CPU_ALL_51 = (CPU_51|CPU_31),
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CPU_ALL_52 = (CPU_52|CPU_32|CPU_51R|CPU_89C51R|CPU_251|
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CPU_DS320|CPU_DS390|CPU_DS390F|
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CPU_C521|CPU_517|CPU_XC88X|
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CPU_F380),
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CPU_ALL_DS3X0 = (CPU_DS320|CPU_DS390|CPU_DS390F),
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CPU_AVR = 0x0001,
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CPU_ALL_AVR = (CPU_AVR),
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CPU_Z80 = 0x0001,
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CPU_Z180 = 0x0002,
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CPU_LR35902 = 0x0004,
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CPU_R2K = 0x0008,
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CPU_R3KA = 0x0010,
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CPU_EZ80 = 0x0020,
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CPU_ALL_Z80 = (CPU_Z80|CPU_Z180|CPU_R2K|CPU_LR35902|CPU_R3KA|CPU_EZ80),
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CPU_XA = 0x0001,
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CPU_ALL_XA = (CPU_XA),
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CPU_HC08 = 0x0001,
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CPU_HCS08 = 0x0002,
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CPU_ALL_HC08 = (CPU_HC08|CPU_HCS08),
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CPU_STM8S = 0x0001, // S and AF family
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CPU_STM8AF = 0x0001,
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CPU_STM8SAF = 0x0001,
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// Devices of S family 0x00 00 00 XX
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DEV_STM8S903 = 0x00000001,
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DEV_STM8S003 = 0x00000002,
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DEV_STM8S005 = 0x00000004,
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DEV_STM8S007 = 0x00000008,
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DEV_STM8S103 = 0x00000010,
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DEV_STM8S105 = 0x00000020,
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DEV_STM8S207 = 0x00000040,
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DEV_STM8S208 = 0x00000080,
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DEV_STM8S = (DEV_STM8S903|
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DEV_STM8S003|
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DEV_STM8S005|
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DEV_STM8S007|
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DEV_STM8S103|
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DEV_STM8S105|
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DEV_STM8S207|
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DEV_STM8S208),
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// Devices of AF family 0x00 00 0X 00
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DEV_STM8AF52 = 0x00000100,
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DEV_STM8AF62_12 = 0x00000200,
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DEV_STM8AF62_46 = 0x00000400,
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DEV_STM8AF = (DEV_STM8AF52|
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DEV_STM8AF62_12|
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DEV_STM8AF62_46),
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DEV_STM8SAF = (DEV_STM8S|DEV_STM8AF),
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CPU_STM8L = 0x0002, // AL and L family
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// Devices of AL family 0x00 0X 00 00
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DEV_STM8AL3xE = 0x00010000,
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DEV_STM8AL3x8 = 0x00020000,
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DEV_STM8AL3x346 = 0x00040000,
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DEV_STM8AL = (DEV_STM8AL3xE|
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DEV_STM8AL3x8|
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DEV_STM8AL3x346),
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// Devices of L family 0xXX 00 00 00
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DEV_STM8L051 = 0x01000000,
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DEV_STM8L052C = 0x02000000,
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DEV_STM8L052R = 0x04000000,
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DEV_STM8L151x23 = 0x08000000,
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DEV_STM8L15x46 = 0x10000000,
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DEV_STM8L15x8 = 0x20000000,
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DEV_STM8L162 = 0x40000000,
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DEV_STM8L = (DEV_STM8L051|
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DEV_STM8L052C|
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DEV_STM8L052R|
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DEV_STM8L151x23|
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DEV_STM8L15x46|
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DEV_STM8L15x8|
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DEV_STM8L162),
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DEV_STM8ALL = (DEV_STM8AL|DEV_STM8L),
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CPU_STM8101 = 0x0004, // L101 family
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CPU_STM8L101 = 0x0004,
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// Devices of L101 family 0x00 00 X0 00
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DEV_STM8101 = 0x00001000,
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DEV_STM8L101 = 0x00001000,
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CPU_ALL_STM8 = (CPU_STM8S|CPU_STM8L|CPU_STM8101),
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CPU_ST7 = 0x0001,
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CPU_ALL_ST7 = (CPU_ST7),
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// technology
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CPU_CMOS = 0x0001,
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CPU_HMOS = 0x0002,
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CPU_PDK13 = 0x0001,
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CPU_PDK14 = 0x0002,
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CPU_PDK15 = 0x0003,
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};
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struct cpu_entry
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{
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const char *type_str;
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enum cpu_type type;
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int subtype;
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const char *type_help;
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const char *sub_help;
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};
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/* Classes of memories, this is index on the list */
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enum mem_class
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{
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MEM_ROM= 0,
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MEM_XRAM,
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MEM_IRAM,
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MEM_SFR,
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MEM_DUMMY,
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MEM_IXRAM,
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MEM_TYPES
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};
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#define MEM_SFR_ID cchars("sfr")
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#define MEM_XRAM_ID cchars("xram")
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#define MEM_IXRAM_ID cchars("ixram")
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#define MEM_IRAM_ID cchars("iram")
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// States of simulator
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enum sim_state {
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SIM_NONE = 0,
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SIM_GO = 0x01, // Processor is running
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SIM_QUIT = 0x02 // Program must exit
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};
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/* States of CPU */
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enum cpu_state {
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stGO = 0, /* Normal state */
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stIDLE = 1, /* Idle mode is active */
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stPD = 2 /* Power Down mode is active */
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};
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/* Result of instruction simulation */
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enum inst_result {
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resGO = 0, /* OK, go on */
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resWDTRESET = 1, /* Reseted by WDT */
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resINTERRUPT = 2, /* Interrupt accepted */
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resSTOP = 100, /* Stop if result greather then this */
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resHALT = 101, /* Serious error, halt CPU */
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resINV_ADDR = 102, /* Invalid indirect address */
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resSTACK_OV = 103, /* Stack overflow */
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resBREAKPOINT = 104, /* Fetch Breakpoint */
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resUSER = 105, /* Stopped by user */
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resINV_INST = 106, /* Invalid instruction */
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resBITADDR = 107, /* Bit address is uninterpretable */
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resERROR = 108, /* Error happened during instruction exec */
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resSTEP = 109, /* Step command done, no more exex needed */
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resSIMIF = 110, /* Stopped by simulated prog itself through sim interface */
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resNOT_DONE = 111, /* Intruction has not simulated */
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resEVENTBREAK = 112, /* Event breakpoint */
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};
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#define BIT_MASK(bitaddr) (1 << (bitaddr & 0x07))
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/* Type of breakpoints */
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enum brk_perm
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{
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brkFIX, /* f */
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brkDYNAMIC /* d */
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};
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enum brk_type
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{
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brkFETCH, /* f */
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brkEVENT /* e */
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};
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enum brk_event
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{
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brkNONE,
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brkWXRAM, /* wx */
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brkRXRAM, /* rx */
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brkRCODE, /* rc */
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brkWIRAM, /* wi */
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brkRIRAM, /* ri */
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brkWSFR, /* ws */
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brkRSFR, /* rs */
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brkREAD,
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brkWRITE,
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brkACCESS
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};
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/* Interrupt levels */
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enum intr_levels {
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//IT_NO = -1, /* not in interroupt service */
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IT_LOW = 1, /* low level interrupt service */
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IT_HIGH = 2 /* service of high priority interrupt */
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};
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/* cathegories of hw elements (peripherials) */
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enum hw_cath {
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HW_DUMMY = 0x0000,
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HW_TIMER = 0x0002,
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HW_UART = 0x0004,
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HW_PORT = 0x0008,
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HW_PCA = 0x0010,
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HW_INTERRUPT = 0x0020,
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HW_WDT = 0x0040,
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HW_SIMIF = 0x0080,
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HW_RESET = 0x0100,
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HW_CLOCK = 0x0200,
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HW_CALC = 0x0400,
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HW_FLASH = 0x0800,
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HW_CPU = 0x1000
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};
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// Events that can happen in peripherals
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enum hw_event {
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EV_OVERFLOW,
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EV_PORT_CHANGED,
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EV_T2_MODE_CHANGED,
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EV_CLK_ON,
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EV_CLK_OFF
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};
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// flags of hw units
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enum hw_flags {
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HWF_NONE = 0,
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HWF_INSIDE = 0x0001,
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HWF_OUTSIDE = 0x0002,
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HWF_MISC = 0x0004
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};
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/* Letter cases */
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enum letter_case {
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case_upper, /* all is upper case */
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case_lower, /* all is lower case */
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case_case /* first letter is upper, others are lower case */
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};
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#endif
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/* End of stypes.h */
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