From 268a53de823a6750d6256ee1fb1e7707b4b45740 Mon Sep 17 00:00:00 2001 From: Xavier ASUS Date: Fri, 18 Oct 2019 00:31:54 +0200 Subject: sdcc-3.9.0 fork implementing GNU assembler syntax This fork aims to provide better support for stm8-binutils --- sim/ucsim/st7.src/(c).1 | 25 + sim/ucsim/st7.src/Makefile | 163 ++++++ sim/ucsim/st7.src/Makefile.in | 163 ++++++ sim/ucsim/st7.src/clean.mk | 26 + sim/ucsim/st7.src/conf.mk | 10 + sim/ucsim/st7.src/glob.cc | 763 +++++++++++++++++++++++++ sim/ucsim/st7.src/glob.h | 44 ++ sim/ucsim/st7.src/inst.cc | 1023 ++++++++++++++++++++++++++++++++++ sim/ucsim/st7.src/instcl.h | 39 ++ sim/ucsim/st7.src/regsst7.h | 61 ++ sim/ucsim/st7.src/simst7.cc | 45 ++ sim/ucsim/st7.src/simst7cl.h | 45 ++ sim/ucsim/st7.src/sst7.cc | 56 ++ sim/ucsim/st7.src/st7.cc | 1229 +++++++++++++++++++++++++++++++++++++++++ sim/ucsim/st7.src/st7cl.h | 82 +++ sim/ucsim/st7.src/st7mac.h | 42 ++ 16 files changed, 3816 insertions(+) create mode 100644 sim/ucsim/st7.src/(c).1 create mode 100644 sim/ucsim/st7.src/Makefile create mode 100644 sim/ucsim/st7.src/Makefile.in create mode 100644 sim/ucsim/st7.src/clean.mk create mode 100644 sim/ucsim/st7.src/conf.mk create mode 100644 sim/ucsim/st7.src/glob.cc create mode 100644 sim/ucsim/st7.src/glob.h create mode 100644 sim/ucsim/st7.src/inst.cc create mode 100644 sim/ucsim/st7.src/instcl.h create mode 100644 sim/ucsim/st7.src/regsst7.h create mode 100644 sim/ucsim/st7.src/simst7.cc create mode 100644 sim/ucsim/st7.src/simst7cl.h create mode 100644 sim/ucsim/st7.src/sst7.cc create mode 100644 sim/ucsim/st7.src/st7.cc create mode 100644 sim/ucsim/st7.src/st7cl.h create mode 100644 sim/ucsim/st7.src/st7mac.h (limited to 'sim/ucsim/st7.src') diff --git a/sim/ucsim/st7.src/(c).1 b/sim/ucsim/st7.src/(c).1 new file mode 100644 index 0000000..0249e68 --- /dev/null +++ b/sim/ucsim/st7.src/(c).1 @@ -0,0 +1,25 @@ +/* + * Simulator of microcontrollers (@@F@@) + * + * Copyright (C) @@S@@,@@Y@@ Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ diff --git a/sim/ucsim/st7.src/Makefile b/sim/ucsim/st7.src/Makefile new file mode 100644 index 0000000..bc87042 --- /dev/null +++ b/sim/ucsim/st7.src/Makefile @@ -0,0 +1,163 @@ +# +# uCsim st7.src/Makefile +# +# (c) Drotos Daniel, Talker Bt. 1997 +# + +STARTYEAR = 1997 + +SHELL = /bin/sh +CXX = g++ +CPP = gcc -E +CXXCPP = g++ -E +RANLIB = ranlib +INSTALL = /usr/bin/install -c +STRIP = strip +MAKEDEP = g++ -MM + +top_builddir = .. +top_srcdir = .. + +transform = s,x,x, + +DEFS = $(subs -DHAVE_CONFIG_H,,-DHAVE_CONFIG_H) +CPPFLAGS = -I$(srcdir) -I$(top_srcdir) -I$(top_builddir) \ + -I$(top_srcdir)/cmd.src -I$(top_srcdir)/sim.src \ + -I$(top_srcdir)/gui.src +CFLAGS = -g -O2 -Wall +CXXFLAGS = -g -O2 -g -Wall +LDFLAGS = +PICOPT = -fPIC -DPIC +SHAREDLIB = yes + +EXEEXT = + +LIBS = -L$(top_builddir) -lsim -lucsimutil -lguiucsim -lcmd -lsim -lrt -lnsl +DL = -ldl +dl_ok = yes + +prefix = /usr/local +exec_prefix = ${prefix} +bindir = ${exec_prefix}/bin +libdir = ${exec_prefix}/lib +datadir = ${datarootdir} +datarootdir = ${prefix}/share +includedir = ${prefix}/include +mandir = ${datarootdir}/man +man1dir = $(mandir)/man1 +man2dir = $(mandir)/man2 +infodir = ${datarootdir}/info +srcdir = . +VPATH = . + +OBJECTS_SHARED = glob.o \ + inst.o \ + simst7.o st7.o +OBJECTS_EXE = sst7.o +OBJECTS = $(OBJECTS_SHARED) $(OBJECTS_EXE) + +ST7ASM = + +enable_dlso = no +dlso_ok = no + +#TEST_OBJ = test_bit.hex test_dis.hex test_mov.hex test_jmp.hex \ +# test_arith.hex + +# Compiling entire program or any subproject +# ------------------------------------------ +all: checkconf otherlibs st7.src tests + +tests: $(TEST_OBJ) + + +# Compiling and installing everything and runing test +# --------------------------------------------------- +install: all installdirs + $(INSTALL) sst7$(EXEEXT) $(DESTDIR)$(bindir)/`echo sst7|sed '$(transform)'`$(EXEEXT) + $(STRIP) $(DESTDIR)$(bindir)/`echo sst7|sed '$(transform)'`$(EXEEXT) + + +# Deleting all the installed files +# -------------------------------- +uninstall: + rm -f $(DESTDIR)$(bindir)/`echo sst7|sed '$(transform)'`$(EXEEXT) + + +# Performing self-test +# -------------------- +check: test + +test: + + +# Performing installation test +# ---------------------------- +installcheck: + + +# Creating installation directories +# --------------------------------- +installdirs: + test -d $(DESTDIR)$(bindir) || $(INSTALL) -d $(DESTDIR)$(bindir) + + +# Creating dependencies +# --------------------- +dep: Makefile.dep + +Makefile.dep: $(srcdir)/*.cc $(srcdir)/*.h + $(MAKEDEP) $(CPPFLAGS) $(filter %.cc,$^) >Makefile.dep + +-include Makefile.dep +include $(srcdir)/clean.mk + +# My rules +# -------- +.SUFFIXES: .asm .hex + +st7.src: sst7$(EXEEXT) shared_lib + +sst7$(EXEEXT): $(OBJECTS) $(top_builddir)/libcmd.a $(top_builddir)/libguiucsim.a $(top_builddir)/libsim.a $(top_builddir)/libucsimutil.a + $(CXX) $(CXXFLAGS) $(LDFLAGS) $(OBJECTS) $(LIBS) -o $@ + +ifeq ($(dlso_ok),yes) +shared_lib: $(top_builddir)/sst7.so +else +shared_lib: + @$(top_srcdir)/mkecho $(top_builddir) "No st7 shared lib made." + @$(top_srcdir)/mkecho $(top_builddir) "(SHAREDLIB="$(SHAREDLIB)",dl_ok="$(dl_ok)",enable_dlso="$(enable_dlso)")" +endif + +$(top_builddir)/sst7.so: $(OBJECTS_SHARED) + $(CXX) -shared $(LDFLAGS) $(OBJECTS_SHARED) -o $(top_builddir)/sst7.so + +otherlibs: $(top_builddir)/libcmd.a $(top_builddir)/libguiucsim.a $(top_builddir)/libsim.a $(top_builddir)/libucsimutil.a + +$(top_builddir)/libcmd.a: + $(MAKE) -C $(top_builddir)/cmd.src all + +$(top_builddir)/libguiucsim.a: + $(MAKE) -C $(top_builddir)/gui.src checkconf ucsim_lib + +$(top_builddir)/libsim.a: + $(MAKE) -C $(top_builddir)/sim.src all + +$(top_builddir)/libucsimutil.a: + $(MAKE) -C $(top_builddir) -f main.mk + +.cc.o: + $(CXX) $(CXXFLAGS) $(CPPFLAGS) $(TARGET_ARCH) -c $< -o $@ + +.asm.hex: + $(ST7ASM) -l $< -o $@ -e $<.lst + + +# Remaking configuration +# ---------------------- +checkconf: + @if [ -f $(top_builddir)/devel ]; then\ + $(MAKE) -f conf.mk srcdir="$(srcdir)" top_builddir="$(top_builddir)" freshconf;\ + fi + +# End of st7.src/Makefile.in diff --git a/sim/ucsim/st7.src/Makefile.in b/sim/ucsim/st7.src/Makefile.in new file mode 100644 index 0000000..e7ab1ee --- /dev/null +++ b/sim/ucsim/st7.src/Makefile.in @@ -0,0 +1,163 @@ +# +# uCsim st7.src/Makefile +# +# (c) Drotos Daniel, Talker Bt. 1997 +# + +STARTYEAR = 1997 + +SHELL = /bin/sh +CXX = @CXX@ +CPP = @CPP@ +CXXCPP = @CXXCPP@ +RANLIB = @RANLIB@ +INSTALL = @INSTALL@ +STRIP = @STRIP@ +MAKEDEP = @MAKEDEP@ + +top_builddir = @top_builddir@ +top_srcdir = @top_srcdir@ + +transform = @program_transform_name@ + +DEFS = $(subs -DHAVE_CONFIG_H,,@DEFS@) +CPPFLAGS = @CPPFLAGS@ -I$(srcdir) -I$(top_srcdir) -I$(top_builddir) \ + -I$(top_srcdir)/cmd.src -I$(top_srcdir)/sim.src \ + -I$(top_srcdir)/gui.src +CFLAGS = @CFLAGS@ @WALL_FLAG@ +CXXFLAGS = @CXXFLAGS@ @WALL_FLAG@ +LDFLAGS = @LDFLAGS@ +PICOPT = @PICOPT@ +SHAREDLIB = @SHAREDLIB@ + +EXEEXT = @EXEEXT@ + +LIBS = -L$(top_builddir) -lsim -lucsimutil -lguiucsim -lcmd -lsim @LIBS@ +DL = @DL@ +dl_ok = @dl_ok@ + +prefix = @prefix@ +exec_prefix = @exec_prefix@ +bindir = @bindir@ +libdir = @libdir@ +datadir = @datadir@ +datarootdir = @datarootdir@ +includedir = @includedir@ +mandir = @mandir@ +man1dir = $(mandir)/man1 +man2dir = $(mandir)/man2 +infodir = @infodir@ +srcdir = @srcdir@ +VPATH = @srcdir@ + +OBJECTS_SHARED = glob.o \ + inst.o \ + simst7.o st7.o +OBJECTS_EXE = sst7.o +OBJECTS = $(OBJECTS_SHARED) $(OBJECTS_EXE) + +ST7ASM = + +enable_dlso = @enable_dlso@ +dlso_ok = @dlso_ok@ + +#TEST_OBJ = test_bit.hex test_dis.hex test_mov.hex test_jmp.hex \ +# test_arith.hex + +# Compiling entire program or any subproject +# ------------------------------------------ +all: checkconf otherlibs st7.src tests + +tests: $(TEST_OBJ) + + +# Compiling and installing everything and runing test +# --------------------------------------------------- +install: all installdirs + $(INSTALL) sst7$(EXEEXT) $(DESTDIR)$(bindir)/`echo sst7|sed '$(transform)'`$(EXEEXT) + $(STRIP) $(DESTDIR)$(bindir)/`echo sst7|sed '$(transform)'`$(EXEEXT) + + +# Deleting all the installed files +# -------------------------------- +uninstall: + rm -f $(DESTDIR)$(bindir)/`echo sst7|sed '$(transform)'`$(EXEEXT) + + +# Performing self-test +# -------------------- +check: test + +test: + + +# Performing installation test +# ---------------------------- +installcheck: + + +# Creating installation directories +# --------------------------------- +installdirs: + test -d $(DESTDIR)$(bindir) || $(INSTALL) -d $(DESTDIR)$(bindir) + + +# Creating dependencies +# --------------------- +dep: Makefile.dep + +Makefile.dep: $(srcdir)/*.cc $(srcdir)/*.h + $(MAKEDEP) $(CPPFLAGS) $(filter %.cc,$^) >Makefile.dep + +-include Makefile.dep +include $(srcdir)/clean.mk + +# My rules +# -------- +.SUFFIXES: .asm .hex + +st7.src: sst7$(EXEEXT) shared_lib + +sst7$(EXEEXT): $(OBJECTS) $(top_builddir)/libcmd.a $(top_builddir)/libguiucsim.a $(top_builddir)/libsim.a $(top_builddir)/libucsimutil.a + $(CXX) $(CXXFLAGS) $(LDFLAGS) $(OBJECTS) $(LIBS) -o $@ + +ifeq ($(dlso_ok),yes) +shared_lib: $(top_builddir)/sst7.so +else +shared_lib: + @$(top_srcdir)/mkecho $(top_builddir) "No st7 shared lib made." + @$(top_srcdir)/mkecho $(top_builddir) "(SHAREDLIB="$(SHAREDLIB)",dl_ok="$(dl_ok)",enable_dlso="$(enable_dlso)")" +endif + +$(top_builddir)/sst7.so: $(OBJECTS_SHARED) + $(CXX) -shared $(LDFLAGS) $(OBJECTS_SHARED) -o $(top_builddir)/sst7.so + +otherlibs: $(top_builddir)/libcmd.a $(top_builddir)/libguiucsim.a $(top_builddir)/libsim.a $(top_builddir)/libucsimutil.a + +$(top_builddir)/libcmd.a: + $(MAKE) -C $(top_builddir)/cmd.src all + +$(top_builddir)/libguiucsim.a: + $(MAKE) -C $(top_builddir)/gui.src checkconf ucsim_lib + +$(top_builddir)/libsim.a: + $(MAKE) -C $(top_builddir)/sim.src all + +$(top_builddir)/libucsimutil.a: + $(MAKE) -C $(top_builddir) -f main.mk + +.cc.o: + $(CXX) $(CXXFLAGS) $(CPPFLAGS) $(TARGET_ARCH) -c $< -o $@ + +.asm.hex: + $(ST7ASM) -l $< -o $@ -e $<.lst + + +# Remaking configuration +# ---------------------- +checkconf: + @if [ -f $(top_builddir)/devel ]; then\ + $(MAKE) -f conf.mk srcdir="$(srcdir)" top_builddir="$(top_builddir)" freshconf;\ + fi + +# End of st7.src/Makefile.in diff --git a/sim/ucsim/st7.src/clean.mk b/sim/ucsim/st7.src/clean.mk new file mode 100644 index 0000000..c162df3 --- /dev/null +++ b/sim/ucsim/st7.src/clean.mk @@ -0,0 +1,26 @@ +# Deleting all files created by building the program +# -------------------------------------------------- +clean: + rm -f *core *[%~] *.[oa] + rm -f .[a-z]*~ + rm -f sst7$(EXEEXT) + + +# Deleting all files created by configuring or building the program +# ----------------------------------------------------------------- +distclean: clean + rm -f config.cache config.log config.status + rm -f Makefile *.dep + + +# Like clean but some files may still exist +# ----------------------------------------- +mostlyclean: clean + + +# Deleting everything that can reconstructed by this Makefile. It deletes +# everything deleted by distclean plus files created by bison, etc. +# ----------------------------------------------------------------------- +realclean: distclean + +# End of st7.src/clean.mk diff --git a/sim/ucsim/st7.src/conf.mk b/sim/ucsim/st7.src/conf.mk new file mode 100644 index 0000000..0b5bc84 --- /dev/null +++ b/sim/ucsim/st7.src/conf.mk @@ -0,0 +1,10 @@ +# +# Makefile targets to remake configuration +# + +freshconf: Makefile + +Makefile: $(srcdir)/Makefile.in $(top_srcdir)/configure.ac + cd $(top_builddir) && $(SHELL) ./config.status + +# End of st7.src/conf.mk diff --git a/sim/ucsim/st7.src/glob.cc b/sim/ucsim/st7.src/glob.cc new file mode 100644 index 0000000..785d8a9 --- /dev/null +++ b/sim/ucsim/st7.src/glob.cc @@ -0,0 +1,763 @@ +/* + * Simulator of microcontrollers (glob.cc) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#include + +#include "stypes.h" + +/* ST7 instructions described in PM0044 + * + * 19.12.2012 - initial - ready for testing + * + */ + + +/* +%d - direct addressing +%x - extended addressing +%p - pc relative addressing +%b - unsigned byte immediate addressing +%w - unsigned word immediate addressing +%e - unsigned 24bit immediate addressing (extmem) +%s - signed byte immediate +%1 - unsigned byte index offset +%2 - unsigned word index offset +%3 - unsigned 24bit index offset +*/ + +/* uint code, mask; char branch; uchar length; char *mnemonic; */ + +/* vaclavpe - commented out is stuff from STM8 */ + +struct dis_entry disass_st7[]= { +// { 0x0019, 0x00ff, ' ', 2, "adc A,(%1,SP)" }, + { 0x00a9, 0x00ff, ' ', 2, "adc A,%b" }, + { 0x00b9, 0x00ff, ' ', 2, "adc A,%d" }, + { 0x00c9, 0x00ff, ' ', 3, "adc A,%x" }, + { 0x00d9, 0x00ff, ' ', 3, "adc A,(%2,X)" }, + { 0x00e9, 0x00ff, ' ', 2, "adc A,(%1,X)" }, + { 0x00f9, 0x00ff, ' ', 1, "adc A,(X)" }, + +// { 0x001b, 0x00ff, ' ', 2, "add A,(%1,SP)" }, + { 0x00ab, 0x00ff, ' ', 2, "add A,%b" }, + { 0x00bb, 0x00ff, ' ', 2, "add A,%d" }, + { 0x00cb, 0x00ff, ' ', 3, "add A,%x" }, + { 0x00db, 0x00ff, ' ', 3, "add A,(%2,X)" }, + { 0x00eb, 0x00ff, ' ', 2, "add A,(%1,X)" }, + { 0x00fb, 0x00ff, ' ', 1, "add A,(X)" }, +// { 0x005b, 0x00ff, ' ', 2, "add SP,%b" }, + +// { 0x001c, 0x00ff, ' ', 3, "addw X,%w" }, + +// { 0x0014, 0x00ff, ' ', 2, "and A,(%1,SP)" }, + { 0x00a4, 0x00ff, ' ', 2, "and A,%b" }, + { 0x00b4, 0x00ff, ' ', 2, "and A,%d" }, + { 0x00c4, 0x00ff, ' ', 3, "and A,%x" }, + { 0x00d4, 0x00ff, ' ', 3, "and A,(%2,X)" }, + { 0x00e4, 0x00ff, ' ', 2, "and A,(%1,X)" }, + { 0x00f4, 0x00ff, ' ', 1, "and A,(X)" }, + +// { 0x0015, 0x00ff, ' ', 2, "bcp A,(%1,SP)" }, + { 0x00a5, 0x00ff, ' ', 2, "bcp A,%b" }, + { 0x00b5, 0x00ff, ' ', 2, "bcp A,%d" }, + { 0x00c5, 0x00ff, ' ', 3, "bcp A,%x" }, + { 0x00d5, 0x00ff, ' ', 3, "bcp A,(%2,X)" }, + { 0x00e5, 0x00ff, ' ', 2, "bcp A,(%1,X)" }, + { 0x00f5, 0x00ff, ' ', 1, "bcp A,(X)" }, + + { 0x0011, 0x00ff, ' ', 2, "bres %d,#0" }, + { 0x0013, 0x00ff, ' ', 2, "bres %d,#1" }, + { 0x0015, 0x00ff, ' ', 2, "bres %d,#2" }, + { 0x0017, 0x00ff, ' ', 2, "bres %d,#3" }, + { 0x0019, 0x00ff, ' ', 2, "bres %d,#4" }, + { 0x001b, 0x00ff, ' ', 2, "bres %d,#5" }, + { 0x001d, 0x00ff, ' ', 2, "bres %d,#6" }, + { 0x001f, 0x00ff, ' ', 2, "bres %d,#7" }, + + { 0x0010, 0x00ff, ' ', 2, "bset %d,#0" }, + { 0x0012, 0x00ff, ' ', 2, "bset %d,#1" }, + { 0x0014, 0x00ff, ' ', 2, "bset %d,#2" }, + { 0x0016, 0x00ff, ' ', 2, "bset %d,#3" }, + { 0x0018, 0x00ff, ' ', 2, "bset %d,#4" }, + { 0x001a, 0x00ff, ' ', 2, "bset %d,#5" }, + { 0x001c, 0x00ff, ' ', 2, "bset %d,#6" }, + { 0x001e, 0x00ff, ' ', 2, "bset %d,#7" }, + + { 0x0001, 0x00ff, ' ', 3, "bjtf %d,#0,%p" }, + { 0x0003, 0x00ff, ' ', 3, "bjtf %d,#1,%p" }, + { 0x0005, 0x00ff, ' ', 3, "bjtf %d,#2,%p" }, + { 0x0007, 0x00ff, ' ', 3, "bjtf %d,#3,%p" }, + { 0x0009, 0x00ff, ' ', 3, "bjtf %d,#4,%p" }, + { 0x000b, 0x00ff, ' ', 3, "bjtf %d,#5,%p" }, + { 0x000d, 0x00ff, ' ', 3, "bjtf %d,#6,%p" }, + { 0x000f, 0x00ff, ' ', 3, "bjtf %d,#7,%p" }, + + { 0x0000, 0x00ff, ' ', 3, "btjt %d,#0,%p" }, + { 0x0002, 0x00ff, ' ', 3, "btjt %d,#1,%p" }, + { 0x0004, 0x00ff, ' ', 3, "btjt %d,#2,%p" }, + { 0x0006, 0x00ff, ' ', 3, "btjt %d,#3,%p" }, + { 0x0008, 0x00ff, ' ', 3, "btjt %d,#4,%p" }, + { 0x000a, 0x00ff, ' ', 3, "btjt %d,#5,%p" }, + { 0x000c, 0x00ff, ' ', 3, "btjt %d,#6,%p" }, + { 0x000e, 0x00ff, ' ', 3, "btjt %d,#7,%p" }, + + { 0x00bd, 0x00ff, ' ', 2, "call %d", true }, + { 0x00cd, 0x00ff, ' ', 3, "call %x", true }, + { 0x00dd, 0x00ff, ' ', 3, "call (%2,X)", true }, + { 0x00ed, 0x00ff, ' ', 2, "call (%1,X)", true }, + { 0x00fd, 0x00ff, ' ', 1, "call (X)", true }, +// { 0x008d, 0x00ff, ' ', 4, "callf %e" }, + { 0x00ad, 0x00ff, ' ', 2, "callr %p", true }, + +// { 0x008c, 0x00ff, ' ', 1, "ccf" }, + +// { 0x000f, 0x00ff, ' ', 2, "clr (%1,SP)" }, + { 0x003f, 0x00ff, ' ', 2, "clr %d" }, + { 0x004f, 0x00ff, ' ', 1, "clr A" }, + { 0x006f, 0x00ff, ' ', 2, "clr (%1,X)" }, + { 0x007f, 0x00ff, ' ', 1, "clr (X)" }, + { 0x005f, 0x00ff, ' ', 1, "clr X" }, + +// { 0x0011, 0x00ff, ' ', 2, "cp A,(%1,SP)" }, + { 0x00a1, 0x00ff, ' ', 2, "cp A,%b" }, + { 0x00b1, 0x00ff, ' ', 2, "cp A,%d" }, + { 0x00c1, 0x00ff, ' ', 3, "cp A,%x" }, + { 0x00d1, 0x00ff, ' ', 3, "cp A,(%2,X)" }, + { 0x00e1, 0x00ff, ' ', 2, "cp A,(%1,X)" }, + { 0x00f1, 0x00ff, ' ', 1, "cp A,(X)" }, +// { 0x0013, 0x00ff, ' ', 2, "cpw X,(%1,SP)" }, + { 0x00a3, 0x00ff, ' ', 3, "cp X,%w" }, + { 0x00b3, 0x00ff, ' ', 2, "cp X,%d" }, + { 0x00c3, 0x00ff, ' ', 3, "cp X,%x" }, + { 0x00d3, 0x00ff, ' ', 3, "cp X,(%2,X)" }, + { 0x00e3, 0x00ff, ' ', 2, "cp X,(%1,X)" }, + { 0x00f3, 0x00ff, ' ', 1, "cp X,(X)" }, + +// { 0x0003, 0x00ff, ' ', 2, "cpl (%1,SP)" }, + { 0x0033, 0x00ff, ' ', 2, "cpl %d" }, + { 0x0043, 0x00ff, ' ', 1, "cpl A" }, + { 0x0063, 0x00ff, ' ', 2, "cpl (%1,X)" }, + { 0x0073, 0x00ff, ' ', 1, "cpl (X)" }, + { 0x0053, 0x00ff, ' ', 1, "cpl X" }, + +// { 0x000a, 0x00ff, ' ', 2, "dec (%1,SP)" }, + { 0x003a, 0x00ff, ' ', 2, "dec %d" }, + { 0x004a, 0x00ff, ' ', 1, "dec A" }, + { 0x006a, 0x00ff, ' ', 2, "dec (%1,X)" }, + { 0x007a, 0x00ff, ' ', 1, "dec (X)" }, + { 0x005a, 0x00ff, ' ', 1, "dec X" }, + +// { 0x0062, 0x00ff, ' ', 1, "div X,A" }, +// { 0x0065, 0x00ff, ' ', 1, "divw X,Y" }, +// { 0x0031, 0x00ff, ' ', 3, "exg A,%x" }, +// { 0x0041, 0x00ff, ' ', 1, "exg A,XL" }, +// { 0x0051, 0x00ff, ' ', 1, "exgw X,Y" }, +// { 0x0061, 0x00ff, ' ', 1, "exg A,YL" }, + { 0x008e, 0x00ff, ' ', 1, "halt" }, + +// { 0x000c, 0x00ff, ' ', 2, "inc (%1,SP)" }, + { 0x003c, 0x00ff, ' ', 2, "inc %d" }, + { 0x004c, 0x00ff, ' ', 1, "inc A" }, + { 0x006c, 0x00ff, ' ', 2, "inc (%1,X)" }, + { 0x007c, 0x00ff, ' ', 1, "inc (X)" }, + { 0x005c, 0x00ff, ' ', 1, "inc X" }, + + { 0x0080, 0x00ff, ' ', 1, "iret" }, + + { 0x00bc, 0x00ff, ' ', 2, "jp %d" }, + { 0x00cc, 0x00ff, ' ', 3, "jp %x" }, + { 0x00dc, 0x00ff, ' ', 3, "jp (%2,X)" }, + { 0x00ec, 0x00ff, ' ', 2, "jp (%1,X)" }, + { 0x00fc, 0x00ff, ' ', 1, "jp (X)" }, +// { 0x00ad, 0x00ff, ' ', 4, "jpf %e" }, + { 0x0020, 0x00ff, ' ', 2, "jra %p" }, + + { 0x0021, 0x00ff, ' ', 2, "jrf %p" }, + { 0x0022, 0x00ff, ' ', 2, "jrugt %p" }, + { 0x0023, 0x00ff, ' ', 2, "jrule %p" }, + { 0x0024, 0x00ff, ' ', 2, "jruge %p" }, + { 0x0025, 0x00ff, ' ', 2, "jrult %p" }, + { 0x0026, 0x00ff, ' ', 2, "jrne %p" }, + { 0x0027, 0x00ff, ' ', 2, "jreq %p" }, + { 0x0028, 0x00ff, ' ', 2, "jrnh %p" }, + { 0x0029, 0x00ff, ' ', 2, "jrh %p" }, + { 0x002a, 0x00ff, ' ', 2, "jrpl %p" }, + { 0x002b, 0x00ff, ' ', 2, "jrmi %p" }, + { 0x002c, 0x00ff, ' ', 2, "jrnm %p" }, + { 0x002d, 0x00ff, ' ', 2, "jrm %p" }, + { 0x002e, 0x00ff, ' ', 2, "jril %p" }, + { 0x002f, 0x00ff, ' ', 2, "jrih %p" }, + +// { 0x007b, 0x00ff, ' ', 2, "ld A,(%1,SP)" }, + { 0x00a6, 0x00ff, ' ', 2, "ld A,%b" }, + { 0x00b6, 0x00ff, ' ', 2, "ld A,%d" }, + { 0x00c6, 0x00ff, ' ', 3, "ld A,%x" }, + { 0x00d6, 0x00ff, ' ', 3, "ld A,(%2,X)" }, + { 0x00e6, 0x00ff, ' ', 2, "ld A,(%1,X)" }, + { 0x00f6, 0x00ff, ' ', 1, "ld A,(X)" }, +// { 0x006b, 0x00ff, ' ', 2, "ld (%1,SP),A" }, +// { 0x00a7, 0x00ff, ' ', 2, "ld %b,A" }, + { 0x00b7, 0x00ff, ' ', 2, "ld %d,A" }, + { 0x00c7, 0x00ff, ' ', 3, "ld %x,A" }, + { 0x00d7, 0x00ff, ' ', 3, "ld (%2,X),A" }, + { 0x00e7, 0x00ff, ' ', 2, "ld (%1,X),A" }, + { 0x00f7, 0x00ff, ' ', 1, "ld (X),A" }, + { 0x0093, 0x00ff, ' ', 1, "ld X,Y" }, + { 0x0094, 0x00ff, ' ', 1, "ld S,X" }, + { 0x0095, 0x00ff, ' ', 1, "ld S,A" }, + { 0x0096, 0x00ff, ' ', 1, "ld X,S" }, + { 0x0097, 0x00ff, ' ', 1, "ld X,A" }, + { 0x009e, 0x00ff, ' ', 1, "ld A,S" }, + { 0x009f, 0x00ff, ' ', 1, "ld A,X" }, + +// { 0x00a7, 0x00ff, ' ', 2, "ldf (%3,X),A" }, +// { 0x00af, 0x00ff, ' ', 2, "ldf A,(%3,X)" }, +// { 0x00bd, 0x00ff, ' ', 2, "ldf %e,A" }, +// { 0x00bc, 0x00ff, ' ', 2, "ldf A,%e" }, +// { 0x001e, 0x00ff, ' ', 2, "ldw X,(%1,SP)" }, + { 0x00ae, 0x00ff, ' ', 2, "ld X,%b" }, + { 0x00be, 0x00ff, ' ', 2, "ld X,%d" }, + { 0x00ce, 0x00ff, ' ', 3, "ld X,%x" }, + { 0x00de, 0x00ff, ' ', 3, "ld X,(%2,X)" }, + { 0x00ee, 0x00ff, ' ', 2, "ld X,(%1,X)" }, + { 0x00fe, 0x00ff, ' ', 1, "ld X,(X)" }, +// { 0x001f, 0x00ff, ' ', 2, "ldw (%1,SP),X" }, + { 0x00bf, 0x00ff, ' ', 2, "ld %d,X" }, + { 0x00cf, 0x00ff, ' ', 3, "ld %x,X" }, + { 0x00df, 0x00ff, ' ', 3, "ld (%2,X),Y" }, + { 0x00ef, 0x00ff, ' ', 2, "ld (%1,X),Y" }, + { 0x00ff, 0x00ff, ' ', 1, "ld (X),Y" }, +// { 0x0016, 0x00ff, ' ', 2, "ldw Y,(%1,SP)" }, +// { 0x0017, 0x00ff, ' ', 2, "ldw (%1,SP),Y" }, + +// { 0x0035, 0x00ff, ' ', 4, "mov %x,%b" }, +// { 0x0045, 0x00ff, ' ', 3, "mov %d,%d" }, +// { 0x0055, 0x00ff, ' ', 5, "mov %x,%x" }, + { 0x0042, 0x00ff, ' ', 1, "mul X,A" }, + +// { 0x0000, 0x00ff, ' ', 2, "neg (%1,SP)" }, + { 0x0030, 0x00ff, ' ', 2, "neg %d" }, + { 0x0040, 0x00ff, ' ', 1, "neg A" }, + { 0x0060, 0x00ff, ' ', 2, "neg (%1,X)" }, + { 0x0070, 0x00ff, ' ', 1, "neg (X)" }, + { 0x0050, 0x00ff, ' ', 1, "neg X" }, + + { 0x009d, 0x00ff, ' ', 1, "nop" }, + +// { 0x001a, 0x00ff, ' ', 2, "or A,(%1,SP)" }, + { 0x00aa, 0x00ff, ' ', 2, "or A,%b" }, + { 0x00ba, 0x00ff, ' ', 2, "or A,%d" }, + { 0x00ca, 0x00ff, ' ', 3, "or A,%x" }, + { 0x00da, 0x00ff, ' ', 3, "or A,(%2,X)" }, + { 0x00ea, 0x00ff, ' ', 2, "or A,(%1,X)" }, + { 0x00fa, 0x00ff, ' ', 1, "or A,(X)" }, + + { 0x0084, 0x00ff, ' ', 1, "pop A" }, + { 0x0085, 0x00ff, ' ', 1, "pop X" }, + { 0x0086, 0x00ff, ' ', 1, "pop CC" }, +// { 0x0032, 0x00ff, ' ', 3, "pop %x" }, + { 0x0088, 0x00ff, ' ', 1, "push A" }, + { 0x0089, 0x00ff, ' ', 1, "push X" }, + { 0x008a, 0x00ff, ' ', 1, "push CC" }, +// { 0x003b, 0x00ff, ' ', 3, "push %x" }, +// { 0x004b, 0x00ff, ' ', 2, "push %b" }, + + { 0x0098, 0x00ff, ' ', 1, "rcf" }, + { 0x0081, 0x00ff, ' ', 1, "ret" }, +// { 0x0087, 0x00ff, ' ', 1, "retf" }, + { 0x009a, 0x00ff, ' ', 1, "rim" }, + +// { 0x0009, 0x00ff, ' ', 2, "rlc (%1,SP)" }, + { 0x0039, 0x00ff, ' ', 2, "rlc %d" }, + { 0x0049, 0x00ff, ' ', 1, "rlc A" }, + { 0x0069, 0x00ff, ' ', 2, "rlc (%1,X)" }, + { 0x0079, 0x00ff, ' ', 1, "rlc (X)" }, + { 0x0059, 0x00ff, ' ', 1, "rlc X" }, +// { 0x0002, 0x00ff, ' ', 1, "rlwa X,A" }, +// { 0x0006, 0x00ff, ' ', 2, "rrc (%1,SP)" }, + { 0x0036, 0x00ff, ' ', 2, "rrc %d" }, + { 0x0046, 0x00ff, ' ', 1, "rrc A" }, + { 0x0066, 0x00ff, ' ', 2, "rrc (%1,X)" }, + { 0x0076, 0x00ff, ' ', 1, "rrc (X)" }, + { 0x0056, 0x00ff, ' ', 1, "rrc X" }, +// { 0x0001, 0x00ff, ' ', 1, "rrwa X,A" }, + + { 0x009c, 0x00ff, ' ', 1, "rsp" }, + +// { 0x0012, 0x00ff, ' ', 2, "sbc A,(%1,SP)" }, + { 0x00a2, 0x00ff, ' ', 2, "sbc A,%b" }, + { 0x00b2, 0x00ff, ' ', 2, "sbc A,%d" }, + { 0x00c2, 0x00ff, ' ', 3, "sbc A,%x" }, + { 0x00d2, 0x00ff, ' ', 3, "sbc A,(%2,X)" }, + { 0x00e2, 0x00ff, ' ', 2, "sbc A,(%1,X)" }, + { 0x00f2, 0x00ff, ' ', 1, "sbc A,(X)" }, + + { 0x0099, 0x00ff, ' ', 1, "scf" }, + { 0x009b, 0x00ff, ' ', 1, "sim" }, + +// { 0x0008, 0x00ff, ' ', 2, "sla (%1,SP)" }, + { 0x0038, 0x00ff, ' ', 2, "sla %d" }, + { 0x0048, 0x00ff, ' ', 1, "sla A" }, + { 0x0068, 0x00ff, ' ', 2, "sla (%1,X)" }, + { 0x0078, 0x00ff, ' ', 1, "sla (X)" }, + { 0x0058, 0x00ff, ' ', 1, "sla X" }, +// { 0x0007, 0x00ff, ' ', 2, "sra (%1,SP)" }, + { 0x0037, 0x00ff, ' ', 2, "sra %d" }, + { 0x0047, 0x00ff, ' ', 1, "sra A" }, + { 0x0067, 0x00ff, ' ', 2, "sra (%1,X)" }, + { 0x0077, 0x00ff, ' ', 1, "sra (X)" }, + { 0x0057, 0x00ff, ' ', 1, "sra X" }, +// { 0x0004, 0x00ff, ' ', 2, "srl (%1,SP)" }, + { 0x0034, 0x00ff, ' ', 2, "srl %d" }, + { 0x0044, 0x00ff, ' ', 1, "srl A" }, + { 0x0064, 0x00ff, ' ', 2, "srl (%1,X)" }, + { 0x0074, 0x00ff, ' ', 1, "srl (X)" }, + { 0x0054, 0x00ff, ' ', 1, "srl X" }, + +// { 0x0010, 0x00ff, ' ', 2, "sub A,(%1,SP)" }, + { 0x00a0, 0x00ff, ' ', 2, "sub A,%b" }, + { 0x00b0, 0x00ff, ' ', 2, "sub A,%d" }, + { 0x00c0, 0x00ff, ' ', 3, "sub A,%x" }, + { 0x00d0, 0x00ff, ' ', 3, "sub A,(%2,X)" }, + { 0x00e0, 0x00ff, ' ', 2, "sub A,(%1,X)" }, + { 0x00f0, 0x00ff, ' ', 1, "sub A,(X)" }, +// { 0x0052, 0x00ff, ' ', 2, "sub SP,%b" }, + +// { 0x001d, 0x00ff, ' ', 3, "subw X,%w" }, + +// { 0x000e, 0x00ff, ' ', 2, "swap (%1,SP)" }, + { 0x003e, 0x00ff, ' ', 2, "swap %d" }, + { 0x004e, 0x00ff, ' ', 1, "swap A" }, + { 0x006e, 0x00ff, ' ', 2, "swap (%1,X)" }, + { 0x007e, 0x00ff, ' ', 1, "swap (X)" }, + { 0x005e, 0x00ff, ' ', 1, "swapw X" }, + +// { 0x000d, 0x00ff, ' ', 2, "tnz (%1,SP)" }, + { 0x003d, 0x00ff, ' ', 2, "tnz %d" }, + { 0x004d, 0x00ff, ' ', 1, "tnz A" }, + { 0x006d, 0x00ff, ' ', 2, "tnz (%1,X)" }, + { 0x007d, 0x00ff, ' ', 1, "tnz (X)" }, + { 0x005d, 0x00ff, ' ', 1, "tnz X" }, + + { 0x0083, 0x00ff, ' ', 1, "trap", true }, + { 0x008f, 0x00ff, ' ', 1, "wfi" }, + +// { 0x0018, 0x00ff, ' ', 2, "xor A,(%1,SP)" }, + { 0x00a8, 0x00ff, ' ', 2, "xor A,%b" }, + { 0x00b8, 0x00ff, ' ', 2, "xor A,%d" }, + { 0x00c8, 0x00ff, ' ', 3, "xor A,%x" }, + { 0x00d8, 0x00ff, ' ', 3, "xor A,(%2,X)" }, + { 0x00e8, 0x00ff, ' ', 2, "xor A,(%1,X)" }, + { 0x00f8, 0x00ff, ' ', 1, "xor A,(X)" }, + + { 0, 0, 0, 0, NULL } +}; + +struct dis_entry disass_st7_90[]= { + + { 0x00d9, 0x00ff, ' ', 3, "adc A,(%2,Y)" }, + { 0x00e9, 0x00ff, ' ', 2, "adc A,(%1,Y)" }, + { 0x00f9, 0x00ff, ' ', 1, "adc A,(Y)" }, + { 0x00db, 0x00ff, ' ', 3, "add A,(%2,Y)" }, + { 0x00eb, 0x00ff, ' ', 2, "add A,(%1,Y)" }, + { 0x00fb, 0x00ff, ' ', 1, "add A,(Y)" }, + { 0x00d4, 0x00ff, ' ', 3, "and A,(%2,Y)" }, + { 0x00e4, 0x00ff, ' ', 2, "and A,(%1,Y)" }, + { 0x00f4, 0x00ff, ' ', 1, "and A,(Y)" }, + { 0x00d5, 0x00ff, ' ', 3, "bcp A,(%2,Y)" }, + { 0x00e5, 0x00ff, ' ', 2, "bcp A,(%1,Y)" }, + { 0x00f5, 0x00ff, ' ', 1, "bcp A,(Y)" }, + +// { 0x0011, 0x00ff, ' ', 3, "bccm %d,#0" }, +// { 0x0013, 0x00ff, ' ', 3, "bccm %d,#1" }, +// { 0x0015, 0x00ff, ' ', 3, "bccm %d,#2" }, +// { 0x0017, 0x00ff, ' ', 3, "bccm %d,#3" }, +// { 0x0019, 0x00ff, ' ', 3, "bccm %d,#4" }, +// { 0x001b, 0x00ff, ' ', 3, "bccm %d,#5" }, +// { 0x001d, 0x00ff, ' ', 3, "bccm %d,#6" }, +// { 0x001f, 0x00ff, ' ', 3, "bccm %d,#7" }, + +// { 0x0010, 0x00ff, ' ', 3, "bcpl %d,#0" }, +// { 0x0012, 0x00ff, ' ', 3, "bcpl %d,#1" }, +// { 0x0014, 0x00ff, ' ', 3, "bcpl %d,#2" }, +// { 0x0016, 0x00ff, ' ', 3, "bcpl %d,#3" }, +// { 0x0018, 0x00ff, ' ', 3, "bcpl %d,#4" }, +// { 0x001a, 0x00ff, ' ', 3, "bcpl %d,#5" }, +// { 0x001c, 0x00ff, ' ', 3, "bcpl %d,#6" }, +// { 0x001e, 0x00ff, ' ', 3, "bcpl %d,#7" }, + + { 0x00dd, 0x00ff, ' ', 3, "call (%2,Y)", true }, + { 0x00ed, 0x00ff, ' ', 2, "call (%1,Y)", true }, + { 0x00fd, 0x00ff, ' ', 1, "call (Y)", true }, + +// { 0x004f, 0x00ff, ' ', 3, "clr (%2,Y)" }, + { 0x006f, 0x00ff, ' ', 2, "clr (%1,Y)" }, + { 0x007f, 0x00ff, ' ', 1, "clr (Y)" }, + { 0x005f, 0x00ff, ' ', 1, "clr Y" }, + + { 0x00d1, 0x00ff, ' ', 3, "cp A,(%2,Y)" }, + { 0x00e1, 0x00ff, ' ', 2, "cp A,(%1,Y)" }, + { 0x00f1, 0x00ff, ' ', 1, "cp A,(Y)" }, + { 0x00a3, 0x00ff, ' ', 2, "cp Y,%b" }, + { 0x00b3, 0x00ff, ' ', 2, "cp Y,%d" }, + { 0x00c3, 0x00ff, ' ', 3, "cp Y,%x" }, + { 0x00d3, 0x00ff, ' ', 3, "cp Y,(%2,Y)" }, + { 0x00e3, 0x00ff, ' ', 2, "cp Y,(%1,Y)" }, + { 0x00f3, 0x00ff, ' ', 1, "cp Y,(Y)" }, + +// { 0x0043, 0x00ff, ' ', 3, "cpl (%2,Y)" }, + { 0x0063, 0x00ff, ' ', 2, "cpl (%1,Y)" }, + { 0x0073, 0x00ff, ' ', 1, "cpl (Y)" }, + { 0x0053, 0x00ff, ' ', 1, "cpl Y" }, + +// { 0x004a, 0x00ff, ' ', 3, "dec (%2,Y)" }, + { 0x006a, 0x00ff, ' ', 2, "dec (%1,Y)" }, + { 0x007a, 0x00ff, ' ', 1, "dec (Y)" }, + { 0x005a, 0x00ff, ' ', 1, "dec Y" }, + +// { 0x0062, 0x00ff, ' ', 1, "div Y,A" }, + +// { 0x004c, 0x00ff, ' ', 3, "inc (%2,Y)" }, + { 0x006c, 0x00ff, ' ', 2, "inc (%1,Y)" }, + { 0x007c, 0x00ff, ' ', 1, "inc (Y)" }, + { 0x005c, 0x00ff, ' ', 1, "inc Y" }, + + { 0x00dc, 0x00ff, ' ', 3, "jp (%2,Y)" }, + { 0x00ec, 0x00ff, ' ', 2, "jp (%1,Y)" }, + { 0x00fc, 0x00ff, ' ', 1, "jp (Y)" }, + + //{ 0x0028, 0x00ff, ' ', 2, "jrnh %p" }, + //{ 0x0029, 0x00ff, ' ', 2, "jrh %p" }, + //{ 0x002c, 0x00ff, ' ', 2, "jrnm %p" }, + //{ 0x002d, 0x00ff, ' ', 2, "jrm %p" }, + //{ 0x002e, 0x00ff, ' ', 2, "jril %p" }, + //{ 0x002f, 0x00ff, ' ', 2, "jrih %p" }, + + { 0x00d6, 0x00ff, ' ', 3, "ld A,(%2,Y)" }, + { 0x00e6, 0x00ff, ' ', 2, "ld A,(%1,Y)" }, + { 0x00f6, 0x00ff, ' ', 1, "ld A,(Y)" }, + { 0x00d7, 0x00ff, ' ', 3, "ld (%2,Y),A" }, + { 0x00e7, 0x00ff, ' ', 2, "ld (%1,Y),A" }, + { 0x00f7, 0x00ff, ' ', 1, "ld (Y),A" }, + + { 0x0093, 0x00ff, ' ', 1, "ld Y,X" }, + { 0x0094, 0x00ff, ' ', 1, "ld S,Y" }, + { 0x0096, 0x00ff, ' ', 1, "ld Y,S" }, + { 0x0097, 0x00ff, ' ', 1, "ld Y,A" }, + { 0x009f, 0x00ff, ' ', 1, "ld A,Y" }, +// { 0x00a7, 0x00ff, ' ', 2, "ldf (%e,Y),A" }, +// { 0x00af, 0x00ff, ' ', 2, "ldf A,(%e,Y)" }, + { 0x00ae, 0x00ff, ' ', 2, "ld Y,%b" }, + { 0x00be, 0x00ff, ' ', 2, "ld Y,%d" }, + { 0x00ce, 0x00ff, ' ', 3, "ld Y,%x" }, + { 0x00de, 0x00ff, ' ', 3, "ld Y,(%2,Y)" }, + { 0x00ee, 0x00ff, ' ', 2, "ld Y,(%1,Y)" }, + { 0x00fe, 0x00ff, ' ', 1, "ld Y,(Y)" }, + + { 0x00bf, 0x00ff, ' ', 2, "ld %d,Y" }, + { 0x00cf, 0x00ff, ' ', 3, "ld %x,Y" }, + { 0x00df, 0x00ff, ' ', 3, "ld (%2,Y),Y" }, + { 0x00ef, 0x00ff, ' ', 2, "ld (%1,Y),Y" }, + { 0x00ff, 0x00ff, ' ', 1, "ld (Y),Y" }, + + { 0x0042, 0x00ff, ' ', 1, "mul Y,A" }, + +// { 0x0040, 0x00ff, ' ', 3, "neg (%2,Y)" }, + { 0x0060, 0x00ff, ' ', 2, "neg (%1,Y)" }, + { 0x0070, 0x00ff, ' ', 1, "neg (Y)" }, + { 0x0050, 0x00ff, ' ', 1, "neg Y" }, + + { 0x00da, 0x00ff, ' ', 3, "or A,(%2,Y)" }, + { 0x00ea, 0x00ff, ' ', 2, "or A,(%1,Y)" }, + { 0x00fa, 0x00ff, ' ', 1, "or A,(Y)" }, + + { 0x0085, 0x00ff, ' ', 1, "pop Y" }, + { 0x0089, 0x00ff, ' ', 1, "push Y" }, + +// { 0x0049, 0x00ff, ' ', 3, "rlc (%2,Y)" }, + { 0x0069, 0x00ff, ' ', 2, "rlc (%1,Y)" }, + { 0x0079, 0x00ff, ' ', 1, "rlc (Y)" }, + { 0x0059, 0x00ff, ' ', 1, "rlc Y" }, +// { 0x0002, 0x00ff, ' ', 1, "rlwa Y,A" }, +// { 0x0046, 0x00ff, ' ', 3, "rrc (%2,Y)" }, + { 0x0066, 0x00ff, ' ', 2, "rrc (%1,Y)" }, + { 0x0076, 0x00ff, ' ', 1, "rrc (Y)" }, + { 0x0056, 0x00ff, ' ', 1, "rrc Y" }, +// { 0x0001, 0x00ff, ' ', 1, "rrwa Y,A" }, + + { 0x00d2, 0x00ff, ' ', 3, "sbc A,(%2,Y)" }, + { 0x00e2, 0x00ff, ' ', 2, "sbc A,(%1,Y)" }, + { 0x00f2, 0x00ff, ' ', 1, "sbc A,(Y)" }, + +// { 0x0048, 0x00ff, ' ', 3, "sla (%2,Y)" }, + { 0x0068, 0x00ff, ' ', 2, "sla (%1,Y)" }, + { 0x0078, 0x00ff, ' ', 1, "sla (Y)" }, + { 0x0058, 0x00ff, ' ', 1, "sla Y" }, +// { 0x0047, 0x00ff, ' ', 3, "sra (%2,Y)" }, + { 0x0067, 0x00ff, ' ', 2, "sra (%1,Y)" }, + { 0x0077, 0x00ff, ' ', 1, "sra (Y)" }, + { 0x0057, 0x00ff, ' ', 1, "sra Y" }, +// { 0x0044, 0x00ff, ' ', 3, "srl (%2,Y)" }, + { 0x0064, 0x00ff, ' ', 2, "srl (%1,Y)" }, + { 0x0074, 0x00ff, ' ', 1, "srl (Y)" }, + { 0x0054, 0x00ff, ' ', 1, "srl Y" }, + + { 0x00d0, 0x00ff, ' ', 3, "sub A,(%2,Y)" }, + { 0x00e0, 0x00ff, ' ', 2, "sub A,(%1,Y)" }, + { 0x00f0, 0x00ff, ' ', 1, "sub A,(Y)" }, + +// { 0x004e, 0x00ff, ' ', 3, "swap (%2,Y)" }, + { 0x006e, 0x00ff, ' ', 2, "swap (%1,Y)" }, + { 0x007e, 0x00ff, ' ', 1, "swap (Y)" }, + { 0x005e, 0x00ff, ' ', 1, "swap Y" }, + +// { 0x004d, 0x00ff, ' ', 3, "tnz (%2,Y)" }, + { 0x006d, 0x00ff, ' ', 2, "tnz (%1,Y)" }, + { 0x007d, 0x00ff, ' ', 1, "tnz (Y)" }, + { 0x005d, 0x00ff, ' ', 1, "tnz Y" }, + + { 0x00d8, 0x00ff, ' ', 3, "xor A,(%2,Y)" }, + { 0x00e8, 0x00ff, ' ', 2, "xor A,(%1,Y)" }, + { 0x00f8, 0x00ff, ' ', 1, "xor A,(Y)" }, + + { 0, 0, 0, 0, NULL } +}; + +struct dis_entry disass_st7_91[]= { + + { 0x00d9, 0x00ff, ' ', 2, "adc A,([%1.w],Y)" }, + { 0x00e9, 0x00ff, ' ', 2, "adc A,([%1],Y)" }, + { 0x00db, 0x00ff, ' ', 2, "add A,([%1.w],Y)" }, + { 0x00eb, 0x00ff, ' ', 2, "add A,([%1],Y)" }, + { 0x00d4, 0x00ff, ' ', 2, "and A,([%1.w],Y)" }, + { 0x00e4, 0x00ff, ' ', 2, "and A,([%1],Y)" }, + { 0x00d5, 0x00ff, ' ', 2, "bcp A,([%1.w],Y)" }, + { 0x00e5, 0x00ff, ' ', 2, "bcp A,([%1],Y)" }, + { 0x00dd, 0x00ff, ' ', 2, "call ([%1.w],Y)", true }, + { 0x00ed, 0x00ff, ' ', 2, "call ([%1],Y)", true }, + { 0x006f, 0x00ff, ' ', 2, "clr ([%1],Y)" }, + { 0x00d1, 0x00ff, ' ', 2, "cp A,([%1.w],Y)" }, + { 0x00e1, 0x00ff, ' ', 2, "cp A,([%1],Y)" }, + { 0x00b3, 0x00ff, ' ', 2, "cp Y,[%1]" }, + { 0x00c3, 0x00ff, ' ', 2, "cp Y,[%1.w]" }, + { 0x00d3, 0x00ff, ' ', 2, "cp Y,([%1.w],Y)" }, + { 0x00e3, 0x00ff, ' ', 2, "cp Y,([%1],Y)" }, + { 0x0063, 0x00ff, ' ', 2, "cpl ([%1],Y)" }, + { 0x006a, 0x00ff, ' ', 2, "dec ([%1],Y)" }, + { 0x006c, 0x00ff, ' ', 2, "inc ([%1],Y)" }, + { 0x00dc, 0x00ff, ' ', 2, "jp ([%1.w],Y)" }, + { 0x00ec, 0x00ff, ' ', 2, "jp ([%1],Y)" }, + { 0x00d6, 0x00ff, ' ', 2, "ld A,([%1.w],Y)" }, + { 0x00e6, 0x00ff, ' ', 2, "ld A,([%1],Y)" }, + { 0x00d7, 0x00ff, ' ', 2, "ld ([%1.w],Y),A" }, + { 0x00e7, 0x00ff, ' ', 2, "ld ([%1],Y),A" }, +// { 0x00a7, 0x00ff, ' ', 2, "ldf ([%2.e],Y),A" }, +// { 0x00af, 0x00ff, ' ', 2, "ldf A,([%2.e],Y)" }, + { 0x00be, 0x00ff, ' ', 3, "ld Y,[%1]" }, + { 0x00ce, 0x00ff, ' ', 3, "ld Y,[%1.w]" }, + { 0x00de, 0x00ff, ' ', 3, "ld Y,([%1.w],Y)" }, + { 0x00ee, 0x00ff, ' ', 3, "ld Y,([%1],Y)" }, + { 0x00bf, 0x00ff, ' ', 3, "ld [%1],Y" }, + { 0x00cf, 0x00ff, ' ', 3, "ld [%1.w],Y" }, + { 0x00df, 0x00ff, ' ', 3, "ld ([%1.w],Y),Y" }, + { 0x00ef, 0x00ff, ' ', 3, "ld ([%1],Y),Y" }, + { 0x0060, 0x00ff, ' ', 2, "neg ([%1],Y)" }, + { 0x00da, 0x00ff, ' ', 2, "or A,([%1.w],Y)" }, + { 0x00ea, 0x00ff, ' ', 2, "or A,([%1],Y)" }, + { 0x0069, 0x00ff, ' ', 2, "rlc ([%1],Y)" }, + { 0x0066, 0x00ff, ' ', 2, "rrc ([%1],Y)" }, + { 0x00d2, 0x00ff, ' ', 2, "sbc A,([%1.w],Y)" }, + { 0x00e2, 0x00ff, ' ', 2, "sbc A,([%1],Y)" }, + { 0x0068, 0x00ff, ' ', 2, "sla ([%1],Y)" }, + { 0x0067, 0x00ff, ' ', 2, "sra ([%1],Y)" }, + { 0x0064, 0x00ff, ' ', 2, "srl ([%1],Y)" }, + { 0x00d0, 0x00ff, ' ', 2, "sub A,([%1.w],Y)" }, + { 0x00e0, 0x00ff, ' ', 2, "sub A,([%1],Y)" }, + { 0x006e, 0x00ff, ' ', 2, "swap ([%1],Y)" }, + { 0x006d, 0x00ff, ' ', 2, "tnz ([%1],Y)" }, + { 0x00d8, 0x00ff, ' ', 2, "xor A,([%1.w],Y)" }, + { 0x00e8, 0x00ff, ' ', 2, "xor A,([%1],Y)" }, + + { 0, 0, 0, 0, NULL } +}; + +struct dis_entry disass_st7_92[]= { + + { 0x00b9, 0x00ff, ' ', 2, "adc A,[%1]" }, + { 0x00c9, 0x00ff, ' ', 2, "adc A,[%1.w]" }, + { 0x00d9, 0x00ff, ' ', 2, "adc A,([%1.w],X)" }, + { 0x00e9, 0x00ff, ' ', 2, "adc A,([%1],X)" }, + { 0x00bb, 0x00ff, ' ', 2, "add A,[%1]" }, + { 0x00cb, 0x00ff, ' ', 2, "add A,[%1.w]" }, + { 0x00db, 0x00ff, ' ', 2, "add A,([%1.w],X)" }, + { 0x00eb, 0x00ff, ' ', 2, "add A,([%1],X)" }, + { 0x00b4, 0x00ff, ' ', 2, "and A,[%1]" }, + { 0x00c4, 0x00ff, ' ', 2, "and A,[%1.w]" }, + { 0x00d4, 0x00ff, ' ', 2, "and A,([%1.w],X)" }, + { 0x00e4, 0x00ff, ' ', 2, "and A,([%1],X)" }, + { 0x00b5, 0x00ff, ' ', 2, "bcp A,[%1]" }, + { 0x00c5, 0x00ff, ' ', 2, "bcp A,[%1.w]" }, + { 0x00d5, 0x00ff, ' ', 2, "bcp A,([%1.w],X)" }, + { 0x00e5, 0x00ff, ' ', 2, "bcp A,([%1],X)" }, + + { 0x0011, 0x00ff, ' ', 2, "bres [%1],#0" }, + { 0x0013, 0x00ff, ' ', 2, "bres [%1],#1" }, + { 0x0015, 0x00ff, ' ', 2, "bres [%1],#2" }, + { 0x0017, 0x00ff, ' ', 2, "bres [%1],#3" }, + { 0x0019, 0x00ff, ' ', 2, "bres [%1],#4" }, + { 0x001b, 0x00ff, ' ', 2, "bres [%1],#5" }, + { 0x001d, 0x00ff, ' ', 2, "bres [%1],#6" }, + { 0x001f, 0x00ff, ' ', 2, "bres [%1],#7" }, + + { 0x0010, 0x00ff, ' ', 2, "bset [%1],#0" }, + { 0x0012, 0x00ff, ' ', 2, "bset [%1],#1" }, + { 0x0014, 0x00ff, ' ', 2, "bset [%1],#2" }, + { 0x0016, 0x00ff, ' ', 2, "bset [%1],#3" }, + { 0x0018, 0x00ff, ' ', 2, "bset [%1],#4" }, + { 0x001a, 0x00ff, ' ', 2, "bset [%1],#5" }, + { 0x001c, 0x00ff, ' ', 2, "bset [%1],#6" }, + { 0x001e, 0x00ff, ' ', 2, "bset [%1],#7" }, + + { 0x0001, 0x00ff, ' ', 3, "bjtf [%1],#0,%p" }, + { 0x0003, 0x00ff, ' ', 3, "bjtf [%1],#1,%p" }, + { 0x0005, 0x00ff, ' ', 3, "bjtf [%1],#2,%p" }, + { 0x0007, 0x00ff, ' ', 3, "bjtf [%1],#3,%p" }, + { 0x0009, 0x00ff, ' ', 3, "bjtf [%1],#4,%p" }, + { 0x000b, 0x00ff, ' ', 3, "bjtf [%1],#5,%p" }, + { 0x000d, 0x00ff, ' ', 3, "bjtf [%1],#6,%p" }, + { 0x000f, 0x00ff, ' ', 3, "bjtf [%1],#7,%p" }, + + { 0x0000, 0x00ff, ' ', 3, "btjt [%1],#0,%p" }, + { 0x0002, 0x00ff, ' ', 3, "btjt [%1],#1,%p" }, + { 0x0004, 0x00ff, ' ', 3, "btjt [%1],#2,%p" }, + { 0x0006, 0x00ff, ' ', 3, "btjt [%1],#3,%p" }, + { 0x0008, 0x00ff, ' ', 3, "btjt [%1],#4,%p" }, + { 0x000a, 0x00ff, ' ', 3, "btjt [%1],#5,%p" }, + { 0x000c, 0x00ff, ' ', 3, "btjt [%1],#6,%p" }, + { 0x000e, 0x00ff, ' ', 3, "btjt [%1],#7,%p" }, + + { 0x00cd, 0x00ff, ' ', 2, "call [%1]", true }, + { 0x00cd, 0x00ff, ' ', 2, "call [%1.w]", true }, + { 0x00dd, 0x00ff, ' ', 2, "call ([%1.w],X)", true }, + { 0x00dd, 0x00ff, ' ', 2, "call ([%1],X)", true }, + { 0x00ad, 0x00ff, ' ', 2, "callr [%1]", true }, +// { 0x008d, 0x00ff, ' ', 3, "callf [%2.e]", true }, + { 0x003f, 0x00ff, ' ', 2, "clr [%1]" }, + { 0x006f, 0x00ff, ' ', 2, "clr ([%1],X)" }, + { 0x00b1, 0x00ff, ' ', 2, "cp A,[%1]" }, + { 0x00c1, 0x00ff, ' ', 2, "cp A,[%1.w]" }, + { 0x00d1, 0x00ff, ' ', 2, "cp A,([%1.w],X)" }, + { 0x00e1, 0x00ff, ' ', 2, "cp A,([%1],X)" }, + { 0x00b3, 0x00ff, ' ', 2, "cp X,[%1.w]" }, + { 0x00c3, 0x00ff, ' ', 2, "cp X,[%1.w]" }, + { 0x00d3, 0x00ff, ' ', 2, "cp X,([%1.w],X)" }, + { 0x00e3, 0x00ff, ' ', 2, "cp X,([%1.w],X)" }, + { 0x0033, 0x00ff, ' ', 2, "cpl [%1]" }, + { 0x0063, 0x00ff, ' ', 2, "cpl ([%1],X)" }, + { 0x003a, 0x00ff, ' ', 2, "dec [%1]" }, + { 0x006a, 0x00ff, ' ', 2, "dec ([%1],X)" }, + { 0x003c, 0x00ff, ' ', 2, "inc [%1]" }, + { 0x006c, 0x00ff, ' ', 2, "inc ([%1],X)" }, + { 0x00bc, 0x00ff, ' ', 2, "jp [%1]" }, + { 0x00cc, 0x00ff, ' ', 2, "jp [%1.w]" }, + { 0x00dc, 0x00ff, ' ', 2, "jp ([%1.w],X)" }, + { 0x00ec, 0x00ff, ' ', 2, "jp ([%1],X)" }, +// { 0x00ac, 0x00ff, ' ', 3, "jpf [%2.e]" }, + { 0x0020, 0x00ff, ' ', 2, "jra [%1]" }, + + { 0x0021, 0x00ff, ' ', 2, "jrf [%1]" }, + { 0x0022, 0x00ff, ' ', 2, "jrugt [%1]" }, + { 0x0023, 0x00ff, ' ', 2, "jrule [%1]" }, + { 0x0024, 0x00ff, ' ', 2, "jruge [%1]" }, + { 0x0025, 0x00ff, ' ', 2, "jrult [%1]" }, + { 0x0026, 0x00ff, ' ', 2, "jrne [%1]" }, + { 0x0027, 0x00ff, ' ', 2, "jreq [%1]" }, + { 0x0028, 0x00ff, ' ', 2, "jrnh [%1]" }, + { 0x0029, 0x00ff, ' ', 2, "jrh [%1]" }, + { 0x002a, 0x00ff, ' ', 2, "jrpl [%1]" }, + { 0x002b, 0x00ff, ' ', 2, "jrmi [%1]" }, + { 0x002c, 0x00ff, ' ', 2, "jrnm [%1]" }, + { 0x002d, 0x00ff, ' ', 2, "jrm [%1]" }, + { 0x002e, 0x00ff, ' ', 2, "jril [%1]" }, + { 0x002f, 0x00ff, ' ', 2, "jrih [%1]" }, + + { 0x00b6, 0x00ff, ' ', 2, "ld A,[%1]" }, + { 0x00c6, 0x00ff, ' ', 2, "ld A,[%1.w]" }, + { 0x00d6, 0x00ff, ' ', 2, "ld A,([%1.w],X)" }, + { 0x00e6, 0x00ff, ' ', 2, "ld A,([%1],X)" }, + { 0x00b7, 0x00ff, ' ', 2, "ld [%1],A" }, + { 0x00c7, 0x00ff, ' ', 2, "ld [%1.w],A" }, + { 0x00d7, 0x00ff, ' ', 2, "ld ([%1.w],X),A" }, + { 0x00e7, 0x00ff, ' ', 2, "ld ([%1],X),A" }, +// { 0x00a7, 0x00ff, ' ', 2, "ldf ([%2.e],X),A" }, +// { 0x00af, 0x00ff, ' ', 2, "ldf A,([%2.e],X)" }, + { 0x00be, 0x00ff, ' ', 2, "ld X,[%1]" }, + { 0x00ce, 0x00ff, ' ', 2, "ld X,[%1.w]" }, + { 0x00de, 0x00ff, ' ', 2, "ld X,([%1.w],X)" }, + { 0x00ee, 0x00ff, ' ', 2, "ld X,([%1],X)" }, + { 0x00bf, 0x00ff, ' ', 2, "ld [%1],X" }, + { 0x00cf, 0x00ff, ' ', 2, "ld [%1.w],X" }, + { 0x00df, 0x00ff, ' ', 2, "ld ([%1.w],X),X" }, + { 0x00ef, 0x00ff, ' ', 2, "ld ([%1],X),X" }, + + { 0x0030, 0x00ff, ' ', 2, "neg [%1]" }, + { 0x0060, 0x00ff, ' ', 2, "neg ([%1],X)" }, + { 0x00ba, 0x00ff, ' ', 2, "or A,[%1]" }, + { 0x00ca, 0x00ff, ' ', 2, "or A,[%1.w]" }, + { 0x00da, 0x00ff, ' ', 2, "or A,([%1.w],X)" }, + { 0x00ea, 0x00ff, ' ', 2, "or A,([%1],X)" }, + { 0x0039, 0x00ff, ' ', 2, "rlc [%1]" }, + { 0x0069, 0x00ff, ' ', 2, "rlc ([%1],X)" }, + { 0x0036, 0x00ff, ' ', 2, "rrc [%1]" }, + { 0x0066, 0x00ff, ' ', 2, "rrc ([%1],X)" }, + { 0x00b2, 0x00ff, ' ', 2, "sbc A,[%1]" }, + { 0x00c2, 0x00ff, ' ', 2, "sbc A,[%1.w]" }, + { 0x00d2, 0x00ff, ' ', 2, "sbc A,([%1.w],X)" }, + { 0x00e2, 0x00ff, ' ', 2, "sbc A,([%1],X)" }, + { 0x0038, 0x00ff, ' ', 2, "sla [%1]" }, + { 0x0068, 0x00ff, ' ', 2, "sla ([%1],X)" }, + { 0x0037, 0x00ff, ' ', 2, "sra [%1]" }, + { 0x0067, 0x00ff, ' ', 2, "sra ([%1],X)" }, + { 0x0034, 0x00ff, ' ', 2, "srl [%1]" }, + { 0x0064, 0x00ff, ' ', 2, "srl ([%1],X)" }, + { 0x00b0, 0x00ff, ' ', 2, "sub A,[%1]" }, + { 0x00c0, 0x00ff, ' ', 2, "sub A,[%1.w]" }, + { 0x00d0, 0x00ff, ' ', 2, "sub A,([%1.w],X)" }, + { 0x00e0, 0x00ff, ' ', 2, "sub A,([%1],X)" }, + { 0x003e, 0x00ff, ' ', 2, "swap [%1]" }, + { 0x006e, 0x00ff, ' ', 2, "swap ([%1],X)" }, + { 0x003d, 0x00ff, ' ', 2, "tnz [%1]" }, + { 0x006d, 0x00ff, ' ', 2, "tnz ([%1],X)" }, + { 0x00b8, 0x00ff, ' ', 2, "xor A,[%1]" }, + { 0x00c8, 0x00ff, ' ', 2, "xor A,[%1.w]" }, + { 0x00d8, 0x00ff, ' ', 2, "xor A,([%1.w],X)" }, + { 0x00e8, 0x00ff, ' ', 2, "xor A,([%1],X)" }, + + { 0, 0, 0, 0, NULL } +}; + +/* glob.cc */ diff --git a/sim/ucsim/st7.src/glob.h b/sim/ucsim/st7.src/glob.h new file mode 100644 index 0000000..3766560 --- /dev/null +++ b/sim/ucsim/st7.src/glob.h @@ -0,0 +1,44 @@ +/* + * Simulator of microcontrollers (glob.h) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#ifndef GLOB_HEADER +#define GLOB_HEADER + +#include "stypes.h" + + +extern struct dis_entry disass_st7[]; + +extern struct dis_entry disass_st7_90[]; + +extern struct dis_entry disass_st7_91[]; + +extern struct dis_entry disass_st7_92[]; + +#endif + +/* End of st7.src/glob.h */ diff --git a/sim/ucsim/st7.src/inst.cc b/sim/ucsim/st7.src/inst.cc new file mode 100644 index 0000000..3d499de --- /dev/null +++ b/sim/ucsim/st7.src/inst.cc @@ -0,0 +1,1023 @@ +/* + * Simulator of microcontrollers (inst.cc) + * + * st7 code base from Vaclav Peroutka vaclavpe@users.sourceforge.net + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#include "ddconfig.h" +#include "stdio.h" +#include + +// local +#include "st7cl.h" +#include "regsst7.h" +#include "st7mac.h" + +unsigned int +cl_st7::fetchea(t_mem code, unsigned char prefix) +{ + unsigned int resaddr; + unsigned int ftc; //because of get2() MACRO!!!!!! +// unsigned int ftc, gt; +// ftc = fetch(); +// gt = get1(ftc); + +// printf("******************** fetchea() start PC= 0x%04x, prefix = 0x%02x, code = 0x%02x \n", PC, prefix, code); + + switch ((code >> 4) & 0x0f) { + + case 0xb: + if ( 0 == prefix) { // short direct + resaddr = fetch(); + } else if ( 0x92 == prefix) { // short indirect - pointer + resaddr = get1(fetch()); + } else { + resaddr = ( resHALT); + } + break; + + case 0xc: + if ( 0 == prefix) { // long direct + resaddr = fetch2(); + } else if ( 0x92 == prefix) { // long indirect - pointer is under 0x100 + ftc = fetch(); + resaddr = get2(ftc); + } else { + resaddr = ( resHALT); + } + break; + + case 0xd: + if ( 0 == prefix) { // long offset with X reg + resaddr = (fetch2()+regs.X); + } else if ( 0x90 == prefix) { // long offset with Y reg + resaddr = (fetch2()+regs.Y); + } else if ( 0x91 == prefix) { // pointer to long offset with Y + ftc = fetch(); + resaddr = (get2(ftc)+regs.Y); + } else if ( 0x92 == prefix) { // pointer to long offset with X + ftc = fetch(); + resaddr = (get2(ftc)+regs.X); + } else { + resaddr =( resHALT); + } + break; + + case 0xe: + if ( 0 == prefix) { // short offset with X + resaddr = (fetch()+regs.X); + } else if ( 0x90 == prefix) { // short offset with Y + resaddr = (fetch()+regs.Y); + } else if ( 0x91 == prefix) { // pointer to short offset with Y + resaddr = (get1(fetch())+regs.Y); + } else if ( 0x92 == prefix) { // pointer to short offset with X + resaddr = (get1(fetch())+regs.X); + } else { + resaddr =( resHALT); + } + break; + + case 0xf: + if ( 0 == prefix) { + resaddr = regs.X; // X index + } else if ( 0x90 == prefix) { + resaddr = regs.Y; // Y index + } else { + resaddr =( resHALT); + } + break; + + default: + resaddr =(resHALT); + break; + } +// printf("******************** fetchea() end - resaddr=0x%04x, PC=0x%04x\n", resaddr, PC); + return resaddr; +} + + +int +cl_st7::get_dest(t_mem code, unsigned char prefix) +{ + int resaddr; +// printf("******************** get_dest() start PC= 0x%04x, prefix = 0x%02x, code = 0x%02x \n", PC, prefix, code); + + switch ((code >> 4) & 0x0f) { + + case 0x3: + if ( 0 == prefix) { // short direct + resaddr = fetch(); + } else if ( 0x92 == prefix) { // short indirect - pointer + resaddr = get1(fetch()); + } else { + resaddr = ( resHALT); + } + break; + + case 0x6: + if ( 0 == prefix) { // short offset with X + resaddr = (fetch()+regs.X); + } else if ( 0x90 == prefix) { // short offset with Y + resaddr = (fetch()+regs.Y); + } else if ( 0x91 == prefix) { // pointer to short offset with Y + resaddr = (get1(fetch())+regs.Y); + } else if ( 0x92 == prefix) { // pointer to short offset with X + resaddr = (get1(fetch())+regs.X); + } else { + resaddr =( resHALT); + } + break; + + case 0x7: + if ( 0 == prefix) { // X index + resaddr = regs.X; + } else if ( 0x90 == prefix) { // Y index + resaddr = regs.Y; + } else { + resaddr =( resHALT); + } + break; + + default: + resaddr =(resHALT); + break; + } +// printf("******************** get_dest() end - resaddr=0x%04x, PC=0x%04x\n", resaddr, PC); + return resaddr; +} + +/***************************************************************************** + * + * + * + ***************************************************************************** + */ + +int +cl_st7::inst_adc(t_mem code, unsigned char prefix) +{ + int result, operand1, operand2; + int carryin = (regs.CC & BIT_C)!=0; + + operand1 = regs.A; + operand2 = OPERAND(code, prefix); + result = operand1 + operand2 + carryin; + +// printf("******************** adc() op1 = 0x%02x, op2=0x%02x , res=0x%02x \n", operand1, operand2, result); + + FLAG_ASSIGN (BIT_Z, (result & 0xff) == 0); + FLAG_ASSIGN (BIT_C, 0x100 & result); + FLAG_ASSIGN (BIT_N, 0x80 & result); + FLAG_ASSIGN (BIT_H, 0x10 & (operand1 ^ operand2 ^ result)); + + regs.A = result & 0xff; + return(resGO); +} + +int +cl_st7::inst_add(t_mem code, unsigned char prefix) +{ + int result, operand1, operand2; + + operand1 = regs.A; + operand2 = OPERAND(code, prefix); + result = operand1 + operand2; + +// printf("******************** adc() op1 = 0x%02x, op2=0x%02x , res=0x%02x \n", operand1, operand2, result); + + FLAG_ASSIGN (BIT_Z, (result & 0xff) == 0); + FLAG_ASSIGN (BIT_C, 0x100 & result); + FLAG_ASSIGN (BIT_N, 0x80 & result); + FLAG_ASSIGN (BIT_H, 0x10 & (operand1 ^ operand2 ^ result)); + + regs.A = result & 0xff; + return(resGO); +} + +int +cl_st7::inst_and(t_mem code, unsigned char prefix) +{ + int operand2; + + operand2 = OPERAND(code, prefix); + regs.A = regs.A & operand2; + + FLAG_ASSIGN (BIT_Z, (regs.A & 0xff) == 0); + FLAG_ASSIGN (BIT_N, 0x80 & regs.A); + + return(resGO); +} + +int +cl_st7::inst_bcp(t_mem code, unsigned char prefix) +{ + int operand2, opresult; + + operand2 = OPERAND(code, prefix); + opresult = regs.A & operand2; + + FLAG_ASSIGN (BIT_Z, (opresult & 0xff) == 0); + FLAG_ASSIGN (BIT_N, 0x80 & opresult); + + return(resGO); +} + +int +cl_st7::inst_bresbset(t_mem code, unsigned char prefix) +{ + int ea = fetch(); + unsigned char dbyte = get1( ea); + + if (code & 0x01) { // bres + char pos = (code - 0x11) >> 1; + dbyte = dbyte & (~(1<> 1; + dbyte = dbyte | (1<> 1; + if(!( dbyte & (1<> 1; + if ( dbyte & (1<>1) & 7) { + case 0: // JRA / JRF + taken = 1; + break; + case 1: // JRUGT / JRULE + taken = !(regs.CC & (BIT_C | BIT_Z)); + break; + case 2: // JRUGE / JRC + taken = !(regs.CC & BIT_C); + break; + case 3: // JRNE / JREQ + taken = !(regs.CC & BIT_Z); + break; + case 4: // JRNH / JRH + taken = !(regs.CC & BIT_H); + break; + case 5: // JRPL / JRMI + taken = !(regs.CC & BIT_N); + break; + case 6: // JRNM / JRM + taken = !(regs.CC & BIT_I); + break; + case 7: // JRIL - interrupt low - no means to test this ??? + taken = 1; + + default: + return(resHALT); + } + + if (code & 1) + taken = ! taken; + + if (prefix == 0x00) { // direct jump relative + ofs = fetch(); + } else if (prefix == 0x92) { // pointer jump relative + ofs = get1(fetch()); + } else { + return (resHALT); + } + + if (taken) + PC += ofs; + + return(resGO); +} + +int +cl_st7::inst_ldxy(t_mem code, unsigned char prefix) +{ + int operand; + + operand = OPERAND(code, prefix); + +// FLAG_ASSIGN (BIT_Z, (result & 0xff) == 0); +// FLAG_ASSIGN (BIT_C, 0x100 & result); +// FLAG_ASSIGN (BIT_N, 0x80 & result); +// FLAG_ASSIGN (BIT_H, 0x10 & (operand1 ^ operand2 ^ result)); + + if ((prefix == 0x90) || (prefix == 0x91)) { + regs.Y = operand; + } else { + regs.X = operand; + } + + return(resGO); +} + +int +cl_st7::inst_lda(t_mem code, unsigned char prefix) +{ + int operand; + + operand = OPERAND(code, prefix); + +// FLAG_ASSIGN (BIT_Z, (result & 0xff) == 0); +// FLAG_ASSIGN (BIT_C, 0x100 & result); +// FLAG_ASSIGN (BIT_N, 0x80 & result); +// FLAG_ASSIGN (BIT_H, 0x10 & (operand1 ^ operand2 ^ result)); + + regs.A = operand; + + return(resGO); +} + +int +cl_st7::inst_lddst(t_mem code, unsigned char prefix) +{ + unsigned int opaddr; + + opaddr = fetchea(code,prefix); + + FLAG_ASSIGN (BIT_Z, (regs.A & 0xff) == 0); + FLAG_ASSIGN (BIT_N, 0x80 & regs.A); + + store1(opaddr, regs.A); + + return(resGO); +} + +int +cl_st7::inst_ldxydst(t_mem code, unsigned char prefix) +{ + unsigned int opaddr; + + opaddr = fetchea(code,prefix); + + if ((prefix == 0x90) || (prefix == 0x91)) { + FLAG_ASSIGN (BIT_Z, (regs.Y & 0xff) == 0); + FLAG_ASSIGN (BIT_N, 0x80 & regs.Y); + + store1(opaddr, regs.Y); + } else { + FLAG_ASSIGN (BIT_Z, (regs.X & 0xff) == 0); + FLAG_ASSIGN (BIT_N, 0x80 & regs.X); + + store1(opaddr, regs.X); + } + + return(resGO); +} + + + +int +cl_st7::inst_neg(t_mem code, unsigned char prefix) +{ + int operand; + unsigned int opaddr = 0xffff; + + if ((code&0xf0)==0x40) { + operand = regs.A; + } else if (((code&0xf0)==0x50) &&(prefix == 0x00)) { + operand = regs.X; + } else if (((code&0xf0)==0x50) &&(prefix == 0x90)) { + operand = regs.Y; + } else { + opaddr = get_dest(code,prefix); + operand = get1(opaddr); + } + + operand ^= 0xff; + operand++; + + FLAG_ASSIGN (BIT_Z, (operand & 0xff) == 0); + FLAG_ASSIGN (BIT_C, operand); + if (operand == 0x80) { + FLAG_SET (BIT_N); + } else { + FLAG_CLEAR (BIT_N); + } + + if ((code&0xf0)==0x40) { + regs.A = operand; + } else if (((code&0xf0)==0x50) &&(prefix == 0x00)) { + regs.X = operand; + } else if (((code&0xf0)==0x50) &&(prefix == 0x90)) { + regs.Y = operand; + } else { + //printf("******************** inst_neg() end - addr=0x%04x, val=0x%02x\n", opaddr, operand); + store1(opaddr, operand); + } + + return(resGO); +} + +int +cl_st7::inst_or(t_mem code, unsigned char prefix) +{ + int result, operand1, operand2; + + operand1 = regs.A; + operand2 = OPERAND(code, prefix); + result = operand1 | operand2; + + FLAG_ASSIGN (BIT_Z, (result & 0xff) == 0); + //FLAG_ASSIGN (BIT_C, 0x100 & result); + FLAG_ASSIGN (BIT_N, 0x80 & result); + //FLAG_ASSIGN (BIT_H, 0x10 & (operand1 ^ operand2 ^ result)); + + regs.A = result & 0xff; + return(resGO); +} + +int +cl_st7::inst_rlc(t_mem code, unsigned char prefix) +{ + int operand; + unsigned int opaddr = 0xffff; + + if ((code&0xf0)==0x40) { + operand = regs.A; + } else if (((code&0xf0)==0x50) &&(prefix == 0x00)) { + operand = regs.X; + } else if (((code&0xf0)==0x50) &&(prefix == 0x90)) { + operand = regs.Y; + } else { + opaddr = get_dest(code,prefix); + operand = get1(opaddr); + } + + operand <<= 0x1; + + if (regs.CC & BIT_C) { + operand++; + } + + FLAG_ASSIGN (BIT_Z, (operand & 0xff) == 0); + FLAG_ASSIGN (BIT_C, (operand & 0x100)); + if (operand == 0x80) { + FLAG_SET (BIT_N); + } else { + FLAG_CLEAR (BIT_N); + } + + if ((code&0xf0)==0x40) { + regs.A = operand; + } else if (((code&0xf0)==0x50) &&(prefix == 0x00)) { + regs.X = operand; + } else if (((code&0xf0)==0x50) &&(prefix == 0x90)) { + regs.Y = operand; + } else { + store1(opaddr, operand); + } + + return(resGO); +} + +int +cl_st7::inst_rrc(t_mem code, unsigned char prefix) +{ + int operand, opres; + unsigned int opaddr = 0xffff; + + if ((code&0xf0)==0x40) { + operand = regs.A; + } else if (((code&0xf0)==0x50) &&(prefix == 0x00)) { + operand = regs.X; + } else if (((code&0xf0)==0x50) &&(prefix == 0x90)) { + operand = regs.Y; + } else { + opaddr = get_dest(code,prefix); + operand = get1(opaddr); + } + + opres = operand >> 1; + + if (regs.CC & BIT_C) { + opres |= 0x80; + } + + FLAG_ASSIGN (BIT_Z, (opres & 0xff) == 0); + FLAG_ASSIGN (BIT_C, (operand & 0x1)); + if (opres == 0x80) { + FLAG_SET (BIT_N); + } else { + FLAG_CLEAR (BIT_N); + } + + if ((code&0xf0)==0x40) { + regs.A = opres; + } else if (((code&0xf0)==0x50) &&(prefix == 0x00)) { + regs.X = opres; + } else if (((code&0xf0)==0x50) &&(prefix == 0x90)) { + regs.Y = opres; + } else { + store1(opaddr, opres); + } + + return(resGO); +} + +int +cl_st7::inst_sbc(t_mem code, unsigned char prefix) +{ + int result, operand1, operand2; + + operand1 = regs.A; + operand2 = OPERAND(code, prefix); + result = operand1 - operand2; + + if (regs.CC & BIT_C) { + result--; + } + + FLAG_ASSIGN (BIT_Z, (result & 0xff) == 0); + FLAG_ASSIGN (BIT_C, 0x100 & result); + FLAG_ASSIGN (BIT_N, 0x80 & result); + //FLAG_ASSIGN (BIT_H, 0x10 & (operand1 ^ operand2 ^ result)); + + regs.A = result & 0xff; + return(resGO); +} + +int +cl_st7::inst_sll(t_mem code, unsigned char prefix) +{ + int operand, opres; + unsigned int opaddr = 0xffff; + + if ((code&0xf0)==0x40) { + operand = regs.A; + } else if (((code&0xf0)==0x50) &&(prefix == 0x00)) { + operand = regs.X; + } else if (((code&0xf0)==0x50) &&(prefix == 0x90)) { + operand = regs.Y; + } else { + opaddr = get_dest(code,prefix); + operand = get1(opaddr); + } + + opres = operand << 1; + + FLAG_ASSIGN (BIT_Z, (opres & 0xff) == 0); + FLAG_ASSIGN (BIT_C, (opres & 0x100)); + if (opres == 0x80) { + FLAG_SET (BIT_N); + } else { + FLAG_CLEAR (BIT_N); + } + + if ((code&0xf0)==0x40) { + regs.A = opres; + } else if (((code&0xf0)==0x50) &&(prefix == 0x00)) { + regs.X = opres; + } else if (((code&0xf0)==0x50) &&(prefix == 0x90)) { + regs.Y = opres; + } else { + store1(opaddr, opres); + } + + return(resGO); +} + +int +cl_st7::inst_sra(t_mem code, unsigned char prefix) +{ + int operand, opres; + unsigned int opaddr = 0xffff; + + if ((code&0xf0)==0x40) { + operand = regs.A; + } else if (((code&0xf0)==0x50) &&(prefix == 0x00)) { + operand = regs.X; + } else if (((code&0xf0)==0x50) &&(prefix == 0x90)) { + operand = regs.Y; + } else { + opaddr = get_dest(code,prefix); + operand = get1(opaddr); + } + + opres = operand >> 1; + + if (opres > 0x3f) { // copy bit6 to bit7 + opres |= 0x80; + } + + FLAG_ASSIGN (BIT_Z, (opres & 0xff) == 0); + FLAG_ASSIGN (BIT_C, (operand & 0x1)); + if (opres == 0x80) { + FLAG_SET (BIT_N); + } else { + FLAG_CLEAR (BIT_N); + } + + if ((code&0xf0)==0x40) { + regs.A = opres; + } else if (((code&0xf0)==0x50) &&(prefix == 0x00)) { + regs.X = opres; + } else if (((code&0xf0)==0x50) &&(prefix == 0x90)) { + regs.Y = opres; + } else { + store1(opaddr, opres); + } + + return(resGO); +} + +int +cl_st7::inst_srl(t_mem code, unsigned char prefix) +{ + int operand, opres; + unsigned int opaddr = 0xffff; + + if ((code&0xf0)==0x40) { + operand = regs.A; + } else if (((code&0xf0)==0x50) &&(prefix == 0x00)) { + operand = regs.X; + } else if (((code&0xf0)==0x50) &&(prefix == 0x90)) { + operand = regs.Y; + } else { + opaddr = get_dest(code,prefix); + operand = get1(opaddr); + } + + opres = operand >> 1; + + FLAG_ASSIGN (BIT_Z, (opres & 0xff) == 0); + FLAG_ASSIGN (BIT_C, (operand & 0x1)); + if (opres == 0x80) { + FLAG_SET (BIT_N); + } else { + FLAG_CLEAR (BIT_N); + } + + if ((code&0xf0)==0x40) { + regs.A = opres; + } else if (((code&0xf0)==0x50) &&(prefix == 0x00)) { + regs.X = opres; + } else if (((code&0xf0)==0x50) &&(prefix == 0x90)) { + regs.Y = opres; + } else { + store1(opaddr, opres); + } + + return(resGO); +} + +int +cl_st7::inst_sub(t_mem code, unsigned char prefix) +{ + int result, operand1, operand2; + + operand1 = regs.A; + operand2 = OPERAND(code, prefix); + result = operand1 - operand2; + + FLAG_ASSIGN (BIT_Z, (result & 0xff) == 0); + FLAG_ASSIGN (BIT_C, 0x100 & result); + FLAG_ASSIGN (BIT_N, 0x80 & result); + //FLAG_ASSIGN (BIT_H, 0x10 & (operand1 ^ operand2 ^ result)); + + regs.A = result & 0xff; + return(resGO); +} + +int +cl_st7::inst_swap(t_mem code, unsigned char prefix) +{ + int operand, opres; + unsigned int opaddr = 0xffff; + + if ((code&0xf0)==0x40) { + operand = regs.A; + } else if (((code&0xf0)==0x50) &&(prefix == 0x00)) { + operand = regs.X; + } else if (((code&0xf0)==0x50) &&(prefix == 0x90)) { + operand = regs.Y; + } else { + opaddr = get_dest(code,prefix); + operand = get1(opaddr); + } + + opres = operand << 4; + opres |= (operand >> 4); + + + FLAG_ASSIGN (BIT_Z, (opres & 0xff) == 0); + if (opres == 0x80) { + FLAG_SET (BIT_N); + } else { + FLAG_CLEAR (BIT_N); + } + + if ((code&0xf0)==0x40) { + regs.A = opres; + } else if (((code&0xf0)==0x50) &&(prefix == 0x00)) { + regs.X = opres; + } else if (((code&0xf0)==0x50) &&(prefix == 0x90)) { + regs.Y = opres; + } else { + store1(opaddr, opres); + } + + return(resGO); +} + +int +cl_st7::inst_tnz(t_mem code, unsigned char prefix) +{ + int operand; + unsigned int opaddr = 0xffff; + + if ((code&0xf0)==0x40) { + operand = regs.A; + } else if (((code&0xf0)==0x50) &&(prefix == 0x00)) { + operand = regs.X; + } else if (((code&0xf0)==0x50) &&(prefix == 0x90)) { + operand = regs.Y; + } else { + opaddr = get_dest(code,prefix); + operand = get1(opaddr); + } + + FLAG_ASSIGN (BIT_Z, (operand & 0xff) == 0); + if (operand == 0x80) { + FLAG_SET (BIT_N); + } else { + FLAG_CLEAR (BIT_N); + } + + return(resGO); +} + +int +cl_st7::inst_xor(t_mem code, unsigned char prefix) +{ + int result, operand1, operand2; + + operand1 = regs.A; + operand2 = OPERAND(code, prefix); + result = operand1 ^ operand2; + + FLAG_ASSIGN (BIT_Z, (result & 0xff) == 0); + FLAG_ASSIGN (BIT_N, 0x80 & result); + + regs.A = result & 0xff; + return(resGO); +} + +/* End of st7.src/inst.cc */ diff --git a/sim/ucsim/st7.src/instcl.h b/sim/ucsim/st7.src/instcl.h new file mode 100644 index 0000000..26f04d9 --- /dev/null +++ b/sim/ucsim/st7.src/instcl.h @@ -0,0 +1,39 @@ +/* st7.src/instcl.h */ + + //virtual void incx(void); + virtual unsigned int fetchea(t_mem code, unsigned char prefix); + virtual int get_dest(t_mem code, unsigned char prefix); + + virtual int inst_adc(t_mem code, unsigned char prefix); + virtual int inst_add(t_mem code, unsigned char prefix); + virtual int inst_and(t_mem code, unsigned char prefix); + virtual int inst_bcp(t_mem code, unsigned char prefix); + virtual int inst_bresbset(t_mem code, unsigned char prefix); + virtual int inst_btjfbtjt(t_mem code, unsigned char prefix); + virtual int inst_call(t_mem code, unsigned char prefix); + virtual int inst_callr(t_mem code, unsigned char prefix); + virtual int inst_clr(t_mem code, unsigned char prefix); + virtual int inst_cp(t_mem code, unsigned char prefix); + virtual int inst_cpxy(t_mem code, unsigned char prefix); + virtual int inst_cpl(t_mem code, unsigned char prefix); + virtual int inst_dec(t_mem code, unsigned char prefix); + virtual int inst_inc(t_mem code, unsigned char prefix); + virtual int inst_jr(t_mem code, unsigned char prefix); + virtual int inst_lda(t_mem code, unsigned char prefix); + virtual int inst_ldxy(t_mem code, unsigned char prefix); + virtual int inst_lddst(t_mem code, unsigned char prefix); + virtual int inst_ldxydst(t_mem code, unsigned char prefix); + virtual int inst_neg(t_mem code, unsigned char prefix); + virtual int inst_or(t_mem code, unsigned char prefix); + virtual int inst_rlc(t_mem code, unsigned char prefix); + virtual int inst_rrc(t_mem code, unsigned char prefix); + virtual int inst_sbc(t_mem code, unsigned char prefix); + virtual int inst_sll(t_mem code, unsigned char prefix); + virtual int inst_sra(t_mem code, unsigned char prefix); + virtual int inst_srl(t_mem code, unsigned char prefix); + virtual int inst_sub(t_mem code, unsigned char prefix); + virtual int inst_swap(t_mem code, unsigned char prefix); + virtual int inst_tnz(t_mem code, unsigned char prefix); + virtual int inst_xor(t_mem code, unsigned char prefix); + +/* End of st7.src/instcl.h */ diff --git a/sim/ucsim/st7.src/regsst7.h b/sim/ucsim/st7.src/regsst7.h new file mode 100644 index 0000000..67e7c9b --- /dev/null +++ b/sim/ucsim/st7.src/regsst7.h @@ -0,0 +1,61 @@ +/* + * Simulator of microcontrollers (regsst7.h) + * + * some z80 code base from Karl Bongers karl@turbobit.com + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#ifndef REGST7_HEADER +#define REGST7_HEADER + +#include "ddconfig.h" + + +struct t_regs +{ + u8_t A; + u8_t X; + u8_t Y; + u16_t SP; + u8_t CC; + u8_t VECTOR; +}; + +#define BIT_C 0x01 // carry status(out of bit 7) +#define BIT_Z 0x02 // zero status, 1=zero, 0=nonzero +#define BIT_N 0x04 // sign, 1=negative, 0=positive (or zero) +#define BIT_I 0x08 // interrupt mask, 1=disabled, 0=enabled +#define BIT_H 0x10 // half carry status(out of bit 3) +#define BIT_ALL (BIT_C |BIT_Z |BIT_N |BIT_I |BIT_H) // all bits + +#define BITPOS_C 0 // 1 +#define BITPOS_Z 1 // 2H +#define BITPOS_N 2 // 4H +#define BITPOS_I 3 // 8H +#define BITPOS_H 4 // 10H + +#endif + +/* End of st7.src/regsst7.h */ diff --git a/sim/ucsim/st7.src/simst7.cc b/sim/ucsim/st7.src/simst7.cc new file mode 100644 index 0000000..b50f4dd --- /dev/null +++ b/sim/ucsim/st7.src/simst7.cc @@ -0,0 +1,45 @@ +/* + * Simulator of microcontrollers (simst7.cc) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + + +// local +#include "simst7cl.h" +#include "st7cl.h" + + +cl_simst7::cl_simst7(class cl_app *the_app): + cl_sim(the_app) +{} + +class cl_uc * +cl_simst7::mk_controller(void) +{ + return(new cl_st7(this)); +} + + +/* End of st7.src/simst7.cc */ diff --git a/sim/ucsim/st7.src/simst7cl.h b/sim/ucsim/st7.src/simst7cl.h new file mode 100644 index 0000000..55befa1 --- /dev/null +++ b/sim/ucsim/st7.src/simst7cl.h @@ -0,0 +1,45 @@ +/* + * Simulator of microcontrollers (simstm8cl.h) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#ifndef SIMST7CL_HEADER +#define SIMST7CL_HEADER + +#include "simcl.h" + + +class cl_simst7: public cl_sim +{ +public: + cl_simst7(class cl_app *the_app); + + virtual class cl_uc *mk_controller(void); +}; + + +#endif + +/* End of st7.src/simst7cl.h */ diff --git a/sim/ucsim/st7.src/sst7.cc b/sim/ucsim/st7.src/sst7.cc new file mode 100644 index 0000000..2357625 --- /dev/null +++ b/sim/ucsim/st7.src/sst7.cc @@ -0,0 +1,56 @@ +/* + * Simulator of microcontrollers (sst7.cc) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +// prj +#include "globals.h" + +// sim.src +#include "appcl.h" + +// local +#include "simst7cl.h" + + +int +main(int argc, char *argv[]) +{ + class cl_sim *sim; + + application= new cl_app(); + application->init(argc, argv); + sim= new cl_simst7(application); + if (sim->init()) + sim->state|= SIM_QUIT; + application->set_simulator(sim); + application->run(); + application->done(); + delete application; + return(0); +} + + +/* End of st7.src/sst7.cc */ diff --git a/sim/ucsim/st7.src/st7.cc b/sim/ucsim/st7.src/st7.cc new file mode 100644 index 0000000..aca8f4f --- /dev/null +++ b/sim/ucsim/st7.src/st7.cc @@ -0,0 +1,1229 @@ +/* + * Simulator of microcontrollers (st7.cc) + * + * some st7 code base from Karl Bongers karl@turbobit.com + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#include "ddconfig.h" + +#include /* for va_list */ +#include +#include +#include +#include "i_string.h" + +// prj +#include "pobjcl.h" + +// sim +#include "simcl.h" + +// local +#include "st7cl.h" +#include "glob.h" +#include "regsst7.h" +#include "st7mac.h" + +#define uint32 t_addr +#define uint8 unsigned char + +/*******************************************************************/ + + +/* + * Base type of ST7 controllers + */ + +cl_st7::cl_st7(class cl_sim *asim): + cl_uc(asim) +{ + type= (struct cpu_entry *)malloc(sizeof(struct cpu_entry)); + type->type= CPU_ST7; +} + +int +cl_st7::init(void) +{ + cl_uc::init(); /* Memories now exist */ + + xtal = 8000000; + + //rom = address_space(MEM_ROM_ID); +// ram = mem(MEM_XRAM); + //ram = rom; + + // zero out ram(this is assumed in regression tests) + //printf("******************** leave the RAM dirty now \n"); +// for (int i=0x0; i<0x8000; i++) { +// ram->set((t_addr) i, 0); +// } + + return(0); +} + + +void +cl_st7::reset(void) +{ + cl_uc::reset(); + + regs.SP = 0x17f; + regs.A = 0; + regs.X = 0; + regs.Y = 0; + regs.CC = 0x00; + regs.VECTOR = 1; + +} + + +char * +cl_st7::id_string(void) +{ + return((char*)"unspecified ST7"); +} + + +/* + * Making elements of the controller + */ +/* +t_addr +cl_st7::get_mem_size(enum mem_class type) +{ + switch(type) + { + case MEM_ROM: return(0x10000); + case MEM_XRAM: return(0x10000); + default: return(0); + } + return(cl_uc::get_mem_size(type)); +} +*/ +void +cl_st7::mk_hw_elements(void) +{ + //class cl_base *o; + cl_uc::mk_hw_elements(); +} + +void +cl_st7::make_memories(void) +{ + class cl_address_space *as; + + rom= ram= as= new cl_address_space("rom", 0, 0x10000, 8); + as->init(); + address_spaces->add(as); + + class cl_address_decoder *ad; + class cl_memory_chip *chip; + + chip= new cl_memory_chip("rom_chip", 0x10000, 8); + chip->init(); + memchips->add(chip); + ad= new cl_address_decoder(as= address_space("rom"), chip, 0, 0xffff, 0); + ad->init(); + as->decoders->add(ad); + ad->activate(0); + + regs8= new cl_address_space("regs8", 0, 2, 8); + regs8->init(); + regs8->get_cell(0)->decode((t_mem*)®s.A); + regs8->get_cell(1)->decode((t_mem*)®s.CC); + + regs16= new cl_address_space("regs16", 0, 3, 16); + regs16->init(); + + regs16->get_cell(0)->decode((t_mem*)®s.X); + regs16->get_cell(1)->decode((t_mem*)®s.Y); + regs16->get_cell(2)->decode((t_mem*)®s.SP); + + address_spaces->add(regs8); + address_spaces->add(regs16); + + class cl_var *v; + vars->add(v= new cl_var(cchars("A"), regs8, 0, "")); + v->init(); + vars->add(v= new cl_var(cchars("CC"), regs8, 1, "")); + v->init(); + + vars->add(v= new cl_var(cchars("X"), regs16, 0, "")); + v->init(); + vars->add(v= new cl_var(cchars("Y"), regs16, 1, "")); + v->init(); + vars->add(v= new cl_var(cchars("SP"), regs16, 2, "")); + v->init(); +} + + +/* + * Help command interpreter + */ + +struct dis_entry * +cl_st7::dis_tbl(void) +{ + return(disass_st7); +} + +/*struct name_entry * +cl_st7::sfr_tbl(void) +{ + return(0); +}*/ + +/*struct name_entry * +cl_st7::bit_tbl(void) +{ + //FIXME + return(0); +}*/ + +int +cl_st7::inst_length(t_addr addr) +{ + int len = 0; + + get_disasm_info(addr, &len, NULL, NULL, NULL); + + return len; +} +int +cl_st7::inst_branch(t_addr addr) +{ + int b; + + get_disasm_info(addr, NULL, &b, NULL, NULL); + + return b; +} + +bool +cl_st7::is_call(t_addr addr) +{ + struct dis_entry *e; + + get_disasm_info(addr, NULL, NULL, NULL, &e); + + return e?(e->is_call):false; +} + +int +cl_st7::longest_inst(void) +{ + return 5; +} + + +const char * +cl_st7::get_disasm_info(t_addr addr, + int *ret_len, + int *ret_branch, + int *immed_offset, + struct dis_entry **dentry) +{ + const char *b = NULL; + uint code; + int len = 0; + int immed_n = 0; + int i; + int start_addr = addr; + struct dis_entry *dis_e; + + code= rom->get(addr++); + dis_e = NULL; + + switch(code) { + /* here will be all the prefixes for ST7 */ + case 0x90 : + code= rom->get(addr++); + i= 0; + while ((code & disass_st7_90[i].mask) != disass_st7_90[i].code && + disass_st7_90[i].mnemonic) + i++; + dis_e = &disass_st7_90[i]; + b= disass_st7_90[i].mnemonic; + if (b != NULL) + len += (disass_st7_90[i].length + 1); + break; + + case 0x91 : + code= rom->get(addr++); + i= 0; + while ((code & disass_st7_91[i].mask) != disass_st7_91[i].code && + disass_st7_91[i].mnemonic) + i++; + dis_e = &disass_st7_91[i]; + b= disass_st7_91[i].mnemonic; + if (b != NULL) + len += (disass_st7_91[i].length + 1); + break; + + case 0x92 : + code= rom->get(addr++); + i= 0; + while ((code & disass_st7_92[i].mask) != disass_st7_92[i].code && + disass_st7_92[i].mnemonic) + i++; + dis_e = &disass_st7_92[i]; + b= disass_st7_92[i].mnemonic; + if (b != NULL) + len += (disass_st7_92[i].length + 1); + break; + + + default: + i= 0; + while ((code & disass_st7[i].mask) != disass_st7[i].code && + disass_st7[i].mnemonic) + i++; + dis_e = &disass_st7[i]; + b= disass_st7[i].mnemonic; + if (b != NULL) + len += (disass_st7[i].length); + break; + } + + if (ret_branch) { + *ret_branch = dis_e->branch; + } + + if (immed_offset) { + if (immed_n > 0) + *immed_offset = immed_n; + else *immed_offset = (addr - start_addr); + } + + if (len == 0) + len = 1; + + if (ret_len) + *ret_len = len; + + if (dentry) + *dentry= dis_e; + + return b; +} + +char * +cl_st7::disass(t_addr addr, const char *sep) +{ + char work[256], temp[20]; + const char *b; + char *buf, *p, *t; + int len = 0; + int immed_offset = 0; + + + p= work; + + b = get_disasm_info(addr, &len, NULL, &immed_offset, NULL); + + if (b == NULL) { + buf= (char*)malloc(30); + strcpy(buf, "UNKNOWN/INVALID"); + return(buf); + } + + while (*b) + { + if (*b == '%') + { + b++; + switch (*(b++)) + { + //case 's': // s signed byte immediate + // sprintf(temp, "#%d", (char)rom->get(addr+immed_offset)); + // ++immed_offset; + // break; + //case 'e': // e extended 24bit immediate operand + // sprintf(temp, "#0x%06lx", + // (ulong)((rom->get(addr+immed_offset)<<16) | + // (rom->get(addr+immed_offset+1)<<8) | + // (rom->get(addr+immed_offset+2))) ); + // ++immed_offset; + // ++immed_offset; + // ++immed_offset; + // break; + //case 'w': // w word immediate operand + // sprintf(temp, "#0x%04x", + // (uint)((rom->get(addr+immed_offset)<<8) | + // (rom->get(addr+immed_offset+1))) ); + // ++immed_offset; + // ++immed_offset; + // break; + case 'b': // b byte immediate operand + sprintf(temp, "#0x%02x", (uint)rom->get(addr+immed_offset)); + ++immed_offset; + break; + case 'd': // d short direct addressing + sprintf(temp, "$0x%02x", (uint)rom->get(addr+immed_offset)); + ++immed_offset; + break; + case 'x': // x long direct + sprintf(temp, "$0x%04x", + (uint)((rom->get(addr+immed_offset)<<8) | + (rom->get(addr+immed_offset+1))) ); + ++immed_offset; + ++immed_offset; + break; + //case '3': // 3 24bit index offset + // sprintf(temp, "0x%06lx", + // (ulong)((rom->get(addr+immed_offset)<<16) | + // (rom->get(addr+immed_offset+1)<<8) | + // (rom->get(addr+immed_offset+2))) ); + // ++immed_offset; + // ++immed_offset; + // ++immed_offset; + // break; + case '2': // 2 word index offset + sprintf(temp, "0x%04x", + (uint)((rom->get(addr+immed_offset)<<8) | + (rom->get(addr+immed_offset+1))) ); + ++immed_offset; + ++immed_offset; + break; + case '1': // b byte index offset + sprintf(temp, "0x%02x", (uint)rom->get(addr+immed_offset)); + ++immed_offset; + break; + case 'p': // b byte index offset + { + int i= (int)(addr+immed_offset+1 + +(char)rom->get(addr+immed_offset)); + sprintf(temp, "0x%04x", i&0xffff); + ++immed_offset; + break; + } + default: + strcpy(temp, "?"); + break; + } + t= temp; + while (*t) + *(p++)= *(t++); + } + else + *(p++)= *(b++); + } + *p= '\0'; + + p= strchr(work, ' '); + if (!p) + { + buf= strdup(work); + return(buf); + } + if (sep == NULL) + buf= (char *)malloc(6+strlen(p)+1); + else + buf= (char *)malloc((p-work)+strlen(sep)+strlen(p)+1); + for (p= work, t= buf; *p != ' '; p++, t++) + *t= *p; + p++; + *t= '\0'; + if (sep == NULL) + { + while (strlen(buf) < 6) + strcat(buf, " "); + } + else + strcat(buf, sep); + strcat(buf, p); + return(buf); +} + + +void +cl_st7::print_regs(class cl_console_base *con) +{ + con->dd_printf("---HINZC Flags= 0x%02x %3d %c ", + regs.CC, regs.CC, isprint(regs.CC)?regs.CC:'.'); + con->dd_printf("A= 0x%02x %3d %c\n", + regs.A, regs.A, isprint(regs.A)?regs.A:'.'); + con->dd_printf("---%c%c%c%c%c ", + (regs.CC&BIT_H)?'1':'0', + (regs.CC&BIT_I)?'1':'0', + (regs.CC&BIT_N)?'1':'0', + (regs.CC&BIT_Z)?'1':'0', + (regs.CC&BIT_C)?'1':'0'); + con->dd_printf("X= 0x%02x %3d %c ", + regs.X, regs.X, isprint(regs.X)?regs.X:'.'); + con->dd_printf("Y= 0x%02x %3d %c\n", + regs.Y, regs.Y, isprint(regs.Y)?regs.Y:'.'); + con->dd_printf("SP= 0x%04x [SP+1]= %02x %3d %c\n", + regs.SP, ram->get(regs.SP+1), ram->get(regs.SP+1), + isprint(ram->get(regs.SP+1))?ram->get(regs.SP+1):'.'); + + print_disass(PC, con); +} + +/* + * Execution + */ + +int +cl_st7::exec_inst(void) +{ + t_mem code; + unsigned char cprefix; // prefix used for processing in functions + + if (regs.VECTOR) { + regs.VECTOR = 0; + PC = get2(0xFFFE); + return(resGO); + } + + instPC= PC; + + if (fetch(&code)) { + //printf("******************** break \n"); + return(resBREAKPOINT); + } + tick(1); + + switch (code) { // get prefix + case 0x90: + case 0x91: + case 0x92: + cprefix = code; + fetch(&code); + break; + default: + cprefix = 0x00; + break; + } + + //printf("******************** switch; pc=0x%lx, prefix = 0x%x, code = 0x%x\n",(long int)(PC), cprefix, code); + switch (code & 0xf) { + int mulres; + + case 0x0: + switch ( code & 0xf0) { + case 0x00: // btjf, btjt + return(inst_btjfbtjt(code, cprefix)); + break; + case 0x10: // bres,btst + return(inst_bresbset(code, cprefix)); + break; + case 0x20: //JR + return( inst_jr( code, cprefix)); + break; + case 0x30: + case 0x40: + case 0x50: + case 0x60: + case 0x70: // NEG + return( inst_neg( code, cprefix)); + break; + case 0x80: // iret + pop1( regs.CC); + pop1( regs.A); + pop1( regs.X); + pop2( PC); + return(resGO); + break; + case 0xA0: + case 0xB0: + case 0xC0: + case 0xD0: + case 0xE0: + case 0xF0: // SUB + return( inst_sub( code, cprefix)); + break; + case 0x90: // this is prefix, do not be mad ??? + default: + //printf("************* bad code !!!!\n"); + return(resINV_INST); + } + + case 0x1: + switch ( code & 0xf0) { + case 0x00: // btjf, btjt + return(inst_btjfbtjt(code, cprefix)); + break; + case 0x10: // bres,btst + return(inst_bresbset(code, cprefix)); + break; + case 0x20: //JR + return( inst_jr( code, cprefix)); + break; + case 0x80: // ret + pop2( PC); + return(resGO); + break; + case 0xA0: + case 0xB0: + case 0xC0: + case 0xD0: + case 0xE0: + case 0xF0: // CP + return( inst_cp( code, cprefix)); + break; + case 0x30: + case 0x40: + case 0x50: + case 0x60: + case 0x70: // + case 0x90: // this is prefix, do not be mad ??? + default: + //printf("************* bad code !!!!\n"); + return(resINV_INST); + } + + case 0x2: + switch ( code & 0xf0) { + case 0x00: // btjf, btjt + return(inst_btjfbtjt(code, cprefix)); + break; + case 0x10: // bres,btst + return(inst_bresbset(code, cprefix)); + break; + case 0x20: //JR + return( inst_jr( code, cprefix)); + break; + case 0x40: // mul + if(cprefix==0) { + mulres = regs.X * regs.A; + regs.A = mulres & 0xff; + regs.X = mulres >> 8; + }else if (cprefix == 0x90) { + mulres = regs.Y * regs.A; + regs.A = mulres & 0xff; + regs.Y = mulres >> 8; + } else { + return (resHALT); + } + return (resGO); + break; + case 0xA0: + case 0xB0: + case 0xC0: + case 0xD0: + case 0xE0: + case 0xF0: // SBC + return( inst_sbc( code, cprefix)); + break; + case 0x30: + case 0x50: + case 0x60: + case 0x70: // + case 0x80: // + case 0x90: // this is prefix, do not be mad ??? + default: + //printf("************* bad code !!!!\n"); + return(resINV_INST); + } + + case 0x3: + switch ( code & 0xf0) { + case 0x00: // btjf, btjt + return(inst_btjfbtjt(code, cprefix)); + break; + case 0x10: // bres,btst + return(inst_bresbset(code, cprefix)); + break; + case 0x20: //JR + return( inst_jr( code, cprefix)); + break; + case 0x30: + case 0x40: + case 0x50: + case 0x60: + case 0x70: // CPL + return( inst_cpl( code, cprefix)); + break; + case 0x80: // trap + //printf("************* TRAP instruction unimplemented !!!!\n"); + return(resINV_INST); + break; + case 0x90: // + if(cprefix==0) { + regs.X = regs.Y; + }else if (cprefix == 0x90) { + regs.Y = regs.X; + } else { + return (resHALT); + } + return (resGO); + break; + case 0xA0: + case 0xB0: + case 0xC0: + case 0xD0: + case 0xE0: + case 0xF0: // + return( inst_cpxy( code, cprefix)); + break; + default: + //printf("************* bad code !!!!\n"); + return(resINV_INST); + } + + case 0x4: + switch ( code & 0xf0) { + case 0x00: // btjf, btjt + return(inst_btjfbtjt(code, cprefix)); + break; + case 0x10: // bres,btst + return(inst_bresbset(code, cprefix)); + break; + case 0x20: //JR + return( inst_jr( code, cprefix)); + break; + case 0x30: + case 0x40: + case 0x50: + case 0x60: + case 0x70: // SRL + return( inst_srl( code, cprefix)); + break; + case 0x80: // pop A + pop1( regs.A); + return (resGO); + break; + case 0x90: // + if(cprefix==0) { + regs.SP = regs.X; + }else if (cprefix == 0x90) { + regs.SP = regs.Y; + } else { + return (resHALT); + } + return (resGO); + break; + case 0xA0: + case 0xB0: + case 0xC0: + case 0xD0: + case 0xE0: + case 0xF0: // AND + return( inst_and( code, cprefix)); + break; + default: + //printf("************* bad code !!!!\n"); + return(resINV_INST); + } + + case 0x5: + switch ( code & 0xf0) { + case 0x00: // btjf, btjt + return(inst_btjfbtjt(code, cprefix)); + break; + case 0x10: // bres,btst + return(inst_bresbset(code, cprefix)); + break; + case 0x20: //JR + return( inst_jr( code, cprefix)); + break; + case 0x80: // + if(cprefix==0) { + pop1(regs.X); + }else if (cprefix == 0x90) { + pop1(regs.Y); + } else { + return (resHALT); + } + return (resGO); + break; + case 0x90: // + if(cprefix==0) { + regs.SP = regs.A; + } else { + return (resHALT); + } + return (resGO); + break; + case 0xA0: + case 0xB0: + case 0xC0: + case 0xD0: + case 0xE0: + case 0xF0: // BCP + return( inst_bcp( code, cprefix)); + break; + case 0x30: + case 0x40: + case 0x50: + case 0x60: + case 0x70: // + default: + //printf("************* bad code !!!!\n"); + return(resINV_INST); + } + + case 0x6: + switch ( code & 0xf0) { + case 0x00: // btjf, btjt + return(inst_btjfbtjt(code, cprefix)); + break; + case 0x10: // bres,btst + return(inst_bresbset(code, cprefix)); + break; + case 0x20: //JR + return( inst_jr( code, cprefix)); + break; + case 0x30: + case 0x40: + case 0x50: + case 0x60: + case 0x70: // + return( inst_rrc( code, cprefix)); + break; + case 0x80: // + pop1( regs.CC); + return (resGO); + break; + case 0x90: // + if(cprefix==0) { + regs.X = regs.SP; + }else if (cprefix == 0x90) { + regs.Y = regs.SP; + } else { + return (resHALT); + } + return (resGO); + break; + case 0xA0: + case 0xB0: + case 0xC0: + case 0xD0: + case 0xE0: + case 0xF0: // LD A,... + return( inst_lda( code, cprefix)); + break; + default: + //printf("************* bad code !!!!\n"); + return(resINV_INST); + } + + case 0x7: + switch ( code & 0xf0) { + case 0x00: // btjf, btjt + return(inst_btjfbtjt(code, cprefix)); + break; + case 0x10: // bres,btst + return(inst_bresbset(code, cprefix)); + break; + case 0x20: //JR + return( inst_jr( code, cprefix)); + break; + case 0x30: + case 0x40: + case 0x50: + case 0x60: + case 0x70: // SRA + return( inst_sra( code, cprefix)); + break; + case 0x90: // + if(cprefix==0) { + regs.X = regs.A; + }else if (cprefix == 0x90) { + regs.Y = regs.A; + } else { + return (resHALT); + } + return (resGO); + break; + case 0xA0: + break; + case 0xB0: + case 0xC0: + case 0xD0: + case 0xE0: + case 0xF0: // + return( inst_lddst( code, cprefix)); + break; + case 0x80: // + default: + //printf("************* bad code !!!!\n"); + return(resINV_INST); + } + + case 0x8: + switch ( code & 0xf0) { + case 0x00: // btjf, btjt + return(inst_btjfbtjt(code, cprefix)); + break; + case 0x10: // bres,btst + return(inst_bresbset(code, cprefix)); + break; + case 0x20: //JR + return( inst_jr( code, cprefix)); + break; + case 0x30: + case 0x40: + case 0x50: + case 0x60: + case 0x70: // SLA, SLL + return( inst_sll( code, cprefix)); + break; + case 0x80: // push A + push1(regs.A); + return (resGO); + break; + case 0x90: // rcf + FLAG_CLEAR (BIT_C); + return (resGO); + break; + case 0xA0: + case 0xB0: + case 0xC0: + case 0xD0: + case 0xE0: + case 0xF0: // XOR + return( inst_xor( code, cprefix)); + break; + default: + //printf("************* bad code !!!!\n"); + return(resINV_INST); + } + + case 0x9: + switch ( code & 0xf0) { + case 0x00: // btjf, btjt + return(inst_btjfbtjt(code, cprefix)); + break; + case 0x10: // bres,btst + return(inst_bresbset(code, cprefix)); + break; + case 0x20: //JR + return( inst_jr( code, cprefix)); + break; + case 0x30: + case 0x40: + case 0x50: + case 0x60: + case 0x70: // RLC + return( inst_rlc( code, cprefix)); + break; + case 0x80: // push X; push Y + if(cprefix==0) { + push1(regs.X); + }else if (cprefix == 0x90) { + push1(regs.Y); + } else { + return (resHALT); + } + return (resGO); + break; + case 0x90: // scf + FLAG_SET (BIT_C); + return (resGO); + break; + case 0xA0: + case 0xB0: + case 0xC0: + case 0xD0: + case 0xE0: + case 0xF0: // ADC + return( inst_adc( code, cprefix)); + break; + default: + //printf("************* bad code !!!!\n"); + return(resINV_INST); + } + + case 0xa: + switch ( code & 0xf0) { + case 0x00: // btjf, btjt + return(inst_btjfbtjt(code, cprefix)); + break; + case 0x10: // bres,btst + return(inst_bresbset(code, cprefix)); + break; + case 0x20: //JR + return( inst_jr( code, cprefix)); + break; + case 0x30: + case 0x40: + case 0x50: + case 0x60: + case 0x70: // DEC + return( inst_dec( code, cprefix)); + break; + case 0x80: // + push1(regs.CC); + return (resGO); + break; + case 0x90: // RIM + FLAG_CLEAR (BIT_I); + return (resGO); + break; + case 0xA0: + case 0xB0: + case 0xC0: + case 0xD0: + case 0xE0: + case 0xF0: // + return( inst_or( code, cprefix)); + break; + default: + //printf("************* bad code !!!!\n"); + return(resINV_INST); + } + + case 0xb: + switch ( code & 0xf0) { + case 0x00: // btjf, btjt + return(inst_btjfbtjt(code, cprefix)); + break; + case 0x10: // bres,btst + return(inst_bresbset(code, cprefix)); + break; + case 0x20: //JR + return( inst_jr( code, cprefix)); + break; + case 0x90: // SIM + FLAG_SET (BIT_I); + return (resGO); + break; + case 0xA0: + case 0xB0: + case 0xC0: + case 0xD0: + case 0xE0: + case 0xF0: // ADD + return( inst_add( code, cprefix)); + break; + case 0x30: + case 0x40: + case 0x50: + case 0x60: + case 0x70: // + case 0x80: // + default: + //printf("************* bad code !!!!\n"); + return(resINV_INST); + } + + case 0xc: + switch ( code & 0xf0) { + case 0x00: // btjf, btjt + return(inst_btjfbtjt(code, cprefix)); + break; + case 0x10: // bres,btst + return(inst_bresbset(code, cprefix)); + break; + case 0x20: //JR + return( inst_jr( code, cprefix)); + break; + case 0x30: + case 0x40: + case 0x50: + case 0x60: + case 0x70: // INC + return( inst_inc( code, cprefix)); + break; + case 0x90: // RSP + regs.SP = 0x17f; + return (resGO); + break; + case 0xA0: + break; + case 0xB0: + case 0xC0: + case 0xD0: + case 0xE0: + case 0xF0: // JP + PC = OPERAND(code, cprefix); + return( resGO); + break; + case 0x80: // + default: + //printf("************* bad code !!!!\n"); + return(resINV_INST); + } + + case 0xd: + switch ( code & 0xf0) { + case 0x00: // btjf, btjt + return(inst_btjfbtjt(code, cprefix)); + break; + case 0x10: // bres,btst + return(inst_bresbset(code, cprefix)); + break; + case 0x20: //JR + return( inst_jr( code, cprefix)); + break; + case 0x30: + case 0x40: + case 0x50: + case 0x60: + case 0x70: // TNZ + return( inst_tnz( code, cprefix)); + break; + case 0x90: // nop + return(resGO); + break; + case 0xA0: // callr + return( inst_callr( code, cprefix)); + break; + case 0xB0: + case 0xC0: + case 0xD0: + case 0xE0: + case 0xF0: // call + return( inst_call( code, cprefix)); + break; + case 0x80: // + default: + //printf("************* bad code !!!!\n"); + return(resINV_INST); + } + + case 0xe: + switch ( code & 0xf0) { + case 0x00: // btjf, btjt + return(inst_btjfbtjt(code, cprefix)); + break; + case 0x10: // bres,btst + return(inst_bresbset(code, cprefix)); + break; + case 0x20: //JR + return( inst_jr( code, cprefix)); + break; + case 0x30: + case 0x40: + case 0x50: + case 0x60: + case 0x70: // SWAP + return( inst_swap( code, cprefix)); + break; + case 0x80: // HALT + FLAG_CLEAR (BIT_I); + PC--; + return(resHALT); + break; + case 0x90: // LD A,SP + if(cprefix==0) { + regs.A = regs.SP; + } else { + return (resHALT); + } + return (resGO); + break; + case 0xA0: + case 0xB0: + case 0xC0: + case 0xD0: + case 0xE0: + case 0xF0: // LDXY + return( inst_ldxy( code, cprefix)); + break; + default: + //printf("************* bad code !!!!\n"); + return(resINV_INST); + } + + case 0xf: + switch ( code & 0xf0) { + case 0x00: // btjf, btjt + return(inst_btjfbtjt(code, cprefix)); + break; + case 0x10: // bres,btst + return(inst_bresbset(code, cprefix)); + break; + case 0x20: //JR + return( inst_jr( code, cprefix)); + break; + case 0x30: + case 0x40: + case 0x50: + case 0x60: + case 0x70: // + return( inst_clr( code, cprefix)); + break; + case 0x80: // WFI + FLAG_CLEAR (BIT_I); + PC--; + return(resHALT); + break; + case 0x90: // ld A,X LD A,Y + if(cprefix==0) { + regs.A = regs.X; + }else if (cprefix == 0x90) { + regs.A = regs.Y; + } else { + return (resHALT); + } + return (resGO); + break; + case 0xB0: + case 0xC0: + case 0xD0: + case 0xE0: + case 0xF0: // + return( inst_ldxydst( code, cprefix)); + break; + case 0xA0: + default: + //printf("************* bad code !!!!\n"); + return(resINV_INST); + } + + + default: + //printf("************* bad code !!!!\n"); + return(resINV_INST); + } + + /*if (PC) + PC--; + else + PC= get_mem_size(MEM_ROM_ID)-1;*/ + PC= rom->inc_address(PC, -1); + + sim->stop(resINV_INST); + return(resINV_INST); +} + +t_mem +cl_st7::get_1(t_addr addr) +{ + vc.rd++; + return ram->read(addr); +} + +t_mem +cl_st7::get_2(t_addr addr) +{ + vc.rd+= 2; + return (ram->read(addr) << 8) | ram->read(addr+1); +} + +t_mem +cl_st7::get_3(t_addr addr) +{ + vc.rd+= 3; + return (ram->read(addr) << 16) | + (ram->read(addr+1) << 8) | + (ram->read(addr+2)); +} + +/* End of st7.src/st7.cc */ diff --git a/sim/ucsim/st7.src/st7cl.h b/sim/ucsim/st7.src/st7cl.h new file mode 100644 index 0000000..bd03389 --- /dev/null +++ b/sim/ucsim/st7.src/st7cl.h @@ -0,0 +1,82 @@ +/* + * Simulator of microcontrollers (st7cl.h) + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +/* This file is part of microcontroller simulator: ucsim. + +UCSIM is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +UCSIM is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with UCSIM; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ +/*@1@*/ + +#ifndef ST7CL_HEADER +#define ST7CL_HEADER + +#include "uccl.h" + +#include "regsst7.h" + + +/* + * Base type of Z80 microcontrollers + */ + +class cl_st7: public cl_uc +{ +public: + class cl_memory *ram; + class cl_memory *rom; + class cl_address_space *regs8, *regs16; + struct t_regs regs; +public: + cl_st7(class cl_sim *asim); + virtual int init(void); + virtual char *id_string(void); + + //virtual t_addr get_mem_size(enum mem_class type); + virtual void mk_hw_elements(void); + virtual void make_memories(void); + + virtual struct dis_entry *dis_tbl(void); + virtual int inst_length(t_addr addr); + virtual int inst_branch(t_addr addr); + virtual int longest_inst(void); + virtual char *disass(t_addr addr, const char *sep); + virtual void print_regs(class cl_console_base *con); + + virtual int exec_inst(void); + + virtual const char *get_disasm_info(t_addr addr, + int *ret_len, + int *ret_branch, + int *immed_offset, + struct dis_entry **dentry); + virtual bool is_call(t_addr addr); + virtual t_mem get_1(t_addr addr); + virtual t_mem get_2(t_addr addr); + virtual t_mem get_3(t_addr addr); + + virtual void reset(void); +#include "instcl.h" +}; + + +#endif + +/* End of st7.src/st7cl.h */ diff --git a/sim/ucsim/st7.src/st7mac.h b/sim/ucsim/st7.src/st7mac.h new file mode 100644 index 0000000..1431a16 --- /dev/null +++ b/sim/ucsim/st7.src/st7mac.h @@ -0,0 +1,42 @@ +/* + * Simulator of microcontrollers (st7mac.h) + * + * some z80 code base from Karl Bongers karl@turbobit.com + * + * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. + * + * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu + * + */ + +// shift positions +#define BITPOS_C 0 // 1 +#define BITPOS_Z 1 // 2H +#define BITPOS_N 2 // 4H +#define BITPOS_I 3 // 8H +#define BITPOS_H 4 // 10H + +#define store2(addr, val) { ram->write((t_addr) (addr), (val >> 8) & 0xff); ram->write((t_addr) (addr+1), val & 0xff); vc.wr+= 2; } +#define store1(addr, val) { ram->write((t_addr) (addr), val); vc.wr++; } +#define get1(addr) get_1(addr) +//ram->get((t_addr) (addr)) +#define get2(addr) get_2(addr) +//((ram->get((t_addr) (addr)) << 8) | ram->get((t_addr) (addr+1)) ) +#define get3(addr) get_3(addr) +//((ram->get((t_addr) (addr)) << 16) | (ram->get((t_addr) (addr+1)) << 8) |ram->get((t_addr) (addr+2)) ) +#define fetch2() ((fetch() << 8) | fetch() ) +#define fetch1() fetch() +#define push2(val) {store2(regs.SP-1,(val)); regs.SP-=2; } +#define push1(val) {store1(regs.SP,(val)); regs.SP-=1; } +#define pop2(var) {var=get2(regs.SP+1); regs.SP+=2;} +#define pop1(var) {var=get1(regs.SP+1); regs.SP+=1;} + + +#define FLAG_SET(f) {regs.CC |= f;} +#define FLAG_CLEAR(f) {regs.CC &= ~(f);} +#define FLAG_ASSIGN(f,c) {regs.CC = (c) ? regs.CC | (f) : regs.CC & ~(f);} +#define EA_IMM(c) ((((c) >> 4) & 0xf)==0xa) +#define OPERAND(code,prefix) (EA_IMM(code) ? fetch() : get1(fetchea(code,prefix))) + + + -- cgit v1.2.3