From 268a53de823a6750d6256ee1fb1e7707b4b45740 Mon Sep 17 00:00:00 2001 From: Xavier ASUS Date: Fri, 18 Oct 2019 00:31:54 +0200 Subject: sdcc-3.9.0 fork implementing GNU assembler syntax This fork aims to provide better support for stm8-binutils --- sim/ucsim/doc/memory.html | 57 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 57 insertions(+) create mode 100644 sim/ucsim/doc/memory.html (limited to 'sim/ucsim/doc/memory.html') diff --git a/sim/ucsim/doc/memory.html b/sim/ucsim/doc/memory.html new file mode 100644 index 0000000..7974125 --- /dev/null +++ b/sim/ucsim/doc/memory.html @@ -0,0 +1,57 @@ + + + + Memory simulation in μCsim + + +

Memory simulation in μCsim

+ Typical microprocessor system can look like this: +

[CPU-memory connection]

Address space

+ In our terminology "address space" means a set of: +

address bus lines
data bus lines
control (read/write) lines

+ Bus lines can be shared by address spaces, in this case number of control + line sets specifies the address spaces. +

Microcontrollers usually have more address spaces. Some is used inside + only, some can be used for external memories.

Address space does not store any value. It just specifies range of + addresses by start address (which is not necessarily zero) and size + which the CPU can provide when it tries to access a memory location.

Memory chip

+ "Memory chip" is a circuit which can hold values in cells. Cells are + indexed from 0 up to size-1. Each cell stores some (usually 8) bits. +

[Memory chip]

Address decoder

+ Addresses coming from an address space via address bus must be routed to + memory and translated to cell indexes. This is done by the "address + decoder". It listens addresses on the bus and control lines and + enables exactly one memory chip. This way cells of the memory chip appear in + the address space. +

[Decoded addresses]

It is possible that some addresses are not decoded. Writing to such an + address results data to be lost. Reading of a non-decoded address results + random value. Pullup or pulldown resistors can be applied to data bus + lines to provide a specific value for read operations.

As it shown above, it is also possible that some cells of a chip is not + mapped to any address.

Mixed address spaces (shared chips)

+ Decoder connects an address of an address space to a cell of a memory chip. + Only one cell can be connected to each addresses but same cell can be + connected to more than one address spaces. This is done by routing different + control lines to the same chip through logic L: +

Because each cell of a memory chip uses same read/write control, in real + world it is not possible to share individual cells of a chip between + address spaces. In μCsim simulator we can define as many address decoders + as we want so it is possible to map any cell to any address.

Memory banking

Banking...

Bit banding

Banding...

+ + -- cgit v1.2.3