Implemented --ffunction-sections
Interrupt vector must be placed on section .vectors, according to the default linker script file. Intermediate labels must be $-terminated so they are not listed by nm.
This commit is contained in:
Xavier ASUS
parent
de28405288
commit
9d8d485a0a
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@ -329,6 +329,7 @@ struct options
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bool noOptsdccInAsm; /* Do not emit .optsdcc in asm */
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bool oldralloc; /* Use old register allocator */
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int gasOutput; /* Output assembly in GNU as format */
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int function_sections; /* Place each function into a separate section. Useful for link-time dead code elimination. */
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};
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/* forward definition for variables accessed globally */
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@ -174,6 +174,7 @@ static const OPTION optionsTable[] = {
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{'W', NULL, NULL, "Pass through options to the pre-processor (p), assembler (a) or linker (l)"},
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{'S', NULL, &noAssemble, "Compile only; do not assemble or link"},
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{0 , "--gas", &options.gasOutput, "Compile in GAS (GNU Assembler) format."},
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{0 , "--function-sections", &options.function_sections, "Place each function into a separate section. Useful for link-time dead code elimination."},
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{'c', "--compile-only", &options.cc_only, "Compile and assemble, but do not link"},
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{'E', "--preprocessonly", &preProcOnly, "Preprocess only, do not compile"},
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{0, "--c1mode", &options.c1mode, "Act in c1 mode. The standard input is preprocessed code, the output is assembly code."},
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@ -60,7 +60,7 @@ extern FILE *junkFile;
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#define BIT_NAME port->mem.bit_name
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#define REG_NAME port->mem.reg_name
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#define STATIC_NAME port->mem.static_name
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#define HOME_NAME (options.gasOutput ? ".text.interrupt_vector" : port->mem.home_name)
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#define HOME_NAME (options.gasOutput ? ".vectors" : port->mem.home_name)
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#define OVERLAY_NAME port->mem.overlay_name
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#define CONST_NAME (options.gasOutput ? ".rodata" : port->mem.const_name)
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#define CABS_NAME port->mem.cabs_name
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@ -1094,7 +1094,7 @@ aopOp (operand *op, const iCode *ic)
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}
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/* None of the above, which only leaves temporaries. */
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{
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{
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bool completely_in_regs = TRUE;
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bool completely_on_stack = TRUE;
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asmop *aop = newAsmop (AOP_REGSTK);
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@ -1397,7 +1397,7 @@ adjustStack (int n, bool a_free, bool x_free, bool y_free)
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else
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{
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emit2 (n > 0 ? "addw" : "sub", "sp, #%d", abs (n));
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cost (2, 1);
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cost (2, 1);
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G.stack.pushed -= n;
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updateCFA ();
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n -= n;
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@ -1513,7 +1513,7 @@ genCopyStack (asmop *result, int roffset, asmop *source, int soffset, int n, boo
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i++;
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continue;
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}
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cost (4, 4);
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cost (4, 4);
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assigned[i] = TRUE;
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assigned[i + 1] = TRUE;
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(*size) -= 2;
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@ -2035,7 +2035,7 @@ skip_byte:
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wassertl_bt (0, "Unimplemented.");
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cost (180, 180);
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return;
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}
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}
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// Copy (stack-to-stack) what we can with whatever free regs we have now.
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a_free = a_dead;
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@ -2138,7 +2138,7 @@ skip_byte:
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i++;
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}
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else
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{
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{
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cheapMove (result, roffset + i, ASMOP_ZERO, 0, !a_free);
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assigned[i] = TRUE;
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if (aopInReg (result, roffset + i, A_IDX))
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@ -2452,9 +2452,9 @@ genNot (const iCode *ic)
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{
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emit3 (A_CLR, ASMOP_A, 0);
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emit3 (A_RLC, ASMOP_A, 0);
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cheapMove (result->aop, 0, ASMOP_A, 0, false);
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for (i = 1; i < result->aop->size; i++)
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cheapMove (result->aop, 0, ASMOP_ZERO, 0, true);
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}
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@ -2730,10 +2730,10 @@ genSub (const iCode *ic, asmop *result_aop, asmop *left_aop, asmop *right_aop)
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if (aopInReg (result_aop, i, A_IDX))
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result_in_a = TRUE;
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i++;
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}
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else if (!started && i + 1 < size && (y_free || aopInReg(left_aop, i, Y_IDX) && regDead (Y_IDX, ic)) &&
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else if (!started && i + 1 < size && (y_free || aopInReg(left_aop, i, Y_IDX) && regDead (Y_IDX, ic)) &&
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(aopOnStack (result_aop, i, 2) || result_aop->type == AOP_DIR) &&
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(aopOnStack (left_aop, i, 2) || aopInReg(left_aop, i, Y_IDX) || left_aop->type == AOP_DIR) &&
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(aopOnStackNotExt (right_aop, i, 2) || right_aop->type == AOP_LIT || right_aop->type == AOP_IMMD || right_aop->type == AOP_DIR && i + 1 < right_aop->size))
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@ -2753,7 +2753,7 @@ genSub (const iCode *ic, asmop *result_aop, asmop *left_aop, asmop *right_aop)
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started = TRUE;
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i += 2;
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}
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else if (!started && right_aop->type == AOP_LIT &&
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else if (!started && right_aop->type == AOP_LIT &&
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(aopInReg (left_aop, i, XH_IDX) && aopInReg (result_aop, i, XH_IDX) || aopInReg (left_aop, i, YH_IDX) && aopInReg (result_aop, i, YH_IDX)))
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{
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emit2 ("subw", "%s, #%d", aopInReg (left_aop, i, YH_IDX) ? "y" : "x", byteOfVal (right_aop->aopu.aop_lit, i) << 8);
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@ -2767,7 +2767,7 @@ genSub (const iCode *ic, asmop *result_aop, asmop *left_aop, asmop *right_aop)
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emit2 ("subw", "%s, #%d", aopInReg (left_aop, i, YL_IDX) ? "y" : "x", byteOfVal (right_aop->aopu.aop_lit, i));
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cost (3 + aopInReg (left_aop, i, YL_IDX), 2);
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started = TRUE;
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i++;
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i++;
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}
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else if (!started && i == size - 1 && aopOnStackNotExt (right_aop, i, 1) &&
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(aopInReg (left_aop, i, XL_IDX) && aopInReg (result_aop, i, XL_IDX) && xh_free || aopInReg (left_aop, i, YL_IDX) && aopInReg (result_aop, i, YL_IDX) && yh_free))
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@ -2847,7 +2847,7 @@ genSub (const iCode *ic, asmop *result_aop, asmop *left_aop, asmop *right_aop)
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if (aopInReg (result_aop, i, A_IDX))
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result_in_a = TRUE;
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i++;
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}
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}
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@ -3154,7 +3154,7 @@ genCall (const iCode *ic)
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else
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{
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genMove (ASMOP_X, left->aop, TRUE, TRUE, TRUE);
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emit2 ("call", "(x)");
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cost (1, 4);
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}
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@ -3265,7 +3265,7 @@ genCall (const iCode *ic)
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aopOp (IC_RESULT (ic), ic);
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size = !half ? IC_RESULT (ic)->aop->size : (IC_RESULT (ic)->aop->size > 2 ? 2 : IC_RESULT (ic)->aop->size);
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size = !half ? IC_RESULT (ic)->aop->size : (IC_RESULT (ic)->aop->size > 2 ? 2 : IC_RESULT (ic)->aop->size);
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wassert (getSize (ftype->next) >= 1 && getSize (ftype->next) <= 4);
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@ -3358,6 +3358,14 @@ genFunction (iCode *ic)
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emit2 (";", " function %s", sym->name);
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emit2 (";", "-----------------------------------------");
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if (options.function_sections && options.gasOutput)
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{
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char name[256];
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snprintf(name, sizeof name, "%s.%s", CODE_NAME, sym->name);
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emit2(".section", " %s", name);
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}
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D (emit2 (";", stm8_assignment_optimal ? "Register assignment is optimal." : "Register assignment might be sub-optimal."));
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D (emit2 (";", "Stack space usage: %d bytes.", sym->stack));
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@ -3451,7 +3459,7 @@ genEndFunction (iCode *ic)
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/* if debug then send end of function */
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if (options.debug && currFunc && !regalloc_dry_run)
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debugFile->writeEndFunction (currFunc, ic, 1);
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emit2 ("iret", "");
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cost (1, 11);
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}
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@ -3756,7 +3764,7 @@ genPlus (const iCode *ic)
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leftop = left->aop;
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rightop = right->aop;
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}
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for (i = 0, started = FALSE; i < size;) // Todo: 16-bit operation in dead source might be cheaper than add.
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{
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bool a_free = regDead (A_IDX, ic) && leftop->regs[A_IDX] <= i && rightop->regs[A_IDX] <= i && !result_in_a || pushed_a;
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@ -3815,7 +3823,7 @@ genPlus (const iCode *ic)
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aopOnStack (leftop, i, size - i - 2) && aopOnStack (leftop, i, size - i - 2) && aopInReg (result->aop, size - 2, Y_IDX) && aopInReg (result->aop, size - 2, Y_IDX)) &&
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result->aop->aopu.bytes[i].byteu.stk == leftop->aopu.bytes[i].byteu.stk ||
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aopOnStack (leftop, i + 2, size - i - 2) && aopOnStack (leftop, i + 2, size - i - 2) && aopInReg (result->aop, i, Y_IDX) && aopInReg (result->aop, i, Y_IDX) && result->aop->aopu.bytes[i + 2].byteu.stk == leftop->aopu.bytes[i + 2].byteu.stk ||
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size - i == 4 &&
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size - i == 4 &&
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(aopInReg (leftop, i, Y_IDX) && aopInReg (result->aop, i, Y_IDX) && aopInReg (leftop, i + 2, X_IDX) && aopInReg (result->aop, i + 2, X_IDX) || aopInReg (leftop, i, X_IDX) && aopInReg (result->aop, i, X_IDX) && aopInReg (leftop, i + 2, Y_IDX) && aopInReg (result->aop, i + 2, Y_IDX))))
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{
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if(!endlbl && !regalloc_dry_run)
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@ -3891,7 +3899,7 @@ genPlus (const iCode *ic)
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started = TRUE;
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i += 2;
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}
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else if (!started && i + 1 < size && (y_free || aopInReg(leftop, i, Y_IDX) && regDead (Y_IDX, ic)) &&
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else if (!started && i + 1 < size && (y_free || aopInReg(leftop, i, Y_IDX) && regDead (Y_IDX, ic)) &&
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(aopOnStack (result->aop, i, 2) || result->aop->type == AOP_DIR) &&
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(aopOnStack (leftop, i, 2) || aopInReg(leftop, i, Y_IDX) || leftop->type == AOP_DIR) &&
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(aopOnStackNotExt (rightop, i, 2) || rightop->type == AOP_LIT || rightop->type == AOP_IMMD || rightop->type == AOP_DIR && i + 1 < rightop->size))
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@ -4827,7 +4835,7 @@ genCmp (const iCode *ic, iCode *ifx)
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cheapMove (ASMOP_A, 0, left->aop, i, FALSE);
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right_stacked = stack_aop (right->aop, i, &right_offset);
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if (right_stacked || aopInReg (right->aop, i, A_IDX))
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{
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emit2 (started ? "sbc" : "cp", "a, (%d, sp)", right_stacked ? right_offset : 1);
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@ -4867,7 +4875,7 @@ _genCmp_1:
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case 20: /* special cases by genCmpTop () */
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emit2 ("jrne", "%05d$", labelKey2num (tlbl1->key));
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break;
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default: /* normal cases */
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default: /* normal cases */
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emit2 (branchInstCmp (opcode, sign, FALSE), "%05d$", labelKey2num (tlbl1->key));
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break;
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}
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@ -5666,7 +5674,7 @@ genAnd (const iCode *ic, iCode *ifx)
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}
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for (i = 0; i < size;)
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{
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{
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// Cases that don't need a free a.
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if (omitbyte == i)
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{
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@ -5747,7 +5755,7 @@ genAnd (const iCode *ic, iCode *ifx)
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result_in_a |= new_in_a;
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i = j;
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}
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else if (aopIsLitVal (right->aop, i, 1, 0xff))
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else if (aopIsLitVal (right->aop, i, 1, 0xff))
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{
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bool new_in_a = FALSE;
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for(j = i; j < size && j != omitbyte && aopIsLitVal (right->aop, j, 1, 0xff); j++)
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@ -5951,7 +5959,7 @@ genLeftShiftLiteral (operand *left, operand *right, operand *result, const iCode
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{
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std_bytes = shCount * 2;
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std_cycles = shCount;
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}
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}
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else if (aopInReg (shiftop, 0, YH_IDX))
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{
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std_bytes = shCount * 5;
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@ -6052,7 +6060,7 @@ std:
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i++;
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}
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}
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genMove (result->aop, shiftop, regDead (A_IDX, ic), regDead (X_IDX, ic), regDead (Y_IDX, ic));
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@ -6222,7 +6230,7 @@ postshift:
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if (pushed_a)
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pop (ASMOP_A, 0, 1);
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genMove (result->aop, shiftop, false, regDead (X_IDX, ic), regDead (Y_IDX, ic));
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}
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}
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freeAsmop (left);
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freeAsmop (result);
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@ -6403,7 +6411,7 @@ genRightShiftLiteral (operand *left, operand *right, operand *result, const iCod
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// Use swap a where beneficial.
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if (!sign && size == 1 && aopRS (shiftop) && !aopOnStack (shiftop, 0, 1) &&
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!(aopInReg (shiftop, 0, XL_IDX) && xh_zero) &&
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!(aopInReg (shiftop, 0, YL_IDX) && yh_zero && shCount <= 3))
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!(aopInReg (shiftop, 0, YL_IDX) && yh_zero && shCount <= 3))
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{
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swap_to_a (shiftop->aopu.bytes[0].byteu.reg->rIdx);
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if (shCount >= 4)
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@ -6494,7 +6502,7 @@ genRightShiftLiteral (operand *left, operand *right, operand *result, const iCod
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}
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if (pushed_sign)
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pop (ASMOP_A, 0, 1);
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if (!regDead (A_IDX, ic))
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pop (ASMOP_A, 0, 1);
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}
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@ -6774,7 +6782,7 @@ genPointerGet (const iCode *ic)
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int blen, bstr;
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bool bit_field = IS_BITVAR (getSpec (operandType (result)));
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symbol *const tlbl = ((regalloc_dry_run || !bit_field) ? 0 : newiTempLabel (NULL));
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blen = bit_field ? SPEC_BLEN (getSpec (operandType (result))) : 0;
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bstr = bit_field ? SPEC_BSTR (getSpec (operandType (result))) : 0;
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@ -6845,7 +6853,7 @@ genPointerGet (const iCode *ic)
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if (use_y ? !(regDead (Y_IDX, ic) || aopInReg (left->aop, 0, Y_IDX)) : !(regDead (X_IDX, ic) || aopInReg (left->aop, 0, X_IDX))) // Preferred index register is not free.
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{
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// Try to free an index register.
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if (result->aop->regs[XL_IDX] < 0 && result->aop->regs[XH_IDX] < 0)
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if (result->aop->regs[XL_IDX] < 0 && result->aop->regs[XH_IDX] < 0)
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{
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push (ASMOP_X, 0, 2);
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pushed_x = true;
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@ -6947,7 +6955,7 @@ genPointerGet (const iCode *ic)
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}
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if (bit_field && blen <= 8 && !SPEC_USIGN (getSpec (operandType (result)))) // Sign extension for partial byte of signed bit-field
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{
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{
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emit2 ("bcp", "a, #0x%02x", 0x80 >> (8 - blen));
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cost (2, 1);
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if (tlbl)
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@ -7056,7 +7064,7 @@ genPointerSet (iCode *ic)
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int blen, bstr;
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bool bit_field = IS_BITVAR (getSpec (operandType (right))) || IS_BITVAR (getSpec (operandType (left)));
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int cache_l = -1, cache_h = -1/*, cache_a = -1*/;
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blen = bit_field ? (SPEC_BLEN (getSpec (operandType (IS_BITVAR (getSpec (operandType (right))) ? right : left)))) : 0;
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bstr = bit_field ? (SPEC_BSTR (getSpec (operandType (IS_BITVAR (getSpec (operandType (right))) ? right : left)))) : 0;
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@ -7098,7 +7106,7 @@ genPointerSet (iCode *ic)
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normal_cycles += 2;
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i++;
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}
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}
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}
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if (!regDead (X_IDX, ic))
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{
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@ -7697,7 +7705,7 @@ genCast (const iCode *ic)
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{
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if (!regDead (A_IDX, ic))
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push (ASMOP_A, 0, 1);
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emit3w (A_NEGW, right->aop, 0);
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cost (aopInReg (right->aop, 0, X_IDX) ? 1 : 2, 2);
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emit3 (A_CLR, ASMOP_A, 0);
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@ -7738,7 +7746,7 @@ genCast (const iCode *ic)
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{
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right_stacked = ASMOP_A;
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right_offset = 0;
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}
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}
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if (!offset && aopInReg (right->aop, offset, A_IDX))
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{
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@ -7797,7 +7805,7 @@ genCast (const iCode *ic)
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cost (2, 2); // 2 for cycle cost is just an estimate; it also ignores pipelining.
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emit3w_o (A_DECW, result->aop, offset, 0, 0);
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emitLabel (tlbl);
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goto release;
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}
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@ -7809,7 +7817,7 @@ genCast (const iCode *ic)
|
|||
|
||||
cheapMove (ASMOP_A, 0, result->aop, right->aop->size - 1, FALSE);
|
||||
emit3 (A_RLC, ASMOP_A, 0);
|
||||
|
||||
|
||||
|
||||
if (size == 2 && (aopInReg (result->aop, offset, X_IDX) || aopInReg (result->aop, offset, Y_IDX))) // Faster when just setting 16-bit reg.
|
||||
{
|
||||
|
|
@ -8152,7 +8160,7 @@ genSTM8Code (iCode *lic)
|
|||
{
|
||||
iCode *ic;
|
||||
int clevel = 0;
|
||||
int cblock = 0;
|
||||
int cblock = 0;
|
||||
int cln = 0;
|
||||
regalloc_dry_run = FALSE;
|
||||
|
||||
|
|
@ -8166,9 +8174,9 @@ genSTM8Code (iCode *lic)
|
|||
for (ic = lic; ic; ic = ic->next)
|
||||
{
|
||||
initGenLineElement ();
|
||||
|
||||
|
||||
genLine.lineElement.ic = ic;
|
||||
|
||||
|
||||
if (ic->level != clevel || ic->block != cblock)
|
||||
{
|
||||
if (options.debug)
|
||||
|
|
|
|||
|
|
@ -281,22 +281,22 @@ stm8_genInitStartup (FILE *of)
|
|||
"_start:\n"
|
||||
"\t; Zeroing .bss\n"
|
||||
"\tldw x, __bss_start\n"
|
||||
"\t$0:\n"
|
||||
"0$:\n"
|
||||
"\tclr (x)\n"
|
||||
"\tincw x\n"
|
||||
"\tcpw x, __bss_end\n"
|
||||
"\tjrne $0\n"
|
||||
"\tjrne 0$\n"
|
||||
"\t; Copying .data from ROM to RAM\n"
|
||||
"\t; Calculate .data section size\n"
|
||||
"\tldw x, __data_load_start\n"
|
||||
"\tldw y, __data_start\n"
|
||||
"\t$1:\n"
|
||||
"1$:\n"
|
||||
"\tld a, (x)\n"
|
||||
"\tld (y), a\n"
|
||||
"\tincw x\n"
|
||||
"\tincw y\n"
|
||||
"\tcpw y, _edata\n"
|
||||
"\tjrne $1\n");
|
||||
"\tjrne 1$\n");
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -308,9 +308,7 @@ stm8_genIVT(struct dbuf_s * oBuf, symbol ** intTable, int intCount)
|
|||
int i;
|
||||
|
||||
if (options.gasOutput)
|
||||
{
|
||||
dbuf_tprintf(oBuf, "!area\n", ".vectors");
|
||||
}
|
||||
dbuf_tprintf(oBuf, "\tint __interrupt_vect ; reset\n");
|
||||
else
|
||||
dbuf_tprintf(oBuf, "\tint s_GSINIT ; reset\n");
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue