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| author | Alexandro Trevisan <alexbaixista@gmail.com> | 2021-01-30 03:43:48 -0300 |
|---|---|---|
| committer | Alexandro Trevisan <alexbaixista@gmail.com> | 2021-01-30 03:43:48 -0300 |
| commit | 814910b366ec3186e331ae64a527b03928f27b27 (patch) | |
| tree | 3422ff9eac0328620446bdbbb421b5eddd39594c /libpsn00b/include/inline_c.h | |
| parent | afffa977373cac72518754fd4a7f2cbcc80fab48 (diff) | |
| download | psn00bsdk-814910b366ec3186e331ae64a527b03928f27b27.tar.gz | |
Added some macros for gte_stsxy3_*
Diffstat (limited to 'libpsn00b/include/inline_c.h')
| -rw-r--r-- | libpsn00b/include/inline_c.h | 64 |
1 files changed, 64 insertions, 0 deletions
diff --git a/libpsn00b/include/inline_c.h b/libpsn00b/include/inline_c.h index 3775fdd..177faf1 100644 --- a/libpsn00b/include/inline_c.h +++ b/libpsn00b/include/inline_c.h @@ -211,6 +211,70 @@ : "r"( r0 ), "r"( r1 ), "r"( r2 ) \ : "memory" ) +#define gte_stsxy3_f3( r0 ) __asm__ volatile ( \ + "swc2 $12, 8( %0 );" \ + "swc2 $13, 12( %0 );" \ + "swc2 $14, 16( %0 )" \ + : \ + : "r"( r0 ) \ + : "memory" ) + +#define gte_stsxy3_g3( r0 ) __asm__ volatile ( \ + "swc2 $12, 8( %0 );" \ + "swc2 $13, 16( %0 );" \ + "swc2 $14, 24( %0 )" \ + : \ + : "r"( r0 ) \ + : "memory" ) + +#define gte_stsxy3_ft3( r0 ) __asm__ volatile ( \ + "swc2 $12, 8( %0 );" \ + "swc2 $13, 16( %0 );" \ + "swc2 $14, 24( %0 )" \ + : \ + : "r"( r0 ) \ + : "memory" ) + +#define gte_stsxy3_gt3( r0 ) __asm__ volatile ( \ + "swc2 $12, 8( %0 );" \ + "swc2 $13, 20( %0 );" \ + "swc2 $14, 32( %0 )" \ + : \ + : "r"( r0 ) \ + : "memory" ) + +#define gte_stsxy3_f4( r0 ) __asm__ volatile ( \ + "swc2 $12, 8( %0 );" \ + "swc2 $13, 12( %0 );" \ + "swc2 $14, 16( %0 )" \ + : \ + : "r"( r0 ) \ + : "memory" ) + +#define gte_stsxy3_g4( r0 ) __asm__ volatile ( \ + "swc2 $12, 8( %0 );" \ + "swc2 $13, 16( %0 );" \ + "swc2 $14, 24( %0 )" \ + : \ + : "r"( r0 ) \ + : "memory" ) + +#define gte_stsxy3_ft4( r0 ) __asm__ volatile ( \ + "swc2 $12, 8( %0 );" \ + "swc2 $13, 16( %0 );" \ + "swc2 $14, 24( %0 )" \ + : \ + : "r"( r0 ) \ + : "memory" ) + +#define gte_stsxy3_gt4( r0 ) __asm__ volatile ( \ + "swc2 $12, 8( %0 );" \ + "swc2 $13, 20( %0 );" \ + "swc2 $14, 32( %0 )" \ + : \ + : "r"( r0 ) \ + : "memory" ) + #define gte_stsz( r0 ) __asm__ volatile ( \ "swc2 $19, 0( %0 );" \ : \ |