530 lines
17 KiB
C
530 lines
17 KiB
C
// ppc_mnemonics.h
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#define INSTR (*(ppcPtr)++)
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/* Link register related */
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#define MFLR(REG) \
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{int _reg = (REG); \
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INSTR = (0x7C0802A6 | (_reg << 21));}
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#define MTLR(REG) \
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{int _reg = (REG); \
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INSTR = (0x7C0803A6 | (_reg << 21));}
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#define MTCTR(REG) \
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{int _reg = (REG); \
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INSTR = (0x7C0903A6 | (_reg << 21));}
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#define BLR() \
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{INSTR = (0x4E800020);}
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#define BGTLR() \
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{INSTR = (0x4D810020);}
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/* Load ops */
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#define LI(REG, IMM) \
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{int _reg = (REG); \
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INSTR = (0x38000000 | (_reg << 21) | ((IMM) & 0xffff));}
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#define LIS(REG_DST, IMM) \
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{int _dst = (REG_DST); \
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INSTR = (0x3C000000 | (_dst << 21) | ((IMM) & 0xffff));}
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#define LWZ(REG_DST, OFFSET, REG) \
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{int _reg = (REG); int _dst=(REG_DST); \
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INSTR = (0x80000000 | (_dst << 21) | (_reg << 16) | ((OFFSET) & 0xffff));}
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#define LWZX(REG_DST, REG, REG_OFF) \
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{int _reg = (REG), _off = (REG_OFF); int _dst=(REG_DST); \
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INSTR = (0x7C00002E | (_dst << 21) | (_reg << 16) | (_off << 11));}
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#define LWBRX(REG_DST, REG, REG_OFF) \
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{int _reg = (REG), _off = (REG_OFF); int _dst=(REG_DST); \
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INSTR = (0x7C00042C | (_dst << 21) | (_reg << 16) | (_off << 11));}
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#define LHZ(REG_DST, OFFSET, REG) \
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{int _reg = (REG); int _dst=(REG_DST); \
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INSTR = (0xA0000000 | (_dst << 21) | (_reg << 16) | ((OFFSET) & 0xffff));}
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#define LHA(REG_DST, OFFSET, REG) \
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{int _reg = (REG); int _dst=(REG_DST); \
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INSTR = (0xA8000000 | (_dst << 21) | (_reg << 16) | ((OFFSET) & 0xffff));}
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#define LHBRX(REG_DST, REG, REG_OFF) \
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{int _reg = (REG), _off = (REG_OFF); int _dst=(REG_DST); \
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INSTR = (0x7C00062C | (_dst << 21) | (_reg << 16) | (_off << 11));}
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#define LBZ(REG_DST, OFFSET, REG) \
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{int _reg = (REG); int _dst=(REG_DST); \
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INSTR = (0x88000000 | (_dst << 21) | (_reg << 16) | ((OFFSET) & 0xffff));}
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#define LMW(REG_DST, OFFSET, REG) \
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{int _reg = (REG); int _dst=(REG_DST); \
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INSTR = (0xB8000000 | (_dst << 21) | (_reg << 16) | ((OFFSET) & 0xffff));}
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/* Store ops */
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#define STMW(REG_SRC, OFFSET, REG) \
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{int _reg = (REG), _src=(REG_SRC); \
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INSTR = (0xBC000000 | (_src << 21) | (_reg << 16) | ((OFFSET) & 0xffff));}
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#define STW(REG_SRC, OFFSET, REG) \
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{int _reg = (REG), _src=(REG_SRC); \
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INSTR = (0x90000000 | (_src << 21) | (_reg << 16) | ((OFFSET) & 0xffff));}
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#define STWBRX(REG_SRC, REG, REG_OFF) \
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{int _reg = (REG), _src=(REG_SRC), _off = (REG_OFF); \
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INSTR = (0x7C00052C | (_src << 21) | (_reg << 16) | (_off << 11));}
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#define STH(REG_SRC, OFFSET, REG) \
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{int _reg = (REG), _src=(REG_SRC); \
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INSTR = (0xB0000000 | (_src << 21) | (_reg << 16) | ((OFFSET) & 0xffff));}
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#define STHBRX(REG_SRC, REG, REG_OFF) \
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{int _reg = (REG), _src=(REG_SRC), _off = (REG_OFF); \
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INSTR = (0x7C00072C | (_src << 21) | (_reg << 16) | (_off << 11));}
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#define STB(REG_SRC, OFFSET, REG) \
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{int _reg = (REG), _src=(REG_SRC); \
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INSTR = (0x98000000 | (_src << 21) | (_reg << 16) | ((OFFSET) & 0xffff));}
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#define STWU(REG_SRC, OFFSET, REG) \
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{int _reg = (REG), _src=(REG_SRC); \
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INSTR = (0x94000000 | (_src << 21) | (_reg << 16) | ((OFFSET) & 0xffff));}
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/* Arithmic ops */
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#define ADDI(REG_DST, REG_SRC, IMM) \
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{int _src = (REG_SRC); int _dst=(REG_DST); \
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INSTR = (0x38000000 | (_dst << 21) | (_src << 16) | ((IMM) & 0xffff));}
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#define ADDIS(REG_DST, REG_SRC, IMM) \
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{int _src = (REG_SRC); int _dst=(REG_DST); \
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INSTR = (0x3C000000 | (_dst << 21) | (_src << 16) | ((IMM) & 0xffff));}
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#define MR(REG_DST, REG_SRC) \
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{int __src = (REG_SRC); int __dst=(REG_DST); \
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if (__src != __dst) {ADDI(__dst, __src, 0)}}
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#define ADD(REG_DST, REG1, REG2) \
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{int _reg1 = (REG1), _reg2 = (REG2); int _dst=(REG_DST); \
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INSTR = (0x7C000214 | (_dst << 21) | (_reg1 << 16) | (_reg2 << 11));}
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#define ADDO(REG_DST, REG1, REG2) \
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{int _reg1 = (REG1), _reg2 = (REG2); int _dst=(REG_DST); \
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INSTR = (0x7C000614 | (_dst << 21) | (_reg1 << 16) | (_reg2 << 11));}
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#define ADDEO(REG_DST, REG1, REG2) \
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{int _reg1 = (REG1), _reg2 = (REG2); int _dst=(REG_DST); \
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INSTR = (0x7C000514 | (_dst << 21) | (_reg1 << 16) | (_reg2 << 11));}
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#define ADDE(REG_DST, REG1, REG2) \
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{int _reg1 = (REG1), _reg2 = (REG2); int _dst=(REG_DST); \
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INSTR = (0x7C000114 | (_dst << 21) | (_reg1 << 16) | (_reg2 << 11));}
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#define ADDCO(REG_DST, REG1, REG2) \
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{int _reg1 = (REG1), _reg2 = (REG2); int _dst=(REG_DST); \
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INSTR = (0x7C000414 | (_dst << 21) | (_reg1 << 16) | (_reg2 << 11));}
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#define ADDIC(REG_DST, REG_SRC, IMM) \
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{int _src = (REG_SRC); int _dst=(REG_DST); \
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INSTR = (0x30000000 | (_dst << 21) | (_src << 16) | ((IMM) & 0xffff));}
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#define ADDIC_(REG_DST, REG_SRC, IMM) \
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{int _src = (REG_SRC); int _dst=(REG_DST); \
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INSTR = (0x34000000 | (_dst << 21) | (_src << 16) | ((IMM) & 0xffff));}
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#define ADDZE(REG_DST, REG_SRC) \
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{int _src = (REG_SRC); int _dst=(REG_DST); \
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INSTR = (0x7C000194 | (_dst << 21) | (_src << 16));}
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#define SUBF(REG_DST, REG1, REG2) \
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{int _reg1 = (REG1), _reg2 = (REG2); int _dst=(REG_DST); \
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INSTR = (0x7C000050 | (_dst << 21) | (_reg1 << 16) | (_reg2 << 11));}
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#define SUBFO(REG_DST, REG1, REG2) \
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{int _reg1 = (REG1), _reg2 = (REG2); int _dst=(REG_DST); \
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INSTR = (0x7C000450 | (_dst << 21) | (_reg1 << 16) | (_reg2 << 11));}
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#define SUBFC(REG_DST, REG1, REG2) \
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{int _reg1 = (REG1), _reg2 = (REG2); int _dst=(REG_DST); \
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INSTR = (0x7C000010 | (_dst << 21) | (_reg1 << 16) | (_reg2 << 11));}
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#define SUBFE(REG_DST, REG1, REG2) \
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{int _reg1 = (REG1), _reg2 = (REG2); int _dst=(REG_DST); \
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INSTR = (0x7C000110 | (_dst << 21) | (_reg1 << 16) | (_reg2 << 11));}
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#define SUBFCO(REG_DST, REG1, REG2) \
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{int _reg1 = (REG1), _reg2 = (REG2); int _dst=(REG_DST); \
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INSTR = (0x7C000410 | (_dst << 21) | (_reg1 << 16) | (_reg2 << 11));}
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#define SUBFCO_(REG_DST, REG1, REG2) \
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{int _reg1 = (REG1), _reg2 = (REG2); int _dst=(REG_DST); \
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INSTR = (0x7C000411 | (_dst << 21) | (_reg1 << 16) | (_reg2 << 11));}
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#define SUB(REG_DST, REG1, REG2) \
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{SUBF(REG_DST, REG2, REG1)}
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#define SUBO(REG_DST, REG1, REG2) \
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{SUBFO(REG_DST, REG2, REG1)}
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#define SUBCO(REG_DST, REG1, REG2) \
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{SUBFCO(REG_DST, REG2, REG1)}
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#define SUBCO_(REG_DST, REG1, REG2) \
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{SUBFCO_(REG_DST, REG2, REG1)}
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#define SRAWI(REG_DST, REG_SRC, SHIFT) \
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{int _src = (REG_SRC); int _dst=(REG_DST); \
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INSTR = (0x7C000670 | (_src << 21) | (_dst << 16) | (SHIFT << 11));}
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#define MULHW(REG_DST, REG1, REG2) \
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{int _reg1 = (REG1), _reg2 = (REG2); int _dst=(REG_DST); \
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INSTR = (0x7C000096 | (_dst << 21) | (_reg1 << 16) | (_reg2 << 11));}
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#define MULLW(REG_DST, REG1, REG2) \
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{int _reg1 = (REG1), _reg2 = (REG2); int _dst=(REG_DST); \
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INSTR = (0x7C0001D6 | (_dst << 21) | (_reg1 << 16) | (_reg2 << 11));}
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#define MULHWU(REG_DST, REG1, REG2) \
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{int _reg1 = (REG1), _reg2 = (REG2); int _dst=(REG_DST); \
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INSTR = (0x7C000016 | (_dst << 21) | (_reg1 << 16) | (_reg2 << 11));}
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#define MULLI(REG_DST, REG_SRC, IMM) \
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{int _src = (REG_SRC); int _dst=(REG_DST); \
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INSTR = (0x1C000000 | (_dst << 21) | (_src << 16) | ((IMM) & 0xffff));}
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#define DIVW(REG_DST, REG1, REG2) \
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{int _reg1 = (REG1), _reg2 = (REG2); int _dst=(REG_DST); \
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INSTR = (0x7C0003D6 | (_dst << 21) | (_reg1 << 16) | (_reg2 << 11));}
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#define DIVWU(REG_DST, REG1, REG2) \
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{int _reg1 = (REG1), _reg2 = (REG2); int _dst=(REG_DST); \
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INSTR = (0x7C000396 | (_dst << 21) | (_reg1 << 16) | (_reg2 << 11));}
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/* Branch ops */
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#define B_FROM(VAR) VAR = ppcPtr
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#define B_DST(VAR) *VAR = *VAR | (((s16)((u32)ppcPtr - (u32)VAR)) & 0xfffc)
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#define B(DST) \
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{INSTR = (0x48000000 | (((s32)(((DST)+1)<<2)) & 0x3fffffc));}
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#define B_L(VAR) \
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{B_FROM(VAR); INSTR = (0x48000000);}
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#define BA(DST) \
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{INSTR = (0x48000002 | ((s32)((DST) & 0x3fffffc)));}
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#define BLA(DST) \
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{INSTR = (0x48000003 | ((s32)((DST) & 0x3fffffc)));}
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#define BNS(DST) \
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{INSTR = (0x40830000 | (((s16)(((DST)+1)<<2)) & 0xfffc));}
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#define BNE(DST) \
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{INSTR = (0x40820000 | (((s16)(((DST)+1)<<2)) & 0xfffc));}
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#define BNE_L(VAR) \
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{B_FROM(VAR); INSTR = (0x40820000);}
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#define BEQ(DST) \
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{INSTR = (0x41820000 | (((s16)(((DST)+1)<<2)) & 0xfffc));}
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#define BEQ_L(VAR) \
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{B_FROM(VAR); INSTR = (0x41820000);}
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#define BLT(DST) \
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{INSTR = (0x41800000 | (((s16)(((DST)+1)<<2)) & 0xfffc));}
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#define BLT_L(VAR) \
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{B_FROM(VAR); INSTR = (0x41800000);}
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#define BGT(DST) \
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{INSTR = (0x41810000 | (((s16)(((DST)+1)<<2)) & 0xfffc));}
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#define BGT_L(VAR) \
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{B_FROM(VAR); INSTR = (0x41810000);}
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#define BGE(DST) \
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{INSTR = (0x40800000 | (((s16)(((DST)+1)<<2)) & 0xfffc));}
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#define BGE_L(VAR) \
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{B_FROM(VAR); INSTR = (0x40800000);}
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#define BLE(DST) \
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{INSTR = (0x40810000 | (((s16)(((DST)+1)<<2)) & 0xfffc));}
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#define BLE_L(VAR) \
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{B_FROM(VAR); INSTR = (0x40810000);}
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#define BCTRL() \
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{INSTR = (0x4E800421);}
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#define BCTR() \
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{INSTR = (0x4E800420);}
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/* compare ops */
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#define CMPLWI(REG, IMM) \
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{int _reg = (REG); \
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INSTR = (0x28000000 | (_reg << 16) | ((IMM) & 0xffff));}
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#define CMPLWI2(REG, IMM) \
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{int _reg = (REG); \
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INSTR = (0x29000000 | (_reg << 16) | ((IMM) & 0xffff));}
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#define CMPLWI7(REG, IMM) \
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{int _reg = (REG); \
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INSTR = (0x2B800000 | (_reg << 16) | ((IMM) & 0xffff));}
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#define CMPLW(REG1, REG2) \
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{int _reg1 = (REG1), _reg2 = (REG2); \
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INSTR = (0x7C000040 | (_reg1 << 16) | (_reg2 << 11));}
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#define CMPLW1(REG1, REG2) \
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{int _reg1 = (REG1), _reg2 = (REG2); \
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INSTR = (0x7C800040 | (_reg1 << 16) | (_reg2 << 11));}
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#define CMPLW2(REG1, REG2) \
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{int _reg1 = (REG1), _reg2 = (REG2); \
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INSTR = (0x7D000040 | (_reg1 << 16) | (_reg2 << 11));}
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#define CMPW(REG1, REG2) \
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{int _reg1 = (REG1), _reg2 = (REG2); \
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INSTR = (0x7C000000 | (_reg1 << 16) | (_reg2 << 11));}
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#define CMPW1(REG1, REG2) \
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{int _reg1 = (REG1), _reg2 = (REG2); \
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INSTR = (0x7C800000 | (_reg1 << 16) | (_reg2 << 11));}
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#define CMPW2(REG1, REG2) \
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{int _reg1 = (REG1), _reg2 = (REG2); \
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INSTR = (0x7D000000 | (_reg1 << 16) | (_reg2 << 11));}
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#define CMPWI(REG, IMM) \
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{int _reg = (REG); \
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INSTR = (0x2C000000 | (_reg << 16) | ((IMM) & 0xffff));}
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#define CMPWI2(REG, IMM) \
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{int _reg = (REG); \
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INSTR = (0x2D000000 | (_reg << 16) | ((IMM) & 0xffff));}
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#define MTCRF(MASK, REG) \
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{int _reg = (REG); \
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INSTR = (0x7C000120 | (_reg << 21) | (((MASK)&0xff)<<12));}
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#define MFCR(REG) \
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{int _reg = (REG); \
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INSTR = (0x7C000026 | (_reg << 21));}
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#define CROR(CR_DST, CR1, CR2) \
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{INSTR = (0x4C000382 | ((CR_DST) << 21) | ((CR1) << 16) | ((CR2) << 11));}
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#define CRXOR(CR_DST, CR1, CR2) \
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{INSTR = (0x4C000182 | ((CR_DST) << 21) | ((CR1) << 16) | ((CR2) << 11));}
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#define CRNAND(CR_DST, CR1, CR2) \
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{INSTR = (0x4C0001C2 | ((CR_DST) << 21) | ((CR1) << 16) | ((CR2) << 11));}
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#define CRANDC(CR_DST, CR1, CR2) \
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{INSTR = (0x4C000102 | ((CR_DST) << 21) | ((CR1) << 16) | ((CR2) << 11));}
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/* shift ops */
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#define RLWINM(REG_DST, REG_SRC, SHIFT, START, END) \
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{int _src = (REG_SRC); int _dst = (REG_DST); \
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INSTR = (0x54000000 | (_src << 21) | (_dst << 16) | (SHIFT << 11) | (START << 6) | (END << 1));}
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#define RLWINM_(REG_DST, REG_SRC, SHIFT, START, END) \
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{int _src = (REG_SRC); int _dst = (REG_DST); \
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INSTR = (0x54000001 | (_src << 21) | (_dst << 16) | (SHIFT << 11) | (START << 6) | (END << 1));}
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#define CLRRWI(REG_DST, REG_SRC, LEN) \
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RLWINM(REG_DST, REG_SRC, 0, 0, 31-LEN)
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#define SLWI(REG_DST, REG_SRC, SHIFT) \
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{int _shift = (SHIFT); \
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if (_shift==0) {MR(REG_DST, REG_SRC)} else \
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{RLWINM(REG_DST, REG_SRC, _shift, 0, 31-_shift)}}
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#define SRWI(REG_DST, REG_SRC, SHIFT) \
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{int _shift = (SHIFT); \
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if (_shift==0) {MR(REG_DST, REG_SRC)} else \
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RLWINM(REG_DST, REG_SRC, 32-_shift, _shift, 31)}
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#define SLW(REG_DST, REG_SRC, REG_SHIFT) \
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{int _src = (REG_SRC), _shift = (REG_SHIFT); int _dst = (REG_DST); \
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INSTR = (0x7C000030 | (_src << 21) | (_dst << 16) | (_shift << 11));}
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#define SRW(REG_DST, REG_SRC, REG_SHIFT) \
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{int _src = (REG_SRC), _shift = (REG_SHIFT); int _dst = (REG_DST); \
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INSTR = (0x7C000430 | (_src << 21) | (_dst << 16) | (_shift << 11));}
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#define SRAW(REG_DST, REG_SRC, REG_SHIFT) \
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{int _src = (REG_SRC), _shift = (REG_SHIFT); int _dst = (REG_DST); \
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INSTR = (0x7C000630 | (_src << 21) | (_dst << 16) | (_shift << 11));}
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#define SRAWI(REG_DST, REG_SRC, SHIFT) \
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{int _src = (REG_SRC); int _dst = (REG_DST); int _shift = (SHIFT); \
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if (_shift==0) {MR(REG_DST, REG_SRC)} else \
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INSTR = (0x7C000670 | (_src << 21) | (_dst << 16) | (_shift << 11));}
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#define RLWNM(REG_DST, REG_SRC, REG_SHIFT, START, END) \
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{int _src = (REG_SRC), _shift = (REG_SHIFT); int _dst = (REG_DST); \
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INSTR = (0x5C000000 | (_src << 21) | (_dst << 16) | (_shift << 11) | (START << 6) | (END << 1));}
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/* other ops */
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#define ORI(REG_DST, REG_SRC, IMM) \
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{int _src = (REG_SRC), _imm = (IMM); int _dst = (REG_DST); \
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if (!((_imm == 0) && ((_src^_dst) == 0))) \
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INSTR = (0x60000000 | (_src << 21) | (_dst << 16) | (_imm & 0xffff));}
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#define ORIS(REG_DST, REG_SRC, IMM) \
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{int _src = (REG_SRC), _imm = (IMM); int _dst = (REG_DST); \
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if (!((_imm == 0) && ((_src^_dst) == 0))) \
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INSTR = (0x64000000 | (_src << 21) | (_dst << 16) | (_imm & 0xffff));}
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#define OR(REG_DST, REG1, REG2) \
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{int _reg1 = (REG1), _reg2 = (REG2); int _dst=(REG_DST); \
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INSTR = (0x7C000378 | (_reg1 << 21) | (_dst << 16) | (_reg2 << 11));}
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#define OR_(REG_DST, REG1, REG2) \
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{int _reg1 = (REG1), _reg2 = (REG2); int _dst=(REG_DST); \
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INSTR = (0x7C000379 | (_reg1 << 21) | (_dst << 16) | (_reg2 << 11));}
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#define XORI(REG_DST, REG_SRC, IMM) \
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{int _src = (REG_SRC); int _dst=(REG_DST); \
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INSTR = (0x68000000 | (_src << 21) | (_dst << 16) | ((IMM) & 0xffff));}
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#define XOR(REG_DST, REG1, REG2) \
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{int _reg1 = (REG1), _reg2 = (REG2); int _dst=(REG_DST); \
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INSTR = (0x7C000278 | (_reg1 << 21) | (_dst << 16) | (_reg2 << 11));}
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#define XOR_(REG_DST, REG1, REG2) \
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{int _reg1 = (REG1), _reg2 = (REG2); int _dst=(REG_DST); \
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INSTR = (0x7C000279 | (_reg1 << 21) | (_dst << 16) | (_reg2 << 11));}
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#define ANDI_(REG_DST, REG_SRC, IMM) \
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{int _src = (REG_SRC); int _dst=(REG_DST); \
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INSTR = (0x70000000 | (_src << 21) | (_dst << 16) | ((IMM) & 0xffff));}
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#define AND(REG_DST, REG1, REG2) \
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{int _reg1 = (REG1), _reg2 = (REG2); int _dst=(REG_DST); \
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INSTR = (0x7C000038 | (_reg1 << 21) | (_dst << 16) | (_reg2 << 11));}
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#define NOR(REG_DST, REG1, REG2) \
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{int _reg1 = (REG1), _reg2 = (REG2); int _dst=(REG_DST); \
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INSTR = (0x7C0000f8 | (_reg1 << 21) | (_dst << 16) | (_reg2 << 11));}
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#define NEG(REG_DST, REG_SRC) \
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{int _src = (REG_SRC); int _dst=(REG_DST); \
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INSTR = (0x7C0000D0 | (_dst << 21) | (_src << 16));}
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#define NOP() \
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{INSTR = 0x60000000;}
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#define MCRXR(CR_DST) \
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{INSTR = (0x7C000400 | (CR_DST << 23));}
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#define EXTSB(REG_DST, REG_SRC) \
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{int _src = (REG_SRC); int _dst=(REG_DST); \
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INSTR = (0x7C000774 | (_src << 21) | (_dst << 16));}
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#define EXTSH(REG_DST, REG_SRC) \
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{int _src = (REG_SRC); int _dst=(REG_DST); \
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INSTR = (0x7C000734 | (_src << 21) | (_dst << 16));}
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/* floating point ops */
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#define FDIVS(FPR_DST, FPR1, FPR2) \
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{INSTR = (0xEC000024 | (FPR_DST << 21) | (FPR1 << 16) | (FPR2 << 11));}
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#define FDIV(FPR_DST, FPR1, FPR2) \
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{INSTR = (0xFC000024 | (FPR_DST << 21) | (FPR1 << 16) | (FPR2 << 11));}
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#define FMULS(FPR_DST, FPR1, FPR2) \
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{INSTR = (0xEC000032 | (FPR_DST << 21) | (FPR1 << 16) | (FPR2 << 11));}
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#define FMUL(FPR_DST, FPR1, FPR2) \
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{INSTR = (0xFC000032 | (FPR_DST << 21) | (FPR1 << 16) | (FPR2 << 11));}
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#define FADDS(FPR_DST, FPR1, FPR2) \
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{INSTR = (0xEC00002A | (FPR_DST << 21) | (FPR1 << 16) | (FPR2 << 11));}
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#define FADD(FPR_DST, FPR1, FPR2) \
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{INSTR = (0xFC00002A | (FPR_DST << 21) | (FPR1 << 16) | (FPR2 << 11));}
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#define FRSP(FPR_DST, FPR_SRC) \
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{INSTR = (0xFC000018 | (FPR_DST << 21) | (FPR_SRC << 11));}
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#define FCTIW(FPR_DST, FPR_SRC) \
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{INSTR = (0xFC00001C | (FPR_DST << 21) | (FPR_SRC << 11));}
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#define LFS(FPR_DST, OFFSET, REG) \
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{INSTR = (0xC0000000 | (FPR_DST << 21) | (REG << 16) | ((OFFSET) & 0xffff));}
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#define STFS(FPR_DST, OFFSET, REG) \
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{INSTR = (0xD0000000 | (FPR_DST << 21) | (REG << 16) | ((OFFSET) & 0xffff));}
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#define LFD(FPR_DST, OFFSET, REG) \
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{INSTR = (0xC8000000 | (FPR_DST << 21) | (REG << 16) | ((OFFSET) & 0xffff));}
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#define STFD(FPR_DST, OFFSET, REG) \
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{INSTR = (0xD8000000 | (FPR_DST << 21) | (REG << 16) | ((OFFSET) & 0xffff));}
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/* extra combined opcodes */
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#if 1
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#define LIW(REG, IMM) /* Load Immidiate Word */ \
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|
{ \
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|
int __reg = (REG); u32 __imm = (u32)(IMM); \
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if ((s32)__imm == (s32)((s16)__imm)) \
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|
{ \
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|
LI(__reg, (s32)((s16)__imm)); \
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} else if (__reg == 0) { \
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LIS(__reg, (((u32)__imm)>>16)); \
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if ((((u32)__imm) & 0xffff) != 0) \
|
|
{ \
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|
ORI(__reg, __reg, __imm); \
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|
} \
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} else { \
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|
if ((((u32)__imm) & 0xffff) == 0) { \
|
|
LIS(__reg, (((u32)__imm)>>16)); \
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|
} else { \
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|
LI(__reg, __imm); \
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|
if ((__imm & 0x8000) == 0) { \
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|
ADDIS(__reg, __reg, ((u32)__imm)>>16); \
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|
} else { \
|
|
ADDIS(__reg, __reg, ((((u32)__imm)>>16) & 0xffff) + 1); \
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|
} \
|
|
} \
|
|
/*if ((((u32)__imm) & 0xffff) != 0) \
|
|
{ \
|
|
ORI(__reg, __reg, __imm); \
|
|
}*/ \
|
|
} \
|
|
}
|
|
#else
|
|
#define LIW(REG, IMM) /* Load Immidiate Word */ \
|
|
{ \
|
|
int __reg = (REG); u32 __imm = (u32)(IMM); \
|
|
if ((s32)__imm == (s32)((s16)__imm)) \
|
|
{ \
|
|
LI(__reg, (s32)((s16)__imm)); \
|
|
} \
|
|
else \
|
|
{ \
|
|
LIS(__reg, (((u32)__imm)>>16)); \
|
|
if ((((u32)__imm) & 0xffff) != 0) \
|
|
{ \
|
|
ORI(__reg, __reg, __imm); \
|
|
} \
|
|
} \
|
|
}
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|
#endif
|