3544 lines
81 KiB
C
3544 lines
81 KiB
C
/* Pcsx - Pc Psx Emulator
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* Copyright (C) 1999-2003 Pcsx Team
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#if defined (__ppc__) || defined (__ppc64__) || defined (__powerpc__) || defined (__powerpc64__) || defined (__POWERPC__)
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#ifdef _MSC_VER_
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#pragma warning(disable:4244)
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#pragma warning(disable:4761)
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#endif
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#include <stdlib.h>
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#include <string.h>
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#include <time.h>
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#include <sys/types.h>
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#include <sys/mman.h>
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#ifndef MAP_ANONYMOUS
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#define MAP_ANONYMOUS MAP_ANON
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#endif
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#include "../psxcommon.h"
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#include "ppc.h"
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#include "reguse.h"
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#include "../r3000a.h"
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#include "../psxhle.h"
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//#define NO_CONSTANT
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u32 *psxRecLUT;
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#undef _Op_
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#define _Op_ _fOp_(psxRegs.code)
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#undef _Funct_
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#define _Funct_ _fFunct_(psxRegs.code)
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#undef _Rd_
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#define _Rd_ _fRd_(psxRegs.code)
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#undef _Rt_
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#define _Rt_ _fRt_(psxRegs.code)
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#undef _Rs_
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#define _Rs_ _fRs_(psxRegs.code)
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#undef _Sa_
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#define _Sa_ _fSa_(psxRegs.code)
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#undef _Im_
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#define _Im_ _fIm_(psxRegs.code)
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#undef _Target_
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#define _Target_ _fTarget_(psxRegs.code)
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#undef _Imm_
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#define _Imm_ _fImm_(psxRegs.code)
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#undef _ImmU_
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#define _ImmU_ _fImmU_(psxRegs.code)
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#undef PC_REC
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#undef PC_REC8
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#undef PC_REC16
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#undef PC_REC32
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#define PC_REC(x) (psxRecLUT[x >> 16] + (x & 0xffff))
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#define PC_REC8(x) (*(u8 *)PC_REC(x))
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#define PC_REC16(x) (*(u16*)PC_REC(x))
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#define PC_REC32(x) (*(u32*)PC_REC(x))
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#define OFFSET(X,Y) ((u32)(Y)-(u32)(X))
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#define RECMEM_SIZE (12*1024*1024)
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static char *recMem; /* the recompiled blocks will be here */
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static char *recRAM; /* and the ptr to the blocks here */
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static char *recROM; /* and here */
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static u32 pc; /* recompiler pc */
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static u32 pcold; /* recompiler oldpc */
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static int count; /* recompiler intruction count */
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static int branch; /* set for branch */
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static u32 target; /* branch target */
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static u32 resp;
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u32 cop2readypc = 0;
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u32 idlecyclecount = 0;
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#define NUM_REGISTERS 34
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typedef struct {
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int state;
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u32 k;
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int reg;
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} iRegisters;
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static iRegisters iRegs[34];
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#define ST_UNK 0x00
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#define ST_CONST 0x01
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#define ST_MAPPED 0x02
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#ifdef NO_CONSTANT
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#define IsConst(reg) 0
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#else
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#define IsConst(reg) (iRegs[reg].state & ST_CONST)
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#endif
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#define IsMapped(reg) (iRegs[reg].state & ST_MAPPED)
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static void (*recBSC[64])();
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static void (*recSPC[64])();
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static void (*recREG[32])();
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static void (*recCP0[32])();
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static void (*recCP2[64])();
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static void (*recCP2BSC[32])();
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#define REG_LO 32
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#define REG_HI 33
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// Hardware register usage
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#define HWUSAGE_NONE 0x00
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#define HWUSAGE_READ 0x01
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#define HWUSAGE_WRITE 0x02
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#define HWUSAGE_CONST 0x04
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#define HWUSAGE_ARG 0x08 /* used as an argument for a function call */
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#define HWUSAGE_RESERVED 0x10 /* won't get flushed when flushing all regs */
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#define HWUSAGE_SPECIAL 0x20 /* special purpose register */
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#define HWUSAGE_HARDWIRED 0x40 /* specific hardware register mapping that is never disposed */
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#define HWUSAGE_INITED 0x80
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#define HWUSAGE_PSXREG 0x100
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// Remember to invalidate the special registers if they are modified by compiler
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enum {
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ARG1 = 3,
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ARG2 = 4,
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ARG3 = 5,
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PSXREGS, // ptr
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PSXMEM, // ptr
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CYCLECOUNT, // ptr
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PSXPC, // ptr
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TARGETPTR, // ptr
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TARGET, // ptr
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RETVAL,
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REG_RZERO,
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REG_WZERO
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};
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typedef struct {
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int code;
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u32 k;
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int usage;
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int lastUsed;
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void (*flush)(int hwreg);
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int private;
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} HWRegister;
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static HWRegister HWRegisters[NUM_HW_REGISTERS];
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static int HWRegUseCount;
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static int DstCPUReg;
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static int UniqueRegAlloc;
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static int GetFreeHWReg();
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static void InvalidateCPURegs();
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static void DisposeHWReg(int index);
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static void FlushHWReg(int index);
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static void FlushAllHWReg();
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static void MapPsxReg32(int reg);
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static void FlushPsxReg32(int hwreg);
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static int UpdateHWRegUsage(int hwreg, int usage);
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static int GetHWReg32(int reg);
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static int PutHWReg32(int reg);
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static int GetSpecialIndexFromHWRegs(int which);
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static int GetHWRegFromCPUReg(int cpureg);
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static int MapRegSpecial(int which);
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static void FlushRegSpecial(int hwreg);
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static int GetHWRegSpecial(int which);
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static int PutHWRegSpecial(int which);
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static void recRecompile();
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static void recError();
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#pragma mark --- Generic register mapping ---
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static int GetFreeHWReg()
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{
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int i, least, index;
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if (DstCPUReg != -1) {
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index = GetHWRegFromCPUReg(DstCPUReg);
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DstCPUReg = -1;
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} else {
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// LRU algorith with a twist ;)
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for (i=0; i<NUM_HW_REGISTERS; i++) {
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if (!(HWRegisters[i].usage & HWUSAGE_RESERVED)) {
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break;
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}
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}
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least = HWRegisters[i].lastUsed; index = i;
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for (; i<NUM_HW_REGISTERS; i++) {
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if (!(HWRegisters[i].usage & HWUSAGE_RESERVED)) {
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if (HWRegisters[i].usage == HWUSAGE_NONE && HWRegisters[i].code >= 13) {
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index = i;
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break;
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}
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else if (HWRegisters[i].lastUsed < least) {
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least = HWRegisters[i].lastUsed;
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index = i;
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}
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}
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}
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// Cycle the registers
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if (HWRegisters[index].usage == HWUSAGE_NONE) {
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for (; i<NUM_HW_REGISTERS; i++) {
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if (!(HWRegisters[i].usage & HWUSAGE_RESERVED)) {
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if (HWRegisters[i].usage == HWUSAGE_NONE &&
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HWRegisters[i].code >= 13 &&
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HWRegisters[i].lastUsed < least) {
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least = HWRegisters[i].lastUsed;
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index = i;
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break;
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}
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}
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}
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}
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}
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/* if (HWRegisters[index].code < 13 && HWRegisters[index].code > 3) {
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SysPrintf("Allocating volatile register %i\n", HWRegisters[index].code);
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}
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if (HWRegisters[index].usage != HWUSAGE_NONE) {
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SysPrintf("RegUse too big. Flushing %i\n", HWRegisters[index].code);
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}*/
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if (HWRegisters[index].usage & (HWUSAGE_RESERVED | HWUSAGE_HARDWIRED)) {
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if (HWRegisters[index].usage & HWUSAGE_RESERVED) {
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SysPrintf("Error! Trying to map a new register to a reserved register (r%i)",
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HWRegisters[index].code);
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}
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if (HWRegisters[index].usage & HWUSAGE_HARDWIRED) {
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SysPrintf("Error! Trying to map a new register to a hardwired register (r%i)",
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HWRegisters[index].code);
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}
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}
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if (HWRegisters[index].lastUsed != 0) {
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UniqueRegAlloc = 0;
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}
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// Make sure the register is really flushed!
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FlushHWReg(index);
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HWRegisters[index].usage = HWUSAGE_NONE;
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HWRegisters[index].flush = NULL;
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return index;
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}
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static void FlushHWReg(int index)
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{
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if (index < 0) return;
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if (HWRegisters[index].usage == HWUSAGE_NONE) return;
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if (HWRegisters[index].flush) {
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HWRegisters[index].usage |= HWUSAGE_RESERVED;
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HWRegisters[index].flush(index);
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HWRegisters[index].flush = NULL;
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}
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if (HWRegisters[index].usage & HWUSAGE_HARDWIRED) {
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HWRegisters[index].usage &= ~(HWUSAGE_READ | HWUSAGE_WRITE);
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} else {
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HWRegisters[index].usage = HWUSAGE_NONE;
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}
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}
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// get rid of a mapped register without flushing the contents to the memory
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static void DisposeHWReg(int index)
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{
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if (index < 0) return;
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if (HWRegisters[index].usage == HWUSAGE_NONE) return;
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HWRegisters[index].usage &= ~(HWUSAGE_READ | HWUSAGE_WRITE);
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if (HWRegisters[index].usage == HWUSAGE_NONE) {
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SysPrintf("Error! not correctly disposing register (r%i)", HWRegisters[index].code);
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}
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FlushHWReg(index);
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}
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// operated on cpu registers
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__inline static void FlushCPURegRange(int start, int end)
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{
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int i;
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if (end <= 0) end = 31;
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if (start <= 0) start = 0;
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for (i=0; i<NUM_HW_REGISTERS; i++) {
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if (HWRegisters[i].code >= start && HWRegisters[i].code <= end)
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if (HWRegisters[i].flush)
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FlushHWReg(i);
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}
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for (i=0; i<NUM_HW_REGISTERS; i++) {
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if (HWRegisters[i].code >= start && HWRegisters[i].code <= end)
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FlushHWReg(i);
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}
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}
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static void FlushAllHWReg()
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{
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FlushCPURegRange(0,31);
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}
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static void InvalidateCPURegs()
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{
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FlushCPURegRange(0,12);
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}
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#pragma mark --- Mapping utility functions ---
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static void MoveHWRegToCPUReg(int cpureg, int hwreg)
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{
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int dstreg;
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if (HWRegisters[hwreg].code == cpureg)
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return;
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dstreg = GetHWRegFromCPUReg(cpureg);
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HWRegisters[dstreg].usage &= ~(HWUSAGE_HARDWIRED | HWUSAGE_ARG);
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if (HWRegisters[hwreg].usage & (HWUSAGE_READ | HWUSAGE_WRITE)) {
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FlushHWReg(dstreg);
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MR(HWRegisters[dstreg].code, HWRegisters[hwreg].code);
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} else {
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if (HWRegisters[dstreg].usage & (HWUSAGE_READ | HWUSAGE_WRITE)) {
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MR(HWRegisters[hwreg].code, HWRegisters[dstreg].code);
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}
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else if (HWRegisters[dstreg].usage != HWUSAGE_NONE) {
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FlushHWReg(dstreg);
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}
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}
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HWRegisters[dstreg].code = HWRegisters[hwreg].code;
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HWRegisters[hwreg].code = cpureg;
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}
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static int UpdateHWRegUsage(int hwreg, int usage)
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{
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HWRegisters[hwreg].lastUsed = ++HWRegUseCount;
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if (usage & HWUSAGE_WRITE) {
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HWRegisters[hwreg].usage &= ~HWUSAGE_CONST;
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}
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if (!(usage & HWUSAGE_INITED)) {
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HWRegisters[hwreg].usage &= ~HWUSAGE_INITED;
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}
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HWRegisters[hwreg].usage |= usage;
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return HWRegisters[hwreg].code;
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}
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static int GetHWRegFromCPUReg(int cpureg)
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{
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int i;
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for (i=0; i<NUM_HW_REGISTERS; i++) {
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if (HWRegisters[i].code == cpureg) {
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return i;
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}
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}
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SysPrintf("Error! Register location failure (r%i)", cpureg);
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return 0;
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}
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// this function operates on cpu registers
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void SetDstCPUReg(int cpureg)
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{
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DstCPUReg = cpureg;
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}
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static void ReserveArgs(int args)
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{
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int index, i;
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for (i=0; i<args; i++) {
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index = GetHWRegFromCPUReg(3+i);
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HWRegisters[index].usage |= HWUSAGE_RESERVED | HWUSAGE_HARDWIRED | HWUSAGE_ARG;
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}
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}
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static void ReleaseArgs()
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{
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int i;
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for (i=0; i<NUM_HW_REGISTERS; i++) {
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if (HWRegisters[i].usage & HWUSAGE_ARG) {
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//HWRegisters[i].usage = HWUSAGE_NONE;
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//HWRegisters[i].flush = NULL;
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HWRegisters[i].usage &= ~(HWUSAGE_RESERVED | HWUSAGE_HARDWIRED | HWUSAGE_ARG);
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FlushHWReg(i);
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}
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}
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}
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#pragma mark --- Psx register mapping ---
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static void MapPsxReg32(int reg)
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{
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int hwreg = GetFreeHWReg();
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HWRegisters[hwreg].flush = FlushPsxReg32;
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HWRegisters[hwreg].private = reg;
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if (iRegs[reg].reg != -1) {
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SysPrintf("error: double mapped psx register");
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}
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iRegs[reg].reg = hwreg;
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iRegs[reg].state |= ST_MAPPED;
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}
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static void FlushPsxReg32(int hwreg)
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{
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int reg = HWRegisters[hwreg].private;
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if (iRegs[reg].reg == -1) {
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SysPrintf("error: flushing unmapped psx register");
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}
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if (HWRegisters[hwreg].usage & HWUSAGE_WRITE) {
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if (branch) {
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/*int reguse = nextPsxRegUse(pc-8, reg);
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if (reguse == REGUSE_NONE || (reguse & REGUSE_READ))*/ {
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STW(HWRegisters[hwreg].code, OFFSET(&psxRegs, &psxRegs.GPR.r[reg]), GetHWRegSpecial(PSXREGS));
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}
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} else {
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int reguse = nextPsxRegUse(pc-4, reg);
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if (reguse == REGUSE_NONE || (reguse & REGUSE_READ)) {
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STW(HWRegisters[hwreg].code, OFFSET(&psxRegs, &psxRegs.GPR.r[reg]), GetHWRegSpecial(PSXREGS));
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}
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}
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}
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iRegs[reg].reg = -1;
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iRegs[reg].state = ST_UNK;
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}
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static int GetHWReg32(int reg)
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{
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int usage = HWUSAGE_PSXREG | HWUSAGE_READ;
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if (reg == 0) {
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return GetHWRegSpecial(REG_RZERO);
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}
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if (!IsMapped(reg)) {
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usage |= HWUSAGE_INITED;
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MapPsxReg32(reg);
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HWRegisters[iRegs[reg].reg].usage |= HWUSAGE_RESERVED;
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if (IsConst(reg)) {
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LIW(HWRegisters[iRegs[reg].reg].code, iRegs[reg].k);
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usage |= HWUSAGE_WRITE | HWUSAGE_CONST;
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//iRegs[reg].state &= ~ST_CONST;
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}
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else {
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LWZ(HWRegisters[iRegs[reg].reg].code, OFFSET(&psxRegs, &psxRegs.GPR.r[reg]), GetHWRegSpecial(PSXREGS));
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}
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HWRegisters[iRegs[reg].reg].usage &= ~HWUSAGE_RESERVED;
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}
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else if (DstCPUReg != -1) {
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int dst = DstCPUReg;
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DstCPUReg = -1;
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if (HWRegisters[iRegs[reg].reg].code < 13) {
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MoveHWRegToCPUReg(dst, iRegs[reg].reg);
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} else {
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MR(DstCPUReg, HWRegisters[iRegs[reg].reg].code);
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}
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}
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DstCPUReg = -1;
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return UpdateHWRegUsage(iRegs[reg].reg, usage);
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}
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static int PutHWReg32(int reg)
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{
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int usage = HWUSAGE_PSXREG | HWUSAGE_WRITE;
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if (reg == 0) {
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return PutHWRegSpecial(REG_WZERO);
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}
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if (DstCPUReg != -1 && IsMapped(reg)) {
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if (HWRegisters[iRegs[reg].reg].code != DstCPUReg) {
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int tmp = DstCPUReg;
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DstCPUReg = -1;
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DisposeHWReg(iRegs[reg].reg);
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DstCPUReg = tmp;
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}
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}
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if (!IsMapped(reg)) {
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usage |= HWUSAGE_INITED;
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MapPsxReg32(reg);
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}
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DstCPUReg = -1;
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iRegs[reg].state &= ~ST_CONST;
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return UpdateHWRegUsage(iRegs[reg].reg, usage);
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}
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#pragma mark --- Special register mapping ---
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static int GetSpecialIndexFromHWRegs(int which)
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{
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int i;
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for (i=0; i<NUM_HW_REGISTERS; i++) {
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if (HWRegisters[i].usage & HWUSAGE_SPECIAL) {
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if (HWRegisters[i].private == which) {
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return i;
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}
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}
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}
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return -1;
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}
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static int MapRegSpecial(int which)
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{
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int hwreg = GetFreeHWReg();
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HWRegisters[hwreg].flush = FlushRegSpecial;
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HWRegisters[hwreg].private = which;
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return hwreg;
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}
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static void FlushRegSpecial(int hwreg)
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{
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int which = HWRegisters[hwreg].private;
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if (!(HWRegisters[hwreg].usage & HWUSAGE_WRITE))
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return;
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switch (which) {
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case CYCLECOUNT:
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STW(HWRegisters[hwreg].code, OFFSET(&psxRegs, &psxRegs.cycle), GetHWRegSpecial(PSXREGS));
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break;
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case PSXPC:
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STW(HWRegisters[hwreg].code, OFFSET(&psxRegs, &psxRegs.pc), GetHWRegSpecial(PSXREGS));
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break;
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case TARGET:
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STW(HWRegisters[hwreg].code, 0, GetHWRegSpecial(TARGETPTR));
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break;
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}
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}
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static int GetHWRegSpecial(int which)
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{
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int index = GetSpecialIndexFromHWRegs(which);
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int usage = HWUSAGE_READ | HWUSAGE_SPECIAL;
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if (index == -1) {
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usage |= HWUSAGE_INITED;
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index = MapRegSpecial(which);
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HWRegisters[index].usage |= HWUSAGE_RESERVED;
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switch (which) {
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case PSXREGS:
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case PSXMEM:
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SysPrintf("error! shouldn't be here!\n");
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//HWRegisters[index].flush = NULL;
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//LIW(HWRegisters[index].code, (u32)&psxRegs);
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break;
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case TARGETPTR:
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HWRegisters[index].flush = NULL;
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LIW(HWRegisters[index].code, (u32)&target);
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break;
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case REG_RZERO:
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HWRegisters[index].flush = NULL;
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LIW(HWRegisters[index].code, 0);
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break;
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case RETVAL:
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MoveHWRegToCPUReg(3, index);
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/*reg = GetHWRegFromCPUReg(3);
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HWRegisters[reg].code = HWRegisters[index].code;
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HWRegisters[index].code = 3;*/
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HWRegisters[index].flush = NULL;
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usage |= HWUSAGE_RESERVED;
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break;
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case CYCLECOUNT:
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LWZ(HWRegisters[index].code, OFFSET(&psxRegs, &psxRegs.cycle), GetHWRegSpecial(PSXREGS));
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break;
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case PSXPC:
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LWZ(HWRegisters[index].code, OFFSET(&psxRegs, &psxRegs.pc), GetHWRegSpecial(PSXREGS));
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break;
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case TARGET:
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LWZ(HWRegisters[index].code, 0, GetHWRegSpecial(TARGETPTR));
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break;
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default:
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SysPrintf("Error: Unknown special register in GetHWRegSpecial()\n");
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break;
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}
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HWRegisters[index].usage &= ~HWUSAGE_RESERVED;
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}
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else if (DstCPUReg != -1) {
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int dst = DstCPUReg;
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DstCPUReg = -1;
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MoveHWRegToCPUReg(dst, index);
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}
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return UpdateHWRegUsage(index, usage);
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}
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static int PutHWRegSpecial(int which)
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{
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int index = GetSpecialIndexFromHWRegs(which);
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int usage = HWUSAGE_WRITE | HWUSAGE_SPECIAL;
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if (DstCPUReg != -1 && index != -1) {
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if (HWRegisters[index].code != DstCPUReg) {
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int tmp = DstCPUReg;
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DstCPUReg = -1;
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DisposeHWReg(index);
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DstCPUReg = tmp;
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}
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}
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switch (which) {
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case PSXREGS:
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case TARGETPTR:
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SysPrintf("Error: Read-only special register in PutHWRegSpecial()\n");
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case REG_WZERO:
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if (index >= 0) {
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if (HWRegisters[index].usage & HWUSAGE_WRITE)
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break;
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}
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index = MapRegSpecial(which);
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HWRegisters[index].flush = NULL;
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break;
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default:
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if (index == -1) {
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usage |= HWUSAGE_INITED;
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index = MapRegSpecial(which);
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HWRegisters[index].usage |= HWUSAGE_RESERVED;
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switch (which) {
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case ARG1:
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case ARG2:
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case ARG3:
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MoveHWRegToCPUReg(3+(which-ARG1), index);
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/*reg = GetHWRegFromCPUReg(3+(which-ARG1));
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if (HWRegisters[reg].usage != HWUSAGE_NONE) {
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HWRegisters[reg].usage &= ~(HWUSAGE_HARDWIRED | HWUSAGE_ARG);
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if (HWRegisters[reg].flush != NULL && HWRegisters[reg].usage & (HWUSAGE_WRITE | HWUSAGE_READ)) {
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MR(HWRegisters[index].code, HWRegisters[reg].code);
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} else {
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FlushHWReg(reg);
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}
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}
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HWRegisters[reg].code = HWRegisters[index].code;
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if (!(HWRegisters[index].code >= 3 && HWRegisters[index].code <=31))
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SysPrintf("Error! Register allocation");
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HWRegisters[index].code = 3+(which-ARG1);*/
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HWRegisters[index].flush = NULL;
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usage |= HWUSAGE_RESERVED | HWUSAGE_HARDWIRED | HWUSAGE_ARG;
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break;
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}
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}
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HWRegisters[index].usage &= ~HWUSAGE_RESERVED;
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break;
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}
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DstCPUReg = -1;
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return UpdateHWRegUsage(index, usage);
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}
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#pragma mark --- ---
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static void MapConst(int reg, u32 _const) {
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if (reg == 0)
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return;
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if (IsConst(reg) && iRegs[reg].k == _const)
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return;
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DisposeHWReg(iRegs[reg].reg);
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iRegs[reg].k = _const;
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iRegs[reg].state = ST_CONST;
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}
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static void MapCopy(int dst, int src)
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{
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// do it the lazy way for now
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MR(PutHWReg32(dst), GetHWReg32(src));
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}
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static void iFlushReg(u32 nextpc, int reg) {
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if (!IsMapped(reg) && IsConst(reg)) {
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GetHWReg32(reg);
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}
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if (IsMapped(reg)) {
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if (nextpc) {
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int use = nextPsxRegUse(nextpc, reg);
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if ((use & REGUSE_RW) == REGUSE_WRITE) {
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DisposeHWReg(iRegs[reg].reg);
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} else {
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FlushHWReg(iRegs[reg].reg);
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}
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} else {
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FlushHWReg(iRegs[reg].reg);
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}
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}
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}
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static void iFlushRegs(u32 nextpc) {
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int i;
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for (i=1; i<NUM_REGISTERS; i++) {
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iFlushReg(nextpc, i);
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}
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}
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static void Return()
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{
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iFlushRegs(0);
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FlushAllHWReg();
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if (((u32)returnPC & 0x1fffffc) == (u32)returnPC) {
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BA((u32)returnPC);
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}
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else {
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LIW(0, (u32)returnPC);
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MTLR(0);
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BLR();
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}
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}
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static void iRet() {
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/* store cycle */
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count = (idlecyclecount + (pc - pcold) / 4) * BIAS;
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ADDI(PutHWRegSpecial(CYCLECOUNT), GetHWRegSpecial(CYCLECOUNT), count);
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Return();
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}
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static int iLoadTest() {
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u32 tmp;
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// check for load delay
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tmp = psxRegs.code >> 26;
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switch (tmp) {
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case 0x10: // COP0
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switch (_Rs_) {
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case 0x00: // MFC0
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case 0x02: // CFC0
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return 1;
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}
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break;
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case 0x12: // COP2
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switch (_Funct_) {
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case 0x00:
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switch (_Rs_) {
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case 0x00: // MFC2
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case 0x02: // CFC2
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return 1;
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}
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break;
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}
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break;
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case 0x32: // LWC2
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return 1;
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default:
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if (tmp >= 0x20 && tmp <= 0x26) { // LB/LH/LWL/LW/LBU/LHU/LWR
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return 1;
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}
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break;
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}
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return 0;
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}
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/* set a pending branch */
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static void SetBranch() {
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int treg;
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branch = 1;
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psxRegs.code = PSXMu32(pc);
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pc+=4;
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if (iLoadTest() == 1) {
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iFlushRegs(0);
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LIW(0, psxRegs.code);
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STW(0, OFFSET(&psxRegs, &psxRegs.code), GetHWRegSpecial(PSXREGS));
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/* store cycle */
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count = (idlecyclecount + (pc - pcold) / 4) * BIAS;
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ADDI(PutHWRegSpecial(CYCLECOUNT), GetHWRegSpecial(CYCLECOUNT), count);
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treg = GetHWRegSpecial(TARGET);
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MR(PutHWRegSpecial(ARG2), treg);
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DisposeHWReg(GetHWRegFromCPUReg(treg));
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LIW(PutHWRegSpecial(ARG1), _Rt_);
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LIW(GetHWRegSpecial(PSXPC), pc);
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FlushAllHWReg();
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CALLFunc((u32)psxDelayTest);
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Return();
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return;
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}
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recBSC[psxRegs.code>>26]();
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iFlushRegs(0);
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treg = GetHWRegSpecial(TARGET);
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MR(PutHWRegSpecial(PSXPC), GetHWRegSpecial(TARGET)); // FIXME: this line should not be needed
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DisposeHWReg(GetHWRegFromCPUReg(treg));
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FlushAllHWReg();
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count = (idlecyclecount + (pc - pcold) / 4) * BIAS;
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ADDI(PutHWRegSpecial(CYCLECOUNT), GetHWRegSpecial(CYCLECOUNT), count);
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FlushAllHWReg();
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CALLFunc((u32)psxBranchTest);
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// TODO: don't return if target is compiled
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Return();
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}
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static void iJump(u32 branchPC) {
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u32 *b1, *b2;
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branch = 1;
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psxRegs.code = PSXMu32(pc);
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pc+=4;
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if (iLoadTest() == 1) {
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iFlushRegs(0);
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LIW(0, psxRegs.code);
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STW(0, OFFSET(&psxRegs, &psxRegs.code), GetHWRegSpecial(PSXREGS));
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/* store cycle */
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count = (idlecyclecount + (pc - pcold) / 4) * BIAS;
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ADDI(PutHWRegSpecial(CYCLECOUNT), GetHWRegSpecial(CYCLECOUNT), count);
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LIW(PutHWRegSpecial(ARG2), branchPC);
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LIW(PutHWRegSpecial(ARG1), _Rt_);
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LIW(GetHWRegSpecial(PSXPC), pc);
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FlushAllHWReg();
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CALLFunc((u32)psxDelayTest);
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Return();
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return;
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}
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|
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recBSC[psxRegs.code>>26]();
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|
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iFlushRegs(branchPC);
|
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LIW(PutHWRegSpecial(PSXPC), branchPC);
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FlushAllHWReg();
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count = (idlecyclecount + (pc - pcold) / 4) * BIAS;
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//if (/*psxRegs.code == 0 &&*/ count == 2 && branchPC == pcold) {
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// LIW(PutHWRegSpecial(CYCLECOUNT), 0);
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//} else {
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ADDI(PutHWRegSpecial(CYCLECOUNT), GetHWRegSpecial(CYCLECOUNT), count);
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//}
|
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FlushAllHWReg();
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CALLFunc((u32)psxBranchTest);
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if (!Config.HLE && Config.PsxOut &&
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((branchPC & 0x1fffff) == 0xa0 ||
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(branchPC & 0x1fffff) == 0xb0 ||
|
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(branchPC & 0x1fffff) == 0xc0))
|
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CALLFunc((u32)psxJumpTest);
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|
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// always return for now...
|
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//Return();
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|
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// maybe just happened an interruption, check so
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LIW(0, branchPC);
|
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CMPLW(GetHWRegSpecial(PSXPC), 0);
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BNE_L(b1);
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|
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LIW(3, PC_REC(branchPC));
|
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LWZ(3, 0, 3);
|
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CMPLWI(3, 0);
|
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BNE_L(b2);
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|
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B_DST(b1);
|
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Return();
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|
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// next bit is already compiled - jump right to it
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B_DST(b2);
|
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MTCTR(3);
|
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BCTR();
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}
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|
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static void iBranch(u32 branchPC, int savectx) {
|
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HWRegister HWRegistersS[NUM_HW_REGISTERS];
|
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iRegisters iRegsS[NUM_REGISTERS];
|
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int HWRegUseCountS = 0;
|
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u32 respold=0;
|
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u32 *b1, *b2;
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|
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if (savectx) {
|
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respold = resp;
|
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memcpy(iRegsS, iRegs, sizeof(iRegs));
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memcpy(HWRegistersS, HWRegisters, sizeof(HWRegisters));
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HWRegUseCountS = HWRegUseCount;
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}
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|
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branch = 1;
|
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psxRegs.code = PSXMu32(pc);
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|
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// the delay test is only made when the branch is taken
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// savectx == 0 will mean that :)
|
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if (savectx == 0 && iLoadTest() == 1) {
|
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iFlushRegs(0);
|
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LIW(0, psxRegs.code);
|
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STW(0, OFFSET(&psxRegs, &psxRegs.code), GetHWRegSpecial(PSXREGS));
|
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/* store cycle */
|
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count = (idlecyclecount + ((pc+4) - pcold) / 4) * BIAS;
|
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ADDI(PutHWRegSpecial(CYCLECOUNT), GetHWRegSpecial(CYCLECOUNT), count);
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|
|
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LIW(PutHWRegSpecial(ARG2), branchPC);
|
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LIW(PutHWRegSpecial(ARG1), _Rt_);
|
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LIW(GetHWRegSpecial(PSXPC), pc);
|
|
FlushAllHWReg();
|
|
CALLFunc((u32)psxDelayTest);
|
|
|
|
Return();
|
|
return;
|
|
}
|
|
|
|
pc+= 4;
|
|
recBSC[psxRegs.code>>26]();
|
|
|
|
iFlushRegs(branchPC);
|
|
LIW(PutHWRegSpecial(PSXPC), branchPC);
|
|
FlushAllHWReg();
|
|
|
|
/* store cycle */
|
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count = (idlecyclecount + (pc - pcold) / 4) * BIAS;
|
|
//if (/*psxRegs.code == 0 &&*/ count == 2 && branchPC == pcold) {
|
|
// LIW(PutHWRegSpecial(CYCLECOUNT), 0);
|
|
//} else {
|
|
ADDI(PutHWRegSpecial(CYCLECOUNT), GetHWRegSpecial(CYCLECOUNT), count);
|
|
//}
|
|
FlushAllHWReg();
|
|
CALLFunc((u32)psxBranchTest);
|
|
|
|
// always return for now...
|
|
//Return();
|
|
|
|
LIW(0, branchPC);
|
|
CMPLW(GetHWRegSpecial(PSXPC), 0);
|
|
BNE_L(b1);
|
|
|
|
LIW(3, PC_REC(branchPC));
|
|
LWZ(3, 0, 3);
|
|
CMPLWI(3, 0);
|
|
BNE_L(b2);
|
|
|
|
B_DST(b1);
|
|
Return();
|
|
|
|
B_DST(b2);
|
|
MTCTR(3);
|
|
BCTR();
|
|
|
|
// maybe just happened an interruption, check so
|
|
/* CMP32ItoM((u32)&psxRegs.pc, branchPC);
|
|
j8Ptr[1] = JE8(0);
|
|
RET();
|
|
|
|
x86SetJ8(j8Ptr[1]);
|
|
MOV32MtoR(EAX, PC_REC(branchPC));
|
|
TEST32RtoR(EAX, EAX);
|
|
j8Ptr[2] = JNE8(0);
|
|
RET();
|
|
|
|
x86SetJ8(j8Ptr[2]);
|
|
JMP32R(EAX);*/
|
|
|
|
pc-= 4;
|
|
if (savectx) {
|
|
resp = respold;
|
|
memcpy(iRegs, iRegsS, sizeof(iRegs));
|
|
memcpy(HWRegisters, HWRegistersS, sizeof(HWRegisters));
|
|
HWRegUseCount = HWRegUseCountS;
|
|
}
|
|
}
|
|
|
|
|
|
static void iDumpRegs() {
|
|
int i, j;
|
|
|
|
printf("%lx %lx\n", psxRegs.pc, psxRegs.cycle);
|
|
for (i=0; i<4; i++) {
|
|
for (j=0; j<8; j++)
|
|
printf("%lx ", psxRegs.GPR.r[j*i]);
|
|
printf("\n");
|
|
}
|
|
}
|
|
|
|
void iDumpBlock(char *ptr) {
|
|
/* FILE *f;
|
|
u32 i;
|
|
|
|
SysPrintf("dump1 %x:%x, %x\n", psxRegs.pc, pc, psxCurrentCycle);
|
|
|
|
for (i = psxRegs.pc; i < pc; i+=4)
|
|
SysPrintf("%s\n", disR3000AF(PSXMu32(i), i));
|
|
|
|
fflush(stdout);
|
|
f = fopen("dump1", "w");
|
|
fwrite(ptr, 1, (u32)x86Ptr - (u32)ptr, f);
|
|
fclose(f);
|
|
system("ndisasmw -u dump1");
|
|
fflush(stdout);*/
|
|
}
|
|
|
|
#define REC_FUNC(f) \
|
|
void psx##f(); \
|
|
static void rec##f() { \
|
|
iFlushRegs(0); \
|
|
LIW(PutHWRegSpecial(ARG1), (u32)psxRegs.code); \
|
|
STW(GetHWRegSpecial(ARG1), OFFSET(&psxRegs, &psxRegs.code), GetHWRegSpecial(PSXREGS)); \
|
|
LIW(PutHWRegSpecial(PSXPC), (u32)pc); \
|
|
FlushAllHWReg(); \
|
|
CALLFunc((u32)psx##f); \
|
|
/* branch = 2; */\
|
|
}
|
|
|
|
#define REC_SYS(f) \
|
|
void psx##f(); \
|
|
static void rec##f() { \
|
|
iFlushRegs(0); \
|
|
LIW(PutHWRegSpecial(ARG1), (u32)psxRegs.code); \
|
|
STW(GetHWRegSpecial(ARG1), OFFSET(&psxRegs, &psxRegs.code), GetHWRegSpecial(PSXREGS)); \
|
|
LIW(PutHWRegSpecial(PSXPC), (u32)pc); \
|
|
FlushAllHWReg(); \
|
|
CALLFunc((u32)psx##f); \
|
|
branch = 2; \
|
|
iRet(); \
|
|
}
|
|
|
|
#define REC_BRANCH(f) \
|
|
void psx##f(); \
|
|
static void rec##f() { \
|
|
iFlushRegs(0); \
|
|
LIW(PutHWRegSpecial(ARG1), (u32)psxRegs.code); \
|
|
STW(GetHWRegSpecial(ARG1), OFFSET(&psxRegs, &psxRegs.code), GetHWRegSpecial(PSXREGS)); \
|
|
LIW(PutHWRegSpecial(PSXPC), (u32)pc); \
|
|
FlushAllHWReg(); \
|
|
CALLFunc((u32)psx##f); \
|
|
branch = 2; \
|
|
iRet(); \
|
|
}
|
|
|
|
static void freeMem(int all)
|
|
{
|
|
if (recMem) free(recMem);
|
|
if (recRAM) free(recRAM);
|
|
if (recROM) free(recROM);
|
|
recMem = recRAM = recROM = 0;
|
|
|
|
if (all && psxRecLUT) {
|
|
free(psxRecLUT); psxRecLUT = NULL;
|
|
}
|
|
}
|
|
|
|
static int allocMem() {
|
|
int i;
|
|
|
|
freeMem(0);
|
|
|
|
if (psxRecLUT==NULL)
|
|
psxRecLUT = (u32*) malloc(0x010000 * 4);
|
|
|
|
recMem = (char*) malloc(RECMEM_SIZE);
|
|
//recMem = mmap(NULL, RECMEM_SIZE, PROT_EXEC|PROT_READ|PROT_WRITE, MAP_ANON|MAP_PRIVATE, -1, 0);
|
|
recRAM = (char*) malloc(0x200000);
|
|
recROM = (char*) malloc(0x080000);
|
|
if (recRAM == NULL || recROM == NULL || recMem == NULL/*(void *)-1*/ || psxRecLUT == NULL) {
|
|
freeMem(1);
|
|
SysMessage("Error allocating memory"); return -1;
|
|
}
|
|
|
|
for (i=0; i<0x80; i++) psxRecLUT[i + 0x0000] = (u32)&recRAM[(i & 0x1f) << 16];
|
|
memcpy(psxRecLUT + 0x8000, psxRecLUT, 0x80 * 4);
|
|
memcpy(psxRecLUT + 0xa000, psxRecLUT, 0x80 * 4);
|
|
|
|
for (i=0; i<0x08; i++) psxRecLUT[i + 0xbfc0] = (u32)&recROM[i << 16];
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int recInit() {
|
|
return allocMem();
|
|
}
|
|
|
|
static void recReset() {
|
|
memset(recRAM, 0, 0x200000);
|
|
memset(recROM, 0, 0x080000);
|
|
|
|
ppcInit();
|
|
ppcSetPtr((u32 *)recMem);
|
|
|
|
branch = 0;
|
|
memset(iRegs, 0, sizeof(iRegs));
|
|
iRegs[0].state = ST_CONST;
|
|
iRegs[0].k = 0;
|
|
}
|
|
|
|
static void recShutdown() {
|
|
freeMem(1);
|
|
ppcShutdown();
|
|
}
|
|
|
|
static void recError() {
|
|
SysReset();
|
|
ClosePlugins();
|
|
SysMessage("Unrecoverable error while running recompiler\n");
|
|
SysRunGui();
|
|
}
|
|
|
|
__inline static void execute() {
|
|
void (**recFunc)();
|
|
char *p;
|
|
|
|
p = (char*)PC_REC(psxRegs.pc);
|
|
/*if (p != NULL)*/ recFunc = (void (**)()) (u32)p;
|
|
/*else { recError(); return; }*/
|
|
|
|
if (*recFunc == 0) {
|
|
recRecompile();
|
|
}
|
|
recRun(*recFunc, (u32)&psxRegs, (u32)&psxM);
|
|
}
|
|
|
|
static void recExecute() {
|
|
for (;;) execute();
|
|
}
|
|
|
|
static void recExecuteBlock() {
|
|
execute();
|
|
}
|
|
|
|
static void recClear(u32 Addr, u32 Size) {
|
|
memset((void*)PC_REC(Addr), 0, Size * 4);
|
|
}
|
|
|
|
static void recNULL() {
|
|
// SysMessage("recUNK: %8.8x\n", psxRegs.code);
|
|
}
|
|
|
|
/*********************************************************
|
|
* goes to opcodes tables... *
|
|
* Format: table[something....] *
|
|
*********************************************************/
|
|
|
|
//REC_SYS(SPECIAL);
|
|
static void recSPECIAL() {
|
|
recSPC[_Funct_]();
|
|
}
|
|
|
|
static void recREGIMM() {
|
|
recREG[_Rt_]();
|
|
}
|
|
|
|
static void recCOP0() {
|
|
recCP0[_Rs_]();
|
|
}
|
|
|
|
//REC_SYS(COP2);
|
|
static void recCOP2() {
|
|
recCP2[_Funct_]();
|
|
}
|
|
|
|
static void recBASIC() {
|
|
recCP2BSC[_Rs_]();
|
|
}
|
|
|
|
//end of Tables opcodes...
|
|
|
|
#pragma mark - Arithmetic with immediate operand -
|
|
/*********************************************************
|
|
* Arithmetic with immediate operand *
|
|
* Format: OP rt, rs, immediate *
|
|
*********************************************************/
|
|
|
|
#if 0
|
|
/*REC_FUNC(ADDI);
|
|
REC_FUNC(ADDIU);
|
|
REC_FUNC(ANDI);
|
|
REC_FUNC(ORI);
|
|
REC_FUNC(XORI);
|
|
REC_FUNC(SLTI);
|
|
REC_FUNC(SLTIU);*/
|
|
#else
|
|
static void recADDIU() {
|
|
// Rt = Rs + Im
|
|
if (!_Rt_) return;
|
|
|
|
if (IsConst(_Rs_)) {
|
|
MapConst(_Rt_, iRegs[_Rs_].k + _Imm_);
|
|
} else {
|
|
if (_Imm_ == 0) {
|
|
MapCopy(_Rt_, _Rs_);
|
|
} else {
|
|
ADDI(PutHWReg32(_Rt_), GetHWReg32(_Rs_), _Imm_);
|
|
}
|
|
}
|
|
}
|
|
|
|
static void recADDI() {
|
|
// Rt = Rs + Im
|
|
recADDIU();
|
|
}
|
|
|
|
//REC_FUNC(SLTI);
|
|
//REC_FUNC(SLTIU);
|
|
//CR0: SIGN | POSITIVE | ZERO | SOVERFLOW | SOVERFLOW | OVERFLOW | CARRY
|
|
static void recSLTI() {
|
|
// Rt = Rs < Im (signed)
|
|
if (!_Rt_) return;
|
|
|
|
if (IsConst(_Rs_)) {
|
|
MapConst(_Rt_, (s32)iRegs[_Rs_].k < _Imm_);
|
|
} else {
|
|
if (_Imm_ == 0) {
|
|
SRWI(PutHWReg32(_Rt_), GetHWReg32(_Rs_), 31);
|
|
} else {
|
|
int reg;
|
|
CMPWI(GetHWReg32(_Rs_), _Imm_);
|
|
reg = PutHWReg32(_Rt_);
|
|
LI(reg, 1);
|
|
BLT(1);
|
|
LI(reg, 0);
|
|
}
|
|
}
|
|
}
|
|
|
|
static void recSLTIU() {
|
|
// Rt = Rs < Im (unsigned)
|
|
if (!_Rt_) return;
|
|
|
|
if (IsConst(_Rs_)) {
|
|
MapConst(_Rt_, iRegs[_Rs_].k < _ImmU_);
|
|
} else {
|
|
int reg;
|
|
CMPLWI(GetHWReg32(_Rs_), _Imm_);
|
|
reg = PutHWReg32(_Rt_);
|
|
LI(reg, 1);
|
|
BLT(1);
|
|
LI(reg, 0);
|
|
}
|
|
}
|
|
|
|
static void recANDI() {
|
|
// Rt = Rs And Im
|
|
if (!_Rt_) return;
|
|
|
|
if (IsConst(_Rs_)) {
|
|
MapConst(_Rt_, iRegs[_Rs_].k & _ImmU_);
|
|
} else {
|
|
ANDI_(PutHWReg32(_Rt_), GetHWReg32(_Rs_), _ImmU_);
|
|
}
|
|
}
|
|
|
|
static void recORI() {
|
|
// Rt = Rs Or Im
|
|
if (!_Rt_) return;
|
|
|
|
if (IsConst(_Rs_)) {
|
|
MapConst(_Rt_, iRegs[_Rs_].k | _ImmU_);
|
|
} else {
|
|
if (_Imm_ == 0) {
|
|
MapCopy(_Rt_, _Rs_);
|
|
} else {
|
|
ORI(PutHWReg32(_Rt_), GetHWReg32(_Rs_), _ImmU_);
|
|
}
|
|
}
|
|
}
|
|
|
|
static void recXORI() {
|
|
// Rt = Rs Xor Im
|
|
if (!_Rt_) return;
|
|
|
|
if (IsConst(_Rs_)) {
|
|
MapConst(_Rt_, iRegs[_Rs_].k ^ _ImmU_);
|
|
} else {
|
|
XORI(PutHWReg32(_Rt_), GetHWReg32(_Rs_), _ImmU_);
|
|
}
|
|
}
|
|
#endif
|
|
//end of * Arithmetic with immediate operand
|
|
|
|
/*********************************************************
|
|
* Load higher 16 bits of the first word in GPR with imm *
|
|
* Format: OP rt, immediate *
|
|
*********************************************************/
|
|
//REC_FUNC(LUI);
|
|
//#if 0*/
|
|
static void recLUI() {
|
|
// Rt = Imm << 16
|
|
if (!_Rt_) return;
|
|
|
|
MapConst(_Rt_, psxRegs.code << 16);
|
|
}
|
|
//#endif
|
|
//End of Load Higher .....
|
|
|
|
#pragma mark - Register arithmetic -
|
|
/*********************************************************
|
|
* Register arithmetic *
|
|
* Format: OP rd, rs, rt *
|
|
*********************************************************/
|
|
|
|
#if 0
|
|
/*REC_FUNC(ADD);
|
|
REC_FUNC(ADDU);
|
|
REC_FUNC(SUB);
|
|
REC_FUNC(SUBU);
|
|
REC_FUNC(AND);
|
|
REC_FUNC(OR);
|
|
REC_FUNC(XOR);
|
|
REC_FUNC(NOR);
|
|
REC_FUNC(SLT);
|
|
REC_FUNC(SLTU);*/
|
|
#else
|
|
static void recADDU() {
|
|
// Rd = Rs + Rt
|
|
if (!_Rd_) return;
|
|
|
|
if (IsConst(_Rs_) && IsConst(_Rt_)) {
|
|
MapConst(_Rd_, iRegs[_Rs_].k + iRegs[_Rt_].k);
|
|
} else if (IsConst(_Rs_) && !IsMapped(_Rs_)) {
|
|
if ((s32)(s16)iRegs[_Rs_].k == (s32)iRegs[_Rs_].k) {
|
|
ADDI(PutHWReg32(_Rd_), GetHWReg32(_Rt_), (s16)iRegs[_Rs_].k);
|
|
} else if ((iRegs[_Rs_].k & 0xffff) == 0) {
|
|
ADDIS(PutHWReg32(_Rd_), GetHWReg32(_Rt_), iRegs[_Rs_].k>>16);
|
|
} else {
|
|
ADD(PutHWReg32(_Rd_), GetHWReg32(_Rs_), GetHWReg32(_Rt_));
|
|
}
|
|
} else if (IsConst(_Rt_) && !IsMapped(_Rt_)) {
|
|
if ((s32)(s16)iRegs[_Rt_].k == (s32)iRegs[_Rt_].k) {
|
|
ADDI(PutHWReg32(_Rd_), GetHWReg32(_Rs_), (s16)iRegs[_Rt_].k);
|
|
} else if ((iRegs[_Rt_].k & 0xffff) == 0) {
|
|
ADDIS(PutHWReg32(_Rd_), GetHWReg32(_Rs_), iRegs[_Rt_].k>>16);
|
|
} else {
|
|
ADD(PutHWReg32(_Rd_), GetHWReg32(_Rs_), GetHWReg32(_Rt_));
|
|
}
|
|
} else {
|
|
ADD(PutHWReg32(_Rd_), GetHWReg32(_Rs_), GetHWReg32(_Rt_));
|
|
}
|
|
}
|
|
|
|
static void recADD() {
|
|
// Rd = Rs + Rt
|
|
recADDU();
|
|
}
|
|
|
|
static void recSUBU() {
|
|
// Rd = Rs - Rt
|
|
if (!_Rd_) return;
|
|
|
|
if (IsConst(_Rs_) && IsConst(_Rt_)) {
|
|
MapConst(_Rd_, iRegs[_Rs_].k - iRegs[_Rt_].k);
|
|
} else if (IsConst(_Rt_) && !IsMapped(_Rt_)) {
|
|
if ((s32)(s16)(-iRegs[_Rt_].k) == (s32)(-iRegs[_Rt_].k)) {
|
|
ADDI(PutHWReg32(_Rd_), GetHWReg32(_Rs_), -iRegs[_Rt_].k);
|
|
} else if (((-iRegs[_Rt_].k) & 0xffff) == 0) {
|
|
ADDIS(PutHWReg32(_Rd_), GetHWReg32(_Rs_), (-iRegs[_Rt_].k)>>16);
|
|
} else {
|
|
SUB(PutHWReg32(_Rd_), GetHWReg32(_Rs_), GetHWReg32(_Rt_));
|
|
}
|
|
} else {
|
|
SUB(PutHWReg32(_Rd_), GetHWReg32(_Rs_), GetHWReg32(_Rt_));
|
|
}
|
|
}
|
|
|
|
static void recSUB() {
|
|
// Rd = Rs - Rt
|
|
recSUBU();
|
|
}
|
|
|
|
static void recAND() {
|
|
// Rd = Rs And Rt
|
|
if (!_Rd_) return;
|
|
|
|
if (IsConst(_Rs_) && IsConst(_Rt_)) {
|
|
MapConst(_Rd_, iRegs[_Rs_].k & iRegs[_Rt_].k);
|
|
} else if (IsConst(_Rs_) && !IsMapped(_Rs_)) {
|
|
// TODO: implement shifted (ANDIS) versions of these
|
|
if ((iRegs[_Rs_].k & 0xffff) == iRegs[_Rs_].k) {
|
|
ANDI_(PutHWReg32(_Rd_), GetHWReg32(_Rt_), iRegs[_Rs_].k);
|
|
} else {
|
|
AND(PutHWReg32(_Rd_), GetHWReg32(_Rs_), GetHWReg32(_Rt_));
|
|
}
|
|
} else if (IsConst(_Rt_) && !IsMapped(_Rt_)) {
|
|
if ((iRegs[_Rt_].k & 0xffff) == iRegs[_Rt_].k) {
|
|
ANDI_(PutHWReg32(_Rd_), GetHWReg32(_Rs_), iRegs[_Rt_].k);
|
|
} else {
|
|
AND(PutHWReg32(_Rd_), GetHWReg32(_Rs_), GetHWReg32(_Rt_));
|
|
}
|
|
} else {
|
|
AND(PutHWReg32(_Rd_), GetHWReg32(_Rs_), GetHWReg32(_Rt_));
|
|
}
|
|
}
|
|
|
|
static void recOR() {
|
|
// Rd = Rs Or Rt
|
|
if (!_Rd_) return;
|
|
|
|
if (IsConst(_Rs_) && IsConst(_Rt_)) {
|
|
MapConst(_Rd_, iRegs[_Rs_].k | iRegs[_Rt_].k);
|
|
}
|
|
else {
|
|
if (_Rs_ == _Rt_) {
|
|
MapCopy(_Rd_, _Rs_);
|
|
}
|
|
else if (IsConst(_Rs_) && !IsMapped(_Rs_)) {
|
|
if ((iRegs[_Rs_].k & 0xffff) == iRegs[_Rs_].k) {
|
|
ORI(PutHWReg32(_Rd_), GetHWReg32(_Rt_), iRegs[_Rs_].k);
|
|
} else {
|
|
OR(PutHWReg32(_Rd_), GetHWReg32(_Rs_), GetHWReg32(_Rt_));
|
|
}
|
|
}
|
|
else if (IsConst(_Rt_) && !IsMapped(_Rt_)) {
|
|
if ((iRegs[_Rt_].k & 0xffff) == iRegs[_Rt_].k) {
|
|
ORI(PutHWReg32(_Rd_), GetHWReg32(_Rs_), iRegs[_Rt_].k);
|
|
} else {
|
|
OR(PutHWReg32(_Rd_), GetHWReg32(_Rs_), GetHWReg32(_Rt_));
|
|
}
|
|
} else {
|
|
OR(PutHWReg32(_Rd_), GetHWReg32(_Rs_), GetHWReg32(_Rt_));
|
|
}
|
|
}
|
|
}
|
|
|
|
static void recXOR() {
|
|
// Rd = Rs Xor Rt
|
|
if (!_Rd_) return;
|
|
|
|
if (IsConst(_Rs_) && IsConst(_Rt_)) {
|
|
MapConst(_Rd_, iRegs[_Rs_].k ^ iRegs[_Rt_].k);
|
|
} else if (IsConst(_Rs_) && !IsMapped(_Rs_)) {
|
|
if ((iRegs[_Rs_].k & 0xffff) == iRegs[_Rs_].k) {
|
|
XORI(PutHWReg32(_Rd_), GetHWReg32(_Rt_), iRegs[_Rs_].k);
|
|
} else {
|
|
XOR(PutHWReg32(_Rd_), GetHWReg32(_Rs_), GetHWReg32(_Rt_));
|
|
}
|
|
} else if (IsConst(_Rt_) && !IsMapped(_Rt_)) {
|
|
if ((iRegs[_Rt_].k & 0xffff) == iRegs[_Rt_].k) {
|
|
XORI(PutHWReg32(_Rd_), GetHWReg32(_Rs_), iRegs[_Rt_].k);
|
|
} else {
|
|
XOR(PutHWReg32(_Rd_), GetHWReg32(_Rs_), GetHWReg32(_Rt_));
|
|
}
|
|
} else {
|
|
XOR(PutHWReg32(_Rd_), GetHWReg32(_Rs_), GetHWReg32(_Rt_));
|
|
}
|
|
}
|
|
|
|
static void recNOR() {
|
|
// Rd = Rs Nor Rt
|
|
if (!_Rd_) return;
|
|
|
|
if (IsConst(_Rs_) && IsConst(_Rt_)) {
|
|
MapConst(_Rd_, ~(iRegs[_Rs_].k | iRegs[_Rt_].k));
|
|
} /*else if (IsConst(_Rs_) && !IsMapped(_Rs_)) {
|
|
if ((iRegs[_Rs_].k & 0xffff) == iRegs[_Rs_].k) {
|
|
NORI(PutHWReg32(_Rd_), GetHWReg32(_Rt_), iRegs[_Rs_].k);
|
|
} else {
|
|
NOR(PutHWReg32(_Rd_), GetHWReg32(_Rs_), GetHWReg32(_Rt_));
|
|
}
|
|
} else if (IsConst(_Rt_) && !IsMapped(_Rt_)) {
|
|
if ((iRegs[_Rt_].k & 0xffff) == iRegs[_Rt_].k) {
|
|
NORI(PutHWReg32(_Rd_), GetHWReg32(_Rs_), iRegs[_Rt_].k);
|
|
} else {
|
|
NOR(PutHWReg32(_Rd_), GetHWReg32(_Rs_), GetHWReg32(_Rt_));
|
|
}
|
|
} */else {
|
|
NOR(PutHWReg32(_Rd_), GetHWReg32(_Rs_), GetHWReg32(_Rt_));
|
|
}
|
|
}
|
|
|
|
static void recSLT() {
|
|
// Rd = Rs < Rt (signed)
|
|
if (!_Rd_) return;
|
|
|
|
if (IsConst(_Rs_) && IsConst(_Rt_)) {
|
|
MapConst(_Rd_, (s32)iRegs[_Rs_].k < (s32)iRegs[_Rt_].k);
|
|
} else { // TODO: add immidiate cases
|
|
int reg;
|
|
CMPW(GetHWReg32(_Rs_), GetHWReg32(_Rt_));
|
|
reg = PutHWReg32(_Rd_);
|
|
LI(reg, 1);
|
|
BLT(1);
|
|
LI(reg, 0);
|
|
}
|
|
}
|
|
|
|
static void recSLTU() {
|
|
// Rd = Rs < Rt (unsigned)
|
|
if (!_Rd_) return;
|
|
|
|
if (IsConst(_Rs_) && IsConst(_Rt_)) {
|
|
MapConst(_Rd_, iRegs[_Rs_].k < iRegs[_Rt_].k);
|
|
} else { // TODO: add immidiate cases
|
|
SUBFC(PutHWReg32(_Rd_), GetHWReg32(_Rt_), GetHWReg32(_Rs_));
|
|
SUBFE(PutHWReg32(_Rd_), GetHWReg32(_Rd_), GetHWReg32(_Rd_));
|
|
NEG(PutHWReg32(_Rd_), GetHWReg32(_Rd_));
|
|
}
|
|
}
|
|
#endif
|
|
//End of * Register arithmetic
|
|
|
|
#pragma mark - mult/div & Register trap logic -
|
|
/*********************************************************
|
|
* Register mult/div & Register trap logic *
|
|
* Format: OP rs, rt *
|
|
*********************************************************/
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#if 0
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REC_FUNC(MULT);
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REC_FUNC(MULTU);
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REC_FUNC(DIV);
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REC_FUNC(DIVU);
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#else
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int DoShift(u32 k)
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{
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u32 i;
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for (i=0; i<30; i++) {
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if (k == (1ul << i))
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return i;
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}
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return -1;
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}
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//REC_FUNC(MULT);
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// FIXME: doesn't work in GT - wrong way marker
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static void recMULT() {
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// Lo/Hi = Rs * Rt (signed)
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s32 k; int r;
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int usehi, uselo;
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if ((IsConst(_Rs_) && iRegs[_Rs_].k == 0) ||
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(IsConst(_Rt_) && iRegs[_Rt_].k == 0)) {
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MapConst(REG_LO, 0);
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MapConst(REG_HI, 0);
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return;
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}
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if (IsConst(_Rs_) && IsConst(_Rt_)) {
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u64 res = (s64)((s64)(s32)iRegs[_Rs_].k * (s64)(s32)iRegs[_Rt_].k);
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MapConst(REG_LO, (res & 0xffffffff));
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MapConst(REG_HI, ((res >> 32) & 0xffffffff));
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return;
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}
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if (IsConst(_Rs_)) {
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k = (s32)iRegs[_Rs_].k;
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r = _Rt_;
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} else if (IsConst(_Rt_)) {
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k = (s32)iRegs[_Rt_].k;
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r = _Rs_;
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} else {
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r = -1;
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k = 0;
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}
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// FIXME: this should not be needed!!!
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// uselo = isPsxRegUsed(pc, REG_LO);
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// usehi = isPsxRegUsed(pc, REG_HI);
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uselo = 1; //isPsxRegUsed(pc, REG_LO);
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usehi = 1; //isPsxRegUsed(pc, REG_HI);
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if (r != -1) {
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int shift = DoShift(k);
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if (shift != -1) {
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if (uselo) {
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SLWI(PutHWReg32(REG_LO), GetHWReg32(r), shift)
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}
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if (usehi) {
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SRAWI(PutHWReg32(REG_HI), GetHWReg32(r), 31-shift);
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}
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} else {
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//if ((s32)(s16)k == k) {
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// MULLWI(PutHWReg32(REG_LO), GetHWReg32(r), k);
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// MULHWI(PutHWReg32(REG_HI), GetHWReg32(r), k);
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//} else
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{
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if (uselo) {
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MULLW(PutHWReg32(REG_LO), GetHWReg32(_Rs_), GetHWReg32(_Rt_));
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}
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if (usehi) {
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MULHW(PutHWReg32(REG_HI), GetHWReg32(_Rs_), GetHWReg32(_Rt_));
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}
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}
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}
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} else {
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if (uselo) {
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MULLW(PutHWReg32(REG_LO), GetHWReg32(_Rs_), GetHWReg32(_Rt_));
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}
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if (usehi) {
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MULHW(PutHWReg32(REG_HI), GetHWReg32(_Rs_), GetHWReg32(_Rt_));
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}
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}
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}
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static void recMULTU() {
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// Lo/Hi = Rs * Rt (unsigned)
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u32 k; int r;
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int usehi, uselo;
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if ((IsConst(_Rs_) && iRegs[_Rs_].k == 0) ||
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(IsConst(_Rt_) && iRegs[_Rt_].k == 0)) {
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MapConst(REG_LO, 0);
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MapConst(REG_HI, 0);
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return;
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}
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if (IsConst(_Rs_) && IsConst(_Rt_)) {
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u64 res = (u64)((u64)(u32)iRegs[_Rs_].k * (u64)(u32)iRegs[_Rt_].k);
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MapConst(REG_LO, (res & 0xffffffff));
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MapConst(REG_HI, ((res >> 32) & 0xffffffff));
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return;
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}
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if (IsConst(_Rs_)) {
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k = (s32)iRegs[_Rs_].k;
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r = _Rt_;
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} else if (IsConst(_Rt_)) {
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k = (s32)iRegs[_Rt_].k;
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r = _Rs_;
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} else {
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r = -1;
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k = 0;
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}
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uselo = isPsxRegUsed(pc, REG_LO);
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usehi = isPsxRegUsed(pc, REG_HI);
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if (r != -1) {
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int shift = DoShift(k);
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if (shift != -1) {
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if (uselo) {
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SLWI(PutHWReg32(REG_LO), GetHWReg32(r), shift);
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}
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if (usehi) {
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SRWI(PutHWReg32(REG_HI), GetHWReg32(r), 31-shift);
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}
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} else {
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{
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if (uselo) {
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MULLW(PutHWReg32(REG_LO), GetHWReg32(_Rs_), GetHWReg32(_Rt_));
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}
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if (usehi) {
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MULHWU(PutHWReg32(REG_HI), GetHWReg32(_Rs_), GetHWReg32(_Rt_));
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}
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}
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}
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} else {
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if (uselo) {
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MULLW(PutHWReg32(REG_LO), GetHWReg32(_Rs_), GetHWReg32(_Rt_));
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}
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if (usehi) {
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MULHWU(PutHWReg32(REG_HI), GetHWReg32(_Rs_), GetHWReg32(_Rt_));
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}
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}
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}
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static void recDIV() {
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// Lo/Hi = Rs / Rt (signed)
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int usehi;
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if (IsConst(_Rs_) && iRegs[_Rs_].k == 0) {
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MapConst(REG_LO, 0);
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MapConst(REG_HI, 0);
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return;
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}
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if (IsConst(_Rt_) && IsConst(_Rs_)) {
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MapConst(REG_LO, (s32)iRegs[_Rs_].k / (s32)iRegs[_Rt_].k);
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MapConst(REG_HI, (s32)iRegs[_Rs_].k % (s32)iRegs[_Rt_].k);
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return;
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}
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usehi = isPsxRegUsed(pc, REG_HI);
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if (IsConst(_Rt_)) {
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int shift = DoShift(iRegs[_Rt_].k);
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if (shift != -1) {
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SRAWI(PutHWReg32(REG_LO), GetHWReg32(_Rs_), shift);
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ADDZE(PutHWReg32(REG_LO), GetHWReg32(REG_LO));
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if (usehi) {
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RLWINM(PutHWReg32(REG_HI), GetHWReg32(_Rs_), 0, 31-shift, 31);
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}
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} else if (iRegs[_Rt_].k == 3) {
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// http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html
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LIS(PutHWReg32(REG_HI), 0x5555);
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ADDI(PutHWReg32(REG_HI), GetHWReg32(REG_HI), 0x5556);
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MULHW(PutHWReg32(REG_LO), GetHWReg32(REG_HI), GetHWReg32(_Rs_));
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SRWI(PutHWReg32(REG_HI), GetHWReg32(_Rs_), 31);
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ADD(PutHWReg32(REG_LO), GetHWReg32(REG_LO), GetHWReg32(REG_HI));
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if (usehi) {
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MULLI(PutHWReg32(REG_HI), GetHWReg32(REG_LO), 3);
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SUB(PutHWReg32(REG_HI), GetHWReg32(_Rs_), GetHWReg32(REG_HI));
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}
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} else {
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DIVW(PutHWReg32(REG_LO), GetHWReg32(_Rs_), GetHWReg32(_Rt_));
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if (usehi) {
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if ((iRegs[_Rt_].k & 0x7fff) == iRegs[_Rt_].k) {
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MULLI(PutHWReg32(REG_HI), GetHWReg32(REG_LO), iRegs[_Rt_].k);
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} else {
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MULLW(PutHWReg32(REG_HI), GetHWReg32(REG_LO), GetHWReg32(_Rt_));
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}
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SUB(PutHWReg32(REG_HI), GetHWReg32(_Rs_), GetHWReg32(REG_HI));
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}
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}
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} else {
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DIVW(PutHWReg32(REG_LO), GetHWReg32(_Rs_), GetHWReg32(_Rt_));
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if (usehi) {
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MULLW(PutHWReg32(REG_HI), GetHWReg32(REG_LO), GetHWReg32(_Rt_));
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SUB(PutHWReg32(REG_HI), GetHWReg32(_Rs_), GetHWReg32(REG_HI));
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}
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}
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}
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static void recDIVU() {
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// Lo/Hi = Rs / Rt (unsigned)
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int usehi;
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if (IsConst(_Rs_) && iRegs[_Rs_].k == 0) {
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MapConst(REG_LO, 0);
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MapConst(REG_HI, 0);
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return;
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}
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if (IsConst(_Rt_) && IsConst(_Rs_)) {
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MapConst(REG_LO, (u32)iRegs[_Rs_].k / (u32)iRegs[_Rt_].k);
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MapConst(REG_HI, (u32)iRegs[_Rs_].k % (u32)iRegs[_Rt_].k);
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return;
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}
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usehi = isPsxRegUsed(pc, REG_HI);
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if (IsConst(_Rt_)) {
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int shift = DoShift(iRegs[_Rt_].k);
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if (shift != -1) {
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SRWI(PutHWReg32(REG_LO), GetHWReg32(_Rs_), shift);
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if (usehi) {
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RLWINM(PutHWReg32(REG_HI), GetHWReg32(_Rs_), 0, 31-shift, 31);
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}
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} else {
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DIVWU(PutHWReg32(REG_LO), GetHWReg32(_Rs_), GetHWReg32(_Rt_));
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if (usehi) {
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MULLW(PutHWReg32(REG_HI), GetHWReg32(_Rt_), GetHWReg32(REG_LO));
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SUB(PutHWReg32(REG_HI), GetHWReg32(_Rs_), GetHWReg32(REG_HI));
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}
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}
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} else {
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DIVWU(PutHWReg32(REG_LO), GetHWReg32(_Rs_), GetHWReg32(_Rt_));
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if (usehi) {
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MULLW(PutHWReg32(REG_HI), GetHWReg32(_Rt_), GetHWReg32(REG_LO));
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SUB(PutHWReg32(REG_HI), GetHWReg32(_Rs_), GetHWReg32(REG_HI));
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}
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}
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}
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#endif
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//End of * Register mult/div & Register trap logic
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#pragma mark - memory access -
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#if 0
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REC_FUNC(LB);
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REC_FUNC(LBU);
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REC_FUNC(LH);
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REC_FUNC(LHU);
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REC_FUNC(LW);
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REC_FUNC(SB);
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REC_FUNC(SH);
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REC_FUNC(SW);
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REC_FUNC(LWL);
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REC_FUNC(LWR);
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REC_FUNC(SWL);
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REC_FUNC(SWR);
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#else
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static void preMemRead()
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{
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int rs;
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ReserveArgs(1);
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if (_Rs_ != _Rt_) {
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DisposeHWReg(iRegs[_Rt_].reg);
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}
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rs = GetHWReg32(_Rs_);
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if (rs != 3 || _Imm_ != 0) {
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ADDI(PutHWRegSpecial(ARG1), rs, _Imm_);
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}
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if (_Rs_ == _Rt_) {
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DisposeHWReg(iRegs[_Rt_].reg);
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}
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InvalidateCPURegs();
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//FlushAllHWReg();
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}
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static void preMemWrite(int size)
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{
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int rs;
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ReserveArgs(2);
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rs = GetHWReg32(_Rs_);
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if (rs != 3 || _Imm_ != 0) {
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ADDI(PutHWRegSpecial(ARG1), rs, _Imm_);
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}
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if (size == 1) {
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RLWINM(PutHWRegSpecial(ARG2), GetHWReg32(_Rt_), 0, 24, 31);
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//ANDI_(PutHWRegSpecial(ARG2), GetHWReg32(_Rt_), 0xff);
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} else if (size == 2) {
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RLWINM(PutHWRegSpecial(ARG2), GetHWReg32(_Rt_), 0, 16, 31);
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//ANDI_(PutHWRegSpecial(ARG2), GetHWReg32(_Rt_), 0xffff);
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} else {
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MR(PutHWRegSpecial(ARG2), GetHWReg32(_Rt_));
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}
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InvalidateCPURegs();
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//FlushAllHWReg();
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}
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static void recLB() {
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// Rt = mem[Rs + Im] (signed)
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/*if (IsConst(_Rs_)) {
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u32 addr = iRegs[_Rs_].k + _Imm_;
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int t = addr >> 16;
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if ((t & 0xfff0) == 0xbfc0) {
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if (!_Rt_) return;
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// since bios is readonly it won't change
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MapConst(_Rt_, psxRs8(addr));
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return;
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}
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if ((t & 0x1fe0) == 0 && (t & 0x1fff) != 0) {
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if (!_Rt_) return;
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addr = (u32)&psxM[addr & 0x1fffff];
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LIW(PutHWReg32(_Rt_), ((addr>>16)<<16)+(addr&0x8000<<1)); // FIXME: is this correct?
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LBZ(PutHWReg32(_Rt_), addr&0xffff, GetHWReg32(_Rt_));
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EXTSB(PutHWReg32(_Rt_), GetHWReg32(_Rt_));
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return;
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}
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if (t == 0x1f80 && addr < 0x1f801000) {
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if (!_Rt_) return;
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addr = (u32)&psxH[addr & 0xfff];
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LIW(PutHWReg32(_Rt_), ((addr>>16)<<16)+(addr&0x8000<<1)); // FIXME: is this correct?
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LBZ(PutHWReg32(_Rt_), addr&0xffff, GetHWReg32(_Rt_));
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EXTSB(PutHWReg32(_Rt_), GetHWReg32(_Rt_));
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return;
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}
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// SysPrintf("unhandled r8 %x\n", addr);
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}*/
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|
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preMemRead();
|
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CALLFunc((u32)psxMemRead8);
|
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if (_Rt_) {
|
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EXTSB(PutHWReg32(_Rt_), GetHWRegSpecial(RETVAL));
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DisposeHWReg(GetSpecialIndexFromHWRegs(RETVAL));
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}
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}
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|
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static void recLBU() {
|
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// Rt = mem[Rs + Im] (unsigned)
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|
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/*if (IsConst(_Rs_)) {
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u32 addr = iRegs[_Rs_].k + _Imm_;
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int t = addr >> 16;
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if ((t & 0xfff0) == 0xbfc0) {
|
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if (!_Rt_) return;
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// since bios is readonly it won't change
|
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MapConst(_Rt_, psxRu8(addr));
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return;
|
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}
|
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if ((t & 0x1fe0) == 0 && (t & 0x1fff) != 0) {
|
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if (!_Rt_) return;
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|
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addr = (u32)&psxM[addr & 0x1fffff];
|
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LIW(PutHWReg32(_Rt_), ((addr>>16)<<16)+(addr&0x8000<<1)); // FIXME: is this correct?
|
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LBZ(PutHWReg32(_Rt_), addr&0xffff, GetHWReg32(_Rt_));
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return;
|
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}
|
|
if (t == 0x1f80 && addr < 0x1f801000) {
|
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if (!_Rt_) return;
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|
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addr = (u32)&psxH[addr & 0xfff];
|
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LIW(PutHWReg32(_Rt_), ((addr>>16)<<16)+(addr&0x8000<<1)); // FIXME: is this correct?
|
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LBZ(PutHWReg32(_Rt_), addr&0xffff, GetHWReg32(_Rt_));
|
|
return;
|
|
}
|
|
// SysPrintf("unhandled r8 %x\n", addr);
|
|
}*/
|
|
|
|
preMemRead();
|
|
CALLFunc((u32)psxMemRead8);
|
|
|
|
if (_Rt_) {
|
|
SetDstCPUReg(3);
|
|
PutHWReg32(_Rt_);
|
|
}
|
|
}
|
|
|
|
static void recLH() {
|
|
// Rt = mem[Rs + Im] (signed)
|
|
|
|
if (IsConst(_Rs_)) {
|
|
u32 addr = iRegs[_Rs_].k + _Imm_;
|
|
int t = addr >> 16;
|
|
|
|
if ((t & 0xfff0) == 0xbfc0) {
|
|
if (!_Rt_) return;
|
|
// since bios is readonly it won't change
|
|
MapConst(_Rt_, psxRs16(addr));
|
|
return;
|
|
}
|
|
if ((t & 0x1fe0) == 0 && (t & 0x1fff) != 0) {
|
|
if (!_Rt_) return;
|
|
|
|
LIW(PutHWReg32(_Rt_), (u32)&psxM[addr & 0x1fffff]);
|
|
LHBRX(PutHWReg32(_Rt_), 0, GetHWReg32(_Rt_));
|
|
EXTSH(PutHWReg32(_Rt_), GetHWReg32(_Rt_));
|
|
return;
|
|
}
|
|
if (t == 0x1f80 && addr < 0x1f801000) {
|
|
if (!_Rt_) return;
|
|
|
|
LIW(PutHWReg32(_Rt_), (u32)&psxH[addr & 0xfff]);
|
|
LHBRX(PutHWReg32(_Rt_), 0, GetHWReg32(_Rt_));
|
|
EXTSH(PutHWReg32(_Rt_), GetHWReg32(_Rt_));
|
|
return;
|
|
}
|
|
// SysPrintf("unhandled r16 %x\n", addr);
|
|
}
|
|
|
|
preMemRead();
|
|
CALLFunc((u32)psxMemRead16);
|
|
if (_Rt_) {
|
|
EXTSH(PutHWReg32(_Rt_), GetHWRegSpecial(RETVAL));
|
|
DisposeHWReg(GetSpecialIndexFromHWRegs(RETVAL));
|
|
}
|
|
}
|
|
|
|
static void recLHU() {
|
|
// Rt = mem[Rs + Im] (unsigned)
|
|
|
|
if (IsConst(_Rs_)) {
|
|
u32 addr = iRegs[_Rs_].k + _Imm_;
|
|
int t = addr >> 16;
|
|
|
|
if ((t & 0xfff0) == 0xbfc0) {
|
|
if (!_Rt_) return;
|
|
// since bios is readonly it won't change
|
|
MapConst(_Rt_, psxRu16(addr));
|
|
return;
|
|
}
|
|
if ((t & 0x1fe0) == 0 && (t & 0x1fff) != 0) {
|
|
if (!_Rt_) return;
|
|
|
|
LIW(PutHWReg32(_Rt_), (u32)&psxM[addr & 0x1fffff]);
|
|
LHBRX(PutHWReg32(_Rt_), 0, GetHWReg32(_Rt_));
|
|
return;
|
|
}
|
|
if (t == 0x1f80 && addr < 0x1f801000) {
|
|
if (!_Rt_) return;
|
|
|
|
LIW(PutHWReg32(_Rt_), (u32)&psxH[addr & 0xfff]);
|
|
LHBRX(PutHWReg32(_Rt_), 0, GetHWReg32(_Rt_));
|
|
return;
|
|
}
|
|
if (t == 0x1f80) {
|
|
if (addr >= 0x1f801c00 && addr < 0x1f801e00) {
|
|
if (!_Rt_) return;
|
|
|
|
ReserveArgs(1);
|
|
LIW(PutHWRegSpecial(ARG1), addr);
|
|
DisposeHWReg(iRegs[_Rt_].reg);
|
|
InvalidateCPURegs();
|
|
CALLFunc((u32)SPU_readRegister);
|
|
|
|
SetDstCPUReg(3);
|
|
PutHWReg32(_Rt_);
|
|
return;
|
|
}
|
|
switch (addr) {
|
|
case 0x1f801100: case 0x1f801110: case 0x1f801120:
|
|
if (!_Rt_) return;
|
|
|
|
ReserveArgs(1);
|
|
LIW(PutHWRegSpecial(ARG1), (addr >> 4) & 0x3);
|
|
DisposeHWReg(iRegs[_Rt_].reg);
|
|
InvalidateCPURegs();
|
|
CALLFunc((u32)psxRcntRcount);
|
|
|
|
SetDstCPUReg(3);
|
|
PutHWReg32(_Rt_);
|
|
return;
|
|
|
|
case 0x1f801104: case 0x1f801114: case 0x1f801124:
|
|
if (!_Rt_) return;
|
|
|
|
ReserveArgs(1);
|
|
LIW(PutHWRegSpecial(ARG1), (addr >> 4) & 0x3);
|
|
DisposeHWReg(iRegs[_Rt_].reg);
|
|
InvalidateCPURegs();
|
|
CALLFunc((u32)psxRcntRmode);
|
|
|
|
SetDstCPUReg(3);
|
|
PutHWReg32(_Rt_);
|
|
return;
|
|
|
|
case 0x1f801108: case 0x1f801118: case 0x1f801128:
|
|
if (!_Rt_) return;
|
|
|
|
ReserveArgs(1);
|
|
LIW(PutHWRegSpecial(ARG1), (addr >> 4) & 0x3);
|
|
DisposeHWReg(iRegs[_Rt_].reg);
|
|
InvalidateCPURegs();
|
|
CALLFunc((u32)psxRcntRtarget);
|
|
|
|
SetDstCPUReg(3);
|
|
PutHWReg32(_Rt_);
|
|
return;
|
|
}
|
|
}
|
|
// SysPrintf("unhandled r16u %x\n", addr);
|
|
}
|
|
|
|
preMemRead();
|
|
CALLFunc((u32)psxMemRead16);
|
|
if (_Rt_) {
|
|
SetDstCPUReg(3);
|
|
PutHWReg32(_Rt_);
|
|
}
|
|
}
|
|
|
|
static void recLW() {
|
|
// Rt = mem[Rs + Im] (unsigned)
|
|
|
|
if (IsConst(_Rs_)) {
|
|
u32 addr = iRegs[_Rs_].k + _Imm_;
|
|
int t = addr >> 16;
|
|
|
|
if ((t & 0xfff0) == 0xbfc0) {
|
|
if (!_Rt_) return;
|
|
// since bios is readonly it won't change
|
|
MapConst(_Rt_, psxRu32(addr));
|
|
return;
|
|
}
|
|
if ((t & 0x1fe0) == 0 && (t & 0x1fff) != 0) {
|
|
if (!_Rt_) return;
|
|
|
|
LIW(PutHWReg32(_Rt_), (u32)&psxM[addr & 0x1fffff]);
|
|
LWBRX(PutHWReg32(_Rt_), 0, GetHWReg32(_Rt_));
|
|
return;
|
|
}
|
|
if (t == 0x1f80 && addr < 0x1f801000) {
|
|
if (!_Rt_) return;
|
|
|
|
LIW(PutHWReg32(_Rt_), (u32)&psxH[addr & 0xfff]);
|
|
LWBRX(PutHWReg32(_Rt_), 0, GetHWReg32(_Rt_));
|
|
return;
|
|
}
|
|
if (t == 0x1f80) {
|
|
switch (addr) {
|
|
case 0x1f801080: case 0x1f801084: case 0x1f801088:
|
|
case 0x1f801090: case 0x1f801094: case 0x1f801098:
|
|
case 0x1f8010a0: case 0x1f8010a4: case 0x1f8010a8:
|
|
case 0x1f8010b0: case 0x1f8010b4: case 0x1f8010b8:
|
|
case 0x1f8010c0: case 0x1f8010c4: case 0x1f8010c8:
|
|
case 0x1f8010d0: case 0x1f8010d4: case 0x1f8010d8:
|
|
case 0x1f8010e0: case 0x1f8010e4: case 0x1f8010e8:
|
|
case 0x1f801070: case 0x1f801074:
|
|
case 0x1f8010f0: case 0x1f8010f4:
|
|
if (!_Rt_) return;
|
|
|
|
LIW(PutHWReg32(_Rt_), (u32)&psxH[addr & 0xffff]);
|
|
LWBRX(PutHWReg32(_Rt_), 0, GetHWReg32(_Rt_));
|
|
return;
|
|
|
|
case 0x1f801810:
|
|
if (!_Rt_) return;
|
|
|
|
DisposeHWReg(iRegs[_Rt_].reg);
|
|
InvalidateCPURegs();
|
|
CALLFunc((u32)GPU_readData);
|
|
|
|
SetDstCPUReg(3);
|
|
PutHWReg32(_Rt_);
|
|
return;
|
|
|
|
case 0x1f801814:
|
|
if (!_Rt_) return;
|
|
|
|
DisposeHWReg(iRegs[_Rt_].reg);
|
|
InvalidateCPURegs();
|
|
CALLFunc((u32)GPU_readStatus);
|
|
|
|
SetDstCPUReg(3);
|
|
PutHWReg32(_Rt_);
|
|
return;
|
|
}
|
|
}
|
|
// SysPrintf("unhandled r32 %x\n", addr);
|
|
}
|
|
|
|
preMemRead();
|
|
CALLFunc((u32)psxMemRead32);
|
|
if (_Rt_) {
|
|
SetDstCPUReg(3);
|
|
PutHWReg32(_Rt_);
|
|
}
|
|
}
|
|
|
|
REC_FUNC(LWL);
|
|
REC_FUNC(LWR);
|
|
REC_FUNC(SWL);
|
|
REC_FUNC(SWR);
|
|
/*extern u32 LWL_MASK[4];
|
|
extern u32 LWL_SHIFT[4];
|
|
|
|
void iLWLk(u32 shift) {
|
|
if (IsConst(_Rt_)) {
|
|
MOV32ItoR(ECX, iRegs[_Rt_].k);
|
|
} else {
|
|
MOV32MtoR(ECX, (u32)&psxRegs.GPR.r[_Rt_]);
|
|
}
|
|
AND32ItoR(ECX, LWL_MASK[shift]);
|
|
SHL32ItoR(EAX, LWL_SHIFT[shift]);
|
|
OR32RtoR (EAX, ECX);
|
|
}
|
|
|
|
void recLWL() {
|
|
// Rt = Rt Merge mem[Rs + Im]
|
|
|
|
if (IsConst(_Rs_)) {
|
|
u32 addr = iRegs[_Rs_].k + _Imm_;
|
|
int t = addr >> 16;
|
|
|
|
if ((t & 0x1fe0) == 0 && (t & 0x1fff) != 0) {
|
|
MOV32MtoR(EAX, (u32)&psxM[addr & 0x1ffffc]);
|
|
iLWLk(addr & 3);
|
|
|
|
iRegs[_Rt_].state = ST_UNK;
|
|
MOV32RtoM((u32)&psxRegs.GPR.r[_Rt_], EAX);
|
|
return;
|
|
}
|
|
if (t == 0x1f80 && addr < 0x1f801000) {
|
|
MOV32MtoR(EAX, (u32)&psxH[addr & 0xffc]);
|
|
iLWLk(addr & 3);
|
|
|
|
iRegs[_Rt_].state = ST_UNK;
|
|
MOV32RtoM((u32)&psxRegs.GPR.r[_Rt_], EAX);
|
|
return;
|
|
}
|
|
}
|
|
|
|
if (IsConst(_Rs_)) MOV32ItoR(EAX, iRegs[_Rs_].k + _Imm_);
|
|
else {
|
|
MOV32MtoR(EAX, (u32)&psxRegs.GPR.r[_Rs_]);
|
|
if (_Imm_) ADD32ItoR(EAX, _Imm_);
|
|
}
|
|
PUSH32R (EAX);
|
|
AND32ItoR(EAX, ~3);
|
|
PUSH32R (EAX);
|
|
CALLFunc((u32)psxMemRead32);
|
|
|
|
if (_Rt_) {
|
|
ADD32ItoR(ESP, 4);
|
|
POP32R (EDX);
|
|
AND32ItoR(EDX, 0x3); // shift = addr & 3;
|
|
|
|
MOV32ItoR(ECX, (u32)LWL_SHIFT);
|
|
MOV32RmStoR(ECX, ECX, EDX, 2);
|
|
SHL32CLtoR(EAX); // mem(EAX) << LWL_SHIFT[shift]
|
|
|
|
MOV32ItoR(ECX, (u32)LWL_MASK);
|
|
MOV32RmStoR(ECX, ECX, EDX, 2);
|
|
if (IsConst(_Rt_)) {
|
|
MOV32ItoR(EDX, iRegs[_Rt_].k);
|
|
} else {
|
|
MOV32MtoR(EDX, (u32)&psxRegs.GPR.r[_Rt_]);
|
|
}
|
|
AND32RtoR(EDX, ECX); // _rRt_ & LWL_MASK[shift]
|
|
|
|
OR32RtoR(EAX, EDX);
|
|
|
|
iRegs[_Rt_].state = ST_UNK;
|
|
MOV32RtoM((u32)&psxRegs.GPR.r[_Rt_], EAX);
|
|
} else {
|
|
// ADD32ItoR(ESP, 8);
|
|
resp+= 8;
|
|
}
|
|
}
|
|
|
|
static void recLWBlock(int count) {
|
|
u32 *code = PSXM(pc);
|
|
int i, respsave;
|
|
// Rt = mem[Rs + Im] (unsigned)
|
|
|
|
// iFlushRegs(0);
|
|
|
|
if (IsConst(_Rs_)) {
|
|
u32 addr = iRegs[_Rs_].k + _Imm_;
|
|
int t = addr >> 16;
|
|
|
|
if ((t & 0xfff0) == 0xbfc0) {
|
|
// since bios is readonly it won't change
|
|
for (i=0; i<count; i++, code++, addr+=4) {
|
|
if (_fRt_(*code)) {
|
|
MapConst(_fRt_(*code), psxRu32(addr));
|
|
}
|
|
}
|
|
return;
|
|
}
|
|
if ((t & 0x1fe0) == 0 && (t & 0x1fff) != 0) {
|
|
for (i=0; i<count; i++, code++, addr+=4) {
|
|
if (!_fRt_(*code)) return;
|
|
iRegs[_fRt_(*code)].state = ST_UNK;
|
|
|
|
MOV32MtoR(EAX, (u32)&psxM[addr & 0x1fffff]);
|
|
MOV32RtoM((u32)&psxRegs.GPR.r[_fRt_(*code)], EAX);
|
|
}
|
|
return;
|
|
}
|
|
if (t == 0x1f80 && addr < 0x1f801000) {
|
|
for (i=0; i<count; i++, code++, addr+=4) {
|
|
if (!_fRt_(*code)) return;
|
|
iRegs[_fRt_(*code)].state = ST_UNK;
|
|
|
|
MOV32MtoR(EAX, (u32)&psxH[addr & 0xfff]);
|
|
MOV32RtoM((u32)&psxRegs.GPR.r[_fRt_(*code)], EAX);
|
|
}
|
|
return;
|
|
}
|
|
}
|
|
|
|
SysPrintf("recLWBlock %d: %d\n", count, IsConst(_Rs_));
|
|
iPushOfB();
|
|
CALLFunc((u32)psxMemPointer);
|
|
// ADD32ItoR(ESP, 4);
|
|
resp+= 4;
|
|
|
|
respsave = resp; resp = 0;
|
|
TEST32RtoR(EAX, EAX);
|
|
j32Ptr[4] = JZ32(0);
|
|
XOR32RtoR(ECX, ECX);
|
|
for (i=0; i<count; i++, code++) {
|
|
if (_fRt_(*code)) {
|
|
iRegs[_fRt_(*code)].state = ST_UNK;
|
|
|
|
MOV32RmStoR(EDX, EAX, ECX, 2);
|
|
MOV32RtoM((u32)&psxRegs.GPR.r[_fRt_(*code)], EDX);
|
|
}
|
|
if (i != (count-1)) INC32R(ECX);
|
|
}
|
|
j32Ptr[5] = JMP32(0);
|
|
x86SetJ32(j32Ptr[4]);
|
|
for (i=0, code = PSXM(pc); i<count; i++, code++) {
|
|
psxRegs.code = *code;
|
|
recLW();
|
|
}
|
|
ADD32ItoR(ESP, resp);
|
|
x86SetJ32(j32Ptr[5]);
|
|
resp = respsave;
|
|
}
|
|
|
|
extern u32 LWR_MASK[4];
|
|
extern u32 LWR_SHIFT[4];
|
|
|
|
void iLWRk(u32 shift) {
|
|
if (IsConst(_Rt_)) {
|
|
MOV32ItoR(ECX, iRegs[_Rt_].k);
|
|
} else {
|
|
MOV32MtoR(ECX, (u32)&psxRegs.GPR.r[_Rt_]);
|
|
}
|
|
AND32ItoR(ECX, LWR_MASK[shift]);
|
|
SHR32ItoR(EAX, LWR_SHIFT[shift]);
|
|
OR32RtoR (EAX, ECX);
|
|
}
|
|
|
|
void recLWR() {
|
|
// Rt = Rt Merge mem[Rs + Im]
|
|
|
|
if (IsConst(_Rs_)) {
|
|
u32 addr = iRegs[_Rs_].k + _Imm_;
|
|
int t = addr >> 16;
|
|
|
|
if ((t & 0x1fe0) == 0 && (t & 0x1fff) != 0) {
|
|
MOV32MtoR(EAX, (u32)&psxM[addr & 0x1ffffc]);
|
|
iLWRk(addr & 3);
|
|
|
|
iRegs[_Rt_].state = ST_UNK;
|
|
MOV32RtoM((u32)&psxRegs.GPR.r[_Rt_], EAX);
|
|
return;
|
|
}
|
|
if (t == 0x1f80 && addr < 0x1f801000) {
|
|
MOV32MtoR(EAX, (u32)&psxH[addr & 0xffc]);
|
|
iLWRk(addr & 3);
|
|
|
|
iRegs[_Rt_].state = ST_UNK;
|
|
MOV32RtoM((u32)&psxRegs.GPR.r[_Rt_], EAX);
|
|
return;
|
|
}
|
|
}
|
|
|
|
if (IsConst(_Rs_)) MOV32ItoR(EAX, iRegs[_Rs_].k + _Imm_);
|
|
else {
|
|
MOV32MtoR(EAX, (u32)&psxRegs.GPR.r[_Rs_]);
|
|
if (_Imm_) ADD32ItoR(EAX, _Imm_);
|
|
}
|
|
PUSH32R (EAX);
|
|
AND32ItoR(EAX, ~3);
|
|
PUSH32R (EAX);
|
|
CALLFunc((u32)psxMemRead32);
|
|
|
|
if (_Rt_) {
|
|
ADD32ItoR(ESP, 4);
|
|
POP32R (EDX);
|
|
AND32ItoR(EDX, 0x3); // shift = addr & 3;
|
|
|
|
MOV32ItoR(ECX, (u32)LWR_SHIFT);
|
|
MOV32RmStoR(ECX, ECX, EDX, 2);
|
|
SHR32CLtoR(EAX); // mem(EAX) >> LWR_SHIFT[shift]
|
|
|
|
MOV32ItoR(ECX, (u32)LWR_MASK);
|
|
MOV32RmStoR(ECX, ECX, EDX, 2);
|
|
|
|
if (IsConst(_Rt_)) {
|
|
MOV32ItoR(EDX, iRegs[_Rt_].k);
|
|
} else {
|
|
MOV32MtoR(EDX, (u32)&psxRegs.GPR.r[_Rt_]);
|
|
}
|
|
AND32RtoR(EDX, ECX); // _rRt_ & LWR_MASK[shift]
|
|
|
|
OR32RtoR(EAX, EDX);
|
|
|
|
iRegs[_Rt_].state = ST_UNK;
|
|
MOV32RtoM((u32)&psxRegs.GPR.r[_Rt_], EAX);
|
|
} else {
|
|
// ADD32ItoR(ESP, 8);
|
|
resp+= 8;
|
|
}
|
|
}*/
|
|
|
|
static void recSB() {
|
|
// mem[Rs + Im] = Rt
|
|
|
|
/*if (IsConst(_Rs_)) {
|
|
u32 addr = iRegs[_Rs_].k + _Imm_;
|
|
int t = addr >> 16;
|
|
|
|
if ((t & 0x1fe0) == 0 && (t & 0x1fff) != 0) {
|
|
if (IsConst(_Rt_)) {
|
|
MOV8ItoM((u32)&psxM[addr & 0x1fffff], (u8)iRegs[_Rt_].k);
|
|
} else {
|
|
MOV8MtoR(EAX, (u32)&psxRegs.GPR.r[_Rt_]);
|
|
MOV8RtoM((u32)&psxM[addr & 0x1fffff], EAX);
|
|
}
|
|
return;
|
|
}
|
|
if (t == 0x1f80 && addr < 0x1f801000) {
|
|
if (IsConst(_Rt_)) {
|
|
MOV8ItoM((u32)&psxH[addr & 0xfff], (u8)iRegs[_Rt_].k);
|
|
} else {
|
|
MOV8MtoR(EAX, (u32)&psxRegs.GPR.r[_Rt_]);
|
|
MOV8RtoM((u32)&psxH[addr & 0xfff], EAX);
|
|
}
|
|
return;
|
|
}
|
|
// SysPrintf("unhandled w8 %x\n", addr);
|
|
}*/
|
|
|
|
preMemWrite(1);
|
|
CALLFunc((u32)psxMemWrite8);
|
|
}
|
|
|
|
static void recSH() {
|
|
// mem[Rs + Im] = Rt
|
|
|
|
/*if (IsConst(_Rs_)) {
|
|
u32 addr = iRegs[_Rs_].k + _Imm_;
|
|
int t = addr >> 16;
|
|
|
|
if ((t & 0x1fe0) == 0 && (t & 0x1fff) != 0) {
|
|
if (IsConst(_Rt_)) {
|
|
MOV16ItoM((u32)&psxM[addr & 0x1fffff], (u16)iRegs[_Rt_].k);
|
|
} else {
|
|
MOV16MtoR(EAX, (u32)&psxRegs.GPR.r[_Rt_]);
|
|
MOV16RtoM((u32)&psxM[addr & 0x1fffff], EAX);
|
|
}
|
|
return;
|
|
}
|
|
if (t == 0x1f80 && addr < 0x1f801000) {
|
|
if (IsConst(_Rt_)) {
|
|
MOV16ItoM((u32)&psxH[addr & 0xfff], (u16)iRegs[_Rt_].k);
|
|
} else {
|
|
MOV16MtoR(EAX, (u32)&psxRegs.GPR.r[_Rt_]);
|
|
MOV16RtoM((u32)&psxH[addr & 0xfff], EAX);
|
|
}
|
|
return;
|
|
}
|
|
if (t == 0x1f80) {
|
|
if (addr >= 0x1f801c00 && addr < 0x1f801e00) {
|
|
if (IsConst(_Rt_)) {
|
|
PUSH32I(iRegs[_Rt_].k);
|
|
} else {
|
|
PUSH32M((u32)&psxRegs.GPR.r[_Rt_]);
|
|
}
|
|
PUSH32I (addr);
|
|
CALL32M ((u32)&SPU_writeRegister);
|
|
#ifndef __WIN32__
|
|
resp+= 8;
|
|
#endif
|
|
return;
|
|
}
|
|
}
|
|
// SysPrintf("unhandled w16 %x\n", addr);
|
|
}*/
|
|
|
|
preMemWrite(2);
|
|
CALLFunc((u32)psxMemWrite16);
|
|
}
|
|
|
|
static void recSW() {
|
|
// mem[Rs + Im] = Rt
|
|
u32 *b1, *b2;
|
|
#if 0
|
|
if (IsConst(_Rs_)) {
|
|
u32 addr = iRegs[_Rs_].k + _Imm_;
|
|
int t = addr >> 16;
|
|
|
|
if ((t & 0x1fe0) == 0 && (t & 0x1fff) != 0) {
|
|
LIW(0, addr & 0x1fffff);
|
|
STWBRX(GetHWReg32(_Rt_), GetHWRegSpecial(PSXMEM), 0);
|
|
return;
|
|
}
|
|
if (t == 0x1f80 && addr < 0x1f801000) {
|
|
LIW(0, (u32)&psxH[addr & 0xfff]);
|
|
STWBRX(GetHWReg32(_Rt_), 0, 0);
|
|
return;
|
|
}
|
|
if (t == 0x1f80) {
|
|
switch (addr) {
|
|
case 0x1f801080: case 0x1f801084:
|
|
case 0x1f801090: case 0x1f801094:
|
|
case 0x1f8010a0: case 0x1f8010a4:
|
|
case 0x1f8010b0: case 0x1f8010b4:
|
|
case 0x1f8010c0: case 0x1f8010c4:
|
|
case 0x1f8010d0: case 0x1f8010d4:
|
|
case 0x1f8010e0: case 0x1f8010e4:
|
|
case 0x1f801074:
|
|
case 0x1f8010f0:
|
|
LIW(0, (u32)&psxH[addr & 0xffff]);
|
|
STWBRX(GetHWReg32(_Rt_), 0, 0);
|
|
return;
|
|
|
|
/* case 0x1f801810:
|
|
if (IsConst(_Rt_)) {
|
|
PUSH32I(iRegs[_Rt_].k);
|
|
} else {
|
|
PUSH32M((u32)&psxRegs.GPR.r[_Rt_]);
|
|
}
|
|
CALL32M((u32)&GPU_writeData);
|
|
#ifndef __WIN32__
|
|
resp+= 4;
|
|
#endif
|
|
return;
|
|
|
|
case 0x1f801814:
|
|
if (IsConst(_Rt_)) {
|
|
PUSH32I(iRegs[_Rt_].k);
|
|
} else {
|
|
PUSH32M((u32)&psxRegs.GPR.r[_Rt_]);
|
|
}
|
|
CALL32M((u32)&GPU_writeStatus);
|
|
#ifndef __WIN32__
|
|
resp+= 4;
|
|
#endif*/
|
|
}
|
|
}
|
|
// SysPrintf("unhandled w32 %x\n", addr);
|
|
}
|
|
|
|
/* LIS(0, 0x0079 + ((_Imm_ <= 0) ? 1 : 0));
|
|
CMPLW(GetHWReg32(_Rs_), 0);
|
|
BGE_L(b1);
|
|
|
|
//SaveContext();
|
|
ADDI(0, GetHWReg32(_Rs_), _Imm_);
|
|
RLWINM(0, GetHWReg32(_Rs_), 0, 11, 31);
|
|
STWBRX(GetHWReg32(_Rt_), GetHWRegSpecial(PSXMEM), 0);
|
|
B_L(b2);
|
|
|
|
B_DST(b1);*/
|
|
#endif
|
|
preMemWrite(4);
|
|
CALLFunc((u32)psxMemWrite32);
|
|
|
|
//B_DST(b2);
|
|
}
|
|
|
|
/*
|
|
static void recSWBlock(int count) {
|
|
u32 *code;
|
|
int i, respsave;
|
|
// mem[Rs + Im] = Rt
|
|
|
|
// iFlushRegs();
|
|
|
|
if (IsConst(_Rs_)) {
|
|
u32 addr = iRegs[_Rs_].k + _Imm_;
|
|
int t = addr >> 16;
|
|
code = PSXM(pc);
|
|
|
|
if ((t & 0x1fe0) == 0 && (t & 0x1fff) != 0) {
|
|
for (i=0; i<count; i++, code++, addr+=4) {
|
|
if (IsConst(_fRt_(*code))) {
|
|
MOV32ItoM((u32)&psxM[addr & 0x1fffff], iRegs[_fRt_(*code)].k);
|
|
} else {
|
|
MOV32MtoR(EAX, (u32)&psxRegs.GPR.r[_fRt_(*code)]);
|
|
MOV32RtoM((u32)&psxM[addr & 0x1fffff], EAX);
|
|
}
|
|
}
|
|
return;
|
|
}
|
|
if (t == 0x1f80 && addr < 0x1f801000) {
|
|
for (i=0; i<count; i++, code++, addr+=4) {
|
|
if (!_fRt_(*code)) return;
|
|
iRegs[_fRt_(*code)].state = ST_UNK;
|
|
|
|
MOV32MtoR(EAX, (u32)&psxH[addr & 0xfff]);
|
|
MOV32RtoM((u32)&psxRegs.GPR.r[_fRt_(*code)], EAX);
|
|
}
|
|
return;
|
|
}
|
|
}
|
|
|
|
SysPrintf("recSWBlock %d: %d\n", count, IsConst(_Rs_));
|
|
iPushOfB();
|
|
CALLFunc((u32)psxMemPointer);
|
|
// ADD32ItoR(ESP, 4);
|
|
resp+= 4;
|
|
|
|
respsave = resp; resp = 0;
|
|
TEST32RtoR(EAX, EAX);
|
|
j32Ptr[4] = JZ32(0);
|
|
XOR32RtoR(ECX, ECX);
|
|
for (i=0, code = PSXM(pc); i<count; i++, code++) {
|
|
if (IsConst(_fRt_(*code))) {
|
|
MOV32ItoR(EDX, iRegs[_fRt_(*code)].k);
|
|
} else {
|
|
MOV32MtoR(EDX, (u32)&psxRegs.GPR.r[_fRt_(*code)]);
|
|
}
|
|
MOV32RtoRmS(EAX, ECX, 2, EDX);
|
|
if (i != (count-1)) INC32R(ECX);
|
|
}
|
|
j32Ptr[5] = JMP32(0);
|
|
x86SetJ32(j32Ptr[4]);
|
|
for (i=0, code = PSXM(pc); i<count; i++, code++) {
|
|
psxRegs.code = *code;
|
|
recSW();
|
|
}
|
|
ADD32ItoR(ESP, resp);
|
|
x86SetJ32(j32Ptr[5]);
|
|
resp = respsave;
|
|
}
|
|
|
|
extern u32 SWL_MASK[4];
|
|
extern u32 SWL_SHIFT[4];
|
|
|
|
void iSWLk(u32 shift) {
|
|
if (IsConst(_Rt_)) {
|
|
MOV32ItoR(ECX, iRegs[_Rt_].k);
|
|
} else {
|
|
MOV32MtoR(ECX, (u32)&psxRegs.GPR.r[_Rt_]);
|
|
}
|
|
SHR32ItoR(ECX, SWL_SHIFT[shift]);
|
|
AND32ItoR(EAX, SWL_MASK[shift]);
|
|
OR32RtoR (EAX, ECX);
|
|
}
|
|
|
|
void recSWL() {
|
|
// mem[Rs + Im] = Rt Merge mem[Rs + Im]
|
|
|
|
if (IsConst(_Rs_)) {
|
|
u32 addr = iRegs[_Rs_].k + _Imm_;
|
|
int t = addr >> 16;
|
|
|
|
if ((t & 0x1fe0) == 0 && (t & 0x1fff) != 0) {
|
|
MOV32MtoR(EAX, (u32)&psxM[addr & 0x1ffffc]);
|
|
iSWLk(addr & 3);
|
|
MOV32RtoM((u32)&psxM[addr & 0x1ffffc], EAX);
|
|
return;
|
|
}
|
|
if (t == 0x1f80 && addr < 0x1f801000) {
|
|
MOV32MtoR(EAX, (u32)&psxH[addr & 0xffc]);
|
|
iSWLk(addr & 3);
|
|
MOV32RtoM((u32)&psxH[addr & 0xffc], EAX);
|
|
return;
|
|
}
|
|
}
|
|
|
|
if (IsConst(_Rs_)) MOV32ItoR(EAX, iRegs[_Rs_].k + _Imm_);
|
|
else {
|
|
MOV32MtoR(EAX, (u32)&psxRegs.GPR.r[_Rs_]);
|
|
if (_Imm_) ADD32ItoR(EAX, _Imm_);
|
|
}
|
|
PUSH32R (EAX);
|
|
AND32ItoR(EAX, ~3);
|
|
PUSH32R (EAX);
|
|
|
|
CALLFunc((u32)psxMemRead32);
|
|
|
|
ADD32ItoR(ESP, 4);
|
|
POP32R (EDX);
|
|
AND32ItoR(EDX, 0x3); // shift = addr & 3;
|
|
|
|
MOV32ItoR(ECX, (u32)SWL_MASK);
|
|
MOV32RmStoR(ECX, ECX, EDX, 2);
|
|
AND32RtoR(EAX, ECX); // mem & SWL_MASK[shift]
|
|
|
|
MOV32ItoR(ECX, (u32)SWL_SHIFT);
|
|
MOV32RmStoR(ECX, ECX, EDX, 2);
|
|
if (IsConst(_Rt_)) {
|
|
MOV32ItoR(EDX, iRegs[_Rt_].k);
|
|
} else {
|
|
MOV32MtoR(EDX, (u32)&psxRegs.GPR.r[_Rt_]);
|
|
}
|
|
SHR32CLtoR(EDX); // _rRt_ >> SWL_SHIFT[shift]
|
|
|
|
OR32RtoR (EAX, EDX);
|
|
PUSH32R (EAX);
|
|
|
|
if (IsConst(_Rs_)) MOV32ItoR(EAX, iRegs[_Rs_].k + _Imm_);
|
|
else {
|
|
MOV32MtoR(EAX, (u32)&psxRegs.GPR.r[_Rs_]);
|
|
if (_Imm_) ADD32ItoR(EAX, _Imm_);
|
|
}
|
|
AND32ItoR(EAX, ~3);
|
|
PUSH32R (EAX);
|
|
|
|
CALLFunc((u32)psxMemWrite32);
|
|
// ADD32ItoR(ESP, 8);
|
|
resp+= 8;
|
|
}
|
|
|
|
extern u32 SWR_MASK[4];
|
|
extern u32 SWR_SHIFT[4];
|
|
|
|
void iSWRk(u32 shift) {
|
|
if (IsConst(_Rt_)) {
|
|
MOV32ItoR(ECX, iRegs[_Rt_].k);
|
|
} else {
|
|
MOV32MtoR(ECX, (u32)&psxRegs.GPR.r[_Rt_]);
|
|
}
|
|
SHL32ItoR(ECX, SWR_SHIFT[shift]);
|
|
AND32ItoR(EAX, SWR_MASK[shift]);
|
|
OR32RtoR (EAX, ECX);
|
|
}
|
|
|
|
void recSWR() {
|
|
// mem[Rs + Im] = Rt Merge mem[Rs + Im]
|
|
|
|
if (IsConst(_Rs_)) {
|
|
u32 addr = iRegs[_Rs_].k + _Imm_;
|
|
int t = addr >> 16;
|
|
|
|
if ((t & 0x1fe0) == 0 && (t & 0x1fff) != 0) {
|
|
MOV32MtoR(EAX, (u32)&psxM[addr & 0x1ffffc]);
|
|
iSWRk(addr & 3);
|
|
MOV32RtoM((u32)&psxM[addr & 0x1ffffc], EAX);
|
|
return;
|
|
}
|
|
if (t == 0x1f80 && addr < 0x1f801000) {
|
|
MOV32MtoR(EAX, (u32)&psxH[addr & 0xffc]);
|
|
iSWRk(addr & 3);
|
|
MOV32RtoM((u32)&psxH[addr & 0xffc], EAX);
|
|
return;
|
|
}
|
|
}
|
|
|
|
if (IsConst(_Rs_)) MOV32ItoR(EAX, iRegs[_Rs_].k + _Imm_);
|
|
else {
|
|
MOV32MtoR(EAX, (u32)&psxRegs.GPR.r[_Rs_]);
|
|
if (_Imm_) ADD32ItoR(EAX, _Imm_);
|
|
}
|
|
PUSH32R (EAX);
|
|
AND32ItoR(EAX, ~3);
|
|
PUSH32R (EAX);
|
|
|
|
CALLFunc((u32)psxMemRead32);
|
|
|
|
ADD32ItoR(ESP, 4);
|
|
POP32R (EDX);
|
|
AND32ItoR(EDX, 0x3); // shift = addr & 3;
|
|
|
|
MOV32ItoR(ECX, (u32)SWR_MASK);
|
|
MOV32RmStoR(ECX, ECX, EDX, 2);
|
|
AND32RtoR(EAX, ECX); // mem & SWR_MASK[shift]
|
|
|
|
MOV32ItoR(ECX, (u32)SWR_SHIFT);
|
|
MOV32RmStoR(ECX, ECX, EDX, 2);
|
|
if (IsConst(_Rt_)) {
|
|
MOV32ItoR(EDX, iRegs[_Rt_].k);
|
|
} else {
|
|
MOV32MtoR(EDX, (u32)&psxRegs.GPR.r[_Rt_]);
|
|
}
|
|
SHL32CLtoR(EDX); // _rRt_ << SWR_SHIFT[shift]
|
|
|
|
OR32RtoR (EAX, EDX);
|
|
PUSH32R (EAX);
|
|
|
|
if (IsConst(_Rs_)) MOV32ItoR(EAX, iRegs[_Rs_].k + _Imm_);
|
|
else {
|
|
MOV32MtoR(EAX, (u32)&psxRegs.GPR.r[_Rs_]);
|
|
if (_Imm_) ADD32ItoR(EAX, _Imm_);
|
|
}
|
|
AND32ItoR(EAX, ~3);
|
|
PUSH32R (EAX);
|
|
|
|
CALLFunc((u32)psxMemWrite32);
|
|
// ADD32ItoR(ESP, 8);
|
|
resp+= 8;
|
|
}*/
|
|
#endif
|
|
|
|
#if 0
|
|
/*REC_FUNC(SLL);
|
|
REC_FUNC(SRL);
|
|
REC_FUNC(SRA);*/
|
|
#else
|
|
static void recSLL() {
|
|
// Rd = Rt << Sa
|
|
if (!_Rd_) return;
|
|
|
|
if (IsConst(_Rt_)) {
|
|
MapConst(_Rd_, iRegs[_Rt_].k << _Sa_);
|
|
} else {
|
|
SLWI(PutHWReg32(_Rd_), GetHWReg32(_Rt_), _Sa_);
|
|
}
|
|
}
|
|
|
|
static void recSRL() {
|
|
// Rd = Rt >> Sa
|
|
if (!_Rd_) return;
|
|
|
|
if (IsConst(_Rt_)) {
|
|
MapConst(_Rd_, iRegs[_Rt_].k >> _Sa_);
|
|
} else {
|
|
SRWI(PutHWReg32(_Rd_), GetHWReg32(_Rt_), _Sa_);
|
|
}
|
|
}
|
|
|
|
static void recSRA() {
|
|
// Rd = Rt >> Sa
|
|
if (!_Rd_) return;
|
|
|
|
if (IsConst(_Rt_)) {
|
|
MapConst(_Rd_, (s32)iRegs[_Rt_].k >> _Sa_);
|
|
} else {
|
|
SRAWI(PutHWReg32(_Rd_), GetHWReg32(_Rt_), _Sa_);
|
|
}
|
|
}
|
|
#endif
|
|
|
|
#pragma mark - shift ops -
|
|
#if 0
|
|
/*REC_FUNC(SLLV);
|
|
REC_FUNC(SRLV);
|
|
REC_FUNC(SRAV);*/
|
|
#else
|
|
static void recSLLV() {
|
|
// Rd = Rt << Rs
|
|
if (!_Rd_) return;
|
|
|
|
if (IsConst(_Rt_) && IsConst(_Rs_)) {
|
|
MapConst(_Rd_, iRegs[_Rt_].k << iRegs[_Rs_].k);
|
|
} else if (IsConst(_Rs_) && !IsMapped(_Rs_)) {
|
|
SLWI(PutHWReg32(_Rd_), GetHWReg32(_Rt_), iRegs[_Rs_].k);
|
|
} else {
|
|
SLW(PutHWReg32(_Rd_), GetHWReg32(_Rt_), GetHWReg32(_Rs_));
|
|
}
|
|
}
|
|
|
|
static void recSRLV() {
|
|
// Rd = Rt >> Rs
|
|
if (!_Rd_) return;
|
|
|
|
if (IsConst(_Rt_) && IsConst(_Rs_)) {
|
|
MapConst(_Rd_, iRegs[_Rt_].k >> iRegs[_Rs_].k);
|
|
} else if (IsConst(_Rs_) && !IsMapped(_Rs_)) {
|
|
SRWI(PutHWReg32(_Rd_), GetHWReg32(_Rt_), iRegs[_Rs_].k);
|
|
} else {
|
|
SRW(PutHWReg32(_Rd_), GetHWReg32(_Rt_), GetHWReg32(_Rs_));
|
|
}
|
|
}
|
|
|
|
static void recSRAV() {
|
|
// Rd = Rt >> Rs
|
|
if (!_Rd_) return;
|
|
|
|
if (IsConst(_Rt_) && IsConst(_Rs_)) {
|
|
MapConst(_Rd_, (s32)iRegs[_Rt_].k >> iRegs[_Rs_].k);
|
|
} else if (IsConst(_Rs_) && !IsMapped(_Rs_)) {
|
|
SRAWI(PutHWReg32(_Rd_), GetHWReg32(_Rt_), iRegs[_Rs_].k);
|
|
} else {
|
|
SRAW(PutHWReg32(_Rd_), GetHWReg32(_Rt_), GetHWReg32(_Rs_));
|
|
}
|
|
}
|
|
#endif
|
|
|
|
//REC_SYS(SYSCALL);
|
|
//REC_SYS(BREAK);
|
|
|
|
//#if 0*/
|
|
/*int dump;*/
|
|
static void recSYSCALL() {
|
|
// dump=1;
|
|
iFlushRegs(0);
|
|
|
|
ReserveArgs(2);
|
|
LIW(PutHWRegSpecial(PSXPC), pc - 4);
|
|
LIW(PutHWRegSpecial(ARG1), 0x20);
|
|
LIW(PutHWRegSpecial(ARG2), (branch == 1 ? 1 : 0));
|
|
FlushAllHWReg();
|
|
CALLFunc ((u32)psxException);
|
|
|
|
branch = 2;
|
|
iRet();
|
|
}
|
|
|
|
static void recBREAK() {
|
|
}
|
|
//#endif
|
|
|
|
#if 0
|
|
/*REC_FUNC(MFHI);
|
|
REC_FUNC(MTHI);
|
|
REC_FUNC(MFLO);
|
|
REC_FUNC(MTLO);*/
|
|
#else
|
|
static void recMFHI() {
|
|
// Rd = Hi
|
|
if (!_Rd_) return;
|
|
|
|
if (IsConst(REG_HI)) {
|
|
MapConst(_Rd_, iRegs[REG_HI].k);
|
|
} else {
|
|
MapCopy(_Rd_, REG_HI);
|
|
}
|
|
}
|
|
|
|
static void recMTHI() {
|
|
// Hi = Rs
|
|
|
|
if (IsConst(_Rs_)) {
|
|
MapConst(REG_HI, iRegs[_Rs_].k);
|
|
} else {
|
|
MapCopy(REG_HI, _Rs_);
|
|
}
|
|
}
|
|
|
|
static void recMFLO() {
|
|
// Rd = Lo
|
|
if (!_Rd_) return;
|
|
|
|
if (IsConst(REG_LO)) {
|
|
MapConst(_Rd_, iRegs[REG_LO].k);
|
|
} else {
|
|
MapCopy(_Rd_, REG_LO);
|
|
}
|
|
}
|
|
|
|
static void recMTLO() {
|
|
// Lo = Rs
|
|
|
|
if (IsConst(_Rs_)) {
|
|
MapConst(REG_LO, iRegs[_Rs_].k);
|
|
} else {
|
|
MapCopy(REG_LO, _Rs_);
|
|
}
|
|
}
|
|
#endif
|
|
|
|
#pragma mark - branch ops -
|
|
#if 0
|
|
/*REC_BRANCH(J);
|
|
REC_BRANCH(JR);
|
|
REC_BRANCH(JAL);
|
|
REC_BRANCH(JALR);
|
|
REC_BRANCH(BLTZ);
|
|
REC_BRANCH(BGTZ);
|
|
REC_BRANCH(BLTZAL);
|
|
REC_BRANCH(BGEZAL);
|
|
REC_BRANCH(BNE);
|
|
REC_BRANCH(BEQ);
|
|
REC_BRANCH(BLEZ);
|
|
REC_BRANCH(BGEZ);*/
|
|
#else
|
|
static void recBLTZ() {
|
|
// Branch if Rs < 0
|
|
u32 bpc = _Imm_ * 4 + pc;
|
|
u32 *b;
|
|
|
|
if (IsConst(_Rs_)) {
|
|
if ((s32)iRegs[_Rs_].k < 0) {
|
|
iJump(bpc); return;
|
|
} else {
|
|
iJump(pc+4); return;
|
|
}
|
|
}
|
|
|
|
CMPWI(GetHWReg32(_Rs_), 0);
|
|
BLT_L(b);
|
|
|
|
iBranch(pc+4, 1);
|
|
|
|
B_DST(b);
|
|
|
|
iBranch(bpc, 0);
|
|
pc+=4;
|
|
}
|
|
|
|
static void recBGTZ() {
|
|
// Branch if Rs > 0
|
|
u32 bpc = _Imm_ * 4 + pc;
|
|
u32 *b;
|
|
|
|
if (IsConst(_Rs_)) {
|
|
if ((s32)iRegs[_Rs_].k > 0) {
|
|
iJump(bpc); return;
|
|
} else {
|
|
iJump(pc+4); return;
|
|
}
|
|
}
|
|
|
|
CMPWI(GetHWReg32(_Rs_), 0);
|
|
BGT_L(b);
|
|
|
|
iBranch(pc+4, 1);
|
|
|
|
B_DST(b);
|
|
|
|
iBranch(bpc, 0);
|
|
pc+=4;
|
|
}
|
|
|
|
static void recBLTZAL() {
|
|
// Branch if Rs < 0
|
|
u32 bpc = _Imm_ * 4 + pc;
|
|
u32 *b;
|
|
|
|
if (IsConst(_Rs_)) {
|
|
if ((s32)iRegs[_Rs_].k < 0) {
|
|
MapConst(31, pc + 4);
|
|
|
|
iJump(bpc); return;
|
|
} else {
|
|
iJump(pc+4); return;
|
|
}
|
|
}
|
|
|
|
CMPWI(GetHWReg32(_Rs_), 0);
|
|
BLT_L(b);
|
|
|
|
iBranch(pc+4, 1);
|
|
|
|
B_DST(b);
|
|
|
|
MapConst(31, pc + 4);
|
|
|
|
iBranch(bpc, 0);
|
|
pc+=4;
|
|
}
|
|
|
|
static void recBGEZAL() {
|
|
// Branch if Rs >= 0
|
|
u32 bpc = _Imm_ * 4 + pc;
|
|
u32 *b;
|
|
|
|
if (IsConst(_Rs_)) {
|
|
if ((s32)iRegs[_Rs_].k >= 0) {
|
|
MapConst(31, pc + 4);
|
|
|
|
iJump(bpc); return;
|
|
} else {
|
|
iJump(pc+4); return;
|
|
}
|
|
}
|
|
|
|
CMPWI(GetHWReg32(_Rs_), 0);
|
|
BGE_L(b);
|
|
|
|
iBranch(pc+4, 1);
|
|
|
|
B_DST(b);
|
|
|
|
MapConst(31, pc + 4);
|
|
|
|
iBranch(bpc, 0);
|
|
pc+=4;
|
|
}
|
|
|
|
static void recJ() {
|
|
// j target
|
|
|
|
iJump(_Target_ * 4 + (pc & 0xf0000000));
|
|
}
|
|
|
|
static void recJAL() {
|
|
// jal target
|
|
MapConst(31, pc + 4);
|
|
|
|
iJump(_Target_ * 4 + (pc & 0xf0000000));
|
|
}
|
|
|
|
static void recJR() {
|
|
// jr Rs
|
|
|
|
if (IsConst(_Rs_)) {
|
|
iJump(iRegs[_Rs_].k);
|
|
//LIW(PutHWRegSpecial(TARGET), iRegs[_Rs_].k);
|
|
} else {
|
|
MR(PutHWRegSpecial(TARGET), GetHWReg32(_Rs_));
|
|
SetBranch();
|
|
}
|
|
}
|
|
|
|
static void recJALR() {
|
|
// jalr Rs
|
|
|
|
if (_Rd_) {
|
|
MapConst(_Rd_, pc + 4);
|
|
}
|
|
|
|
if (IsConst(_Rs_)) {
|
|
iJump(iRegs[_Rs_].k);
|
|
//LIW(PutHWRegSpecial(TARGET), iRegs[_Rs_].k);
|
|
} else {
|
|
MR(PutHWRegSpecial(TARGET), GetHWReg32(_Rs_));
|
|
SetBranch();
|
|
}
|
|
}
|
|
|
|
static void recBEQ() {
|
|
// Branch if Rs == Rt
|
|
u32 bpc = _Imm_ * 4 + pc;
|
|
u32 *b;
|
|
|
|
if (_Rs_ == _Rt_) {
|
|
iJump(bpc);
|
|
}
|
|
else {
|
|
if (IsConst(_Rs_) && IsConst(_Rt_)) {
|
|
if (iRegs[_Rs_].k == iRegs[_Rt_].k) {
|
|
iJump(bpc); return;
|
|
} else {
|
|
iJump(pc+4); return;
|
|
}
|
|
}
|
|
else if (IsConst(_Rs_) && !IsMapped(_Rs_)) {
|
|
if ((iRegs[_Rs_].k & 0xffff) == iRegs[_Rs_].k) {
|
|
CMPLWI(GetHWReg32(_Rt_), iRegs[_Rs_].k);
|
|
}
|
|
else if ((s32)(s16)iRegs[_Rs_].k == (s32)iRegs[_Rs_].k) {
|
|
CMPWI(GetHWReg32(_Rt_), iRegs[_Rs_].k);
|
|
}
|
|
else {
|
|
CMPLW(GetHWReg32(_Rs_), GetHWReg32(_Rt_));
|
|
}
|
|
}
|
|
else if (IsConst(_Rt_) && !IsMapped(_Rt_)) {
|
|
if ((iRegs[_Rt_].k & 0xffff) == iRegs[_Rt_].k) {
|
|
CMPLWI(GetHWReg32(_Rs_), iRegs[_Rt_].k);
|
|
}
|
|
else if ((s32)(s16)iRegs[_Rt_].k == (s32)iRegs[_Rt_].k) {
|
|
CMPWI(GetHWReg32(_Rs_), iRegs[_Rt_].k);
|
|
}
|
|
else {
|
|
CMPLW(GetHWReg32(_Rs_), GetHWReg32(_Rt_));
|
|
}
|
|
}
|
|
else {
|
|
CMPLW(GetHWReg32(_Rs_), GetHWReg32(_Rt_));
|
|
}
|
|
|
|
BEQ_L(b);
|
|
|
|
iBranch(pc+4, 1);
|
|
|
|
B_DST(b);
|
|
|
|
iBranch(bpc, 0);
|
|
pc+=4;
|
|
}
|
|
}
|
|
|
|
static void recBNE() {
|
|
// Branch if Rs != Rt
|
|
u32 bpc = _Imm_ * 4 + pc;
|
|
u32 *b;
|
|
|
|
if (_Rs_ == _Rt_) {
|
|
iJump(pc+4);
|
|
}
|
|
else {
|
|
if (IsConst(_Rs_) && IsConst(_Rt_)) {
|
|
if (iRegs[_Rs_].k != iRegs[_Rt_].k) {
|
|
iJump(bpc); return;
|
|
} else {
|
|
iJump(pc+4); return;
|
|
}
|
|
}
|
|
else if (IsConst(_Rs_) && !IsMapped(_Rs_)) {
|
|
if ((iRegs[_Rs_].k & 0xffff) == iRegs[_Rs_].k) {
|
|
CMPLWI(GetHWReg32(_Rt_), iRegs[_Rs_].k);
|
|
}
|
|
else if ((s32)(s16)iRegs[_Rs_].k == (s32)iRegs[_Rs_].k) {
|
|
CMPWI(GetHWReg32(_Rt_), iRegs[_Rs_].k);
|
|
}
|
|
else {
|
|
CMPLW(GetHWReg32(_Rs_), GetHWReg32(_Rt_));
|
|
}
|
|
}
|
|
else if (IsConst(_Rt_) && !IsMapped(_Rt_)) {
|
|
if ((iRegs[_Rt_].k & 0xffff) == iRegs[_Rt_].k) {
|
|
CMPLWI(GetHWReg32(_Rs_), iRegs[_Rt_].k);
|
|
}
|
|
else if ((s32)(s16)iRegs[_Rt_].k == (s32)iRegs[_Rt_].k) {
|
|
CMPWI(GetHWReg32(_Rs_), iRegs[_Rt_].k);
|
|
}
|
|
else {
|
|
CMPLW(GetHWReg32(_Rs_), GetHWReg32(_Rt_));
|
|
}
|
|
}
|
|
else {
|
|
CMPLW(GetHWReg32(_Rs_), GetHWReg32(_Rt_));
|
|
}
|
|
|
|
BNE_L(b);
|
|
|
|
iBranch(pc+4, 1);
|
|
|
|
B_DST(b);
|
|
|
|
iBranch(bpc, 0);
|
|
pc+=4;
|
|
}
|
|
}
|
|
|
|
static void recBLEZ() {
|
|
// Branch if Rs <= 0
|
|
u32 bpc = _Imm_ * 4 + pc;
|
|
u32 *b;
|
|
|
|
if (IsConst(_Rs_)) {
|
|
if ((s32)iRegs[_Rs_].k <= 0) {
|
|
iJump(bpc); return;
|
|
} else {
|
|
iJump(pc+4); return;
|
|
}
|
|
}
|
|
|
|
CMPWI(GetHWReg32(_Rs_), 0);
|
|
BLE_L(b);
|
|
|
|
iBranch(pc+4, 1);
|
|
|
|
B_DST(b);
|
|
|
|
iBranch(bpc, 0);
|
|
pc+=4;
|
|
}
|
|
|
|
static void recBGEZ() {
|
|
// Branch if Rs >= 0
|
|
u32 bpc = _Imm_ * 4 + pc;
|
|
u32 *b;
|
|
|
|
if (IsConst(_Rs_)) {
|
|
if ((s32)iRegs[_Rs_].k >= 0) {
|
|
iJump(bpc); return;
|
|
} else {
|
|
iJump(pc+4); return;
|
|
}
|
|
}
|
|
|
|
CMPWI(GetHWReg32(_Rs_), 0);
|
|
BGE_L(b);
|
|
|
|
iBranch(pc+4, 1);
|
|
|
|
B_DST(b);
|
|
|
|
iBranch(bpc, 0);
|
|
pc+=4;
|
|
}
|
|
#endif
|
|
|
|
#if 1
|
|
//REC_FUNC(MFC0);
|
|
//REC_SYS(MTC0);
|
|
//REC_FUNC(CFC0);
|
|
//REC_SYS(CTC0);
|
|
REC_FUNC(RFE);
|
|
//#else
|
|
static void recMFC0() {
|
|
// Rt = Cop0->Rd
|
|
if (!_Rt_) return;
|
|
|
|
LWZ(PutHWReg32(_Rt_), OFFSET(&psxRegs, &psxRegs.CP0.r[_Rd_]), GetHWRegSpecial(PSXREGS));
|
|
}
|
|
|
|
static void recCFC0() {
|
|
// Rt = Cop0->Rd
|
|
|
|
recMFC0();
|
|
}
|
|
|
|
static void recMTC0() {
|
|
// Cop0->Rd = Rt
|
|
|
|
/*if (IsConst(_Rt_)) {
|
|
switch (_Rd_) {
|
|
case 12:
|
|
MOV32ItoM((u32)&psxRegs.CP0.r[_Rd_], iRegs[_Rt_].k);
|
|
break;
|
|
case 13:
|
|
MOV32ItoM((u32)&psxRegs.CP0.r[_Rd_], iRegs[_Rt_].k & ~(0xfc00));
|
|
break;
|
|
default:
|
|
MOV32ItoM((u32)&psxRegs.CP0.r[_Rd_], iRegs[_Rt_].k);
|
|
break;
|
|
}
|
|
} else*/ {
|
|
switch (_Rd_) {
|
|
case 13:
|
|
RLWINM(0,GetHWReg32(_Rt_),0,22,15); // & ~(0xfc00)
|
|
STW(0, OFFSET(&psxRegs, &psxRegs.CP0.r[_Rd_]), GetHWRegSpecial(PSXREGS));
|
|
break;
|
|
default:
|
|
STW(GetHWReg32(_Rt_), OFFSET(&psxRegs, &psxRegs.CP0.r[_Rd_]), GetHWRegSpecial(PSXREGS));
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (_Rd_ == 12 || _Rd_ == 13) {
|
|
iFlushRegs(0);
|
|
LIW(PutHWRegSpecial(PSXPC), (u32)pc);
|
|
FlushAllHWReg();
|
|
CALLFunc((u32)psxTestSWInts);
|
|
if(_Rd_ == 12) {
|
|
LWZ(0, OFFSET(&psxRegs, &psxRegs.interrupt), GetHWRegSpecial(PSXREGS));
|
|
ORIS(0, 0, 0x8000);
|
|
STW(0, OFFSET(&psxRegs, &psxRegs.interrupt), GetHWRegSpecial(PSXREGS));
|
|
}
|
|
branch = 2;
|
|
iRet();
|
|
}
|
|
}
|
|
|
|
static void recCTC0() {
|
|
// Cop0->Rd = Rt
|
|
|
|
recMTC0();
|
|
}
|
|
#else
|
|
static void recRFE() {
|
|
// TODO: implement multiple temp registers or cop0 registers
|
|
RLWINM(t1,Status,0,0,27);
|
|
RLWINM(Status,Status,30,28,31);
|
|
OR(Status,t1,Status);
|
|
|
|
MOV32MtoR(EAX, (u32)&psxRegs.CP0.n.Status);
|
|
MOV32RtoR(ECX, EAX);
|
|
AND32ItoR(EAX, 0xfffffff0);
|
|
AND32ItoR(ECX, 0x3c);
|
|
SHR32ItoR(ECX, 2);
|
|
OR32RtoR (EAX, ECX);
|
|
MOV32RtoM((u32)&psxRegs.CP0.n.Status, EAX);
|
|
CALLFunc((u32)psxExceptionTest);
|
|
}
|
|
#endif
|
|
|
|
#if 0
|
|
#define CP2_FUNC(f) \
|
|
void gte##f(); \
|
|
static void rec##f() { \
|
|
iFlushRegs(0); \
|
|
LIW(0, (u32)psxRegs.code); \
|
|
STW(0, OFFSET(&psxRegs, &psxRegs.code), GetHWRegSpecial(PSXREGS)); \
|
|
FlushAllHWReg(); \
|
|
CALLFunc ((u32)gte##f); \
|
|
}
|
|
CP2_FUNC(LWC2);
|
|
CP2_FUNC(SWC2);
|
|
|
|
#else
|
|
#include "pGte.h"
|
|
#endif
|
|
//
|
|
|
|
static void recHLE() {
|
|
iFlushRegs(0);
|
|
FlushAllHWReg();
|
|
|
|
if ((psxRegs.code & 0x3ffffff) == (psxRegs.code & 0x7)) {
|
|
CALLFunc((u32)psxHLEt[psxRegs.code & 0x7]);
|
|
} else {
|
|
// somebody else must have written to current opcode for this to happen!!!!
|
|
CALLFunc((u32)psxHLEt[0]); // call dummy function
|
|
}
|
|
|
|
count = (idlecyclecount + (pc - pcold) / 4 + 20) * BIAS;
|
|
ADDI(PutHWRegSpecial(CYCLECOUNT), GetHWRegSpecial(CYCLECOUNT), count);
|
|
FlushAllHWReg();
|
|
CALLFunc((u32)psxBranchTest);
|
|
Return();
|
|
|
|
branch = 2;
|
|
}
|
|
|
|
//
|
|
|
|
static void (*recBSC[64])() = {
|
|
recSPECIAL, recREGIMM, recJ , recJAL , recBEQ , recBNE , recBLEZ, recBGTZ,
|
|
recADDI , recADDIU , recSLTI, recSLTIU, recANDI, recORI , recXORI, recLUI ,
|
|
recCOP0 , recNULL , recCOP2, recNULL , recNULL, recNULL, recNULL, recNULL,
|
|
recNULL , recNULL , recNULL, recNULL , recNULL, recNULL, recNULL, recNULL,
|
|
recLB , recLH , recLWL , recLW , recLBU , recLHU , recLWR , recNULL,
|
|
recSB , recSH , recSWL , recSW , recNULL, recNULL, recSWR , recNULL,
|
|
recNULL , recNULL , recLWC2, recNULL , recNULL, recNULL, recNULL, recNULL,
|
|
recNULL , recNULL , recSWC2, recHLE , recNULL, recNULL, recNULL, recNULL
|
|
};
|
|
|
|
static void (*recSPC[64])() = {
|
|
recSLL , recNULL, recSRL , recSRA , recSLLV , recNULL , recSRLV, recSRAV,
|
|
recJR , recJALR, recNULL, recNULL, recSYSCALL, recBREAK, recNULL, recNULL,
|
|
recMFHI, recMTHI, recMFLO, recMTLO, recNULL , recNULL , recNULL, recNULL,
|
|
recMULT, recMULTU, recDIV, recDIVU, recNULL , recNULL , recNULL, recNULL,
|
|
recADD , recADDU, recSUB , recSUBU, recAND , recOR , recXOR , recNOR ,
|
|
recNULL, recNULL, recSLT , recSLTU, recNULL , recNULL , recNULL, recNULL,
|
|
recNULL, recNULL, recNULL, recNULL, recNULL , recNULL , recNULL, recNULL,
|
|
recNULL, recNULL, recNULL, recNULL, recNULL , recNULL , recNULL, recNULL
|
|
};
|
|
|
|
static void (*recREG[32])() = {
|
|
recBLTZ , recBGEZ , recNULL, recNULL, recNULL, recNULL, recNULL, recNULL,
|
|
recNULL , recNULL , recNULL, recNULL, recNULL, recNULL, recNULL, recNULL,
|
|
recBLTZAL, recBGEZAL, recNULL, recNULL, recNULL, recNULL, recNULL, recNULL,
|
|
recNULL , recNULL , recNULL, recNULL, recNULL, recNULL, recNULL, recNULL
|
|
};
|
|
|
|
static void (*recCP0[32])() = {
|
|
recMFC0, recNULL, recCFC0, recNULL, recMTC0, recNULL, recCTC0, recNULL,
|
|
recNULL, recNULL, recNULL, recNULL, recNULL, recNULL, recNULL, recNULL,
|
|
recRFE , recNULL, recNULL, recNULL, recNULL, recNULL, recNULL, recNULL,
|
|
recNULL, recNULL, recNULL, recNULL, recNULL, recNULL, recNULL, recNULL
|
|
};
|
|
|
|
static void (*recCP2[64])() = {
|
|
recBASIC, recRTPS , recNULL , recNULL, recNULL, recNULL , recNCLIP, recNULL, // 00
|
|
recNULL , recNULL , recNULL , recNULL, recOP , recNULL , recNULL , recNULL, // 08
|
|
recDPCS , recINTPL, recMVMVA, recNCDS, recCDP , recNULL , recNCDT , recNULL, // 10
|
|
recNULL , recNULL , recNULL , recNCCS, recCC , recNULL , recNCS , recNULL, // 18
|
|
recNCT , recNULL , recNULL , recNULL, recNULL, recNULL , recNULL , recNULL, // 20
|
|
recSQR , recDCPL , recDPCT , recNULL, recNULL, recAVSZ3, recAVSZ4, recNULL, // 28
|
|
recRTPT , recNULL , recNULL , recNULL, recNULL, recNULL , recNULL , recNULL, // 30
|
|
recNULL , recNULL , recNULL , recNULL, recNULL, recGPF , recGPL , recNCCT // 38
|
|
};
|
|
|
|
static void (*recCP2BSC[32])() = {
|
|
recMFC2, recNULL, recCFC2, recNULL, recMTC2, recNULL, recCTC2, recNULL,
|
|
recNULL, recNULL, recNULL, recNULL, recNULL, recNULL, recNULL, recNULL,
|
|
recNULL, recNULL, recNULL, recNULL, recNULL, recNULL, recNULL, recNULL,
|
|
recNULL, recNULL, recNULL, recNULL, recNULL, recNULL, recNULL, recNULL
|
|
};
|
|
|
|
static void recRecompile() {
|
|
//static int recCount = 0;
|
|
char *p;
|
|
u32 *ptr;
|
|
int i;
|
|
|
|
cop2readypc = 0;
|
|
idlecyclecount = 0;
|
|
|
|
// initialize state variables
|
|
UniqueRegAlloc = 1;
|
|
HWRegUseCount = 0;
|
|
DstCPUReg = -1;
|
|
memset(HWRegisters, 0, sizeof(HWRegisters));
|
|
for (i=0; i<NUM_HW_REGISTERS; i++)
|
|
HWRegisters[i].code = cpuHWRegisters[NUM_HW_REGISTERS-i-1];
|
|
|
|
// reserve the special psxReg register
|
|
HWRegisters[0].usage = HWUSAGE_SPECIAL | HWUSAGE_RESERVED | HWUSAGE_HARDWIRED;
|
|
HWRegisters[0].private = PSXREGS;
|
|
HWRegisters[0].k = (u32)&psxRegs;
|
|
|
|
HWRegisters[1].usage = HWUSAGE_SPECIAL | HWUSAGE_RESERVED | HWUSAGE_HARDWIRED;
|
|
HWRegisters[1].private = PSXMEM;
|
|
HWRegisters[1].k = (u32)&psxM;
|
|
|
|
// reserve the special psxRegs.cycle register
|
|
//HWRegisters[1].usage = HWUSAGE_SPECIAL | HWUSAGE_RESERVED | HWUSAGE_HARDWIRED;
|
|
//HWRegisters[1].private = CYCLECOUNT;
|
|
|
|
//memset(iRegs, 0, sizeof(iRegs));
|
|
for (i=0; i<NUM_REGISTERS; i++) {
|
|
iRegs[i].state = ST_UNK;
|
|
iRegs[i].reg = -1;
|
|
}
|
|
iRegs[0].k = 0;
|
|
iRegs[0].state = ST_CONST;
|
|
|
|
/* if ppcPtr reached the mem limit reset whole mem */
|
|
if (((u32)ppcPtr - (u32)recMem) >= (RECMEM_SIZE - 0x10000))
|
|
recReset();
|
|
|
|
ppcAlign(/*32*/4);
|
|
ptr = ppcPtr;
|
|
|
|
// give us write access
|
|
//mprotect(recMem, RECMEM_SIZE, PROT_EXEC|PROT_READ|PROT_WRITE);
|
|
|
|
// tell the LUT where to find us
|
|
PC_REC32(psxRegs.pc) = (u32)ppcPtr;
|
|
|
|
pcold = pc = psxRegs.pc;
|
|
|
|
//SysPrintf("RecCount: %i\n", recCount++);
|
|
|
|
for (count=0; count<500;) {
|
|
p = (char *)PSXM(pc);
|
|
if (p == NULL) recError();
|
|
psxRegs.code = SWAP32(*(u32 *)p);
|
|
/*
|
|
if ((psxRegs.code >> 26) == 0x23) { // LW
|
|
int i;
|
|
u32 code;
|
|
|
|
for (i=1;; i++) {
|
|
p = (char *)PSXM(pc+i*4);
|
|
if (p == NULL) recError();
|
|
code = *(u32 *)p;
|
|
|
|
if ((code >> 26) != 0x23 ||
|
|
_fRs_(code) != _Rs_ ||
|
|
_fImm_(code) != (_Imm_+i*4))
|
|
break;
|
|
}
|
|
if (i > 1) {
|
|
recLWBlock(i);
|
|
pc = pc + i*4; continue;
|
|
}
|
|
}
|
|
|
|
if ((psxRegs.code >> 26) == 0x2b) { // SW
|
|
int i;
|
|
u32 code;
|
|
|
|
for (i=1;; i++) {
|
|
p = (char *)PSXM(pc+i*4);
|
|
if (p == NULL) recError();
|
|
code = *(u32 *)p;
|
|
|
|
if ((code >> 26) != 0x2b ||
|
|
_fRs_(code) != _Rs_ ||
|
|
_fImm_(code) != (_Imm_+i*4))
|
|
break;
|
|
}
|
|
if (i > 1) {
|
|
recSWBlock(i);
|
|
pc = pc + i*4; continue;
|
|
}
|
|
}*/
|
|
|
|
pc+=4; count++;
|
|
// iFlushRegs(0); // test
|
|
recBSC[psxRegs.code>>26]();
|
|
|
|
if (branch) {
|
|
branch = 0;
|
|
//if (dump) iDumpBlock(ptr);
|
|
goto done;
|
|
}
|
|
}
|
|
|
|
iFlushRegs(pc);
|
|
|
|
LIW(PutHWRegSpecial(PSXPC), pc);
|
|
|
|
iRet();
|
|
|
|
done:;
|
|
#if 0
|
|
MakeDataExecutable(ptr, ((u8*)ppcPtr)-((u8*)ptr));
|
|
#else
|
|
u32 a = (u32)(u8*)ptr;
|
|
while(a < (u32)(u8*)ppcPtr) {
|
|
__asm__ __volatile__("icbi 0,%0" : : "r" (a));
|
|
__asm__ __volatile__("dcbst 0,%0" : : "r" (a));
|
|
a += 4;
|
|
}
|
|
__asm__ __volatile__("sync");
|
|
__asm__ __volatile__("isync");
|
|
#endif
|
|
|
|
#if 1
|
|
sprintf((char *)ppcPtr, "PC=%08x", pcold);
|
|
ppcPtr += strlen((char *)ppcPtr);
|
|
#endif
|
|
|
|
//mprotect(recMem, RECMEM_SIZE, PROT_EXEC|PROT_READ/*|PROT_WRITE*/);
|
|
}
|
|
|
|
|
|
R3000Acpu psxRec = {
|
|
recInit,
|
|
recReset,
|
|
recExecute,
|
|
recExecuteBlock,
|
|
recClear,
|
|
recShutdown
|
|
};
|
|
|
|
#endif
|