254 lines
4.7 KiB
C
254 lines
4.7 KiB
C
// stop compiling if NORECBUILD build (only for Visual Studio)
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#ifdef __x86_64__
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#if !(defined(_MSC_VER) && defined(PCSX2_NORECBUILD))
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#include <stdio.h>
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#include <string.h>
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#include "ix86-64.h"
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/********************/
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/* FPU instructions */
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/********************/
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/* fild m32 to fpu reg stack */
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void FILD32( uptr from )
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{
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MEMADDR_OP(0, VAROP1(0xDB), false, 0, from, 0);
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}
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/* fistp m32 from fpu reg stack */
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void FISTP32( uptr from )
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{
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MEMADDR_OP(0, VAROP1(0xDB), false, 3, from, 0);
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}
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/* fld m32 to fpu reg stack */
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void FLD32( uptr from )
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{
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MEMADDR_OP(0, VAROP1(0xD9), false, 0, from, 0);
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}
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// fld st(i)
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void FLD(int st) { write16(0xc0d9+(st<<8)); }
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void FLD1() { write16(0xe8d9); }
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void FLDL2E() { write16(0xead9); }
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/* fst m32 from fpu reg stack */
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void FST32( uptr to )
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{
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MEMADDR_OP(0, VAROP1(0xD9), false, 2, to, 0);
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}
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/* fstp m32 from fpu reg stack */
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void FSTP32( uptr to )
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{
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MEMADDR_OP(0, VAROP1(0xD9), false, 3, to, 0);
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}
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// fstp st(i)
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void FSTP(int st) { write16(0xd8dd+(st<<8)); }
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/* fldcw fpu control word from m16 */
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void FLDCW( uptr from )
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{
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MEMADDR_OP(0, VAROP1(0xD9), false, 5, from, 0);
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}
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/* fnstcw fpu control word to m16 */
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void FNSTCW( uptr to )
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{
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MEMADDR_OP(0, VAROP1(0xD9), false, 7, to, 0);
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}
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void FNSTSWtoAX( void )
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{
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write16( 0xE0DF );
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}
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void FXAM()
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{
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write16(0xe5d9);
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}
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void FDECSTP() { write16(0xf6d9); }
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void FRNDINT() { write16(0xfcd9); }
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void FXCH(int st) { write16(0xc8d9+(st<<8)); }
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void F2XM1() { write16(0xf0d9); }
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void FSCALE() { write16(0xfdd9); }
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/* fadd ST(src) to fpu reg stack ST(0) */
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void FADD32Rto0( x86IntRegType src )
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{
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write8( 0xD8 );
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write8( 0xC0 + src );
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}
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/* fadd ST(0) to fpu reg stack ST(src) */
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void FADD320toR( x86IntRegType src )
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{
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write8( 0xDC );
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write8( 0xC0 + src );
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}
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/* fsub ST(src) to fpu reg stack ST(0) */
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void FSUB32Rto0( x86IntRegType src )
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{
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write8( 0xD8 );
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write8( 0xE0 + src );
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}
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/* fsub ST(0) to fpu reg stack ST(src) */
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void FSUB320toR( x86IntRegType src )
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{
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write8( 0xDC );
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write8( 0xE8 + src );
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}
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/* fsubp -> substract ST(0) from ST(1), store in ST(1) and POP stack */
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void FSUBP( void )
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{
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write8( 0xDE );
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write8( 0xE9 );
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}
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/* fmul ST(src) to fpu reg stack ST(0) */
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void FMUL32Rto0( x86IntRegType src )
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{
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write8( 0xD8 );
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write8( 0xC8 + src );
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}
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/* fmul ST(0) to fpu reg stack ST(src) */
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void FMUL320toR( x86IntRegType src )
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{
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write8( 0xDC );
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write8( 0xC8 + src );
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}
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/* fdiv ST(src) to fpu reg stack ST(0) */
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void FDIV32Rto0( x86IntRegType src )
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{
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write8( 0xD8 );
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write8( 0xF0 + src );
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}
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/* fdiv ST(0) to fpu reg stack ST(src) */
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void FDIV320toR( x86IntRegType src )
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{
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write8( 0xDC );
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write8( 0xF8 + src );
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}
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void FDIV320toRP( x86IntRegType src )
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{
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write8( 0xDE );
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write8( 0xF8 + src );
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}
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/* fadd m32 to fpu reg stack */
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void FADD32( uptr from )
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{
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MEMADDR_OP(0, VAROP1(0xD8), false, 0, from, 0);
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}
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/* fsub m32 to fpu reg stack */
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void FSUB32( uptr from )
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{
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MEMADDR_OP(0, VAROP1(0xD8), false, 4, from, 0);
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}
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/* fmul m32 to fpu reg stack */
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void FMUL32( uptr from )
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{
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MEMADDR_OP(0, VAROP1(0xD8), false, 1, from, 0);
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}
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/* fdiv m32 to fpu reg stack */
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void FDIV32( uptr from )
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{
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MEMADDR_OP(0, VAROP1(0xD8), false, 6, from, 0);
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}
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/* fabs fpu reg stack */
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void FABS( void )
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{
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write16( 0xE1D9 );
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}
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/* fsqrt fpu reg stack */
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void FSQRT( void )
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{
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write16( 0xFAD9 );
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}
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void FPATAN(void) { write16(0xf3d9); }
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void FSIN(void) { write16(0xfed9); }
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/* fchs fpu reg stack */
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void FCHS( void )
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{
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write16( 0xE0D9 );
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}
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/* fcomi st, st(i) */
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void FCOMI( x86IntRegType src )
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{
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write8( 0xDB );
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write8( 0xF0 + src );
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}
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/* fcomip st, st(i) */
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void FCOMIP( x86IntRegType src )
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{
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write8( 0xDF );
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write8( 0xF0 + src );
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}
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/* fucomi st, st(i) */
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void FUCOMI( x86IntRegType src )
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{
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write8( 0xDB );
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write8( 0xE8 + src );
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}
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/* fucomip st, st(i) */
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void FUCOMIP( x86IntRegType src )
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{
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write8( 0xDF );
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write8( 0xE8 + src );
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}
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/* fcom m32 to fpu reg stack */
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void FCOM32( uptr from )
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{
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MEMADDR_OP(0, VAROP1(0xD8), false, 2, from, 0);
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}
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/* fcomp m32 to fpu reg stack */
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void FCOMP32( uptr from )
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{
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MEMADDR_OP(0, VAROP1(0xD8), false, 3, from, 0);
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}
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#define FCMOV32( low, high ) \
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{ \
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write8( low ); \
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write8( high + from ); \
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}
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void FCMOVB32( x86IntRegType from ) { FCMOV32( 0xDA, 0xC0 ); }
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void FCMOVE32( x86IntRegType from ) { FCMOV32( 0xDA, 0xC8 ); }
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void FCMOVBE32( x86IntRegType from ) { FCMOV32( 0xDA, 0xD0 ); }
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void FCMOVU32( x86IntRegType from ) { FCMOV32( 0xDA, 0xD8 ); }
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void FCMOVNB32( x86IntRegType from ) { FCMOV32( 0xDB, 0xC0 ); }
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void FCMOVNE32( x86IntRegType from ) { FCMOV32( 0xDB, 0xC8 ); }
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void FCMOVNBE32( x86IntRegType from ) { FCMOV32( 0xDB, 0xD0 ); }
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void FCMOVNU32( x86IntRegType from ) { FCMOV32( 0xDB, 0xD8 ); }
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#endif
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#endif
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