From 78e935a3e7ec856d50849b3e2a6df7949f56a634 Mon Sep 17 00:00:00 2001 From: "SND\\shalma_cp" Date: Sun, 5 Sep 2010 00:35:53 +0000 Subject: Rebel Assault 2 needs longer DMA times (black screens in-game) git-svn-id: https://pcsxr.svn.codeplex.com/svn/pcsxr@56821 e17a0e51-4ae3-4d35-97c3-1a29b211df97 --- libpcsxcore/mdec.c | 19 ++++++++++++++++--- libpcsxcore/psxdma.c | 24 ++++++++++++++++++++---- libpcsxcore/psxdma.h | 18 ++++++++++++++++++ libpcsxcore/r3000a.c | 28 +++++++++++++++++++++------- libpcsxcore/r3000a.h | 38 +++++++++++++++++++++----------------- 5 files changed, 96 insertions(+), 31 deletions(-) (limited to 'libpcsxcore') diff --git a/libpcsxcore/mdec.c b/libpcsxcore/mdec.c index f9b8d580..2ad12585 100644 --- a/libpcsxcore/mdec.c +++ b/libpcsxcore/mdec.c @@ -474,7 +474,10 @@ void psxDma0(u32 adr, u32 bcr, u32 chcr) { case 0x3: // decode mdec.rl = (u16 *)PSXM(adr); mdec.rlsize = mdec.reg0 & MDEC0_SIZE_MASK; - break; + + MDECINDMA_INT( size / 4 ); + return; + case 0x4: // quantization table upload { @@ -485,11 +488,15 @@ void psxDma0(u32 adr, u32 bcr, u32 chcr) { iqtab_init(iq_y, p); iqtab_init(iq_uv, p + 64); } - break; + + MDECINDMA_INT( size / 4 ); + return; case 0x6: // cosine table // printf("mdec cosine table\n"); - break; + + MDECINDMA_INT( size / 4 ); + return; default: // printf("mdec unknown command\n"); @@ -498,6 +505,12 @@ void psxDma0(u32 adr, u32 bcr, u32 chcr) { HW_DMA0_CHCR &= SWAP32(~0x01000000); DMA_INTERRUPT(0); +} + +void mdec0Interrupt() +{ + HW_DMA0_CHCR &= SWAP32(~0x01000000); + DMA_INTERRUPT(0); } void psxDma1(u32 adr, u32 bcr, u32 chcr) { diff --git a/libpcsxcore/psxdma.c b/libpcsxcore/psxdma.c index f59f268e..7b0cdd37 100644 --- a/libpcsxcore/psxdma.c +++ b/libpcsxcore/psxdma.c @@ -65,7 +65,9 @@ void psxDma4(u32 madr, u32 bcr, u32 chcr) { // SPU size = (bcr >> 16) * (bcr & 0xffff) * 2; SPU_readDMAMem(ptr, size); psxCpu->Clear(madr, size); - break; + + SPUDMA_INT((bcr >> 16) * (bcr & 0xffff) / 2); + return; #ifdef PSXDMA_LOG default: @@ -97,7 +99,9 @@ void psxDma2(u32 madr, u32 bcr, u32 chcr) { // GPU size = (bcr >> 16) * (bcr & 0xffff); GPU_readDataMem(ptr, size); psxCpu->Clear(madr, size); - break; + + GPUDMA_INT(size / 4); + return; case 0x01000201: // mem2vram #ifdef PSXDMA_LOG @@ -112,6 +116,7 @@ void psxDma2(u32 madr, u32 bcr, u32 chcr) { // GPU } size = (bcr >> 16) * (bcr & 0xffff); GPU_writeDataMem(ptr, size); + GPUDMA_INT(size / 4); return; @@ -120,7 +125,10 @@ void psxDma2(u32 madr, u32 bcr, u32 chcr) { // GPU PSXDMA_LOG("*** DMA 2 - GPU dma chain *** %x addr = %x size = %x\n", chcr, madr, bcr); #endif GPU_dmaChain((u32 *)psxM, madr & 0x1fffff); - break; + + // FIXME!!! Walk through DMA chain and add the cycles + GPUDMA_INT( 0x4000 / 4 ); + return; #ifdef PSXDMA_LOG default: @@ -160,6 +168,9 @@ void psxDma6(u32 madr, u32 bcr, u32 chcr) { madr -= 4; } mem++; *mem = 0xffffff; + + RAMDMA_INT( size / BIAS); + return; } #ifdef PSXDMA_LOG else { @@ -171,4 +182,9 @@ void psxDma6(u32 madr, u32 bcr, u32 chcr) { HW_DMA6_CHCR &= SWAP32(~0x01000000); DMA_INTERRUPT(6); } - + +void gpuotcInterrupt() +{ + HW_DMA6_CHCR &= SWAP32(~0x01000000); + DMA_INTERRUPT(6); +} diff --git a/libpcsxcore/psxdma.h b/libpcsxcore/psxdma.h index eb554334..326e5d42 100644 --- a/libpcsxcore/psxdma.h +++ b/libpcsxcore/psxdma.h @@ -47,12 +47,30 @@ extern "C" { psxRegs.intCycle[PSXINT_MDECOUTDMA].sCycle = psxRegs.cycle; \ } +#define MDECINDMA_INT(eCycle) { \ + psxRegs.interrupt |= (1 << PSXINT_MDECINDMA); \ + psxRegs.intCycle[PSXINT_MDECINDMA].cycle = eCycle; \ + psxRegs.intCycle[PSXINT_MDECINDMA].sCycle = psxRegs.cycle; \ +} + +#define GPUOTCDMA_INT(eCycle) { \ + psxRegs.interrupt |= (1 << PSXINT_GPUOTCDMA); \ + psxRegs.intCycle[PSXINT_GPUOTCDMA].cycle = eCycle; \ + psxRegs.intCycle[PSXINT_GPUOTCDMA].sCycle = psxRegs.cycle; \ +} + +/* +DMA5 = N/A (PIO) +*/ + void psxDma2(u32 madr, u32 bcr, u32 chcr); void psxDma3(u32 madr, u32 bcr, u32 chcr); void psxDma4(u32 madr, u32 bcr, u32 chcr); void psxDma6(u32 madr, u32 bcr, u32 chcr); void gpuInterrupt(); void spuInterrupt(); +void mdec0Interrupt(); +void gpuotcInterrupt(); #ifdef __cplusplus } diff --git a/libpcsxcore/r3000a.c b/libpcsxcore/r3000a.c index acc8eb60..550a17bb 100644 --- a/libpcsxcore/r3000a.c +++ b/libpcsxcore/r3000a.c @@ -114,7 +114,7 @@ void psxBranchTest() { if ((psxRegs.cycle - psxNextsCounter) >= psxNextCounter) psxRcntUpdate(); - if (psxRegs.interrupt) { + if (psxRegs.interrupt) { if ((psxRegs.interrupt & (1 << PSXINT_SIO)) && !Config.Sio) { // sio if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_SIO].sCycle) >= psxRegs.intCycle[PSXINT_SIO].cycle) { psxRegs.interrupt &= ~(1 << PSXINT_SIO); @@ -151,12 +151,26 @@ void psxBranchTest() { spuInterrupt(); } } - if (psxRegs.interrupt & (1 << PSXINT_GPUBUSY)) { // gpu busy - if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_GPUBUSY].sCycle) >= psxRegs.intCycle[PSXINT_GPUBUSY].cycle) { - psxRegs.interrupt &= ~(1 << PSXINT_GPUBUSY); - GPU_idle(); - } - } + if (psxRegs.interrupt & (1 << PSXINT_GPUBUSY)) { // gpu busy + if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_GPUBUSY].sCycle) >= psxRegs.intCycle[PSXINT_GPUBUSY].cycle) { + psxRegs.interrupt &= ~(1 << PSXINT_GPUBUSY); + GPU_idle(); + } + } + + if (psxRegs.interrupt & (1 << PSXINT_MDECINDMA)) { // mdec in + if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_MDECINDMA].sCycle) >= psxRegs.intCycle[PSXINT_MDECINDMA].cycle) { + psxRegs.interrupt &= ~(1 << PSXINT_MDECINDMA); + mdec0Interrupt(); + } + } + + if (psxRegs.interrupt & (1 << PSXINT_GPUOTCDMA)) { // gpu otc + if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_GPUOTCDMA].sCycle) >= psxRegs.intCycle[PSXINT_GPUOTCDMA].cycle) { + psxRegs.interrupt &= ~(1 << PSXINT_GPUOTCDMA); + gpuotcInterrupt(); + } + } } if (psxHu32(0x1070) & psxHu32(0x1074)) { diff --git a/libpcsxcore/r3000a.h b/libpcsxcore/r3000a.h index 0150b0e6..f0b4e369 100644 --- a/libpcsxcore/r3000a.h +++ b/libpcsxcore/r3000a.h @@ -70,20 +70,19 @@ typedef union { PAIR p[34]; } psxGPRRegs; -typedef union { - struct { - u32 Index, Random, EntryLo0, EntryLo1, - Context, PageMask, Wired, Reserved0, - BadVAddr, Count, EntryHi, Compare, - Status, Cause, EPC, PRid, - Config, LLAddr, WatchLO, WatchHI, - XContext, Reserved1, Reserved2, Reserved3, - Reserved4, Reserved5, ECC, CacheErr, - TagLo, TagHi, ErrorEPC, Reserved6; - } n; - u32 r[32]; - PAIR p[32]; -} psxCP0Regs; +typedef union { + struct { + u32 Index, Random, EntryLo0, BPC, + Context, BDA, PIDMask, DCIC, + BadVAddr, BDAM, EntryHi, BPCM, + Status, Cause, EPC, PRid, + Config, LLAddr, WatchLO, WatchHI, + XContext, Reserved1, Reserved2, Reserved3, + Reserved4, Reserved5, ECC, CacheErr, + TagLo, TagHi, ErrorEPC, Reserved6; + } n; + u32 r[32]; +} psxCP0Regs; typedef struct { short x, y; @@ -152,7 +151,9 @@ enum { PSXINT_GPUDMA, PSXINT_MDECOUTDMA, PSXINT_SPUDMA, - PSXINT_GPUBUSY + PSXINT_GPUBUSY, + PSXINT_MDECINDMA, + PSXINT_GPUOTCDMA }; typedef struct { @@ -160,11 +161,14 @@ typedef struct { psxCP0Regs CP0; /* Coprocessor0 Registers */ psxCP2Data CP2D; /* Cop2 data registers */ psxCP2Ctrl CP2C; /* Cop2 control registers */ - u32 pc; /* Program counter */ - u32 code; /* The instruction */ + u32 pc; /* Program counter */ + u32 code; /* The instruction */ u32 cycle; u32 interrupt; struct { u32 sCycle, cycle; } intCycle[32]; + u8 ICache_Addr[0x1000]; + u8 ICache_Code[0x1000]; + u32 ICache_valid; } psxRegisters; extern psxRegisters psxRegs; -- cgit v1.2.3