From aecaf18a950fc708823780f2e59303ad63f4e3bd Mon Sep 17 00:00:00 2001 From: Xavi Del Campo Date: Thu, 23 Apr 2020 23:02:27 +0200 Subject: [PATCH] Added dynstr, fixed NULL pointer access --- .gitmodules | 3 +++ dynstr/dynstr | 1 + libpcsxcore/pgxp_cpu.c | 36 ++++++++++++++++++------------------ plugins/peopsxgl/pgxp_gpu.c | 17 +++++++++++------ 4 files changed, 33 insertions(+), 24 deletions(-) create mode 100644 .gitmodules create mode 160000 dynstr/dynstr diff --git a/.gitmodules b/.gitmodules new file mode 100644 index 00000000..a178facc --- /dev/null +++ b/.gitmodules @@ -0,0 +1,3 @@ +[submodule "dynstr/dynstr"] + path = dynstr/dynstr + url = https://github.com/XaviDCR92/dynstr diff --git a/dynstr/dynstr b/dynstr/dynstr new file mode 160000 index 00000000..357d4f2c --- /dev/null +++ b/dynstr/dynstr @@ -0,0 +1 @@ +Subproject commit 357d4f2c0fc52ae7e5967f542161d59d09830e27 diff --git a/libpcsxcore/pgxp_cpu.c b/libpcsxcore/pgxp_cpu.c index 2b36da57..7f84f9a2 100644 --- a/libpcsxcore/pgxp_cpu.c +++ b/libpcsxcore/pgxp_cpu.c @@ -14,12 +14,12 @@ PGXP_value* CPU_reg = CPU_reg_mem; PGXP_value* CP0_reg = CP0_reg_mem; // Instruction register decoding -#define op(_instr) (_instr >> 26) // The op part of the instruction register -#define func(_instr) ((_instr) & 0x3F) // The funct part of the instruction register +#define op(_instr) (_instr >> 26) // The op part of the instruction register +#define func(_instr) ((_instr) & 0x3F) // The funct part of the instruction register #define sa(_instr) ((_instr >> 6) & 0x1F) // The sa part of the instruction register -#define rd(_instr) ((_instr >> 11) & 0x1F) // The rd part of the instruction register -#define rt(_instr) ((_instr >> 16) & 0x1F) // The rt part of the instruction register -#define rs(_instr) ((_instr >> 21) & 0x1F) // The rs part of the instruction register +#define rd(_instr) ((_instr >> 11) & 0x1F) // The rd part of the instruction register +#define rt(_instr) ((_instr >> 16) & 0x1F) // The rt part of the instruction register +#define rs(_instr) ((_instr >> 21) & 0x1F) // The rs part of the instruction register #define imm(_instr) (_instr & 0xFFFF) // The immediate part of the instruction register void PGXP_InitCPU() @@ -31,7 +31,7 @@ void PGXP_InitCPU() // invalidate register (invalid 8 bit read) void InvalidLoad(u32 addr, u32 code, u32 value) { - u32 reg = ((code >> 16) & 0x1F); // The rt part of the instruction register + u32 reg = ((code >> 16) & 0x1F); // The rt part of the instruction register PGXP_value* pD = NULL; PGXP_value p; @@ -60,7 +60,7 @@ void InvalidLoad(u32 addr, u32 code, u32 value) // invalidate memory address (invalid 8 bit write) void InvalidStore(u32 addr, u32 code, u32 value) { - u32 reg = ((code >> 16) & 0x1F); // The rt part of the instruction register + u32 reg = ((code >> 16) & 0x1F); // The rt part of the instruction register PGXP_value* pD = NULL; PGXP_value p; @@ -86,7 +86,7 @@ void PGXP_CPU_ADDI(u32 instr, u32 rtVal, u32 rsVal) // Rt = Rs + Imm (signed) psx_value tempImm; PGXP_value ret; - + Validate(&CPU_reg[rs(instr)], rsVal); ret = CPU_reg[rs(instr)]; tempImm.d = imm(instr); @@ -674,11 +674,11 @@ void PGXP_CPU_SLL(u32 instr, u32 rdVal, u32 rtVal) PGXP_value ret; u32 sh = sa(instr); Validate(&CPU_reg[rt(instr)], rtVal); - + ret = CPU_reg[rt(instr)]; // TODO: Shift flags -#if 1 +#if 1 double x = f16Unsign(CPU_reg[rt(instr)].x); double y = f16Unsign(CPU_reg[rt(instr)].y); if (sh >= 32) @@ -797,7 +797,7 @@ void PGXP_CPU_SRL(u32 instr, u32 rdVal, u32 rtVal) else if ((valt.w.h & mask) == 0) x = x; else - x += y * (1 << (16 - sh));//f16Overflow(y); + x += y * (1 << (16 - sh));//f16Overflow(y); y = y / (1 << sh); x = f16Sign(x); @@ -882,7 +882,7 @@ void PGXP_CPU_SRA(u32 instr, u32 rdVal, u32 rtVal) else { x = x / (1 << sh); - + // check for potential sign extension in overflow psx_value valt; valt.d = rtVal; @@ -892,7 +892,7 @@ void PGXP_CPU_SRA(u32 instr, u32 rdVal, u32 rtVal) else if ((valt.w.h & mask) == 0) x = x; else - x += y * (1 << (16 - sh));//f16Overflow(y); + x += y * (1 << (16 - sh));//f16Overflow(y); y = y / (1 << sh); x = f16Sign(x); @@ -1076,7 +1076,7 @@ void PGXP_CPU_SRLV(u32 instr, u32 rdVal, u32 rtVal, u32 rsVal) else { x = x / (1 << sh); - + // check for potential sign extension in overflow psx_value valt; valt.d = rtVal; @@ -1086,7 +1086,7 @@ void PGXP_CPU_SRLV(u32 instr, u32 rdVal, u32 rtVal, u32 rsVal) else if ((valt.w.h & mask) == 0) x = x; else - x += y * (1 << (16 - sh));//f16Overflow(y); + x += y * (1 << (16 - sh));//f16Overflow(y); y = y / (1 << sh); x = f16Sign(x); @@ -1173,7 +1173,7 @@ void PGXP_CPU_SRAV(u32 instr, u32 rdVal, u32 rtVal, u32 rsVal) else { x = x / (1 << sh); - + // check for potential sign extension in overflow psx_value valt; valt.d = rtVal; @@ -1183,7 +1183,7 @@ void PGXP_CPU_SRAV(u32 instr, u32 rdVal, u32 rtVal, u32 rsVal) else if ((valt.w.h & mask) == 0) x = x; else - x += y * (1 << (16 - sh));//f16Overflow(y); + x += y * (1 << (16 - sh));//f16Overflow(y); y = y / (1 << sh); x = f16Sign(x); @@ -1402,4 +1402,4 @@ void PGXP_CP0_CTC0(u32 instr, u32 rdVal, u32 rtVal) } void PGXP_CP0_RFE(u32 instr) -{} \ No newline at end of file +{} diff --git a/plugins/peopsxgl/pgxp_gpu.c b/plugins/peopsxgl/pgxp_gpu.c index 184c7452..afb6cf31 100644 --- a/plugins/peopsxgl/pgxp_gpu.c +++ b/plugins/peopsxgl/pgxp_gpu.c @@ -160,7 +160,7 @@ void CALLBACK GPUpgxpCacheVertex(short sx, short sy, const unsigned char* _pVert if ((fabsf(pOldVertex->x - pNewVertex->x) > 0.1f) || (fabsf(pOldVertex->y - pNewVertex->y) > 0.1f) || (fabsf(pOldVertex->z - pNewVertex->z) > 0.1f)) - { + { pOldVertex->mFlags = 5; return; } @@ -390,6 +390,11 @@ int PGXP_GetVertices(unsigned int* addr, void* pOutput, int xOffs, int yOffs) // calculate offset to actual data int offset = 0; + + /* Dirty hack */ + if (!pDMABlock) + return 0; + while ((pDMABlock[offset] != *addr) && (offset < blockSize)) { unsigned char command = (unsigned char)((pDMABlock[offset] >> 24) & 0xff); @@ -455,7 +460,7 @@ int PGXP_GetVertices(unsigned int* addr, void* pOutput, int xOffs, int yOffs) } // Log incorrect vertices - //if (PGXP_tDebug && + //if (PGXP_tDebug && // (fabs((float)pPrimData[stride * i * 2] - primStart[stride * i].x) > debug_tolerance) || // (fabs((float)pPrimData[(stride * i * 2) + 1] - primStart[stride * i].y) > debug_tolerance)) // __Log("GPPV: v:%x (%d, %d) pgxp(%f, %f)|\n", (currentAddr + offset + 1 + (i * stride)) * 4, pPrimData[stride * i * 2], pPrimData[(stride * i * 2) + 1], primStart[stride * i].x, primStart[stride * i].y); @@ -527,7 +532,7 @@ enum PGXP_vDebugMode vDEBUG_MAX, vDEBUG_TEXCOORD, - vDEBUG_ID, + vDEBUG_ID, }; const char red[4] = { 255, 0, 0, 255 }; @@ -569,7 +574,7 @@ void ColourFromRange(float val, float min, float max, GLubyte alpha, int wrap) if (wrap) val = fmod(val, 1); - if (0 <= val && val<= 1.f / 8.f) + if (0 <= val && val<= 1.f / 8.f) { r = 0; g = 0; @@ -672,7 +677,7 @@ void PGXP_colour(OGLVertex* vertex, GLubyte alpha, int prim, int isTextured, int glColor4ubv(vertex->c.col); break; } - + break; case vDEBUG_TEXTURE: // Texture only @@ -830,4 +835,4 @@ int PGXP_DrawDebugQuad(OGLVertex* vertex1, OGLVertex* vertex2, OGLVertex* vertex int PGXP_DrawDebugTriQuad(OGLVertex* vertex1, OGLVertex* vertex2, OGLVertex* vertex3, OGLVertex* vertex4, int colourMode, int isTextured) { return DrawDebugPrim(DRAW_TRIQUAD, vertex1, vertex2, vertex3, vertex4, colourMode, isTextured); -} \ No newline at end of file +}