Change shift count overflow to be masking.

2 files changed, 25 insertions, 4 deletions

diff --git a/AstSemantics.md b/AstSemantics.md
index 7cd58ee..9aabf87 100644
--- a/AstSemantics.md
+++ b/AstSemantics.md
@@ -383,10 +383,10 @@ results into the result type.
   * `i32.ctz`: sign-agnostic count trailing zero bits (All zero bits are considered trailing if the value is zero)
   * `i32.popcnt`: sign-agnostic count number of one bits
 
-Shifts interpret their shift count operand as an unsigned value. When the shift
-count is at least the bitwidth of the shift, `shl` and `shr_u` produce `0`, and
-`shr_s` produces `0` if the value being shifted is non-negative, and `-1`
-otherwise.
+Shifts counts are wrapped to be less than the log-base-2 of the number of bits
+in the value to be shifted, as an unsigned quantity. For example, in a 32-bit
+shift, only the least 5 significant bits of the count affect the result. In a
+64-bit shift, only the least 6 significant bits of the count affect the result.
 
 All comparison operators yield 32-bit integer results with `1` representing
 `true` and `0` representing `false`.
diff --git a/Rationale.md b/Rationale.md
index d99cda4..7aab354 100644
--- a/Rationale.md
+++ b/Rationale.md
@@ -292,6 +292,27 @@ However, since the publication of IEEE 754-2008, MIPS has added a configuration
 mode (NAN2008) which enables support for the new rules.
 
 
+## Integer operations
+
+WebAssembly's signed integer divide rounds its result toward zero. This is not
+because of a lack of sympathy for
+[better alternatives](https://python-history.blogspot.com/2010/08/why-pythons-integer-division-floors.html),
+but out of practicality. Because all popular hardware today implements
+rounding toward zero, and because C and many other languages now specify
+rounding to zero, having WebAssembly in the middle doing something different
+would mean divisions would have to be doubly complicated.
+
+Similarly, WebAssembly's shift operators mask their shift counts to the number
+of bits in the shifted value. Confusingly, this means that shifting a 32-bit
+value by 32 bits is an identity operation, and that a left shift is not
+equivalent to a multiplication by a power of 2 because the overflow behavior
+is different. Nevertheless, because several popular hardware architectures
+today implement this masking behavior, and those that don't can typically
+emulate it with a single extra mask instruction, and because several popular
+source languages, including JavaScript, have come to specify this behavior
+too, we reluctantly adopt this behavior as well.
+
+
 ## Motivating Scenarios for Feature Testing
 
 1. [Post-MVP](PostMVP.md),